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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* kirkwood-i2s.c
*
* (c) 2010 Arnaud Patard <[email protected]>
* (c) 2010 Arnaud Patard <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/platform_data/asoc-kirkwood.h>
#include <linux/of.h>
#include "kirkwood.h"
#define KIRKWOOD_I2S_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define KIRKWOOD_SPDIF_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* These registers are relative to the second register region -
* audio pll configuration.
*/
#define A38X_PLL_CONF_REG0 0x0
#define A38X_PLL_FB_CLK_DIV_OFFSET 10
#define A38X_PLL_FB_CLK_DIV_MASK 0x7fc00
#define A38X_PLL_CONF_REG1 0x4
#define A38X_PLL_FREQ_OFFSET_MASK 0xffff
#define A38X_PLL_FREQ_OFFSET_VALID BIT(16)
#define A38X_PLL_SW_RESET BIT(31)
#define A38X_PLL_CONF_REG2 0x8
#define A38X_PLL_AUDIO_POSTDIV_MASK 0x7f
/* Bit below belongs to SoC control register corresponding to the third
* register region.
*/
#define A38X_SPDIF_MODE_ENABLE BIT(27)
static int armada_38x_i2s_init_quirk(struct platform_device *pdev,
struct kirkwood_dma_data *priv,
struct snd_soc_dai_driver *dai_drv)
{
struct device_node *np = pdev->dev.of_node;
u32 reg_val;
int i;
priv->pll_config = devm_platform_ioremap_resource_byname(pdev, "pll_regs");
if (IS_ERR(priv->pll_config))
return -ENOMEM;
priv->soc_control = devm_platform_ioremap_resource_byname(pdev, "soc_ctrl");
if (IS_ERR(priv->soc_control))
return -ENOMEM;
/* Select one of exceptive modes: I2S or S/PDIF */
reg_val = readl(priv->soc_control);
if (of_property_read_bool(np, "spdif-mode")) {
reg_val |= A38X_SPDIF_MODE_ENABLE;
dev_info(&pdev->dev, "using S/PDIF mode\n");
} else {
reg_val &= ~A38X_SPDIF_MODE_ENABLE;
dev_info(&pdev->dev, "using I2S mode\n");
}
writel(reg_val, priv->soc_control);
/* Update available rates of mclk's fs */
for (i = 0; i < 2; i++) {
dai_drv[i].playback.rates |= SNDRV_PCM_RATE_192000;
dai_drv[i].capture.rates |= SNDRV_PCM_RATE_192000;
}
return 0;
}
static inline void armada_38x_set_pll(void __iomem *base, unsigned long rate)
{
u32 reg_val;
u16 freq_offset = 0x22b0;
u8 audio_postdiv, fb_clk_div = 0x1d;
/* Set frequency offset value to not valid and enable PLL reset */
reg_val = readl(base + A38X_PLL_CONF_REG1);
reg_val &= ~A38X_PLL_FREQ_OFFSET_VALID;
reg_val &= ~A38X_PLL_SW_RESET;
writel(reg_val, base + A38X_PLL_CONF_REG1);
udelay(1);
/* Update PLL parameters */
switch (rate) {
default:
case 44100:
freq_offset = 0x735;
fb_clk_div = 0x1b;
audio_postdiv = 0xc;
break;
case 48000:
audio_postdiv = 0xc;
break;
case 96000:
audio_postdiv = 0x6;
break;
case 192000:
audio_postdiv = 0x3;
break;
}
reg_val = readl(base + A38X_PLL_CONF_REG0);
reg_val &= ~A38X_PLL_FB_CLK_DIV_MASK;
reg_val |= (fb_clk_div << A38X_PLL_FB_CLK_DIV_OFFSET);
writel(reg_val, base + A38X_PLL_CONF_REG0);
reg_val = readl(base + A38X_PLL_CONF_REG2);
reg_val &= ~A38X_PLL_AUDIO_POSTDIV_MASK;
reg_val |= audio_postdiv;
writel(reg_val, base + A38X_PLL_CONF_REG2);
reg_val = readl(base + A38X_PLL_CONF_REG1);
reg_val &= ~A38X_PLL_FREQ_OFFSET_MASK;
reg_val |= freq_offset;
writel(reg_val, base + A38X_PLL_CONF_REG1);
udelay(1);
/* Disable reset */
reg_val |= A38X_PLL_SW_RESET;
writel(reg_val, base + A38X_PLL_CONF_REG1);
/* Wait 50us for PLL to lock */
udelay(50);
/* Restore frequency offset value validity */
reg_val |= A38X_PLL_FREQ_OFFSET_VALID;
writel(reg_val, base + A38X_PLL_CONF_REG1);
}
static int kirkwood_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct kirkwood_dma_data *priv = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long mask;
unsigned long value;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
mask = KIRKWOOD_I2S_CTL_RJ;
break;
case SND_SOC_DAIFMT_LEFT_J:
mask = KIRKWOOD_I2S_CTL_LJ;
break;
case SND_SOC_DAIFMT_I2S:
mask = KIRKWOOD_I2S_CTL_I2S;
break;
default:
return -EINVAL;
}
/*
* Set same format for playback and record
* This avoids some troubles.
*/
value = readl(priv->io+KIRKWOOD_I2S_PLAYCTL);
value &= ~KIRKWOOD_I2S_CTL_JUST_MASK;
value |= mask;
writel(value, priv->io+KIRKWOOD_I2S_PLAYCTL);
value = readl(priv->io+KIRKWOOD_I2S_RECCTL);
value &= ~KIRKWOOD_I2S_CTL_JUST_MASK;
value |= mask;
writel(value, priv->io+KIRKWOOD_I2S_RECCTL);
return 0;
}
static inline void kirkwood_set_dco(void __iomem *io, unsigned long rate)
{
unsigned long value;
value = KIRKWOOD_DCO_CTL_OFFSET_0;
switch (rate) {
default:
case 44100:
value |= KIRKWOOD_DCO_CTL_FREQ_11;
break;
case 48000:
value |= KIRKWOOD_DCO_CTL_FREQ_12;
break;
case 96000:
value |= KIRKWOOD_DCO_CTL_FREQ_24;
break;
}
writel(value, io + KIRKWOOD_DCO_CTL);
/* wait for dco locked */
do {
cpu_relax();
value = readl(io + KIRKWOOD_DCO_SPCR_STATUS);
value &= KIRKWOOD_DCO_SPCR_STATUS_DCO_LOCK;
} while (value == 0);
}
static void kirkwood_set_rate(struct snd_soc_dai *dai,
struct kirkwood_dma_data *priv, unsigned long rate)
{
uint32_t clks_ctrl;
if (IS_ERR(priv->extclk)) {
/* use internal dco for the supported rates
* defined in kirkwood_i2s_dai */
dev_dbg(dai->dev, "%s: dco set rate = %lu\n",
__func__, rate);
if (priv->pll_config)
armada_38x_set_pll(priv->pll_config, rate);
else
kirkwood_set_dco(priv->io, rate);
clks_ctrl = KIRKWOOD_MCLK_SOURCE_DCO;
} else {
/* use the external clock for the other rates
* defined in kirkwood_i2s_dai_extclk */
dev_dbg(dai->dev, "%s: extclk set rate = %lu -> %lu\n",
__func__, rate, 256 * rate);
clk_set_rate(priv->extclk, 256 * rate);
clks_ctrl = KIRKWOOD_MCLK_SOURCE_EXTCLK;
}
writel(clks_ctrl, priv->io + KIRKWOOD_CLOCKS_CTRL);
}
static int kirkwood_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct kirkwood_dma_data *priv = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_set_dma_data(dai, substream, priv);
return 0;
}
static int kirkwood_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct kirkwood_dma_data *priv = snd_soc_dai_get_drvdata(dai);
uint32_t ctl_play, ctl_rec;
unsigned int i2s_reg;
unsigned long i2s_value;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
i2s_reg = KIRKWOOD_I2S_PLAYCTL;
} else {
i2s_reg = KIRKWOOD_I2S_RECCTL;
}
kirkwood_set_rate(dai, priv, params_rate(params));
i2s_value = readl(priv->io+i2s_reg);
i2s_value &= ~KIRKWOOD_I2S_CTL_SIZE_MASK;
/*
* Size settings in play/rec i2s control regs and play/rec control
* regs must be the same.
*/
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
i2s_value |= KIRKWOOD_I2S_CTL_SIZE_16;
ctl_play = KIRKWOOD_PLAYCTL_SIZE_16_C |
KIRKWOOD_PLAYCTL_I2S_EN |
KIRKWOOD_PLAYCTL_SPDIF_EN;
ctl_rec = KIRKWOOD_RECCTL_SIZE_16_C |
KIRKWOOD_RECCTL_I2S_EN |
KIRKWOOD_RECCTL_SPDIF_EN;
break;
/*
* doesn't work... S20_3LE != kirkwood 20bit format ?
*
case SNDRV_PCM_FORMAT_S20_3LE:
i2s_value |= KIRKWOOD_I2S_CTL_SIZE_20;
ctl_play = KIRKWOOD_PLAYCTL_SIZE_20 |
KIRKWOOD_PLAYCTL_I2S_EN;
ctl_rec = KIRKWOOD_RECCTL_SIZE_20 |
KIRKWOOD_RECCTL_I2S_EN;
break;
*/
case SNDRV_PCM_FORMAT_S24_LE:
i2s_value |= KIRKWOOD_I2S_CTL_SIZE_24;
ctl_play = KIRKWOOD_PLAYCTL_SIZE_24 |
KIRKWOOD_PLAYCTL_I2S_EN |
KIRKWOOD_PLAYCTL_SPDIF_EN;
ctl_rec = KIRKWOOD_RECCTL_SIZE_24 |
KIRKWOOD_RECCTL_I2S_EN |
KIRKWOOD_RECCTL_SPDIF_EN;
break;
case SNDRV_PCM_FORMAT_S32_LE:
i2s_value |= KIRKWOOD_I2S_CTL_SIZE_32;
ctl_play = KIRKWOOD_PLAYCTL_SIZE_32 |
KIRKWOOD_PLAYCTL_I2S_EN;
ctl_rec = KIRKWOOD_RECCTL_SIZE_32 |
KIRKWOOD_RECCTL_I2S_EN;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (params_channels(params) == 1)
ctl_play |= KIRKWOOD_PLAYCTL_MONO_BOTH;
else
ctl_play |= KIRKWOOD_PLAYCTL_MONO_OFF;
priv->ctl_play &= ~(KIRKWOOD_PLAYCTL_MONO_MASK |
KIRKWOOD_PLAYCTL_ENABLE_MASK |
KIRKWOOD_PLAYCTL_SIZE_MASK);
priv->ctl_play |= ctl_play;
} else {
priv->ctl_rec &= ~(KIRKWOOD_RECCTL_ENABLE_MASK |
KIRKWOOD_RECCTL_SIZE_MASK);
priv->ctl_rec |= ctl_rec;
}
writel(i2s_value, priv->io+i2s_reg);
return 0;
}
static unsigned kirkwood_i2s_play_mute(unsigned ctl)
{
if (!(ctl & KIRKWOOD_PLAYCTL_I2S_EN))
ctl |= KIRKWOOD_PLAYCTL_I2S_MUTE;
if (!(ctl & KIRKWOOD_PLAYCTL_SPDIF_EN))
ctl |= KIRKWOOD_PLAYCTL_SPDIF_MUTE;
return ctl;
}
static int kirkwood_i2s_play_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct kirkwood_dma_data *priv = snd_soc_dai_get_drvdata(dai);
uint32_t ctl, value;
ctl = readl(priv->io + KIRKWOOD_PLAYCTL);
if ((ctl & KIRKWOOD_PLAYCTL_ENABLE_MASK) == 0) {
unsigned timeout = 5000;
/*
* The Armada510 spec says that if we enter pause mode, the
* busy bit must be read back as clear _twice_. Make sure
* we respect that otherwise we get DMA underruns.
*/
do {
value = ctl;
ctl = readl(priv->io + KIRKWOOD_PLAYCTL);
if (!((ctl | value) & KIRKWOOD_PLAYCTL_PLAY_BUSY))
break;
udelay(1);
} while (timeout--);
if ((ctl | value) & KIRKWOOD_PLAYCTL_PLAY_BUSY)
dev_notice(dai->dev, "timed out waiting for busy to deassert: %08x\n",
ctl);
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
/* configure */
ctl = priv->ctl_play;
if (dai->id == 0)
ctl &= ~KIRKWOOD_PLAYCTL_SPDIF_EN; /* i2s */
else
ctl &= ~KIRKWOOD_PLAYCTL_I2S_EN; /* spdif */
ctl = kirkwood_i2s_play_mute(ctl);
value = ctl & ~KIRKWOOD_PLAYCTL_ENABLE_MASK;
writel(value, priv->io + KIRKWOOD_PLAYCTL);
/* enable interrupts */
if (!runtime->no_period_wakeup) {
value = readl(priv->io + KIRKWOOD_INT_MASK);
value |= KIRKWOOD_INT_CAUSE_PLAY_BYTES;
writel(value, priv->io + KIRKWOOD_INT_MASK);
}
/* enable playback */
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
break;
case SNDRV_PCM_TRIGGER_STOP:
/* stop audio, disable interrupts */
ctl |= KIRKWOOD_PLAYCTL_PAUSE | KIRKWOOD_PLAYCTL_I2S_MUTE |
KIRKWOOD_PLAYCTL_SPDIF_MUTE;
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
value = readl(priv->io + KIRKWOOD_INT_MASK);
value &= ~KIRKWOOD_INT_CAUSE_PLAY_BYTES;
writel(value, priv->io + KIRKWOOD_INT_MASK);
/* disable all playbacks */
ctl &= ~KIRKWOOD_PLAYCTL_ENABLE_MASK;
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
ctl |= KIRKWOOD_PLAYCTL_PAUSE | KIRKWOOD_PLAYCTL_I2S_MUTE |
KIRKWOOD_PLAYCTL_SPDIF_MUTE;
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
break;
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ctl &= ~(KIRKWOOD_PLAYCTL_PAUSE | KIRKWOOD_PLAYCTL_I2S_MUTE |
KIRKWOOD_PLAYCTL_SPDIF_MUTE);
ctl = kirkwood_i2s_play_mute(ctl);
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
break;
default:
return -EINVAL;
}
return 0;
}
static int kirkwood_i2s_rec_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct kirkwood_dma_data *priv = snd_soc_dai_get_drvdata(dai);
uint32_t ctl, value;
value = readl(priv->io + KIRKWOOD_RECCTL);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
/* configure */
ctl = priv->ctl_rec;
if (dai->id == 0)
ctl &= ~KIRKWOOD_RECCTL_SPDIF_EN; /* i2s */
else
ctl &= ~KIRKWOOD_RECCTL_I2S_EN; /* spdif */
value = ctl & ~KIRKWOOD_RECCTL_ENABLE_MASK;
writel(value, priv->io + KIRKWOOD_RECCTL);
/* enable interrupts */
value = readl(priv->io + KIRKWOOD_INT_MASK);
value |= KIRKWOOD_INT_CAUSE_REC_BYTES;
writel(value, priv->io + KIRKWOOD_INT_MASK);
/* enable record */
writel(ctl, priv->io + KIRKWOOD_RECCTL);
break;
case SNDRV_PCM_TRIGGER_STOP:
/* stop audio, disable interrupts */
value = readl(priv->io + KIRKWOOD_RECCTL);
value |= KIRKWOOD_RECCTL_PAUSE | KIRKWOOD_RECCTL_MUTE;
writel(value, priv->io + KIRKWOOD_RECCTL);
value = readl(priv->io + KIRKWOOD_INT_MASK);
value &= ~KIRKWOOD_INT_CAUSE_REC_BYTES;
writel(value, priv->io + KIRKWOOD_INT_MASK);
/* disable all records */
value = readl(priv->io + KIRKWOOD_RECCTL);
value &= ~KIRKWOOD_RECCTL_ENABLE_MASK;
writel(value, priv->io + KIRKWOOD_RECCTL);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
value = readl(priv->io + KIRKWOOD_RECCTL);
value |= KIRKWOOD_RECCTL_PAUSE | KIRKWOOD_RECCTL_MUTE;
writel(value, priv->io + KIRKWOOD_RECCTL);
break;
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
value = readl(priv->io + KIRKWOOD_RECCTL);
value &= ~(KIRKWOOD_RECCTL_PAUSE | KIRKWOOD_RECCTL_MUTE);
writel(value, priv->io + KIRKWOOD_RECCTL);
break;
default:
return -EINVAL;
}
return 0;
}
static int kirkwood_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return kirkwood_i2s_play_trigger(substream, cmd, dai);
else
return kirkwood_i2s_rec_trigger(substream, cmd, dai);
return 0;
}
static int kirkwood_i2s_init(struct kirkwood_dma_data *priv)
{
unsigned long value;
unsigned int reg_data;
/* put system in a "safe" state : */
/* disable audio interrupts */
writel(0xffffffff, priv->io + KIRKWOOD_INT_CAUSE);
writel(0, priv->io + KIRKWOOD_INT_MASK);
reg_data = readl(priv->io + 0x1200);
reg_data &= (~(0x333FF8));
reg_data |= 0x111D18;
writel(reg_data, priv->io + 0x1200);
msleep(500);
reg_data = readl(priv->io + 0x1200);
reg_data &= (~(0x333FF8));
reg_data |= 0x111D18;
writel(reg_data, priv->io + 0x1200);
/* disable playback/record */
value = readl(priv->io + KIRKWOOD_PLAYCTL);
value &= ~KIRKWOOD_PLAYCTL_ENABLE_MASK;
writel(value, priv->io + KIRKWOOD_PLAYCTL);
value = readl(priv->io + KIRKWOOD_RECCTL);
value &= ~KIRKWOOD_RECCTL_ENABLE_MASK;
writel(value, priv->io + KIRKWOOD_RECCTL);
return 0;
}
static const struct snd_soc_dai_ops kirkwood_i2s_dai_ops = {
.startup = kirkwood_i2s_startup,
.trigger = kirkwood_i2s_trigger,
.hw_params = kirkwood_i2s_hw_params,
.set_fmt = kirkwood_i2s_set_fmt,
};
static struct snd_soc_dai_driver kirkwood_i2s_dai[2] = {
{
.name = "i2s",
.id = 0,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.formats = KIRKWOOD_I2S_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.formats = KIRKWOOD_I2S_FORMATS,
},
.ops = &kirkwood_i2s_dai_ops,
},
{
.name = "spdif",
.id = 1,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.formats = KIRKWOOD_SPDIF_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.formats = KIRKWOOD_SPDIF_FORMATS,
},
.ops = &kirkwood_i2s_dai_ops,
},
};
static struct snd_soc_dai_driver kirkwood_i2s_dai_extclk[2] = {
{
.name = "i2s",
.id = 0,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 192000,
.formats = KIRKWOOD_I2S_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 192000,
.formats = KIRKWOOD_I2S_FORMATS,
},
.ops = &kirkwood_i2s_dai_ops,
},
{
.name = "spdif",
.id = 1,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 192000,
.formats = KIRKWOOD_SPDIF_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 192000,
.formats = KIRKWOOD_SPDIF_FORMATS,
},
.ops = &kirkwood_i2s_dai_ops,
},
};
static int kirkwood_i2s_dev_probe(struct platform_device *pdev)
{
struct kirkwood_asoc_platform_data *data = pdev->dev.platform_data;
struct snd_soc_dai_driver *soc_dai = kirkwood_i2s_dai;
struct kirkwood_dma_data *priv;
struct device_node *np = pdev->dev.of_node;
int err;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, priv);
if (of_device_is_compatible(np, "marvell,armada-380-audio"))
priv->io = devm_platform_ioremap_resource_byname(pdev, "i2s_regs");
else
priv->io = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->io))
return PTR_ERR(priv->io);
priv->irq = platform_get_irq(pdev, 0);
if (priv->irq < 0)
return priv->irq;
if (of_device_is_compatible(np, "marvell,armada-380-audio")) {
err = armada_38x_i2s_init_quirk(pdev, priv, soc_dai);
if (err < 0)
return err;
/* Set initial pll frequency */
armada_38x_set_pll(priv->pll_config, 44100);
}
if (np) {
priv->burst = 128; /* might be 32 or 128 */
} else if (data) {
priv->burst = data->burst;
} else {
dev_err(&pdev->dev, "no DT nor platform data ?!\n");
return -EINVAL;
}
priv->clk = devm_clk_get(&pdev->dev, np ? "internal" : NULL);
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "no clock\n");
return PTR_ERR(priv->clk);
}
priv->extclk = devm_clk_get(&pdev->dev, "extclk");
if (IS_ERR(priv->extclk)) {
if (PTR_ERR(priv->extclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
} else {
if (clk_is_match(priv->extclk, priv->clk)) {
devm_clk_put(&pdev->dev, priv->extclk);
priv->extclk = ERR_PTR(-EINVAL);
} else {
dev_info(&pdev->dev, "found external clock\n");
clk_prepare_enable(priv->extclk);
soc_dai = kirkwood_i2s_dai_extclk;
}
}
err = clk_prepare_enable(priv->clk);
if (err < 0)
return err;
/* Some sensible defaults - this reflects the powerup values */
priv->ctl_play = KIRKWOOD_PLAYCTL_SIZE_24;
priv->ctl_rec = KIRKWOOD_RECCTL_SIZE_24;
/* Select the burst size */
if (priv->burst == 32) {
priv->ctl_play |= KIRKWOOD_PLAYCTL_BURST_32;
priv->ctl_rec |= KIRKWOOD_RECCTL_BURST_32;
} else {
priv->ctl_play |= KIRKWOOD_PLAYCTL_BURST_128;
priv->ctl_rec |= KIRKWOOD_RECCTL_BURST_128;
}
err = snd_soc_register_component(&pdev->dev, &kirkwood_soc_component,
soc_dai, 2);
if (err) {
dev_err(&pdev->dev, "snd_soc_register_component failed\n");
goto err_component;
}
kirkwood_i2s_init(priv);
return 0;
err_component:
if (!IS_ERR(priv->extclk))
clk_disable_unprepare(priv->extclk);
clk_disable_unprepare(priv->clk);
return err;
}
static void kirkwood_i2s_dev_remove(struct platform_device *pdev)
{
struct kirkwood_dma_data *priv = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
if (!IS_ERR(priv->extclk))
clk_disable_unprepare(priv->extclk);
clk_disable_unprepare(priv->clk);
}
#ifdef CONFIG_OF
static const struct of_device_id mvebu_audio_of_match[] = {
{ .compatible = "marvell,kirkwood-audio" },
{ .compatible = "marvell,dove-audio" },
{ .compatible = "marvell,armada370-audio" },
{ .compatible = "marvell,armada-380-audio" },
{ }
};
MODULE_DEVICE_TABLE(of, mvebu_audio_of_match);
#endif
static struct platform_driver kirkwood_i2s_driver = {
.probe = kirkwood_i2s_dev_probe,
.remove_new = kirkwood_i2s_dev_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(mvebu_audio_of_match),
},
};
module_platform_driver(kirkwood_i2s_driver);
/* Module information */
MODULE_AUTHOR("Arnaud Patard, <[email protected]>");
MODULE_DESCRIPTION("Kirkwood I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mvebu-audio");
| linux-master | sound/soc/kirkwood/kirkwood-i2s.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2014 Marvell
*
* Thomas Petazzoni <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <linux/of.h>
#include <linux/platform_data/asoc-kirkwood.h>
#include "../codecs/cs42l51.h"
static int a370db_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int freq;
switch (params_rate(params)) {
default:
case 44100:
freq = 11289600;
break;
case 48000:
freq = 12288000;
break;
case 96000:
freq = 24576000;
break;
}
return snd_soc_dai_set_sysclk(codec_dai, 0, freq, SND_SOC_CLOCK_IN);
}
static const struct snd_soc_ops a370db_ops = {
.hw_params = a370db_hw_params,
};
static const struct snd_soc_dapm_widget a370db_dapm_widgets[] = {
SND_SOC_DAPM_HP("Out Jack", NULL),
SND_SOC_DAPM_LINE("In Jack", NULL),
};
static const struct snd_soc_dapm_route a370db_route[] = {
{ "Out Jack", NULL, "HPL" },
{ "Out Jack", NULL, "HPR" },
{ "AIN1L", NULL, "In Jack" },
{ "AIN1L", NULL, "In Jack" },
};
SND_SOC_DAILINK_DEFS(analog,
DAILINK_COMP_ARRAY(COMP_CPU("i2s")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42l51-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(spdif_out,
DAILINK_COMP_ARRAY(COMP_CPU("spdif")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "dit-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(spdif_in,
DAILINK_COMP_ARRAY(COMP_CPU("spdif")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "dir-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link a370db_dai[] = {
{
.name = "CS42L51",
.stream_name = "analog",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
.ops = &a370db_ops,
SND_SOC_DAILINK_REG(analog),
},
{
.name = "S/PDIF out",
.stream_name = "spdif-out",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(spdif_out),
},
{
.name = "S/PDIF in",
.stream_name = "spdif-in",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(spdif_in),
},
};
static struct snd_soc_card a370db = {
.name = "a370db",
.owner = THIS_MODULE,
.dai_link = a370db_dai,
.num_links = ARRAY_SIZE(a370db_dai),
.dapm_widgets = a370db_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(a370db_dapm_widgets),
.dapm_routes = a370db_route,
.num_dapm_routes = ARRAY_SIZE(a370db_route),
};
static int a370db_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &a370db;
card->dev = &pdev->dev;
a370db_dai[0].cpus->of_node =
of_parse_phandle(pdev->dev.of_node,
"marvell,audio-controller", 0);
a370db_dai[0].platforms->of_node = a370db_dai[0].cpus->of_node;
a370db_dai[0].codecs->of_node =
of_parse_phandle(pdev->dev.of_node,
"marvell,audio-codec", 0);
a370db_dai[1].cpus->of_node = a370db_dai[0].cpus->of_node;
a370db_dai[1].platforms->of_node = a370db_dai[0].cpus->of_node;
a370db_dai[1].codecs->of_node =
of_parse_phandle(pdev->dev.of_node,
"marvell,audio-codec", 1);
a370db_dai[2].cpus->of_node = a370db_dai[0].cpus->of_node;
a370db_dai[2].platforms->of_node = a370db_dai[0].cpus->of_node;
a370db_dai[2].codecs->of_node =
of_parse_phandle(pdev->dev.of_node,
"marvell,audio-codec", 2);
return devm_snd_soc_register_card(card->dev, card);
}
static const struct of_device_id a370db_dt_ids[] __maybe_unused = {
{ .compatible = "marvell,a370db-audio" },
{ },
};
MODULE_DEVICE_TABLE(of, a370db_dt_ids);
static struct platform_driver a370db_driver = {
.driver = {
.name = "a370db-audio",
.of_match_table = of_match_ptr(a370db_dt_ids),
},
.probe = a370db_probe,
};
module_platform_driver(a370db_driver);
MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC a370db audio client");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:a370db-audio");
| linux-master | sound/soc/kirkwood/armada-370-db.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* kirkwood-dma.c
*
* (c) 2010 Arnaud Patard <[email protected]>
* (c) 2010 Arnaud Patard <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <sound/soc.h>
#include "kirkwood.h"
static struct kirkwood_dma_data *kirkwood_priv(struct snd_pcm_substream *subs)
{
struct snd_soc_pcm_runtime *soc_runtime = subs->private_data;
return snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(soc_runtime, 0));
}
static const struct snd_pcm_hardware kirkwood_dma_snd_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
.buffer_bytes_max = KIRKWOOD_SND_MAX_BUFFER_BYTES,
.period_bytes_min = KIRKWOOD_SND_MIN_PERIOD_BYTES,
.period_bytes_max = KIRKWOOD_SND_MAX_PERIOD_BYTES,
.periods_min = KIRKWOOD_SND_MIN_PERIODS,
.periods_max = KIRKWOOD_SND_MAX_PERIODS,
.fifo_size = 0,
};
static irqreturn_t kirkwood_dma_irq(int irq, void *dev_id)
{
struct kirkwood_dma_data *priv = dev_id;
unsigned long mask, status, cause;
mask = readl(priv->io + KIRKWOOD_INT_MASK);
status = readl(priv->io + KIRKWOOD_INT_CAUSE) & mask;
cause = readl(priv->io + KIRKWOOD_ERR_CAUSE);
if (unlikely(cause)) {
printk(KERN_WARNING "%s: got err interrupt 0x%lx\n",
__func__, cause);
writel(cause, priv->io + KIRKWOOD_ERR_CAUSE);
}
/* we've enabled only bytes interrupts ... */
if (status & ~(KIRKWOOD_INT_CAUSE_PLAY_BYTES | \
KIRKWOOD_INT_CAUSE_REC_BYTES)) {
printk(KERN_WARNING "%s: unexpected interrupt %lx\n",
__func__, status);
return IRQ_NONE;
}
/* ack int */
writel(status, priv->io + KIRKWOOD_INT_CAUSE);
if (status & KIRKWOOD_INT_CAUSE_PLAY_BYTES)
snd_pcm_period_elapsed(priv->substream_play);
if (status & KIRKWOOD_INT_CAUSE_REC_BYTES)
snd_pcm_period_elapsed(priv->substream_rec);
return IRQ_HANDLED;
}
static void
kirkwood_dma_conf_mbus_windows(void __iomem *base, int win,
unsigned long dma,
const struct mbus_dram_target_info *dram)
{
int i;
/* First disable and clear windows */
writel(0, base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win));
writel(0, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win));
/* try to find matching cs for current dma address */
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = &dram->cs[i];
if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) {
writel(cs->base & 0xffff0000,
base + KIRKWOOD_AUDIO_WIN_BASE_REG(win));
writel(((cs->size - 1) & 0xffff0000) |
(cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win));
}
}
}
static int kirkwood_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
int err;
struct snd_pcm_runtime *runtime = substream->runtime;
struct kirkwood_dma_data *priv = kirkwood_priv(substream);
snd_soc_set_runtime_hwparams(substream, &kirkwood_dma_snd_hw);
/* Ensure that all constraints linked to dma burst are fulfilled */
err = snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
priv->burst * 2,
KIRKWOOD_AUDIO_BUF_MAX-1);
if (err < 0)
return err;
err = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
priv->burst);
if (err < 0)
return err;
err = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
priv->burst);
if (err < 0)
return err;
if (!priv->substream_play && !priv->substream_rec) {
err = request_irq(priv->irq, kirkwood_dma_irq, IRQF_SHARED,
"kirkwood-i2s", priv);
if (err)
return err;
/*
* Enable Error interrupts. We're only ack'ing them but
* it's useful for diagnostics
*/
writel((unsigned int)-1, priv->io + KIRKWOOD_ERR_MASK);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (priv->substream_play)
return -EBUSY;
priv->substream_play = substream;
} else {
if (priv->substream_rec)
return -EBUSY;
priv->substream_rec = substream;
}
return 0;
}
static int kirkwood_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct kirkwood_dma_data *priv = kirkwood_priv(substream);
if (!priv)
return 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
priv->substream_play = NULL;
else
priv->substream_rec = NULL;
if (!priv->substream_play && !priv->substream_rec) {
writel(0, priv->io + KIRKWOOD_ERR_MASK);
free_irq(priv->irq, priv);
}
return 0;
}
static int kirkwood_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct kirkwood_dma_data *priv = kirkwood_priv(substream);
const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
unsigned long addr = substream->runtime->dma_addr;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
kirkwood_dma_conf_mbus_windows(priv->io,
KIRKWOOD_PLAYBACK_WIN, addr, dram);
else
kirkwood_dma_conf_mbus_windows(priv->io,
KIRKWOOD_RECORD_WIN, addr, dram);
return 0;
}
static int kirkwood_dma_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct kirkwood_dma_data *priv = kirkwood_priv(substream);
unsigned long size, count;
/* compute buffer size in term of "words" as requested in specs */
size = frames_to_bytes(runtime, runtime->buffer_size);
size = (size>>2)-1;
count = snd_pcm_lib_period_bytes(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
writel(count, priv->io + KIRKWOOD_PLAY_BYTE_INT_COUNT);
writel(runtime->dma_addr, priv->io + KIRKWOOD_PLAY_BUF_ADDR);
writel(size, priv->io + KIRKWOOD_PLAY_BUF_SIZE);
} else {
writel(count, priv->io + KIRKWOOD_REC_BYTE_INT_COUNT);
writel(runtime->dma_addr, priv->io + KIRKWOOD_REC_BUF_ADDR);
writel(size, priv->io + KIRKWOOD_REC_BUF_SIZE);
}
return 0;
}
static snd_pcm_uframes_t kirkwood_dma_pointer(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct kirkwood_dma_data *priv = kirkwood_priv(substream);
snd_pcm_uframes_t count;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
count = bytes_to_frames(substream->runtime,
readl(priv->io + KIRKWOOD_PLAY_BYTE_COUNT));
else
count = bytes_to_frames(substream->runtime,
readl(priv->io + KIRKWOOD_REC_BYTE_COUNT));
return count;
}
static int kirkwood_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
size_t size = kirkwood_dma_snd_hw.buffer_bytes_max;
struct snd_card *card = rtd->card->snd_card;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
card->dev, size, size);
return 0;
}
const struct snd_soc_component_driver kirkwood_soc_component = {
.name = DRV_NAME,
.open = kirkwood_dma_open,
.close = kirkwood_dma_close,
.hw_params = kirkwood_dma_hw_params,
.prepare = kirkwood_dma_prepare,
.pointer = kirkwood_dma_pointer,
.pcm_construct = kirkwood_dma_new,
};
| linux-master | sound/soc/kirkwood/kirkwood-dma.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012-2013, Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#define AXI_I2S_REG_RESET 0x00
#define AXI_I2S_REG_CTRL 0x04
#define AXI_I2S_REG_CLK_CTRL 0x08
#define AXI_I2S_REG_STATUS 0x10
#define AXI_I2S_REG_RX_FIFO 0x28
#define AXI_I2S_REG_TX_FIFO 0x2C
#define AXI_I2S_RESET_GLOBAL BIT(0)
#define AXI_I2S_RESET_TX_FIFO BIT(1)
#define AXI_I2S_RESET_RX_FIFO BIT(2)
#define AXI_I2S_CTRL_TX_EN BIT(0)
#define AXI_I2S_CTRL_RX_EN BIT(1)
/* The frame size is configurable, but for now we always set it 64 bit */
#define AXI_I2S_BITS_PER_FRAME 64
struct axi_i2s {
struct regmap *regmap;
struct clk *clk;
struct clk *clk_ref;
bool has_capture;
bool has_playback;
struct snd_soc_dai_driver dai_driver;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct snd_ratnum ratnum;
struct snd_pcm_hw_constraint_ratnums rate_constraints;
};
static int axi_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mask = AXI_I2S_CTRL_RX_EN;
else
mask = AXI_I2S_CTRL_TX_EN;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
val = mask;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
val = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val);
return 0;
}
static int axi_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int bclk_div, word_size;
unsigned int bclk_rate;
bclk_rate = params_rate(params) * AXI_I2S_BITS_PER_FRAME;
word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1;
bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1;
regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) |
bclk_div);
return 0;
}
static int axi_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
uint32_t mask;
int ret;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mask = AXI_I2S_RESET_RX_FIFO;
else
mask = AXI_I2S_RESET_TX_FIFO;
regmap_write(i2s->regmap, AXI_I2S_REG_RESET, mask);
ret = snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&i2s->rate_constraints);
if (ret)
return ret;
return clk_prepare_enable(i2s->clk_ref);
}
static void axi_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
clk_disable_unprepare(i2s->clk_ref);
}
static int axi_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(
dai,
i2s->has_playback ? &i2s->playback_dma_data : NULL,
i2s->has_capture ? &i2s->capture_dma_data : NULL);
return 0;
}
static const struct snd_soc_dai_ops axi_i2s_dai_ops = {
.probe = axi_i2s_dai_probe,
.startup = axi_i2s_startup,
.shutdown = axi_i2s_shutdown,
.trigger = axi_i2s_trigger,
.hw_params = axi_i2s_hw_params,
};
static struct snd_soc_dai_driver axi_i2s_dai = {
.ops = &axi_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver axi_i2s_component = {
.name = "axi-i2s",
.legacy_dai_naming = 1,
};
static const struct regmap_config axi_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = AXI_I2S_REG_STATUS,
};
static void axi_i2s_parse_of(struct axi_i2s *i2s, const struct device_node *np)
{
struct property *dma_names;
const char *dma_name;
of_property_for_each_string(np, "dma-names", dma_names, dma_name) {
if (strcmp(dma_name, "rx") == 0)
i2s->has_capture = true;
if (strcmp(dma_name, "tx") == 0)
i2s->has_playback = true;
}
}
static int axi_i2s_probe(struct platform_device *pdev)
{
struct resource *res;
struct axi_i2s *i2s;
void __iomem *base;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
platform_set_drvdata(pdev, i2s);
axi_i2s_parse_of(i2s, pdev->dev.of_node);
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&axi_i2s_regmap_config);
if (IS_ERR(i2s->regmap))
return PTR_ERR(i2s->regmap);
i2s->clk = devm_clk_get(&pdev->dev, "axi");
if (IS_ERR(i2s->clk))
return PTR_ERR(i2s->clk);
i2s->clk_ref = devm_clk_get(&pdev->dev, "ref");
if (IS_ERR(i2s->clk_ref))
return PTR_ERR(i2s->clk_ref);
ret = clk_prepare_enable(i2s->clk);
if (ret)
return ret;
if (i2s->has_playback) {
axi_i2s_dai.playback.channels_min = 2;
axi_i2s_dai.playback.channels_max = 2;
axi_i2s_dai.playback.rates = SNDRV_PCM_RATE_KNOT;
axi_i2s_dai.playback.formats =
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE;
i2s->playback_dma_data.addr = res->start + AXI_I2S_REG_TX_FIFO;
i2s->playback_dma_data.addr_width = 4;
i2s->playback_dma_data.maxburst = 1;
}
if (i2s->has_capture) {
axi_i2s_dai.capture.channels_min = 2;
axi_i2s_dai.capture.channels_max = 2;
axi_i2s_dai.capture.rates = SNDRV_PCM_RATE_KNOT;
axi_i2s_dai.capture.formats =
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE;
i2s->capture_dma_data.addr = res->start + AXI_I2S_REG_RX_FIFO;
i2s->capture_dma_data.addr_width = 4;
i2s->capture_dma_data.maxburst = 1;
}
i2s->ratnum.num = clk_get_rate(i2s->clk_ref) / 2 / AXI_I2S_BITS_PER_FRAME;
i2s->ratnum.den_step = 1;
i2s->ratnum.den_min = 1;
i2s->ratnum.den_max = 64;
i2s->rate_constraints.rats = &i2s->ratnum;
i2s->rate_constraints.nrats = 1;
regmap_write(i2s->regmap, AXI_I2S_REG_RESET, AXI_I2S_RESET_GLOBAL);
ret = devm_snd_soc_register_component(&pdev->dev, &axi_i2s_component,
&axi_i2s_dai, 1);
if (ret)
goto err_clk_disable;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_clk_disable;
dev_info(&pdev->dev, "probed, capture %s, playback %s\n",
i2s->has_capture ? "enabled" : "disabled",
i2s->has_playback ? "enabled" : "disabled");
return 0;
err_clk_disable:
clk_disable_unprepare(i2s->clk);
return ret;
}
static void axi_i2s_dev_remove(struct platform_device *pdev)
{
struct axi_i2s *i2s = platform_get_drvdata(pdev);
clk_disable_unprepare(i2s->clk);
}
static const struct of_device_id axi_i2s_of_match[] = {
{ .compatible = "adi,axi-i2s-1.00.a", },
{},
};
MODULE_DEVICE_TABLE(of, axi_i2s_of_match);
static struct platform_driver axi_i2s_driver = {
.driver = {
.name = "axi-i2s",
.of_match_table = axi_i2s_of_match,
},
.probe = axi_i2s_probe,
.remove_new = axi_i2s_dev_remove,
};
module_platform_driver(axi_i2s_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("AXI I2S driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/adi/axi-i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012-2013, Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/dmaengine_pcm.h>
#define AXI_SPDIF_REG_CTRL 0x0
#define AXI_SPDIF_REG_STAT 0x4
#define AXI_SPDIF_REG_TX_FIFO 0xc
#define AXI_SPDIF_CTRL_TXDATA BIT(1)
#define AXI_SPDIF_CTRL_TXEN BIT(0)
#define AXI_SPDIF_CTRL_CLKDIV_OFFSET 8
#define AXI_SPDIF_CTRL_CLKDIV_MASK (0xff << 8)
#define AXI_SPDIF_FREQ_44100 (0x0 << 6)
#define AXI_SPDIF_FREQ_48000 (0x1 << 6)
#define AXI_SPDIF_FREQ_32000 (0x2 << 6)
#define AXI_SPDIF_FREQ_NA (0x3 << 6)
struct axi_spdif {
struct regmap *regmap;
struct clk *clk;
struct clk *clk_ref;
struct snd_dmaengine_dai_dma_data dma_data;
struct snd_ratnum ratnum;
struct snd_pcm_hw_constraint_ratnums rate_constraints;
};
static int axi_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
unsigned int val;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
val = AXI_SPDIF_CTRL_TXDATA;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
val = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
AXI_SPDIF_CTRL_TXDATA, val);
return 0;
}
static int axi_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
unsigned int clkdiv, stat;
switch (params_rate(params)) {
case 32000:
stat = AXI_SPDIF_FREQ_32000;
break;
case 44100:
stat = AXI_SPDIF_FREQ_44100;
break;
case 48000:
stat = AXI_SPDIF_FREQ_48000;
break;
default:
stat = AXI_SPDIF_FREQ_NA;
break;
}
clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref),
rate * 64 * 2) - 1;
clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET;
regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat);
regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
AXI_SPDIF_CTRL_CLKDIV_MASK, clkdiv);
return 0;
}
static int axi_spdif_dai_probe(struct snd_soc_dai *dai)
{
struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
return 0;
}
static int axi_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
int ret;
ret = snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&spdif->rate_constraints);
if (ret)
return ret;
ret = clk_prepare_enable(spdif->clk_ref);
if (ret)
return ret;
regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
AXI_SPDIF_CTRL_TXEN, AXI_SPDIF_CTRL_TXEN);
return 0;
}
static void axi_spdif_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axi_spdif *spdif = snd_soc_dai_get_drvdata(dai);
regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL,
AXI_SPDIF_CTRL_TXEN, 0);
clk_disable_unprepare(spdif->clk_ref);
}
static const struct snd_soc_dai_ops axi_spdif_dai_ops = {
.probe = axi_spdif_dai_probe,
.startup = axi_spdif_startup,
.shutdown = axi_spdif_shutdown,
.trigger = axi_spdif_trigger,
.hw_params = axi_spdif_hw_params,
};
static struct snd_soc_dai_driver axi_spdif_dai = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &axi_spdif_dai_ops,
};
static const struct snd_soc_component_driver axi_spdif_component = {
.name = "axi-spdif",
.legacy_dai_naming = 1,
};
static const struct regmap_config axi_spdif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = AXI_SPDIF_REG_STAT,
};
static int axi_spdif_probe(struct platform_device *pdev)
{
struct axi_spdif *spdif;
struct resource *res;
void __iomem *base;
int ret;
spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
if (!spdif)
return -ENOMEM;
platform_set_drvdata(pdev, spdif);
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
spdif->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&axi_spdif_regmap_config);
if (IS_ERR(spdif->regmap))
return PTR_ERR(spdif->regmap);
spdif->clk = devm_clk_get(&pdev->dev, "axi");
if (IS_ERR(spdif->clk))
return PTR_ERR(spdif->clk);
spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
if (IS_ERR(spdif->clk_ref))
return PTR_ERR(spdif->clk_ref);
ret = clk_prepare_enable(spdif->clk);
if (ret)
return ret;
spdif->dma_data.addr = res->start + AXI_SPDIF_REG_TX_FIFO;
spdif->dma_data.addr_width = 4;
spdif->dma_data.maxburst = 1;
spdif->ratnum.num = clk_get_rate(spdif->clk_ref) / 128;
spdif->ratnum.den_step = 1;
spdif->ratnum.den_min = 1;
spdif->ratnum.den_max = 64;
spdif->rate_constraints.rats = &spdif->ratnum;
spdif->rate_constraints.nrats = 1;
ret = devm_snd_soc_register_component(&pdev->dev, &axi_spdif_component,
&axi_spdif_dai, 1);
if (ret)
goto err_clk_disable;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_clk_disable;
return 0;
err_clk_disable:
clk_disable_unprepare(spdif->clk);
return ret;
}
static void axi_spdif_dev_remove(struct platform_device *pdev)
{
struct axi_spdif *spdif = platform_get_drvdata(pdev);
clk_disable_unprepare(spdif->clk);
}
static const struct of_device_id axi_spdif_of_match[] = {
{ .compatible = "adi,axi-spdif-tx-1.00.a", },
{},
};
MODULE_DEVICE_TABLE(of, axi_spdif_of_match);
static struct platform_driver axi_spdif_driver = {
.driver = {
.name = "axi-spdif",
.of_match_table = axi_spdif_of_match,
},
.probe = axi_spdif_probe,
.remove_new = axi_spdif_dev_remove,
};
module_platform_driver(axi_spdif_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("AXI SPDIF driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/adi/axi-spdif.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Xtfpga I2S controller driver
*
* Copyright (c) 2014 Cadence Design Systems Inc.
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define DRV_NAME "xtfpga-i2s"
#define XTFPGA_I2S_VERSION 0x00
#define XTFPGA_I2S_CONFIG 0x04
#define XTFPGA_I2S_INT_MASK 0x08
#define XTFPGA_I2S_INT_STATUS 0x0c
#define XTFPGA_I2S_CHAN0_DATA 0x10
#define XTFPGA_I2S_CHAN1_DATA 0x14
#define XTFPGA_I2S_CHAN2_DATA 0x18
#define XTFPGA_I2S_CHAN3_DATA 0x1c
#define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
#define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
#define XTFPGA_I2S_CONFIG_LEFT 0x4
#define XTFPGA_I2S_CONFIG_RATIO_BASE 8
#define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
#define XTFPGA_I2S_CONFIG_RES_BASE 16
#define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
#define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
#define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
#define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
#define XTFPGA_I2S_INT_UNDERRUN 0x1
#define XTFPGA_I2S_INT_LEVEL 0x2
#define XTFPGA_I2S_INT_VALID 0x3
#define XTFPGA_I2S_FIFO_SIZE 8192
/*
* I2S controller operation:
*
* Enabling TX: output 1 period of zeros (starting with left channel)
* and then queued data.
*
* Level status and interrupt: whenever FIFO level is below FIFO trigger,
* level status is 1 and an IRQ is asserted (if enabled).
*
* Underrun status and interrupt: whenever FIFO is empty, underrun status
* is 1 and an IRQ is asserted (if enabled).
*/
struct xtfpga_i2s {
struct device *dev;
struct clk *clk;
struct regmap *regmap;
void __iomem *regs;
/* current playback substream. NULL if not playing.
*
* Access to that field is synchronized between the interrupt handler
* and userspace through RCU.
*
* Interrupt handler (threaded part) does PIO on substream data in RCU
* read-side critical section. Trigger callback sets and clears the
* pointer when the playback is started and stopped with
* rcu_assign_pointer. When userspace is about to free the playback
* stream in the pcm_close callback it synchronizes with the interrupt
* handler by means of synchronize_rcu call.
*/
struct snd_pcm_substream __rcu *tx_substream;
unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
struct snd_pcm_runtime *runtime,
unsigned tx_ptr);
unsigned tx_ptr; /* next frame index in the sample buffer */
/* current fifo level estimate.
* Doesn't have to be perfectly accurate, but must be not less than
* the actual FIFO level in order to avoid stall on push attempt.
*/
unsigned tx_fifo_level;
/* FIFO level at which level interrupt occurs */
unsigned tx_fifo_low;
/* maximal FIFO level */
unsigned tx_fifo_high;
};
static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
{
return reg >= XTFPGA_I2S_CONFIG;
}
static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
{
return reg < XTFPGA_I2S_CHAN0_DATA;
}
static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
return reg == XTFPGA_I2S_INT_STATUS;
}
static const struct regmap_config xtfpga_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = XTFPGA_I2S_CHAN3_DATA,
.writeable_reg = xtfpga_i2s_wr_reg,
.readable_reg = xtfpga_i2s_rd_reg,
.volatile_reg = xtfpga_i2s_volatile_reg,
.cache_type = REGCACHE_FLAT,
};
/* Generate functions that do PIO from TX DMA area to FIFO for all supported
* stream formats.
* Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
* xtfpga_pcm_tx_2x16 for 16-bit stereo.
*
* FIFO consists of 32-bit words, one word per channel, always 2 channels.
* If I2S interface is configured with smaller sample resolution, only
* the LSB of each word is used.
*/
#define xtfpga_pcm_tx_fn(channels, sample_bits) \
static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
unsigned tx_ptr) \
{ \
const u##sample_bits (*p)[channels] = \
(void *)runtime->dma_area; \
\
for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
i2s->tx_fifo_level += 2) { \
iowrite32(p[tx_ptr][0], \
i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
iowrite32(p[tx_ptr][channels - 1], \
i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
if (++tx_ptr >= runtime->buffer_size) \
tx_ptr = 0; \
} \
return tx_ptr; \
}
xtfpga_pcm_tx_fn(1, 16)
xtfpga_pcm_tx_fn(2, 16)
xtfpga_pcm_tx_fn(1, 32)
xtfpga_pcm_tx_fn(2, 32)
#undef xtfpga_pcm_tx_fn
static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
{
struct snd_pcm_substream *tx_substream;
bool tx_active;
rcu_read_lock();
tx_substream = rcu_dereference(i2s->tx_substream);
tx_active = tx_substream && snd_pcm_running(tx_substream);
if (tx_active) {
unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
tx_ptr);
cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
}
rcu_read_unlock();
return tx_active;
}
static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
{
unsigned int_status;
unsigned i;
regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
&int_status);
for (i = 0; i < 2; ++i) {
bool tx_active = xtfpga_pcm_push_tx(i2s);
regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
XTFPGA_I2S_INT_VALID);
if (tx_active)
regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
&int_status);
if (!tx_active ||
!(int_status & XTFPGA_I2S_INT_LEVEL))
break;
/* After the push the level IRQ is still asserted,
* means FIFO level is below tx_fifo_low. Estimate
* it as tx_fifo_low.
*/
i2s->tx_fifo_level = i2s->tx_fifo_low;
}
if (!(int_status & XTFPGA_I2S_INT_LEVEL))
regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
XTFPGA_I2S_INT_VALID);
else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
XTFPGA_I2S_INT_UNDERRUN);
if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
XTFPGA_I2S_CONFIG_INT_ENABLE |
XTFPGA_I2S_CONFIG_TX_ENABLE,
XTFPGA_I2S_CONFIG_INT_ENABLE |
XTFPGA_I2S_CONFIG_TX_ENABLE);
else
regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
XTFPGA_I2S_CONFIG_INT_ENABLE |
XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
}
static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
{
struct xtfpga_i2s *i2s = dev_id;
struct snd_pcm_substream *tx_substream;
unsigned config, int_status, int_mask;
regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
!(int_status & int_mask & XTFPGA_I2S_INT_VALID))
return IRQ_NONE;
/* Update FIFO level estimate in accordance with interrupt status
* register.
*/
if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
i2s->tx_fifo_level = 0;
regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
} else {
/* The FIFO isn't empty, but is below tx_fifo_low. Estimate
* it as tx_fifo_low.
*/
i2s->tx_fifo_level = i2s->tx_fifo_low;
}
rcu_read_lock();
tx_substream = rcu_dereference(i2s->tx_substream);
if (tx_substream && snd_pcm_running(tx_substream)) {
snd_pcm_period_elapsed(tx_substream);
if (int_status & XTFPGA_I2S_INT_UNDERRUN)
dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
__func__);
}
rcu_read_unlock();
/* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
* not empty.
*/
xtfpga_pcm_refill_fifo(i2s);
return IRQ_HANDLED;
}
static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_set_dma_data(dai, substream, i2s);
return 0;
}
static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned srate = params_rate(params);
unsigned channels = params_channels(params);
unsigned period_size = params_period_size(params);
unsigned sample_size = snd_pcm_format_width(params_format(params));
unsigned freq, ratio, level;
int err;
regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
XTFPGA_I2S_CONFIG_RES_MASK,
sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
freq = 256 * srate;
err = clk_set_rate(i2s->clk, freq);
if (err < 0)
return err;
/* ratio field of the config register controls MCLK->I2S clock
* derivation: I2S clock = MCLK / (2 * (ratio + 2)).
*
* So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
* and 2 for 16 bit stereo.
*/
ratio = (freq - (srate * sample_size * 8)) /
(srate * sample_size * 4);
regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
XTFPGA_I2S_CONFIG_RATIO_MASK,
ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
/* period_size * 2: FIFO always gets 2 samples per frame */
for (level = 1;
i2s->tx_fifo_low / 2 >= period_size * 2 &&
level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
i2s->tx_fifo_low /= 2;
i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
XTFPGA_I2S_CONFIG_LEVEL_MASK,
level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
dev_dbg(i2s->dev,
"%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
__func__, srate, channels, sample_size, period_size);
dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
__func__, freq, ratio, level);
return 0;
}
static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
return -EINVAL;
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP)
return -EINVAL;
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
return -EINVAL;
return 0;
}
/* PCM */
static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BLOCK_TRANSFER,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 2,
.period_bytes_min = 2,
.period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
.periods_min = 2,
.periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
.buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
.fifo_size = 16,
};
static int xtfpga_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
void *p;
snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
p = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
runtime->private_data = p;
return 0;
}
static int xtfpga_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
synchronize_rcu();
return 0;
}
static int xtfpga_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct xtfpga_i2s *i2s = runtime->private_data;
unsigned channels = params_channels(hw_params);
switch (channels) {
case 1:
case 2:
break;
default:
return -EINVAL;
}
switch (params_format(hw_params)) {
case SNDRV_PCM_FORMAT_S16_LE:
i2s->tx_fn = (channels == 1) ?
xtfpga_pcm_tx_1x16 :
xtfpga_pcm_tx_2x16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
i2s->tx_fn = (channels == 1) ?
xtfpga_pcm_tx_1x32 :
xtfpga_pcm_tx_2x32;
break;
default:
return -EINVAL;
}
return 0;
}
static int xtfpga_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct xtfpga_i2s *i2s = runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
WRITE_ONCE(i2s->tx_ptr, 0);
rcu_assign_pointer(i2s->tx_substream, substream);
xtfpga_pcm_refill_fifo(i2s);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
rcu_assign_pointer(i2s->tx_substream, NULL);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct xtfpga_i2s *i2s = runtime->private_data;
snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
return pos < runtime->buffer_size ? pos : 0;
}
static int xtfpga_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
card->dev, size, size);
return 0;
}
static const struct snd_soc_component_driver xtfpga_i2s_component = {
.name = DRV_NAME,
.open = xtfpga_pcm_open,
.close = xtfpga_pcm_close,
.hw_params = xtfpga_pcm_hw_params,
.trigger = xtfpga_pcm_trigger,
.pointer = xtfpga_pcm_pointer,
.pcm_construct = xtfpga_pcm_new,
.legacy_dai_naming = 1,
};
static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
.startup = xtfpga_i2s_startup,
.hw_params = xtfpga_i2s_hw_params,
.set_fmt = xtfpga_i2s_set_fmt,
};
static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
{
.name = "xtfpga-i2s",
.id = 0,
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &xtfpga_i2s_dai_ops,
},
};
static int xtfpga_i2s_runtime_suspend(struct device *dev)
{
struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
clk_disable_unprepare(i2s->clk);
return 0;
}
static int xtfpga_i2s_runtime_resume(struct device *dev)
{
struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s->clk);
if (ret) {
dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
return ret;
}
return 0;
}
static int xtfpga_i2s_probe(struct platform_device *pdev)
{
struct xtfpga_i2s *i2s;
int err, irq;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s) {
err = -ENOMEM;
goto err;
}
platform_set_drvdata(pdev, i2s);
i2s->dev = &pdev->dev;
dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
i2s->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(i2s->regs)) {
err = PTR_ERR(i2s->regs);
goto err;
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
&xtfpga_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
err = PTR_ERR(i2s->regmap);
goto err;
}
i2s->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(i2s->clk)) {
dev_err(&pdev->dev, "couldn't get clock\n");
err = PTR_ERR(i2s->clk);
goto err;
}
regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
(0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
err = irq;
goto err;
}
err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
xtfpga_i2s_threaded_irq_handler,
IRQF_SHARED | IRQF_ONESHOT,
pdev->name, i2s);
if (err < 0) {
dev_err(&pdev->dev, "request_irq failed\n");
goto err;
}
err = devm_snd_soc_register_component(&pdev->dev,
&xtfpga_i2s_component,
xtfpga_i2s_dai,
ARRAY_SIZE(xtfpga_i2s_dai));
if (err < 0) {
dev_err(&pdev->dev, "couldn't register component\n");
goto err;
}
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
err = xtfpga_i2s_runtime_resume(&pdev->dev);
if (err)
goto err_pm_disable;
}
return 0;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err:
dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
return err;
}
static void xtfpga_i2s_remove(struct platform_device *pdev)
{
struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
if (i2s->regmap && !IS_ERR(i2s->regmap)) {
regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
XTFPGA_I2S_INT_VALID);
}
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
xtfpga_i2s_runtime_suspend(&pdev->dev);
}
#ifdef CONFIG_OF
static const struct of_device_id xtfpga_i2s_of_match[] = {
{ .compatible = "cdns,xtfpga-i2s", },
{},
};
MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
#endif
static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
xtfpga_i2s_runtime_resume, NULL)
};
static struct platform_driver xtfpga_i2s_driver = {
.probe = xtfpga_i2s_probe,
.remove_new = xtfpga_i2s_remove,
.driver = {
.name = "xtfpga-i2s",
.of_match_table = of_match_ptr(xtfpga_i2s_of_match),
.pm = &xtfpga_i2s_pm_ops,
},
};
module_platform_driver(xtfpga_i2s_driver);
MODULE_AUTHOR("Max Filippov <[email protected]>");
MODULE_DESCRIPTION("xtfpga I2S controller driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/xtensa/xtfpga-i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/sound/arm/pxa2xx-pcm.c -- ALSA PCM interface for the Intel PXA2xx chip
*
* Author: Nicolas Pitre
* Created: Nov 30, 2004
* Copyright: (C) 2004 MontaVista Software, Inc.
*/
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/dmaengine.h>
#include <linux/of.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
static const struct snd_soc_component_driver pxa2xx_soc_platform = {
.pcm_construct = pxa2xx_soc_pcm_new,
.open = pxa2xx_soc_pcm_open,
.close = pxa2xx_soc_pcm_close,
.hw_params = pxa2xx_soc_pcm_hw_params,
.prepare = pxa2xx_soc_pcm_prepare,
.trigger = pxa2xx_soc_pcm_trigger,
.pointer = pxa2xx_soc_pcm_pointer,
};
static int pxa2xx_soc_platform_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev, &pxa2xx_soc_platform,
NULL, 0);
}
static struct platform_driver pxa_pcm_driver = {
.driver = {
.name = "pxa-pcm-audio",
},
.probe = pxa2xx_soc_platform_probe,
};
module_platform_driver(pxa_pcm_driver);
MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel PXA2xx PCM DMA module");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-pcm-audio");
| linux-master | sound/soc/pxa/pxa2xx-pcm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* spitz.c -- SoC audio for Sharp SL-Cxx00 models Spitz, Borzoi and Akita
*
* Copyright 2005 Wolfson Microelectronics PLC.
* Copyright 2005 Openedhand Ltd.
*
* Authors: Liam Girdwood <[email protected]>
* Richard Purdie <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <asm/mach-types.h>
#include "../codecs/wm8750.h"
#include "pxa2xx-i2s.h"
#define SPITZ_HP 0
#define SPITZ_MIC 1
#define SPITZ_LINE 2
#define SPITZ_HEADSET 3
#define SPITZ_HP_OFF 4
#define SPITZ_SPK_ON 0
#define SPITZ_SPK_OFF 1
/* audio clock in Hz - rounded from 12.235MHz */
#define SPITZ_AUDIO_CLOCK 12288000
static int spitz_jack_func;
static int spitz_spk_func;
static struct gpio_desc *gpiod_mic, *gpiod_mute_l, *gpiod_mute_r;
static void spitz_ext_control(struct snd_soc_dapm_context *dapm)
{
snd_soc_dapm_mutex_lock(dapm);
if (spitz_spk_func == SPITZ_SPK_ON)
snd_soc_dapm_enable_pin_unlocked(dapm, "Ext Spk");
else
snd_soc_dapm_disable_pin_unlocked(dapm, "Ext Spk");
/* set up jack connection */
switch (spitz_jack_func) {
case SPITZ_HP:
/* enable and unmute hp jack, disable mic bias */
snd_soc_dapm_disable_pin_unlocked(dapm, "Headset Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Mic Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Line Jack");
snd_soc_dapm_enable_pin_unlocked(dapm, "Headphone Jack");
gpiod_set_value(gpiod_mute_l, 1);
gpiod_set_value(gpiod_mute_r, 1);
break;
case SPITZ_MIC:
/* enable mic jack and bias, mute hp */
snd_soc_dapm_disable_pin_unlocked(dapm, "Headphone Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Headset Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Line Jack");
snd_soc_dapm_enable_pin_unlocked(dapm, "Mic Jack");
gpiod_set_value(gpiod_mute_l, 0);
gpiod_set_value(gpiod_mute_r, 0);
break;
case SPITZ_LINE:
/* enable line jack, disable mic bias and mute hp */
snd_soc_dapm_disable_pin_unlocked(dapm, "Headphone Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Headset Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Mic Jack");
snd_soc_dapm_enable_pin_unlocked(dapm, "Line Jack");
gpiod_set_value(gpiod_mute_l, 0);
gpiod_set_value(gpiod_mute_r, 0);
break;
case SPITZ_HEADSET:
/* enable and unmute headset jack enable mic bias, mute L hp */
snd_soc_dapm_disable_pin_unlocked(dapm, "Headphone Jack");
snd_soc_dapm_enable_pin_unlocked(dapm, "Mic Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Line Jack");
snd_soc_dapm_enable_pin_unlocked(dapm, "Headset Jack");
gpiod_set_value(gpiod_mute_l, 0);
gpiod_set_value(gpiod_mute_r, 1);
break;
case SPITZ_HP_OFF:
/* jack removed, everything off */
snd_soc_dapm_disable_pin_unlocked(dapm, "Headphone Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Headset Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Mic Jack");
snd_soc_dapm_disable_pin_unlocked(dapm, "Line Jack");
gpiod_set_value(gpiod_mute_l, 0);
gpiod_set_value(gpiod_mute_r, 0);
break;
}
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
static int spitz_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
/* check the jack status at stream startup */
spitz_ext_control(&rtd->card->dapm);
return 0;
}
static int spitz_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
unsigned int clk = 0;
int ret = 0;
switch (params_rate(params)) {
case 8000:
case 16000:
case 48000:
case 96000:
clk = 12288000;
break;
case 11025:
case 22050:
case 44100:
clk = 11289600;
break;
}
/* set the codec system clock for DAC and ADC */
ret = snd_soc_dai_set_sysclk(codec_dai, WM8750_SYSCLK, clk,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
/* set the I2S system clock as input (unused) */
ret = snd_soc_dai_set_sysclk(cpu_dai, PXA2XX_I2S_SYSCLK, 0,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_ops spitz_ops = {
.startup = spitz_startup,
.hw_params = spitz_hw_params,
};
static int spitz_get_jack(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.enumerated.item[0] = spitz_jack_func;
return 0;
}
static int spitz_set_jack(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
if (spitz_jack_func == ucontrol->value.enumerated.item[0])
return 0;
spitz_jack_func = ucontrol->value.enumerated.item[0];
spitz_ext_control(&card->dapm);
return 1;
}
static int spitz_get_spk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.enumerated.item[0] = spitz_spk_func;
return 0;
}
static int spitz_set_spk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
if (spitz_spk_func == ucontrol->value.enumerated.item[0])
return 0;
spitz_spk_func = ucontrol->value.enumerated.item[0];
spitz_ext_control(&card->dapm);
return 1;
}
static int spitz_mic_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
gpiod_set_value_cansleep(gpiod_mic, SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
/* spitz machine dapm widgets */
static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic Jack", spitz_mic_bias),
SND_SOC_DAPM_SPK("Ext Spk", NULL),
SND_SOC_DAPM_LINE("Line Jack", NULL),
/* headset is a mic and mono headphone */
SND_SOC_DAPM_HP("Headset Jack", NULL),
};
/* Spitz machine audio_map */
static const struct snd_soc_dapm_route spitz_audio_map[] = {
/* headphone connected to LOUT1, ROUT1 */
{"Headphone Jack", NULL, "LOUT1"},
{"Headphone Jack", NULL, "ROUT1"},
/* headset connected to ROUT1 and LINPUT1 with bias (def below) */
{"Headset Jack", NULL, "ROUT1"},
/* ext speaker connected to LOUT2, ROUT2 */
{"Ext Spk", NULL, "ROUT2"},
{"Ext Spk", NULL, "LOUT2"},
/* mic is connected to input 1 - with bias */
{"LINPUT1", NULL, "Mic Bias"},
{"Mic Bias", NULL, "Mic Jack"},
/* line is connected to input 1 - no bias */
{"LINPUT1", NULL, "Line Jack"},
};
static const char * const jack_function[] = {"Headphone", "Mic", "Line",
"Headset", "Off"};
static const char * const spk_function[] = {"On", "Off"};
static const struct soc_enum spitz_enum[] = {
SOC_ENUM_SINGLE_EXT(5, jack_function),
SOC_ENUM_SINGLE_EXT(2, spk_function),
};
static const struct snd_kcontrol_new wm8750_spitz_controls[] = {
SOC_ENUM_EXT("Jack Function", spitz_enum[0], spitz_get_jack,
spitz_set_jack),
SOC_ENUM_EXT("Speaker Function", spitz_enum[1], spitz_get_spk,
spitz_set_spk),
};
/* spitz digital audio interface glue - connects codec <--> CPU */
SND_SOC_DAILINK_DEFS(wm8750,
DAILINK_COMP_ARRAY(COMP_CPU("pxa2xx-i2s")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8750.0-001b", "wm8750-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("pxa-pcm-audio")));
static struct snd_soc_dai_link spitz_dai = {
.name = "wm8750",
.stream_name = "WM8750",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &spitz_ops,
SND_SOC_DAILINK_REG(wm8750),
};
/* spitz audio machine driver */
static struct snd_soc_card snd_soc_spitz = {
.name = "Spitz",
.owner = THIS_MODULE,
.dai_link = &spitz_dai,
.num_links = 1,
.controls = wm8750_spitz_controls,
.num_controls = ARRAY_SIZE(wm8750_spitz_controls),
.dapm_widgets = wm8750_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8750_dapm_widgets),
.dapm_routes = spitz_audio_map,
.num_dapm_routes = ARRAY_SIZE(spitz_audio_map),
.fully_routed = true,
};
static int spitz_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &snd_soc_spitz;
int ret;
gpiod_mic = devm_gpiod_get(&pdev->dev, "mic", GPIOD_OUT_LOW);
if (IS_ERR(gpiod_mic))
return PTR_ERR(gpiod_mic);
gpiod_mute_l = devm_gpiod_get(&pdev->dev, "mute-l", GPIOD_OUT_LOW);
if (IS_ERR(gpiod_mute_l))
return PTR_ERR(gpiod_mute_l);
gpiod_mute_r = devm_gpiod_get(&pdev->dev, "mute-r", GPIOD_OUT_LOW);
if (IS_ERR(gpiod_mute_r))
return PTR_ERR(gpiod_mute_r);
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
ret);
return ret;
}
static struct platform_driver spitz_driver = {
.driver = {
.name = "spitz-audio",
.pm = &snd_soc_pm_ops,
},
.probe = spitz_probe,
};
module_platform_driver(spitz_driver);
MODULE_AUTHOR("Richard Purdie");
MODULE_DESCRIPTION("ALSA SoC Spitz");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:spitz-audio");
| linux-master | sound/soc/pxa/spitz.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/sound/soc/pxa/mmp-sspa.c
* Base on pxa2xx-ssp.c
*
* Copyright (C) 2011 Marvell International Ltd.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/dmaengine.h>
#include <linux/pm_runtime.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
#include "mmp-sspa.h"
/*
* SSPA audio private data
*/
struct sspa_priv {
void __iomem *tx_base;
void __iomem *rx_base;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct clk *clk;
struct clk *audio_clk;
struct clk *sysclk;
int running_cnt;
u32 sp;
u32 ctrl;
};
static void mmp_sspa_tx_enable(struct sspa_priv *sspa)
{
unsigned int sspa_sp = sspa->sp;
sspa_sp &= ~SSPA_SP_MSL;
sspa_sp |= SSPA_SP_S_EN;
sspa_sp |= SSPA_SP_WEN;
__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
}
static void mmp_sspa_tx_disable(struct sspa_priv *sspa)
{
unsigned int sspa_sp = sspa->sp;
sspa_sp &= ~SSPA_SP_MSL;
sspa_sp &= ~SSPA_SP_S_EN;
sspa_sp |= SSPA_SP_WEN;
__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
}
static void mmp_sspa_rx_enable(struct sspa_priv *sspa)
{
unsigned int sspa_sp = sspa->sp;
sspa_sp |= SSPA_SP_S_EN;
sspa_sp |= SSPA_SP_WEN;
__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
}
static void mmp_sspa_rx_disable(struct sspa_priv *sspa)
{
unsigned int sspa_sp = sspa->sp;
sspa_sp &= ~SSPA_SP_S_EN;
sspa_sp |= SSPA_SP_WEN;
__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
}
static int mmp_sspa_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
clk_prepare_enable(sspa->sysclk);
clk_prepare_enable(sspa->clk);
return 0;
}
static void mmp_sspa_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
clk_disable_unprepare(sspa->clk);
clk_disable_unprepare(sspa->sysclk);
}
/*
* Set the SSP ports SYSCLK.
*/
static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
struct device *dev = cpu_dai->component->dev;
int ret = 0;
if (dev->of_node)
return -ENOTSUPP;
switch (clk_id) {
case MMP_SSPA_CLK_AUDIO:
ret = clk_set_rate(sspa->audio_clk, freq);
if (ret)
return ret;
break;
case MMP_SSPA_CLK_PLL:
case MMP_SSPA_CLK_VCXO:
/* not support yet */
return -EINVAL;
default:
return -EINVAL;
}
return 0;
}
static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
struct device *dev = cpu_dai->component->dev;
int ret = 0;
if (dev->of_node)
return -ENOTSUPP;
switch (pll_id) {
case MMP_SYSCLK:
ret = clk_set_rate(sspa->sysclk, freq_out);
if (ret)
return ret;
break;
case MMP_SSPA_CLK:
ret = clk_set_rate(sspa->clk, freq_out);
if (ret)
return ret;
break;
default:
return -ENODEV;
}
return 0;
}
/*
* Set up the sspa dai format.
*/
static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
/* reset port settings */
sspa->sp = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH;
sspa->ctrl = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
sspa->sp |= SSPA_SP_MSL;
break;
case SND_SOC_DAIFMT_BC_FC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
sspa->sp |= SSPA_SP_FSP;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
sspa->ctrl |= SSPA_CTL_XDATDLY(1);
break;
default:
return -EINVAL;
}
/* Since we are configuring the timings for the format by hand
* we have to defer some things until hw_params() where we
* know parameters like the sample size.
*/
return 0;
}
/*
* Set the SSPA audio DMA parameters and sample size.
* Can be called multiple times by oss emulation.
*/
static int mmp_sspa_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
struct device *dev = dai->component->dev;
u32 sspa_ctrl = sspa->ctrl;
int bits;
int bitval;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
bits = 8;
bitval = SSPA_CTL_8_BITS;
break;
case SNDRV_PCM_FORMAT_S16_LE:
bits = 16;
bitval = SSPA_CTL_16_BITS;
break;
case SNDRV_PCM_FORMAT_S24_3LE:
bits = 24;
bitval = SSPA_CTL_24_BITS;
break;
case SNDRV_PCM_FORMAT_S32_LE:
bits = 32;
bitval = SSPA_CTL_32_BITS;
break;
default:
return -EINVAL;
}
sspa_ctrl &= ~SSPA_CTL_XPH;
if (dev->of_node || params_channels(params) == 2)
sspa_ctrl |= SSPA_CTL_XPH;
sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK;
sspa_ctrl |= SSPA_CTL_XWDLEN1(bitval);
sspa_ctrl &= ~SSPA_CTL_XWDLEN2_MASK;
sspa_ctrl |= SSPA_CTL_XWDLEN2(bitval);
sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK;
sspa_ctrl |= SSPA_CTL_XSSZ1(bitval);
sspa_ctrl &= ~SSPA_CTL_XSSZ2_MASK;
sspa_ctrl |= SSPA_CTL_XSSZ2(bitval);
sspa->sp &= ~SSPA_SP_FWID_MASK;
sspa->sp |= SSPA_SP_FWID(bits - 1);
sspa->sp &= ~SSPA_TXSP_FPER_MASK;
sspa->sp |= SSPA_TXSP_FPER(bits * 2 - 1);
if (dev->of_node) {
clk_set_rate(sspa->clk, params_rate(params) *
params_channels(params) * bits);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
__raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL);
__raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL);
} else {
__raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL);
__raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL);
}
return 0;
}
static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/*
* whatever playback or capture, must enable rx.
* this is a hw issue, so need check if rx has been
* enabled or not; if has been enabled by another
* stream, do not enable again.
*/
if (!sspa->running_cnt)
mmp_sspa_rx_enable(sspa);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mmp_sspa_tx_enable(sspa);
sspa->running_cnt++;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
sspa->running_cnt--;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mmp_sspa_tx_disable(sspa);
/* have no capture stream, disable rx port */
if (!sspa->running_cnt)
mmp_sspa_rx_disable(sspa);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int mmp_sspa_probe(struct snd_soc_dai *dai)
{
struct sspa_priv *sspa = dev_get_drvdata(dai->dev);
snd_soc_dai_init_dma_data(dai,
&sspa->playback_dma_data,
&sspa->capture_dma_data);
return 0;
}
#define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000
#define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops mmp_sspa_dai_ops = {
.probe = mmp_sspa_probe,
.startup = mmp_sspa_startup,
.shutdown = mmp_sspa_shutdown,
.trigger = mmp_sspa_trigger,
.hw_params = mmp_sspa_hw_params,
.set_sysclk = mmp_sspa_set_dai_sysclk,
.set_pll = mmp_sspa_set_dai_pll,
.set_fmt = mmp_sspa_set_dai_fmt,
};
static struct snd_soc_dai_driver mmp_sspa_dai = {
.playback = {
.channels_min = 1,
.channels_max = 128,
.rates = MMP_SSPA_RATES,
.formats = MMP_SSPA_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = MMP_SSPA_RATES,
.formats = MMP_SSPA_FORMATS,
},
.ops = &mmp_sspa_dai_ops,
};
#define MMP_PCM_INFO (SNDRV_PCM_INFO_MMAP | \
SNDRV_PCM_INFO_MMAP_VALID | \
SNDRV_PCM_INFO_INTERLEAVED | \
SNDRV_PCM_INFO_PAUSE | \
SNDRV_PCM_INFO_RESUME | \
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP)
static const struct snd_pcm_hardware mmp_pcm_hardware[] = {
{
.info = MMP_PCM_INFO,
.period_bytes_min = 1024,
.period_bytes_max = 2048,
.periods_min = 2,
.periods_max = 32,
.buffer_bytes_max = 4096,
.fifo_size = 32,
},
{
.info = MMP_PCM_INFO,
.period_bytes_min = 1024,
.period_bytes_max = 2048,
.periods_min = 2,
.periods_max = 32,
.buffer_bytes_max = 4096,
.fifo_size = 32,
},
};
static const struct snd_dmaengine_pcm_config mmp_pcm_config = {
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
.pcm_hardware = mmp_pcm_hardware,
.prealloc_buffer_size = 4096,
};
static int mmp_pcm_mmap(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP);
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
return remap_pfn_range(vma, vma->vm_start,
substream->dma_buffer.addr >> PAGE_SHIFT,
vma->vm_end - vma->vm_start, vma->vm_page_prot);
}
static int mmp_sspa_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct sspa_priv *sspa = snd_soc_component_get_drvdata(component);
pm_runtime_get_sync(component->dev);
/* we can only change the settings if the port is not in use */
if ((__raw_readl(sspa->tx_base + SSPA_SP) & SSPA_SP_S_EN) ||
(__raw_readl(sspa->rx_base + SSPA_SP) & SSPA_SP_S_EN)) {
dev_err(component->dev,
"can't change hardware dai format: stream is in use\n");
return -EBUSY;
}
__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
sspa->sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH);
__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
/*
* FIXME: hw issue, for the tx serial port,
* can not config the master/slave mode;
* so must clean this bit.
* The master/slave mode has been set in the
* rx port.
*/
__raw_writel(sspa->sp & ~SSPA_SP_MSL, sspa->tx_base + SSPA_SP);
__raw_writel(sspa->ctrl, sspa->tx_base + SSPA_CTL);
__raw_writel(sspa->ctrl, sspa->rx_base + SSPA_CTL);
return 0;
}
static int mmp_sspa_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
pm_runtime_put_sync(component->dev);
return 0;
}
static const struct snd_soc_component_driver mmp_sspa_component = {
.name = "mmp-sspa",
.mmap = mmp_pcm_mmap,
.open = mmp_sspa_open,
.close = mmp_sspa_close,
.legacy_dai_naming = 1,
};
static int asoc_mmp_sspa_probe(struct platform_device *pdev)
{
struct sspa_priv *sspa;
int ret;
sspa = devm_kzalloc(&pdev->dev,
sizeof(struct sspa_priv), GFP_KERNEL);
if (!sspa)
return -ENOMEM;
if (pdev->dev.of_node) {
sspa->rx_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sspa->rx_base))
return PTR_ERR(sspa->rx_base);
sspa->tx_base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(sspa->tx_base))
return PTR_ERR(sspa->tx_base);
sspa->clk = devm_clk_get(&pdev->dev, "bitclk");
if (IS_ERR(sspa->clk))
return PTR_ERR(sspa->clk);
sspa->audio_clk = devm_clk_get(&pdev->dev, "audio");
if (IS_ERR(sspa->audio_clk))
return PTR_ERR(sspa->audio_clk);
} else {
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (res == NULL)
return -ENODEV;
sspa->rx_base = devm_ioremap(&pdev->dev, res->start, 0x30);
if (!sspa->rx_base)
return -ENOMEM;
sspa->tx_base = devm_ioremap(&pdev->dev,
res->start + 0x80, 0x30);
if (!sspa->tx_base)
return -ENOMEM;
sspa->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(sspa->clk))
return PTR_ERR(sspa->clk);
sspa->audio_clk = clk_get(NULL, "mmp-audio");
if (IS_ERR(sspa->audio_clk))
return PTR_ERR(sspa->audio_clk);
sspa->sysclk = clk_get(NULL, "mmp-sysclk");
if (IS_ERR(sspa->sysclk)) {
clk_put(sspa->audio_clk);
return PTR_ERR(sspa->sysclk);
}
}
platform_set_drvdata(pdev, sspa);
sspa->playback_dma_data.maxburst = 4;
sspa->capture_dma_data.maxburst = 4;
/* You know, these addresses are actually ignored. */
sspa->capture_dma_data.addr = SSPA_D;
sspa->playback_dma_data.addr = 0x80 + SSPA_D;
if (pdev->dev.of_node) {
ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
&mmp_pcm_config, 0);
if (ret)
return ret;
}
ret = devm_snd_soc_register_component(&pdev->dev, &mmp_sspa_component,
&mmp_sspa_dai, 1);
if (ret)
return ret;
pm_runtime_enable(&pdev->dev);
clk_prepare_enable(sspa->audio_clk);
return 0;
}
static void asoc_mmp_sspa_remove(struct platform_device *pdev)
{
struct sspa_priv *sspa = platform_get_drvdata(pdev);
clk_disable_unprepare(sspa->audio_clk);
pm_runtime_disable(&pdev->dev);
if (pdev->dev.of_node)
return;
clk_put(sspa->audio_clk);
clk_put(sspa->sysclk);
}
#ifdef CONFIG_OF
static const struct of_device_id mmp_sspa_of_match[] = {
{ .compatible = "marvell,mmp-sspa" },
{},
};
MODULE_DEVICE_TABLE(of, mmp_sspa_of_match);
#endif
static struct platform_driver asoc_mmp_sspa_driver = {
.driver = {
.name = "mmp-sspa-dai",
.of_match_table = of_match_ptr(mmp_sspa_of_match),
},
.probe = asoc_mmp_sspa_probe,
.remove_new = asoc_mmp_sspa_remove,
};
module_platform_driver(asoc_mmp_sspa_driver);
MODULE_AUTHOR("Leo Yan <[email protected]>");
MODULE_DESCRIPTION("MMP SSPA SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mmp-sspa-dai");
| linux-master | sound/soc/pxa/mmp-sspa.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
*
* Author: Nicolas Pitre
* Created: Dec 02, 2004
* Copyright: MontaVista Software Inc.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/dma/pxa-dma.h>
#include <sound/ac97/controller.h>
#include <sound/core.h>
#include <sound/ac97_codec.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
#include <linux/platform_data/asoc-pxa.h>
#define PCDR 0x0040 /* PCM FIFO Data Register */
#define MODR 0x0140 /* Modem FIFO Data Register */
#define MCDR 0x0060 /* Mic-in FIFO Data Register */
static void pxa2xx_ac97_warm_reset(struct ac97_controller *adrv)
{
pxa2xx_ac97_try_warm_reset();
pxa2xx_ac97_finish_reset();
}
static void pxa2xx_ac97_cold_reset(struct ac97_controller *adrv)
{
pxa2xx_ac97_try_cold_reset();
pxa2xx_ac97_finish_reset();
}
static int pxa2xx_ac97_read_actrl(struct ac97_controller *adrv, int slot,
unsigned short reg)
{
return pxa2xx_ac97_read(slot, reg);
}
static int pxa2xx_ac97_write_actrl(struct ac97_controller *adrv, int slot,
unsigned short reg, unsigned short val)
{
return pxa2xx_ac97_write(slot, reg, val);
}
static struct ac97_controller_ops pxa2xx_ac97_ops = {
.read = pxa2xx_ac97_read_actrl,
.write = pxa2xx_ac97_write_actrl,
.warm_reset = pxa2xx_ac97_warm_reset,
.reset = pxa2xx_ac97_cold_reset,
};
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_in = {
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
.chan_name = "pcm_pcm_stereo_in",
.maxburst = 32,
};
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_out = {
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
.chan_name = "pcm_pcm_stereo_out",
.maxburst = 32,
};
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_out = {
.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
.chan_name = "pcm_aux_mono_out",
.maxburst = 16,
};
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_in = {
.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
.chan_name = "pcm_aux_mono_in",
.maxburst = 16,
};
static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_mic_mono_in = {
.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
.chan_name = "pcm_aux_mic_mono",
.maxburst = 16,
};
static int pxa2xx_ac97_hifi_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_dmaengine_dai_dma_data *dma_data;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = &pxa2xx_ac97_pcm_stereo_out;
else
dma_data = &pxa2xx_ac97_pcm_stereo_in;
snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
return 0;
}
static int pxa2xx_ac97_aux_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_dmaengine_dai_dma_data *dma_data;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = &pxa2xx_ac97_pcm_aux_mono_out;
else
dma_data = &pxa2xx_ac97_pcm_aux_mono_in;
snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
return 0;
}
static int pxa2xx_ac97_mic_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return -ENODEV;
snd_soc_dai_set_dma_data(cpu_dai, substream,
&pxa2xx_ac97_pcm_mic_mono_in);
return 0;
}
#define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
static const struct snd_soc_dai_ops pxa_ac97_hifi_dai_ops = {
.startup = pxa2xx_ac97_hifi_startup,
};
static const struct snd_soc_dai_ops pxa_ac97_aux_dai_ops = {
.startup = pxa2xx_ac97_aux_startup,
};
static const struct snd_soc_dai_ops pxa_ac97_mic_dai_ops = {
.startup = pxa2xx_ac97_mic_startup,
};
/*
* There is only 1 physical AC97 interface for pxa2xx, but it
* has extra fifo's that can be used for aux DACs and ADCs.
*/
static struct snd_soc_dai_driver pxa_ac97_dai_driver[] = {
{
.name = "pxa2xx-ac97",
.playback = {
.stream_name = "AC97 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = PXA2XX_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "AC97 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = PXA2XX_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &pxa_ac97_hifi_dai_ops,
},
{
.name = "pxa2xx-ac97-aux",
.playback = {
.stream_name = "AC97 Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = PXA2XX_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "AC97 Aux Capture",
.channels_min = 1,
.channels_max = 1,
.rates = PXA2XX_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &pxa_ac97_aux_dai_ops,
},
{
.name = "pxa2xx-ac97-mic",
.capture = {
.stream_name = "AC97 Mic Capture",
.channels_min = 1,
.channels_max = 1,
.rates = PXA2XX_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &pxa_ac97_mic_dai_ops,
},
};
static const struct snd_soc_component_driver pxa_ac97_component = {
.name = "pxa-ac97",
.pcm_construct = pxa2xx_soc_pcm_new,
.open = pxa2xx_soc_pcm_open,
.close = pxa2xx_soc_pcm_close,
.hw_params = pxa2xx_soc_pcm_hw_params,
.prepare = pxa2xx_soc_pcm_prepare,
.trigger = pxa2xx_soc_pcm_trigger,
.pointer = pxa2xx_soc_pcm_pointer,
};
#ifdef CONFIG_OF
static const struct of_device_id pxa2xx_ac97_dt_ids[] = {
{ .compatible = "marvell,pxa250-ac97", },
{ .compatible = "marvell,pxa270-ac97", },
{ .compatible = "marvell,pxa300-ac97", },
{ }
};
MODULE_DEVICE_TABLE(of, pxa2xx_ac97_dt_ids);
#endif
static int pxa2xx_ac97_dev_probe(struct platform_device *pdev)
{
int ret;
struct ac97_controller *ctrl;
pxa2xx_audio_ops_t *pdata = pdev->dev.platform_data;
struct resource *regs;
void **codecs_pdata;
if (pdev->id != -1) {
dev_err(&pdev->dev, "PXA2xx has only one AC97 port.\n");
return -ENXIO;
}
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs)
return -ENXIO;
pxa2xx_ac97_pcm_stereo_in.addr = regs->start + PCDR;
pxa2xx_ac97_pcm_stereo_out.addr = regs->start + PCDR;
pxa2xx_ac97_pcm_aux_mono_out.addr = regs->start + MODR;
pxa2xx_ac97_pcm_aux_mono_in.addr = regs->start + MODR;
pxa2xx_ac97_pcm_mic_mono_in.addr = regs->start + MCDR;
ret = pxa2xx_ac97_hw_probe(pdev);
if (ret) {
dev_err(&pdev->dev, "PXA2xx AC97 hw probe error (%d)\n", ret);
return ret;
}
codecs_pdata = pdata ? pdata->codec_pdata : NULL;
ctrl = snd_ac97_controller_register(&pxa2xx_ac97_ops, &pdev->dev,
AC97_SLOTS_AVAILABLE_ALL,
codecs_pdata);
if (IS_ERR(ctrl))
return PTR_ERR(ctrl);
platform_set_drvdata(pdev, ctrl);
/* Punt most of the init to the SoC probe; we may need the machine
* driver to do interesting things with the clocking to get us up
* and running.
*/
return devm_snd_soc_register_component(&pdev->dev, &pxa_ac97_component,
pxa_ac97_dai_driver, ARRAY_SIZE(pxa_ac97_dai_driver));
}
static void pxa2xx_ac97_dev_remove(struct platform_device *pdev)
{
struct ac97_controller *ctrl = platform_get_drvdata(pdev);
snd_ac97_controller_unregister(ctrl);
pxa2xx_ac97_hw_remove(pdev);
}
#ifdef CONFIG_PM_SLEEP
static int pxa2xx_ac97_dev_suspend(struct device *dev)
{
return pxa2xx_ac97_hw_suspend();
}
static int pxa2xx_ac97_dev_resume(struct device *dev)
{
return pxa2xx_ac97_hw_resume();
}
static SIMPLE_DEV_PM_OPS(pxa2xx_ac97_pm_ops,
pxa2xx_ac97_dev_suspend, pxa2xx_ac97_dev_resume);
#endif
static struct platform_driver pxa2xx_ac97_driver = {
.probe = pxa2xx_ac97_dev_probe,
.remove_new = pxa2xx_ac97_dev_remove,
.driver = {
.name = "pxa2xx-ac97",
#ifdef CONFIG_PM_SLEEP
.pm = &pxa2xx_ac97_pm_ops,
#endif
.of_match_table = of_match_ptr(pxa2xx_ac97_dt_ids),
},
};
module_platform_driver(pxa2xx_ac97_driver);
MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-ac97");
| linux-master | sound/soc/pxa/pxa2xx-ac97.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pxa2xx-i2s.c -- ALSA Soc Audio Layer
*
* Copyright 2005 Wolfson Microelectronics PLC.
* Author: Liam Girdwood
* [email protected]
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
#include <linux/platform_data/asoc-pxa.h>
#include "pxa2xx-i2s.h"
/*
* I2S Controller Register and Bit Definitions
*/
#define SACR0 (0x0000) /* Global Control Register */
#define SACR1 (0x0004) /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0 (0x000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR (0x0014) /* Serial Audio Interrupt Mask Register */
#define SAICR (0x0018) /* Serial Audio Interrupt Clear Register */
#define SADIV (0x0060) /* Audio Clock Divider Register. */
#define SADR (0x0080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
#define SACR0_ENB (1 << 0) /* Enable I2S Link */
#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
#define SACR1_DREC (1 << 3) /* Disable Recording Function */
#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
#define SASR0_I2SOFF (1 << 7) /* Controller Status */
#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
#define SASR0_BSY (1 << 2) /* I2S Busy */
#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
struct pxa_i2s_port {
u32 sadiv;
u32 sacr0;
u32 sacr1;
u32 saimr;
int master;
u32 fmt;
};
static struct pxa_i2s_port pxa_i2s;
static struct clk *clk_i2s;
static int clk_ena = 0;
static void __iomem *i2s_reg_base;
static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
.chan_name = "tx",
.maxburst = 32,
};
static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
.chan_name = "rx",
.maxburst = 32,
};
static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
if (IS_ERR(clk_i2s))
return PTR_ERR(clk_i2s);
if (!snd_soc_dai_active(cpu_dai))
writel(0, i2s_reg_base + SACR0);
return 0;
}
/* wait for I2S controller to be ready */
static int pxa_i2s_wait(void)
{
int i;
/* flush the Rx FIFO */
for (i = 0; i < 16; i++)
readl(i2s_reg_base + SADR);
return 0;
}
static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pxa_i2s.fmt = 0;
break;
case SND_SOC_DAIFMT_LEFT_J:
pxa_i2s.fmt = SACR1_AMSL;
break;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
pxa_i2s.master = 1;
break;
case SND_SOC_DAIFMT_BC_FP:
pxa_i2s.master = 0;
break;
default:
break;
}
return 0;
}
static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
if (clk_id != PXA2XX_I2S_SYSCLK)
return -ENODEV;
return 0;
}
static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_dmaengine_dai_dma_data *dma_data;
if (WARN_ON(IS_ERR(clk_i2s)))
return -EINVAL;
clk_prepare_enable(clk_i2s);
clk_ena = 1;
pxa_i2s_wait();
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = &pxa2xx_i2s_pcm_stereo_out;
else
dma_data = &pxa2xx_i2s_pcm_stereo_in;
snd_soc_dai_set_dma_data(dai, substream, dma_data);
/* is port used by another stream */
if (!(SACR0 & SACR0_ENB)) {
writel(0, i2s_reg_base + SACR0);
if (pxa_i2s.master)
writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0);
writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0);
writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR);
else
writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR);
switch (params_rate(params)) {
case 8000:
writel(0x48, i2s_reg_base + SADIV);
break;
case 11025:
writel(0x34, i2s_reg_base + SADIV);
break;
case 16000:
writel(0x24, i2s_reg_base + SADIV);
break;
case 22050:
writel(0x1a, i2s_reg_base + SADIV);
break;
case 44100:
writel(0xd, i2s_reg_base + SADIV);
break;
case 48000:
writel(0xc, i2s_reg_base + SADIV);
break;
case 96000: /* not in manual and possibly slightly inaccurate */
writel(0x6, i2s_reg_base + SADIV);
break;
}
return 0;
}
static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
writel(readl(i2s_reg_base + SACR1) & (~SACR1_DRPL), i2s_reg_base + SACR1);
else
writel(readl(i2s_reg_base + SACR1) & (~SACR1_DREC), i2s_reg_base + SACR1);
writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0);
break;
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
default:
ret = -EINVAL;
}
return ret;
}
static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
writel(readl(i2s_reg_base + SACR1) | (SACR1_DRPL), i2s_reg_base + SACR1);
writel(readl(i2s_reg_base + SAIMR) & (~SAIMR_TFS), i2s_reg_base + SAIMR);
} else {
writel(readl(i2s_reg_base + SACR1) | (SACR1_DREC), i2s_reg_base + SACR1);
writel(readl(i2s_reg_base + SAIMR) & (~SAIMR_RFS), i2s_reg_base + SAIMR);
}
if ((readl(i2s_reg_base + SACR1) & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
pxa_i2s_wait();
if (clk_ena) {
clk_disable_unprepare(clk_i2s);
clk_ena = 0;
}
}
}
#ifdef CONFIG_PM
static int pxa2xx_soc_pcm_suspend(struct snd_soc_component *component)
{
/* store registers */
pxa_i2s.sacr0 = readl(i2s_reg_base + SACR0);
pxa_i2s.sacr1 = readl(i2s_reg_base + SACR1);
pxa_i2s.saimr = readl(i2s_reg_base + SAIMR);
pxa_i2s.sadiv = readl(i2s_reg_base + SADIV);
/* deactivate link */
writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
pxa_i2s_wait();
return 0;
}
static int pxa2xx_soc_pcm_resume(struct snd_soc_component *component)
{
pxa_i2s_wait();
writel(pxa_i2s.sacr0 & ~SACR0_ENB, i2s_reg_base + SACR0);
writel(pxa_i2s.sacr1, i2s_reg_base + SACR1);
writel(pxa_i2s.saimr, i2s_reg_base + SAIMR);
writel(pxa_i2s.sadiv, i2s_reg_base + SADIV);
writel(pxa_i2s.sacr0, i2s_reg_base + SACR0);
return 0;
}
#else
#define pxa2xx_soc_pcm_suspend NULL
#define pxa2xx_soc_pcm_resume NULL
#endif
static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
{
clk_i2s = clk_get(dai->dev, "I2SCLK");
if (IS_ERR(clk_i2s))
return PTR_ERR(clk_i2s);
/*
* PXA Developer's Manual:
* If SACR0[ENB] is toggled in the middle of a normal operation,
* the SACR0[RST] bit must also be set and cleared to reset all
* I2S controller registers.
*/
writel(SACR0_RST, i2s_reg_base + SACR0);
writel(0, i2s_reg_base + SACR0);
/* Make sure RPL and REC are disabled */
writel(SACR1_DRPL | SACR1_DREC, i2s_reg_base + SACR1);
/* Along with FIFO servicing */
writel(readl(i2s_reg_base + SAIMR) & (~(SAIMR_RFS | SAIMR_TFS)), i2s_reg_base + SAIMR);
snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
&pxa2xx_i2s_pcm_stereo_in);
return 0;
}
static int pxa2xx_i2s_remove(struct snd_soc_dai *dai)
{
clk_put(clk_i2s);
clk_i2s = ERR_PTR(-ENOENT);
return 0;
}
#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
.probe = pxa2xx_i2s_probe,
.remove = pxa2xx_i2s_remove,
.startup = pxa2xx_i2s_startup,
.shutdown = pxa2xx_i2s_shutdown,
.trigger = pxa2xx_i2s_trigger,
.hw_params = pxa2xx_i2s_hw_params,
.set_fmt = pxa2xx_i2s_set_dai_fmt,
.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
};
static struct snd_soc_dai_driver pxa_i2s_dai = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = PXA2XX_I2S_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = PXA2XX_I2S_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &pxa_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver pxa_i2s_component = {
.name = "pxa-i2s",
.pcm_construct = pxa2xx_soc_pcm_new,
.open = pxa2xx_soc_pcm_open,
.close = pxa2xx_soc_pcm_close,
.hw_params = pxa2xx_soc_pcm_hw_params,
.prepare = pxa2xx_soc_pcm_prepare,
.trigger = pxa2xx_soc_pcm_trigger,
.pointer = pxa2xx_soc_pcm_pointer,
.suspend = pxa2xx_soc_pcm_suspend,
.resume = pxa2xx_soc_pcm_resume,
.legacy_dai_naming = 1,
};
static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
{
struct resource *res;
i2s_reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(i2s_reg_base))
return PTR_ERR(i2s_reg_base);
pxa2xx_i2s_pcm_stereo_out.addr = res->start + SADR;
pxa2xx_i2s_pcm_stereo_in.addr = res->start + SADR;
return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
&pxa_i2s_dai, 1);
}
static struct platform_driver pxa2xx_i2s_driver = {
.probe = pxa2xx_i2s_drv_probe,
.driver = {
.name = "pxa2xx-i2s",
},
};
static int __init pxa2xx_i2s_init(void)
{
clk_i2s = ERR_PTR(-ENOENT);
return platform_driver_register(&pxa2xx_i2s_driver);
}
static void __exit pxa2xx_i2s_exit(void)
{
platform_driver_unregister(&pxa2xx_i2s_driver);
}
module_init(pxa2xx_i2s_init);
module_exit(pxa2xx_i2s_exit);
/* Module information */
MODULE_AUTHOR("Liam Girdwood, [email protected]");
MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-i2s");
| linux-master | sound/soc/pxa/pxa2xx-i2s.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pxa-ssp.c -- ALSA Soc Audio Layer
*
* Copyright 2005,2008 Wolfson Microelectronics PLC.
* Author: Liam Girdwood
* Mark Brown <[email protected]>
*
* TODO:
* o Test network mode for > 16bit sample size
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/pxa2xx_ssp.h>
#include <linux/of.h>
#include <linux/dmaengine.h>
#include <asm/irq.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
#include "pxa-ssp.h"
/*
* SSP audio private data
*/
struct ssp_priv {
struct ssp_device *ssp;
struct clk *extclk;
unsigned long ssp_clk;
unsigned int sysclk;
unsigned int dai_fmt;
unsigned int configured_dai_fmt;
#ifdef CONFIG_PM
uint32_t cr0;
uint32_t cr1;
uint32_t to;
uint32_t psp;
#endif
};
static void dump_registers(struct ssp_device *ssp)
{
dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
pxa_ssp_read_reg(ssp, SSTO));
dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
pxa_ssp_read_reg(ssp, SSACD));
}
static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
int out, struct snd_dmaengine_dai_dma_data *dma)
{
dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
DMA_SLAVE_BUSWIDTH_2_BYTES;
dma->maxburst = 16;
dma->addr = ssp->phys_base + SSDR;
}
static int pxa_ssp_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
struct snd_dmaengine_dai_dma_data *dma;
int ret = 0;
if (!snd_soc_dai_active(cpu_dai)) {
clk_prepare_enable(ssp->clk);
pxa_ssp_disable(ssp);
}
clk_prepare_enable(priv->extclk);
dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
if (!dma)
return -ENOMEM;
dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
"tx" : "rx";
snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
return ret;
}
static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
if (!snd_soc_dai_active(cpu_dai)) {
pxa_ssp_disable(ssp);
clk_disable_unprepare(ssp->clk);
}
clk_disable_unprepare(priv->extclk);
kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
}
#ifdef CONFIG_PM
static int pxa_ssp_suspend(struct snd_soc_component *component)
{
struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
struct ssp_device *ssp = priv->ssp;
if (!snd_soc_component_active(component))
clk_prepare_enable(ssp->clk);
priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
priv->to = __raw_readl(ssp->mmio_base + SSTO);
priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
pxa_ssp_disable(ssp);
clk_disable_unprepare(ssp->clk);
return 0;
}
static int pxa_ssp_resume(struct snd_soc_component *component)
{
struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
struct ssp_device *ssp = priv->ssp;
uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
clk_prepare_enable(ssp->clk);
__raw_writel(sssr, ssp->mmio_base + SSSR);
__raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
__raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
__raw_writel(priv->to, ssp->mmio_base + SSTO);
__raw_writel(priv->psp, ssp->mmio_base + SSPSP);
if (snd_soc_component_active(component))
pxa_ssp_enable(ssp);
else
clk_disable_unprepare(ssp->clk);
return 0;
}
#else
#define pxa_ssp_suspend NULL
#define pxa_ssp_resume NULL
#endif
/*
* ssp_set_clkdiv - set SSP clock divider
* @div: serial clock rate divider
*/
static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
{
u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
if (ssp->type == PXA25x_SSP) {
sscr0 &= ~0x0000ff00;
sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
} else {
sscr0 &= ~0x000fff00;
sscr0 |= (div - 1) << 8; /* 1..4096 */
}
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
}
/*
* Set the SSP ports SYSCLK.
*/
static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
if (priv->extclk) {
int ret;
/*
* For DT based boards, if an extclk is given, use it
* here and configure PXA_SSP_CLK_EXT.
*/
ret = clk_set_rate(priv->extclk, freq);
if (ret < 0)
return ret;
clk_id = PXA_SSP_CLK_EXT;
}
dev_dbg(ssp->dev,
"pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
cpu_dai->id, clk_id, freq);
switch (clk_id) {
case PXA_SSP_CLK_NET_PLL:
sscr0 |= SSCR0_MOD;
break;
case PXA_SSP_CLK_PLL:
/* Internal PLL is fixed */
if (ssp->type == PXA25x_SSP)
priv->sysclk = 1843200;
else
priv->sysclk = 13000000;
break;
case PXA_SSP_CLK_EXT:
priv->sysclk = freq;
sscr0 |= SSCR0_ECS;
break;
case PXA_SSP_CLK_NET:
priv->sysclk = freq;
sscr0 |= SSCR0_NCS | SSCR0_MOD;
break;
case PXA_SSP_CLK_AUDIO:
priv->sysclk = 0;
pxa_ssp_set_scr(ssp, 1);
sscr0 |= SSCR0_ACS;
break;
default:
return -ENODEV;
}
/* The SSP clock must be disabled when changing SSP clock mode
* on PXA2xx. On PXA3xx it must be enabled when doing so. */
if (ssp->type != PXA3xx_SSP)
clk_disable_unprepare(ssp->clk);
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
if (ssp->type != PXA3xx_SSP)
clk_prepare_enable(ssp->clk);
return 0;
}
/*
* Configure the PLL frequency pxa27x and (afaik - pxa320 only)
*/
static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
{
struct ssp_device *ssp = priv->ssp;
u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
if (ssp->type == PXA3xx_SSP)
pxa_ssp_write_reg(ssp, SSACDD, 0);
switch (freq) {
case 5622000:
break;
case 11345000:
ssacd |= (0x1 << 4);
break;
case 12235000:
ssacd |= (0x2 << 4);
break;
case 14857000:
ssacd |= (0x3 << 4);
break;
case 32842000:
ssacd |= (0x4 << 4);
break;
case 48000000:
ssacd |= (0x5 << 4);
break;
case 0:
/* Disable */
break;
default:
/* PXA3xx has a clock ditherer which can be used to generate
* a wider range of frequencies - calculate a value for it.
*/
if (ssp->type == PXA3xx_SSP) {
u32 val;
u64 tmp = 19968;
tmp *= 1000000;
do_div(tmp, freq);
val = tmp;
val = (val << 16) | 64;
pxa_ssp_write_reg(ssp, SSACDD, val);
ssacd |= (0x6 << 4);
dev_dbg(ssp->dev,
"Using SSACDD %x to supply %uHz\n",
val, freq);
break;
}
return -EINVAL;
}
pxa_ssp_write_reg(ssp, SSACD, ssacd);
return 0;
}
/*
* Set the active slots in TDM/Network mode
*/
static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
u32 sscr0;
sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
/* set slot width */
if (slot_width > 16)
sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
else
sscr0 |= SSCR0_DataSize(slot_width);
if (slots > 1) {
/* enable network mode */
sscr0 |= SSCR0_MOD;
/* set number of active slots */
sscr0 |= SSCR0_SlotsPerFrm(slots);
/* set active slot mask */
pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
}
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
return 0;
}
/*
* Tristate the SSP DAI lines
*/
static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
int tristate)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
u32 sscr1;
sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
if (tristate)
sscr1 &= ~SSCR1_TTE;
else
sscr1 |= SSCR1_TTE;
pxa_ssp_write_reg(ssp, SSCR1, sscr1);
return 0;
}
static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
case SND_SOC_DAIFMT_BC_FP:
case SND_SOC_DAIFMT_BP_FP:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
case SND_SOC_DAIFMT_NB_IF:
case SND_SOC_DAIFMT_IB_IF:
case SND_SOC_DAIFMT_IB_NF:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
break;
default:
return -EINVAL;
}
/* Settings will be applied in hw_params() */
priv->dai_fmt = fmt;
return 0;
}
/*
* Set up the SSP DAI format.
* The SSP Port must be inactive before calling this function as the
* physical interface format is changed.
*/
static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
{
struct ssp_device *ssp = priv->ssp;
u32 sscr0, sscr1, sspsp, scfr;
/* check if we need to change anything at all */
if (priv->configured_dai_fmt == priv->dai_fmt)
return 0;
/* reset port settings */
sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
~(SSCR0_PSP | SSCR0_MOD);
sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
~(SSPSP_SFRMP | SSPSP_SCMODE(3));
sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
switch (priv->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
break;
case SND_SOC_DAIFMT_BC_FP:
sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
break;
case SND_SOC_DAIFMT_BP_FP:
break;
default:
return -EINVAL;
}
switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
sspsp |= SSPSP_SFRMP;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
case SND_SOC_DAIFMT_IB_IF:
sspsp |= SSPSP_SCMODE(2);
break;
case SND_SOC_DAIFMT_IB_NF:
sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
break;
default:
return -EINVAL;
}
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
sscr0 |= SSCR0_PSP;
sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
/* See hw_params() */
break;
case SND_SOC_DAIFMT_DSP_A:
sspsp |= SSPSP_FSRT;
fallthrough;
case SND_SOC_DAIFMT_DSP_B:
sscr0 |= SSCR0_MOD | SSCR0_PSP;
sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
break;
default:
return -EINVAL;
}
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
pxa_ssp_write_reg(ssp, SSCR1, sscr1);
pxa_ssp_write_reg(ssp, SSPSP, sspsp);
switch (priv->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
case SND_SOC_DAIFMT_BC_FP:
scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
pxa_ssp_write_reg(ssp, SSCR1, scfr);
while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
cpu_relax();
break;
}
dump_registers(ssp);
/* Since we are configuring the timings for the format by hand
* we have to defer some things until hw_params() where we
* know parameters like the sample size.
*/
priv->configured_dai_fmt = priv->dai_fmt;
return 0;
}
struct pxa_ssp_clock_mode {
int rate;
int pll;
u8 acds;
u8 scdb;
};
static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
{ .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
{ .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
{ .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
{ .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
{ .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
{ .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
{ .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
{}
};
/*
* Set the SSP audio DMA parameters and sample size.
* Can be called multiple times by oss emulation.
*/
static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
int chn = params_channels(params);
u32 sscr0, sspsp;
int width = snd_pcm_format_physical_width(params_format(params));
int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
struct snd_dmaengine_dai_dma_data *dma_data;
int rate = params_rate(params);
int bclk = rate * chn * (width / 8);
int ret;
dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
/* Network mode with one active slot (ttsa == 1) can be used
* to force 16-bit frame width on the wire (for S16_LE), even
* with two channels. Use 16-bit DMA transfers for this case.
*/
pxa_ssp_set_dma_params(ssp,
((chn == 2) && (ttsa != 1)) || (width == 32),
substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
/* we can only change the settings if the port is not in use */
if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
return 0;
ret = pxa_ssp_configure_dai_fmt(priv);
if (ret < 0)
return ret;
/* clear selected SSP bits */
sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
if (ssp->type == PXA3xx_SSP)
sscr0 |= SSCR0_FPCKE;
sscr0 |= SSCR0_DataSize(16);
break;
case SNDRV_PCM_FORMAT_S24_LE:
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
break;
case SNDRV_PCM_FORMAT_S32_LE:
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
break;
}
pxa_ssp_write_reg(ssp, SSCR0, sscr0);
if (sscr0 & SSCR0_ACS) {
ret = pxa_ssp_set_pll(priv, bclk);
/*
* If we were able to generate the bclk directly,
* all is fine. Otherwise, look up the closest rate
* from the table and also set the dividers.
*/
if (ret < 0) {
const struct pxa_ssp_clock_mode *m;
int ssacd;
for (m = pxa_ssp_clock_modes; m->rate; m++) {
if (m->rate == rate)
break;
}
if (!m->rate)
return -EINVAL;
ret = pxa_ssp_set_pll(priv, bclk);
if (ret < 0)
return ret;
ssacd = pxa_ssp_read_reg(ssp, SSACD);
ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
ssacd |= SSACD_ACDS(m->acds);
ssacd |= m->scdb;
pxa_ssp_write_reg(ssp, SSACD, ssacd);
}
} else if (sscr0 & SSCR0_ECS) {
/*
* For setups with external clocking, the PLL and its diviers
* are not active. Instead, the SCR bits in SSCR0 can be used
* to divide the clock.
*/
pxa_ssp_set_scr(ssp, bclk / rate);
}
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
sspsp = pxa_ssp_read_reg(ssp, SSPSP);
if (((priv->sysclk / bclk) == 64) && (width == 16)) {
/* This is a special case where the bitclk is 64fs
* and we're not dealing with 2*32 bits of audio
* samples.
*
* The SSP values used for that are all found out by
* trying and failing a lot; some of the registers
* needed for that mode are only available on PXA3xx.
*/
if (ssp->type != PXA3xx_SSP)
return -EINVAL;
sspsp |= SSPSP_SFRMWDTH(width * 2);
sspsp |= SSPSP_SFRMDLY(width * 4);
sspsp |= SSPSP_EDMYSTOP(3);
sspsp |= SSPSP_DMYSTOP(3);
sspsp |= SSPSP_DMYSTRT(1);
} else {
/* The frame width is the width the LRCLK is
* asserted for; the delay is expressed in
* half cycle units. We need the extra cycle
* because the data starts clocking out one BCLK
* after LRCLK changes polarity.
*/
sspsp |= SSPSP_SFRMWDTH(width + 1);
sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
sspsp |= SSPSP_DMYSTRT(1);
}
pxa_ssp_write_reg(ssp, SSPSP, sspsp);
break;
default:
break;
}
/* When we use a network mode, we always require TDM slots
* - complain loudly and fail if they've not been set up yet.
*/
if ((sscr0 & SSCR0_MOD) && !ttsa) {
dev_err(ssp->dev, "No TDM timeslot configured\n");
return -EINVAL;
}
dump_registers(ssp);
return 0;
}
static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
struct ssp_device *ssp, int value)
{
uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
if (value && (sscr0 & SSCR0_SSE))
pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (value)
sscr1 |= SSCR1_TSRE;
else
sscr1 &= ~SSCR1_TSRE;
} else {
if (value)
sscr1 |= SSCR1_RSRE;
else
sscr1 &= ~SSCR1_RSRE;
}
pxa_ssp_write_reg(ssp, SSCR1, sscr1);
if (value) {
pxa_ssp_write_reg(ssp, SSSR, sssr);
pxa_ssp_write_reg(ssp, SSPSP, sspsp);
pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
}
}
static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
int ret = 0;
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
int val;
switch (cmd) {
case SNDRV_PCM_TRIGGER_RESUME:
pxa_ssp_enable(ssp);
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pxa_ssp_set_running_bit(substream, ssp, 1);
val = pxa_ssp_read_reg(ssp, SSSR);
pxa_ssp_write_reg(ssp, SSSR, val);
break;
case SNDRV_PCM_TRIGGER_START:
pxa_ssp_set_running_bit(substream, ssp, 1);
break;
case SNDRV_PCM_TRIGGER_STOP:
pxa_ssp_set_running_bit(substream, ssp, 0);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
pxa_ssp_disable(ssp);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
pxa_ssp_set_running_bit(substream, ssp, 0);
break;
default:
ret = -EINVAL;
}
dump_registers(ssp);
return ret;
}
static int pxa_ssp_probe(struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct ssp_priv *priv;
int ret;
priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (dev->of_node) {
struct device_node *ssp_handle;
ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
if (!ssp_handle) {
dev_err(dev, "unable to get 'port' phandle\n");
ret = -ENODEV;
goto err_priv;
}
priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
if (priv->ssp == NULL) {
ret = -ENODEV;
goto err_priv;
}
priv->extclk = devm_clk_get(dev, "extclk");
if (IS_ERR(priv->extclk)) {
ret = PTR_ERR(priv->extclk);
if (ret == -EPROBE_DEFER)
return ret;
priv->extclk = NULL;
}
} else {
priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
if (priv->ssp == NULL) {
ret = -ENODEV;
goto err_priv;
}
}
priv->dai_fmt = (unsigned int) -1;
snd_soc_dai_set_drvdata(dai, priv);
return 0;
err_priv:
kfree(priv);
return ret;
}
static int pxa_ssp_remove(struct snd_soc_dai *dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
pxa_ssp_free(priv->ssp);
kfree(priv);
return 0;
}
#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
.probe = pxa_ssp_probe,
.remove = pxa_ssp_remove,
.startup = pxa_ssp_startup,
.shutdown = pxa_ssp_shutdown,
.trigger = pxa_ssp_trigger,
.hw_params = pxa_ssp_hw_params,
.set_sysclk = pxa_ssp_set_dai_sysclk,
.set_fmt = pxa_ssp_set_dai_fmt,
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
.set_tristate = pxa_ssp_set_dai_tristate,
};
static struct snd_soc_dai_driver pxa_ssp_dai = {
.playback = {
.channels_min = 1,
.channels_max = 8,
.rates = PXA_SSP_RATES,
.formats = PXA_SSP_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
.rates = PXA_SSP_RATES,
.formats = PXA_SSP_FORMATS,
},
.ops = &pxa_ssp_dai_ops,
};
static const struct snd_soc_component_driver pxa_ssp_component = {
.name = "pxa-ssp",
.pcm_construct = pxa2xx_soc_pcm_new,
.open = pxa2xx_soc_pcm_open,
.close = pxa2xx_soc_pcm_close,
.hw_params = pxa2xx_soc_pcm_hw_params,
.prepare = pxa2xx_soc_pcm_prepare,
.trigger = pxa2xx_soc_pcm_trigger,
.pointer = pxa2xx_soc_pcm_pointer,
.suspend = pxa_ssp_suspend,
.resume = pxa_ssp_resume,
.legacy_dai_naming = 1,
};
#ifdef CONFIG_OF
static const struct of_device_id pxa_ssp_of_ids[] = {
{ .compatible = "mrvl,pxa-ssp-dai" },
{}
};
MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
#endif
static int asoc_ssp_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
&pxa_ssp_dai, 1);
}
static struct platform_driver asoc_ssp_driver = {
.driver = {
.name = "pxa-ssp-dai",
.of_match_table = of_match_ptr(pxa_ssp_of_ids),
},
.probe = asoc_ssp_probe,
};
module_platform_driver(asoc_ssp_driver);
/* Module information */
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-ssp-dai");
| linux-master | sound/soc/pxa/pxa-ssp.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver
*
* Copyright 2008-12 Wolfson Microelectronics PLC.
*
* Notes:
* The WM8580 is a multichannel codec with S/PDIF support, featuring six
* DAC channels and two ADC channels.
*
* The WM8581 is a multichannel codec with S/PDIF support, featuring eight
* DAC channels and two ADC channels.
*
* Currently only the primary audio interface is supported - S/PDIF and
* the secondary audio interfaces are not.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include <asm/div64.h>
#include "wm8580.h"
/* WM8580 register space */
#define WM8580_PLLA1 0x00
#define WM8580_PLLA2 0x01
#define WM8580_PLLA3 0x02
#define WM8580_PLLA4 0x03
#define WM8580_PLLB1 0x04
#define WM8580_PLLB2 0x05
#define WM8580_PLLB3 0x06
#define WM8580_PLLB4 0x07
#define WM8580_CLKSEL 0x08
#define WM8580_PAIF1 0x09
#define WM8580_PAIF2 0x0A
#define WM8580_SAIF1 0x0B
#define WM8580_PAIF3 0x0C
#define WM8580_PAIF4 0x0D
#define WM8580_SAIF2 0x0E
#define WM8580_DAC_CONTROL1 0x0F
#define WM8580_DAC_CONTROL2 0x10
#define WM8580_DAC_CONTROL3 0x11
#define WM8580_DAC_CONTROL4 0x12
#define WM8580_DAC_CONTROL5 0x13
#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
#define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A
#define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B
#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
#define WM8580_ADC_CONTROL1 0x1D
#define WM8580_SPDTXCHAN0 0x1E
#define WM8580_SPDTXCHAN1 0x1F
#define WM8580_SPDTXCHAN2 0x20
#define WM8580_SPDTXCHAN3 0x21
#define WM8580_SPDTXCHAN4 0x22
#define WM8580_SPDTXCHAN5 0x23
#define WM8580_SPDMODE 0x24
#define WM8580_INTMASK 0x25
#define WM8580_GPO1 0x26
#define WM8580_GPO2 0x27
#define WM8580_GPO3 0x28
#define WM8580_GPO4 0x29
#define WM8580_GPO5 0x2A
#define WM8580_INTSTAT 0x2B
#define WM8580_SPDRXCHAN1 0x2C
#define WM8580_SPDRXCHAN2 0x2D
#define WM8580_SPDRXCHAN3 0x2E
#define WM8580_SPDRXCHAN4 0x2F
#define WM8580_SPDRXCHAN5 0x30
#define WM8580_SPDSTAT 0x31
#define WM8580_PWRDN1 0x32
#define WM8580_PWRDN2 0x33
#define WM8580_READBACK 0x34
#define WM8580_RESET 0x35
#define WM8580_MAX_REGISTER 0x35
#define WM8580_DACOSR 0x40
/* PLLB4 (register 7h) */
#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
/* CLKSEL (register 8h) */
#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
/* AIF control 1 (registers 9h-bh) */
#define WM8580_AIF_RATE_MASK 0x7
#define WM8580_AIF_BCLKSEL_MASK 0x18
#define WM8580_AIF_MS 0x20
#define WM8580_AIF_CLKSRC_MASK 0xc0
#define WM8580_AIF_CLKSRC_PLLA 0x40
#define WM8580_AIF_CLKSRC_PLLB 0x40
#define WM8580_AIF_CLKSRC_MCLK 0xc0
/* AIF control 2 (registers ch-eh) */
#define WM8580_AIF_FMT_MASK 0x03
#define WM8580_AIF_FMT_RIGHTJ 0x00
#define WM8580_AIF_FMT_LEFTJ 0x01
#define WM8580_AIF_FMT_I2S 0x02
#define WM8580_AIF_FMT_DSP 0x03
#define WM8580_AIF_LENGTH_MASK 0x0c
#define WM8580_AIF_LENGTH_16 0x00
#define WM8580_AIF_LENGTH_20 0x04
#define WM8580_AIF_LENGTH_24 0x08
#define WM8580_AIF_LENGTH_32 0x0c
#define WM8580_AIF_LRP 0x10
#define WM8580_AIF_BCP 0x20
/* Powerdown Register 1 (register 32h) */
#define WM8580_PWRDN1_PWDN 0x001
#define WM8580_PWRDN1_ALLDACPD 0x040
/* Powerdown Register 2 (register 33h) */
#define WM8580_PWRDN2_OSSCPD 0x001
#define WM8580_PWRDN2_PLLAPD 0x002
#define WM8580_PWRDN2_PLLBPD 0x004
#define WM8580_PWRDN2_SPDIFPD 0x008
#define WM8580_PWRDN2_SPDIFTXD 0x010
#define WM8580_PWRDN2_SPDIFRXD 0x020
#define WM8580_DAC_CONTROL5_MUTEALL 0x10
/*
* wm8580 register cache
* We can't read the WM8580 register space when we
* are using 2 wire for device control, so we cache them instead.
*/
static const struct reg_default wm8580_reg_defaults[] = {
{ 0, 0x0121 },
{ 1, 0x017e },
{ 2, 0x007d },
{ 3, 0x0014 },
{ 4, 0x0121 },
{ 5, 0x017e },
{ 6, 0x007d },
{ 7, 0x0194 },
{ 8, 0x0010 },
{ 9, 0x0002 },
{ 10, 0x0002 },
{ 11, 0x00c2 },
{ 12, 0x0182 },
{ 13, 0x0082 },
{ 14, 0x000a },
{ 15, 0x0024 },
{ 16, 0x0009 },
{ 17, 0x0000 },
{ 18, 0x00ff },
{ 19, 0x0000 },
{ 20, 0x00ff },
{ 21, 0x00ff },
{ 22, 0x00ff },
{ 23, 0x00ff },
{ 24, 0x00ff },
{ 25, 0x00ff },
{ 26, 0x00ff },
{ 27, 0x00ff },
{ 28, 0x01f0 },
{ 29, 0x0040 },
{ 30, 0x0000 },
{ 31, 0x0000 },
{ 32, 0x0000 },
{ 33, 0x0000 },
{ 34, 0x0031 },
{ 35, 0x000b },
{ 36, 0x0039 },
{ 37, 0x0000 },
{ 38, 0x0010 },
{ 39, 0x0032 },
{ 40, 0x0054 },
{ 41, 0x0076 },
{ 42, 0x0098 },
{ 43, 0x0000 },
{ 44, 0x0000 },
{ 45, 0x0000 },
{ 46, 0x0000 },
{ 47, 0x0000 },
{ 48, 0x0000 },
{ 49, 0x0000 },
{ 50, 0x005e },
{ 51, 0x003e },
{ 52, 0x0000 },
};
static bool wm8580_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8580_RESET:
return true;
default:
return false;
}
}
struct pll_state {
unsigned int in;
unsigned int out;
};
#define WM8580_NUM_SUPPLIES 3
static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
"AVDD",
"DVDD",
"PVDD",
};
struct wm8580_driver_data {
int num_dacs;
};
/* codec private data */
struct wm8580_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
struct pll_state a;
struct pll_state b;
const struct wm8580_driver_data *drvdata;
int sysclk[2];
};
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
int ret;
/* Clear the register cache VU so we write without VU set */
regcache_cache_only(wm8580->regmap, true);
regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
regcache_cache_only(wm8580->regmap, false);
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
/* Now write again with the volume update bit set */
snd_soc_component_update_bits(component, reg, 0x100, 0x100);
snd_soc_component_update_bits(component, reg2, 0x100, 0x100);
return 0;
}
static const struct snd_kcontrol_new wm8580_snd_controls[] = {
SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
WM8580_DIGITAL_ATTENUATION_DACL1,
WM8580_DIGITAL_ATTENUATION_DACR1,
0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
WM8580_DIGITAL_ATTENUATION_DACL2,
WM8580_DIGITAL_ATTENUATION_DACR2,
0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
WM8580_DIGITAL_ATTENUATION_DACL3,
WM8580_DIGITAL_ATTENUATION_DACR3,
0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
};
static const struct snd_kcontrol_new wm8581_snd_controls[] = {
SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
WM8581_DIGITAL_ATTENUATION_DACL4,
WM8581_DIGITAL_ATTENUATION_DACR4,
0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0),
SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
};
static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
SND_SOC_DAPM_OUTPUT("VOUT1L"),
SND_SOC_DAPM_OUTPUT("VOUT1R"),
SND_SOC_DAPM_OUTPUT("VOUT2L"),
SND_SOC_DAPM_OUTPUT("VOUT2R"),
SND_SOC_DAPM_OUTPUT("VOUT3L"),
SND_SOC_DAPM_OUTPUT("VOUT3R"),
SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
};
static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
SND_SOC_DAPM_OUTPUT("VOUT4L"),
SND_SOC_DAPM_OUTPUT("VOUT4R"),
};
static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
{ "VOUT1L", NULL, "DAC1" },
{ "VOUT1R", NULL, "DAC1" },
{ "VOUT2L", NULL, "DAC2" },
{ "VOUT2R", NULL, "DAC2" },
{ "VOUT3L", NULL, "DAC3" },
{ "VOUT3R", NULL, "DAC3" },
{ "ADC", NULL, "AINL" },
{ "ADC", NULL, "AINR" },
};
static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
{ "VOUT4L", NULL, "DAC4" },
{ "VOUT4R", NULL, "DAC4" },
};
/* PLL divisors */
struct _pll_div {
u32 prescale:1;
u32 postscale:1;
u32 freqmode:2;
u32 n:4;
u32 k:24;
};
/* The size in bits of the pll divide */
#define FIXED_PLL_SIZE (1 << 22)
/* PLL rate to output rate divisions */
static struct {
unsigned int div;
unsigned int freqmode;
unsigned int postscale;
} post_table[] = {
{ 2, 0, 0 },
{ 4, 0, 1 },
{ 4, 1, 0 },
{ 8, 1, 1 },
{ 8, 2, 0 },
{ 16, 2, 1 },
{ 12, 3, 0 },
{ 24, 3, 1 }
};
static int pll_factors(struct _pll_div *pll_div, unsigned int target,
unsigned int source)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod;
int i;
pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
/* Scale the output frequency up; the PLL should run in the
* region of 90-100MHz.
*/
for (i = 0; i < ARRAY_SIZE(post_table); i++) {
if (target * post_table[i].div >= 90000000 &&
target * post_table[i].div <= 100000000) {
pll_div->freqmode = post_table[i].freqmode;
pll_div->postscale = post_table[i].postscale;
target *= post_table[i].div;
break;
}
}
if (i == ARRAY_SIZE(post_table)) {
printk(KERN_ERR "wm8580: Unable to scale output frequency "
"%u\n", target);
return -EINVAL;
}
Ndiv = target / source;
if (Ndiv < 5) {
source /= 2;
pll_div->prescale = 1;
Ndiv = target / source;
} else
pll_div->prescale = 0;
if ((Ndiv < 5) || (Ndiv > 13)) {
printk(KERN_ERR
"WM8580 N=%u outside supported range\n", Ndiv);
return -EINVAL;
}
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
pll_div->k = K;
pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
pll_div->postscale);
return 0;
}
static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
int offset;
struct snd_soc_component *component = codec_dai->component;
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
struct pll_state *state;
struct _pll_div pll_div;
unsigned int reg;
unsigned int pwr_mask;
int ret;
/* GCC isn't able to work out the ifs below for initialising/using
* pll_div so suppress warnings.
*/
memset(&pll_div, 0, sizeof(pll_div));
switch (pll_id) {
case WM8580_PLLA:
state = &wm8580->a;
offset = 0;
pwr_mask = WM8580_PWRDN2_PLLAPD;
break;
case WM8580_PLLB:
state = &wm8580->b;
offset = 4;
pwr_mask = WM8580_PWRDN2_PLLBPD;
break;
default:
return -ENODEV;
}
if (freq_in && freq_out) {
ret = pll_factors(&pll_div, freq_out, freq_in);
if (ret != 0)
return ret;
}
state->in = freq_in;
state->out = freq_out;
/* Always disable the PLL - it is not safe to leave it running
* while reprogramming it.
*/
snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, pwr_mask);
if (!freq_in || !freq_out)
return 0;
snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8580_PLLA3 + offset,
(pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
reg = snd_soc_component_read(component, WM8580_PLLA4 + offset);
reg &= ~0x1b;
reg |= pll_div.prescale | pll_div.postscale << 1 |
pll_div.freqmode << 3;
snd_soc_component_write(component, WM8580_PLLA4 + offset, reg);
/* All done, turn it on */
snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, 0);
return 0;
}
static const int wm8580_sysclk_ratios[] = {
128, 192, 256, 384, 512, 768, 1152,
};
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
u16 paifa = 0;
u16 paifb = 0;
int i, ratio, osr;
/* bit size */
switch (params_width(params)) {
case 16:
paifa |= 0x8;
break;
case 20:
paifa |= 0x0;
paifb |= WM8580_AIF_LENGTH_20;
break;
case 24:
paifa |= 0x0;
paifb |= WM8580_AIF_LENGTH_24;
break;
case 32:
paifa |= 0x0;
paifb |= WM8580_AIF_LENGTH_32;
break;
default:
return -EINVAL;
}
/* Look up the SYSCLK ratio; accept only exact matches */
ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
if (ratio == wm8580_sysclk_ratios[i])
break;
if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
dev_err(component->dev, "Invalid clock ratio %d/%d\n",
wm8580->sysclk[dai->driver->id], params_rate(params));
return -EINVAL;
}
paifa |= i;
dev_dbg(component->dev, "Running at %dfs with %dHz clock\n",
wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (ratio) {
case 128:
case 192:
osr = WM8580_DACOSR;
dev_dbg(component->dev, "Selecting 64x OSR\n");
break;
default:
osr = 0;
dev_dbg(component->dev, "Selecting 128x OSR\n");
break;
}
snd_soc_component_update_bits(component, WM8580_PAIF3, WM8580_DACOSR, osr);
}
snd_soc_component_update_bits(component, WM8580_PAIF1 + dai->driver->id,
WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
paifa);
snd_soc_component_update_bits(component, WM8580_PAIF3 + dai->driver->id,
WM8580_AIF_LENGTH_MASK, paifb);
return 0;
}
static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int aifa;
unsigned int aifb;
int can_invert_lrclk;
aifa = snd_soc_component_read(component, WM8580_PAIF1 + codec_dai->driver->id);
aifb = snd_soc_component_read(component, WM8580_PAIF3 + codec_dai->driver->id);
aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
aifa &= ~WM8580_AIF_MS;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aifa |= WM8580_AIF_MS;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
can_invert_lrclk = 1;
aifb |= WM8580_AIF_FMT_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
can_invert_lrclk = 1;
aifb |= WM8580_AIF_FMT_RIGHTJ;
break;
case SND_SOC_DAIFMT_LEFT_J:
can_invert_lrclk = 1;
aifb |= WM8580_AIF_FMT_LEFTJ;
break;
case SND_SOC_DAIFMT_DSP_A:
can_invert_lrclk = 0;
aifb |= WM8580_AIF_FMT_DSP;
break;
case SND_SOC_DAIFMT_DSP_B:
can_invert_lrclk = 0;
aifb |= WM8580_AIF_FMT_DSP;
aifb |= WM8580_AIF_LRP;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
if (!can_invert_lrclk)
return -EINVAL;
aifb |= WM8580_AIF_BCP;
aifb |= WM8580_AIF_LRP;
break;
case SND_SOC_DAIFMT_IB_NF:
aifb |= WM8580_AIF_BCP;
break;
case SND_SOC_DAIFMT_NB_IF:
if (!can_invert_lrclk)
return -EINVAL;
aifb |= WM8580_AIF_LRP;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8580_PAIF1 + codec_dai->driver->id, aifa);
snd_soc_component_write(component, WM8580_PAIF3 + codec_dai->driver->id, aifb);
return 0;
}
static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int reg;
switch (div_id) {
case WM8580_MCLK:
reg = snd_soc_component_read(component, WM8580_PLLB4);
reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
switch (div) {
case WM8580_CLKSRC_MCLK:
/* Input */
break;
case WM8580_CLKSRC_PLLA:
reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
break;
case WM8580_CLKSRC_PLLB:
reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
break;
case WM8580_CLKSRC_OSC:
reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8580_PLLB4, reg);
break;
case WM8580_CLKOUTSRC:
reg = snd_soc_component_read(component, WM8580_PLLB4);
reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
switch (div) {
case WM8580_CLKSRC_NONE:
break;
case WM8580_CLKSRC_PLLA:
reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
break;
case WM8580_CLKSRC_PLLB:
reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
break;
case WM8580_CLKSRC_OSC:
reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8580_PLLB4, reg);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
int ret, sel, sel_mask, sel_shift;
switch (dai->driver->id) {
case WM8580_DAI_PAIFRX:
sel_mask = 0x3;
sel_shift = 0;
break;
case WM8580_DAI_PAIFTX:
sel_mask = 0xc;
sel_shift = 2;
break;
default:
WARN(1, "Unknown DAI driver ID\n");
return -EINVAL;
}
switch (clk_id) {
case WM8580_CLKSRC_ADCMCLK:
if (dai->driver->id != WM8580_DAI_PAIFTX)
return -EINVAL;
sel = 0 << sel_shift;
break;
case WM8580_CLKSRC_PLLA:
sel = 1 << sel_shift;
break;
case WM8580_CLKSRC_PLLB:
sel = 2 << sel_shift;
break;
case WM8580_CLKSRC_MCLK:
sel = 3 << sel_shift;
break;
default:
dev_err(component->dev, "Unknown clock %d\n", clk_id);
return -EINVAL;
}
/* We really should validate PLL settings but not yet */
wm8580->sysclk[dai->driver->id] = freq;
ret = snd_soc_component_update_bits(component, WM8580_CLKSEL, sel_mask, sel);
if (ret < 0)
return ret;
return 0;
}
static int wm8580_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
unsigned int reg;
reg = snd_soc_component_read(component, WM8580_DAC_CONTROL5);
if (mute)
reg |= WM8580_DAC_CONTROL5_MUTEALL;
else
reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg);
return 0;
}
static int wm8580_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Power up and get individual control of the DACs */
snd_soc_component_update_bits(component, WM8580_PWRDN1,
WM8580_PWRDN1_PWDN |
WM8580_PWRDN1_ALLDACPD, 0);
/* Make VMID high impedance */
snd_soc_component_update_bits(component, WM8580_ADC_CONTROL1,
0x100, 0);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, WM8580_PWRDN1,
WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
break;
}
return 0;
}
static int wm8580_playback_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
}
#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
.startup = wm8580_playback_startup,
.set_sysclk = wm8580_set_sysclk,
.hw_params = wm8580_paif_hw_params,
.set_fmt = wm8580_set_paif_dai_fmt,
.set_clkdiv = wm8580_set_dai_clkdiv,
.set_pll = wm8580_set_dai_pll,
.mute_stream = wm8580_mute,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
.set_sysclk = wm8580_set_sysclk,
.hw_params = wm8580_paif_hw_params,
.set_fmt = wm8580_set_paif_dai_fmt,
.set_clkdiv = wm8580_set_dai_clkdiv,
.set_pll = wm8580_set_dai_pll,
};
static struct snd_soc_dai_driver wm8580_dai[] = {
{
.name = "wm8580-hifi-playback",
.id = WM8580_DAI_PAIFRX,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = WM8580_FORMATS,
},
.ops = &wm8580_dai_ops_playback,
},
{
.name = "wm8580-hifi-capture",
.id = WM8580_DAI_PAIFTX,
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = WM8580_FORMATS,
},
.ops = &wm8580_dai_ops_capture,
},
};
static int wm8580_probe(struct snd_soc_component *component)
{
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret = 0;
switch (wm8580->drvdata->num_dacs) {
case 4:
snd_soc_add_component_controls(component, wm8581_snd_controls,
ARRAY_SIZE(wm8581_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
ARRAY_SIZE(wm8581_dapm_widgets));
snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
ARRAY_SIZE(wm8581_dapm_routes));
break;
default:
break;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
wm8580->supplies);
if (ret != 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
goto err_regulator_get;
}
/* Get the codec into a known state */
ret = snd_soc_component_write(component, WM8580_RESET, 0);
if (ret != 0) {
dev_err(component->dev, "Failed to reset component: %d\n", ret);
goto err_regulator_enable;
}
return 0;
err_regulator_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
err_regulator_get:
return ret;
}
/* power down chip */
static void wm8580_remove(struct snd_soc_component *component)
{
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
}
static const struct snd_soc_component_driver soc_component_dev_wm8580 = {
.probe = wm8580_probe,
.remove = wm8580_remove,
.set_bias_level = wm8580_set_bias_level,
.controls = wm8580_snd_controls,
.num_controls = ARRAY_SIZE(wm8580_snd_controls),
.dapm_widgets = wm8580_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
.dapm_routes = wm8580_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8580_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8580_MAX_REGISTER,
.reg_defaults = wm8580_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8580_volatile,
};
static const struct wm8580_driver_data wm8580_data = {
.num_dacs = 3,
};
static const struct wm8580_driver_data wm8581_data = {
.num_dacs = 4,
};
static const struct of_device_id wm8580_of_match[] = {
{ .compatible = "wlf,wm8580", .data = &wm8580_data },
{ .compatible = "wlf,wm8581", .data = &wm8581_data },
{ },
};
MODULE_DEVICE_TABLE(of, wm8580_of_match);
static int wm8580_i2c_probe(struct i2c_client *i2c)
{
const struct of_device_id *of_id;
struct wm8580_priv *wm8580;
int ret, i;
wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
GFP_KERNEL);
if (wm8580 == NULL)
return -ENOMEM;
wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
if (IS_ERR(wm8580->regmap))
return PTR_ERR(wm8580->regmap);
for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
wm8580->supplies[i].supply = wm8580_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
wm8580->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, wm8580);
of_id = of_match_device(wm8580_of_match, &i2c->dev);
if (of_id)
wm8580->drvdata = of_id->data;
if (!wm8580->drvdata) {
dev_err(&i2c->dev, "failed to find driver data\n");
return -EINVAL;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
return ret;
}
static const struct i2c_device_id wm8580_i2c_id[] = {
{ "wm8580", (kernel_ulong_t)&wm8580_data },
{ "wm8581", (kernel_ulong_t)&wm8581_data },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
static struct i2c_driver wm8580_i2c_driver = {
.driver = {
.name = "wm8580",
.of_match_table = wm8580_of_match,
},
.probe = wm8580_i2c_probe,
.id_table = wm8580_i2c_id,
};
module_i2c_driver(wm8580_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8580 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_AUTHOR("Matt Flax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8580.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arizona.c - Wolfson Arizona class device shared support
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/delay.h>
#include <linux/gcd.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_runtime.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#define ARIZONA_AIF_BCLK_CTRL 0x00
#define ARIZONA_AIF_TX_PIN_CTRL 0x01
#define ARIZONA_AIF_RX_PIN_CTRL 0x02
#define ARIZONA_AIF_RATE_CTRL 0x03
#define ARIZONA_AIF_FORMAT 0x04
#define ARIZONA_AIF_TX_BCLK_RATE 0x05
#define ARIZONA_AIF_RX_BCLK_RATE 0x06
#define ARIZONA_AIF_FRAME_CTRL_1 0x07
#define ARIZONA_AIF_FRAME_CTRL_2 0x08
#define ARIZONA_AIF_FRAME_CTRL_3 0x09
#define ARIZONA_AIF_FRAME_CTRL_4 0x0A
#define ARIZONA_AIF_FRAME_CTRL_5 0x0B
#define ARIZONA_AIF_FRAME_CTRL_6 0x0C
#define ARIZONA_AIF_FRAME_CTRL_7 0x0D
#define ARIZONA_AIF_FRAME_CTRL_8 0x0E
#define ARIZONA_AIF_FRAME_CTRL_9 0x0F
#define ARIZONA_AIF_FRAME_CTRL_10 0x10
#define ARIZONA_AIF_FRAME_CTRL_11 0x11
#define ARIZONA_AIF_FRAME_CTRL_12 0x12
#define ARIZONA_AIF_FRAME_CTRL_13 0x13
#define ARIZONA_AIF_FRAME_CTRL_14 0x14
#define ARIZONA_AIF_FRAME_CTRL_15 0x15
#define ARIZONA_AIF_FRAME_CTRL_16 0x16
#define ARIZONA_AIF_FRAME_CTRL_17 0x17
#define ARIZONA_AIF_FRAME_CTRL_18 0x18
#define ARIZONA_AIF_TX_ENABLES 0x19
#define ARIZONA_AIF_RX_ENABLES 0x1A
#define ARIZONA_AIF_FORCE_WRITE 0x1B
#define ARIZONA_FLL_VCO_CORNER 141900000
#define ARIZONA_FLL_MAX_FREF 13500000
#define ARIZONA_FLL_MIN_FVCO 90000000
#define ARIZONA_FLL_MAX_FRATIO 16
#define ARIZONA_FLL_MAX_REFDIV 8
#define ARIZONA_FLL_MIN_OUTDIV 2
#define ARIZONA_FLL_MAX_OUTDIV 7
#define ARIZONA_FMT_DSP_MODE_A 0
#define ARIZONA_FMT_DSP_MODE_B 1
#define ARIZONA_FMT_I2S_MODE 2
#define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3
#define arizona_fll_err(_fll, fmt, ...) \
dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
#define arizona_fll_warn(_fll, fmt, ...) \
dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
#define arizona_fll_dbg(_fll, fmt, ...) \
dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
#define arizona_aif_err(_dai, fmt, ...) \
dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
#define arizona_aif_warn(_dai, fmt, ...) \
dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
#define arizona_aif_dbg(_dai, fmt, ...) \
dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = snd_soc_component_read(component,
ARIZONA_INTERRUPT_RAW_STATUS_3);
if (val & ARIZONA_SPK_OVERHEAT_STS) {
dev_crit(arizona->dev,
"Speaker not enabled due to temperature\n");
return -EBUSY;
}
regmap_update_bits_async(arizona->regmap,
ARIZONA_OUTPUT_ENABLES_1,
1 << w->shift, 1 << w->shift);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits_async(arizona->regmap,
ARIZONA_OUTPUT_ENABLES_1,
1 << w->shift, 0);
break;
default:
break;
}
return arizona_out_ev(w, kcontrol, event);
}
static irqreturn_t arizona_thermal_warn(int irq, void *data)
{
struct arizona *arizona = data;
unsigned int val;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
&val);
if (ret != 0) {
dev_err(arizona->dev, "Failed to read thermal status: %d\n",
ret);
} else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) {
dev_crit(arizona->dev, "Thermal warning\n");
}
return IRQ_HANDLED;
}
static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
{
struct arizona *arizona = data;
unsigned int val;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
&val);
if (ret != 0) {
dev_err(arizona->dev, "Failed to read thermal status: %d\n",
ret);
} else if (val & ARIZONA_SPK_OVERHEAT_STS) {
dev_crit(arizona->dev, "Thermal shutdown\n");
ret = regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT4L_ENA |
ARIZONA_OUT4R_ENA, 0);
if (ret != 0)
dev_crit(arizona->dev,
"Failed to disable speaker outputs: %d\n",
ret);
}
return IRQ_HANDLED;
}
static const struct snd_soc_dapm_widget arizona_spkl =
SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD);
static const struct snd_soc_dapm_widget arizona_spkr =
SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD);
int arizona_init_spk(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int ret;
ret = snd_soc_dapm_new_controls(dapm, &arizona_spkl, 1);
if (ret != 0)
return ret;
switch (arizona->type) {
case WM8997:
case CS47L24:
case WM1831:
break;
default:
ret = snd_soc_dapm_new_controls(dapm, &arizona_spkr, 1);
if (ret != 0)
return ret;
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_spk);
int arizona_init_spk_irqs(struct arizona *arizona)
{
int ret;
ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN,
"Thermal warning", arizona_thermal_warn,
arizona);
if (ret != 0)
dev_err(arizona->dev,
"Failed to get thermal warning IRQ: %d\n",
ret);
ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT,
"Thermal shutdown", arizona_thermal_shutdown,
arizona);
if (ret != 0)
dev_err(arizona->dev,
"Failed to get thermal shutdown IRQ: %d\n",
ret);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_spk_irqs);
int arizona_free_spk_irqs(struct arizona *arizona)
{
arizona_free_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT, arizona);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_free_spk_irqs);
static const struct snd_soc_dapm_route arizona_mono_routes[] = {
{ "OUT1R", NULL, "OUT1L" },
{ "OUT2R", NULL, "OUT2L" },
{ "OUT3R", NULL, "OUT3L" },
{ "OUT4R", NULL, "OUT4L" },
{ "OUT5R", NULL, "OUT5L" },
{ "OUT6R", NULL, "OUT6L" },
};
int arizona_init_mono(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int i;
for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) {
if (arizona->pdata.out_mono[i])
snd_soc_dapm_add_routes(dapm,
&arizona_mono_routes[i], 1);
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_mono);
int arizona_init_gpio(struct snd_soc_component *component)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int i;
switch (arizona->type) {
case WM5110:
case WM8280:
snd_soc_component_disable_pin(component,
"DRC2 Signal Activity");
break;
default:
break;
}
snd_soc_component_disable_pin(component, "DRC1 Signal Activity");
for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
snd_soc_component_enable_pin(component,
"DRC1 Signal Activity");
break;
case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
snd_soc_component_enable_pin(component,
"DRC2 Signal Activity");
break;
default:
break;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_gpio);
int arizona_init_common(struct arizona *arizona)
{
struct arizona_pdata *pdata = &arizona->pdata;
unsigned int val, mask;
int i;
BLOCKING_INIT_NOTIFIER_HEAD(&arizona->notifier);
for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) {
/* Default is 0 so noop with defaults */
if (pdata->out_mono[i])
val = ARIZONA_OUT1_MONO;
else
val = 0;
regmap_update_bits(arizona->regmap,
ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
ARIZONA_OUT1_MONO, val);
}
for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
if (pdata->spk_mute[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
ARIZONA_SPK1_MUTE_ENDIAN_MASK |
ARIZONA_SPK1_MUTE_SEQ1_MASK,
pdata->spk_mute[i]);
if (pdata->spk_fmt[i])
regmap_update_bits(arizona->regmap,
ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
ARIZONA_SPK1_FMT_MASK,
pdata->spk_fmt[i]);
}
for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
/* Default for both is 0 so noop with defaults */
val = pdata->dmic_ref[i] << ARIZONA_IN1_DMIC_SUP_SHIFT;
if (pdata->inmode[i] & ARIZONA_INMODE_DMIC)
val |= 1 << ARIZONA_IN1_MODE_SHIFT;
switch (arizona->type) {
case WM8998:
case WM1814:
regmap_update_bits(arizona->regmap,
ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 8),
ARIZONA_IN1L_SRC_SE_MASK,
(pdata->inmode[i] & ARIZONA_INMODE_SE)
<< ARIZONA_IN1L_SRC_SE_SHIFT);
regmap_update_bits(arizona->regmap,
ARIZONA_ADC_DIGITAL_VOLUME_1R + (i * 8),
ARIZONA_IN1R_SRC_SE_MASK,
(pdata->inmode[i] & ARIZONA_INMODE_SE)
<< ARIZONA_IN1R_SRC_SE_SHIFT);
mask = ARIZONA_IN1_DMIC_SUP_MASK |
ARIZONA_IN1_MODE_MASK;
break;
default:
if (pdata->inmode[i] & ARIZONA_INMODE_SE)
val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT;
mask = ARIZONA_IN1_DMIC_SUP_MASK |
ARIZONA_IN1_MODE_MASK |
ARIZONA_IN1_SINGLE_ENDED_MASK;
break;
}
regmap_update_bits(arizona->regmap,
ARIZONA_IN1L_CONTROL + (i * 8),
mask, val);
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_common);
int arizona_init_vol_limit(struct arizona *arizona)
{
int i;
for (i = 0; i < ARRAY_SIZE(arizona->pdata.out_vol_limit); ++i) {
if (arizona->pdata.out_vol_limit[i])
regmap_update_bits(arizona->regmap,
ARIZONA_DAC_VOLUME_LIMIT_1L + i * 4,
ARIZONA_OUT1L_VOL_LIM_MASK,
arizona->pdata.out_vol_limit[i]);
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_vol_limit);
const char * const arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
"None",
"Tone Generator 1",
"Tone Generator 2",
"Haptics",
"AEC",
"AEC2",
"Mic Mute Mixer",
"Noise Generator",
"IN1L",
"IN1R",
"IN2L",
"IN2R",
"IN3L",
"IN3R",
"IN4L",
"IN4R",
"AIF1RX1",
"AIF1RX2",
"AIF1RX3",
"AIF1RX4",
"AIF1RX5",
"AIF1RX6",
"AIF1RX7",
"AIF1RX8",
"AIF2RX1",
"AIF2RX2",
"AIF2RX3",
"AIF2RX4",
"AIF2RX5",
"AIF2RX6",
"AIF3RX1",
"AIF3RX2",
"SLIMRX1",
"SLIMRX2",
"SLIMRX3",
"SLIMRX4",
"SLIMRX5",
"SLIMRX6",
"SLIMRX7",
"SLIMRX8",
"EQ1",
"EQ2",
"EQ3",
"EQ4",
"DRC1L",
"DRC1R",
"DRC2L",
"DRC2R",
"LHPF1",
"LHPF2",
"LHPF3",
"LHPF4",
"DSP1.1",
"DSP1.2",
"DSP1.3",
"DSP1.4",
"DSP1.5",
"DSP1.6",
"DSP2.1",
"DSP2.2",
"DSP2.3",
"DSP2.4",
"DSP2.5",
"DSP2.6",
"DSP3.1",
"DSP3.2",
"DSP3.3",
"DSP3.4",
"DSP3.5",
"DSP3.6",
"DSP4.1",
"DSP4.2",
"DSP4.3",
"DSP4.4",
"DSP4.5",
"DSP4.6",
"ASRC1L",
"ASRC1R",
"ASRC2L",
"ASRC2R",
"ISRC1INT1",
"ISRC1INT2",
"ISRC1INT3",
"ISRC1INT4",
"ISRC1DEC1",
"ISRC1DEC2",
"ISRC1DEC3",
"ISRC1DEC4",
"ISRC2INT1",
"ISRC2INT2",
"ISRC2INT3",
"ISRC2INT4",
"ISRC2DEC1",
"ISRC2DEC2",
"ISRC2DEC3",
"ISRC2DEC4",
"ISRC3INT1",
"ISRC3INT2",
"ISRC3INT3",
"ISRC3INT4",
"ISRC3DEC1",
"ISRC3DEC2",
"ISRC3DEC3",
"ISRC3DEC4",
};
EXPORT_SYMBOL_GPL(arizona_mixer_texts);
unsigned int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
0x00, /* None */
0x04, /* Tone */
0x05,
0x06, /* Haptics */
0x08, /* AEC */
0x09, /* AEC2 */
0x0c, /* Noise mixer */
0x0d, /* Comfort noise */
0x10, /* IN1L */
0x11,
0x12,
0x13,
0x14,
0x15,
0x16,
0x17,
0x20, /* AIF1RX1 */
0x21,
0x22,
0x23,
0x24,
0x25,
0x26,
0x27,
0x28, /* AIF2RX1 */
0x29,
0x2a,
0x2b,
0x2c,
0x2d,
0x30, /* AIF3RX1 */
0x31,
0x38, /* SLIMRX1 */
0x39,
0x3a,
0x3b,
0x3c,
0x3d,
0x3e,
0x3f,
0x50, /* EQ1 */
0x51,
0x52,
0x53,
0x58, /* DRC1L */
0x59,
0x5a,
0x5b,
0x60, /* LHPF1 */
0x61,
0x62,
0x63,
0x68, /* DSP1.1 */
0x69,
0x6a,
0x6b,
0x6c,
0x6d,
0x70, /* DSP2.1 */
0x71,
0x72,
0x73,
0x74,
0x75,
0x78, /* DSP3.1 */
0x79,
0x7a,
0x7b,
0x7c,
0x7d,
0x80, /* DSP4.1 */
0x81,
0x82,
0x83,
0x84,
0x85,
0x90, /* ASRC1L */
0x91,
0x92,
0x93,
0xa0, /* ISRC1INT1 */
0xa1,
0xa2,
0xa3,
0xa4, /* ISRC1DEC1 */
0xa5,
0xa6,
0xa7,
0xa8, /* ISRC2DEC1 */
0xa9,
0xaa,
0xab,
0xac, /* ISRC2INT1 */
0xad,
0xae,
0xaf,
0xb0, /* ISRC3DEC1 */
0xb1,
0xb2,
0xb3,
0xb4, /* ISRC3INT1 */
0xb5,
0xb6,
0xb7,
};
EXPORT_SYMBOL_GPL(arizona_mixer_values);
const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
const char * const arizona_sample_rate_text[ARIZONA_SAMPLE_RATE_ENUM_SIZE] = {
"12kHz", "24kHz", "48kHz", "96kHz", "192kHz",
"11.025kHz", "22.05kHz", "44.1kHz", "88.2kHz", "176.4kHz",
"4kHz", "8kHz", "16kHz", "32kHz",
};
EXPORT_SYMBOL_GPL(arizona_sample_rate_text);
const unsigned int arizona_sample_rate_val[ARIZONA_SAMPLE_RATE_ENUM_SIZE] = {
0x01, 0x02, 0x03, 0x04, 0x05, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
0x10, 0x11, 0x12, 0x13,
};
EXPORT_SYMBOL_GPL(arizona_sample_rate_val);
const char *arizona_sample_rate_val_to_name(unsigned int rate_val)
{
int i;
for (i = 0; i < ARRAY_SIZE(arizona_sample_rate_val); ++i) {
if (arizona_sample_rate_val[i] == rate_val)
return arizona_sample_rate_text[i];
}
return "Illegal";
}
EXPORT_SYMBOL_GPL(arizona_sample_rate_val_to_name);
const char * const arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
"SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
};
EXPORT_SYMBOL_GPL(arizona_rate_text);
const unsigned int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
0, 1, 2, 8,
};
EXPORT_SYMBOL_GPL(arizona_rate_val);
const struct soc_enum arizona_isrc_fsh[] = {
SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
ARIZONA_ISRC1_FSH_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
ARIZONA_ISRC2_FSH_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
ARIZONA_ISRC3_FSH_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
};
EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
const struct soc_enum arizona_isrc_fsl[] = {
SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
ARIZONA_ISRC1_FSL_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
ARIZONA_ISRC2_FSL_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
ARIZONA_ISRC3_FSL_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
};
EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
const struct soc_enum arizona_asrc_rate1 =
SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
ARIZONA_ASRC_RATE1_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE - 1,
arizona_rate_text, arizona_rate_val);
EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
static const char * const arizona_vol_ramp_text[] = {
"0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
"15ms/6dB", "30ms/6dB",
};
SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
ARIZONA_INPUT_VOLUME_RAMP,
ARIZONA_IN_VD_RAMP_SHIFT,
arizona_vol_ramp_text);
EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
ARIZONA_INPUT_VOLUME_RAMP,
ARIZONA_IN_VI_RAMP_SHIFT,
arizona_vol_ramp_text);
EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
ARIZONA_OUTPUT_VOLUME_RAMP,
ARIZONA_OUT_VD_RAMP_SHIFT,
arizona_vol_ramp_text);
EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
ARIZONA_OUTPUT_VOLUME_RAMP,
ARIZONA_OUT_VI_RAMP_SHIFT,
arizona_vol_ramp_text);
EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
static const char * const arizona_lhpf_mode_text[] = {
"Low-pass", "High-pass"
};
SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
ARIZONA_HPLPF1_1,
ARIZONA_LHPF1_MODE_SHIFT,
arizona_lhpf_mode_text);
EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
ARIZONA_HPLPF2_1,
ARIZONA_LHPF2_MODE_SHIFT,
arizona_lhpf_mode_text);
EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
ARIZONA_HPLPF3_1,
ARIZONA_LHPF3_MODE_SHIFT,
arizona_lhpf_mode_text);
EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
ARIZONA_HPLPF4_1,
ARIZONA_LHPF4_MODE_SHIFT,
arizona_lhpf_mode_text);
EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
static const char * const arizona_ng_hold_text[] = {
"30ms", "120ms", "250ms", "500ms",
};
SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_HOLD_SHIFT,
arizona_ng_hold_text);
EXPORT_SYMBOL_GPL(arizona_ng_hold);
static const char * const arizona_in_hpf_cut_text[] = {
"2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
};
SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
ARIZONA_HPF_CONTROL,
ARIZONA_IN_HPF_CUT_SHIFT,
arizona_in_hpf_cut_text);
EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
static const char * const arizona_in_dmic_osr_text[] = {
"1.536MHz", "3.072MHz", "6.144MHz", "768kHz",
};
const struct soc_enum arizona_in_dmic_osr[] = {
SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
ARRAY_SIZE(arizona_in_dmic_osr_text),
arizona_in_dmic_osr_text),
SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
ARRAY_SIZE(arizona_in_dmic_osr_text),
arizona_in_dmic_osr_text),
SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
ARRAY_SIZE(arizona_in_dmic_osr_text),
arizona_in_dmic_osr_text),
SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
ARRAY_SIZE(arizona_in_dmic_osr_text),
arizona_in_dmic_osr_text),
};
EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
static const char * const arizona_anc_input_src_text[] = {
"None", "IN1", "IN2", "IN3", "IN4",
};
static const char * const arizona_anc_channel_src_text[] = {
"None", "Left", "Right", "Combine",
};
const struct soc_enum arizona_anc_input_src[] = {
SOC_ENUM_SINGLE(ARIZONA_ANC_SRC,
ARIZONA_IN_RXANCL_SEL_SHIFT,
ARRAY_SIZE(arizona_anc_input_src_text),
arizona_anc_input_src_text),
SOC_ENUM_SINGLE(ARIZONA_FCL_ADC_REFORMATTER_CONTROL,
ARIZONA_FCL_MIC_MODE_SEL_SHIFT,
ARRAY_SIZE(arizona_anc_channel_src_text),
arizona_anc_channel_src_text),
SOC_ENUM_SINGLE(ARIZONA_ANC_SRC,
ARIZONA_IN_RXANCR_SEL_SHIFT,
ARRAY_SIZE(arizona_anc_input_src_text),
arizona_anc_input_src_text),
SOC_ENUM_SINGLE(ARIZONA_FCR_ADC_REFORMATTER_CONTROL,
ARIZONA_FCR_MIC_MODE_SEL_SHIFT,
ARRAY_SIZE(arizona_anc_channel_src_text),
arizona_anc_channel_src_text),
};
EXPORT_SYMBOL_GPL(arizona_anc_input_src);
static const char * const arizona_anc_ng_texts[] = {
"None",
"Internal",
"External",
};
SOC_ENUM_SINGLE_DECL(arizona_anc_ng_enum, SND_SOC_NOPM, 0,
arizona_anc_ng_texts);
EXPORT_SYMBOL_GPL(arizona_anc_ng_enum);
static const char * const arizona_output_anc_src_text[] = {
"None", "RXANCL", "RXANCR",
};
const struct soc_enum arizona_output_anc_src[] = {
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1L,
ARIZONA_OUT1L_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1R,
ARIZONA_OUT1R_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2L,
ARIZONA_OUT2L_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2R,
ARIZONA_OUT2R_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3L,
ARIZONA_OUT3L_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_DAC_VOLUME_LIMIT_3R,
ARIZONA_OUT3R_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_4L,
ARIZONA_OUT4L_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_4R,
ARIZONA_OUT4R_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_5L,
ARIZONA_OUT5L_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_5R,
ARIZONA_OUT5R_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_6L,
ARIZONA_OUT6L_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_6R,
ARIZONA_OUT6R_ANC_SRC_SHIFT,
ARRAY_SIZE(arizona_output_anc_src_text),
arizona_output_anc_src_text),
};
EXPORT_SYMBOL_GPL(arizona_output_anc_src);
const struct snd_kcontrol_new arizona_voice_trigger_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 1, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 2, 1, 0),
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 3, 1, 0),
};
EXPORT_SYMBOL_GPL(arizona_voice_trigger_switch);
static void arizona_in_set_vu(struct snd_soc_component *component, int ena)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int val;
int i;
if (ena)
val = ARIZONA_IN_VU;
else
val = 0;
for (i = 0; i < priv->num_inputs; i++)
snd_soc_component_update_bits(component,
ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
ARIZONA_IN_VU, val);
}
bool arizona_input_analog(struct snd_soc_component *component, int shift)
{
unsigned int reg = ARIZONA_IN1L_CONTROL + ((shift / 2) * 8);
unsigned int val = snd_soc_component_read(component, reg);
return !(val & ARIZONA_IN1_MODE_MASK);
}
EXPORT_SYMBOL_GPL(arizona_input_analog);
int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int reg;
if (w->shift % 2)
reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
else
reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
priv->in_pending++;
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, reg,
ARIZONA_IN1L_MUTE, 0);
/* If this is the last input pending then allow VU */
priv->in_pending--;
if (priv->in_pending == 0) {
msleep(1);
arizona_in_set_vu(component, 1);
}
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, reg,
ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable volume updates if no inputs are enabled */
reg = snd_soc_component_read(component, ARIZONA_INPUT_ENABLES);
if (reg == 0)
arizona_in_set_vu(component, 0);
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_in_ev);
int arizona_out_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (w->shift) {
case ARIZONA_OUT1L_ENA_SHIFT:
case ARIZONA_OUT1R_ENA_SHIFT:
case ARIZONA_OUT2L_ENA_SHIFT:
case ARIZONA_OUT2R_ENA_SHIFT:
case ARIZONA_OUT3L_ENA_SHIFT:
case ARIZONA_OUT3R_ENA_SHIFT:
priv->out_up_pending++;
priv->out_up_delay += 17;
break;
case ARIZONA_OUT4L_ENA_SHIFT:
case ARIZONA_OUT4R_ENA_SHIFT:
priv->out_up_pending++;
switch (arizona->type) {
case WM5102:
case WM8997:
break;
default:
priv->out_up_delay += 10;
break;
}
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
switch (w->shift) {
case ARIZONA_OUT1L_ENA_SHIFT:
case ARIZONA_OUT1R_ENA_SHIFT:
case ARIZONA_OUT2L_ENA_SHIFT:
case ARIZONA_OUT2R_ENA_SHIFT:
case ARIZONA_OUT3L_ENA_SHIFT:
case ARIZONA_OUT3R_ENA_SHIFT:
case ARIZONA_OUT4L_ENA_SHIFT:
case ARIZONA_OUT4R_ENA_SHIFT:
priv->out_up_pending--;
if (!priv->out_up_pending && priv->out_up_delay) {
dev_dbg(component->dev, "Power up delay: %d\n",
priv->out_up_delay);
msleep(priv->out_up_delay);
priv->out_up_delay = 0;
}
break;
default:
break;
}
break;
case SND_SOC_DAPM_PRE_PMD:
switch (w->shift) {
case ARIZONA_OUT1L_ENA_SHIFT:
case ARIZONA_OUT1R_ENA_SHIFT:
case ARIZONA_OUT2L_ENA_SHIFT:
case ARIZONA_OUT2R_ENA_SHIFT:
case ARIZONA_OUT3L_ENA_SHIFT:
case ARIZONA_OUT3R_ENA_SHIFT:
priv->out_down_pending++;
priv->out_down_delay++;
break;
case ARIZONA_OUT4L_ENA_SHIFT:
case ARIZONA_OUT4R_ENA_SHIFT:
priv->out_down_pending++;
switch (arizona->type) {
case WM5102:
case WM8997:
break;
case WM8998:
case WM1814:
priv->out_down_delay += 5;
break;
default:
priv->out_down_delay++;
break;
}
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMD:
switch (w->shift) {
case ARIZONA_OUT1L_ENA_SHIFT:
case ARIZONA_OUT1R_ENA_SHIFT:
case ARIZONA_OUT2L_ENA_SHIFT:
case ARIZONA_OUT2R_ENA_SHIFT:
case ARIZONA_OUT3L_ENA_SHIFT:
case ARIZONA_OUT3R_ENA_SHIFT:
case ARIZONA_OUT4L_ENA_SHIFT:
case ARIZONA_OUT4R_ENA_SHIFT:
priv->out_down_pending--;
if (!priv->out_down_pending && priv->out_down_delay) {
dev_dbg(component->dev, "Power down delay: %d\n",
priv->out_down_delay);
msleep(priv->out_down_delay);
priv->out_down_delay = 0;
}
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(arizona_out_ev);
int arizona_hp_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
unsigned int mask = 1 << w->shift;
unsigned int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = mask;
break;
case SND_SOC_DAPM_PRE_PMD:
val = 0;
break;
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_POST_PMD:
return arizona_out_ev(w, kcontrol, event);
default:
return -EINVAL;
}
/* Store the desired state for the HP outputs */
priv->arizona->hp_ena &= ~mask;
priv->arizona->hp_ena |= val;
/* Force off if HPDET clamp is active */
if (priv->arizona->hpdet_clamp)
val = 0;
regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
mask, val);
return arizona_out_ev(w, kcontrol, event);
}
EXPORT_SYMBOL_GPL(arizona_hp_ev);
static int arizona_dvfs_enable(struct snd_soc_component *component)
{
const struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int ret;
ret = regulator_set_voltage(arizona->dcvdd, 1800000, 1800000);
if (ret) {
dev_err(component->dev, "Failed to boost DCVDD: %d\n", ret);
return ret;
}
ret = regmap_update_bits(arizona->regmap,
ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
ARIZONA_SUBSYS_MAX_FREQ,
ARIZONA_SUBSYS_MAX_FREQ);
if (ret) {
dev_err(component->dev, "Failed to enable subsys max: %d\n", ret);
regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
return ret;
}
return 0;
}
static int arizona_dvfs_disable(struct snd_soc_component *component)
{
const struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int ret;
ret = regmap_update_bits(arizona->regmap,
ARIZONA_DYNAMIC_FREQUENCY_SCALING_1,
ARIZONA_SUBSYS_MAX_FREQ, 0);
if (ret) {
dev_err(component->dev, "Failed to disable subsys max: %d\n", ret);
return ret;
}
ret = regulator_set_voltage(arizona->dcvdd, 1200000, 1800000);
if (ret) {
dev_err(component->dev, "Failed to unboost DCVDD: %d\n", ret);
return ret;
}
return 0;
}
int arizona_dvfs_up(struct snd_soc_component *component, unsigned int flags)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
int ret = 0;
mutex_lock(&priv->dvfs_lock);
if (!priv->dvfs_cached && !priv->dvfs_reqs) {
ret = arizona_dvfs_enable(component);
if (ret)
goto err;
}
priv->dvfs_reqs |= flags;
err:
mutex_unlock(&priv->dvfs_lock);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_dvfs_up);
int arizona_dvfs_down(struct snd_soc_component *component, unsigned int flags)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int old_reqs;
int ret = 0;
mutex_lock(&priv->dvfs_lock);
old_reqs = priv->dvfs_reqs;
priv->dvfs_reqs &= ~flags;
if (!priv->dvfs_cached && old_reqs && !priv->dvfs_reqs)
ret = arizona_dvfs_disable(component);
mutex_unlock(&priv->dvfs_lock);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_dvfs_down);
int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
int ret = 0;
mutex_lock(&priv->dvfs_lock);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (priv->dvfs_reqs)
ret = arizona_dvfs_enable(component);
priv->dvfs_cached = false;
break;
case SND_SOC_DAPM_PRE_PMD:
/* We must ensure DVFS is disabled before the codec goes into
* suspend so that we are never in an illegal state of DVFS
* enabled without enough DCVDD
*/
priv->dvfs_cached = true;
if (priv->dvfs_reqs)
ret = arizona_dvfs_disable(component);
break;
default:
break;
}
mutex_unlock(&priv->dvfs_lock);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev);
void arizona_init_dvfs(struct arizona_priv *priv)
{
mutex_init(&priv->dvfs_lock);
}
EXPORT_SYMBOL_GPL(arizona_init_dvfs);
int arizona_anc_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = 1 << w->shift;
break;
case SND_SOC_DAPM_PRE_PMD:
val = 1 << (w->shift + 1);
break;
default:
return 0;
}
snd_soc_component_write(component, ARIZONA_CLOCK_CONTROL, val);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_anc_ev);
static unsigned int arizona_opclk_ref_48k_rates[] = {
6144000,
12288000,
24576000,
49152000,
};
static unsigned int arizona_opclk_ref_44k1_rates[] = {
5644800,
11289600,
22579200,
45158400,
};
static int arizona_set_opclk(struct snd_soc_component *component,
unsigned int clk, unsigned int freq)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int reg;
unsigned int *rates;
int ref, div, refclk;
switch (clk) {
case ARIZONA_CLK_OPCLK:
reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
refclk = priv->sysclk;
break;
case ARIZONA_CLK_ASYNC_OPCLK:
reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
refclk = priv->asyncclk;
break;
default:
return -EINVAL;
}
if (refclk % 8000)
rates = arizona_opclk_ref_44k1_rates;
else
rates = arizona_opclk_ref_48k_rates;
for (ref = 0; ref < ARRAY_SIZE(arizona_opclk_ref_48k_rates) &&
rates[ref] <= refclk; ref++) {
div = 1;
while (rates[ref] / div >= freq && div < 32) {
if (rates[ref] / div == freq) {
dev_dbg(component->dev, "Configured %dHz OPCLK\n",
freq);
snd_soc_component_update_bits(component, reg,
ARIZONA_OPCLK_DIV_MASK |
ARIZONA_OPCLK_SEL_MASK,
(div <<
ARIZONA_OPCLK_DIV_SHIFT) |
ref);
return 0;
}
div++;
}
}
dev_err(component->dev, "Unable to generate %dHz OPCLK\n", freq);
return -EINVAL;
}
int arizona_clk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
unsigned int val;
int clk_idx;
int ret;
ret = regmap_read(arizona->regmap, w->reg, &val);
if (ret) {
dev_err(component->dev, "Failed to check clock source: %d\n", ret);
return ret;
}
val = (val & ARIZONA_SYSCLK_SRC_MASK) >> ARIZONA_SYSCLK_SRC_SHIFT;
switch (val) {
case ARIZONA_CLK_SRC_MCLK1:
clk_idx = ARIZONA_MCLK1;
break;
case ARIZONA_CLK_SRC_MCLK2:
clk_idx = ARIZONA_MCLK2;
break;
default:
return 0;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return clk_prepare_enable(arizona->mclk[clk_idx]);
case SND_SOC_DAPM_POST_PMD:
clk_disable_unprepare(arizona->mclk[clk_idx]);
return 0;
default:
return 0;
}
}
EXPORT_SYMBOL_GPL(arizona_clk_ev);
int arizona_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
char *name;
unsigned int reg;
unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
int *clk;
switch (clk_id) {
case ARIZONA_CLK_SYSCLK:
name = "SYSCLK";
reg = ARIZONA_SYSTEM_CLOCK_1;
clk = &priv->sysclk;
mask |= ARIZONA_SYSCLK_FRAC;
break;
case ARIZONA_CLK_ASYNCCLK:
name = "ASYNCCLK";
reg = ARIZONA_ASYNC_CLOCK_1;
clk = &priv->asyncclk;
break;
case ARIZONA_CLK_OPCLK:
case ARIZONA_CLK_ASYNC_OPCLK:
return arizona_set_opclk(component, clk_id, freq);
default:
return -EINVAL;
}
switch (freq) {
case 5644800:
case 6144000:
break;
case 11289600:
case 12288000:
val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 22579200:
case 24576000:
val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 45158400:
case 49152000:
val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 67737600:
case 73728000:
val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 90316800:
case 98304000:
val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 135475200:
case 147456000:
val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
break;
case 0:
dev_dbg(arizona->dev, "%s cleared\n", name);
*clk = freq;
return 0;
default:
return -EINVAL;
}
*clk = freq;
if (freq % 6144000)
val |= ARIZONA_SYSCLK_FRAC;
dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
return regmap_update_bits(arizona->regmap, reg, mask, val);
}
EXPORT_SYMBOL_GPL(arizona_set_sysclk);
static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int lrclk, bclk, mode, base;
base = dai->driver->base;
lrclk = 0;
bclk = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
mode = ARIZONA_FMT_DSP_MODE_A;
break;
case SND_SOC_DAIFMT_DSP_B:
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
!= SND_SOC_DAIFMT_CBM_CFM) {
arizona_aif_err(dai, "DSP_B not valid in slave mode\n");
return -EINVAL;
}
mode = ARIZONA_FMT_DSP_MODE_B;
break;
case SND_SOC_DAIFMT_I2S:
mode = ARIZONA_FMT_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK)
!= SND_SOC_DAIFMT_CBM_CFM) {
arizona_aif_err(dai, "LEFT_J not valid in slave mode\n");
return -EINVAL;
}
mode = ARIZONA_FMT_LEFT_JUSTIFIED_MODE;
break;
default:
arizona_aif_err(dai, "Unsupported DAI format %d\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
bclk |= ARIZONA_AIF1_BCLK_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
bclk |= ARIZONA_AIF1_BCLK_MSTR;
lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
break;
default:
arizona_aif_err(dai, "Unsupported master mode %d\n",
fmt & SND_SOC_DAIFMT_MASTER_MASK);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bclk |= ARIZONA_AIF1_BCLK_INV;
lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
bclk |= ARIZONA_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
break;
default:
return -EINVAL;
}
regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
ARIZONA_AIF1_BCLK_INV |
ARIZONA_AIF1_BCLK_MSTR,
bclk);
regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
ARIZONA_AIF1TX_LRCLK_INV |
ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_RX_PIN_CTRL,
ARIZONA_AIF1RX_LRCLK_INV |
ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
ARIZONA_AIF1_FMT_MASK, mode);
return 0;
}
static const int arizona_48k_bclk_rates[] = {
-1,
48000,
64000,
96000,
128000,
192000,
256000,
384000,
512000,
768000,
1024000,
1536000,
2048000,
3072000,
4096000,
6144000,
8192000,
12288000,
24576000,
};
static const int arizona_44k1_bclk_rates[] = {
-1,
44100,
58800,
88200,
117600,
177640,
235200,
352800,
470400,
705600,
940800,
1411200,
1881600,
2822400,
3763200,
5644800,
7526400,
11289600,
22579200,
};
static const unsigned int arizona_sr_vals[] = {
0,
12000,
24000,
48000,
96000,
192000,
384000,
768000,
0,
11025,
22050,
44100,
88200,
176400,
352800,
705600,
4000,
8000,
16000,
32000,
64000,
128000,
256000,
512000,
};
#define ARIZONA_48K_RATE_MASK 0x0F003E
#define ARIZONA_44K1_RATE_MASK 0x003E00
#define ARIZONA_RATE_MASK (ARIZONA_48K_RATE_MASK | ARIZONA_44K1_RATE_MASK)
static const struct snd_pcm_hw_constraint_list arizona_constraint = {
.count = ARRAY_SIZE(arizona_sr_vals),
.list = arizona_sr_vals,
};
static int arizona_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
unsigned int base_rate;
if (!substream->runtime)
return 0;
switch (dai_priv->clk) {
case ARIZONA_CLK_SYSCLK:
base_rate = priv->sysclk;
break;
case ARIZONA_CLK_ASYNCCLK:
base_rate = priv->asyncclk;
break;
default:
return 0;
}
if (base_rate == 0)
dai_priv->constraint.mask = ARIZONA_RATE_MASK;
else if (base_rate % 8000)
dai_priv->constraint.mask = ARIZONA_44K1_RATE_MASK;
else
dai_priv->constraint.mask = ARIZONA_48K_RATE_MASK;
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&dai_priv->constraint);
}
static void arizona_wm5102_set_dac_comp(struct snd_soc_component *component,
unsigned int rate)
{
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
struct reg_sequence dac_comp[] = {
{ 0x80, 0x3 },
{ ARIZONA_DAC_COMP_1, 0 },
{ ARIZONA_DAC_COMP_2, 0 },
{ 0x80, 0x0 },
};
mutex_lock(&arizona->dac_comp_lock);
dac_comp[1].def = arizona->dac_comp_coeff;
if (rate >= 176400)
dac_comp[2].def = arizona->dac_comp_enabled;
mutex_unlock(&arizona->dac_comp_lock);
regmap_multi_reg_write(arizona->regmap,
dac_comp,
ARRAY_SIZE(dac_comp));
}
static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
int base = dai->driver->base;
int i, sr_val, ret;
/*
* We will need to be more flexible than this in future,
* currently we use a single sample rate for SYSCLK.
*/
for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
if (arizona_sr_vals[i] == params_rate(params))
break;
if (i == ARRAY_SIZE(arizona_sr_vals)) {
arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
params_rate(params));
return -EINVAL;
}
sr_val = i;
switch (priv->arizona->type) {
case WM5102:
case WM8997:
if (arizona_sr_vals[sr_val] >= 88200)
ret = arizona_dvfs_up(component, ARIZONA_DVFS_SR1_RQ);
else
ret = arizona_dvfs_down(component, ARIZONA_DVFS_SR1_RQ);
if (ret) {
arizona_aif_err(dai, "Failed to change DVFS %d\n", ret);
return ret;
}
break;
default:
break;
}
switch (dai_priv->clk) {
case ARIZONA_CLK_SYSCLK:
switch (priv->arizona->type) {
case WM5102:
arizona_wm5102_set_dac_comp(component,
params_rate(params));
break;
default:
break;
}
snd_soc_component_update_bits(component, ARIZONA_SAMPLE_RATE_1,
ARIZONA_SAMPLE_RATE_1_MASK,
sr_val);
if (base)
snd_soc_component_update_bits(component,
base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_RATE_MASK, 0);
break;
case ARIZONA_CLK_ASYNCCLK:
snd_soc_component_update_bits(component,
ARIZONA_ASYNC_SAMPLE_RATE_1,
ARIZONA_ASYNC_SAMPLE_RATE_1_MASK,
sr_val);
if (base)
snd_soc_component_update_bits(component,
base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_RATE_MASK,
8 << ARIZONA_AIF1_RATE_SHIFT);
break;
default:
arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
return -EINVAL;
}
return 0;
}
static bool arizona_aif_cfg_changed(struct snd_soc_component *component,
int base, int bclk, int lrclk, int frame)
{
int val;
val = snd_soc_component_read(component, base + ARIZONA_AIF_BCLK_CTRL);
if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK))
return true;
val = snd_soc_component_read(component, base + ARIZONA_AIF_RX_BCLK_RATE);
if (lrclk != (val & ARIZONA_AIF1RX_BCPF_MASK))
return true;
val = snd_soc_component_read(component, base + ARIZONA_AIF_FRAME_CTRL_1);
if (frame != (val & (ARIZONA_AIF1TX_WL_MASK |
ARIZONA_AIF1TX_SLOT_LEN_MASK)))
return true;
return false;
}
static int arizona_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int base = dai->driver->base;
const int *rates;
int i, ret, val;
int channels = params_channels(params);
int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
int tdm_width = arizona->tdm_width[dai->id - 1];
int tdm_slots = arizona->tdm_slots[dai->id - 1];
int bclk, lrclk, wl, frame, bclk_target;
bool reconfig;
unsigned int aif_tx_state, aif_rx_state;
if (params_rate(params) % 4000)
rates = &arizona_44k1_bclk_rates[0];
else
rates = &arizona_48k_bclk_rates[0];
wl = params_width(params);
if (tdm_slots) {
arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
tdm_slots, tdm_width);
bclk_target = tdm_slots * tdm_width * params_rate(params);
channels = tdm_slots;
} else {
bclk_target = snd_soc_params_to_bclk(params);
tdm_width = wl;
}
if (chan_limit && chan_limit < channels) {
arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
bclk_target /= channels;
bclk_target *= chan_limit;
}
/* Force multiple of 2 channels for I2S mode */
val = snd_soc_component_read(component, base + ARIZONA_AIF_FORMAT);
val &= ARIZONA_AIF1_FMT_MASK;
if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) {
arizona_aif_dbg(dai, "Forcing stereo mode\n");
bclk_target /= channels;
bclk_target *= channels + 1;
}
for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
if (rates[i] >= bclk_target &&
rates[i] % params_rate(params) == 0) {
bclk = i;
break;
}
}
if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
params_rate(params));
return -EINVAL;
}
lrclk = rates[bclk] / params_rate(params);
arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
rates[bclk], rates[bclk] / lrclk);
frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width;
reconfig = arizona_aif_cfg_changed(component, base, bclk, lrclk, frame);
if (reconfig) {
/* Save AIF TX/RX state */
aif_tx_state = snd_soc_component_read(component,
base + ARIZONA_AIF_TX_ENABLES);
aif_rx_state = snd_soc_component_read(component,
base + ARIZONA_AIF_RX_ENABLES);
/* Disable AIF TX/RX before reconfiguring it */
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_TX_ENABLES,
0xff, 0x0);
regmap_update_bits(arizona->regmap,
base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0);
}
ret = arizona_hw_params_rate(substream, params, dai);
if (ret != 0)
goto restore_aif;
if (reconfig) {
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_BCLK_CTRL,
ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_TX_BCLK_RATE,
ARIZONA_AIF1TX_BCPF_MASK, lrclk);
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_RX_BCLK_RATE,
ARIZONA_AIF1RX_BCPF_MASK, lrclk);
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_FRAME_CTRL_1,
ARIZONA_AIF1TX_WL_MASK |
ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
regmap_update_bits(arizona->regmap,
base + ARIZONA_AIF_FRAME_CTRL_2,
ARIZONA_AIF1RX_WL_MASK |
ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
}
restore_aif:
if (reconfig) {
/* Restore AIF TX/RX state */
regmap_update_bits_async(arizona->regmap,
base + ARIZONA_AIF_TX_ENABLES,
0xff, aif_tx_state);
regmap_update_bits(arizona->regmap,
base + ARIZONA_AIF_RX_ENABLES,
0xff, aif_rx_state);
}
return ret;
}
static const char *arizona_dai_clk_str(int clk_id)
{
switch (clk_id) {
case ARIZONA_CLK_SYSCLK:
return "SYSCLK";
case ARIZONA_CLK_ASYNCCLK:
return "ASYNCCLK";
default:
return "Unknown clock";
}
}
static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
struct snd_soc_dapm_route routes[2];
switch (clk_id) {
case ARIZONA_CLK_SYSCLK:
case ARIZONA_CLK_ASYNCCLK:
break;
default:
return -EINVAL;
}
if (clk_id == dai_priv->clk)
return 0;
if (snd_soc_dai_active(dai)) {
dev_err(component->dev, "Can't change clock on active DAI %d\n",
dai->id);
return -EBUSY;
}
dev_dbg(component->dev, "Setting AIF%d to %s\n", dai->id + 1,
arizona_dai_clk_str(clk_id));
memset(&routes, 0, sizeof(routes));
routes[0].sink = dai->driver->capture.stream_name;
routes[1].sink = dai->driver->playback.stream_name;
routes[0].source = arizona_dai_clk_str(dai_priv->clk);
routes[1].source = arizona_dai_clk_str(dai_priv->clk);
snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
routes[0].source = arizona_dai_clk_str(clk_id);
routes[1].source = arizona_dai_clk_str(clk_id);
snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
dai_priv->clk = clk_id;
return snd_soc_dapm_sync(dapm);
}
static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
int base = dai->driver->base;
unsigned int reg;
if (tristate)
reg = ARIZONA_AIF1_TRI;
else
reg = 0;
return snd_soc_component_update_bits(component,
base + ARIZONA_AIF_RATE_CTRL,
ARIZONA_AIF1_TRI, reg);
}
static void arizona_set_channels_to_mask(struct snd_soc_dai *dai,
unsigned int base,
int channels, unsigned int mask)
{
struct snd_soc_component *component = dai->component;
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int slot, i;
for (i = 0; i < channels; ++i) {
slot = ffs(mask) - 1;
if (slot < 0)
return;
regmap_write(arizona->regmap, base + i, slot);
mask &= ~(1 << slot);
}
if (mask)
arizona_aif_warn(dai, "Too many channels in TDM mask\n");
}
static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct arizona_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->arizona;
int base = dai->driver->base;
int rx_max_chan = dai->driver->playback.channels_max;
int tx_max_chan = dai->driver->capture.channels_max;
/* Only support TDM for the physical AIFs */
if (dai->id > ARIZONA_MAX_AIF)
return -ENOTSUPP;
if (slots == 0) {
tx_mask = (1 << tx_max_chan) - 1;
rx_mask = (1 << rx_max_chan) - 1;
}
arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3,
tx_max_chan, tx_mask);
arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11,
rx_max_chan, rx_mask);
arizona->tdm_width[dai->id - 1] = slot_width;
arizona->tdm_slots[dai->id - 1] = slots;
return 0;
}
const struct snd_soc_dai_ops arizona_dai_ops = {
.startup = arizona_startup,
.set_fmt = arizona_set_fmt,
.set_tdm_slot = arizona_set_tdm_slot,
.hw_params = arizona_hw_params,
.set_sysclk = arizona_dai_set_sysclk,
.set_tristate = arizona_set_tristate,
};
EXPORT_SYMBOL_GPL(arizona_dai_ops);
const struct snd_soc_dai_ops arizona_simple_dai_ops = {
.startup = arizona_startup,
.hw_params = arizona_hw_params_rate,
.set_sysclk = arizona_dai_set_sysclk,
};
EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
int arizona_init_dai(struct arizona_priv *priv, int id)
{
struct arizona_dai_priv *dai_priv = &priv->dai[id];
dai_priv->clk = ARIZONA_CLK_SYSCLK;
dai_priv->constraint = arizona_constraint;
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_dai);
static struct {
unsigned int min;
unsigned int max;
u16 fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static const unsigned int pseudo_fref_max[ARIZONA_FLL_MAX_FRATIO] = {
13500000,
6144000,
6144000,
3072000,
3072000,
2822400,
2822400,
1536000,
1536000,
1536000,
1536000,
1536000,
1536000,
1536000,
1536000,
768000,
};
static struct {
unsigned int min;
unsigned int max;
u16 gain;
} fll_gains[] = {
{ 0, 256000, 0 },
{ 256000, 1000000, 2 },
{ 1000000, 13500000, 4 },
};
struct arizona_fll_cfg {
int n;
unsigned int theta;
unsigned int lambda;
int refdiv;
int outdiv;
int fratio;
int gain;
};
static int arizona_validate_fll(struct arizona_fll *fll,
unsigned int Fref,
unsigned int Fout)
{
unsigned int Fvco_min;
if (fll->fout && Fout != fll->fout) {
arizona_fll_err(fll,
"Can't change output on active FLL\n");
return -EINVAL;
}
if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
arizona_fll_err(fll,
"Can't scale %dMHz in to <=13.5MHz\n",
Fref);
return -EINVAL;
}
Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
return 0;
}
static int arizona_find_fratio(unsigned int Fref, int *fratio)
{
int i;
/* Find an appropriate FLL_FRATIO */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
if (fratio)
*fratio = fll_fratios[i].fratio;
return fll_fratios[i].ratio;
}
}
return -EINVAL;
}
static int arizona_calc_fratio(struct arizona_fll *fll,
struct arizona_fll_cfg *cfg,
unsigned int target,
unsigned int Fref, bool sync)
{
int init_ratio, ratio;
int refdiv, div;
/* Fref must be <=13.5MHz, find initial refdiv */
div = 1;
cfg->refdiv = 0;
while (Fref > ARIZONA_FLL_MAX_FREF) {
div *= 2;
Fref /= 2;
cfg->refdiv++;
if (div > ARIZONA_FLL_MAX_REFDIV)
return -EINVAL;
}
/* Find an appropriate FLL_FRATIO */
init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
if (init_ratio < 0) {
arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
Fref);
return init_ratio;
}
switch (fll->arizona->type) {
case WM5102:
case WM8997:
return init_ratio;
case WM5110:
case WM8280:
if (fll->arizona->rev < 3 || sync)
return init_ratio;
break;
default:
if (sync)
return init_ratio;
break;
}
cfg->fratio = init_ratio - 1;
/* Adjust FRATIO/refdiv to avoid integer mode if possible */
refdiv = cfg->refdiv;
arizona_fll_dbg(fll, "pseudo: initial ratio=%u fref=%u refdiv=%u\n",
init_ratio, Fref, refdiv);
while (div <= ARIZONA_FLL_MAX_REFDIV) {
/* start from init_ratio because this may already give a
* fractional N.K
*/
for (ratio = init_ratio; ratio > 0; ratio--) {
if (target % (ratio * Fref)) {
cfg->refdiv = refdiv;
cfg->fratio = ratio - 1;
arizona_fll_dbg(fll,
"pseudo: found fref=%u refdiv=%d(%d) ratio=%d\n",
Fref, refdiv, div, ratio);
return ratio;
}
}
for (ratio = init_ratio + 1; ratio <= ARIZONA_FLL_MAX_FRATIO;
ratio++) {
if ((ARIZONA_FLL_VCO_CORNER / 2) /
(fll->vco_mult * ratio) < Fref) {
arizona_fll_dbg(fll, "pseudo: hit VCO corner\n");
break;
}
if (Fref > pseudo_fref_max[ratio - 1]) {
arizona_fll_dbg(fll,
"pseudo: exceeded max fref(%u) for ratio=%u\n",
pseudo_fref_max[ratio - 1],
ratio);
break;
}
if (target % (ratio * Fref)) {
cfg->refdiv = refdiv;
cfg->fratio = ratio - 1;
arizona_fll_dbg(fll,
"pseudo: found fref=%u refdiv=%d(%d) ratio=%d\n",
Fref, refdiv, div, ratio);
return ratio;
}
}
div *= 2;
Fref /= 2;
refdiv++;
init_ratio = arizona_find_fratio(Fref, NULL);
arizona_fll_dbg(fll,
"pseudo: change fref=%u refdiv=%d(%d) ratio=%u\n",
Fref, refdiv, div, init_ratio);
}
arizona_fll_warn(fll, "Falling back to integer mode operation\n");
return cfg->fratio + 1;
}
static int arizona_calc_fll(struct arizona_fll *fll,
struct arizona_fll_cfg *cfg,
unsigned int Fref, bool sync)
{
unsigned int target, div, gcd_fll;
int i, ratio;
arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
/* Fvco should be over the targt; don't check the upper bound */
div = ARIZONA_FLL_MIN_OUTDIV;
while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
div++;
if (div > ARIZONA_FLL_MAX_OUTDIV)
return -EINVAL;
}
target = fll->fout * div / fll->vco_mult;
cfg->outdiv = div;
arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
/* Find an appropriate FLL_FRATIO and refdiv */
ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
if (ratio < 0)
return ratio;
/* Apply the division for our remaining calculations */
Fref = Fref / (1 << cfg->refdiv);
cfg->n = target / (ratio * Fref);
if (target % (ratio * Fref)) {
gcd_fll = gcd(target, ratio * Fref);
arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
cfg->theta = (target - (cfg->n * ratio * Fref))
/ gcd_fll;
cfg->lambda = (ratio * Fref) / gcd_fll;
} else {
cfg->theta = 0;
cfg->lambda = 0;
}
/* Round down to 16bit range with cost of accuracy lost.
* Denominator must be bigger than numerator so we only
* take care of it.
*/
while (cfg->lambda >= (1 << 16)) {
cfg->theta >>= 1;
cfg->lambda >>= 1;
}
for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
cfg->gain = fll_gains[i].gain;
break;
}
}
if (i == ARRAY_SIZE(fll_gains)) {
arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
Fref);
return -EINVAL;
}
arizona_fll_dbg(fll, "N=%d THETA=%d LAMBDA=%d\n",
cfg->n, cfg->theta, cfg->lambda);
arizona_fll_dbg(fll, "FRATIO=0x%x(%d) OUTDIV=%d REFCLK_DIV=0x%x(%d)\n",
cfg->fratio, ratio, cfg->outdiv,
cfg->refdiv, 1 << cfg->refdiv);
arizona_fll_dbg(fll, "GAIN=0x%x(%d)\n", cfg->gain, 1 << cfg->gain);
return 0;
}
static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
struct arizona_fll_cfg *cfg, int source,
bool sync)
{
regmap_update_bits_async(arizona->regmap, base + 3,
ARIZONA_FLL1_THETA_MASK, cfg->theta);
regmap_update_bits_async(arizona->regmap, base + 4,
ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
regmap_update_bits_async(arizona->regmap, base + 5,
ARIZONA_FLL1_FRATIO_MASK,
cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
regmap_update_bits_async(arizona->regmap, base + 6,
ARIZONA_FLL1_CLK_REF_DIV_MASK |
ARIZONA_FLL1_CLK_REF_SRC_MASK,
cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
if (sync) {
regmap_update_bits(arizona->regmap, base + 0x7,
ARIZONA_FLL1_GAIN_MASK,
cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
} else {
regmap_update_bits(arizona->regmap, base + 0x5,
ARIZONA_FLL1_OUTDIV_MASK,
cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
regmap_update_bits(arizona->regmap, base + 0x9,
ARIZONA_FLL1_GAIN_MASK,
cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
}
regmap_update_bits_async(arizona->regmap, base + 2,
ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
ARIZONA_FLL1_CTRL_UPD | cfg->n);
}
static int arizona_is_enabled_fll(struct arizona_fll *fll, int base)
{
struct arizona *arizona = fll->arizona;
unsigned int reg;
int ret;
ret = regmap_read(arizona->regmap, base + 1, ®);
if (ret != 0) {
arizona_fll_err(fll, "Failed to read current state: %d\n",
ret);
return ret;
}
return reg & ARIZONA_FLL1_ENA;
}
static int arizona_set_fll_clks(struct arizona_fll *fll, int base, bool ena)
{
struct arizona *arizona = fll->arizona;
unsigned int val;
struct clk *clk;
int ret;
ret = regmap_read(arizona->regmap, base + 6, &val);
if (ret != 0) {
arizona_fll_err(fll, "Failed to read current source: %d\n",
ret);
return ret;
}
val &= ARIZONA_FLL1_CLK_REF_SRC_MASK;
val >>= ARIZONA_FLL1_CLK_REF_SRC_SHIFT;
switch (val) {
case ARIZONA_FLL_SRC_MCLK1:
clk = arizona->mclk[ARIZONA_MCLK1];
break;
case ARIZONA_FLL_SRC_MCLK2:
clk = arizona->mclk[ARIZONA_MCLK2];
break;
default:
return 0;
}
if (ena) {
return clk_prepare_enable(clk);
} else {
clk_disable_unprepare(clk);
return 0;
}
}
static int arizona_enable_fll(struct arizona_fll *fll)
{
struct arizona *arizona = fll->arizona;
bool use_sync = false;
int already_enabled = arizona_is_enabled_fll(fll, fll->base);
int sync_enabled = arizona_is_enabled_fll(fll, fll->base + 0x10);
struct arizona_fll_cfg cfg;
int i;
unsigned int val;
if (already_enabled < 0)
return already_enabled;
if (sync_enabled < 0)
return sync_enabled;
if (already_enabled) {
/* Facilitate smooth refclk across the transition */
regmap_update_bits(fll->arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
udelay(32);
regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9,
ARIZONA_FLL1_GAIN_MASK, 0);
if (arizona_is_enabled_fll(fll, fll->base + 0x10) > 0)
arizona_set_fll_clks(fll, fll->base + 0x10, false);
arizona_set_fll_clks(fll, fll->base, false);
}
/*
* If we have both REFCLK and SYNCCLK then enable both,
* otherwise apply the SYNCCLK settings to REFCLK.
*/
if (fll->ref_src >= 0 && fll->ref_freq &&
fll->ref_src != fll->sync_src) {
arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
/* Ref path hardcodes lambda to 65536 when sync is on */
if (fll->sync_src >= 0 && cfg.lambda)
cfg.theta = (cfg.theta * (1 << 16)) / cfg.lambda;
arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
false);
if (fll->sync_src >= 0) {
arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
fll->sync_src, true);
use_sync = true;
}
} else if (fll->sync_src >= 0) {
arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
arizona_apply_fll(arizona, fll->base, &cfg,
fll->sync_src, false);
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
ARIZONA_FLL1_SYNC_ENA, 0);
} else {
arizona_fll_err(fll, "No clocks provided\n");
return -EINVAL;
}
if (already_enabled && !!sync_enabled != use_sync)
arizona_fll_warn(fll, "Synchroniser changed on active FLL\n");
/*
* Increase the bandwidth if we're not using a low frequency
* sync source.
*/
if (use_sync && fll->sync_freq > 100000)
regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
ARIZONA_FLL1_SYNC_BW, 0);
else
regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
ARIZONA_FLL1_SYNC_BW,
ARIZONA_FLL1_SYNC_BW);
if (!already_enabled)
pm_runtime_get_sync(arizona->dev);
if (use_sync) {
arizona_set_fll_clks(fll, fll->base + 0x10, true);
regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
ARIZONA_FLL1_SYNC_ENA,
ARIZONA_FLL1_SYNC_ENA);
}
arizona_set_fll_clks(fll, fll->base, true);
regmap_update_bits_async(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
if (already_enabled)
regmap_update_bits_async(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN, 0);
arizona_fll_dbg(fll, "Waiting for FLL lock...\n");
val = 0;
for (i = 0; i < 15; i++) {
if (i < 5)
usleep_range(200, 400);
else
msleep(20);
regmap_read(arizona->regmap,
ARIZONA_INTERRUPT_RAW_STATUS_5,
&val);
if (val & (ARIZONA_FLL1_CLOCK_OK_STS << (fll->id - 1)))
break;
}
if (i == 15)
arizona_fll_warn(fll, "Timed out waiting for lock\n");
else
arizona_fll_dbg(fll, "FLL locked (%d polls)\n", i);
return 0;
}
static void arizona_disable_fll(struct arizona_fll *fll)
{
struct arizona *arizona = fll->arizona;
bool ref_change, sync_change;
regmap_update_bits_async(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
regmap_update_bits_check(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_ENA, 0, &ref_change);
regmap_update_bits_check(arizona->regmap, fll->base + 0x11,
ARIZONA_FLL1_SYNC_ENA, 0, &sync_change);
regmap_update_bits_async(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN, 0);
if (sync_change)
arizona_set_fll_clks(fll, fll->base + 0x10, false);
if (ref_change) {
arizona_set_fll_clks(fll, fll->base, false);
pm_runtime_put_autosuspend(arizona->dev);
}
}
int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
unsigned int Fref, unsigned int Fout)
{
int ret = 0;
if (fll->ref_src == source && fll->ref_freq == Fref)
return 0;
if (fll->fout && Fref > 0) {
ret = arizona_validate_fll(fll, Fref, fll->fout);
if (ret != 0)
return ret;
}
fll->ref_src = source;
fll->ref_freq = Fref;
if (fll->fout && Fref > 0)
ret = arizona_enable_fll(fll);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
int arizona_set_fll(struct arizona_fll *fll, int source,
unsigned int Fref, unsigned int Fout)
{
int ret = 0;
if (fll->sync_src == source &&
fll->sync_freq == Fref && fll->fout == Fout)
return 0;
if (Fout) {
if (fll->ref_src >= 0) {
ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
if (ret != 0)
return ret;
}
ret = arizona_validate_fll(fll, Fref, Fout);
if (ret != 0)
return ret;
}
fll->sync_src = source;
fll->sync_freq = Fref;
fll->fout = Fout;
if (Fout)
ret = arizona_enable_fll(fll);
else
arizona_disable_fll(fll);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_set_fll);
int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
int ok_irq, struct arizona_fll *fll)
{
unsigned int val;
fll->id = id;
fll->base = base;
fll->arizona = arizona;
fll->sync_src = ARIZONA_FLL_SRC_NONE;
/* Configure default refclk to 32kHz if we have one */
regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
switch (val & ARIZONA_CLK_32K_SRC_MASK) {
case ARIZONA_CLK_SRC_MCLK1:
case ARIZONA_CLK_SRC_MCLK2:
fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
break;
default:
fll->ref_src = ARIZONA_FLL_SRC_NONE;
}
fll->ref_freq = 32768;
snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
"FLL%d clock OK", id);
regmap_update_bits(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN, 0);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_init_fll);
/**
* arizona_set_output_mode - Set the mode of the specified output
*
* @component: Device to configure
* @output: Output number
* @diff: True to set the output to differential mode
*
* Some systems use external analogue switches to connect more
* analogue devices to the CODEC than are supported by the device. In
* some systems this requires changing the switched output from single
* ended to differential mode dynamically at runtime, an operation
* supported using this function.
*
* Most systems have a single static configuration and should use
* platform data instead.
*/
int arizona_set_output_mode(struct snd_soc_component *component, int output,
bool diff)
{
unsigned int reg, val;
if (output < 1 || output > 6)
return -EINVAL;
reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
if (diff)
val = ARIZONA_OUT1_MONO;
else
val = 0;
return snd_soc_component_update_bits(component, reg,
ARIZONA_OUT1_MONO, val);
}
EXPORT_SYMBOL_GPL(arizona_set_output_mode);
static const struct soc_enum arizona_adsp2_rate_enum[] = {
SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
ARIZONA_DSP1_RATE_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
ARIZONA_DSP1_RATE_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
ARIZONA_DSP1_RATE_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
ARIZONA_DSP1_RATE_SHIFT, 0xf,
ARIZONA_RATE_ENUM_SIZE,
arizona_rate_text, arizona_rate_val),
};
const struct snd_kcontrol_new arizona_adsp2_rate_controls[] = {
SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum[0]),
SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum[1]),
SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum[2]),
SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum[3]),
};
EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls);
static bool arizona_eq_filter_unstable(bool mode, __be16 _a, __be16 _b)
{
s16 a = be16_to_cpu(_a);
s16 b = be16_to_cpu(_b);
if (!mode) {
return abs(a) >= 4096;
} else {
if (abs(b) >= 4096)
return true;
return (abs((a << 16) / (4096 - b)) >= 4096 << 4);
}
}
int arizona_eq_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
struct soc_bytes *params = (void *)kcontrol->private_value;
unsigned int val;
__be16 *data;
int len;
int ret;
len = params->num_regs * regmap_get_val_bytes(arizona->regmap);
data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA);
if (!data)
return -ENOMEM;
data[0] &= cpu_to_be16(ARIZONA_EQ1_B1_MODE);
if (arizona_eq_filter_unstable(!!data[0], data[1], data[2]) ||
arizona_eq_filter_unstable(true, data[4], data[5]) ||
arizona_eq_filter_unstable(true, data[8], data[9]) ||
arizona_eq_filter_unstable(true, data[12], data[13]) ||
arizona_eq_filter_unstable(false, data[16], data[17])) {
dev_err(arizona->dev, "Rejecting unstable EQ coefficients\n");
ret = -EINVAL;
goto out;
}
ret = regmap_read(arizona->regmap, params->base, &val);
if (ret != 0)
goto out;
val &= ~ARIZONA_EQ1_B1_MODE;
data[0] |= cpu_to_be16(val);
ret = regmap_raw_write(arizona->regmap, params->base, data, len);
out:
kfree(data);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_eq_coeff_put);
int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
__be16 *data = (__be16 *)ucontrol->value.bytes.data;
s16 val = be16_to_cpu(*data);
if (abs(val) >= 4096) {
dev_err(arizona->dev, "Rejecting unstable LHPF coefficients\n");
return -EINVAL;
}
return snd_soc_bytes_put(kcontrol, ucontrol);
}
EXPORT_SYMBOL_GPL(arizona_lhpf_coeff_put);
int arizona_of_get_audio_pdata(struct arizona *arizona)
{
struct arizona_pdata *pdata = &arizona->pdata;
struct device_node *np = arizona->dev->of_node;
struct property *prop;
const __be32 *cur;
u32 val;
u32 pdm_val[ARIZONA_MAX_PDM_SPK];
int ret;
int count = 0;
count = 0;
of_property_for_each_u32(np, "wlf,inmode", prop, cur, val) {
if (count == ARRAY_SIZE(pdata->inmode))
break;
pdata->inmode[count] = val;
count++;
}
count = 0;
of_property_for_each_u32(np, "wlf,dmic-ref", prop, cur, val) {
if (count == ARRAY_SIZE(pdata->dmic_ref))
break;
pdata->dmic_ref[count] = val;
count++;
}
count = 0;
of_property_for_each_u32(np, "wlf,out-mono", prop, cur, val) {
if (count == ARRAY_SIZE(pdata->out_mono))
break;
pdata->out_mono[count] = !!val;
count++;
}
count = 0;
of_property_for_each_u32(np, "wlf,max-channels-clocked", prop, cur, val) {
if (count == ARRAY_SIZE(pdata->max_channels_clocked))
break;
pdata->max_channels_clocked[count] = val;
count++;
}
count = 0;
of_property_for_each_u32(np, "wlf,out-volume-limit", prop, cur, val) {
if (count == ARRAY_SIZE(pdata->out_vol_limit))
break;
pdata->out_vol_limit[count] = val;
count++;
}
ret = of_property_read_u32_array(np, "wlf,spk-fmt",
pdm_val, ARRAY_SIZE(pdm_val));
if (ret >= 0)
for (count = 0; count < ARRAY_SIZE(pdata->spk_fmt); ++count)
pdata->spk_fmt[count] = pdm_val[count];
ret = of_property_read_u32_array(np, "wlf,spk-mute",
pdm_val, ARRAY_SIZE(pdm_val));
if (ret >= 0)
for (count = 0; count < ARRAY_SIZE(pdata->spk_mute); ++count)
pdata->spk_mute[count] = pdm_val[count];
return 0;
}
EXPORT_SYMBOL_GPL(arizona_of_get_audio_pdata);
MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/arizona.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADAU1381/ADAU1781 CODEC
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "adau1781.h"
static const struct i2c_device_id adau1781_i2c_ids[];
static int adau1781_i2c_probe(struct i2c_client *client)
{
struct regmap_config config;
const struct i2c_device_id *id = i2c_match_id(adau1781_i2c_ids, client);
config = adau1781_regmap_config;
config.val_bits = 8;
config.reg_bits = 16;
return adau1781_probe(&client->dev,
devm_regmap_init_i2c(client, &config),
id->driver_data, NULL);
}
static void adau1781_i2c_remove(struct i2c_client *client)
{
adau17x1_remove(&client->dev);
}
static const struct i2c_device_id adau1781_i2c_ids[] = {
{ "adau1381", ADAU1381 },
{ "adau1781", ADAU1781 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adau1781_i2c_ids);
#if defined(CONFIG_OF)
static const struct of_device_id adau1781_i2c_dt_ids[] = {
{ .compatible = "adi,adau1381", },
{ .compatible = "adi,adau1781", },
{ },
};
MODULE_DEVICE_TABLE(of, adau1781_i2c_dt_ids);
#endif
static struct i2c_driver adau1781_i2c_driver = {
.driver = {
.name = "adau1781",
.of_match_table = of_match_ptr(adau1781_i2c_dt_ids),
},
.probe = adau1781_i2c_probe,
.remove = adau1781_i2c_remove,
.id_table = adau1781_i2c_ids,
};
module_i2c_driver(adau1781_i2c_driver);
MODULE_DESCRIPTION("ASoC ADAU1381/ADAU1781 CODEC I2C driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1781-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt1318-sdw.c -- rt1318 SDCA ALSA SoC amplifier audio driver
//
// Copyright(c) 2022 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/dmi.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "rt1318-sdw.h"
static const struct reg_sequence rt1318_blind_write[] = {
{ 0xc001, 0x43 },
{ 0xc003, 0xa2 },
{ 0xc004, 0x44 },
{ 0xc005, 0x44 },
{ 0xc006, 0x33 },
{ 0xc007, 0x64 },
{ 0xc320, 0x20 },
{ 0xf203, 0x18 },
{ 0xf211, 0x00 },
{ 0xf212, 0x26 },
{ 0xf20d, 0x17 },
{ 0xf214, 0x06 },
{ 0xf20e, 0x00 },
{ 0xf223, 0x7f },
{ 0xf224, 0xdb },
{ 0xf225, 0xee },
{ 0xf226, 0x3f },
{ 0xf227, 0x0f },
{ 0xf21a, 0x78 },
{ 0xf242, 0x3c },
{ 0xc321, 0x0b },
{ 0xc200, 0xd8 },
{ 0xc201, 0x27 },
{ 0xc202, 0x0f },
{ 0xf800, 0x20 },
{ 0xdf00, 0x10 },
{ 0xdf5f, 0x01 },
{ 0xdf60, 0xa7 },
{ 0xc400, 0x0e },
{ 0xc401, 0x43 },
{ 0xc402, 0xe0 },
{ 0xc403, 0x00 },
{ 0xc404, 0x4c },
{ 0xc407, 0x02 },
{ 0xc408, 0x3f },
{ 0xc300, 0x01 },
{ 0xc206, 0x78 },
{ 0xc203, 0x84 },
{ 0xc120, 0xc0 },
{ 0xc121, 0x03 },
{ 0xe000, 0x88 },
{ 0xc321, 0x09 },
{ 0xc322, 0x01 },
{ 0xe706, 0x0f },
{ 0xe707, 0x30 },
{ 0xe806, 0x0f },
{ 0xe807, 0x30 },
{ 0xed00, 0xb0 },
{ 0xce04, 0x02 },
{ 0xce05, 0x63 },
{ 0xce06, 0x68 },
{ 0xce07, 0x07 },
{ 0xcf04, 0x02 },
{ 0xcf05, 0x63 },
{ 0xcf06, 0x68 },
{ 0xcf07, 0x07 },
{ 0xce60, 0xe3 },
{ 0xc130, 0x51 },
{ 0xf102, 0x00 },
{ 0xf103, 0x00 },
{ 0xf104, 0xf5 },
{ 0xf105, 0x06 },
{ 0xf109, 0x9b },
{ 0xf10a, 0x0b },
{ 0xf10b, 0x4c },
{ 0xf10b, 0x5c },
{ 0xf102, 0x00 },
{ 0xf103, 0x00 },
{ 0xf104, 0xf5 },
{ 0xf105, 0x0b },
{ 0xf109, 0x03 },
{ 0xf10a, 0x0b },
{ 0xf10b, 0x4c },
{ 0xf10b, 0x5c },
{ 0xf102, 0x00 },
{ 0xf103, 0x00 },
{ 0xf104, 0xf5 },
{ 0xf105, 0x0c },
{ 0xf109, 0x7f },
{ 0xf10a, 0x0b },
{ 0xf10b, 0x4c },
{ 0xf10b, 0x5c },
{ 0xe604, 0x00 },
{ 0xdb00, 0x0c },
{ 0xdd00, 0x0c },
{ 0xdc19, 0x00 },
{ 0xdc1a, 0xff },
{ 0xdc1b, 0xff },
{ 0xdc1c, 0xff },
{ 0xdc1d, 0x00 },
{ 0xdc1e, 0x00 },
{ 0xdc1f, 0x00 },
{ 0xdc20, 0xff },
{ 0xde19, 0x00 },
{ 0xde1a, 0xff },
{ 0xde1b, 0xff },
{ 0xde1c, 0xff },
{ 0xde1d, 0x00 },
{ 0xde1e, 0x00 },
{ 0xde1f, 0x00 },
{ 0xde20, 0xff },
{ 0xdb32, 0x00 },
{ 0xdd32, 0x00 },
{ 0xdb33, 0x0a },
{ 0xdd33, 0x0a },
{ 0xdb34, 0x1a },
{ 0xdd34, 0x1a },
{ 0xdb17, 0xef },
{ 0xdd17, 0xef },
{ 0xdba7, 0x00 },
{ 0xdba8, 0x64 },
{ 0xdda7, 0x00 },
{ 0xdda8, 0x64 },
{ 0xdb19, 0x40 },
{ 0xdd19, 0x40 },
{ 0xdb00, 0x4c },
{ 0xdb01, 0x79 },
{ 0xdd01, 0x79 },
{ 0xdb04, 0x05 },
{ 0xdb05, 0x03 },
{ 0xdd04, 0x05 },
{ 0xdd05, 0x03 },
{ 0xdbbb, 0x09 },
{ 0xdbbc, 0x30 },
{ 0xdbbd, 0xf0 },
{ 0xdbbe, 0xf1 },
{ 0xddbb, 0x09 },
{ 0xddbc, 0x30 },
{ 0xddbd, 0xf0 },
{ 0xddbe, 0xf1 },
{ 0xdb01, 0x79 },
{ 0xdd01, 0x79 },
{ 0xdc52, 0xef },
{ 0xde52, 0xef },
{ 0x2f55, 0x22 },
};
static const struct reg_default rt1318_reg_defaults[] = {
{ 0x3000, 0x00 },
{ 0x3004, 0x01 },
{ 0x3005, 0x23 },
{ 0x3202, 0x00 },
{ 0x3203, 0x01 },
{ 0x3206, 0x00 },
{ 0xc000, 0x00 },
{ 0xc001, 0x43 },
{ 0xc003, 0x22 },
{ 0xc004, 0x44 },
{ 0xc005, 0x44 },
{ 0xc006, 0x33 },
{ 0xc007, 0x64 },
{ 0xc008, 0x05 },
{ 0xc00a, 0xfc },
{ 0xc00b, 0x0f },
{ 0xc00c, 0x0e },
{ 0xc00d, 0xef },
{ 0xc00e, 0xe5 },
{ 0xc00f, 0xff },
{ 0xc120, 0xc0 },
{ 0xc121, 0x00 },
{ 0xc122, 0x00 },
{ 0xc123, 0x14 },
{ 0xc125, 0x00 },
{ 0xc200, 0x00 },
{ 0xc201, 0x00 },
{ 0xc202, 0x00 },
{ 0xc203, 0x04 },
{ 0xc204, 0x00 },
{ 0xc205, 0x00 },
{ 0xc206, 0x68 },
{ 0xc207, 0x70 },
{ 0xc208, 0x00 },
{ 0xc20a, 0x00 },
{ 0xc20b, 0x01 },
{ 0xc20c, 0x7f },
{ 0xc20d, 0x01 },
{ 0xc20e, 0x7f },
{ 0xc300, 0x00 },
{ 0xc301, 0x00 },
{ 0xc303, 0x80 },
{ 0xc320, 0x00 },
{ 0xc321, 0x09 },
{ 0xc322, 0x02 },
{ 0xc410, 0x04 },
{ 0xc430, 0x00 },
{ 0xc431, 0x00 },
{ 0xca00, 0x10 },
{ 0xca01, 0x00 },
{ 0xca02, 0x0b },
{ 0xca10, 0x10 },
{ 0xca11, 0x00 },
{ 0xca12, 0x0b },
{ 0xdd93, 0x00 },
{ 0xdd94, 0x64 },
{ 0xe300, 0xa0 },
{ 0xed00, 0x80 },
{ 0xed01, 0x0f },
{ 0xed02, 0xff },
{ 0xed03, 0x00 },
{ 0xed04, 0x00 },
{ 0xed05, 0x0f },
{ 0xed06, 0xff },
{ 0xf010, 0x10 },
{ 0xf011, 0xec },
{ 0xf012, 0x68 },
{ 0xf013, 0x21 },
{ 0xf800, 0x00 },
{ 0xf801, 0x12 },
{ 0xf802, 0xe0 },
{ 0xf803, 0x2f },
{ 0xf804, 0x00 },
{ 0xf805, 0x00 },
{ 0xf806, 0x07 },
{ 0xf807, 0xff },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
};
static bool rt1318_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f55:
case 0x3000:
case 0x3004 ... 0x3005:
case 0x3202 ... 0x3203:
case 0x3206:
case 0xc000 ... 0xc00f:
case 0xc120 ... 0xc125:
case 0xc200 ... 0xc20e:
case 0xc300 ... 0xc303:
case 0xc320 ... 0xc322:
case 0xc410:
case 0xc430 ... 0xc431:
case 0xca00 ... 0xca02:
case 0xca10 ... 0xca12:
case 0xcb00 ... 0xcb0b:
case 0xcc00 ... 0xcce5:
case 0xcd00 ... 0xcde5:
case 0xce00 ... 0xce6a:
case 0xcf00 ... 0xcf53:
case 0xd000 ... 0xd0cc:
case 0xd100 ... 0xd1b9:
case 0xdb00 ... 0xdc53:
case 0xdd00 ... 0xde53:
case 0xdf00 ... 0xdf6b:
case 0xe300:
case 0xeb00 ... 0xebcc:
case 0xec00 ... 0xecb9:
case 0xed00 ... 0xed06:
case 0xf010 ... 0xf014:
case 0xf800 ... 0xf807:
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
return true;
default:
return false;
}
}
static bool rt1318_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f55:
case 0x3000 ... 0x3001:
case 0xc000:
case 0xc301:
case 0xc410:
case 0xc430 ... 0xc431:
case 0xdb06:
case 0xdb12:
case 0xdb1d ... 0xdb1f:
case 0xdb35:
case 0xdb37:
case 0xdb8a ... 0xdb92:
case 0xdbc5 ... 0xdbc8:
case 0xdc2b ... 0xdc49:
case 0xdd0b:
case 0xdd12:
case 0xdd1d ... 0xdd1f:
case 0xdd35:
case 0xdd8a ... 0xdd92:
case 0xddc5 ... 0xddc8:
case 0xde2b ... 0xde44:
case 0xdf4a ... 0xdf55:
case 0xe224 ... 0xe23b:
case 0xea01:
case 0xebc5:
case 0xebc8:
case 0xebcb ... 0xebcc:
case 0xed03 ... 0xed06:
case 0xf010 ... 0xf014:
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
return true;
default:
return false;
}
}
static const struct regmap_config rt1318_sdw_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt1318_readable_register,
.volatile_reg = rt1318_volatile_register,
.max_register = 0x41081488,
.reg_defaults = rt1318_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt1318_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt1318_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = BIT(2);
prop->sink_ports = BIT(1);
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
return 0;
}
static int rt1318_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
if (rt1318->hw_init)
return 0;
regcache_cache_only(rt1318->regmap, false);
if (rt1318->first_hw_init) {
regcache_cache_bypass(rt1318->regmap, true);
} else {
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
/* blind write */
regmap_multi_reg_write(rt1318->regmap, rt1318_blind_write,
ARRAY_SIZE(rt1318_blind_write));
if (rt1318->first_hw_init) {
regcache_cache_bypass(rt1318->regmap, false);
regcache_mark_dirty(rt1318->regmap);
}
/* Mark Slave initialization complete */
rt1318->first_hw_init = true;
rt1318->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
static int rt1318_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt1318->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt1318->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt1318_io_init(&slave->dev, slave);
}
static int rt1318_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt1318->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23,
RT1318_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt1318->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23,
RT1318_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
default:
break;
}
return 0;
}
static const char * const rt1318_rx_data_ch_select[] = {
"L,R",
"L,L",
"L,R",
"L,L+R",
"R,L",
"R,R",
"R,L+R",
"L+R,L",
"L+R,R",
"L+R,L+R",
};
static SOC_ENUM_SINGLE_DECL(rt1318_rx_data_ch_enum,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
rt1318_rx_data_ch_select);
static const struct snd_kcontrol_new rt1318_snd_controls[] = {
/* UDMPU Cluster Selection */
SOC_ENUM("RX Channel Select", rt1318_rx_data_ch_enum),
};
static const struct snd_kcontrol_new rt1318_sto_dac =
SOC_DAPM_DOUBLE_R("Switch",
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L),
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R),
0, 1, 1);
static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = {
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Digital Interface */
SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1318_sto_dac),
/* Output */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1318_classd_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
/* Input */
SND_SOC_DAPM_PGA("FB Data", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("FB Gen"),
};
static const struct snd_soc_dapm_route rt1318_dapm_routes[] = {
{ "DAC", "Switch", "DP1RX" },
{ "CLASS D", NULL, "DAC" },
{ "SPOL", NULL, "CLASS D" },
{ "SPOR", NULL, "CLASS D" },
{ "FB Data", NULL, "FB Gen" },
{ "DP2TX", NULL, "FB Data" },
};
static int rt1318_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt1318_sdw_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt1318_sdw_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1318_sdw_priv *rt1318 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config;
struct sdw_port_config port_config;
enum sdw_data_direction direction;
struct sdw_stream_runtime *sdw_stream;
int retval, port, num_channels, ch_mask;
unsigned int sampling_rate;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt1318->sdw_slave)
return -EINVAL;
/* SoundWire specific configuration */
/* port 1 for playback */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
direction = SDW_DATA_DIR_RX;
port = 1;
} else {
direction = SDW_DATA_DIR_TX;
port = 2;
}
num_channels = params_channels(params);
ch_mask = (1 << num_channels) - 1;
stream_config.frame_rate = params_rate(params);
stream_config.ch_count = num_channels;
stream_config.bps = snd_pcm_format_width(params_format(params));
stream_config.direction = direction;
port_config.ch_mask = ch_mask;
port_config.num = port;
retval = sdw_stream_add_slave(rt1318->sdw_slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
/* sampling rate configuration */
switch (params_rate(params)) {
case 16000:
sampling_rate = RT1318_SDCA_RATE_16000HZ;
break;
case 32000:
sampling_rate = RT1318_SDCA_RATE_32000HZ;
break;
case 44100:
sampling_rate = RT1318_SDCA_RATE_44100HZ;
break;
case 48000:
sampling_rate = RT1318_SDCA_RATE_48000HZ;
break;
case 96000:
sampling_rate = RT1318_SDCA_RATE_96000HZ;
break;
case 192000:
sampling_rate = RT1318_SDCA_RATE_192000HZ;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set sampling frequency */
regmap_write(rt1318->regmap,
SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
return 0;
}
static int rt1318_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1318_sdw_priv *rt1318 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt1318->sdw_slave)
return -EINVAL;
sdw_stream_remove_slave(rt1318->sdw_slave, sdw_stream);
return 0;
}
/*
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
* port_prep are not defined for now
*/
static const struct sdw_slave_ops rt1318_slave_ops = {
.read_prop = rt1318_read_prop,
.update_status = rt1318_update_status,
};
static int rt1318_sdw_component_probe(struct snd_soc_component *component)
{
int ret;
struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component);
rt1318->component = component;
if (!rt1318->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
dev_dbg(&rt1318->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
if (ret < 0 && ret != -EACCES)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_component_sdw_rt1318 = {
.probe = rt1318_sdw_component_probe,
.controls = rt1318_snd_controls,
.num_controls = ARRAY_SIZE(rt1318_snd_controls),
.dapm_widgets = rt1318_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets),
.dapm_routes = rt1318_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes),
.endianness = 1,
};
static const struct snd_soc_dai_ops rt1318_aif_dai_ops = {
.hw_params = rt1318_sdw_hw_params,
.hw_free = rt1318_sdw_pcm_hw_free,
.set_stream = rt1318_set_sdw_stream,
.shutdown = rt1318_sdw_shutdown,
};
#define RT1318_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver rt1318_sdw_dai[] = {
{
.name = "rt1318-aif",
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1318_STEREO_RATES,
.formats = RT1318_FORMATS,
},
.capture = {
.stream_name = "DP2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT1318_STEREO_RATES,
.formats = RT1318_FORMATS,
},
.ops = &rt1318_aif_dai_ops,
},
};
static int rt1318_sdw_init(struct device *dev, struct regmap *regmap,
struct sdw_slave *slave)
{
struct rt1318_sdw_priv *rt1318;
int ret;
rt1318 = devm_kzalloc(dev, sizeof(*rt1318), GFP_KERNEL);
if (!rt1318)
return -ENOMEM;
dev_set_drvdata(dev, rt1318);
rt1318->sdw_slave = slave;
rt1318->regmap = regmap;
regcache_cache_only(rt1318->regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt1318->hw_init = false;
rt1318->first_hw_init = false;
ret = devm_snd_soc_register_component(dev,
&soc_component_sdw_rt1318,
rt1318_sdw_dai,
ARRAY_SIZE(rt1318_sdw_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return ret;
}
static int rt1318_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &rt1318_sdw_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt1318_sdw_init(&slave->dev, regmap, slave);
}
static int rt1318_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt1318_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1318, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt1318_id);
static int __maybe_unused rt1318_dev_suspend(struct device *dev)
{
struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
if (!rt1318->hw_init)
return 0;
regcache_cache_only(rt1318->regmap, true);
return 0;
}
#define RT1318_PROBE_TIMEOUT 5000
static int __maybe_unused rt1318_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
unsigned long time;
if (!rt1318->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT1318_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt1318->regmap, false);
regcache_sync(rt1318->regmap);
return 0;
}
static const struct dev_pm_ops rt1318_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume)
SET_RUNTIME_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume, NULL)
};
static struct sdw_driver rt1318_sdw_driver = {
.driver = {
.name = "rt1318-sdca",
.owner = THIS_MODULE,
.pm = &rt1318_pm,
},
.probe = rt1318_sdw_probe,
.remove = rt1318_sdw_remove,
.ops = &rt1318_slave_ops,
.id_table = rt1318_id,
};
module_sdw_driver(rt1318_sdw_driver);
MODULE_DESCRIPTION("ASoC RT1318 driver SDCA SDW");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt1318-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2022, The Linux Foundation. All rights reserved.
#include <linux/export.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include "lpass-macro-common.h"
struct lpass_macro *lpass_macro_pds_init(struct device *dev)
{
struct lpass_macro *l_pds;
int ret;
if (!of_property_present(dev->of_node, "power-domains"))
return NULL;
l_pds = devm_kzalloc(dev, sizeof(*l_pds), GFP_KERNEL);
if (!l_pds)
return ERR_PTR(-ENOMEM);
l_pds->macro_pd = dev_pm_domain_attach_by_name(dev, "macro");
if (IS_ERR_OR_NULL(l_pds->macro_pd)) {
ret = l_pds->macro_pd ? PTR_ERR(l_pds->macro_pd) : -ENODATA;
goto macro_err;
}
ret = pm_runtime_resume_and_get(l_pds->macro_pd);
if (ret < 0)
goto macro_sync_err;
l_pds->dcodec_pd = dev_pm_domain_attach_by_name(dev, "dcodec");
if (IS_ERR_OR_NULL(l_pds->dcodec_pd)) {
ret = l_pds->dcodec_pd ? PTR_ERR(l_pds->dcodec_pd) : -ENODATA;
goto dcodec_err;
}
ret = pm_runtime_resume_and_get(l_pds->dcodec_pd);
if (ret < 0)
goto dcodec_sync_err;
return l_pds;
dcodec_sync_err:
dev_pm_domain_detach(l_pds->dcodec_pd, false);
dcodec_err:
pm_runtime_put(l_pds->macro_pd);
macro_sync_err:
dev_pm_domain_detach(l_pds->macro_pd, false);
macro_err:
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(lpass_macro_pds_init);
void lpass_macro_pds_exit(struct lpass_macro *pds)
{
if (pds) {
pm_runtime_put(pds->macro_pd);
dev_pm_domain_detach(pds->macro_pd, false);
pm_runtime_put(pds->dcodec_pd);
dev_pm_domain_detach(pds->dcodec_pd, false);
}
}
EXPORT_SYMBOL_GPL(lpass_macro_pds_exit);
MODULE_DESCRIPTION("Common macro driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/lpass-macro-common.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt5682-sdw.c -- RT5682 ALSA SoC audio component driver
//
// Copyright 2019 Realtek Semiconductor Corp.
// Author: Oder Chiou <[email protected]>
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/acpi.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/mutex.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/sdw.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rt5682.h"
#define RT5682_SDW_ADDR_L 0x3000
#define RT5682_SDW_ADDR_H 0x3001
#define RT5682_SDW_DATA_L 0x3004
#define RT5682_SDW_DATA_H 0x3005
#define RT5682_SDW_CMD 0x3008
static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val)
{
struct device *dev = context;
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
unsigned int data_l, data_h;
regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0);
regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h);
regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l);
*val = (data_h << 8) | data_l;
dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val);
return 0;
}
static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val)
{
struct device *dev = context;
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1);
regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff);
regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff));
dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
return 0;
}
static const struct regmap_config rt5682_sdw_indirect_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = RT5682_I2C_MODE,
.volatile_reg = rt5682_volatile_register,
.readable_reg = rt5682_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5682_reg,
.num_reg_defaults = RT5682_REG_NUM,
.use_single_read = true,
.use_single_write = true,
.reg_read = rt5682_sdw_read,
.reg_write = rt5682_sdw_write,
};
static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config = {0};
struct sdw_port_config port_config = {0};
struct sdw_stream_runtime *sdw_stream;
int retval;
unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -ENOMEM;
if (!rt5682->slave)
return -EINVAL;
/* SoundWire specific configuration */
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_config.num = 1;
else
port_config.num = 2;
retval = sdw_stream_add_slave(rt5682->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
switch (params_rate(params)) {
case 48000:
val_p = RT5682_SDW_REF_1_48K;
val_c = RT5682_SDW_REF_2_48K;
break;
case 96000:
val_p = RT5682_SDW_REF_1_96K;
val_c = RT5682_SDW_REF_2_96K;
break;
case 192000:
val_p = RT5682_SDW_REF_1_192K;
val_c = RT5682_SDW_REF_2_192K;
break;
case 32000:
val_p = RT5682_SDW_REF_1_32K;
val_c = RT5682_SDW_REF_2_32K;
break;
case 24000:
val_p = RT5682_SDW_REF_1_24K;
val_c = RT5682_SDW_REF_2_24K;
break;
case 16000:
val_p = RT5682_SDW_REF_1_16K;
val_c = RT5682_SDW_REF_2_16K;
break;
case 12000:
val_p = RT5682_SDW_REF_1_12K;
val_c = RT5682_SDW_REF_2_12K;
break;
case 8000:
val_p = RT5682_SDW_REF_1_8K;
val_c = RT5682_SDW_REF_2_8K;
break;
case 44100:
val_p = RT5682_SDW_REF_1_44K;
val_c = RT5682_SDW_REF_2_44K;
break;
case 88200:
val_p = RT5682_SDW_REF_1_88K;
val_c = RT5682_SDW_REF_2_88K;
break;
case 176400:
val_p = RT5682_SDW_REF_1_176K;
val_c = RT5682_SDW_REF_2_176K;
break;
case 22050:
val_p = RT5682_SDW_REF_1_22K;
val_c = RT5682_SDW_REF_2_22K;
break;
case 11025:
val_p = RT5682_SDW_REF_1_11K;
val_c = RT5682_SDW_REF_2_11K;
break;
default:
return -EINVAL;
}
if (params_rate(params) <= 48000) {
osr_p = RT5682_DAC_OSR_D_8;
osr_c = RT5682_ADC_OSR_D_8;
} else if (params_rate(params) <= 96000) {
osr_p = RT5682_DAC_OSR_D_4;
osr_c = RT5682_ADC_OSR_D_4;
} else {
osr_p = RT5682_DAC_OSR_D_2;
osr_c = RT5682_ADC_OSR_D_2;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
RT5682_SDW_REF_1_MASK, val_p);
regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
RT5682_DAC_OSR_MASK, osr_p);
} else {
regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
RT5682_SDW_REF_2_MASK, val_c);
regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
RT5682_ADC_OSR_MASK, osr_c);
}
return retval;
}
static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt5682->slave)
return -EINVAL;
sdw_stream_remove_slave(rt5682->slave, sdw_stream);
return 0;
}
static const struct snd_soc_dai_ops rt5682_sdw_ops = {
.hw_params = rt5682_sdw_hw_params,
.hw_free = rt5682_sdw_hw_free,
.set_stream = rt5682_set_sdw_stream,
.shutdown = rt5682_sdw_shutdown,
};
static struct snd_soc_dai_driver rt5682_dai[] = {
{
.name = "rt5682-aif1",
.id = RT5682_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.ops = &rt5682_aif1_dai_ops,
},
{
.name = "rt5682-aif2",
.id = RT5682_AIF2,
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.ops = &rt5682_aif2_dai_ops,
},
{
.name = "rt5682-sdw",
.id = RT5682_SDW,
.playback = {
.stream_name = "SDW Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.capture = {
.stream_name = "SDW Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682_STEREO_RATES,
.formats = RT5682_FORMATS,
},
.ops = &rt5682_sdw_ops,
},
};
static int rt5682_sdw_init(struct device *dev, struct regmap *regmap,
struct sdw_slave *slave)
{
struct rt5682_priv *rt5682;
int ret;
rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL);
if (!rt5682)
return -ENOMEM;
dev_set_drvdata(dev, rt5682);
rt5682->slave = slave;
rt5682->sdw_regmap = regmap;
rt5682->is_sdw = true;
mutex_init(&rt5682->disable_irq_lock);
rt5682->regmap = devm_regmap_init(dev, NULL, dev,
&rt5682_sdw_indirect_regmap);
if (IS_ERR(rt5682->regmap)) {
ret = PTR_ERR(rt5682->regmap);
dev_err(dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = rt5682_get_ldo1(rt5682, dev);
if (ret)
return ret;
regcache_cache_only(rt5682->sdw_regmap, true);
regcache_cache_only(rt5682->regmap, true);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt5682->hw_init = false;
rt5682->first_hw_init = false;
mutex_init(&rt5682->calibrate_mutex);
INIT_DELAYED_WORK(&rt5682->jack_detect_work,
rt5682_jack_detect_handler);
ret = devm_snd_soc_register_component(dev,
&rt5682_soc_component_dev,
rt5682_dai, ARRAY_SIZE(rt5682_dai));
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return ret;
}
static int rt5682_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
int ret = 0, loop = 10;
unsigned int val;
rt5682->disable_irq = false;
if (rt5682->hw_init)
return 0;
regcache_cache_only(rt5682->sdw_regmap, false);
regcache_cache_only(rt5682->regmap, false);
if (rt5682->first_hw_init)
regcache_cache_bypass(rt5682->regmap, true);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!rt5682->first_hw_init)
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
pm_runtime_get_noresume(&slave->dev);
while (loop > 0) {
regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
if (val == DEVICE_ID)
break;
dev_warn(dev, "Device with ID register %x is not rt5682\n", val);
usleep_range(30000, 30005);
loop--;
}
if (val != DEVICE_ID) {
dev_err(dev, "Device with ID register %x is not rt5682\n", val);
ret = -ENODEV;
goto err_nodev;
}
rt5682_calibrate(rt5682);
if (rt5682->first_hw_init) {
regcache_cache_bypass(rt5682->regmap, false);
regcache_mark_dirty(rt5682->regmap);
regcache_sync(rt5682->regmap);
/* volatile registers */
regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
goto reinit;
}
rt5682_apply_patch_list(rt5682, dev);
regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
/* Soundwire */
regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266);
regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700);
regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006);
regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600);
regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f);
regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000);
regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000);
regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK,
RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK,
RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW);
regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd142);
regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3,
RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1,
RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
RT5682_POW_IRQ | RT5682_POW_JDH |
RT5682_POW_ANA, RT5682_POW_IRQ |
RT5682_POW_JDH | RT5682_POW_ANA);
regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
RT5682_PWR_JDH, RT5682_PWR_JDH);
regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK,
RT5682_JD1_EN | RT5682_JD1_IRQ_PUL);
reinit:
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work, msecs_to_jiffies(250));
/* Mark Slave initialization complete */
rt5682->hw_init = true;
rt5682->first_hw_init = true;
err_nodev:
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete: %d\n", __func__, ret);
return ret;
}
static bool rt5682_sdw_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00e0:
case 0x00f0:
case 0x3000:
case 0x3001:
case 0x3004:
case 0x3005:
case 0x3008:
return true;
default:
return false;
}
}
static const struct regmap_config rt5682_sdw_regmap = {
.name = "sdw",
.reg_bits = 32,
.val_bits = 8,
.max_register = RT5682_I2C_MODE,
.readable_reg = rt5682_sdw_readable_register,
.cache_type = REGCACHE_NONE,
.use_single_read = true,
.use_single_write = true,
};
static int rt5682_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt5682->hw_init = false;
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt5682->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt5682_io_init(&slave->dev, slave);
}
static int rt5682_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = false;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x4; /* BITMAP: 00000100 */
prop->sink_ports = 0x2; /* BITMAP: 00000010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 20;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
/* Bus clock frequency */
#define RT5682_CLK_FREQ_9600000HZ 9600000
#define RT5682_CLK_FREQ_12000000HZ 12000000
#define RT5682_CLK_FREQ_6000000HZ 6000000
#define RT5682_CLK_FREQ_4800000HZ 4800000
#define RT5682_CLK_FREQ_2400000HZ 2400000
#define RT5682_CLK_FREQ_12288000HZ 12288000
static int rt5682_clock_config(struct device *dev)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
unsigned int clk_freq, value;
clk_freq = (rt5682->params.curr_dr_freq >> 1);
switch (clk_freq) {
case RT5682_CLK_FREQ_12000000HZ:
value = 0x0;
break;
case RT5682_CLK_FREQ_6000000HZ:
value = 0x1;
break;
case RT5682_CLK_FREQ_9600000HZ:
value = 0x2;
break;
case RT5682_CLK_FREQ_4800000HZ:
value = 0x3;
break;
case RT5682_CLK_FREQ_2400000HZ:
value = 0x4;
break;
case RT5682_CLK_FREQ_12288000HZ:
value = 0x5;
break;
default:
return -EINVAL;
}
regmap_write(rt5682->sdw_regmap, 0xe0, value);
regmap_write(rt5682->sdw_regmap, 0xf0, value);
dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
return 0;
}
static int rt5682_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
int ret;
memcpy(&rt5682->params, params, sizeof(*params));
ret = rt5682_clock_config(&slave->dev);
if (ret < 0)
dev_err(&slave->dev, "Invalid clk config");
return ret;
}
static int rt5682_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
dev_dbg(&slave->dev,
"%s control_port_stat=%x", __func__, status->control_port);
mutex_lock(&rt5682->disable_irq_lock);
if (status->control_port & 0x4 && !rt5682->disable_irq) {
mod_delayed_work(system_power_efficient_wq,
&rt5682->jack_detect_work, msecs_to_jiffies(rt5682->irq_work_delay_time));
}
mutex_unlock(&rt5682->disable_irq_lock);
return 0;
}
static const struct sdw_slave_ops rt5682_slave_ops = {
.read_prop = rt5682_read_prop,
.interrupt_callback = rt5682_interrupt_callback,
.update_status = rt5682_update_status,
.bus_config = rt5682_bus_config,
};
static int rt5682_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &rt5682_sdw_regmap);
if (IS_ERR(regmap))
return -EINVAL;
return rt5682_sdw_init(&slave->dev, regmap, slave);
}
static int rt5682_sdw_remove(struct sdw_slave *slave)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
if (rt5682->hw_init)
cancel_delayed_work_sync(&rt5682->jack_detect_work);
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt5682_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x5682, 0x2, 0, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt5682_id);
static int __maybe_unused rt5682_dev_suspend(struct device *dev)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
if (!rt5682->hw_init)
return 0;
cancel_delayed_work_sync(&rt5682->jack_detect_work);
regcache_cache_only(rt5682->sdw_regmap, true);
regcache_cache_only(rt5682->regmap, true);
regcache_mark_dirty(rt5682->regmap);
return 0;
}
static int __maybe_unused rt5682_dev_system_suspend(struct device *dev)
{
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
struct sdw_slave *slave = dev_to_sdw_dev(dev);
int ret;
if (!rt5682->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt5682->disable_irq_lock);
rt5682->disable_irq = true;
ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1,
SDW_SCP_INT1_IMPL_DEF, 0);
mutex_unlock(&rt5682->disable_irq_lock);
if (ret < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable imp-def interrupts\n:", __func__);
}
return rt5682_dev_suspend(dev);
}
static int __maybe_unused rt5682_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
unsigned long time;
if (!rt5682->first_hw_init)
return 0;
if (!slave->unattach_request) {
if (rt5682->disable_irq == true) {
mutex_lock(&rt5682->disable_irq_lock);
sdw_write_no_pm(slave, SDW_SCP_INTMASK1, SDW_SCP_INT1_IMPL_DEF);
rt5682->disable_irq = false;
mutex_unlock(&rt5682->disable_irq_lock);
}
goto regmap_sync;
}
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt5682->sdw_regmap, false);
regcache_cache_only(rt5682->regmap, false);
regcache_sync(rt5682->regmap);
return 0;
}
static const struct dev_pm_ops rt5682_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt5682_dev_system_suspend, rt5682_dev_resume)
SET_RUNTIME_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume, NULL)
};
static struct sdw_driver rt5682_sdw_driver = {
.driver = {
.name = "rt5682",
.owner = THIS_MODULE,
.pm = &rt5682_pm,
},
.probe = rt5682_sdw_probe,
.remove = rt5682_sdw_remove,
.ops = &rt5682_slave_ops,
.id_table = rt5682_id,
};
module_sdw_driver(rt5682_sdw_driver);
MODULE_DESCRIPTION("ASoC RT5682 driver SDW");
MODULE_AUTHOR("Oder Chiou <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5682-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SSM4567 amplifier audio driver
*
* Copyright 2014 Google Chromium project.
* Author: Anatol Pomozov <[email protected]>
*
* Based on code copyright/by:
* Copyright 2013 Analog Devices Inc.
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#define SSM4567_REG_POWER_CTRL 0x00
#define SSM4567_REG_AMP_SNS_CTRL 0x01
#define SSM4567_REG_DAC_CTRL 0x02
#define SSM4567_REG_DAC_VOLUME 0x03
#define SSM4567_REG_SAI_CTRL_1 0x04
#define SSM4567_REG_SAI_CTRL_2 0x05
#define SSM4567_REG_SAI_PLACEMENT_1 0x06
#define SSM4567_REG_SAI_PLACEMENT_2 0x07
#define SSM4567_REG_SAI_PLACEMENT_3 0x08
#define SSM4567_REG_SAI_PLACEMENT_4 0x09
#define SSM4567_REG_SAI_PLACEMENT_5 0x0a
#define SSM4567_REG_SAI_PLACEMENT_6 0x0b
#define SSM4567_REG_BATTERY_V_OUT 0x0c
#define SSM4567_REG_LIMITER_CTRL_1 0x0d
#define SSM4567_REG_LIMITER_CTRL_2 0x0e
#define SSM4567_REG_LIMITER_CTRL_3 0x0f
#define SSM4567_REG_STATUS_1 0x10
#define SSM4567_REG_STATUS_2 0x11
#define SSM4567_REG_FAULT_CTRL 0x12
#define SSM4567_REG_PDM_CTRL 0x13
#define SSM4567_REG_MCLK_RATIO 0x14
#define SSM4567_REG_BOOST_CTRL_1 0x15
#define SSM4567_REG_BOOST_CTRL_2 0x16
#define SSM4567_REG_SOFT_RESET 0xff
/* POWER_CTRL */
#define SSM4567_POWER_APWDN_EN BIT(7)
#define SSM4567_POWER_BSNS_PWDN BIT(6)
#define SSM4567_POWER_VSNS_PWDN BIT(5)
#define SSM4567_POWER_ISNS_PWDN BIT(4)
#define SSM4567_POWER_BOOST_PWDN BIT(3)
#define SSM4567_POWER_AMP_PWDN BIT(2)
#define SSM4567_POWER_VBAT_ONLY BIT(1)
#define SSM4567_POWER_SPWDN BIT(0)
/* DAC_CTRL */
#define SSM4567_DAC_HV BIT(7)
#define SSM4567_DAC_MUTE BIT(6)
#define SSM4567_DAC_HPF BIT(5)
#define SSM4567_DAC_LPM BIT(4)
#define SSM4567_DAC_FS_MASK 0x7
#define SSM4567_DAC_FS_8000_12000 0x0
#define SSM4567_DAC_FS_16000_24000 0x1
#define SSM4567_DAC_FS_32000_48000 0x2
#define SSM4567_DAC_FS_64000_96000 0x3
#define SSM4567_DAC_FS_128000_192000 0x4
/* SAI_CTRL_1 */
#define SSM4567_SAI_CTRL_1_BCLK BIT(6)
#define SSM4567_SAI_CTRL_1_TDM_BLCKS_MASK (0x3 << 4)
#define SSM4567_SAI_CTRL_1_TDM_BLCKS_32 (0x0 << 4)
#define SSM4567_SAI_CTRL_1_TDM_BLCKS_48 (0x1 << 4)
#define SSM4567_SAI_CTRL_1_TDM_BLCKS_64 (0x2 << 4)
#define SSM4567_SAI_CTRL_1_FSYNC BIT(3)
#define SSM4567_SAI_CTRL_1_LJ BIT(2)
#define SSM4567_SAI_CTRL_1_TDM BIT(1)
#define SSM4567_SAI_CTRL_1_PDM BIT(0)
/* SAI_CTRL_2 */
#define SSM4567_SAI_CTRL_2_AUTO_SLOT BIT(3)
#define SSM4567_SAI_CTRL_2_TDM_SLOT_MASK 0x7
#define SSM4567_SAI_CTRL_2_TDM_SLOT(x) (x)
struct ssm4567 {
struct regmap *regmap;
};
static const struct reg_default ssm4567_reg_defaults[] = {
{ SSM4567_REG_POWER_CTRL, 0x81 },
{ SSM4567_REG_AMP_SNS_CTRL, 0x09 },
{ SSM4567_REG_DAC_CTRL, 0x32 },
{ SSM4567_REG_DAC_VOLUME, 0x40 },
{ SSM4567_REG_SAI_CTRL_1, 0x00 },
{ SSM4567_REG_SAI_CTRL_2, 0x08 },
{ SSM4567_REG_SAI_PLACEMENT_1, 0x01 },
{ SSM4567_REG_SAI_PLACEMENT_2, 0x20 },
{ SSM4567_REG_SAI_PLACEMENT_3, 0x32 },
{ SSM4567_REG_SAI_PLACEMENT_4, 0x07 },
{ SSM4567_REG_SAI_PLACEMENT_5, 0x07 },
{ SSM4567_REG_SAI_PLACEMENT_6, 0x07 },
{ SSM4567_REG_BATTERY_V_OUT, 0x00 },
{ SSM4567_REG_LIMITER_CTRL_1, 0xa4 },
{ SSM4567_REG_LIMITER_CTRL_2, 0x73 },
{ SSM4567_REG_LIMITER_CTRL_3, 0x00 },
{ SSM4567_REG_STATUS_1, 0x00 },
{ SSM4567_REG_STATUS_2, 0x00 },
{ SSM4567_REG_FAULT_CTRL, 0x30 },
{ SSM4567_REG_PDM_CTRL, 0x40 },
{ SSM4567_REG_MCLK_RATIO, 0x11 },
{ SSM4567_REG_BOOST_CTRL_1, 0x03 },
{ SSM4567_REG_BOOST_CTRL_2, 0x00 },
{ SSM4567_REG_SOFT_RESET, 0x00 },
};
static bool ssm4567_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SSM4567_REG_POWER_CTRL ... SSM4567_REG_BOOST_CTRL_2:
return true;
default:
return false;
}
}
static bool ssm4567_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SSM4567_REG_POWER_CTRL ... SSM4567_REG_SAI_PLACEMENT_6:
case SSM4567_REG_LIMITER_CTRL_1 ... SSM4567_REG_LIMITER_CTRL_3:
case SSM4567_REG_FAULT_CTRL ... SSM4567_REG_BOOST_CTRL_2:
/* The datasheet states that soft reset register is read-only,
* but logically it is write-only. */
case SSM4567_REG_SOFT_RESET:
return true;
default:
return false;
}
}
static bool ssm4567_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SSM4567_REG_BATTERY_V_OUT:
case SSM4567_REG_STATUS_1 ... SSM4567_REG_STATUS_2:
case SSM4567_REG_SOFT_RESET:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_MINMAX_MUTE(ssm4567_vol_tlv, -7125, 2400);
static const struct snd_kcontrol_new ssm4567_snd_controls[] = {
SOC_SINGLE_TLV("Master Playback Volume", SSM4567_REG_DAC_VOLUME, 0,
0xff, 1, ssm4567_vol_tlv),
SOC_SINGLE("DAC Low Power Mode Switch", SSM4567_REG_DAC_CTRL, 4, 1, 0),
SOC_SINGLE("DAC High Pass Filter Switch", SSM4567_REG_DAC_CTRL,
5, 1, 0),
};
static const struct snd_kcontrol_new ssm4567_amplifier_boost_control =
SOC_DAPM_SINGLE("Switch", SSM4567_REG_POWER_CTRL, 1, 1, 1);
static const struct snd_soc_dapm_widget ssm4567_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM4567_REG_POWER_CTRL, 2, 1),
SND_SOC_DAPM_SWITCH("Amplifier Boost", SSM4567_REG_POWER_CTRL, 3, 1,
&ssm4567_amplifier_boost_control),
SND_SOC_DAPM_SIGGEN("Sense"),
SND_SOC_DAPM_PGA("Current Sense", SSM4567_REG_POWER_CTRL, 4, 1, NULL, 0),
SND_SOC_DAPM_PGA("Voltage Sense", SSM4567_REG_POWER_CTRL, 5, 1, NULL, 0),
SND_SOC_DAPM_PGA("VBAT Sense", SSM4567_REG_POWER_CTRL, 6, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route ssm4567_routes[] = {
{ "OUT", NULL, "Amplifier Boost" },
{ "Amplifier Boost", "Switch", "DAC" },
{ "OUT", NULL, "DAC" },
{ "Current Sense", NULL, "Sense" },
{ "Voltage Sense", NULL, "Sense" },
{ "VBAT Sense", NULL, "Sense" },
{ "Capture Sense", NULL, "Current Sense" },
{ "Capture Sense", NULL, "Voltage Sense" },
{ "Capture Sense", NULL, "VBAT Sense" },
};
static int ssm4567_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ssm4567 *ssm4567 = snd_soc_component_get_drvdata(component);
unsigned int rate = params_rate(params);
unsigned int dacfs;
if (rate >= 8000 && rate <= 12000)
dacfs = SSM4567_DAC_FS_8000_12000;
else if (rate >= 16000 && rate <= 24000)
dacfs = SSM4567_DAC_FS_16000_24000;
else if (rate >= 32000 && rate <= 48000)
dacfs = SSM4567_DAC_FS_32000_48000;
else if (rate >= 64000 && rate <= 96000)
dacfs = SSM4567_DAC_FS_64000_96000;
else if (rate >= 128000 && rate <= 192000)
dacfs = SSM4567_DAC_FS_128000_192000;
else
return -EINVAL;
return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
SSM4567_DAC_FS_MASK, dacfs);
}
static int ssm4567_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct ssm4567 *ssm4567 = snd_soc_component_get_drvdata(dai->component);
unsigned int val;
val = mute ? SSM4567_DAC_MUTE : 0;
return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
SSM4567_DAC_MUTE, val);
}
static int ssm4567_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int width)
{
struct ssm4567 *ssm4567 = snd_soc_dai_get_drvdata(dai);
unsigned int blcks;
int slot;
int ret;
if (tx_mask == 0)
return -EINVAL;
if (rx_mask && rx_mask != tx_mask)
return -EINVAL;
slot = __ffs(tx_mask);
if (tx_mask != BIT(slot))
return -EINVAL;
switch (width) {
case 32:
blcks = SSM4567_SAI_CTRL_1_TDM_BLCKS_32;
break;
case 48:
blcks = SSM4567_SAI_CTRL_1_TDM_BLCKS_48;
break;
case 64:
blcks = SSM4567_SAI_CTRL_1_TDM_BLCKS_64;
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(ssm4567->regmap, SSM4567_REG_SAI_CTRL_2,
SSM4567_SAI_CTRL_2_AUTO_SLOT | SSM4567_SAI_CTRL_2_TDM_SLOT_MASK,
SSM4567_SAI_CTRL_2_TDM_SLOT(slot));
if (ret)
return ret;
return regmap_update_bits(ssm4567->regmap, SSM4567_REG_SAI_CTRL_1,
SSM4567_SAI_CTRL_1_TDM_BLCKS_MASK, blcks);
}
static int ssm4567_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct ssm4567 *ssm4567 = snd_soc_dai_get_drvdata(dai);
unsigned int ctrl1 = 0;
bool invert_fclk;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
invert_fclk = false;
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1 |= SSM4567_SAI_CTRL_1_BCLK;
invert_fclk = false;
break;
case SND_SOC_DAIFMT_NB_IF:
ctrl1 |= SSM4567_SAI_CTRL_1_FSYNC;
invert_fclk = true;
break;
case SND_SOC_DAIFMT_IB_IF:
ctrl1 |= SSM4567_SAI_CTRL_1_BCLK;
invert_fclk = true;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1 |= SSM4567_SAI_CTRL_1_LJ;
invert_fclk = !invert_fclk;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1 |= SSM4567_SAI_CTRL_1_TDM;
break;
case SND_SOC_DAIFMT_DSP_B:
ctrl1 |= SSM4567_SAI_CTRL_1_TDM | SSM4567_SAI_CTRL_1_LJ;
break;
case SND_SOC_DAIFMT_PDM:
ctrl1 |= SSM4567_SAI_CTRL_1_PDM;
break;
default:
return -EINVAL;
}
if (invert_fclk)
ctrl1 |= SSM4567_SAI_CTRL_1_FSYNC;
return regmap_update_bits(ssm4567->regmap, SSM4567_REG_SAI_CTRL_1,
SSM4567_SAI_CTRL_1_BCLK |
SSM4567_SAI_CTRL_1_FSYNC |
SSM4567_SAI_CTRL_1_LJ |
SSM4567_SAI_CTRL_1_TDM |
SSM4567_SAI_CTRL_1_PDM,
ctrl1);
}
static int ssm4567_set_power(struct ssm4567 *ssm4567, bool enable)
{
int ret = 0;
if (!enable) {
ret = regmap_update_bits(ssm4567->regmap,
SSM4567_REG_POWER_CTRL,
SSM4567_POWER_SPWDN, SSM4567_POWER_SPWDN);
regcache_mark_dirty(ssm4567->regmap);
}
regcache_cache_only(ssm4567->regmap, !enable);
if (enable) {
ret = regmap_write(ssm4567->regmap, SSM4567_REG_SOFT_RESET,
0x00);
if (ret)
return ret;
ret = regmap_update_bits(ssm4567->regmap,
SSM4567_REG_POWER_CTRL,
SSM4567_POWER_SPWDN, 0x00);
regcache_sync(ssm4567->regmap);
}
return ret;
}
static int ssm4567_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct ssm4567 *ssm4567 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
ret = ssm4567_set_power(ssm4567, true);
break;
case SND_SOC_BIAS_OFF:
ret = ssm4567_set_power(ssm4567, false);
break;
}
return ret;
}
static const struct snd_soc_dai_ops ssm4567_dai_ops = {
.hw_params = ssm4567_hw_params,
.mute_stream = ssm4567_mute,
.set_fmt = ssm4567_set_dai_fmt,
.set_tdm_slot = ssm4567_set_tdm_slot,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ssm4567_dai = {
.name = "ssm4567-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32,
},
.capture = {
.stream_name = "Capture Sense",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32,
},
.ops = &ssm4567_dai_ops,
};
static const struct snd_soc_component_driver ssm4567_component_driver = {
.set_bias_level = ssm4567_set_bias_level,
.controls = ssm4567_snd_controls,
.num_controls = ARRAY_SIZE(ssm4567_snd_controls),
.dapm_widgets = ssm4567_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ssm4567_dapm_widgets),
.dapm_routes = ssm4567_routes,
.num_dapm_routes = ARRAY_SIZE(ssm4567_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ssm4567_regmap_config = {
.val_bits = 8,
.reg_bits = 8,
.max_register = SSM4567_REG_SOFT_RESET,
.readable_reg = ssm4567_readable_reg,
.writeable_reg = ssm4567_writeable_reg,
.volatile_reg = ssm4567_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = ssm4567_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ssm4567_reg_defaults),
};
static int ssm4567_i2c_probe(struct i2c_client *i2c)
{
struct ssm4567 *ssm4567;
int ret;
ssm4567 = devm_kzalloc(&i2c->dev, sizeof(*ssm4567), GFP_KERNEL);
if (ssm4567 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, ssm4567);
ssm4567->regmap = devm_regmap_init_i2c(i2c, &ssm4567_regmap_config);
if (IS_ERR(ssm4567->regmap))
return PTR_ERR(ssm4567->regmap);
ret = regmap_write(ssm4567->regmap, SSM4567_REG_SOFT_RESET, 0x00);
if (ret)
return ret;
ret = ssm4567_set_power(ssm4567, false);
if (ret)
return ret;
return devm_snd_soc_register_component(&i2c->dev, &ssm4567_component_driver,
&ssm4567_dai, 1);
}
static const struct i2c_device_id ssm4567_i2c_ids[] = {
{ "ssm4567", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ssm4567_i2c_ids);
#ifdef CONFIG_OF
static const struct of_device_id ssm4567_of_match[] = {
{ .compatible = "adi,ssm4567", },
{ }
};
MODULE_DEVICE_TABLE(of, ssm4567_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id ssm4567_acpi_match[] = {
{ "INT343B", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, ssm4567_acpi_match);
#endif
static struct i2c_driver ssm4567_driver = {
.driver = {
.name = "ssm4567",
.of_match_table = of_match_ptr(ssm4567_of_match),
.acpi_match_table = ACPI_PTR(ssm4567_acpi_match),
},
.probe = ssm4567_i2c_probe,
.id_table = ssm4567_i2c_ids,
};
module_i2c_driver(ssm4567_driver);
MODULE_DESCRIPTION("ASoC SSM4567 driver");
MODULE_AUTHOR("Anatol Pomozov <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ssm4567.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2022, Analog Devices Inc.
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98363.h"
static struct reg_default max98363_reg[] = {
{MAX98363_R2021_ERR_MON_CTRL, 0x0},
{MAX98363_R2022_SPK_MON_THRESH, 0x0},
{MAX98363_R2023_SPK_MON_DURATION, 0x0},
{MAX98363_R2030_TONE_GEN_CFG, 0x0},
{MAX98363_R203F_TONE_GEN_EN, 0x0},
{MAX98363_R2040_AMP_VOL, 0x0},
{MAX98363_R2041_AMP_GAIN, 0x5},
{MAX98363_R2042_DSP_CFG, 0x0},
};
static bool max98363_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98363_R2001_INTR_RAW:
case MAX98363_R2003_INTR_STATE:
case MAX98363_R2005_INTR_FALG:
case MAX98363_R2007_INTR_EN:
case MAX98363_R2009_INTR_CLR:
case MAX98363_R2021_ERR_MON_CTRL ... MAX98363_R2023_SPK_MON_DURATION:
case MAX98363_R2030_TONE_GEN_CFG:
case MAX98363_R203F_TONE_GEN_EN:
case MAX98363_R2040_AMP_VOL:
case MAX98363_R2041_AMP_GAIN:
case MAX98363_R2042_DSP_CFG:
case MAX98363_R21FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98363_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98363_R2001_INTR_RAW:
case MAX98363_R2003_INTR_STATE:
case MAX98363_R2005_INTR_FALG:
case MAX98363_R2007_INTR_EN:
case MAX98363_R2009_INTR_CLR:
case MAX98363_R21FF_REV_ID:
return true;
default:
return false;
}
}
static const struct regmap_config max98363_sdw_regmap = {
.reg_bits = 32,
.val_bits = 8,
.max_register = MAX98363_R21FF_REV_ID,
.reg_defaults = max98363_reg,
.num_reg_defaults = ARRAY_SIZE(max98363_reg),
.readable_reg = max98363_readable_register,
.volatile_reg = max98363_volatile_reg,
.cache_type = REGCACHE_RBTREE,
.use_single_read = true,
.use_single_write = true,
};
static int max98363_suspend(struct device *dev)
{
struct max98363_priv *max98363 = dev_get_drvdata(dev);
regcache_cache_only(max98363->regmap, true);
regcache_mark_dirty(max98363->regmap);
return 0;
}
#define MAX98363_PROBE_TIMEOUT 5000
static int max98363_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct max98363_priv *max98363 = dev_get_drvdata(dev);
unsigned long time;
if (!max98363->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(MAX98363_PROBE_TIMEOUT));
if (!time) {
dev_err(dev, "Initialization not complete, timed out\n");
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(max98363->regmap, false);
regcache_sync(max98363->regmap);
return 0;
}
static DEFINE_RUNTIME_DEV_PM_OPS(max98363_pm, max98363_suspend, max98363_resume, NULL);
static int max98363_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
/* BITMAP: 00000010 Dataport 1 is active */
prop->sink_ports = BIT(1);
prop->paging_support = true;
prop->clk_stop_timeout = 20;
prop->simple_clk_stop_capable = true;
prop->clock_reg_supported = true;
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
return 0;
}
static int max98363_io_init(struct sdw_slave *slave)
{
struct device *dev = &slave->dev;
struct max98363_priv *max98363 = dev_get_drvdata(dev);
int ret, reg;
regcache_cache_only(max98363->regmap, false);
if (max98363->first_hw_init)
regcache_cache_bypass(max98363->regmap, true);
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
if (!max98363->first_hw_init)
/* update count of parent 'active' children */
pm_runtime_set_active(dev);
pm_runtime_get_noresume(dev);
ret = regmap_read(max98363->regmap, MAX98363_R21FF_REV_ID, ®);
if (!ret)
dev_info(dev, "Revision ID: %X\n", reg);
else
goto out;
if (max98363->first_hw_init) {
regcache_cache_bypass(max98363->regmap, false);
regcache_mark_dirty(max98363->regmap);
}
max98363->first_hw_init = true;
max98363->hw_init = true;
out:
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
return ret;
}
#define MAX98363_RATES SNDRV_PCM_RATE_8000_192000
#define MAX98363_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static int max98363_sdw_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98363_priv *max98363 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config;
struct sdw_port_config port_config;
enum sdw_data_direction direction;
struct sdw_stream_runtime *stream;
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
stream = snd_soc_dai_get_dma_data(dai, substream);
if (!stream)
return -EINVAL;
if (!max98363->slave)
return -EINVAL;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
direction = SDW_DATA_DIR_RX;
port_config.num = 1;
stream_config.frame_rate = params_rate(params);
stream_config.bps = snd_pcm_format_width(params_format(params));
stream_config.direction = direction;
stream_config.ch_count = 1;
if (stream_config.ch_count > runtime->hw.channels_max) {
stream_config.ch_count = runtime->hw.channels_max;
dev_info(dai->dev, "Number of channels: %d (requested: %d)\n",
stream_config.ch_count, params_channels(params));
}
port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
ret = sdw_stream_add_slave(max98363->slave, &stream_config,
&port_config, 1, stream);
if (ret) {
dev_err(dai->dev, "Unable to configure port\n");
return ret;
}
dev_dbg(component->dev, "Format supported %d", params_format(params));
return 0;
}
static int max98363_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98363_priv *max98363 =
snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!max98363->slave)
return -EINVAL;
sdw_stream_remove_slave(max98363->slave, stream);
return 0;
}
static int max98363_set_sdw_stream(struct snd_soc_dai *dai,
void *sdw_stream, int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static const struct snd_soc_dai_ops max98363_dai_sdw_ops = {
.hw_params = max98363_sdw_dai_hw_params,
.hw_free = max98363_pcm_hw_free,
.set_stream = max98363_set_sdw_stream,
};
static struct snd_soc_dai_driver max98363_dai[] = {
{
.name = "max98363-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 1,
.rates = MAX98363_RATES,
.formats = MAX98363_FORMATS,
},
.ops = &max98363_dai_sdw_ops,
}
};
static int max98363_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct max98363_priv *max98363 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
max98363->hw_init = false;
/*
* Perform initialization only if slave status is SDW_SLAVE_ATTACHED
*/
if (max98363->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return max98363_io_init(slave);
}
static struct sdw_slave_ops max98363_slave_ops = {
.read_prop = max98363_read_prop,
.update_status = max98363_update_status,
};
static DECLARE_TLV_DB_SCALE(max98363_digital_tlv, -6350, 50, 1);
static const DECLARE_TLV_DB_RANGE(max98363_spk_tlv,
0, 5, TLV_DB_SCALE_ITEM(-300, 300, 0),
);
static const char * const max98363_tone_cfg_text[] = {
"Reserved", "0", "+FS/2", "-FS/2", "1KHz",
"12KHz", "8KHz", "6KHz", "4KHz", "3KHz",
"2KHz", "1.5KHz", "Reserved", "500Hz", "250Hz"
};
static SOC_ENUM_SINGLE_DECL(max98363_tone_cfg_enum,
MAX98363_R2030_TONE_GEN_CFG, 0,
max98363_tone_cfg_text);
static const char * const max98363_spkmon_duration_text[] = {
"8ms", "20ms", "40ms", "60ms",
"80ms", "160ms", "240ms", "320ms",
"400ms", "480ms", "560ms", "640ms",
"720ms", "800ms", "880ms", "960ms"
};
static SOC_ENUM_SINGLE_DECL(max98363_spkmon_duration_enum,
MAX98363_R2023_SPK_MON_DURATION, 0,
max98363_spkmon_duration_text);
static const struct snd_kcontrol_new max98363_snd_controls[] = {
SOC_SINGLE_TLV("Digital Volume", MAX98363_R2040_AMP_VOL,
0, 0x7F, 1, max98363_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98363_R2041_AMP_GAIN,
0, 10, 0, max98363_spk_tlv),
SOC_SINGLE("Tone Generator Switch", MAX98363_R203F_TONE_GEN_EN,
0, 1, 0),
SOC_ENUM("Tone Config", max98363_tone_cfg_enum),
SOC_SINGLE("Ramp Switch", MAX98363_R2042_DSP_CFG,
MAX98363_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
SOC_SINGLE("CLK Monitor Switch", MAX98363_R2021_ERR_MON_CTRL,
MAX98363_CLOCK_MON_SHIFT, 1, 0),
SOC_SINGLE("SPKMON Monitor Switch", MAX98363_R2021_ERR_MON_CTRL,
MAX98363_SPKMON_SHIFT, 1, 0),
SOC_SINGLE("SPKMON Thresh", MAX98363_R2022_SPK_MON_THRESH, 0, 0xFF, 0),
SOC_ENUM("SPKMON Duration", max98363_spkmon_duration_enum),
};
static const struct snd_soc_dapm_widget max98363_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
};
static const struct snd_soc_dapm_route max98363_audio_map[] = {
/* Plabyack */
{"BE_OUT", NULL, "AIFIN"},
};
static const struct snd_soc_component_driver soc_codec_dev_max98363 = {
.controls = max98363_snd_controls,
.num_controls = ARRAY_SIZE(max98363_snd_controls),
.dapm_widgets = max98363_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98363_dapm_widgets),
.dapm_routes = max98363_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98363_audio_map),
.use_pmdown_time = 1,
.endianness = 1,
};
static int max98363_init(struct sdw_slave *slave, struct regmap *regmap)
{
struct max98363_priv *max98363;
int ret;
struct device *dev = &slave->dev;
/* Allocate and assign private driver data structure */
max98363 = devm_kzalloc(dev, sizeof(*max98363), GFP_KERNEL);
if (!max98363)
return -ENOMEM;
dev_set_drvdata(dev, max98363);
max98363->regmap = regmap;
max98363->slave = slave;
regcache_cache_only(max98363->regmap, true);
max98363->hw_init = false;
max98363->first_hw_init = false;
/* codec registration */
ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98363,
max98363_dai,
ARRAY_SIZE(max98363_dai));
if (ret < 0) {
dev_err(dev, "Failed to register codec: %d\n", ret);
return ret;
}
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
return 0;
}
static int max98363_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap;
/* Regmap Initialization */
regmap = devm_regmap_init_sdw(slave, &max98363_sdw_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return max98363_init(slave, regmap);
}
static const struct sdw_device_id max98363_id[] = {
SDW_SLAVE_ENTRY(0x019F, 0x8363, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, max98363_id);
static struct sdw_driver max98363_sdw_driver = {
.driver = {
.name = "max98363",
.pm = pm_ptr(&max98363_pm),
},
.probe = max98363_sdw_probe,
.ops = &max98363_slave_ops,
.id_table = max98363_id,
};
module_sdw_driver(max98363_sdw_driver);
MODULE_DESCRIPTION("ASoC MAX98363 driver SDW");
MODULE_AUTHOR("Ryan Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98363.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Audio Codec driver supporting:
* AD1835A, AD1836, AD1837A, AD1838A, AD1839A
*
* Copyright 2009-2011 Analog Devices Inc.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include "ad1836.h"
enum ad1836_type {
AD1835,
AD1836,
AD1838,
};
/* codec private data */
struct ad1836_priv {
enum ad1836_type type;
struct regmap *regmap;
};
/*
* AD1836 volume/mute/de-emphasis etc. controls
*/
static const char *ad1836_deemp[] = {"None", "44.1kHz", "32kHz", "48kHz"};
static SOC_ENUM_SINGLE_DECL(ad1836_deemp_enum,
AD1836_DAC_CTRL1, 8, ad1836_deemp);
#define AD1836_DAC_VOLUME(x) \
SOC_DOUBLE_R("DAC" #x " Playback Volume", AD1836_DAC_L_VOL(x), \
AD1836_DAC_R_VOL(x), 0, 0x3FF, 0)
#define AD1836_DAC_SWITCH(x) \
SOC_DOUBLE("DAC" #x " Playback Switch", AD1836_DAC_CTRL2, \
AD1836_MUTE_LEFT(x), AD1836_MUTE_RIGHT(x), 1, 1)
#define AD1836_ADC_SWITCH(x) \
SOC_DOUBLE("ADC" #x " Capture Switch", AD1836_ADC_CTRL2, \
AD1836_MUTE_LEFT(x), AD1836_MUTE_RIGHT(x), 1, 1)
static const struct snd_kcontrol_new ad183x_dac_controls[] = {
AD1836_DAC_VOLUME(1),
AD1836_DAC_SWITCH(1),
AD1836_DAC_VOLUME(2),
AD1836_DAC_SWITCH(2),
AD1836_DAC_VOLUME(3),
AD1836_DAC_SWITCH(3),
AD1836_DAC_VOLUME(4),
AD1836_DAC_SWITCH(4),
};
static const struct snd_soc_dapm_widget ad183x_dac_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("DAC1OUT"),
SND_SOC_DAPM_OUTPUT("DAC2OUT"),
SND_SOC_DAPM_OUTPUT("DAC3OUT"),
SND_SOC_DAPM_OUTPUT("DAC4OUT"),
};
static const struct snd_soc_dapm_route ad183x_dac_routes[] = {
{ "DAC1OUT", NULL, "DAC" },
{ "DAC2OUT", NULL, "DAC" },
{ "DAC3OUT", NULL, "DAC" },
{ "DAC4OUT", NULL, "DAC" },
};
static const struct snd_kcontrol_new ad183x_adc_controls[] = {
AD1836_ADC_SWITCH(1),
AD1836_ADC_SWITCH(2),
AD1836_ADC_SWITCH(3),
};
static const struct snd_soc_dapm_widget ad183x_adc_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("ADC1IN"),
SND_SOC_DAPM_INPUT("ADC2IN"),
};
static const struct snd_soc_dapm_route ad183x_adc_routes[] = {
{ "ADC", NULL, "ADC1IN" },
{ "ADC", NULL, "ADC2IN" },
};
static const struct snd_kcontrol_new ad183x_controls[] = {
/* ADC high-pass filter */
SOC_SINGLE("ADC High Pass Filter Switch", AD1836_ADC_CTRL1,
AD1836_ADC_HIGHPASS_FILTER, 1, 0),
/* DAC de-emphasis */
SOC_ENUM("Playback Deemphasis", ad1836_deemp_enum),
};
static const struct snd_soc_dapm_widget ad183x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", AD1836_DAC_CTRL1,
AD1836_DAC_POWERDOWN, 1),
SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC_PWR", AD1836_ADC_CTRL1,
AD1836_ADC_POWERDOWN, 1, NULL, 0),
};
static const struct snd_soc_dapm_route ad183x_dapm_routes[] = {
{ "DAC", NULL, "ADC_PWR" },
{ "ADC", NULL, "ADC_PWR" },
};
static const DECLARE_TLV_DB_SCALE(ad1836_in_tlv, 0, 300, 0);
static const struct snd_kcontrol_new ad1836_controls[] = {
SOC_DOUBLE_TLV("ADC2 Capture Volume", AD1836_ADC_CTRL1, 3, 0, 4, 0,
ad1836_in_tlv),
};
/*
* DAI ops entries
*/
static int ad1836_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
/* at present, we support adc aux mode to interface with
* blackfin sport tdm mode
*/
case SND_SOC_DAIFMT_DSP_A:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
/* ALCLK,ABCLK are both output, AD1836 can only be provider */
case SND_SOC_DAIFMT_CBP_CFP:
break;
default:
return -EINVAL;
}
return 0;
}
static int ad1836_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(dai->component);
int word_len = 0;
/* bit size */
switch (params_width(params)) {
case 16:
word_len = AD1836_WORD_LEN_16;
break;
case 20:
word_len = AD1836_WORD_LEN_20;
break;
case 24:
case 32:
word_len = AD1836_WORD_LEN_24;
break;
default:
return -EINVAL;
}
regmap_update_bits(ad1836->regmap, AD1836_DAC_CTRL1,
AD1836_DAC_WORD_LEN_MASK,
word_len << AD1836_DAC_WORD_LEN_OFFSET);
regmap_update_bits(ad1836->regmap, AD1836_ADC_CTRL2,
AD1836_ADC_WORD_LEN_MASK,
word_len << AD1836_ADC_WORD_OFFSET);
return 0;
}
static const struct snd_soc_dai_ops ad1836_dai_ops = {
.hw_params = ad1836_hw_params,
.set_fmt = ad1836_set_dai_fmt,
};
#define AD183X_DAI(_name, num_dacs, num_adcs) \
{ \
.name = _name "-hifi", \
.playback = { \
.stream_name = "Playback", \
.channels_min = 2, \
.channels_max = (num_dacs) * 2, \
.rates = SNDRV_PCM_RATE_48000, \
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, \
}, \
.capture = { \
.stream_name = "Capture", \
.channels_min = 2, \
.channels_max = (num_adcs) * 2, \
.rates = SNDRV_PCM_RATE_48000, \
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, \
}, \
.ops = &ad1836_dai_ops, \
}
static struct snd_soc_dai_driver ad183x_dais[] = {
[AD1835] = AD183X_DAI("ad1835", 4, 1),
[AD1836] = AD183X_DAI("ad1836", 3, 2),
[AD1838] = AD183X_DAI("ad1838", 3, 1),
};
#ifdef CONFIG_PM
static int ad1836_suspend(struct snd_soc_component *component)
{
struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(component);
/* reset clock control mode */
return regmap_update_bits(ad1836->regmap, AD1836_ADC_CTRL2,
AD1836_ADC_SERFMT_MASK, 0);
}
static int ad1836_resume(struct snd_soc_component *component)
{
struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(component);
/* restore clock control mode */
return regmap_update_bits(ad1836->regmap, AD1836_ADC_CTRL2,
AD1836_ADC_SERFMT_MASK, AD1836_ADC_AUX);
}
#else
#define ad1836_suspend NULL
#define ad1836_resume NULL
#endif
static int ad1836_probe(struct snd_soc_component *component)
{
struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int num_dacs, num_adcs;
int ret = 0;
int i;
num_dacs = ad183x_dais[ad1836->type].playback.channels_max / 2;
num_adcs = ad183x_dais[ad1836->type].capture.channels_max / 2;
/* default setting for ad1836 */
/* de-emphasis: 48kHz, power-on dac */
regmap_write(ad1836->regmap, AD1836_DAC_CTRL1, 0x300);
/* unmute dac channels */
regmap_write(ad1836->regmap, AD1836_DAC_CTRL2, 0x0);
/* high-pass filter enable, power-on adc */
regmap_write(ad1836->regmap, AD1836_ADC_CTRL1, 0x100);
/* unmute adc channles, adc aux mode */
regmap_write(ad1836->regmap, AD1836_ADC_CTRL2, 0x180);
/* volume */
for (i = 1; i <= num_dacs; ++i) {
regmap_write(ad1836->regmap, AD1836_DAC_L_VOL(i), 0x3FF);
regmap_write(ad1836->regmap, AD1836_DAC_R_VOL(i), 0x3FF);
}
if (ad1836->type == AD1836) {
/* left/right diff:PGA/MUX */
regmap_write(ad1836->regmap, AD1836_ADC_CTRL3, 0x3A);
ret = snd_soc_add_component_controls(component, ad1836_controls,
ARRAY_SIZE(ad1836_controls));
if (ret)
return ret;
} else {
regmap_write(ad1836->regmap, AD1836_ADC_CTRL3, 0x00);
}
ret = snd_soc_add_component_controls(component, ad183x_dac_controls, num_dacs * 2);
if (ret)
return ret;
ret = snd_soc_add_component_controls(component, ad183x_adc_controls, num_adcs);
if (ret)
return ret;
ret = snd_soc_dapm_new_controls(dapm, ad183x_dac_dapm_widgets, num_dacs);
if (ret)
return ret;
ret = snd_soc_dapm_new_controls(dapm, ad183x_adc_dapm_widgets, num_adcs);
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, ad183x_dac_routes, num_dacs);
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, ad183x_adc_routes, num_adcs);
return ret;
}
/* power down chip */
static void ad1836_remove(struct snd_soc_component *component)
{
struct ad1836_priv *ad1836 = snd_soc_component_get_drvdata(component);
/* reset clock control mode */
regmap_update_bits(ad1836->regmap, AD1836_ADC_CTRL2,
AD1836_ADC_SERFMT_MASK, 0);
}
static const struct snd_soc_component_driver soc_component_dev_ad1836 = {
.probe = ad1836_probe,
.remove = ad1836_remove,
.suspend = ad1836_suspend,
.resume = ad1836_resume,
.controls = ad183x_controls,
.num_controls = ARRAY_SIZE(ad183x_controls),
.dapm_widgets = ad183x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ad183x_dapm_widgets),
.dapm_routes = ad183x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ad183x_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct reg_default ad1836_reg_defaults[] = {
{ AD1836_DAC_CTRL1, 0x0000 },
{ AD1836_DAC_CTRL2, 0x0000 },
{ AD1836_DAC_L_VOL(0), 0x0000 },
{ AD1836_DAC_R_VOL(0), 0x0000 },
{ AD1836_DAC_L_VOL(1), 0x0000 },
{ AD1836_DAC_R_VOL(1), 0x0000 },
{ AD1836_DAC_L_VOL(2), 0x0000 },
{ AD1836_DAC_R_VOL(2), 0x0000 },
{ AD1836_DAC_L_VOL(3), 0x0000 },
{ AD1836_DAC_R_VOL(3), 0x0000 },
{ AD1836_ADC_CTRL1, 0x0000 },
{ AD1836_ADC_CTRL2, 0x0000 },
{ AD1836_ADC_CTRL3, 0x0000 },
};
static const struct regmap_config ad1836_regmap_config = {
.val_bits = 12,
.reg_bits = 4,
.read_flag_mask = 0x08,
.max_register = AD1836_ADC_CTRL3,
.reg_defaults = ad1836_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ad1836_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
static int ad1836_spi_probe(struct spi_device *spi)
{
struct ad1836_priv *ad1836;
int ret;
ad1836 = devm_kzalloc(&spi->dev, sizeof(struct ad1836_priv),
GFP_KERNEL);
if (ad1836 == NULL)
return -ENOMEM;
ad1836->regmap = devm_regmap_init_spi(spi, &ad1836_regmap_config);
if (IS_ERR(ad1836->regmap))
return PTR_ERR(ad1836->regmap);
ad1836->type = spi_get_device_id(spi)->driver_data;
spi_set_drvdata(spi, ad1836);
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_ad1836, &ad183x_dais[ad1836->type], 1);
return ret;
}
static const struct spi_device_id ad1836_ids[] = {
{ "ad1835", AD1835 },
{ "ad1836", AD1836 },
{ "ad1837", AD1835 },
{ "ad1838", AD1838 },
{ "ad1839", AD1838 },
{ },
};
MODULE_DEVICE_TABLE(spi, ad1836_ids);
static struct spi_driver ad1836_spi_driver = {
.driver = {
.name = "ad1836",
},
.probe = ad1836_spi_probe,
.id_table = ad1836_ids,
};
module_spi_driver(ad1836_spi_driver);
MODULE_DESCRIPTION("ASoC ad1836 driver");
MODULE_AUTHOR("Barry Song <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ad1836.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADAU1977/ADAU1978/ADAU1979 driver
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "adau1977.h"
static const struct i2c_device_id adau1977_i2c_ids[];
static int adau1977_i2c_probe(struct i2c_client *client)
{
struct regmap_config config;
const struct i2c_device_id *id = i2c_match_id(adau1977_i2c_ids, client);
config = adau1977_regmap_config;
config.val_bits = 8;
config.reg_bits = 8;
return adau1977_probe(&client->dev,
devm_regmap_init_i2c(client, &config),
id->driver_data, NULL);
}
static const struct i2c_device_id adau1977_i2c_ids[] = {
{ "adau1977", ADAU1977 },
{ "adau1978", ADAU1978 },
{ "adau1979", ADAU1978 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adau1977_i2c_ids);
static struct i2c_driver adau1977_i2c_driver = {
.driver = {
.name = "adau1977",
},
.probe = adau1977_i2c_probe,
.id_table = adau1977_i2c_ids,
};
module_i2c_driver(adau1977_i2c_driver);
MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1977-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8991.c -- WM8991 ALSA Soc Audio driver
*
* Copyright 2007-2010 Wolfson Microelectronics PLC.
* Author: Graeme Gregory
* [email protected]
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "wm8991.h"
struct wm8991_priv {
struct regmap *regmap;
unsigned int pcmclk;
};
static const struct reg_default wm8991_reg_defaults[] = {
{ 1, 0x0000 }, /* R1 - Power Management (1) */
{ 2, 0x6000 }, /* R2 - Power Management (2) */
{ 3, 0x0000 }, /* R3 - Power Management (3) */
{ 4, 0x4050 }, /* R4 - Audio Interface (1) */
{ 5, 0x4000 }, /* R5 - Audio Interface (2) */
{ 6, 0x01C8 }, /* R6 - Clocking (1) */
{ 7, 0x0000 }, /* R7 - Clocking (2) */
{ 8, 0x0040 }, /* R8 - Audio Interface (3) */
{ 9, 0x0040 }, /* R9 - Audio Interface (4) */
{ 10, 0x0004 }, /* R10 - DAC CTRL */
{ 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
{ 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
{ 13, 0x0000 }, /* R13 - Digital Side Tone */
{ 14, 0x0100 }, /* R14 - ADC CTRL */
{ 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
{ 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
{ 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
{ 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */
{ 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */
{ 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */
{ 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
{ 23, 0x0800 }, /* R23 - GPIO_POL */
{ 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
{ 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
{ 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
{ 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
{ 28, 0x0000 }, /* R28 - Left Output Volume */
{ 29, 0x0000 }, /* R29 - Right Output Volume */
{ 30, 0x0066 }, /* R30 - Line Outputs Volume */
{ 31, 0x0022 }, /* R31 - Out3/4 Volume */
{ 32, 0x0079 }, /* R32 - Left OPGA Volume */
{ 33, 0x0079 }, /* R33 - Right OPGA Volume */
{ 34, 0x0003 }, /* R34 - Speaker Volume */
{ 35, 0x0003 }, /* R35 - ClassD1 */
{ 37, 0x0100 }, /* R37 - ClassD3 */
{ 39, 0x0000 }, /* R39 - Input Mixer1 */
{ 40, 0x0000 }, /* R40 - Input Mixer2 */
{ 41, 0x0000 }, /* R41 - Input Mixer3 */
{ 42, 0x0000 }, /* R42 - Input Mixer4 */
{ 43, 0x0000 }, /* R43 - Input Mixer5 */
{ 44, 0x0000 }, /* R44 - Input Mixer6 */
{ 45, 0x0000 }, /* R45 - Output Mixer1 */
{ 46, 0x0000 }, /* R46 - Output Mixer2 */
{ 47, 0x0000 }, /* R47 - Output Mixer3 */
{ 48, 0x0000 }, /* R48 - Output Mixer4 */
{ 49, 0x0000 }, /* R49 - Output Mixer5 */
{ 50, 0x0000 }, /* R50 - Output Mixer6 */
{ 51, 0x0180 }, /* R51 - Out3/4 Mixer */
{ 52, 0x0000 }, /* R52 - Line Mixer1 */
{ 53, 0x0000 }, /* R53 - Line Mixer2 */
{ 54, 0x0000 }, /* R54 - Speaker Mixer */
{ 55, 0x0000 }, /* R55 - Additional Control */
{ 56, 0x0000 }, /* R56 - AntiPOP1 */
{ 57, 0x0000 }, /* R57 - AntiPOP2 */
{ 58, 0x0000 }, /* R58 - MICBIAS */
{ 60, 0x0008 }, /* R60 - PLL1 */
{ 61, 0x0031 }, /* R61 - PLL2 */
{ 62, 0x0026 }, /* R62 - PLL3 */
};
static bool wm8991_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8991_RESET:
return true;
default:
return false;
}
}
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_pga_tlv, -1650, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(out_mix_tlv, -2100, 300, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_pga_tlv,
0x00, 0x2f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(SNDRV_CTL_TLVD_DB_GAIN_MUTE, 0, 1),
0x30, 0x7f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-7300, 100, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_dac_tlv,
0x00, 0xbf, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1),
0xc0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(in_adc_tlv,
0x00, 0xef, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1),
0xf0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(17625, 0, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_sidetone_tlv,
0x00, 0x0c, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-3600, 300, 0),
0x0d, 0x0f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0),
);
static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int reg = kcontrol->private_value & 0xff;
int ret;
u16 val;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
/* now hit the volume update bits (always bit 8) */
val = snd_soc_component_read(component, reg);
return snd_soc_component_write(component, reg, val | 0x0100);
}
static const char *wm8991_digital_sidetone[] =
{"None", "Left ADC", "Right ADC", "Reserved"};
static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum,
WM8991_DIGITAL_SIDE_TONE,
WM8991_ADC_TO_DACL_SHIFT,
wm8991_digital_sidetone);
static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum,
WM8991_DIGITAL_SIDE_TONE,
WM8991_ADC_TO_DACR_SHIFT,
wm8991_digital_sidetone);
static const char *wm8991_adcmode[] =
{"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum,
WM8991_ADC_CTRL,
WM8991_ADC_HPF_CUT_SHIFT,
wm8991_adcmode);
static const struct snd_kcontrol_new wm8991_snd_controls[] = {
/* INMIXL */
SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0),
SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0),
/* INMIXR */
SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0),
SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0),
/* LOMIX */
SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
/* ROMIX */
SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv),
SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv),
/* LOUT */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME,
WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0),
/* ROUT */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME,
WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0),
/* LOPGA */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME,
WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME,
WM8991_LOPGAZC_BIT, 1, 0),
/* ROPGA */
SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME,
WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv),
SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME,
WM8991_ROPGAZC_BIT, 1, 0),
SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
WM8991_LONMUTE_BIT, 1, 0),
SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
WM8991_LOPMUTE_BIT, 1, 0),
SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
WM8991_LOATTN_BIT, 1, 0),
SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
WM8991_RONMUTE_BIT, 1, 0),
SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
WM8991_ROPMUTE_BIT, 1, 0),
SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
WM8991_ROATTN_BIT, 1, 0),
SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME,
WM8991_OUT3MUTE_BIT, 1, 0),
SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME,
WM8991_OUT3ATTN_BIT, 1, 0),
SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME,
WM8991_OUT4MUTE_BIT, 1, 0),
SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME,
WM8991_OUT4ATTN_BIT, 1, 0),
SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1,
WM8991_CDMODE_BIT, 1, 0),
SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME,
WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0),
SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3,
WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0),
SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3,
WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
WM8991_LEFT_DAC_DIGITAL_VOLUME,
WM8991_DACL_VOL_SHIFT,
WM8991_DACL_VOL_MASK,
0,
out_dac_tlv),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
WM8991_RIGHT_DAC_DIGITAL_VOLUME,
WM8991_DACR_VOL_SHIFT,
WM8991_DACR_VOL_MASK,
0,
out_dac_tlv),
SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum),
SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum),
SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0,
out_sidetone_tlv),
SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0,
out_sidetone_tlv),
SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL,
WM8991_ADC_HPF_ENA_BIT, 1, 0),
SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
WM8991_LEFT_ADC_DIGITAL_VOLUME,
WM8991_ADCL_VOL_SHIFT,
WM8991_ADCL_VOL_MASK,
0,
in_adc_tlv),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
WM8991_RIGHT_ADC_DIGITAL_VOLUME,
WM8991_ADCR_VOL_SHIFT,
WM8991_ADCR_VOL_MASK,
0,
in_adc_tlv),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
WM8991_LIN12VOL_SHIFT,
WM8991_LIN12VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
WM8991_LI12ZC_BIT, 1, 0),
SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
WM8991_LI12MUTE_BIT, 1, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
WM8991_LIN34VOL_SHIFT,
WM8991_LIN34VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
WM8991_LI34ZC_BIT, 1, 0),
SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
WM8991_LI34MUTE_BIT, 1, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8991_RIN12VOL_SHIFT,
WM8991_RIN12VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8991_RI12ZC_BIT, 1, 0),
SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8991_RI12MUTE_BIT, 1, 0),
SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8991_RIN34VOL_SHIFT,
WM8991_RIN34VOL_MASK,
0,
in_pga_tlv),
SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8991_RI34ZC_BIT, 1, 0),
SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8991_RI34MUTE_BIT, 1, 0),
};
/*
* _DAPM_ Controls
*/
static int outmixer_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u32 reg_shift = kcontrol->private_value & 0xfff;
int ret = 0;
u16 reg;
switch (reg_shift) {
case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8):
reg = snd_soc_component_read(component, WM8991_OUTPUT_MIXER1);
if (reg & WM8991_LDLO) {
printk(KERN_WARNING
"Cannot set as Output Mixer 1 LDLO Set\n");
ret = -1;
}
break;
case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8):
reg = snd_soc_component_read(component, WM8991_OUTPUT_MIXER2);
if (reg & WM8991_RDRO) {
printk(KERN_WARNING
"Cannot set as Output Mixer 2 RDRO Set\n");
ret = -1;
}
break;
case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8):
reg = snd_soc_component_read(component, WM8991_SPEAKER_MIXER);
if (reg & WM8991_LDSPK) {
printk(KERN_WARNING
"Cannot set as Speaker Mixer LDSPK Set\n");
ret = -1;
}
break;
case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8):
reg = snd_soc_component_read(component, WM8991_SPEAKER_MIXER);
if (reg & WM8991_RDSPK) {
printk(KERN_WARNING
"Cannot set as Speaker Mixer RDSPK Set\n");
ret = -1;
}
break;
}
return ret;
}
/* INMIX dB values */
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_mix_tlv, -1200, 300, 1);
/* Left In PGA Connections */
static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = {
SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0),
SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0),
};
static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = {
SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0),
SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0),
};
/* Right In PGA Connections */
static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = {
SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0),
SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0),
};
static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = {
SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0),
SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0),
};
/* INMIXL */
static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = {
SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3,
WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv),
SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT,
7, 0, in_mix_tlv),
SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
1, 0),
SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
1, 0),
};
/* INMIXR */
static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = {
SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4,
WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv),
SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT,
7, 0, in_mix_tlv),
SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
1, 0),
SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
1, 0),
};
/* AINLMUX */
static const char *wm8991_ainlmux[] =
{"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum,
WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT,
wm8991_ainlmux);
static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls =
SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum);
/* DIFFINL */
/* AINRMUX */
static const char *wm8991_ainrmux[] =
{"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum,
WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT,
wm8991_ainrmux);
static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls =
SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum);
/* LOMIX */
static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = {
SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
WM8991_LRBLO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
WM8991_LLBLO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
WM8991_LRI3LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
WM8991_LLI3LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
WM8991_LR12LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
WM8991_LL12LO_BIT, 1, 0),
SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1,
WM8991_LDLO_BIT, 1, 0),
};
/* ROMIX */
static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = {
SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
WM8991_RLBRO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
WM8991_RRBRO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
WM8991_RLI3RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
WM8991_RRI3RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
WM8991_RL12RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
WM8991_RR12RO_BIT, 1, 0),
SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2,
WM8991_RDRO_BIT, 1, 0),
};
/* LONMIX */
static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = {
SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
WM8991_LLOPGALON_BIT, 1, 0),
SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1,
WM8991_LROPGALON_BIT, 1, 0),
SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1,
WM8991_LOPLON_BIT, 1, 0),
};
/* LOPMIX */
static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = {
SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1,
WM8991_LR12LOP_BIT, 1, 0),
SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1,
WM8991_LL12LOP_BIT, 1, 0),
SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
WM8991_LLOPGALOP_BIT, 1, 0),
};
/* RONMIX */
static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = {
SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
WM8991_RROPGARON_BIT, 1, 0),
SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2,
WM8991_RLOPGARON_BIT, 1, 0),
SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2,
WM8991_ROPRON_BIT, 1, 0),
};
/* ROPMIX */
static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = {
SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2,
WM8991_RL12ROP_BIT, 1, 0),
SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2,
WM8991_RR12ROP_BIT, 1, 0),
SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
WM8991_RROPGAROP_BIT, 1, 0),
};
/* OUT3MIX */
static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = {
SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER,
WM8991_LI4O3_BIT, 1, 0),
SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER,
WM8991_LPGAO3_BIT, 1, 0),
};
/* OUT4MIX */
static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = {
SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER,
WM8991_RPGAO4_BIT, 1, 0),
SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER,
WM8991_RI4O4_BIT, 1, 0),
};
/* SPKMIX */
static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = {
SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
WM8991_LI2SPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER,
WM8991_LB2SPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER,
WM8991_LOPGASPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER,
WM8991_LDSPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER,
WM8991_RDSPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER,
WM8991_ROPGASPK_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER,
WM8991_RL12ROP_BIT, 1, 0),
SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
WM8991_RI2SPK_BIT, 1, 0),
};
static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = {
/* Input Side */
/* Input Lines */
SND_SOC_DAPM_INPUT("LIN1"),
SND_SOC_DAPM_INPUT("LIN2"),
SND_SOC_DAPM_INPUT("LIN3"),
SND_SOC_DAPM_INPUT("LIN4RXN"),
SND_SOC_DAPM_INPUT("RIN3"),
SND_SOC_DAPM_INPUT("RIN4RXP"),
SND_SOC_DAPM_INPUT("RIN1"),
SND_SOC_DAPM_INPUT("RIN2"),
SND_SOC_DAPM_INPUT("Internal ADC Source"),
SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2,
WM8991_AINL_ENA_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2,
WM8991_AINR_ENA_BIT, 0, NULL, 0),
/* DACs */
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2,
WM8991_ADCL_ENA_BIT, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2,
WM8991_ADCR_ENA_BIT, 0),
/* Input PGAs */
SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT,
0, &wm8991_dapm_lin12_pga_controls[0],
ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)),
SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT,
0, &wm8991_dapm_lin34_pga_controls[0],
ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)),
SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT,
0, &wm8991_dapm_rin12_pga_controls[0],
ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)),
SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT,
0, &wm8991_dapm_rin34_pga_controls[0],
ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)),
/* INMIXL */
SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
&wm8991_dapm_inmixl_controls[0],
ARRAY_SIZE(wm8991_dapm_inmixl_controls)),
/* AINLMUX */
SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0,
&wm8991_dapm_ainlmux_controls),
/* INMIXR */
SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
&wm8991_dapm_inmixr_controls[0],
ARRAY_SIZE(wm8991_dapm_inmixr_controls)),
/* AINRMUX */
SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0,
&wm8991_dapm_ainrmux_controls),
/* Output Side */
/* DACs */
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3,
WM8991_DACL_ENA_BIT, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3,
WM8991_DACR_ENA_BIT, 0),
/* LOMIX */
SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT,
0, &wm8991_dapm_lomix_controls[0],
ARRAY_SIZE(wm8991_dapm_lomix_controls),
outmixer_event, SND_SOC_DAPM_PRE_REG),
/* LONMIX */
SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0,
&wm8991_dapm_lonmix_controls[0],
ARRAY_SIZE(wm8991_dapm_lonmix_controls)),
/* LOPMIX */
SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0,
&wm8991_dapm_lopmix_controls[0],
ARRAY_SIZE(wm8991_dapm_lopmix_controls)),
/* OUT3MIX */
SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0,
&wm8991_dapm_out3mix_controls[0],
ARRAY_SIZE(wm8991_dapm_out3mix_controls)),
/* SPKMIX */
SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0,
&wm8991_dapm_spkmix_controls[0],
ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event,
SND_SOC_DAPM_PRE_REG),
/* OUT4MIX */
SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0,
&wm8991_dapm_out4mix_controls[0],
ARRAY_SIZE(wm8991_dapm_out4mix_controls)),
/* ROPMIX */
SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0,
&wm8991_dapm_ropmix_controls[0],
ARRAY_SIZE(wm8991_dapm_ropmix_controls)),
/* RONMIX */
SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0,
&wm8991_dapm_ronmix_controls[0],
ARRAY_SIZE(wm8991_dapm_ronmix_controls)),
/* ROMIX */
SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT,
0, &wm8991_dapm_romix_controls[0],
ARRAY_SIZE(wm8991_dapm_romix_controls),
outmixer_event, SND_SOC_DAPM_PRE_REG),
/* LOUT PGA */
SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0,
NULL, 0),
/* ROUT PGA */
SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0,
NULL, 0),
/* LOPGA */
SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0,
NULL, 0),
/* ROPGA */
SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0,
NULL, 0),
/* MICBIAS */
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1,
WM8991_MICBIAS_ENA_BIT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LON"),
SND_SOC_DAPM_OUTPUT("LOP"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("SPKN"),
SND_SOC_DAPM_OUTPUT("SPKP"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("OUT4"),
SND_SOC_DAPM_OUTPUT("ROP"),
SND_SOC_DAPM_OUTPUT("RON"),
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
};
static const struct snd_soc_dapm_route wm8991_dapm_routes[] = {
/* Make DACs turn on when playing even if not mixed into any outputs */
{"Internal DAC Sink", NULL, "Left DAC"},
{"Internal DAC Sink", NULL, "Right DAC"},
/* Make ADCs turn on when recording even if not mixed from any inputs */
{"Left ADC", NULL, "Internal ADC Source"},
{"Right ADC", NULL, "Internal ADC Source"},
/* Input Side */
{"INMIXL", NULL, "INL"},
{"AINLMUX", NULL, "INL"},
{"INMIXR", NULL, "INR"},
{"AINRMUX", NULL, "INR"},
/* LIN12 PGA */
{"LIN12 PGA", "LIN1 Switch", "LIN1"},
{"LIN12 PGA", "LIN2 Switch", "LIN2"},
/* LIN34 PGA */
{"LIN34 PGA", "LIN3 Switch", "LIN3"},
{"LIN34 PGA", "LIN4 Switch", "LIN4RXN"},
/* INMIXL */
{"INMIXL", "Record Left Volume", "LOMIX"},
{"INMIXL", "LIN2 Volume", "LIN2"},
{"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
{"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
/* AINLMUX */
{"AINLMUX", "INMIXL Mix", "INMIXL"},
{"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
{"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
{"AINLMUX", "RXVOICE Mix", "LIN4RXN"},
{"AINLMUX", "RXVOICE Mix", "RIN4RXP"},
/* ADC */
{"Left ADC", NULL, "AINLMUX"},
/* RIN12 PGA */
{"RIN12 PGA", "RIN1 Switch", "RIN1"},
{"RIN12 PGA", "RIN2 Switch", "RIN2"},
/* RIN34 PGA */
{"RIN34 PGA", "RIN3 Switch", "RIN3"},
{"RIN34 PGA", "RIN4 Switch", "RIN4RXP"},
/* INMIXL */
{"INMIXR", "Record Right Volume", "ROMIX"},
{"INMIXR", "RIN2 Volume", "RIN2"},
{"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
{"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
/* AINRMUX */
{"AINRMUX", "INMIXR Mix", "INMIXR"},
{"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
{"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
{"AINRMUX", "RXVOICE Mix", "LIN4RXN"},
{"AINRMUX", "RXVOICE Mix", "RIN4RXP"},
/* ADC */
{"Right ADC", NULL, "AINRMUX"},
/* LOMIX */
{"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
{"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
{"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
{"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
{"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
{"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
{"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
/* ROMIX */
{"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
{"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
{"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
{"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
{"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
{"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
{"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
/* SPKMIX */
{"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
{"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
{"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
{"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
{"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
{"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
{"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
{"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
/* LONMIX */
{"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
{"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
{"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
/* LOPMIX */
{"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
{"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
{"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
/* OUT3MIX */
{"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"},
{"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
/* OUT4MIX */
{"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
{"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"},
/* RONMIX */
{"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
{"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
{"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
/* ROPMIX */
{"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
{"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
{"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
/* Out Mixer PGAs */
{"LOPGA", NULL, "LOMIX"},
{"ROPGA", NULL, "ROMIX"},
{"LOUT PGA", NULL, "LOMIX"},
{"ROUT PGA", NULL, "ROMIX"},
/* Output Pins */
{"LON", NULL, "LONMIX"},
{"LOP", NULL, "LOPMIX"},
{"OUT", NULL, "OUT3MIX"},
{"LOUT", NULL, "LOUT PGA"},
{"SPKN", NULL, "SPKMIX"},
{"ROUT", NULL, "ROUT PGA"},
{"OUT4", NULL, "OUT4MIX"},
{"ROP", NULL, "ROPMIX"},
{"RON", NULL, "RONMIX"},
};
/* PLL divisors */
struct _pll_div {
u32 div2;
u32 n;
u32 k;
};
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 16) * 10)
static void pll_factors(struct _pll_div *pll_div, unsigned int target,
unsigned int source)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->div2 = 1;
Ndiv = target / source;
} else
pll_div->div2 = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8991 N value outwith recommended range! N = %d\n", Ndiv);
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
}
static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai,
int pll_id, int src, unsigned int freq_in, unsigned int freq_out)
{
u16 reg;
struct snd_soc_component *component = codec_dai->component;
struct _pll_div pll_div;
if (freq_in && freq_out) {
pll_factors(&pll_div, freq_out * 4, freq_in);
/* Turn on PLL */
reg = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_2);
reg |= WM8991_PLL_ENA;
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg);
/* sysclk comes from PLL */
reg = snd_soc_component_read(component, WM8991_CLOCKING_2);
snd_soc_component_write(component, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC);
/* set up N , fractional mode and pre-divisor if necessary */
snd_soc_component_write(component, WM8991_PLL1, pll_div.n | WM8991_SDM |
(pll_div.div2 ? WM8991_PRESCALE : 0));
snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8));
snd_soc_component_write(component, WM8991_PLL3, (u8)(pll_div.k & 0xFF));
} else {
/* Turn on PLL */
reg = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_2);
reg &= ~WM8991_PLL_ENA;
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg);
}
return 0;
}
/*
* Set's ADC and Voice DAC format.
*/
static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 audio1, audio3;
audio1 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_1);
audio3 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_3);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
audio3 &= ~WM8991_AIF_MSTR1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
audio3 |= WM8991_AIF_MSTR1;
break;
default:
return -EINVAL;
}
audio1 &= ~WM8991_AIF_FMT_MASK;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
audio1 |= WM8991_AIF_TMF_I2S;
audio1 &= ~WM8991_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_RIGHT_J:
audio1 |= WM8991_AIF_TMF_RIGHTJ;
audio1 &= ~WM8991_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_LEFT_J:
audio1 |= WM8991_AIF_TMF_LEFTJ;
audio1 &= ~WM8991_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_A:
audio1 |= WM8991_AIF_TMF_DSP;
audio1 &= ~WM8991_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_DSP_B:
audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1);
snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_3, audio3);
return 0;
}
static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
switch (div_id) {
case WM8991_MCLK_DIV:
reg = snd_soc_component_read(component, WM8991_CLOCKING_2) &
~WM8991_MCLK_DIV_MASK;
snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div);
break;
case WM8991_DACCLK_DIV:
reg = snd_soc_component_read(component, WM8991_CLOCKING_2) &
~WM8991_DAC_CLKDIV_MASK;
snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div);
break;
case WM8991_ADCCLK_DIV:
reg = snd_soc_component_read(component, WM8991_CLOCKING_2) &
~WM8991_ADC_CLKDIV_MASK;
snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div);
break;
case WM8991_BCLK_DIV:
reg = snd_soc_component_read(component, WM8991_CLOCKING_1) &
~WM8991_BCLK_DIV_MASK;
snd_soc_component_write(component, WM8991_CLOCKING_1, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8991_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
u16 audio1 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_1);
audio1 &= ~WM8991_AIF_WL_MASK;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
audio1 |= WM8991_AIF_WL_20BITS;
break;
case 24:
audio1 |= WM8991_AIF_WL_24BITS;
break;
case 32:
audio1 |= WM8991_AIF_WL_32BITS;
break;
}
snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1);
return 0;
}
static int wm8991_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u16 val;
val = snd_soc_component_read(component, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE;
if (mute)
snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
else
snd_soc_component_write(component, WM8991_DAC_CTRL, val);
return 0;
}
static int wm8991_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8991_priv *wm8991 = snd_soc_component_get_drvdata(component);
u16 val;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID=2*50k */
val = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_1) &
~WM8991_VMID_MODE_MASK;
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x2);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_sync(wm8991->regmap);
/* Enable all output discharge bits */
snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
WM8991_DIS_ROUT);
/* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
WM8991_BUFDCOPEN | WM8991_POBCTRL |
WM8991_VMIDTOG);
/* Delay to allow output caps to discharge */
msleep(300);
/* Disable VMIDTOG */
snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
WM8991_BUFDCOPEN | WM8991_POBCTRL);
/* disable all output discharge bits */
snd_soc_component_write(component, WM8991_ANTIPOP1, 0);
/* Enable outputs */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1b00);
msleep(50);
/* Enable VMID at 2x50k */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f02);
msleep(100);
/* Enable VREF */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03);
msleep(600);
/* Enable BUFIOEN */
snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
WM8991_BUFDCOPEN | WM8991_POBCTRL |
WM8991_BUFIOEN);
/* Disable outputs */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x3);
/* disable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_BUFIOEN);
}
/* VMID=2*250k */
val = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_1) &
~WM8991_VMID_MODE_MASK;
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x4);
break;
case SND_SOC_BIAS_OFF:
/* Enable POBCTRL and SOFT_ST */
snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
WM8991_POBCTRL | WM8991_BUFIOEN);
/* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
WM8991_BUFDCOPEN | WM8991_POBCTRL |
WM8991_BUFIOEN);
/* mute DAC */
val = snd_soc_component_read(component, WM8991_DAC_CTRL);
snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
/* Enable any disabled outputs */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03);
/* Disable VMID */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f01);
msleep(300);
/* Enable all output discharge bits */
snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
WM8991_DIS_ROUT);
/* Disable VREF */
snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x0);
/* disable POBCTRL, SOFT_ST and BUFDCOPEN */
snd_soc_component_write(component, WM8991_ANTIPOP2, 0x0);
regcache_mark_dirty(wm8991->regmap);
break;
}
return 0;
}
#define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8991_ops = {
.hw_params = wm8991_hw_params,
.mute_stream = wm8991_mute,
.set_fmt = wm8991_set_dai_fmt,
.set_clkdiv = wm8991_set_dai_clkdiv,
.set_pll = wm8991_set_dai_pll,
.no_capture_mute = 1,
};
/*
* The WM8991 supports 2 different and mutually exclusive DAI
* configurations.
*
* 1. ADC/DAC on Primary Interface
* 2. ADC on Primary Interface/DAC on secondary
*/
static struct snd_soc_dai_driver wm8991_dai = {
/* ADC/DAC on primary */
.name = "wm8991",
.id = 1,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = WM8991_FORMATS
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = WM8991_FORMATS
},
.ops = &wm8991_ops
};
static const struct snd_soc_component_driver soc_component_dev_wm8991 = {
.set_bias_level = wm8991_set_bias_level,
.controls = wm8991_snd_controls,
.num_controls = ARRAY_SIZE(wm8991_snd_controls),
.dapm_widgets = wm8991_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8991_dapm_widgets),
.dapm_routes = wm8991_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8991_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8991_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8991_PLL3,
.volatile_reg = wm8991_volatile,
.reg_defaults = wm8991_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults),
.cache_type = REGCACHE_MAPLE,
};
static int wm8991_i2c_probe(struct i2c_client *i2c)
{
struct wm8991_priv *wm8991;
unsigned int val;
int ret;
wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL);
if (!wm8991)
return -ENOMEM;
wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap);
if (IS_ERR(wm8991->regmap))
return PTR_ERR(wm8991->regmap);
i2c_set_clientdata(i2c, wm8991);
ret = regmap_read(wm8991->regmap, WM8991_RESET, &val);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret);
return ret;
}
if (val != 0x8991) {
dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val);
return -EINVAL;
}
ret = regmap_write(wm8991->regmap, WM8991_RESET, 0);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4,
WM8991_ALRCGPIO1, WM8991_ALRCGPIO1);
regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2,
WM8991_GPIO1_SEL_MASK, 1);
regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1,
WM8991_VREF_ENA | WM8991_VMID_MODE_MASK,
WM8991_VREF_ENA | WM8991_VMID_MODE_MASK);
regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2,
WM8991_OPCLK_ENA, WM8991_OPCLK_ENA);
regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0);
regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME,
0x50 | (1<<8));
regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME,
0x50 | (1<<8));
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8991, &wm8991_dai, 1);
return ret;
}
static const struct i2c_device_id wm8991_i2c_id[] = {
{ "wm8991", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id);
static struct i2c_driver wm8991_i2c_driver = {
.driver = {
.name = "wm8991",
},
.probe = wm8991_i2c_probe,
.id_table = wm8991_i2c_id,
};
module_i2c_driver(wm8991_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8991 driver");
MODULE_AUTHOR("Graeme Gregory");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8991.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Stephan Gerhold
*
* Register definitions/sequences taken from various tfa98xx kernel drivers:
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright (C) 2013 Sony Mobile Communications Inc.
*/
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#define TFA989X_STATUSREG 0x00
#define TFA989X_BATTERYVOLTAGE 0x01
#define TFA989X_TEMPERATURE 0x02
#define TFA989X_REVISIONNUMBER 0x03
#define TFA989X_REVISIONNUMBER_REV_MSK GENMASK(7, 0) /* device revision */
#define TFA989X_I2SREG 0x04
#define TFA989X_I2SREG_RCV 2 /* receiver mode */
#define TFA989X_I2SREG_CHSA 6 /* amplifier input select */
#define TFA989X_I2SREG_CHSA_MSK GENMASK(7, 6)
#define TFA989X_I2SREG_I2SSR 12 /* sample rate */
#define TFA989X_I2SREG_I2SSR_MSK GENMASK(15, 12)
#define TFA989X_BAT_PROT 0x05
#define TFA989X_AUDIO_CTR 0x06
#define TFA989X_DCDCBOOST 0x07
#define TFA989X_SPKR_CALIBRATION 0x08
#define TFA989X_SYS_CTRL 0x09
#define TFA989X_SYS_CTRL_PWDN 0 /* power down */
#define TFA989X_SYS_CTRL_I2CR 1 /* I2C reset */
#define TFA989X_SYS_CTRL_CFE 2 /* enable CoolFlux DSP */
#define TFA989X_SYS_CTRL_AMPE 3 /* enable amplifier */
#define TFA989X_SYS_CTRL_DCA 4 /* enable boost */
#define TFA989X_SYS_CTRL_SBSL 5 /* DSP configured */
#define TFA989X_SYS_CTRL_AMPC 6 /* amplifier enabled by DSP */
#define TFA989X_I2S_SEL_REG 0x0a
#define TFA989X_I2S_SEL_REG_SPKR_MSK GENMASK(10, 9) /* speaker impedance */
#define TFA989X_I2S_SEL_REG_DCFG_MSK GENMASK(14, 11) /* DCDC compensation */
#define TFA989X_HIDE_UNHIDE_KEY 0x40
#define TFA989X_PWM_CONTROL 0x41
#define TFA989X_CURRENTSENSE1 0x46
#define TFA989X_CURRENTSENSE2 0x47
#define TFA989X_CURRENTSENSE3 0x48
#define TFA989X_CURRENTSENSE4 0x49
#define TFA9890_REVISION 0x80
#define TFA9895_REVISION 0x12
#define TFA9897_REVISION 0x97
struct tfa989x_rev {
unsigned int rev;
int (*init)(struct regmap *regmap);
};
struct tfa989x {
const struct tfa989x_rev *rev;
struct regulator *vddd_supply;
struct gpio_desc *rcv_gpiod;
};
static bool tfa989x_writeable_reg(struct device *dev, unsigned int reg)
{
return reg > TFA989X_REVISIONNUMBER;
}
static bool tfa989x_volatile_reg(struct device *dev, unsigned int reg)
{
return reg < TFA989X_REVISIONNUMBER;
}
static const struct regmap_config tfa989x_regmap = {
.reg_bits = 8,
.val_bits = 16,
.writeable_reg = tfa989x_writeable_reg,
.volatile_reg = tfa989x_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static const char * const chsa_text[] = { "Left", "Right", /* "DSP" */ };
static SOC_ENUM_SINGLE_DECL(chsa_enum, TFA989X_I2SREG, TFA989X_I2SREG_CHSA, chsa_text);
static const struct snd_kcontrol_new chsa_mux = SOC_DAPM_ENUM("Amp Input", chsa_enum);
static const struct snd_soc_dapm_widget tfa989x_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("OUT"),
SND_SOC_DAPM_SUPPLY("POWER", TFA989X_SYS_CTRL, TFA989X_SYS_CTRL_PWDN, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("AMPE", TFA989X_SYS_CTRL, TFA989X_SYS_CTRL_AMPE, 0, NULL, 0),
SND_SOC_DAPM_MUX("Amp Input", SND_SOC_NOPM, 0, 0, &chsa_mux),
SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route tfa989x_dapm_routes[] = {
{"OUT", NULL, "AMPE"},
{"AMPE", NULL, "POWER"},
{"AMPE", NULL, "Amp Input"},
{"Amp Input", "Left", "AIFINL"},
{"Amp Input", "Right", "AIFINR"},
};
static int tfa989x_put_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tfa989x *tfa989x = snd_soc_component_get_drvdata(component);
gpiod_set_value_cansleep(tfa989x->rcv_gpiod, ucontrol->value.enumerated.item[0]);
return snd_soc_put_enum_double(kcontrol, ucontrol);
}
static const char * const mode_text[] = { "Speaker", "Receiver" };
static SOC_ENUM_SINGLE_DECL(mode_enum, TFA989X_I2SREG, TFA989X_I2SREG_RCV, mode_text);
static const struct snd_kcontrol_new tfa989x_mode_controls[] = {
SOC_ENUM_EXT("Mode", mode_enum, snd_soc_get_enum_double, tfa989x_put_mode),
};
static int tfa989x_probe(struct snd_soc_component *component)
{
struct tfa989x *tfa989x = snd_soc_component_get_drvdata(component);
if (tfa989x->rev->rev == TFA9897_REVISION)
return snd_soc_add_component_controls(component, tfa989x_mode_controls,
ARRAY_SIZE(tfa989x_mode_controls));
return 0;
}
static const struct snd_soc_component_driver tfa989x_component = {
.probe = tfa989x_probe,
.dapm_widgets = tfa989x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tfa989x_dapm_widgets),
.dapm_routes = tfa989x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tfa989x_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static const unsigned int tfa989x_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
};
static int tfa989x_find_sample_rate(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(tfa989x_rates); ++i)
if (tfa989x_rates[i] == rate)
return i;
return -EINVAL;
}
static int tfa989x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int sr;
sr = tfa989x_find_sample_rate(params_rate(params));
if (sr < 0)
return sr;
return snd_soc_component_update_bits(component, TFA989X_I2SREG,
TFA989X_I2SREG_I2SSR_MSK,
sr << TFA989X_I2SREG_I2SSR);
}
static const struct snd_soc_dai_ops tfa989x_dai_ops = {
.hw_params = tfa989x_hw_params,
};
static struct snd_soc_dai_driver tfa989x_dai = {
.name = "tfa989x-hifi",
.playback = {
.stream_name = "HiFi Playback",
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &tfa989x_dai_ops,
};
static int tfa9890_init(struct regmap *regmap)
{
int ret;
/* temporarily allow access to hidden registers */
ret = regmap_write(regmap, TFA989X_HIDE_UNHIDE_KEY, 0x5a6b);
if (ret)
return ret;
/* update PLL registers */
ret = regmap_set_bits(regmap, 0x59, 0x3);
if (ret)
return ret;
/* hide registers again */
ret = regmap_write(regmap, TFA989X_HIDE_UNHIDE_KEY, 0x0000);
if (ret)
return ret;
return regmap_write(regmap, TFA989X_CURRENTSENSE2, 0x7BE1);
}
static const struct tfa989x_rev tfa9890_rev = {
.rev = TFA9890_REVISION,
.init = tfa9890_init,
};
static const struct reg_sequence tfa9895_reg_init[] = {
/* some other registers must be set for optimal amplifier behaviour */
{ TFA989X_BAT_PROT, 0x13ab },
{ TFA989X_AUDIO_CTR, 0x001f },
/* peak voltage protection is always on, but may be written */
{ TFA989X_SPKR_CALIBRATION, 0x3c4e },
/* TFA989X_SYSCTRL_DCA = 0 */
{ TFA989X_SYS_CTRL, 0x024d },
{ TFA989X_PWM_CONTROL, 0x0308 },
{ TFA989X_CURRENTSENSE4, 0x0e82 },
};
static int tfa9895_init(struct regmap *regmap)
{
return regmap_multi_reg_write(regmap, tfa9895_reg_init,
ARRAY_SIZE(tfa9895_reg_init));
}
static const struct tfa989x_rev tfa9895_rev = {
.rev = TFA9895_REVISION,
.init = tfa9895_init,
};
static int tfa9897_init(struct regmap *regmap)
{
int ret;
/* Reduce slewrate by clearing iddqtestbst to avoid booster damage */
ret = regmap_write(regmap, TFA989X_CURRENTSENSE3, 0x0300);
if (ret)
return ret;
/* Enable clipping */
ret = regmap_clear_bits(regmap, TFA989X_CURRENTSENSE4, 0x1);
if (ret)
return ret;
/* Set required TDM configuration */
return regmap_write(regmap, 0x14, 0x0);
}
static const struct tfa989x_rev tfa9897_rev = {
.rev = TFA9897_REVISION,
.init = tfa9897_init,
};
/*
* Note: At the moment this driver bypasses the "CoolFlux DSP" built into the
* TFA989X amplifiers. Unfortunately, there seems to be absolutely
* no documentation for it - the public "short datasheets" do not provide
* any information about the DSP or available registers.
*
* Usually the TFA989X amplifiers are configured through proprietary userspace
* libraries. There are also some (rather complex) kernel drivers but even those
* rely on obscure firmware blobs for configuration (so-called "containers").
* They seem to contain different "profiles" with tuned speaker settings, sample
* rates and volume steps (which would be better exposed as separate ALSA mixers).
*
* Bypassing the DSP disables volume control (and perhaps some speaker
* optimization?), but at least allows using the speaker without obscure
* kernel drivers and firmware.
*
* Ideally NXP (or now Goodix) should release proper documentation for these
* amplifiers so that support for the "CoolFlux DSP" can be implemented properly.
*/
static int tfa989x_dsp_bypass(struct regmap *regmap)
{
int ret;
/* Clear CHSA to bypass DSP and take input from I2S 1 left channel */
ret = regmap_clear_bits(regmap, TFA989X_I2SREG, TFA989X_I2SREG_CHSA_MSK);
if (ret)
return ret;
/* Set DCDC compensation to off and speaker impedance to 8 ohm */
ret = regmap_update_bits(regmap, TFA989X_I2S_SEL_REG,
TFA989X_I2S_SEL_REG_DCFG_MSK |
TFA989X_I2S_SEL_REG_SPKR_MSK,
TFA989X_I2S_SEL_REG_SPKR_MSK);
if (ret)
return ret;
/* Set DCDC to follower mode and disable CoolFlux DSP */
return regmap_clear_bits(regmap, TFA989X_SYS_CTRL,
BIT(TFA989X_SYS_CTRL_DCA) |
BIT(TFA989X_SYS_CTRL_CFE) |
BIT(TFA989X_SYS_CTRL_AMPC));
}
static void tfa989x_regulator_disable(void *data)
{
struct tfa989x *tfa989x = data;
regulator_disable(tfa989x->vddd_supply);
}
static int tfa989x_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
const struct tfa989x_rev *rev;
struct tfa989x *tfa989x;
struct regmap *regmap;
unsigned int val;
int ret;
rev = device_get_match_data(dev);
if (!rev) {
dev_err(dev, "unknown device revision\n");
return -ENODEV;
}
tfa989x = devm_kzalloc(dev, sizeof(*tfa989x), GFP_KERNEL);
if (!tfa989x)
return -ENOMEM;
tfa989x->rev = rev;
i2c_set_clientdata(i2c, tfa989x);
tfa989x->vddd_supply = devm_regulator_get(dev, "vddd");
if (IS_ERR(tfa989x->vddd_supply))
return dev_err_probe(dev, PTR_ERR(tfa989x->vddd_supply),
"Failed to get vddd regulator\n");
if (tfa989x->rev->rev == TFA9897_REVISION) {
tfa989x->rcv_gpiod = devm_gpiod_get_optional(dev, "rcv", GPIOD_OUT_LOW);
if (IS_ERR(tfa989x->rcv_gpiod))
return PTR_ERR(tfa989x->rcv_gpiod);
}
regmap = devm_regmap_init_i2c(i2c, &tfa989x_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = regulator_enable(tfa989x->vddd_supply);
if (ret) {
dev_err(dev, "Failed to enable vddd regulator: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(dev, tfa989x_regulator_disable, tfa989x);
if (ret)
return ret;
/* Bypass regcache for reset and init sequence */
regcache_cache_bypass(regmap, true);
/* Dummy read to generate i2c clocks, required on some devices */
regmap_read(regmap, TFA989X_REVISIONNUMBER, &val);
ret = regmap_read(regmap, TFA989X_REVISIONNUMBER, &val);
if (ret) {
dev_err(dev, "failed to read revision number: %d\n", ret);
return ret;
}
val &= TFA989X_REVISIONNUMBER_REV_MSK;
if (val != rev->rev) {
dev_err(dev, "invalid revision number, expected %#x, got %#x\n",
rev->rev, val);
return -ENODEV;
}
ret = regmap_write(regmap, TFA989X_SYS_CTRL, BIT(TFA989X_SYS_CTRL_I2CR));
if (ret) {
dev_err(dev, "failed to reset I2C registers: %d\n", ret);
return ret;
}
ret = rev->init(regmap);
if (ret) {
dev_err(dev, "failed to initialize registers: %d\n", ret);
return ret;
}
ret = tfa989x_dsp_bypass(regmap);
if (ret) {
dev_err(dev, "failed to enable DSP bypass: %d\n", ret);
return ret;
}
regcache_cache_bypass(regmap, false);
return devm_snd_soc_register_component(dev, &tfa989x_component,
&tfa989x_dai, 1);
}
static const struct of_device_id tfa989x_of_match[] = {
{ .compatible = "nxp,tfa9890", .data = &tfa9890_rev },
{ .compatible = "nxp,tfa9895", .data = &tfa9895_rev },
{ .compatible = "nxp,tfa9897", .data = &tfa9897_rev },
{ }
};
MODULE_DEVICE_TABLE(of, tfa989x_of_match);
static struct i2c_driver tfa989x_i2c_driver = {
.driver = {
.name = "tfa989x",
.of_match_table = tfa989x_of_match,
},
.probe = tfa989x_i2c_probe,
};
module_i2c_driver(tfa989x_i2c_driver);
MODULE_DESCRIPTION("ASoC NXP/Goodix TFA989X (TFA1) driver");
MODULE_AUTHOR("Stephan Gerhold <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tfa989x.c |
// SPDX-License-Identifier: GPL-2.0
//
// Audio driver for AK5558 ADC
//
// Copyright (C) 2015 Asahi Kasei Microdevices Corporation
// Copyright 2018 NXP
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "ak5558.h"
enum ak555x_type {
AK5558,
AK5552,
};
#define AK5558_NUM_SUPPLIES 2
static const char *ak5558_supply_names[AK5558_NUM_SUPPLIES] = {
"DVDD",
"AVDD",
};
/* AK5558 Codec Private Data */
struct ak5558_priv {
struct regulator_bulk_data supplies[AK5558_NUM_SUPPLIES];
struct snd_soc_component component;
struct regmap *regmap;
struct i2c_client *i2c;
struct gpio_desc *reset_gpiod; /* Reset & Power down GPIO */
int slots;
int slot_width;
};
/* ak5558 register cache & default register settings */
static const struct reg_default ak5558_reg[] = {
{ 0x0, 0xFF }, /* 0x00 AK5558_00_POWER_MANAGEMENT1 */
{ 0x1, 0x01 }, /* 0x01 AK5558_01_POWER_MANAGEMENT2 */
{ 0x2, 0x01 }, /* 0x02 AK5558_02_CONTROL1 */
{ 0x3, 0x00 }, /* 0x03 AK5558_03_CONTROL2 */
{ 0x4, 0x00 }, /* 0x04 AK5558_04_CONTROL3 */
{ 0x5, 0x00 } /* 0x05 AK5558_05_DSD */
};
static const char * const mono_texts[] = {
"8 Slot", "2 Slot", "4 Slot", "1 Slot",
};
static const struct soc_enum ak5558_mono_enum[] = {
SOC_ENUM_SINGLE(AK5558_01_POWER_MANAGEMENT2, 1,
ARRAY_SIZE(mono_texts), mono_texts),
};
static const char * const mono_5552_texts[] = {
"2 Slot", "1 Slot (Fixed)", "2 Slot", "1 Slot (Optimal)",
};
static const struct soc_enum ak5552_mono_enum[] = {
SOC_ENUM_SINGLE(AK5558_01_POWER_MANAGEMENT2, 1,
ARRAY_SIZE(mono_5552_texts), mono_5552_texts),
};
static const char * const digfil_texts[] = {
"Sharp Roll-Off", "Slow Roll-Off",
"Short Delay Sharp Roll-Off", "Short Delay Slow Roll-Off",
};
static const struct soc_enum ak5558_adcset_enum[] = {
SOC_ENUM_SINGLE(AK5558_04_CONTROL3, 0,
ARRAY_SIZE(digfil_texts), digfil_texts),
};
static const struct snd_kcontrol_new ak5558_snd_controls[] = {
SOC_ENUM("Monaural Mode", ak5558_mono_enum[0]),
SOC_ENUM("Digital Filter", ak5558_adcset_enum[0]),
};
static const struct snd_kcontrol_new ak5552_snd_controls[] = {
SOC_ENUM("Monaural Mode", ak5552_mono_enum[0]),
SOC_ENUM("Digital Filter", ak5558_adcset_enum[0]),
};
static const struct snd_soc_dapm_widget ak5558_dapm_widgets[] = {
/* Analog Input */
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN4"),
SND_SOC_DAPM_INPUT("AIN5"),
SND_SOC_DAPM_INPUT("AIN6"),
SND_SOC_DAPM_INPUT("AIN7"),
SND_SOC_DAPM_INPUT("AIN8"),
SND_SOC_DAPM_ADC("ADC Ch1", NULL, AK5558_00_POWER_MANAGEMENT1, 0, 0),
SND_SOC_DAPM_ADC("ADC Ch2", NULL, AK5558_00_POWER_MANAGEMENT1, 1, 0),
SND_SOC_DAPM_ADC("ADC Ch3", NULL, AK5558_00_POWER_MANAGEMENT1, 2, 0),
SND_SOC_DAPM_ADC("ADC Ch4", NULL, AK5558_00_POWER_MANAGEMENT1, 3, 0),
SND_SOC_DAPM_ADC("ADC Ch5", NULL, AK5558_00_POWER_MANAGEMENT1, 4, 0),
SND_SOC_DAPM_ADC("ADC Ch6", NULL, AK5558_00_POWER_MANAGEMENT1, 5, 0),
SND_SOC_DAPM_ADC("ADC Ch7", NULL, AK5558_00_POWER_MANAGEMENT1, 6, 0),
SND_SOC_DAPM_ADC("ADC Ch8", NULL, AK5558_00_POWER_MANAGEMENT1, 7, 0),
SND_SOC_DAPM_AIF_OUT("SDTO", "Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_widget ak5552_dapm_widgets[] = {
/* Analog Input */
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_ADC("ADC Ch1", NULL, AK5558_00_POWER_MANAGEMENT1, 0, 0),
SND_SOC_DAPM_ADC("ADC Ch2", NULL, AK5558_00_POWER_MANAGEMENT1, 1, 0),
SND_SOC_DAPM_AIF_OUT("SDTO", "Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route ak5558_intercon[] = {
{"ADC Ch1", NULL, "AIN1"},
{"SDTO", NULL, "ADC Ch1"},
{"ADC Ch2", NULL, "AIN2"},
{"SDTO", NULL, "ADC Ch2"},
{"ADC Ch3", NULL, "AIN3"},
{"SDTO", NULL, "ADC Ch3"},
{"ADC Ch4", NULL, "AIN4"},
{"SDTO", NULL, "ADC Ch4"},
{"ADC Ch5", NULL, "AIN5"},
{"SDTO", NULL, "ADC Ch5"},
{"ADC Ch6", NULL, "AIN6"},
{"SDTO", NULL, "ADC Ch6"},
{"ADC Ch7", NULL, "AIN7"},
{"SDTO", NULL, "ADC Ch7"},
{"ADC Ch8", NULL, "AIN8"},
{"SDTO", NULL, "ADC Ch8"},
};
static const struct snd_soc_dapm_route ak5552_intercon[] = {
{"ADC Ch1", NULL, "AIN1"},
{"SDTO", NULL, "ADC Ch1"},
{"ADC Ch2", NULL, "AIN2"},
{"SDTO", NULL, "ADC Ch2"},
};
static int ak5558_set_mcki(struct snd_soc_component *component)
{
return snd_soc_component_update_bits(component, AK5558_02_CONTROL1, AK5558_CKS,
AK5558_CKS_AUTO);
}
static int ak5558_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
u8 bits;
int pcm_width = max(params_physical_width(params), ak5558->slot_width);
switch (pcm_width) {
case 16:
bits = AK5558_DIF_24BIT_MODE;
break;
case 32:
bits = AK5558_DIF_32BIT_MODE;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, AK5558_02_CONTROL1, AK5558_BITS, bits);
return 0;
}
static int ak5558_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u8 format;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
case SND_SOC_DAIFMT_CBP_CFP:
break;
case SND_SOC_DAIFMT_CBC_CFP:
case SND_SOC_DAIFMT_CBP_CFC:
default:
dev_err(dai->dev, "Clock mode unsupported");
return -EINVAL;
}
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = AK5558_DIF_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = AK5558_DIF_MSB_MODE;
break;
case SND_SOC_DAIFMT_DSP_B:
format = AK5558_DIF_MSB_MODE;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, AK5558_02_CONTROL1, AK5558_DIF, format);
return 0;
}
static int ak5558_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots,
int slot_width)
{
struct snd_soc_component *component = dai->component;
struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
int tdm_mode;
ak5558->slots = slots;
ak5558->slot_width = slot_width;
switch (slots * slot_width) {
case 128:
tdm_mode = AK5558_MODE_TDM128;
break;
case 256:
tdm_mode = AK5558_MODE_TDM256;
break;
case 512:
tdm_mode = AK5558_MODE_TDM512;
break;
default:
tdm_mode = AK5558_MODE_NORMAL;
break;
}
snd_soc_component_update_bits(component, AK5558_03_CONTROL2, AK5558_MODE_BITS,
tdm_mode);
return 0;
}
#define AK5558_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const unsigned int ak5558_rates[] = {
8000, 11025, 16000, 22050,
32000, 44100, 48000, 88200,
96000, 176400, 192000, 352800,
384000, 705600, 768000, 1411200,
2822400,
};
static const struct snd_pcm_hw_constraint_list ak5558_rate_constraints = {
.count = ARRAY_SIZE(ak5558_rates),
.list = ak5558_rates,
};
static int ak5558_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&ak5558_rate_constraints);
}
static const struct snd_soc_dai_ops ak5558_dai_ops = {
.startup = ak5558_startup,
.hw_params = ak5558_hw_params,
.set_fmt = ak5558_set_dai_fmt,
.set_tdm_slot = ak5558_set_tdm_slot,
};
static struct snd_soc_dai_driver ak5558_dai = {
.name = "ak5558-aif",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = AK5558_FORMATS,
},
.ops = &ak5558_dai_ops,
};
static struct snd_soc_dai_driver ak5552_dai = {
.name = "ak5552-aif",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = AK5558_FORMATS,
},
.ops = &ak5558_dai_ops,
};
static void ak5558_reset(struct ak5558_priv *ak5558, bool active)
{
if (!ak5558->reset_gpiod)
return;
gpiod_set_value_cansleep(ak5558->reset_gpiod, active);
usleep_range(1000, 2000);
}
static int ak5558_probe(struct snd_soc_component *component)
{
struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
ak5558_reset(ak5558, false);
return ak5558_set_mcki(component);
}
static void ak5558_remove(struct snd_soc_component *component)
{
struct ak5558_priv *ak5558 = snd_soc_component_get_drvdata(component);
ak5558_reset(ak5558, true);
}
static int __maybe_unused ak5558_runtime_suspend(struct device *dev)
{
struct ak5558_priv *ak5558 = dev_get_drvdata(dev);
regcache_cache_only(ak5558->regmap, true);
ak5558_reset(ak5558, true);
regulator_bulk_disable(ARRAY_SIZE(ak5558->supplies),
ak5558->supplies);
return 0;
}
static int __maybe_unused ak5558_runtime_resume(struct device *dev)
{
struct ak5558_priv *ak5558 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(ak5558->supplies),
ak5558->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ak5558_reset(ak5558, true);
ak5558_reset(ak5558, false);
regcache_cache_only(ak5558->regmap, false);
regcache_mark_dirty(ak5558->regmap);
return regcache_sync(ak5558->regmap);
}
static const struct dev_pm_ops ak5558_pm = {
SET_RUNTIME_PM_OPS(ak5558_runtime_suspend, ak5558_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct snd_soc_component_driver soc_codec_dev_ak5558 = {
.probe = ak5558_probe,
.remove = ak5558_remove,
.controls = ak5558_snd_controls,
.num_controls = ARRAY_SIZE(ak5558_snd_controls),
.dapm_widgets = ak5558_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak5558_dapm_widgets),
.dapm_routes = ak5558_intercon,
.num_dapm_routes = ARRAY_SIZE(ak5558_intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver soc_codec_dev_ak5552 = {
.probe = ak5558_probe,
.remove = ak5558_remove,
.controls = ak5552_snd_controls,
.num_controls = ARRAY_SIZE(ak5552_snd_controls),
.dapm_widgets = ak5552_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak5552_dapm_widgets),
.dapm_routes = ak5552_intercon,
.num_dapm_routes = ARRAY_SIZE(ak5552_intercon),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak5558_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AK5558_05_DSD,
.reg_defaults = ak5558_reg,
.num_reg_defaults = ARRAY_SIZE(ak5558_reg),
.cache_type = REGCACHE_RBTREE,
};
static int ak5558_i2c_probe(struct i2c_client *i2c)
{
struct ak5558_priv *ak5558;
int ret = 0;
int dev_id;
int i;
ak5558 = devm_kzalloc(&i2c->dev, sizeof(*ak5558), GFP_KERNEL);
if (!ak5558)
return -ENOMEM;
ak5558->regmap = devm_regmap_init_i2c(i2c, &ak5558_regmap);
if (IS_ERR(ak5558->regmap))
return PTR_ERR(ak5558->regmap);
i2c_set_clientdata(i2c, ak5558);
ak5558->i2c = i2c;
ak5558->reset_gpiod = devm_gpiod_get_optional(&i2c->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(ak5558->reset_gpiod))
return PTR_ERR(ak5558->reset_gpiod);
for (i = 0; i < ARRAY_SIZE(ak5558->supplies); i++)
ak5558->supplies[i].supply = ak5558_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(ak5558->supplies),
ak5558->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
dev_id = (uintptr_t)of_device_get_match_data(&i2c->dev);
switch (dev_id) {
case AK5552:
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_ak5552,
&ak5552_dai, 1);
break;
case AK5558:
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_ak5558,
&ak5558_dai, 1);
break;
default:
dev_err(&i2c->dev, "unexpected device type\n");
return -EINVAL;
}
if (ret < 0) {
dev_err(&i2c->dev, "failed to register component: %d\n", ret);
return ret;
}
pm_runtime_enable(&i2c->dev);
regcache_cache_only(ak5558->regmap, true);
return 0;
}
static void ak5558_i2c_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
}
static const struct of_device_id ak5558_i2c_dt_ids[] __maybe_unused = {
{ .compatible = "asahi-kasei,ak5558", .data = (void *) AK5558 },
{ .compatible = "asahi-kasei,ak5552", .data = (void *) AK5552 },
{ }
};
MODULE_DEVICE_TABLE(of, ak5558_i2c_dt_ids);
static struct i2c_driver ak5558_i2c_driver = {
.driver = {
.name = "ak5558",
.of_match_table = of_match_ptr(ak5558_i2c_dt_ids),
.pm = &ak5558_pm,
},
.probe = ak5558_i2c_probe,
.remove = ak5558_i2c_remove,
};
module_i2c_driver(ak5558_i2c_driver);
MODULE_AUTHOR("Junichi Wakasugi <[email protected]>");
MODULE_AUTHOR("Mihai Serban <[email protected]>");
MODULE_DESCRIPTION("ASoC AK5558 ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ak5558.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Load Analog Devices SigmaStudio firmware files
*
* Copyright 2009-2014 Analog Devices Inc.
*/
#include <linux/crc32.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/control.h>
#include <sound/soc.h>
#include "sigmadsp.h"
#define SIGMA_MAGIC "ADISIGM"
#define SIGMA_FW_CHUNK_TYPE_DATA 0
#define SIGMA_FW_CHUNK_TYPE_CONTROL 1
#define SIGMA_FW_CHUNK_TYPE_SAMPLERATES 2
#define READBACK_CTRL_NAME "ReadBack"
struct sigmadsp_control {
struct list_head head;
uint32_t samplerates;
unsigned int addr;
unsigned int num_bytes;
const char *name;
struct snd_kcontrol *kcontrol;
bool is_readback;
bool cached;
uint8_t cache[];
};
struct sigmadsp_data {
struct list_head head;
uint32_t samplerates;
unsigned int addr;
unsigned int length;
uint8_t data[];
};
struct sigma_fw_chunk {
__le32 length;
__le32 tag;
__le32 samplerates;
} __packed;
struct sigma_fw_chunk_data {
struct sigma_fw_chunk chunk;
__le16 addr;
uint8_t data[];
} __packed;
struct sigma_fw_chunk_control {
struct sigma_fw_chunk chunk;
__le16 type;
__le16 addr;
__le16 num_bytes;
const char name[];
} __packed;
struct sigma_fw_chunk_samplerate {
struct sigma_fw_chunk chunk;
__le32 samplerates[];
} __packed;
struct sigma_firmware_header {
unsigned char magic[7];
u8 version;
__le32 crc;
} __packed;
enum {
SIGMA_ACTION_WRITEXBYTES = 0,
SIGMA_ACTION_WRITESINGLE,
SIGMA_ACTION_WRITESAFELOAD,
SIGMA_ACTION_END,
};
struct sigma_action {
u8 instr;
u8 len_hi;
__le16 len;
__be16 addr;
unsigned char payload[];
} __packed;
static int sigmadsp_write(struct sigmadsp *sigmadsp, unsigned int addr,
const uint8_t data[], size_t len)
{
return sigmadsp->write(sigmadsp->control_data, addr, data, len);
}
static int sigmadsp_read(struct sigmadsp *sigmadsp, unsigned int addr,
uint8_t data[], size_t len)
{
return sigmadsp->read(sigmadsp->control_data, addr, data, len);
}
static int sigmadsp_ctrl_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *info)
{
struct sigmadsp_control *ctrl = (void *)kcontrol->private_value;
info->type = SNDRV_CTL_ELEM_TYPE_BYTES;
info->count = ctrl->num_bytes;
return 0;
}
static int sigmadsp_ctrl_write(struct sigmadsp *sigmadsp,
struct sigmadsp_control *ctrl, void *data)
{
/* safeload loads up to 20 bytes in a atomic operation */
if (ctrl->num_bytes <= 20 && sigmadsp->ops && sigmadsp->ops->safeload)
return sigmadsp->ops->safeload(sigmadsp, ctrl->addr, data,
ctrl->num_bytes);
else
return sigmadsp_write(sigmadsp, ctrl->addr, data,
ctrl->num_bytes);
}
static int sigmadsp_ctrl_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sigmadsp_control *ctrl = (void *)kcontrol->private_value;
struct sigmadsp *sigmadsp = snd_kcontrol_chip(kcontrol);
uint8_t *data;
int ret = 0;
mutex_lock(&sigmadsp->lock);
data = ucontrol->value.bytes.data;
if (!(kcontrol->vd[0].access & SNDRV_CTL_ELEM_ACCESS_INACTIVE))
ret = sigmadsp_ctrl_write(sigmadsp, ctrl, data);
if (ret == 0) {
memcpy(ctrl->cache, data, ctrl->num_bytes);
if (!ctrl->is_readback)
ctrl->cached = true;
}
mutex_unlock(&sigmadsp->lock);
return ret;
}
static int sigmadsp_ctrl_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sigmadsp_control *ctrl = (void *)kcontrol->private_value;
struct sigmadsp *sigmadsp = snd_kcontrol_chip(kcontrol);
int ret = 0;
mutex_lock(&sigmadsp->lock);
if (!ctrl->cached) {
ret = sigmadsp_read(sigmadsp, ctrl->addr, ctrl->cache,
ctrl->num_bytes);
}
if (ret == 0) {
if (!ctrl->is_readback)
ctrl->cached = true;
memcpy(ucontrol->value.bytes.data, ctrl->cache,
ctrl->num_bytes);
}
mutex_unlock(&sigmadsp->lock);
return ret;
}
static void sigmadsp_control_free(struct snd_kcontrol *kcontrol)
{
struct sigmadsp_control *ctrl = (void *)kcontrol->private_value;
ctrl->kcontrol = NULL;
}
static bool sigma_fw_validate_control_name(const char *name, unsigned int len)
{
unsigned int i;
for (i = 0; i < len; i++) {
/* Normal ASCII characters are valid */
if (name[i] < ' ' || name[i] > '~')
return false;
}
return true;
}
static int sigma_fw_load_control(struct sigmadsp *sigmadsp,
const struct sigma_fw_chunk *chunk, unsigned int length)
{
const struct sigma_fw_chunk_control *ctrl_chunk;
struct sigmadsp_control *ctrl;
unsigned int num_bytes;
size_t name_len;
char *name;
int ret;
if (length <= sizeof(*ctrl_chunk))
return -EINVAL;
ctrl_chunk = (const struct sigma_fw_chunk_control *)chunk;
name_len = length - sizeof(*ctrl_chunk);
if (name_len >= SNDRV_CTL_ELEM_ID_NAME_MAXLEN)
name_len = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - 1;
/* Make sure there are no non-displayable characaters in the string */
if (!sigma_fw_validate_control_name(ctrl_chunk->name, name_len))
return -EINVAL;
num_bytes = le16_to_cpu(ctrl_chunk->num_bytes);
ctrl = kzalloc(sizeof(*ctrl) + num_bytes, GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
name = kmemdup_nul(ctrl_chunk->name, name_len, GFP_KERNEL);
if (!name) {
ret = -ENOMEM;
goto err_free_ctrl;
}
ctrl->name = name;
/*
* Readbacks doesn't work with non-volatile controls, since the
* firmware updates the control value without driver interaction. Mark
* the readbacks to ensure that the values are not cached.
*/
if (ctrl->name && strncmp(ctrl->name, READBACK_CTRL_NAME,
(sizeof(READBACK_CTRL_NAME) - 1)) == 0)
ctrl->is_readback = true;
ctrl->addr = le16_to_cpu(ctrl_chunk->addr);
ctrl->num_bytes = num_bytes;
ctrl->samplerates = le32_to_cpu(chunk->samplerates);
list_add_tail(&ctrl->head, &sigmadsp->ctrl_list);
return 0;
err_free_ctrl:
kfree(ctrl);
return ret;
}
static int sigma_fw_load_data(struct sigmadsp *sigmadsp,
const struct sigma_fw_chunk *chunk, unsigned int length)
{
const struct sigma_fw_chunk_data *data_chunk;
struct sigmadsp_data *data;
if (length <= sizeof(*data_chunk))
return -EINVAL;
data_chunk = (struct sigma_fw_chunk_data *)chunk;
length -= sizeof(*data_chunk);
data = kzalloc(sizeof(*data) + length, GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = le16_to_cpu(data_chunk->addr);
data->length = length;
data->samplerates = le32_to_cpu(chunk->samplerates);
memcpy(data->data, data_chunk->data, length);
list_add_tail(&data->head, &sigmadsp->data_list);
return 0;
}
static int sigma_fw_load_samplerates(struct sigmadsp *sigmadsp,
const struct sigma_fw_chunk *chunk, unsigned int length)
{
const struct sigma_fw_chunk_samplerate *rate_chunk;
unsigned int num_rates;
unsigned int *rates;
unsigned int i;
rate_chunk = (const struct sigma_fw_chunk_samplerate *)chunk;
num_rates = (length - sizeof(*rate_chunk)) / sizeof(__le32);
if (num_rates > 32 || num_rates == 0)
return -EINVAL;
/* We only allow one samplerates block per file */
if (sigmadsp->rate_constraints.count)
return -EINVAL;
rates = kcalloc(num_rates, sizeof(*rates), GFP_KERNEL);
if (!rates)
return -ENOMEM;
for (i = 0; i < num_rates; i++)
rates[i] = le32_to_cpu(rate_chunk->samplerates[i]);
sigmadsp->rate_constraints.count = num_rates;
sigmadsp->rate_constraints.list = rates;
return 0;
}
static int sigmadsp_fw_load_v2(struct sigmadsp *sigmadsp,
const struct firmware *fw)
{
struct sigma_fw_chunk *chunk;
unsigned int length, pos;
int ret;
/*
* Make sure that there is at least one chunk to avoid integer
* underflows later on. Empty firmware is still valid though.
*/
if (fw->size < sizeof(*chunk) + sizeof(struct sigma_firmware_header))
return 0;
pos = sizeof(struct sigma_firmware_header);
while (pos < fw->size - sizeof(*chunk)) {
chunk = (struct sigma_fw_chunk *)(fw->data + pos);
length = le32_to_cpu(chunk->length);
if (length > fw->size - pos || length < sizeof(*chunk))
return -EINVAL;
switch (le32_to_cpu(chunk->tag)) {
case SIGMA_FW_CHUNK_TYPE_DATA:
ret = sigma_fw_load_data(sigmadsp, chunk, length);
break;
case SIGMA_FW_CHUNK_TYPE_CONTROL:
ret = sigma_fw_load_control(sigmadsp, chunk, length);
break;
case SIGMA_FW_CHUNK_TYPE_SAMPLERATES:
ret = sigma_fw_load_samplerates(sigmadsp, chunk, length);
break;
default:
dev_warn(sigmadsp->dev, "Unknown chunk type: %d\n",
chunk->tag);
ret = 0;
break;
}
if (ret)
return ret;
/*
* This can not overflow since if length is larger than the
* maximum firmware size (0x4000000) we'll error out earilier.
*/
pos += ALIGN(length, sizeof(__le32));
}
return 0;
}
static inline u32 sigma_action_len(struct sigma_action *sa)
{
return (sa->len_hi << 16) | le16_to_cpu(sa->len);
}
static size_t sigma_action_size(struct sigma_action *sa)
{
size_t payload = 0;
switch (sa->instr) {
case SIGMA_ACTION_WRITEXBYTES:
case SIGMA_ACTION_WRITESINGLE:
case SIGMA_ACTION_WRITESAFELOAD:
payload = sigma_action_len(sa);
break;
default:
break;
}
payload = ALIGN(payload, 2);
return payload + sizeof(struct sigma_action);
}
/*
* Returns a negative error value in case of an error, 0 if processing of
* the firmware should be stopped after this action, 1 otherwise.
*/
static int process_sigma_action(struct sigmadsp *sigmadsp,
struct sigma_action *sa)
{
size_t len = sigma_action_len(sa);
struct sigmadsp_data *data;
pr_debug("%s: instr:%i addr:%#x len:%zu\n", __func__,
sa->instr, sa->addr, len);
switch (sa->instr) {
case SIGMA_ACTION_WRITEXBYTES:
case SIGMA_ACTION_WRITESINGLE:
case SIGMA_ACTION_WRITESAFELOAD:
if (len < 3)
return -EINVAL;
data = kzalloc(sizeof(*data) + len - 2, GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = be16_to_cpu(sa->addr);
data->length = len - 2;
memcpy(data->data, sa->payload, data->length);
list_add_tail(&data->head, &sigmadsp->data_list);
break;
case SIGMA_ACTION_END:
return 0;
default:
return -EINVAL;
}
return 1;
}
static int sigmadsp_fw_load_v1(struct sigmadsp *sigmadsp,
const struct firmware *fw)
{
struct sigma_action *sa;
size_t size, pos;
int ret;
pos = sizeof(struct sigma_firmware_header);
while (pos + sizeof(*sa) <= fw->size) {
sa = (struct sigma_action *)(fw->data + pos);
size = sigma_action_size(sa);
pos += size;
if (pos > fw->size || size == 0)
break;
ret = process_sigma_action(sigmadsp, sa);
pr_debug("%s: action returned %i\n", __func__, ret);
if (ret <= 0)
return ret;
}
if (pos != fw->size)
return -EINVAL;
return 0;
}
static void sigmadsp_firmware_release(struct sigmadsp *sigmadsp)
{
struct sigmadsp_control *ctrl, *_ctrl;
struct sigmadsp_data *data, *_data;
list_for_each_entry_safe(ctrl, _ctrl, &sigmadsp->ctrl_list, head) {
kfree(ctrl->name);
kfree(ctrl);
}
list_for_each_entry_safe(data, _data, &sigmadsp->data_list, head)
kfree(data);
INIT_LIST_HEAD(&sigmadsp->ctrl_list);
INIT_LIST_HEAD(&sigmadsp->data_list);
}
static void devm_sigmadsp_release(struct device *dev, void *res)
{
sigmadsp_firmware_release((struct sigmadsp *)res);
}
static int sigmadsp_firmware_load(struct sigmadsp *sigmadsp, const char *name)
{
const struct sigma_firmware_header *ssfw_head;
const struct firmware *fw;
int ret;
u32 crc;
/* first load the blob */
ret = request_firmware(&fw, name, sigmadsp->dev);
if (ret) {
pr_debug("%s: request_firmware() failed with %i\n", __func__, ret);
goto done;
}
/* then verify the header */
ret = -EINVAL;
/*
* Reject too small or unreasonable large files. The upper limit has been
* chosen a bit arbitrarily, but it should be enough for all practical
* purposes and having the limit makes it easier to avoid integer
* overflows later in the loading process.
*/
if (fw->size < sizeof(*ssfw_head) || fw->size >= 0x4000000) {
dev_err(sigmadsp->dev, "Failed to load firmware: Invalid size\n");
goto done;
}
ssfw_head = (void *)fw->data;
if (memcmp(ssfw_head->magic, SIGMA_MAGIC, ARRAY_SIZE(ssfw_head->magic))) {
dev_err(sigmadsp->dev, "Failed to load firmware: Invalid magic\n");
goto done;
}
crc = crc32(0, fw->data + sizeof(*ssfw_head),
fw->size - sizeof(*ssfw_head));
pr_debug("%s: crc=%x\n", __func__, crc);
if (crc != le32_to_cpu(ssfw_head->crc)) {
dev_err(sigmadsp->dev, "Failed to load firmware: Wrong crc checksum: expected %x got %x\n",
le32_to_cpu(ssfw_head->crc), crc);
goto done;
}
switch (ssfw_head->version) {
case 1:
ret = sigmadsp_fw_load_v1(sigmadsp, fw);
break;
case 2:
ret = sigmadsp_fw_load_v2(sigmadsp, fw);
break;
default:
dev_err(sigmadsp->dev,
"Failed to load firmware: Invalid version %d. Supported firmware versions: 1, 2\n",
ssfw_head->version);
ret = -EINVAL;
break;
}
if (ret)
sigmadsp_firmware_release(sigmadsp);
done:
release_firmware(fw);
return ret;
}
static int sigmadsp_init(struct sigmadsp *sigmadsp, struct device *dev,
const struct sigmadsp_ops *ops, const char *firmware_name)
{
sigmadsp->ops = ops;
sigmadsp->dev = dev;
INIT_LIST_HEAD(&sigmadsp->ctrl_list);
INIT_LIST_HEAD(&sigmadsp->data_list);
mutex_init(&sigmadsp->lock);
return sigmadsp_firmware_load(sigmadsp, firmware_name);
}
/**
* devm_sigmadsp_init() - Initialize SigmaDSP instance
* @dev: The parent device
* @ops: The sigmadsp_ops to use for this instance
* @firmware_name: Name of the firmware file to load
*
* Allocates a SigmaDSP instance and loads the specified firmware file.
*
* Returns a pointer to a struct sigmadsp on success, or a PTR_ERR() on error.
*/
struct sigmadsp *devm_sigmadsp_init(struct device *dev,
const struct sigmadsp_ops *ops, const char *firmware_name)
{
struct sigmadsp *sigmadsp;
int ret;
sigmadsp = devres_alloc(devm_sigmadsp_release, sizeof(*sigmadsp),
GFP_KERNEL);
if (!sigmadsp)
return ERR_PTR(-ENOMEM);
ret = sigmadsp_init(sigmadsp, dev, ops, firmware_name);
if (ret) {
devres_free(sigmadsp);
return ERR_PTR(ret);
}
devres_add(dev, sigmadsp);
return sigmadsp;
}
EXPORT_SYMBOL_GPL(devm_sigmadsp_init);
static int sigmadsp_rate_to_index(struct sigmadsp *sigmadsp, unsigned int rate)
{
unsigned int i;
for (i = 0; i < sigmadsp->rate_constraints.count; i++) {
if (sigmadsp->rate_constraints.list[i] == rate)
return i;
}
return -EINVAL;
}
static unsigned int sigmadsp_get_samplerate_mask(struct sigmadsp *sigmadsp,
unsigned int samplerate)
{
int samplerate_index;
if (samplerate == 0)
return 0;
if (sigmadsp->rate_constraints.count) {
samplerate_index = sigmadsp_rate_to_index(sigmadsp, samplerate);
if (samplerate_index < 0)
return 0;
return BIT(samplerate_index);
} else {
return ~0;
}
}
static bool sigmadsp_samplerate_valid(unsigned int supported,
unsigned int requested)
{
/* All samplerates are supported */
if (!supported)
return true;
return supported & requested;
}
static int sigmadsp_alloc_control(struct sigmadsp *sigmadsp,
struct sigmadsp_control *ctrl, unsigned int samplerate_mask)
{
struct snd_kcontrol_new template;
struct snd_kcontrol *kcontrol;
memset(&template, 0, sizeof(template));
template.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
template.name = ctrl->name;
template.info = sigmadsp_ctrl_info;
template.get = sigmadsp_ctrl_get;
template.put = sigmadsp_ctrl_put;
template.private_value = (unsigned long)ctrl;
template.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
if (!sigmadsp_samplerate_valid(ctrl->samplerates, samplerate_mask))
template.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
kcontrol = snd_ctl_new1(&template, sigmadsp);
if (!kcontrol)
return -ENOMEM;
kcontrol->private_free = sigmadsp_control_free;
ctrl->kcontrol = kcontrol;
return snd_ctl_add(sigmadsp->component->card->snd_card, kcontrol);
}
static void sigmadsp_activate_ctrl(struct sigmadsp *sigmadsp,
struct sigmadsp_control *ctrl, unsigned int samplerate_mask)
{
struct snd_card *card = sigmadsp->component->card->snd_card;
bool active;
int changed;
active = sigmadsp_samplerate_valid(ctrl->samplerates, samplerate_mask);
if (!ctrl->kcontrol)
return;
changed = snd_ctl_activate_id(card, &ctrl->kcontrol->id, active);
if (active && changed > 0) {
mutex_lock(&sigmadsp->lock);
if (ctrl->cached)
sigmadsp_ctrl_write(sigmadsp, ctrl, ctrl->cache);
mutex_unlock(&sigmadsp->lock);
}
}
/**
* sigmadsp_attach() - Attach a sigmadsp instance to a ASoC component
* @sigmadsp: The sigmadsp instance to attach
* @component: The component to attach to
*
* Typically called in the components probe callback.
*
* Note, once this function has been called the firmware must not be released
* until after the ALSA snd_card that the component belongs to has been
* disconnected, even if sigmadsp_attach() returns an error.
*/
int sigmadsp_attach(struct sigmadsp *sigmadsp,
struct snd_soc_component *component)
{
struct sigmadsp_control *ctrl;
unsigned int samplerate_mask;
int ret;
sigmadsp->component = component;
samplerate_mask = sigmadsp_get_samplerate_mask(sigmadsp,
sigmadsp->current_samplerate);
list_for_each_entry(ctrl, &sigmadsp->ctrl_list, head) {
ret = sigmadsp_alloc_control(sigmadsp, ctrl, samplerate_mask);
if (ret)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(sigmadsp_attach);
/**
* sigmadsp_setup() - Setup the DSP for the specified samplerate
* @sigmadsp: The sigmadsp instance to configure
* @samplerate: The samplerate the DSP should be configured for
*
* Loads the appropriate firmware program and parameter memory (if not already
* loaded) and enables the controls for the specified samplerate. Any control
* parameter changes that have been made previously will be restored.
*
* Returns 0 on success, a negative error code otherwise.
*/
int sigmadsp_setup(struct sigmadsp *sigmadsp, unsigned int samplerate)
{
struct sigmadsp_control *ctrl;
unsigned int samplerate_mask;
struct sigmadsp_data *data;
int ret;
if (sigmadsp->current_samplerate == samplerate)
return 0;
samplerate_mask = sigmadsp_get_samplerate_mask(sigmadsp, samplerate);
if (samplerate_mask == 0)
return -EINVAL;
list_for_each_entry(data, &sigmadsp->data_list, head) {
if (!sigmadsp_samplerate_valid(data->samplerates,
samplerate_mask))
continue;
ret = sigmadsp_write(sigmadsp, data->addr, data->data,
data->length);
if (ret)
goto err;
}
list_for_each_entry(ctrl, &sigmadsp->ctrl_list, head)
sigmadsp_activate_ctrl(sigmadsp, ctrl, samplerate_mask);
sigmadsp->current_samplerate = samplerate;
return 0;
err:
sigmadsp_reset(sigmadsp);
return ret;
}
EXPORT_SYMBOL_GPL(sigmadsp_setup);
/**
* sigmadsp_reset() - Notify the sigmadsp instance that the DSP has been reset
* @sigmadsp: The sigmadsp instance to reset
*
* Should be called whenever the DSP has been reset and parameter and program
* memory need to be re-loaded.
*/
void sigmadsp_reset(struct sigmadsp *sigmadsp)
{
struct sigmadsp_control *ctrl;
list_for_each_entry(ctrl, &sigmadsp->ctrl_list, head)
sigmadsp_activate_ctrl(sigmadsp, ctrl, false);
sigmadsp->current_samplerate = 0;
}
EXPORT_SYMBOL_GPL(sigmadsp_reset);
/**
* sigmadsp_restrict_params() - Applies DSP firmware specific constraints
* @sigmadsp: The sigmadsp instance
* @substream: The substream to restrict
*
* Applies samplerate constraints that may be required by the firmware Should
* typically be called from the CODEC/component drivers startup callback.
*
* Returns 0 on success, a negative error code otherwise.
*/
int sigmadsp_restrict_params(struct sigmadsp *sigmadsp,
struct snd_pcm_substream *substream)
{
if (sigmadsp->rate_constraints.count == 0)
return 0;
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &sigmadsp->rate_constraints);
}
EXPORT_SYMBOL_GPL(sigmadsp_restrict_params);
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sigmadsp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5668.c -- RT5668B ALSA SoC audio component driver
*
* Copyright 2018 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5668.h>
#include "rl6231.h"
#include "rt5668.h"
#define RT5668_NUM_SUPPLIES 3
static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = {
"AVDD",
"MICVDD",
"VBAT",
};
struct rt5668_priv {
struct snd_soc_component *component;
struct rt5668_platform_data pdata;
struct gpio_desc *ldo1_en;
struct regmap *regmap;
struct snd_soc_jack *hs_jack;
struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES];
struct delayed_work jack_detect_work;
struct delayed_work jd_check_work;
struct mutex calibrate_mutex;
int sysclk;
int sysclk_src;
int lrck[RT5668_AIFS];
int bclk[RT5668_AIFS];
int master[RT5668_AIFS];
int pll_src;
int pll_in;
int pll_out;
int jack_type;
};
static const struct reg_default rt5668_reg[] = {
{0x0002, 0x8080},
{0x0003, 0x8000},
{0x0005, 0x0000},
{0x0006, 0x0000},
{0x0008, 0x800f},
{0x000b, 0x0000},
{0x0010, 0x4040},
{0x0011, 0x0000},
{0x0012, 0x1404},
{0x0013, 0x1000},
{0x0014, 0xa00a},
{0x0015, 0x0404},
{0x0016, 0x0404},
{0x0019, 0xafaf},
{0x001c, 0x2f2f},
{0x001f, 0x0000},
{0x0022, 0x5757},
{0x0023, 0x0039},
{0x0024, 0x000b},
{0x0026, 0xc0c4},
{0x0029, 0x8080},
{0x002a, 0xa0a0},
{0x002b, 0x0300},
{0x0030, 0x0000},
{0x003c, 0x0080},
{0x0044, 0x0c0c},
{0x0049, 0x0000},
{0x0061, 0x0000},
{0x0062, 0x0000},
{0x0063, 0x003f},
{0x0064, 0x0000},
{0x0065, 0x0000},
{0x0066, 0x0030},
{0x0067, 0x0000},
{0x006b, 0x0000},
{0x006c, 0x0000},
{0x006d, 0x2200},
{0x006e, 0x0a10},
{0x0070, 0x8000},
{0x0071, 0x8000},
{0x0073, 0x0000},
{0x0074, 0x0000},
{0x0075, 0x0002},
{0x0076, 0x0001},
{0x0079, 0x0000},
{0x007a, 0x0000},
{0x007b, 0x0000},
{0x007c, 0x0100},
{0x007e, 0x0000},
{0x0080, 0x0000},
{0x0081, 0x0000},
{0x0082, 0x0000},
{0x0083, 0x0000},
{0x0084, 0x0000},
{0x0085, 0x0000},
{0x0086, 0x0005},
{0x0087, 0x0000},
{0x0088, 0x0000},
{0x008c, 0x0003},
{0x008d, 0x0000},
{0x008e, 0x0060},
{0x008f, 0x1000},
{0x0091, 0x0c26},
{0x0092, 0x0073},
{0x0093, 0x0000},
{0x0094, 0x0080},
{0x0098, 0x0000},
{0x009a, 0x0000},
{0x009b, 0x0000},
{0x009c, 0x0000},
{0x009d, 0x0000},
{0x009e, 0x100c},
{0x009f, 0x0000},
{0x00a0, 0x0000},
{0x00a3, 0x0002},
{0x00a4, 0x0001},
{0x00ae, 0x2040},
{0x00af, 0x0000},
{0x00b6, 0x0000},
{0x00b7, 0x0000},
{0x00b8, 0x0000},
{0x00b9, 0x0002},
{0x00be, 0x0000},
{0x00c0, 0x0160},
{0x00c1, 0x82a0},
{0x00c2, 0x0000},
{0x00d0, 0x0000},
{0x00d1, 0x2244},
{0x00d2, 0x3300},
{0x00d3, 0x2200},
{0x00d4, 0x0000},
{0x00d9, 0x0009},
{0x00da, 0x0000},
{0x00db, 0x0000},
{0x00dc, 0x00c0},
{0x00dd, 0x2220},
{0x00de, 0x3131},
{0x00df, 0x3131},
{0x00e0, 0x3131},
{0x00e2, 0x0000},
{0x00e3, 0x4000},
{0x00e4, 0x0aa0},
{0x00e5, 0x3131},
{0x00e6, 0x3131},
{0x00e7, 0x3131},
{0x00e8, 0x3131},
{0x00ea, 0xb320},
{0x00eb, 0x0000},
{0x00f0, 0x0000},
{0x00f1, 0x00d0},
{0x00f2, 0x00d0},
{0x00f6, 0x0000},
{0x00fa, 0x0000},
{0x00fb, 0x0000},
{0x00fc, 0x0000},
{0x00fd, 0x0000},
{0x00fe, 0x10ec},
{0x00ff, 0x6530},
{0x0100, 0xa0a0},
{0x010b, 0x0000},
{0x010c, 0xae00},
{0x010d, 0xaaa0},
{0x010e, 0x8aa2},
{0x010f, 0x02a2},
{0x0110, 0xc000},
{0x0111, 0x04a2},
{0x0112, 0x2800},
{0x0113, 0x0000},
{0x0117, 0x0100},
{0x0125, 0x0410},
{0x0132, 0x6026},
{0x0136, 0x5555},
{0x0138, 0x3700},
{0x013a, 0x2000},
{0x013b, 0x2000},
{0x013c, 0x2005},
{0x013f, 0x0000},
{0x0142, 0x0000},
{0x0145, 0x0002},
{0x0146, 0x0000},
{0x0147, 0x0000},
{0x0148, 0x0000},
{0x0149, 0x0000},
{0x0150, 0x79a1},
{0x0151, 0x0000},
{0x0160, 0x4ec0},
{0x0161, 0x0080},
{0x0162, 0x0200},
{0x0163, 0x0800},
{0x0164, 0x0000},
{0x0165, 0x0000},
{0x0166, 0x0000},
{0x0167, 0x000f},
{0x0168, 0x000f},
{0x0169, 0x0021},
{0x0190, 0x413d},
{0x0194, 0x0000},
{0x0195, 0x0000},
{0x0197, 0x0022},
{0x0198, 0x0000},
{0x0199, 0x0000},
{0x01af, 0x0000},
{0x01b0, 0x0400},
{0x01b1, 0x0000},
{0x01b2, 0x0000},
{0x01b3, 0x0000},
{0x01b4, 0x0000},
{0x01b5, 0x0000},
{0x01b6, 0x01c3},
{0x01b7, 0x02a0},
{0x01b8, 0x03e9},
{0x01b9, 0x1389},
{0x01ba, 0xc351},
{0x01bb, 0x0009},
{0x01bc, 0x0018},
{0x01bd, 0x002a},
{0x01be, 0x004c},
{0x01bf, 0x0097},
{0x01c0, 0x433d},
{0x01c1, 0x2800},
{0x01c2, 0x0000},
{0x01c3, 0x0000},
{0x01c4, 0x0000},
{0x01c5, 0x0000},
{0x01c6, 0x0000},
{0x01c7, 0x0000},
{0x01c8, 0x40af},
{0x01c9, 0x0702},
{0x01ca, 0x0000},
{0x01cb, 0x0000},
{0x01cc, 0x5757},
{0x01cd, 0x5757},
{0x01ce, 0x5757},
{0x01cf, 0x5757},
{0x01d0, 0x5757},
{0x01d1, 0x5757},
{0x01d2, 0x5757},
{0x01d3, 0x5757},
{0x01d4, 0x5757},
{0x01d5, 0x5757},
{0x01d6, 0x0000},
{0x01d7, 0x0008},
{0x01d8, 0x0029},
{0x01d9, 0x3333},
{0x01da, 0x0000},
{0x01db, 0x0004},
{0x01dc, 0x0000},
{0x01de, 0x7c00},
{0x01df, 0x0320},
{0x01e0, 0x06a1},
{0x01e1, 0x0000},
{0x01e2, 0x0000},
{0x01e3, 0x0000},
{0x01e4, 0x0000},
{0x01e6, 0x0001},
{0x01e7, 0x0000},
{0x01e8, 0x0000},
{0x01ea, 0x0000},
{0x01eb, 0x0000},
{0x01ec, 0x0000},
{0x01ed, 0x0000},
{0x01ee, 0x0000},
{0x01ef, 0x0000},
{0x01f0, 0x0000},
{0x01f1, 0x0000},
{0x01f2, 0x0000},
{0x01f3, 0x0000},
{0x01f4, 0x0000},
{0x0210, 0x6297},
{0x0211, 0xa005},
{0x0212, 0x824c},
{0x0213, 0xf7ff},
{0x0214, 0xf24c},
{0x0215, 0x0102},
{0x0216, 0x00a3},
{0x0217, 0x0048},
{0x0218, 0xa2c0},
{0x0219, 0x0400},
{0x021a, 0x00c8},
{0x021b, 0x00c0},
{0x021c, 0x0000},
{0x0250, 0x4500},
{0x0251, 0x40b3},
{0x0252, 0x0000},
{0x0253, 0x0000},
{0x0254, 0x0000},
{0x0255, 0x0000},
{0x0256, 0x0000},
{0x0257, 0x0000},
{0x0258, 0x0000},
{0x0259, 0x0000},
{0x025a, 0x0005},
{0x0270, 0x0000},
{0x02ff, 0x0110},
{0x0300, 0x001f},
{0x0301, 0x032c},
{0x0302, 0x5f21},
{0x0303, 0x4000},
{0x0304, 0x4000},
{0x0305, 0x06d5},
{0x0306, 0x8000},
{0x0307, 0x0700},
{0x0310, 0x4560},
{0x0311, 0xa4a8},
{0x0312, 0x7418},
{0x0313, 0x0000},
{0x0314, 0x0006},
{0x0315, 0xffff},
{0x0316, 0xc400},
{0x0317, 0x0000},
{0x03c0, 0x7e00},
{0x03c1, 0x8000},
{0x03c2, 0x8000},
{0x03c3, 0x8000},
{0x03c4, 0x8000},
{0x03c5, 0x8000},
{0x03c6, 0x8000},
{0x03c7, 0x8000},
{0x03c8, 0x8000},
{0x03c9, 0x8000},
{0x03ca, 0x8000},
{0x03cb, 0x8000},
{0x03cc, 0x8000},
{0x03d0, 0x0000},
{0x03d1, 0x0000},
{0x03d2, 0x0000},
{0x03d3, 0x0000},
{0x03d4, 0x2000},
{0x03d5, 0x2000},
{0x03d6, 0x0000},
{0x03d7, 0x0000},
{0x03d8, 0x2000},
{0x03d9, 0x2000},
{0x03da, 0x2000},
{0x03db, 0x2000},
{0x03dc, 0x0000},
{0x03dd, 0x0000},
{0x03de, 0x0000},
{0x03df, 0x2000},
{0x03e0, 0x0000},
{0x03e1, 0x0000},
{0x03e2, 0x0000},
{0x03e3, 0x0000},
{0x03e4, 0x0000},
{0x03e5, 0x0000},
{0x03e6, 0x0000},
{0x03e7, 0x0000},
{0x03e8, 0x0000},
{0x03e9, 0x0000},
{0x03ea, 0x0000},
{0x03eb, 0x0000},
{0x03ec, 0x0000},
{0x03ed, 0x0000},
{0x03ee, 0x0000},
{0x03ef, 0x0000},
{0x03f0, 0x0800},
{0x03f1, 0x0800},
{0x03f2, 0x0800},
{0x03f3, 0x0800},
};
static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5668_RESET:
case RT5668_CBJ_CTRL_2:
case RT5668_INT_ST_1:
case RT5668_4BTN_IL_CMD_1:
case RT5668_AJD1_CTRL:
case RT5668_HP_CALIB_CTRL_1:
case RT5668_DEVICE_ID:
case RT5668_I2C_MODE:
case RT5668_HP_CALIB_CTRL_10:
case RT5668_EFUSE_CTRL_2:
case RT5668_JD_TOP_VC_VTRL:
case RT5668_HP_IMP_SENS_CTRL_19:
case RT5668_IL_CMD_1:
case RT5668_SAR_IL_CMD_2:
case RT5668_SAR_IL_CMD_4:
case RT5668_SAR_IL_CMD_10:
case RT5668_SAR_IL_CMD_11:
case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11:
case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11:
return true;
default:
return false;
}
}
static bool rt5668_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5668_RESET:
case RT5668_VERSION_ID:
case RT5668_VENDOR_ID:
case RT5668_DEVICE_ID:
case RT5668_HP_CTRL_1:
case RT5668_HP_CTRL_2:
case RT5668_HPL_GAIN:
case RT5668_HPR_GAIN:
case RT5668_I2C_CTRL:
case RT5668_CBJ_BST_CTRL:
case RT5668_CBJ_CTRL_1:
case RT5668_CBJ_CTRL_2:
case RT5668_CBJ_CTRL_3:
case RT5668_CBJ_CTRL_4:
case RT5668_CBJ_CTRL_5:
case RT5668_CBJ_CTRL_6:
case RT5668_CBJ_CTRL_7:
case RT5668_DAC1_DIG_VOL:
case RT5668_STO1_ADC_DIG_VOL:
case RT5668_STO1_ADC_BOOST:
case RT5668_HP_IMP_GAIN_1:
case RT5668_HP_IMP_GAIN_2:
case RT5668_SIDETONE_CTRL:
case RT5668_STO1_ADC_MIXER:
case RT5668_AD_DA_MIXER:
case RT5668_STO1_DAC_MIXER:
case RT5668_A_DAC1_MUX:
case RT5668_DIG_INF2_DATA:
case RT5668_REC_MIXER:
case RT5668_CAL_REC:
case RT5668_ALC_BACK_GAIN:
case RT5668_PWR_DIG_1:
case RT5668_PWR_DIG_2:
case RT5668_PWR_ANLG_1:
case RT5668_PWR_ANLG_2:
case RT5668_PWR_ANLG_3:
case RT5668_PWR_MIXER:
case RT5668_PWR_VOL:
case RT5668_CLK_DET:
case RT5668_RESET_LPF_CTRL:
case RT5668_RESET_HPF_CTRL:
case RT5668_DMIC_CTRL_1:
case RT5668_I2S1_SDP:
case RT5668_I2S2_SDP:
case RT5668_ADDA_CLK_1:
case RT5668_ADDA_CLK_2:
case RT5668_I2S1_F_DIV_CTRL_1:
case RT5668_I2S1_F_DIV_CTRL_2:
case RT5668_TDM_CTRL:
case RT5668_TDM_ADDA_CTRL_1:
case RT5668_TDM_ADDA_CTRL_2:
case RT5668_DATA_SEL_CTRL_1:
case RT5668_TDM_TCON_CTRL:
case RT5668_GLB_CLK:
case RT5668_PLL_CTRL_1:
case RT5668_PLL_CTRL_2:
case RT5668_PLL_TRACK_1:
case RT5668_PLL_TRACK_2:
case RT5668_PLL_TRACK_3:
case RT5668_PLL_TRACK_4:
case RT5668_PLL_TRACK_5:
case RT5668_PLL_TRACK_6:
case RT5668_PLL_TRACK_11:
case RT5668_SDW_REF_CLK:
case RT5668_DEPOP_1:
case RT5668_DEPOP_2:
case RT5668_HP_CHARGE_PUMP_1:
case RT5668_HP_CHARGE_PUMP_2:
case RT5668_MICBIAS_1:
case RT5668_MICBIAS_2:
case RT5668_PLL_TRACK_12:
case RT5668_PLL_TRACK_14:
case RT5668_PLL2_CTRL_1:
case RT5668_PLL2_CTRL_2:
case RT5668_PLL2_CTRL_3:
case RT5668_PLL2_CTRL_4:
case RT5668_RC_CLK_CTRL:
case RT5668_I2S_M_CLK_CTRL_1:
case RT5668_I2S2_F_DIV_CTRL_1:
case RT5668_I2S2_F_DIV_CTRL_2:
case RT5668_EQ_CTRL_1:
case RT5668_EQ_CTRL_2:
case RT5668_IRQ_CTRL_1:
case RT5668_IRQ_CTRL_2:
case RT5668_IRQ_CTRL_3:
case RT5668_IRQ_CTRL_4:
case RT5668_INT_ST_1:
case RT5668_GPIO_CTRL_1:
case RT5668_GPIO_CTRL_2:
case RT5668_GPIO_CTRL_3:
case RT5668_HP_AMP_DET_CTRL_1:
case RT5668_HP_AMP_DET_CTRL_2:
case RT5668_MID_HP_AMP_DET:
case RT5668_LOW_HP_AMP_DET:
case RT5668_DELAY_BUF_CTRL:
case RT5668_SV_ZCD_1:
case RT5668_SV_ZCD_2:
case RT5668_IL_CMD_1:
case RT5668_IL_CMD_2:
case RT5668_IL_CMD_3:
case RT5668_IL_CMD_4:
case RT5668_IL_CMD_5:
case RT5668_IL_CMD_6:
case RT5668_4BTN_IL_CMD_1:
case RT5668_4BTN_IL_CMD_2:
case RT5668_4BTN_IL_CMD_3:
case RT5668_4BTN_IL_CMD_4:
case RT5668_4BTN_IL_CMD_5:
case RT5668_4BTN_IL_CMD_6:
case RT5668_4BTN_IL_CMD_7:
case RT5668_ADC_STO1_HP_CTRL_1:
case RT5668_ADC_STO1_HP_CTRL_2:
case RT5668_AJD1_CTRL:
case RT5668_JD1_THD:
case RT5668_JD2_THD:
case RT5668_JD_CTRL_1:
case RT5668_DUMMY_1:
case RT5668_DUMMY_2:
case RT5668_DUMMY_3:
case RT5668_DAC_ADC_DIG_VOL1:
case RT5668_BIAS_CUR_CTRL_2:
case RT5668_BIAS_CUR_CTRL_3:
case RT5668_BIAS_CUR_CTRL_4:
case RT5668_BIAS_CUR_CTRL_5:
case RT5668_BIAS_CUR_CTRL_6:
case RT5668_BIAS_CUR_CTRL_7:
case RT5668_BIAS_CUR_CTRL_8:
case RT5668_BIAS_CUR_CTRL_9:
case RT5668_BIAS_CUR_CTRL_10:
case RT5668_VREF_REC_OP_FB_CAP_CTRL:
case RT5668_CHARGE_PUMP_1:
case RT5668_DIG_IN_CTRL_1:
case RT5668_PAD_DRIVING_CTRL:
case RT5668_SOFT_RAMP_DEPOP:
case RT5668_CHOP_DAC:
case RT5668_CHOP_ADC:
case RT5668_CALIB_ADC_CTRL:
case RT5668_VOL_TEST:
case RT5668_SPKVDD_DET_STA:
case RT5668_TEST_MODE_CTRL_1:
case RT5668_TEST_MODE_CTRL_2:
case RT5668_TEST_MODE_CTRL_3:
case RT5668_TEST_MODE_CTRL_4:
case RT5668_TEST_MODE_CTRL_5:
case RT5668_PLL1_INTERNAL:
case RT5668_PLL2_INTERNAL:
case RT5668_STO_NG2_CTRL_1:
case RT5668_STO_NG2_CTRL_2:
case RT5668_STO_NG2_CTRL_3:
case RT5668_STO_NG2_CTRL_4:
case RT5668_STO_NG2_CTRL_5:
case RT5668_STO_NG2_CTRL_6:
case RT5668_STO_NG2_CTRL_7:
case RT5668_STO_NG2_CTRL_8:
case RT5668_STO_NG2_CTRL_9:
case RT5668_STO_NG2_CTRL_10:
case RT5668_STO1_DAC_SIL_DET:
case RT5668_SIL_PSV_CTRL1:
case RT5668_SIL_PSV_CTRL2:
case RT5668_SIL_PSV_CTRL3:
case RT5668_SIL_PSV_CTRL4:
case RT5668_SIL_PSV_CTRL5:
case RT5668_HP_IMP_SENS_CTRL_01:
case RT5668_HP_IMP_SENS_CTRL_02:
case RT5668_HP_IMP_SENS_CTRL_03:
case RT5668_HP_IMP_SENS_CTRL_04:
case RT5668_HP_IMP_SENS_CTRL_05:
case RT5668_HP_IMP_SENS_CTRL_06:
case RT5668_HP_IMP_SENS_CTRL_07:
case RT5668_HP_IMP_SENS_CTRL_08:
case RT5668_HP_IMP_SENS_CTRL_09:
case RT5668_HP_IMP_SENS_CTRL_10:
case RT5668_HP_IMP_SENS_CTRL_11:
case RT5668_HP_IMP_SENS_CTRL_12:
case RT5668_HP_IMP_SENS_CTRL_13:
case RT5668_HP_IMP_SENS_CTRL_14:
case RT5668_HP_IMP_SENS_CTRL_15:
case RT5668_HP_IMP_SENS_CTRL_16:
case RT5668_HP_IMP_SENS_CTRL_17:
case RT5668_HP_IMP_SENS_CTRL_18:
case RT5668_HP_IMP_SENS_CTRL_19:
case RT5668_HP_IMP_SENS_CTRL_20:
case RT5668_HP_IMP_SENS_CTRL_21:
case RT5668_HP_IMP_SENS_CTRL_22:
case RT5668_HP_IMP_SENS_CTRL_23:
case RT5668_HP_IMP_SENS_CTRL_24:
case RT5668_HP_IMP_SENS_CTRL_25:
case RT5668_HP_IMP_SENS_CTRL_26:
case RT5668_HP_IMP_SENS_CTRL_27:
case RT5668_HP_IMP_SENS_CTRL_28:
case RT5668_HP_IMP_SENS_CTRL_29:
case RT5668_HP_IMP_SENS_CTRL_30:
case RT5668_HP_IMP_SENS_CTRL_31:
case RT5668_HP_IMP_SENS_CTRL_32:
case RT5668_HP_IMP_SENS_CTRL_33:
case RT5668_HP_IMP_SENS_CTRL_34:
case RT5668_HP_IMP_SENS_CTRL_35:
case RT5668_HP_IMP_SENS_CTRL_36:
case RT5668_HP_IMP_SENS_CTRL_37:
case RT5668_HP_IMP_SENS_CTRL_38:
case RT5668_HP_IMP_SENS_CTRL_39:
case RT5668_HP_IMP_SENS_CTRL_40:
case RT5668_HP_IMP_SENS_CTRL_41:
case RT5668_HP_IMP_SENS_CTRL_42:
case RT5668_HP_IMP_SENS_CTRL_43:
case RT5668_HP_LOGIC_CTRL_1:
case RT5668_HP_LOGIC_CTRL_2:
case RT5668_HP_LOGIC_CTRL_3:
case RT5668_HP_CALIB_CTRL_1:
case RT5668_HP_CALIB_CTRL_2:
case RT5668_HP_CALIB_CTRL_3:
case RT5668_HP_CALIB_CTRL_4:
case RT5668_HP_CALIB_CTRL_5:
case RT5668_HP_CALIB_CTRL_6:
case RT5668_HP_CALIB_CTRL_7:
case RT5668_HP_CALIB_CTRL_9:
case RT5668_HP_CALIB_CTRL_10:
case RT5668_HP_CALIB_CTRL_11:
case RT5668_HP_CALIB_STA_1:
case RT5668_HP_CALIB_STA_2:
case RT5668_HP_CALIB_STA_3:
case RT5668_HP_CALIB_STA_4:
case RT5668_HP_CALIB_STA_5:
case RT5668_HP_CALIB_STA_6:
case RT5668_HP_CALIB_STA_7:
case RT5668_HP_CALIB_STA_8:
case RT5668_HP_CALIB_STA_9:
case RT5668_HP_CALIB_STA_10:
case RT5668_HP_CALIB_STA_11:
case RT5668_SAR_IL_CMD_1:
case RT5668_SAR_IL_CMD_2:
case RT5668_SAR_IL_CMD_3:
case RT5668_SAR_IL_CMD_4:
case RT5668_SAR_IL_CMD_5:
case RT5668_SAR_IL_CMD_6:
case RT5668_SAR_IL_CMD_7:
case RT5668_SAR_IL_CMD_8:
case RT5668_SAR_IL_CMD_9:
case RT5668_SAR_IL_CMD_10:
case RT5668_SAR_IL_CMD_11:
case RT5668_SAR_IL_CMD_12:
case RT5668_SAR_IL_CMD_13:
case RT5668_EFUSE_CTRL_1:
case RT5668_EFUSE_CTRL_2:
case RT5668_EFUSE_CTRL_3:
case RT5668_EFUSE_CTRL_4:
case RT5668_EFUSE_CTRL_5:
case RT5668_EFUSE_CTRL_6:
case RT5668_EFUSE_CTRL_7:
case RT5668_EFUSE_CTRL_8:
case RT5668_EFUSE_CTRL_9:
case RT5668_EFUSE_CTRL_10:
case RT5668_EFUSE_CTRL_11:
case RT5668_JD_TOP_VC_VTRL:
case RT5668_DRC1_CTRL_0:
case RT5668_DRC1_CTRL_1:
case RT5668_DRC1_CTRL_2:
case RT5668_DRC1_CTRL_3:
case RT5668_DRC1_CTRL_4:
case RT5668_DRC1_CTRL_5:
case RT5668_DRC1_CTRL_6:
case RT5668_DRC1_HARD_LMT_CTRL_1:
case RT5668_DRC1_HARD_LMT_CTRL_2:
case RT5668_DRC1_PRIV_1:
case RT5668_DRC1_PRIV_2:
case RT5668_DRC1_PRIV_3:
case RT5668_DRC1_PRIV_4:
case RT5668_DRC1_PRIV_5:
case RT5668_DRC1_PRIV_6:
case RT5668_DRC1_PRIV_7:
case RT5668_DRC1_PRIV_8:
case RT5668_EQ_AUTO_RCV_CTRL1:
case RT5668_EQ_AUTO_RCV_CTRL2:
case RT5668_EQ_AUTO_RCV_CTRL3:
case RT5668_EQ_AUTO_RCV_CTRL4:
case RT5668_EQ_AUTO_RCV_CTRL5:
case RT5668_EQ_AUTO_RCV_CTRL6:
case RT5668_EQ_AUTO_RCV_CTRL7:
case RT5668_EQ_AUTO_RCV_CTRL8:
case RT5668_EQ_AUTO_RCV_CTRL9:
case RT5668_EQ_AUTO_RCV_CTRL10:
case RT5668_EQ_AUTO_RCV_CTRL11:
case RT5668_EQ_AUTO_RCV_CTRL12:
case RT5668_EQ_AUTO_RCV_CTRL13:
case RT5668_ADC_L_EQ_LPF1_A1:
case RT5668_R_EQ_LPF1_A1:
case RT5668_L_EQ_LPF1_H0:
case RT5668_R_EQ_LPF1_H0:
case RT5668_L_EQ_BPF1_A1:
case RT5668_R_EQ_BPF1_A1:
case RT5668_L_EQ_BPF1_A2:
case RT5668_R_EQ_BPF1_A2:
case RT5668_L_EQ_BPF1_H0:
case RT5668_R_EQ_BPF1_H0:
case RT5668_L_EQ_BPF2_A1:
case RT5668_R_EQ_BPF2_A1:
case RT5668_L_EQ_BPF2_A2:
case RT5668_R_EQ_BPF2_A2:
case RT5668_L_EQ_BPF2_H0:
case RT5668_R_EQ_BPF2_H0:
case RT5668_L_EQ_BPF3_A1:
case RT5668_R_EQ_BPF3_A1:
case RT5668_L_EQ_BPF3_A2:
case RT5668_R_EQ_BPF3_A2:
case RT5668_L_EQ_BPF3_H0:
case RT5668_R_EQ_BPF3_H0:
case RT5668_L_EQ_BPF4_A1:
case RT5668_R_EQ_BPF4_A1:
case RT5668_L_EQ_BPF4_A2:
case RT5668_R_EQ_BPF4_A2:
case RT5668_L_EQ_BPF4_H0:
case RT5668_R_EQ_BPF4_H0:
case RT5668_L_EQ_HPF1_A1:
case RT5668_R_EQ_HPF1_A1:
case RT5668_L_EQ_HPF1_H0:
case RT5668_R_EQ_HPF1_H0:
case RT5668_L_EQ_PRE_VOL:
case RT5668_R_EQ_PRE_VOL:
case RT5668_L_EQ_POST_VOL:
case RT5668_R_EQ_POST_VOL:
case RT5668_I2C_MODE:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
/* Interface data select */
static const char * const rt5668_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum,
RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select);
static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum,
RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select);
static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum,
RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select);
static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum,
RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select);
static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum,
RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select);
static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux =
SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum);
static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux =
SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum);
static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux =
SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum);
static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux =
SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum);
static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux =
SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum);
static void rt5668_reset(struct regmap *regmap)
{
regmap_write(regmap, RT5668_RESET, 0);
regmap_write(regmap, RT5668_I2C_MODE, 1);
}
/**
* rt5668_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the component driver will turn on
* ASRC for these filters if ASRC is selected as their clock source.
*/
int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
switch (clk_src) {
case RT5668_CLK_SEL_SYS:
case RT5668_CLK_SEL_I2S1_ASRC:
case RT5668_CLK_SEL_I2S2_ASRC:
break;
default:
return -EINVAL;
}
if (filter_mask & RT5668_DA_STEREO1_FILTER) {
snd_soc_component_update_bits(component, RT5668_PLL_TRACK_2,
RT5668_FILTER_CLK_SEL_MASK,
clk_src << RT5668_FILTER_CLK_SEL_SFT);
}
if (filter_mask & RT5668_AD_STEREO1_FILTER) {
snd_soc_component_update_bits(component, RT5668_PLL_TRACK_3,
RT5668_FILTER_CLK_SEL_MASK,
clk_src << RT5668_FILTER_CLK_SEL_SFT);
}
return 0;
}
EXPORT_SYMBOL_GPL(rt5668_sel_asrc_clk_src);
static int rt5668_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5668_4BTN_IL_CMD_1);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val);
pr_debug("%s btn_type=%x\n", __func__, btn_type);
return btn_type;
}
static void rt5668_enable_push_button_irq(struct snd_soc_component *component,
bool enable)
{
if (enable) {
snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN);
snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN);
snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040);
snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK,
RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR);
snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN);
} else {
snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS);
snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS);
snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS);
snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST);
snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE);
}
}
/**
* rt5668_headset_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5668_headset_detect(struct snd_soc_component *component,
int jack_insert)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
unsigned int val, count;
if (jack_insert) {
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH);
count = 0;
val = snd_soc_component_read(component, RT5668_CBJ_CTRL_2)
& RT5668_JACK_TYPE_MASK;
while (val == 0 && count < 50) {
usleep_range(10000, 15000);
val = snd_soc_component_read(component,
RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK;
count++;
}
switch (val) {
case 0x1:
case 0x2:
rt5668->jack_type = SND_JACK_HEADSET;
rt5668_enable_push_button_irq(component, true);
break;
default:
rt5668->jack_type = SND_JACK_HEADPHONE;
}
} else {
rt5668_enable_push_button_irq(component, false);
snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW);
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
rt5668->jack_type = 0;
}
dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type);
return rt5668->jack_type;
}
static irqreturn_t rt5668_irq(int irq, void *data)
{
struct rt5668_priv *rt5668 = data;
mod_delayed_work(system_power_efficient_wq,
&rt5668->jack_detect_work, msecs_to_jiffies(250));
return IRQ_HANDLED;
}
static void rt5668_jd_check_handler(struct work_struct *work)
{
struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv,
jd_check_work.work);
if (snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL)
& RT5668_JDH_RS_MASK) {
/* jack out */
rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
} else {
schedule_delayed_work(&rt5668->jd_check_work, 500);
}
}
static int rt5668_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
switch (rt5668->pdata.jd_src) {
case RT5668_JD1:
snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2,
RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL);
snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002);
snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3,
RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN);
snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN);
regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ);
regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
RT5668_POW_IRQ | RT5668_POW_JDH |
RT5668_POW_ANA, RT5668_POW_IRQ |
RT5668_POW_JDH | RT5668_POW_ANA);
regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2,
RT5668_PWR_JDH | RT5668_PWR_JDL,
RT5668_PWR_JDH | RT5668_PWR_JDL);
regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK,
RT5668_JD1_EN | RT5668_JD1_POL_NOR);
mod_delayed_work(system_power_efficient_wq,
&rt5668->jack_detect_work, msecs_to_jiffies(250));
break;
case RT5668_JD_NULL:
regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
RT5668_JD1_EN_MASK, RT5668_JD1_DIS);
regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
RT5668_POW_JDH | RT5668_POW_JDL, 0);
break;
default:
dev_warn(component->dev, "Wrong JD source\n");
break;
}
rt5668->hs_jack = hs_jack;
return 0;
}
static void rt5668_jack_detect_handler(struct work_struct *work)
{
struct rt5668_priv *rt5668 =
container_of(work, struct rt5668_priv, jack_detect_work.work);
int val, btn_type;
if (!rt5668->component ||
!snd_soc_card_is_instantiated(rt5668->component->card)) {
/* card not yet ready, try later */
mod_delayed_work(system_power_efficient_wq,
&rt5668->jack_detect_work, msecs_to_jiffies(15));
return;
}
mutex_lock(&rt5668->calibrate_mutex);
val = snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL)
& RT5668_JDH_RS_MASK;
if (!val) {
/* jack in */
if (rt5668->jack_type == 0) {
/* jack was out, report jack type */
rt5668->jack_type =
rt5668_headset_detect(rt5668->component, 1);
} else {
/* jack is already in, report button event */
rt5668->jack_type = SND_JACK_HEADSET;
btn_type = rt5668_button_detect(rt5668->component);
/**
* rt5668 can report three kinds of button behavior,
* one click, double click and hold. However,
* currently we will report button pressed/released
* event. So all the three button behaviors are
* treated as button pressed.
*/
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
rt5668->jack_type |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
rt5668->jack_type |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
rt5668->jack_type |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
rt5668->jack_type |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
btn_type = 0;
dev_err(rt5668->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
}
} else {
/* jack out */
rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
}
snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3))
schedule_delayed_work(&rt5668->jd_check_work, 0);
else
cancel_delayed_work_sync(&rt5668->jd_check_work);
mutex_unlock(&rt5668->calibrate_mutex);
}
static const struct snd_kcontrol_new rt5668_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN,
RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL,
RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv),
/* IN Boost Volume */
SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL,
RT5668_BST_CBJ_SFT, 8, 0, bst_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL,
RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL,
RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST,
RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
};
static int rt5668_div_sel(struct rt5668_priv *rt5668,
int target, const int div[], int size)
{
int i;
if (rt5668->sysclk < target) {
pr_err("sysclk rate %d is too low\n",
rt5668->sysclk);
return 0;
}
for (i = 0; i < size - 1; i++) {
pr_info("div[%d]=%d\n", i, div[i]);
if (target * div[i] == rt5668->sysclk)
return i;
if (target * div[i + 1] > rt5668->sysclk) {
pr_err("can't find div for sysclk %d\n",
rt5668->sysclk);
return i;
}
}
if (target * div[i] < rt5668->sysclk)
pr_err("sysclk rate %d is too high\n",
rt5668->sysclk);
return size - 1;
}
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
int idx;
static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div));
snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1,
RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT);
return 0;
}
static int set_filter_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
int ref, val, reg, idx;
static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
val = snd_soc_component_read(component, RT5668_GPIO_CTRL_1) &
RT5668_GP4_PIN_MASK;
if (w->shift == RT5668_PWR_ADC_S1F_BIT &&
val == RT5668_GP4_PIN_ADCDAT2)
ref = 256 * rt5668->lrck[RT5668_AIF2];
else
ref = 256 * rt5668->lrck[RT5668_AIF1];
idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div));
if (w->shift == RT5668_PWR_ADC_S1F_BIT)
reg = RT5668_PLL_TRACK_3;
else
reg = RT5668_PLL_TRACK_2;
snd_soc_component_update_bits(component, reg,
RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT);
return 0;
}
static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
val = snd_soc_component_read(component, RT5668_GLB_CLK);
val &= RT5668_SCLK_SRC_MASK;
if (val == RT5668_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, shift, val;
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case RT5668_ADC_STO1_ASRC_SFT:
reg = RT5668_PLL_TRACK_3;
shift = RT5668_FILTER_CLK_SEL_SFT;
break;
case RT5668_DAC_STO1_ASRC_SFT:
reg = RT5668_PLL_TRACK_2;
shift = RT5668_FILTER_CLK_SEL_SFT;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
switch (val) {
case RT5668_CLK_SEL_I2S1_ASRC:
case RT5668_CLK_SEL_I2S2_ASRC:
return 1;
default:
return 0;
}
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
RT5668_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
RT5668_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
RT5668_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
RT5668_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
RT5668_M_DAC_L1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
RT5668_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
RT5668_M_DAC_L1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
RT5668_M_DAC_R1_STO_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = {
SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER,
RT5668_M_CBJ_RM1_L_SFT, 1, 1),
};
/* STO1 ADC1 Source */
/* MX-26 [13] [5] */
static const char * const rt5668_sto1_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER,
RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src);
static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER,
RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src);
static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum);
/* STO1 ADC Source */
/* MX-26 [11:10] [3:2] */
static const char * const rt5668_sto1_adc_src[] = {
"ADC1 L", "ADC1 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER,
RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src);
static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(
rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER,
RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src);
static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum);
/* STO1 ADC2 Source */
/* MX-26 [12] [4] */
static const char * const rt5668_sto1_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER,
RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src);
static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux =
SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER,
RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src);
static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux =
SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum);
/* MX-79 [6:4] I2S1 ADC data location */
static const unsigned int rt5668_if1_adc_slot_values[] = {
0,
2,
4,
6,
};
static const char * const rt5668_if1_adc_slot_src[] = {
"Slot 0", "Slot 2", "Slot 4", "Slot 6"
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum,
RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK,
rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values);
static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux =
SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum);
/* Analog DAC L1 Source, Analog DAC R1 Source*/
/* MX-2B [4], MX-2B [0]*/
static const char * const rt5668_alg_dac1_src[] = {
"Stereo1 DAC Mixer", "DAC1"
};
static SOC_ENUM_SINGLE_DECL(
rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX,
RT5668_A_DACL1_SFT, rt5668_alg_dac1_src);
static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux =
SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX,
RT5668_A_DACR1_SFT, rt5668_alg_dac1_src);
static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux =
SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum);
/* Out Switch */
static const struct snd_kcontrol_new hpol_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
RT5668_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpor_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
RT5668_R_MUTE_SFT, 1, 1);
static int rt5668_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write(component,
RT5668_HP_LOGIC_CTRL_2, 0x0012);
snd_soc_component_write(component,
RT5668_HP_CTRL_2, 0x6000);
snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1,
RT5668_NG2_EN_MASK, RT5668_NG2_EN);
snd_soc_component_update_bits(component,
RT5668_DEPOP_1, 0x60, 0x60);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
RT5668_DEPOP_1, 0x60, 0x0);
snd_soc_component_write(component,
RT5668_HP_CTRL_2, 0x0000);
break;
default:
return 0;
}
return 0;
}
static int set_dmic_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/*Add delay to avoid pop noise*/
msleep(150);
break;
default:
return 0;
}
return 0;
}
static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (w->shift) {
case RT5668_PWR_VREF1_BIT:
snd_soc_component_update_bits(component,
RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0);
break;
case RT5668_PWR_VREF2_BIT:
snd_soc_component_update_bits(component,
RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0);
break;
default:
break;
}
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(15000, 20000);
switch (w->shift) {
case RT5668_PWR_VREF1_BIT:
snd_soc_component_update_bits(component,
RT5668_PWR_ANLG_1, RT5668_PWR_FV1,
RT5668_PWR_FV1);
break;
case RT5668_PWR_VREF2_BIT:
snd_soc_component_update_bits(component,
RT5668_PWR_ANLG_1, RT5668_PWR_FV2,
RT5668_PWR_FV2);
break;
default:
break;
}
break;
default:
return 0;
}
return 0;
}
static const unsigned int rt5668_adcdat_pin_values[] = {
1,
3,
};
static const char * const rt5668_adcdat_pin_select[] = {
"ADCDAT1",
"ADCDAT2",
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum,
RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK,
rt5668_adcdat_pin_select, rt5668_adcdat_pin_values);
static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl =
SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum);
static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0,
rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0,
rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1,
RT5668_AD_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1,
RT5668_DA_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1,
RT5668_DMIC_ASRC_SFT, 0, NULL, 0),
/* Input Side */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT,
0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1,
RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3,
RT5668_PWR_CBJ_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix,
ARRAY_SIZE(rt5668_rec1_l_mix)),
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2,
RT5668_PWR_RM1_L_BIT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1,
RT5668_PWR_ADC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1,
RT5668_PWR_ADC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC,
RT5668_CKGEN_ADC1_SFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adc1l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adc1r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adc2l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adc2r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adcl_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adcr_mux),
SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5668_if1_adc_slot_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2,
RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL,
RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix,
ARRAY_SIZE(rt5668_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL,
RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix,
ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5668_if1_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5668_if1_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5668_if1_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5668_if1_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5668_if2_adc_swap_mux),
SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
&rt5668_adcdat_pin_ctrl),
/* Audio Interface */
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1),
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)),
/* DAC channel Mux */
SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
&rt5668_alg_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
&rt5668_alg_dac_r1_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2,
RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1,
RT5668_PWR_DAC_L1_BIT, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1,
RT5668_PWR_DAC_R1_BIT, 0),
SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC,
RT5668_CKGEN_DAC1_SFT, 0, NULL, 0),
/* HPO */
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1,
RT5668_PWR_HA_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1,
RT5668_PWR_HA_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1,
RT5668_PUMP_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1,
RT5668_CAPLESS_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
&hpol_switch),
SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
&hpor_switch),
/* CLK DET */
SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET,
RT5668_SYS_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET,
RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET,
RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET,
RT5668_POW_CLK_DET_SFT, 0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route rt5668_dapm_routes[] = {
/*PLL*/
{"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
{"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
/*ASRC*/
{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
{"ADC STO1 ASRC", NULL, "AD ASRC"},
{"DAC STO1 ASRC", NULL, "DA ASRC"},
/*Vref*/
{"MICBIAS1", NULL, "Vref1"},
{"MICBIAS1", NULL, "Vref2"},
{"MICBIAS2", NULL, "Vref1"},
{"MICBIAS2", NULL, "Vref2"},
{"CLKDET SYS", NULL, "CLKDET"},
{"IN1P", NULL, "LDO2"},
{"BST1 CBJ", NULL, "IN1P"},
{"BST1 CBJ", NULL, "CBJ Power"},
{"CBJ Power", NULL, "Vref2"},
{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
{"RECMIX1L", NULL, "RECMIX1L Power"},
{"ADC1 L", NULL, "RECMIX1L"},
{"ADC1 L", NULL, "ADC1 L Power"},
{"ADC1 L", NULL, "ADC1 clock"},
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC1 Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC1 Power"},
{"DMIC CLK", NULL, "DMIC ASRC"},
{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
{"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
{"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
{"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
{"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
{"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
{"IF1_ADC Mux", NULL, "I2S1"},
{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
{"AIF1TX", NULL, "ADCDAT Mux"},
{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
{"AIF2TX", NULL, "ADCDAT Mux"},
{"IF1 DAC1 L", NULL, "AIF1RX"},
{"IF1 DAC1 L", NULL, "I2S1"},
{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
{"IF1 DAC1 R", NULL, "AIF1RX"},
{"IF1 DAC1 R", NULL, "I2S1"},
{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
{"DAC L1 Source", "DAC1", "DAC1 MIXL"},
{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
{"DAC R1 Source", "DAC1", "DAC1 MIXR"},
{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
{"DAC L1", NULL, "DAC L1 Source"},
{"DAC R1", NULL, "DAC R1 Source"},
{"DAC L1", NULL, "DAC 1 Clock"},
{"DAC R1", NULL, "DAC 1 Clock"},
{"HP Amp", NULL, "DAC L1"},
{"HP Amp", NULL, "DAC R1"},
{"HP Amp", NULL, "HP Amp L"},
{"HP Amp", NULL, "HP Amp R"},
{"HP Amp", NULL, "Capless"},
{"HP Amp", NULL, "Charge Pump"},
{"HP Amp", NULL, "CLKDET SYS"},
{"HP Amp", NULL, "CBJ Power"},
{"HP Amp", NULL, "Vref2"},
{"HPOL Playback", "Switch", "HP Amp"},
{"HPOR Playback", "Switch", "HP Amp"},
{"HPOL", NULL, "HPOL Playback"},
{"HPOR", NULL, "HPOR Playback"},
};
static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
switch (slots) {
case 4:
val |= RT5668_TDM_TX_CH_4;
val |= RT5668_TDM_RX_CH_4;
break;
case 6:
val |= RT5668_TDM_TX_CH_6;
val |= RT5668_TDM_RX_CH_6;
break;
case 8:
val |= RT5668_TDM_TX_CH_8;
val |= RT5668_TDM_RX_CH_8;
break;
case 2:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5668_TDM_CTRL,
RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val);
switch (slot_width) {
case 16:
val = RT5668_TDM_CL_16;
break;
case 20:
val = RT5668_TDM_CL_20;
break;
case 24:
val = RT5668_TDM_CL_24;
break;
case 32:
val = RT5668_TDM_CL_32;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
RT5668_TDM_CL_MASK, val);
return 0;
}
static int rt5668_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
unsigned int len_1 = 0, len_2 = 0;
int pre_div, frame_size;
rt5668->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]);
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt5668->lrck[dai->id], pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
len_1 |= RT5668_I2S1_DL_20;
len_2 |= RT5668_I2S2_DL_20;
break;
case 24:
len_1 |= RT5668_I2S1_DL_24;
len_2 |= RT5668_I2S2_DL_24;
break;
case 32:
len_1 |= RT5668_I2S1_DL_32;
len_2 |= RT5668_I2S2_DL_24;
break;
case 8:
len_1 |= RT5668_I2S2_DL_8;
len_2 |= RT5668_I2S2_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5668_AIF1:
snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
RT5668_I2S1_DL_MASK, len_1);
if (rt5668->master[RT5668_AIF1]) {
snd_soc_component_update_bits(component,
RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK,
pre_div << RT5668_I2S_M_DIV_SFT);
}
if (params_channels(params) == 1) /* mono mode */
snd_soc_component_update_bits(component,
RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
RT5668_I2S1_MONO_EN);
else
snd_soc_component_update_bits(component,
RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
RT5668_I2S1_MONO_DIS);
break;
case RT5668_AIF2:
snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
RT5668_I2S2_DL_MASK, len_2);
if (rt5668->master[RT5668_AIF2]) {
snd_soc_component_update_bits(component,
RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK,
pre_div << RT5668_I2S2_M_PD_SFT);
}
if (params_channels(params) == 1) /* mono mode */
snd_soc_component_update_bits(component,
RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
RT5668_I2S2_MONO_EN);
else
snd_soc_component_update_bits(component,
RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
RT5668_I2S2_MONO_DIS);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, tdm_ctrl = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5668->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
rt5668->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5668_I2S_BP_INV;
tdm_ctrl |= RT5668_TDM_S_BP_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
if (dai->id == RT5668_AIF1)
tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV;
else
return -EINVAL;
break;
case SND_SOC_DAIFMT_IB_IF:
if (dai->id == RT5668_AIF1)
tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV |
RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV;
else
return -EINVAL;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5668_I2S_DF_LEFT;
tdm_ctrl |= RT5668_TDM_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5668_I2S_DF_PCM_A;
tdm_ctrl |= RT5668_TDM_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5668_I2S_DF_PCM_B;
tdm_ctrl |= RT5668_TDM_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5668_AIF1:
snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
RT5668_I2S_DF_MASK, reg_val);
snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK |
RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK |
RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK,
tdm_ctrl | rt5668->master[dai->id]);
break;
case RT5668_AIF2:
if (rt5668->master[dai->id] == 0)
reg_val |= RT5668_I2S2_MS_S;
snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK |
RT5668_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5668_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, src = 0;
if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src)
return 0;
switch (clk_id) {
case RT5668_SCLK_S_MCLK:
reg_val |= RT5668_SCLK_SRC_MCLK;
src = RT5668_CLK_SRC_MCLK;
break;
case RT5668_SCLK_S_PLL1:
reg_val |= RT5668_SCLK_SRC_PLL1;
src = RT5668_CLK_SRC_PLL1;
break;
case RT5668_SCLK_S_PLL2:
reg_val |= RT5668_SCLK_SRC_PLL2;
src = RT5668_CLK_SRC_PLL2;
break;
case RT5668_SCLK_S_RCCLK:
reg_val |= RT5668_SCLK_SRC_RCCLK;
src = RT5668_CLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5668_GLB_CLK,
RT5668_SCLK_SRC_MASK, reg_val);
if (rt5668->master[RT5668_AIF2]) {
snd_soc_component_update_bits(component,
RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK,
src << RT5668_I2S2_SRC_SFT);
}
rt5668->sysclk = freq;
rt5668->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt5668_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5668->pll_src && freq_in == rt5668->pll_in &&
freq_out == rt5668->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5668->pll_in = 0;
rt5668->pll_out = 0;
snd_soc_component_update_bits(component, RT5668_GLB_CLK,
RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5668_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5668_GLB_CLK,
RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK);
break;
case RT5668_PLL1_S_BCLK1:
snd_soc_component_update_bits(component, RT5668_GLB_CLK,
RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1);
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5668_PLL_CTRL_1,
pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5668_PLL_CTRL_2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT) |
(pll_code.m_bp << RT5668_PLL_M_BP_SFT));
rt5668->pll_in = freq_in;
rt5668->pll_out = freq_out;
rt5668->pll_src = source;
return 0;
}
static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
rt5668->bclk[dai->id] = ratio;
switch (ratio) {
case 64:
snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
RT5668_I2S2_BCLK_MS2_MASK,
RT5668_I2S2_BCLK_MS2_64);
break;
case 32:
snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
RT5668_I2S2_BCLK_MS2_MASK,
RT5668_I2S2_BCLK_MS2_32);
break;
default:
dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
return -EINVAL;
}
return 0;
}
static int rt5668_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
RT5668_PWR_MB | RT5668_PWR_BG,
RT5668_PWR_MB | RT5668_PWR_BG);
regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO,
RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO);
break;
case SND_SOC_BIAS_STANDBY:
regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
RT5668_PWR_MB, RT5668_PWR_MB);
regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0);
regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
RT5668_PWR_MB | RT5668_PWR_BG, 0);
break;
default:
break;
}
return 0;
}
static int rt5668_probe(struct snd_soc_component *component)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
rt5668->component = component;
return 0;
}
static void rt5668_remove(struct snd_soc_component *component)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
rt5668_reset(rt5668->regmap);
}
#ifdef CONFIG_PM
static int rt5668_suspend(struct snd_soc_component *component)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5668->regmap, true);
regcache_mark_dirty(rt5668->regmap);
return 0;
}
static int rt5668_resume(struct snd_soc_component *component)
{
struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5668->regmap, false);
regcache_sync(rt5668->regmap);
return 0;
}
#else
#define rt5668_suspend NULL
#define rt5668_resume NULL
#endif
#define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = {
.hw_params = rt5668_hw_params,
.set_fmt = rt5668_set_dai_fmt,
.set_tdm_slot = rt5668_set_tdm_slot,
};
static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = {
.hw_params = rt5668_hw_params,
.set_fmt = rt5668_set_dai_fmt,
.set_bclk_ratio = rt5668_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt5668_dai[] = {
{
.name = "rt5668-aif1",
.id = RT5668_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5668_STEREO_RATES,
.formats = RT5668_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5668_STEREO_RATES,
.formats = RT5668_FORMATS,
},
.ops = &rt5668_aif1_dai_ops,
},
{
.name = "rt5668-aif2",
.id = RT5668_AIF2,
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5668_STEREO_RATES,
.formats = RT5668_FORMATS,
},
.ops = &rt5668_aif2_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5668 = {
.probe = rt5668_probe,
.remove = rt5668_remove,
.suspend = rt5668_suspend,
.resume = rt5668_resume,
.set_bias_level = rt5668_set_bias_level,
.controls = rt5668_snd_controls,
.num_controls = ARRAY_SIZE(rt5668_snd_controls),
.dapm_widgets = rt5668_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets),
.dapm_routes = rt5668_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes),
.set_sysclk = rt5668_set_component_sysclk,
.set_pll = rt5668_set_component_pll,
.set_jack = rt5668_set_jack_detect,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5668_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = RT5668_I2C_MODE,
.volatile_reg = rt5668_volatile_register,
.readable_reg = rt5668_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5668_reg,
.num_reg_defaults = ARRAY_SIZE(rt5668_reg),
.use_single_read = true,
.use_single_write = true,
};
static const struct i2c_device_id rt5668_i2c_id[] = {
{"rt5668b", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id);
static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev)
{
of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
&rt5668->pdata.dmic1_data_pin);
of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin",
&rt5668->pdata.dmic1_clk_pin);
of_property_read_u32(dev->of_node, "realtek,jd-src",
&rt5668->pdata.jd_src);
return 0;
}
static void rt5668_calibrate(struct rt5668_priv *rt5668)
{
int value, count;
mutex_lock(&rt5668->calibrate_mutex);
rt5668_reset(rt5668->regmap);
regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf);
usleep_range(15000, 20000);
regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf);
regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001);
regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080);
regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040);
regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069);
regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000);
regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000);
regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26);
regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05);
regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c);
regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d);
regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f);
regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01);
regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321);
regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004);
regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00);
regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1);
regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311);
regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000);
regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320);
regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00);
for (count = 0; count < 60; count++) {
regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value);
if (!(value & 0x8000))
break;
usleep_range(10000, 10005);
}
if (count >= 60)
pr_err("HP Calibration Failure\n");
/* restore settings */
regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4);
regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000);
mutex_unlock(&rt5668->calibrate_mutex);
}
static int rt5668_i2c_probe(struct i2c_client *i2c)
{
struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5668_priv *rt5668;
int i, ret;
unsigned int val;
rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv),
GFP_KERNEL);
if (rt5668 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5668);
if (pdata)
rt5668->pdata = *pdata;
else
rt5668_parse_dt(rt5668, &i2c->dev);
rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
if (IS_ERR(rt5668->regmap)) {
ret = PTR_ERR(rt5668->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++)
rt5668->supplies[i].supply = rt5668_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies),
rt5668->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies),
rt5668->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
rt5668->ldo1_en = devm_gpiod_get_optional(&i2c->dev,
"realtek,ldo1-en",
GPIOD_OUT_HIGH);
if (IS_ERR(rt5668->ldo1_en)) {
dev_err(&i2c->dev, "Fail gpio request ldo1_en\n");
return PTR_ERR(rt5668->ldo1_en);
}
/* Sleep for 300 ms miniumum */
usleep_range(300000, 350000);
regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1);
usleep_range(10000, 15000);
regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val);
if (val != DEVICE_ID) {
pr_err("Device with ID register %x is not rt5668\n", val);
return -ENODEV;
}
rt5668_reset(rt5668->regmap);
rt5668_calibrate(rt5668);
regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000);
/* DMIC pin*/
if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) {
switch (rt5668->pdata.dmic1_data_pin) {
case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */
regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2);
regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA);
break;
case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5);
regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA);
break;
default:
dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n");
break;
}
switch (rt5668->pdata.dmic1_clk_pin) {
case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */
regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK);
break;
case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */
regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK);
break;
default:
dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n");
break;
}
}
regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK,
RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X);
regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK,
RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1);
regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
INIT_DELAYED_WORK(&rt5668->jack_detect_work,
rt5668_jack_detect_handler);
INIT_DELAYED_WORK(&rt5668->jd_check_work,
rt5668_jd_check_handler);
mutex_init(&rt5668->calibrate_mutex);
if (i2c->irq) {
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT, "rt5668", rt5668);
if (ret)
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
}
return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668,
rt5668_dai, ARRAY_SIZE(rt5668_dai));
}
static void rt5668_i2c_shutdown(struct i2c_client *client)
{
struct rt5668_priv *rt5668 = i2c_get_clientdata(client);
rt5668_reset(rt5668->regmap);
}
#ifdef CONFIG_OF
static const struct of_device_id rt5668_of_match[] = {
{.compatible = "realtek,rt5668b"},
{},
};
MODULE_DEVICE_TABLE(of, rt5668_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5668_acpi_match[] = {
{"10EC5668", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match);
#endif
static struct i2c_driver rt5668_i2c_driver = {
.driver = {
.name = "rt5668b",
.of_match_table = of_match_ptr(rt5668_of_match),
.acpi_match_table = ACPI_PTR(rt5668_acpi_match),
},
.probe = rt5668_i2c_probe,
.shutdown = rt5668_i2c_shutdown,
.id_table = rt5668_i2c_id,
};
module_i2c_driver(rt5668_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5668B driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5668.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm9712.c -- ALSA Soc WM9712 codec support
*
* Copyright 2006-12 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <[email protected]>
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mfd/wm97xx.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/ac97/codec.h>
#include <sound/ac97/compat.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define WM9712_VENDOR_ID 0x574d4c12
#define WM9712_VENDOR_ID_MASK 0xffffffff
struct wm9712_priv {
struct snd_ac97 *ac97;
unsigned int hp_mixer[2];
struct mutex lock;
struct wm97xx_platform_data *mfd_pdata;
};
static const struct reg_default wm9712_reg_defaults[] = {
{ 0x02, 0x8000 },
{ 0x04, 0x8000 },
{ 0x06, 0x8000 },
{ 0x08, 0x0f0f },
{ 0x0a, 0xaaa0 },
{ 0x0c, 0xc008 },
{ 0x0e, 0x6808 },
{ 0x10, 0xe808 },
{ 0x12, 0xaaa0 },
{ 0x14, 0xad00 },
{ 0x16, 0x8000 },
{ 0x18, 0xe808 },
{ 0x1a, 0x3000 },
{ 0x1c, 0x8000 },
{ 0x20, 0x0000 },
{ 0x22, 0x0000 },
{ 0x26, 0x000f },
{ 0x28, 0x0605 },
{ 0x2a, 0x0410 },
{ 0x2c, 0xbb80 },
{ 0x2e, 0xbb80 },
{ 0x32, 0xbb80 },
{ 0x34, 0x2000 },
{ 0x4c, 0xf83e },
{ 0x4e, 0xffff },
{ 0x50, 0x0000 },
{ 0x52, 0x0000 },
{ 0x56, 0xf83e },
{ 0x58, 0x0008 },
{ 0x5c, 0x0000 },
{ 0x60, 0xb032 },
{ 0x62, 0x3e00 },
{ 0x64, 0x0000 },
{ 0x76, 0x0006 },
{ 0x78, 0x0001 },
{ 0x7a, 0x0000 },
};
static bool wm9712_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AC97_REC_GAIN:
return true;
default:
return regmap_ac97_default_volatile(dev, reg);
}
}
static const struct regmap_config wm9712_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x7e,
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm9712_volatile_reg,
.reg_defaults = wm9712_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm9712_reg_defaults),
};
#define HPL_MIXER 0x0
#define HPR_MIXER 0x1
static const char *wm9712_alc_select[] = {"None", "Left", "Right", "Stereo"};
static const char *wm9712_alc_mux[] = {"Stereo", "Left", "Right", "None"};
static const char *wm9712_out3_src[] = {"Left", "VREF", "Left + Right",
"Mono"};
static const char *wm9712_spk_src[] = {"Speaker Mix", "Headphone Mix"};
static const char *wm9712_rec_adc[] = {"Stereo", "Left", "Right", "Mute"};
static const char *wm9712_base[] = {"Linear Control", "Adaptive Boost"};
static const char *wm9712_rec_gain[] = {"+1.5dB Steps", "+0.75dB Steps"};
static const char *wm9712_mic[] = {"Mic 1", "Differential", "Mic 2",
"Stereo"};
static const char *wm9712_rec_sel[] = {"Mic", "NC", "NC", "Speaker Mixer",
"Line", "Headphone Mixer", "Phone Mixer", "Phone"};
static const char *wm9712_ng_type[] = {"Constant Gain", "Mute"};
static const char *wm9712_diff_sel[] = {"Mic", "Line"};
static const DECLARE_TLV_DB_SCALE(main_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 2000, 0);
static const struct soc_enum wm9712_enum[] = {
SOC_ENUM_SINGLE(AC97_PCI_SVID, 14, 4, wm9712_alc_select),
SOC_ENUM_SINGLE(AC97_VIDEO, 12, 4, wm9712_alc_mux),
SOC_ENUM_SINGLE(AC97_AUX, 9, 4, wm9712_out3_src),
SOC_ENUM_SINGLE(AC97_AUX, 8, 2, wm9712_spk_src),
SOC_ENUM_SINGLE(AC97_REC_SEL, 12, 4, wm9712_rec_adc),
SOC_ENUM_SINGLE(AC97_MASTER_TONE, 15, 2, wm9712_base),
SOC_ENUM_DOUBLE(AC97_REC_GAIN, 14, 6, 2, wm9712_rec_gain),
SOC_ENUM_SINGLE(AC97_MIC, 5, 4, wm9712_mic),
SOC_ENUM_SINGLE(AC97_REC_SEL, 8, 8, wm9712_rec_sel),
SOC_ENUM_SINGLE(AC97_REC_SEL, 0, 8, wm9712_rec_sel),
SOC_ENUM_SINGLE(AC97_PCI_SVID, 5, 2, wm9712_ng_type),
SOC_ENUM_SINGLE(0x5c, 8, 2, wm9712_diff_sel),
};
static const struct snd_kcontrol_new wm9712_snd_ac97_controls[] = {
SOC_DOUBLE("Speaker Playback Volume", AC97_MASTER, 8, 0, 31, 1),
SOC_SINGLE("Speaker Playback Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1),
SOC_SINGLE("Speaker Playback ZC Switch", AC97_MASTER, 7, 1, 0),
SOC_SINGLE("Speaker Playback Invert Switch", AC97_MASTER, 6, 1, 0),
SOC_SINGLE("Headphone Playback ZC Switch", AC97_HEADPHONE, 7, 1, 0),
SOC_SINGLE("Mono Playback ZC Switch", AC97_MASTER_MONO, 7, 1, 0),
SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0),
SOC_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0),
SOC_SINGLE("ALC Decay Time", AC97_CODEC_CLASS_REV, 4, 15, 0),
SOC_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0),
SOC_ENUM("ALC Function", wm9712_enum[0]),
SOC_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 0),
SOC_SINGLE("ALC ZC Timeout", AC97_PCI_SVID, 9, 3, 1),
SOC_SINGLE("ALC ZC Switch", AC97_PCI_SVID, 8, 1, 0),
SOC_SINGLE("ALC NG Switch", AC97_PCI_SVID, 7, 1, 0),
SOC_ENUM("ALC NG Type", wm9712_enum[10]),
SOC_SINGLE("ALC NG Threshold", AC97_PCI_SVID, 0, 31, 1),
SOC_SINGLE("Mic Headphone Volume", AC97_VIDEO, 12, 7, 1),
SOC_SINGLE("ALC Headphone Volume", AC97_VIDEO, 7, 7, 1),
SOC_SINGLE("Out3 Switch", AC97_AUX, 15, 1, 1),
SOC_SINGLE("Out3 ZC Switch", AC97_AUX, 7, 1, 1),
SOC_SINGLE("Out3 Volume", AC97_AUX, 0, 31, 1),
SOC_SINGLE("PCBeep Bypass Headphone Volume", AC97_PC_BEEP, 12, 7, 1),
SOC_SINGLE("PCBeep Bypass Speaker Volume", AC97_PC_BEEP, 8, 7, 1),
SOC_SINGLE("PCBeep Bypass Phone Volume", AC97_PC_BEEP, 4, 7, 1),
SOC_SINGLE("Aux Playback Headphone Volume", AC97_CD, 12, 7, 1),
SOC_SINGLE("Aux Playback Speaker Volume", AC97_CD, 8, 7, 1),
SOC_SINGLE("Aux Playback Phone Volume", AC97_CD, 4, 7, 1),
SOC_SINGLE("Phone Volume", AC97_PHONE, 0, 15, 1),
SOC_DOUBLE("Line Capture Volume", AC97_LINE, 8, 0, 31, 1),
SOC_SINGLE_TLV("Capture Boost Switch", AC97_REC_SEL, 14, 1, 0, boost_tlv),
SOC_SINGLE_TLV("Capture to Phone Boost Switch", AC97_REC_SEL, 11, 1, 1,
boost_tlv),
SOC_SINGLE("3D Upper Cut-off Switch", AC97_3D_CONTROL, 5, 1, 1),
SOC_SINGLE("3D Lower Cut-off Switch", AC97_3D_CONTROL, 4, 1, 1),
SOC_SINGLE("3D Playback Volume", AC97_3D_CONTROL, 0, 15, 0),
SOC_ENUM("Bass Control", wm9712_enum[5]),
SOC_SINGLE("Bass Cut-off Switch", AC97_MASTER_TONE, 12, 1, 1),
SOC_SINGLE("Tone Cut-off Switch", AC97_MASTER_TONE, 4, 1, 1),
SOC_SINGLE("Playback Attenuate (-6dB) Switch", AC97_MASTER_TONE, 6, 1, 0),
SOC_SINGLE("Bass Volume", AC97_MASTER_TONE, 8, 15, 1),
SOC_SINGLE("Treble Volume", AC97_MASTER_TONE, 0, 15, 1),
SOC_SINGLE("Capture Switch", AC97_REC_GAIN, 15, 1, 1),
SOC_ENUM("Capture Volume Steps", wm9712_enum[6]),
SOC_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 63, 0),
SOC_SINGLE("Capture ZC Switch", AC97_REC_GAIN, 7, 1, 0),
SOC_SINGLE_TLV("Mic 1 Volume", AC97_MIC, 8, 31, 1, main_tlv),
SOC_SINGLE_TLV("Mic 2 Volume", AC97_MIC, 0, 31, 1, main_tlv),
SOC_SINGLE_TLV("Mic Boost Volume", AC97_MIC, 7, 1, 0, boost_tlv),
};
static const unsigned int wm9712_mixer_mute_regs[] = {
AC97_VIDEO,
AC97_PCM,
AC97_LINE,
AC97_PHONE,
AC97_CD,
AC97_PC_BEEP,
};
/* We have to create a fake left and right HP mixers because
* the codec only has a single control that is shared by both channels.
* This makes it impossible to determine the audio path.
*/
static int wm9712_hp_mixer_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct wm9712_priv *wm9712 = snd_soc_component_get_drvdata(component);
unsigned int val = ucontrol->value.integer.value[0];
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mixer, mask, shift, old;
struct snd_soc_dapm_update update = {};
bool change;
mixer = mc->shift >> 8;
shift = mc->shift & 0xff;
mask = 1 << shift;
mutex_lock(&wm9712->lock);
old = wm9712->hp_mixer[mixer];
if (ucontrol->value.integer.value[0])
wm9712->hp_mixer[mixer] |= mask;
else
wm9712->hp_mixer[mixer] &= ~mask;
change = old != wm9712->hp_mixer[mixer];
if (change) {
update.kcontrol = kcontrol;
update.reg = wm9712_mixer_mute_regs[shift];
update.mask = 0x8000;
if ((wm9712->hp_mixer[0] & mask) ||
(wm9712->hp_mixer[1] & mask))
update.val = 0x0;
else
update.val = 0x8000;
snd_soc_dapm_mixer_update_power(dapm, kcontrol, val,
&update);
}
mutex_unlock(&wm9712->lock);
return change;
}
static int wm9712_hp_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
struct wm9712_priv *wm9712 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int shift, mixer;
mixer = mc->shift >> 8;
shift = mc->shift & 0xff;
ucontrol->value.integer.value[0] =
(wm9712->hp_mixer[mixer] >> shift) & 1;
return 0;
}
#define WM9712_HP_MIXER_CTRL(xname, xmixer, xshift) { \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_volsw, \
.get = wm9712_hp_mixer_get, .put = wm9712_hp_mixer_put, \
.private_value = SOC_SINGLE_VALUE(SND_SOC_NOPM, \
(xmixer << 8) | xshift, 1, 0, 0) \
}
/* Left Headphone Mixers */
static const struct snd_kcontrol_new wm9712_hpl_mixer_controls[] = {
WM9712_HP_MIXER_CTRL("PCBeep Bypass Switch", HPL_MIXER, 5),
WM9712_HP_MIXER_CTRL("Aux Playback Switch", HPL_MIXER, 4),
WM9712_HP_MIXER_CTRL("Phone Bypass Switch", HPL_MIXER, 3),
WM9712_HP_MIXER_CTRL("Line Bypass Switch", HPL_MIXER, 2),
WM9712_HP_MIXER_CTRL("PCM Playback Switch", HPL_MIXER, 1),
WM9712_HP_MIXER_CTRL("Mic Sidetone Switch", HPL_MIXER, 0),
};
/* Right Headphone Mixers */
static const struct snd_kcontrol_new wm9712_hpr_mixer_controls[] = {
WM9712_HP_MIXER_CTRL("PCBeep Bypass Switch", HPR_MIXER, 5),
WM9712_HP_MIXER_CTRL("Aux Playback Switch", HPR_MIXER, 4),
WM9712_HP_MIXER_CTRL("Phone Bypass Switch", HPR_MIXER, 3),
WM9712_HP_MIXER_CTRL("Line Bypass Switch", HPR_MIXER, 2),
WM9712_HP_MIXER_CTRL("PCM Playback Switch", HPR_MIXER, 1),
WM9712_HP_MIXER_CTRL("Mic Sidetone Switch", HPR_MIXER, 0),
};
/* Speaker Mixer */
static const struct snd_kcontrol_new wm9712_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Bypass Switch", AC97_PC_BEEP, 11, 1, 1),
SOC_DAPM_SINGLE("Aux Playback Switch", AC97_CD, 11, 1, 1),
SOC_DAPM_SINGLE("Phone Bypass Switch", AC97_PHONE, 14, 1, 1),
SOC_DAPM_SINGLE("Line Bypass Switch", AC97_LINE, 14, 1, 1),
SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PCM, 14, 1, 1),
};
/* Phone Mixer */
static const struct snd_kcontrol_new wm9712_phone_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Bypass Switch", AC97_PC_BEEP, 7, 1, 1),
SOC_DAPM_SINGLE("Aux Playback Switch", AC97_CD, 7, 1, 1),
SOC_DAPM_SINGLE("Line Bypass Switch", AC97_LINE, 13, 1, 1),
SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PCM, 13, 1, 1),
SOC_DAPM_SINGLE("Mic 1 Sidetone Switch", AC97_MIC, 14, 1, 1),
SOC_DAPM_SINGLE("Mic 2 Sidetone Switch", AC97_MIC, 13, 1, 1),
};
/* ALC headphone mux */
static const struct snd_kcontrol_new wm9712_alc_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[1]);
/* out 3 mux */
static const struct snd_kcontrol_new wm9712_out3_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[2]);
/* spk mux */
static const struct snd_kcontrol_new wm9712_spk_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[3]);
/* Capture to Phone mux */
static const struct snd_kcontrol_new wm9712_capture_phone_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[4]);
/* Capture left select */
static const struct snd_kcontrol_new wm9712_capture_selectl_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[8]);
/* Capture right select */
static const struct snd_kcontrol_new wm9712_capture_selectr_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[9]);
/* Mic select */
static const struct snd_kcontrol_new wm9712_mic_src_controls =
SOC_DAPM_ENUM("Mic Source Select", wm9712_enum[7]);
/* diff select */
static const struct snd_kcontrol_new wm9712_diff_sel_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[11]);
static const struct snd_soc_dapm_widget wm9712_dapm_widgets[] = {
SND_SOC_DAPM_MUX("ALC Sidetone Mux", SND_SOC_NOPM, 0, 0,
&wm9712_alc_mux_controls),
SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0,
&wm9712_out3_mux_controls),
SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
&wm9712_spk_mux_controls),
SND_SOC_DAPM_MUX("Capture Phone Mux", SND_SOC_NOPM, 0, 0,
&wm9712_capture_phone_mux_controls),
SND_SOC_DAPM_MUX("Left Capture Select", SND_SOC_NOPM, 0, 0,
&wm9712_capture_selectl_controls),
SND_SOC_DAPM_MUX("Right Capture Select", SND_SOC_NOPM, 0, 0,
&wm9712_capture_selectr_controls),
SND_SOC_DAPM_MUX("Left Mic Select Source", SND_SOC_NOPM, 0, 0,
&wm9712_mic_src_controls),
SND_SOC_DAPM_MUX("Right Mic Select Source", SND_SOC_NOPM, 0, 0,
&wm9712_mic_src_controls),
SND_SOC_DAPM_MUX("Differential Source", SND_SOC_NOPM, 0, 0,
&wm9712_diff_sel_controls),
SND_SOC_DAPM_MIXER("AC97 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Left HP Mixer", AC97_INT_PAGING, 9, 1,
&wm9712_hpl_mixer_controls[0], ARRAY_SIZE(wm9712_hpl_mixer_controls)),
SND_SOC_DAPM_MIXER("Right HP Mixer", AC97_INT_PAGING, 8, 1,
&wm9712_hpr_mixer_controls[0], ARRAY_SIZE(wm9712_hpr_mixer_controls)),
SND_SOC_DAPM_MIXER("Phone Mixer", AC97_INT_PAGING, 6, 1,
&wm9712_phone_mixer_controls[0], ARRAY_SIZE(wm9712_phone_mixer_controls)),
SND_SOC_DAPM_MIXER("Speaker Mixer", AC97_INT_PAGING, 7, 1,
&wm9712_speaker_mixer_controls[0],
ARRAY_SIZE(wm9712_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", AC97_INT_PAGING, 14, 1),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", AC97_INT_PAGING, 13, 1),
SND_SOC_DAPM_DAC("Aux DAC", "Aux Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", AC97_INT_PAGING, 12, 1),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", AC97_INT_PAGING, 11, 1),
SND_SOC_DAPM_PGA("Headphone PGA", AC97_INT_PAGING, 4, 1, NULL, 0),
SND_SOC_DAPM_PGA("Speaker PGA", AC97_INT_PAGING, 3, 1, NULL, 0),
SND_SOC_DAPM_PGA("Out 3 PGA", AC97_INT_PAGING, 5, 1, NULL, 0),
SND_SOC_DAPM_PGA("Line PGA", AC97_INT_PAGING, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("Phone PGA", AC97_INT_PAGING, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic PGA", AC97_INT_PAGING, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Differential Mic", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", AC97_INT_PAGING, 10, 1),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("PHONE"),
SND_SOC_DAPM_INPUT("PCBEEP"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
};
static const struct snd_soc_dapm_route wm9712_audio_map[] = {
/* virtual mixer - mixes left & right channels for spk and mono */
{"AC97 Mixer", NULL, "Left DAC"},
{"AC97 Mixer", NULL, "Right DAC"},
/* Left HP mixer */
{"Left HP Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Left HP Mixer", "Aux Playback Switch", "Aux DAC"},
{"Left HP Mixer", "Phone Bypass Switch", "Phone PGA"},
{"Left HP Mixer", "Line Bypass Switch", "Line PGA"},
{"Left HP Mixer", "PCM Playback Switch", "Left DAC"},
{"Left HP Mixer", "Mic Sidetone Switch", "Mic PGA"},
{"Left HP Mixer", NULL, "ALC Sidetone Mux"},
/* Right HP mixer */
{"Right HP Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Right HP Mixer", "Aux Playback Switch", "Aux DAC"},
{"Right HP Mixer", "Phone Bypass Switch", "Phone PGA"},
{"Right HP Mixer", "Line Bypass Switch", "Line PGA"},
{"Right HP Mixer", "PCM Playback Switch", "Right DAC"},
{"Right HP Mixer", "Mic Sidetone Switch", "Mic PGA"},
{"Right HP Mixer", NULL, "ALC Sidetone Mux"},
/* speaker mixer */
{"Speaker Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Speaker Mixer", "Line Bypass Switch", "Line PGA"},
{"Speaker Mixer", "PCM Playback Switch", "AC97 Mixer"},
{"Speaker Mixer", "Phone Bypass Switch", "Phone PGA"},
{"Speaker Mixer", "Aux Playback Switch", "Aux DAC"},
/* Phone mixer */
{"Phone Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Phone Mixer", "Line Bypass Switch", "Line PGA"},
{"Phone Mixer", "Aux Playback Switch", "Aux DAC"},
{"Phone Mixer", "PCM Playback Switch", "AC97 Mixer"},
{"Phone Mixer", "Mic 1 Sidetone Switch", "Mic PGA"},
{"Phone Mixer", "Mic 2 Sidetone Switch", "Mic PGA"},
/* inputs */
{"Line PGA", NULL, "LINEINL"},
{"Line PGA", NULL, "LINEINR"},
{"Phone PGA", NULL, "PHONE"},
{"Mic PGA", NULL, "MIC1"},
{"Mic PGA", NULL, "MIC2"},
/* microphones */
{"Differential Mic", NULL, "MIC1"},
{"Differential Mic", NULL, "MIC2"},
{"Left Mic Select Source", "Mic 1", "MIC1"},
{"Left Mic Select Source", "Mic 2", "MIC2"},
{"Left Mic Select Source", "Stereo", "MIC1"},
{"Left Mic Select Source", "Differential", "Differential Mic"},
{"Right Mic Select Source", "Mic 1", "MIC1"},
{"Right Mic Select Source", "Mic 2", "MIC2"},
{"Right Mic Select Source", "Stereo", "MIC2"},
{"Right Mic Select Source", "Differential", "Differential Mic"},
/* left capture selector */
{"Left Capture Select", "Mic", "MIC1"},
{"Left Capture Select", "Speaker Mixer", "Speaker Mixer"},
{"Left Capture Select", "Line", "LINEINL"},
{"Left Capture Select", "Headphone Mixer", "Left HP Mixer"},
{"Left Capture Select", "Phone Mixer", "Phone Mixer"},
{"Left Capture Select", "Phone", "PHONE"},
/* right capture selector */
{"Right Capture Select", "Mic", "MIC2"},
{"Right Capture Select", "Speaker Mixer", "Speaker Mixer"},
{"Right Capture Select", "Line", "LINEINR"},
{"Right Capture Select", "Headphone Mixer", "Right HP Mixer"},
{"Right Capture Select", "Phone Mixer", "Phone Mixer"},
{"Right Capture Select", "Phone", "PHONE"},
/* ALC Sidetone */
{"ALC Sidetone Mux", "Stereo", "Left Capture Select"},
{"ALC Sidetone Mux", "Stereo", "Right Capture Select"},
{"ALC Sidetone Mux", "Left", "Left Capture Select"},
{"ALC Sidetone Mux", "Right", "Right Capture Select"},
/* ADC's */
{"Left ADC", NULL, "Left Capture Select"},
{"Right ADC", NULL, "Right Capture Select"},
/* outputs */
{"MONOOUT", NULL, "Phone Mixer"},
{"HPOUTL", NULL, "Headphone PGA"},
{"Headphone PGA", NULL, "Left HP Mixer"},
{"HPOUTR", NULL, "Headphone PGA"},
{"Headphone PGA", NULL, "Right HP Mixer"},
/* mono mixer */
{"Mono Mixer", NULL, "Left HP Mixer"},
{"Mono Mixer", NULL, "Right HP Mixer"},
/* Out3 Mux */
{"Out3 Mux", "Left", "Left HP Mixer"},
{"Out3 Mux", "Mono", "Phone Mixer"},
{"Out3 Mux", "Left + Right", "Mono Mixer"},
{"Out 3 PGA", NULL, "Out3 Mux"},
{"OUT3", NULL, "Out 3 PGA"},
/* speaker Mux */
{"Speaker Mux", "Speaker Mix", "Speaker Mixer"},
{"Speaker Mux", "Headphone Mix", "Mono Mixer"},
{"Speaker PGA", NULL, "Speaker Mux"},
{"LOUT2", NULL, "Speaker PGA"},
{"ROUT2", NULL, "Speaker PGA"},
};
static int ac97_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int reg;
struct snd_pcm_runtime *runtime = substream->runtime;
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x1, 0x1);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return snd_soc_component_write(component, reg, runtime->rate);
}
static int ac97_aux_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_pcm_runtime *runtime = substream->runtime;
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x1, 0x1);
snd_soc_component_update_bits(component, AC97_PCI_SID, 0x8000, 0x8000);
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -ENODEV;
return snd_soc_component_write(component, AC97_PCM_SURR_DAC_RATE, runtime->rate);
}
#define WM9712_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
static const struct snd_soc_dai_ops wm9712_dai_ops_hifi = {
.prepare = ac97_prepare,
};
static const struct snd_soc_dai_ops wm9712_dai_ops_aux = {
.prepare = ac97_aux_prepare,
};
static struct snd_soc_dai_driver wm9712_dai[] = {
{
.name = "wm9712-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM9712_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM9712_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &wm9712_dai_ops_hifi,
},
{
.name = "wm9712-aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM9712_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &wm9712_dai_ops_aux,
}
};
static int wm9712_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_write(component, AC97_POWERDOWN, 0x0000);
break;
case SND_SOC_BIAS_OFF:
/* disable everything including AC link */
snd_soc_component_write(component, AC97_EXTENDED_MSTATUS, 0xffff);
snd_soc_component_write(component, AC97_POWERDOWN, 0xffff);
break;
}
return 0;
}
static int wm9712_soc_resume(struct snd_soc_component *component)
{
struct wm9712_priv *wm9712 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_ac97_reset(wm9712->ac97, true, WM9712_VENDOR_ID,
WM9712_VENDOR_ID_MASK);
if (ret < 0)
return ret;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
if (ret == 0)
snd_soc_component_cache_sync(component);
return ret;
}
static int wm9712_soc_probe(struct snd_soc_component *component)
{
struct wm9712_priv *wm9712 = snd_soc_component_get_drvdata(component);
struct regmap *regmap;
if (wm9712->mfd_pdata) {
wm9712->ac97 = wm9712->mfd_pdata->ac97;
regmap = wm9712->mfd_pdata->regmap;
} else if (IS_ENABLED(CONFIG_SND_SOC_AC97_BUS)) {
int ret;
wm9712->ac97 = snd_soc_new_ac97_component(component, WM9712_VENDOR_ID,
WM9712_VENDOR_ID_MASK);
if (IS_ERR(wm9712->ac97)) {
ret = PTR_ERR(wm9712->ac97);
dev_err(component->dev,
"Failed to register AC97 codec: %d\n", ret);
return ret;
}
regmap = regmap_init_ac97(wm9712->ac97, &wm9712_regmap_config);
if (IS_ERR(regmap)) {
snd_soc_free_ac97_component(wm9712->ac97);
return PTR_ERR(regmap);
}
} else {
return -ENXIO;
}
snd_soc_component_init_regmap(component, regmap);
/* set alc mux to none */
snd_soc_component_update_bits(component, AC97_VIDEO, 0x3000, 0x3000);
return 0;
}
static void wm9712_soc_remove(struct snd_soc_component *component)
{
struct wm9712_priv *wm9712 = snd_soc_component_get_drvdata(component);
if (IS_ENABLED(CONFIG_SND_SOC_AC97_BUS) && !wm9712->mfd_pdata) {
snd_soc_component_exit_regmap(component);
snd_soc_free_ac97_component(wm9712->ac97);
}
}
static const struct snd_soc_component_driver soc_component_dev_wm9712 = {
.probe = wm9712_soc_probe,
.remove = wm9712_soc_remove,
.resume = wm9712_soc_resume,
.set_bias_level = wm9712_set_bias_level,
.controls = wm9712_snd_ac97_controls,
.num_controls = ARRAY_SIZE(wm9712_snd_ac97_controls),
.dapm_widgets = wm9712_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm9712_dapm_widgets),
.dapm_routes = wm9712_audio_map,
.num_dapm_routes = ARRAY_SIZE(wm9712_audio_map),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm9712_probe(struct platform_device *pdev)
{
struct wm9712_priv *wm9712;
wm9712 = devm_kzalloc(&pdev->dev, sizeof(*wm9712), GFP_KERNEL);
if (wm9712 == NULL)
return -ENOMEM;
mutex_init(&wm9712->lock);
wm9712->mfd_pdata = dev_get_platdata(&pdev->dev);
platform_set_drvdata(pdev, wm9712);
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm9712, wm9712_dai, ARRAY_SIZE(wm9712_dai));
}
static struct platform_driver wm9712_component_driver = {
.driver = {
.name = "wm9712-codec",
},
.probe = wm9712_probe,
};
module_platform_driver(wm9712_component_driver);
MODULE_DESCRIPTION("ASoC WM9711/WM9712 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm9712.c |
// SPDX-License-Identifier: GPL-2.0
/*
* rt1011.c -- rt1011 ALSA SoC amplifier component driver
*
* Copyright(c) 2019 Realtek Semiconductor Corp.
*
* Author: Shuming Fan <[email protected]>
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt1011.h"
static int rt1011_calibrate(struct rt1011_priv *rt1011,
unsigned char cali_flag);
static const struct reg_sequence init_list[] = {
{ RT1011_POWER_9, 0xa840 },
{ RT1011_ADC_SET_5, 0x0a20 },
{ RT1011_DAC_SET_2, 0xa032 },
{ RT1011_SPK_PRO_DC_DET_1, 0xb00c },
{ RT1011_SPK_PRO_DC_DET_2, 0xcccc },
{ RT1011_A_TIMING_1, 0x6054 },
{ RT1011_POWER_7, 0x3e55 },
{ RT1011_POWER_8, 0x0520 },
{ RT1011_BOOST_CON_1, 0xe188 },
{ RT1011_POWER_4, 0x16f2 },
{ RT1011_CROSS_BQ_SET_1, 0x0004 },
{ RT1011_SIL_DET, 0xc313 },
{ RT1011_SINE_GEN_REG_1, 0x0707 },
{ RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
{ RT1011_DAC_SET_1, 0xe702 },
{ RT1011_DAC_SET_3, 0x2004 },
};
static const struct reg_default rt1011_reg[] = {
{0x0000, 0x0000},
{0x0002, 0x0000},
{0x0004, 0xa000},
{0x0006, 0x0000},
{0x0008, 0x0003},
{0x000a, 0x087e},
{0x000c, 0x0020},
{0x000e, 0x9002},
{0x0010, 0x0000},
{0x0012, 0x0000},
{0x0020, 0x0c40},
{0x0022, 0x4313},
{0x0076, 0x0000},
{0x0078, 0x0000},
{0x007a, 0x0000},
{0x007c, 0x10ec},
{0x007d, 0x1011},
{0x00f0, 0x5000},
{0x00f2, 0x0374},
{0x00f3, 0x0000},
{0x00f4, 0x0000},
{0x0100, 0x0038},
{0x0102, 0xff02},
{0x0104, 0x0232},
{0x0106, 0x200c},
{0x0107, 0x0000},
{0x0108, 0x2f2f},
{0x010a, 0x2f2f},
{0x010c, 0x002f},
{0x010e, 0xe000},
{0x0110, 0x0820},
{0x0111, 0x4010},
{0x0112, 0x0000},
{0x0114, 0x0000},
{0x0116, 0x0000},
{0x0118, 0x0000},
{0x011a, 0x0101},
{0x011c, 0x4567},
{0x011e, 0x0000},
{0x0120, 0x0000},
{0x0122, 0x0000},
{0x0124, 0x0123},
{0x0126, 0x4567},
{0x0200, 0x0000},
{0x0300, 0xffdd},
{0x0302, 0x001e},
{0x0311, 0x0000},
{0x0313, 0x5254},
{0x0314, 0x0062},
{0x0316, 0x7f40},
{0x0319, 0x000f},
{0x031a, 0xffff},
{0x031b, 0x0000},
{0x031c, 0x009f},
{0x031d, 0xffff},
{0x031e, 0x0000},
{0x031f, 0x0000},
{0x0320, 0xe31c},
{0x0321, 0x0000},
{0x0322, 0x0000},
{0x0324, 0x0000},
{0x0326, 0x0002},
{0x0328, 0x20b2},
{0x0329, 0x0175},
{0x032a, 0x32ad},
{0x032b, 0x3455},
{0x032c, 0x0528},
{0x032d, 0xa800},
{0x032e, 0x030e},
{0x0330, 0x2080},
{0x0332, 0x0034},
{0x0334, 0x0000},
{0x0508, 0x0010},
{0x050a, 0x0018},
{0x050c, 0x0000},
{0x050d, 0xffff},
{0x050e, 0x1f1f},
{0x050f, 0x04ff},
{0x0510, 0x4020},
{0x0511, 0x01f0},
{0x0512, 0x0702},
{0x0516, 0xbb80},
{0x0517, 0xffff},
{0x0518, 0xffff},
{0x0519, 0x307f},
{0x051a, 0xffff},
{0x051b, 0x0000},
{0x051c, 0x0000},
{0x051d, 0x2000},
{0x051e, 0x0000},
{0x051f, 0x0000},
{0x0520, 0x0000},
{0x0521, 0x1001},
{0x0522, 0x7fff},
{0x0524, 0x7fff},
{0x0526, 0x0000},
{0x0528, 0x0000},
{0x052a, 0x0000},
{0x0530, 0x0401},
{0x0532, 0x3000},
{0x0534, 0x0000},
{0x0535, 0xffff},
{0x0536, 0x101c},
{0x0538, 0x1814},
{0x053a, 0x100c},
{0x053c, 0x0804},
{0x053d, 0x0000},
{0x053e, 0x0000},
{0x053f, 0x0000},
{0x0540, 0x0000},
{0x0541, 0x0000},
{0x0542, 0x0000},
{0x0543, 0x0000},
{0x0544, 0x001c},
{0x0545, 0x1814},
{0x0546, 0x100c},
{0x0547, 0x0804},
{0x0548, 0x0000},
{0x0549, 0x0000},
{0x054a, 0x0000},
{0x054b, 0x0000},
{0x054c, 0x0000},
{0x054d, 0x0000},
{0x054e, 0x0000},
{0x054f, 0x0000},
{0x0566, 0x0000},
{0x0568, 0x20f1},
{0x056a, 0x0007},
{0x0600, 0x9d00},
{0x0611, 0x2000},
{0x0612, 0x505f},
{0x0613, 0x0444},
{0x0614, 0x4000},
{0x0615, 0x4004},
{0x0616, 0x0606},
{0x0617, 0x8904},
{0x0618, 0xe021},
{0x0621, 0x2000},
{0x0622, 0x505f},
{0x0623, 0x0444},
{0x0624, 0x4000},
{0x0625, 0x4004},
{0x0626, 0x0606},
{0x0627, 0x8704},
{0x0628, 0xe021},
{0x0631, 0x2000},
{0x0632, 0x517f},
{0x0633, 0x0440},
{0x0634, 0x4000},
{0x0635, 0x4104},
{0x0636, 0x0306},
{0x0637, 0x8904},
{0x0638, 0xe021},
{0x0702, 0x0014},
{0x0704, 0x0000},
{0x0706, 0x0014},
{0x0708, 0x0000},
{0x070a, 0x0000},
{0x0710, 0x0200},
{0x0711, 0x0000},
{0x0712, 0x0200},
{0x0713, 0x0000},
{0x0720, 0x0200},
{0x0721, 0x0000},
{0x0722, 0x0000},
{0x0723, 0x0000},
{0x0724, 0x0000},
{0x0725, 0x0000},
{0x0726, 0x0000},
{0x0727, 0x0000},
{0x0728, 0x0000},
{0x0729, 0x0000},
{0x0730, 0x0200},
{0x0731, 0x0000},
{0x0732, 0x0000},
{0x0733, 0x0000},
{0x0734, 0x0000},
{0x0735, 0x0000},
{0x0736, 0x0000},
{0x0737, 0x0000},
{0x0738, 0x0000},
{0x0739, 0x0000},
{0x0740, 0x0200},
{0x0741, 0x0000},
{0x0742, 0x0000},
{0x0743, 0x0000},
{0x0744, 0x0000},
{0x0745, 0x0000},
{0x0746, 0x0000},
{0x0747, 0x0000},
{0x0748, 0x0000},
{0x0749, 0x0000},
{0x0750, 0x0200},
{0x0751, 0x0000},
{0x0752, 0x0000},
{0x0753, 0x0000},
{0x0754, 0x0000},
{0x0755, 0x0000},
{0x0756, 0x0000},
{0x0757, 0x0000},
{0x0758, 0x0000},
{0x0759, 0x0000},
{0x0760, 0x0200},
{0x0761, 0x0000},
{0x0762, 0x0000},
{0x0763, 0x0000},
{0x0764, 0x0000},
{0x0765, 0x0000},
{0x0766, 0x0000},
{0x0767, 0x0000},
{0x0768, 0x0000},
{0x0769, 0x0000},
{0x0770, 0x0200},
{0x0771, 0x0000},
{0x0772, 0x0000},
{0x0773, 0x0000},
{0x0774, 0x0000},
{0x0775, 0x0000},
{0x0776, 0x0000},
{0x0777, 0x0000},
{0x0778, 0x0000},
{0x0779, 0x0000},
{0x0780, 0x0200},
{0x0781, 0x0000},
{0x0782, 0x0000},
{0x0783, 0x0000},
{0x0784, 0x0000},
{0x0785, 0x0000},
{0x0786, 0x0000},
{0x0787, 0x0000},
{0x0788, 0x0000},
{0x0789, 0x0000},
{0x0790, 0x0200},
{0x0791, 0x0000},
{0x0792, 0x0000},
{0x0793, 0x0000},
{0x0794, 0x0000},
{0x0795, 0x0000},
{0x0796, 0x0000},
{0x0797, 0x0000},
{0x0798, 0x0000},
{0x0799, 0x0000},
{0x07a0, 0x0200},
{0x07a1, 0x0000},
{0x07a2, 0x0000},
{0x07a3, 0x0000},
{0x07a4, 0x0000},
{0x07a5, 0x0000},
{0x07a6, 0x0000},
{0x07a7, 0x0000},
{0x07a8, 0x0000},
{0x07a9, 0x0000},
{0x07b0, 0x0200},
{0x07b1, 0x0000},
{0x07b2, 0x0000},
{0x07b3, 0x0000},
{0x07b4, 0x0000},
{0x07b5, 0x0000},
{0x07b6, 0x0000},
{0x07b7, 0x0000},
{0x07b8, 0x0000},
{0x07b9, 0x0000},
{0x07c0, 0x0200},
{0x07c1, 0x0000},
{0x07c2, 0x0000},
{0x07c3, 0x0000},
{0x07c4, 0x0000},
{0x07c5, 0x0000},
{0x07c6, 0x0000},
{0x07c7, 0x0000},
{0x07c8, 0x0000},
{0x07c9, 0x0000},
{0x1000, 0x4040},
{0x1002, 0x6505},
{0x1004, 0x5405},
{0x1006, 0x5555},
{0x1007, 0x003f},
{0x1008, 0x7fd7},
{0x1009, 0x770f},
{0x100a, 0xfffe},
{0x100b, 0xe000},
{0x100c, 0x0000},
{0x100d, 0x0007},
{0x1010, 0xa433},
{0x1020, 0x0000},
{0x1022, 0x0000},
{0x1024, 0x0000},
{0x1200, 0x5a01},
{0x1202, 0x6324},
{0x1204, 0x0b00},
{0x1206, 0x0000},
{0x1208, 0x0000},
{0x120a, 0x0024},
{0x120c, 0x0000},
{0x120e, 0x000e},
{0x1210, 0x0000},
{0x1212, 0x0000},
{0x1300, 0x0701},
{0x1302, 0x12f9},
{0x1304, 0x3405},
{0x1305, 0x0844},
{0x1306, 0x5611},
{0x1308, 0x555e},
{0x130a, 0xa605},
{0x130c, 0x2000},
{0x130e, 0x0000},
{0x130f, 0x0001},
{0x1310, 0xaa48},
{0x1312, 0x0285},
{0x1314, 0xaaaa},
{0x1316, 0xaaa0},
{0x1318, 0x2aaa},
{0x131a, 0xaa07},
{0x1322, 0x0029},
{0x1323, 0x4a52},
{0x1324, 0x002c},
{0x1325, 0x0b02},
{0x1326, 0x002d},
{0x1327, 0x6b5a},
{0x1328, 0x002e},
{0x1329, 0xcbb2},
{0x132a, 0x0030},
{0x132b, 0x2c0b},
{0x1330, 0x0031},
{0x1331, 0x8c63},
{0x1332, 0x0032},
{0x1333, 0xecbb},
{0x1334, 0x0034},
{0x1335, 0x4d13},
{0x1336, 0x0037},
{0x1337, 0x0dc3},
{0x1338, 0x003d},
{0x1339, 0xef7b},
{0x133a, 0x0044},
{0x133b, 0xd134},
{0x133c, 0x0047},
{0x133d, 0x91e4},
{0x133e, 0x004d},
{0x133f, 0xc370},
{0x1340, 0x0053},
{0x1341, 0xf4fd},
{0x1342, 0x0060},
{0x1343, 0x5816},
{0x1344, 0x006c},
{0x1345, 0xbb2e},
{0x1346, 0x0072},
{0x1347, 0xecbb},
{0x1348, 0x0076},
{0x1349, 0x5d97},
{0x1500, 0x0702},
{0x1502, 0x002f},
{0x1504, 0x0000},
{0x1510, 0x0064},
{0x1512, 0x0000},
{0x1514, 0xdf47},
{0x1516, 0x079c},
{0x1518, 0xfbf5},
{0x151a, 0x00bc},
{0x151c, 0x3b85},
{0x151e, 0x02b3},
{0x1520, 0x3333},
{0x1522, 0x0000},
{0x1524, 0x4000},
{0x1528, 0x0064},
{0x152a, 0x0000},
{0x152c, 0x0000},
{0x152e, 0x0000},
{0x1530, 0x0000},
{0x1532, 0x0000},
{0x1534, 0x0000},
{0x1536, 0x0000},
{0x1538, 0x0040},
{0x1539, 0x0000},
{0x153a, 0x0040},
{0x153b, 0x0000},
{0x153c, 0x0064},
{0x153e, 0x0bf9},
{0x1540, 0xb2a9},
{0x1544, 0x0200},
{0x1546, 0x0000},
{0x1548, 0x00ca},
{0x1552, 0x03ff},
{0x1554, 0x017f},
{0x1556, 0x017f},
{0x155a, 0x0000},
{0x155c, 0x0000},
{0x1560, 0x0040},
{0x1562, 0x0000},
{0x1570, 0x03ff},
{0x1571, 0xdcff},
{0x1572, 0x1e00},
{0x1573, 0x224f},
{0x1574, 0x0000},
{0x1575, 0x0000},
{0x1576, 0x1e00},
{0x1577, 0x0000},
{0x1578, 0x0000},
{0x1579, 0x1128},
{0x157a, 0x03ff},
{0x157b, 0xdcff},
{0x157c, 0x1e00},
{0x157d, 0x224f},
{0x157e, 0x0000},
{0x157f, 0x0000},
{0x1580, 0x1e00},
{0x1581, 0x0000},
{0x1582, 0x0000},
{0x1583, 0x1128},
{0x1590, 0x03ff},
{0x1591, 0xdcff},
{0x1592, 0x1e00},
{0x1593, 0x224f},
{0x1594, 0x0000},
{0x1595, 0x0000},
{0x1596, 0x1e00},
{0x1597, 0x0000},
{0x1598, 0x0000},
{0x1599, 0x1128},
{0x159a, 0x03ff},
{0x159b, 0xdcff},
{0x159c, 0x1e00},
{0x159d, 0x224f},
{0x159e, 0x0000},
{0x159f, 0x0000},
{0x15a0, 0x1e00},
{0x15a1, 0x0000},
{0x15a2, 0x0000},
{0x15a3, 0x1128},
{0x15b0, 0x007f},
{0x15b1, 0xffff},
{0x15b2, 0x007f},
{0x15b3, 0xffff},
{0x15b4, 0x007f},
{0x15b5, 0xffff},
{0x15b8, 0x007f},
{0x15b9, 0xffff},
{0x15bc, 0x0000},
{0x15bd, 0x0000},
{0x15be, 0xff00},
{0x15bf, 0x0000},
{0x15c0, 0xff00},
{0x15c1, 0x0000},
{0x15c3, 0xfc00},
{0x15c4, 0xbb80},
{0x15d0, 0x0000},
{0x15d1, 0x0000},
{0x15d2, 0x0000},
{0x15d3, 0x0000},
{0x15d4, 0x0000},
{0x15d5, 0x0000},
{0x15d6, 0x0000},
{0x15d7, 0x0000},
{0x15d8, 0x0200},
{0x15d9, 0x0000},
{0x15da, 0x0000},
{0x15db, 0x0000},
{0x15dc, 0x0000},
{0x15dd, 0x0000},
{0x15de, 0x0000},
{0x15df, 0x0000},
{0x15e0, 0x0000},
{0x15e1, 0x0000},
{0x15e2, 0x0200},
{0x15e3, 0x0000},
{0x15e4, 0x0000},
{0x15e5, 0x0000},
{0x15e6, 0x0000},
{0x15e7, 0x0000},
{0x15e8, 0x0000},
{0x15e9, 0x0000},
{0x15ea, 0x0000},
{0x15eb, 0x0000},
{0x15ec, 0x0200},
{0x15ed, 0x0000},
{0x15ee, 0x0000},
{0x15ef, 0x0000},
{0x15f0, 0x0000},
{0x15f1, 0x0000},
{0x15f2, 0x0000},
{0x15f3, 0x0000},
{0x15f4, 0x0000},
{0x15f5, 0x0000},
{0x15f6, 0x0200},
{0x15f7, 0x0200},
{0x15f8, 0x8200},
{0x15f9, 0x0000},
{0x1600, 0x007d},
{0x1601, 0xa178},
{0x1602, 0x00c2},
{0x1603, 0x5383},
{0x1604, 0x0000},
{0x1605, 0x02c1},
{0x1606, 0x007d},
{0x1607, 0xa178},
{0x1608, 0x00c2},
{0x1609, 0x5383},
{0x160a, 0x003e},
{0x160b, 0xd37d},
{0x1611, 0x3210},
{0x1612, 0x7418},
{0x1613, 0xc0ff},
{0x1614, 0x0000},
{0x1615, 0x00ff},
{0x1616, 0x0000},
{0x1617, 0x0000},
{0x1621, 0x6210},
{0x1622, 0x7418},
{0x1623, 0xc0ff},
{0x1624, 0x0000},
{0x1625, 0x00ff},
{0x1626, 0x0000},
{0x1627, 0x0000},
{0x1631, 0x3a14},
{0x1632, 0x7418},
{0x1633, 0xc3ff},
{0x1634, 0x0000},
{0x1635, 0x00ff},
{0x1636, 0x0000},
{0x1637, 0x0000},
{0x1638, 0x0000},
{0x163a, 0x0000},
{0x163c, 0x0000},
{0x163e, 0x0000},
{0x1640, 0x0000},
{0x1642, 0x0000},
{0x1644, 0x0000},
{0x1646, 0x0000},
{0x1648, 0x0000},
{0x1650, 0x0000},
{0x1652, 0x0000},
{0x1654, 0x0000},
{0x1656, 0x0000},
{0x1658, 0x0000},
{0x1660, 0x0000},
{0x1662, 0x0000},
{0x1664, 0x0000},
{0x1666, 0x0000},
{0x1668, 0x0000},
{0x1670, 0x0000},
{0x1672, 0x0000},
{0x1674, 0x0000},
{0x1676, 0x0000},
{0x1678, 0x0000},
{0x1680, 0x0000},
{0x1682, 0x0000},
{0x1684, 0x0000},
{0x1686, 0x0000},
{0x1688, 0x0000},
{0x1690, 0x0000},
{0x1692, 0x0000},
{0x1694, 0x0000},
{0x1696, 0x0000},
{0x1698, 0x0000},
{0x1700, 0x0000},
{0x1702, 0x0000},
{0x1704, 0x0000},
{0x1706, 0x0000},
{0x1708, 0x0000},
{0x1710, 0x0000},
{0x1712, 0x0000},
{0x1714, 0x0000},
{0x1716, 0x0000},
{0x1718, 0x0000},
{0x1720, 0x0000},
{0x1722, 0x0000},
{0x1724, 0x0000},
{0x1726, 0x0000},
{0x1728, 0x0000},
{0x1730, 0x0000},
{0x1732, 0x0000},
{0x1734, 0x0000},
{0x1736, 0x0000},
{0x1738, 0x0000},
{0x173a, 0x0000},
{0x173c, 0x0000},
{0x173e, 0x0000},
{0x17bb, 0x0500},
{0x17bd, 0x0004},
{0x17bf, 0x0004},
{0x17c1, 0x0004},
{0x17c2, 0x7fff},
{0x17c3, 0x0000},
{0x17c5, 0x0000},
{0x17c7, 0x0000},
{0x17c9, 0x0000},
{0x17cb, 0x2010},
{0x17cd, 0x0000},
{0x17cf, 0x0000},
{0x17d1, 0x0000},
{0x17d3, 0x0000},
{0x17d5, 0x0000},
{0x17d7, 0x0000},
{0x17d9, 0x0000},
{0x17db, 0x0000},
{0x17dd, 0x0000},
{0x17df, 0x0000},
{0x17e1, 0x0000},
{0x17e3, 0x0000},
{0x17e5, 0x0000},
{0x17e7, 0x0000},
{0x17e9, 0x0000},
{0x17eb, 0x0000},
{0x17ed, 0x0000},
{0x17ef, 0x0000},
{0x17f1, 0x0000},
{0x17f3, 0x0000},
{0x17f5, 0x0000},
{0x17f7, 0x0000},
{0x17f9, 0x0000},
{0x17fb, 0x0000},
{0x17fd, 0x0000},
{0x17ff, 0x0000},
{0x1801, 0x0000},
{0x1803, 0x0000},
};
static int rt1011_reg_init(struct snd_soc_component *component)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
regmap_multi_reg_write(rt1011->regmap,
init_list, ARRAY_SIZE(init_list));
return 0;
}
static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1011_RESET:
case RT1011_SRC_2:
case RT1011_CLK_DET:
case RT1011_SIL_DET:
case RT1011_VERSION_ID:
case RT1011_VENDOR_ID:
case RT1011_DEVICE_ID:
case RT1011_DUM_RO:
case RT1011_DAC_SET_3:
case RT1011_PWM_CAL:
case RT1011_SPK_VOL_TEST_OUT:
case RT1011_VBAT_VOL_DET_1:
case RT1011_VBAT_TEST_OUT_1:
case RT1011_VBAT_TEST_OUT_2:
case RT1011_VBAT_PROTECTION:
case RT1011_VBAT_DET:
case RT1011_BOOST_CON_1:
case RT1011_SHORT_CIRCUIT_DET_1:
case RT1011_SPK_TEMP_PROTECT_3:
case RT1011_SPK_TEMP_PROTECT_6:
case RT1011_SPK_PRO_DC_DET_3:
case RT1011_SPK_PRO_DC_DET_7:
case RT1011_SPK_PRO_DC_DET_8:
case RT1011_SPL_1:
case RT1011_SPL_4:
case RT1011_EXCUR_PROTECT_1:
case RT1011_CROSS_BQ_SET_1:
case RT1011_CROSS_BQ_SET_2:
case RT1011_BQ_SET_0:
case RT1011_BQ_SET_1:
case RT1011_BQ_SET_2:
case RT1011_TEST_PAD_STATUS:
case RT1011_DC_CALIB_CLASSD_1:
case RT1011_DC_CALIB_CLASSD_5:
case RT1011_DC_CALIB_CLASSD_6:
case RT1011_DC_CALIB_CLASSD_7:
case RT1011_DC_CALIB_CLASSD_8:
case RT1011_SINE_GEN_REG_2:
case RT1011_STP_CALIB_RS_TEMP:
case RT1011_SPK_RESISTANCE_1:
case RT1011_SPK_RESISTANCE_2:
case RT1011_SPK_THERMAL:
case RT1011_ALC_BK_GAIN_O:
case RT1011_ALC_BK_GAIN_O_PRE:
case RT1011_SPK_DC_O_23_16:
case RT1011_SPK_DC_O_15_0:
case RT1011_INIT_RECIPROCAL_SYN_24_16:
case RT1011_INIT_RECIPROCAL_SYN_15_0:
case RT1011_SPK_EXCURSION_23_16:
case RT1011_SPK_EXCURSION_15_0:
case RT1011_SEP_MAIN_OUT_23_16:
case RT1011_SEP_MAIN_OUT_15_0:
case RT1011_ALC_DRC_HB_INTERNAL_5:
case RT1011_ALC_DRC_HB_INTERNAL_6:
case RT1011_ALC_DRC_HB_INTERNAL_7:
case RT1011_ALC_DRC_BB_INTERNAL_5:
case RT1011_ALC_DRC_BB_INTERNAL_6:
case RT1011_ALC_DRC_BB_INTERNAL_7:
case RT1011_ALC_DRC_POS_INTERNAL_5:
case RT1011_ALC_DRC_POS_INTERNAL_6:
case RT1011_ALC_DRC_POS_INTERNAL_7:
case RT1011_ALC_DRC_POS_INTERNAL_8:
case RT1011_ALC_DRC_POS_INTERNAL_9:
case RT1011_ALC_DRC_POS_INTERNAL_10:
case RT1011_ALC_DRC_POS_INTERNAL_11:
case RT1011_IRQ_1:
case RT1011_EFUSE_CONTROL_1:
case RT1011_EFUSE_CONTROL_2:
case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
return true;
default:
return false;
}
}
static bool rt1011_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1011_RESET:
case RT1011_CLK_1:
case RT1011_CLK_2:
case RT1011_CLK_3:
case RT1011_CLK_4:
case RT1011_PLL_1:
case RT1011_PLL_2:
case RT1011_SRC_1:
case RT1011_SRC_2:
case RT1011_SRC_3:
case RT1011_CLK_DET:
case RT1011_SIL_DET:
case RT1011_PRIV_INDEX:
case RT1011_PRIV_DATA:
case RT1011_CUSTOMER_ID:
case RT1011_FM_VER:
case RT1011_VERSION_ID:
case RT1011_VENDOR_ID:
case RT1011_DEVICE_ID:
case RT1011_DUM_RW_0:
case RT1011_DUM_YUN:
case RT1011_DUM_RW_1:
case RT1011_DUM_RO:
case RT1011_MAN_I2C_DEV:
case RT1011_DAC_SET_1:
case RT1011_DAC_SET_2:
case RT1011_DAC_SET_3:
case RT1011_ADC_SET:
case RT1011_ADC_SET_1:
case RT1011_ADC_SET_2:
case RT1011_ADC_SET_3:
case RT1011_ADC_SET_4:
case RT1011_ADC_SET_5:
case RT1011_TDM_TOTAL_SET:
case RT1011_TDM1_SET_TCON:
case RT1011_TDM1_SET_1:
case RT1011_TDM1_SET_2:
case RT1011_TDM1_SET_3:
case RT1011_TDM1_SET_4:
case RT1011_TDM1_SET_5:
case RT1011_TDM2_SET_1:
case RT1011_TDM2_SET_2:
case RT1011_TDM2_SET_3:
case RT1011_TDM2_SET_4:
case RT1011_TDM2_SET_5:
case RT1011_PWM_CAL:
case RT1011_MIXER_1:
case RT1011_MIXER_2:
case RT1011_ADRC_LIMIT:
case RT1011_A_PRO:
case RT1011_A_TIMING_1:
case RT1011_A_TIMING_2:
case RT1011_A_TEMP_SEN:
case RT1011_SPK_VOL_DET_1:
case RT1011_SPK_VOL_DET_2:
case RT1011_SPK_VOL_TEST_OUT:
case RT1011_VBAT_VOL_DET_1:
case RT1011_VBAT_VOL_DET_2:
case RT1011_VBAT_TEST_OUT_1:
case RT1011_VBAT_TEST_OUT_2:
case RT1011_VBAT_PROTECTION:
case RT1011_VBAT_DET:
case RT1011_POWER_1:
case RT1011_POWER_2:
case RT1011_POWER_3:
case RT1011_POWER_4:
case RT1011_POWER_5:
case RT1011_POWER_6:
case RT1011_POWER_7:
case RT1011_POWER_8:
case RT1011_POWER_9:
case RT1011_CLASS_D_POS:
case RT1011_BOOST_CON_1:
case RT1011_BOOST_CON_2:
case RT1011_ANALOG_CTRL:
case RT1011_POWER_SEQ:
case RT1011_SHORT_CIRCUIT_DET_1:
case RT1011_SHORT_CIRCUIT_DET_2:
case RT1011_SPK_TEMP_PROTECT_0:
case RT1011_SPK_TEMP_PROTECT_1:
case RT1011_SPK_TEMP_PROTECT_2:
case RT1011_SPK_TEMP_PROTECT_3:
case RT1011_SPK_TEMP_PROTECT_4:
case RT1011_SPK_TEMP_PROTECT_5:
case RT1011_SPK_TEMP_PROTECT_6:
case RT1011_SPK_TEMP_PROTECT_7:
case RT1011_SPK_TEMP_PROTECT_8:
case RT1011_SPK_TEMP_PROTECT_9:
case RT1011_SPK_PRO_DC_DET_1:
case RT1011_SPK_PRO_DC_DET_2:
case RT1011_SPK_PRO_DC_DET_3:
case RT1011_SPK_PRO_DC_DET_4:
case RT1011_SPK_PRO_DC_DET_5:
case RT1011_SPK_PRO_DC_DET_6:
case RT1011_SPK_PRO_DC_DET_7:
case RT1011_SPK_PRO_DC_DET_8:
case RT1011_SPL_1:
case RT1011_SPL_2:
case RT1011_SPL_3:
case RT1011_SPL_4:
case RT1011_THER_FOLD_BACK_1:
case RT1011_THER_FOLD_BACK_2:
case RT1011_EXCUR_PROTECT_1:
case RT1011_EXCUR_PROTECT_2:
case RT1011_EXCUR_PROTECT_3:
case RT1011_EXCUR_PROTECT_4:
case RT1011_BAT_GAIN_1:
case RT1011_BAT_GAIN_2:
case RT1011_BAT_GAIN_3:
case RT1011_BAT_GAIN_4:
case RT1011_BAT_GAIN_5:
case RT1011_BAT_GAIN_6:
case RT1011_BAT_GAIN_7:
case RT1011_BAT_GAIN_8:
case RT1011_BAT_GAIN_9:
case RT1011_BAT_GAIN_10:
case RT1011_BAT_GAIN_11:
case RT1011_BAT_RT_THMAX_1:
case RT1011_BAT_RT_THMAX_2:
case RT1011_BAT_RT_THMAX_3:
case RT1011_BAT_RT_THMAX_4:
case RT1011_BAT_RT_THMAX_5:
case RT1011_BAT_RT_THMAX_6:
case RT1011_BAT_RT_THMAX_7:
case RT1011_BAT_RT_THMAX_8:
case RT1011_BAT_RT_THMAX_9:
case RT1011_BAT_RT_THMAX_10:
case RT1011_BAT_RT_THMAX_11:
case RT1011_BAT_RT_THMAX_12:
case RT1011_SPREAD_SPECTURM:
case RT1011_PRO_GAIN_MODE:
case RT1011_RT_DRC_CROSS:
case RT1011_RT_DRC_HB_1:
case RT1011_RT_DRC_HB_2:
case RT1011_RT_DRC_HB_3:
case RT1011_RT_DRC_HB_4:
case RT1011_RT_DRC_HB_5:
case RT1011_RT_DRC_HB_6:
case RT1011_RT_DRC_HB_7:
case RT1011_RT_DRC_HB_8:
case RT1011_RT_DRC_BB_1:
case RT1011_RT_DRC_BB_2:
case RT1011_RT_DRC_BB_3:
case RT1011_RT_DRC_BB_4:
case RT1011_RT_DRC_BB_5:
case RT1011_RT_DRC_BB_6:
case RT1011_RT_DRC_BB_7:
case RT1011_RT_DRC_BB_8:
case RT1011_RT_DRC_POS_1:
case RT1011_RT_DRC_POS_2:
case RT1011_RT_DRC_POS_3:
case RT1011_RT_DRC_POS_4:
case RT1011_RT_DRC_POS_5:
case RT1011_RT_DRC_POS_6:
case RT1011_RT_DRC_POS_7:
case RT1011_RT_DRC_POS_8:
case RT1011_CROSS_BQ_SET_1:
case RT1011_CROSS_BQ_SET_2:
case RT1011_BQ_SET_0:
case RT1011_BQ_SET_1:
case RT1011_BQ_SET_2:
case RT1011_BQ_PRE_GAIN_28_16:
case RT1011_BQ_PRE_GAIN_15_0:
case RT1011_BQ_POST_GAIN_28_16:
case RT1011_BQ_POST_GAIN_15_0:
case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
return true;
default:
return false;
}
}
static const char * const rt1011_din_source_select[] = {
"Left",
"Right",
"Left + Right average",
};
static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
rt1011_din_source_select);
static const char * const rt1011_tdm_data_out_select[] = {
"TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
"ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
"SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
};
static const char * const rt1011_tdm_l_ch_data_select[] = {
"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
};
static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
rt1011_tdm_l_ch_data_select);
static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
rt1011_tdm_l_ch_data_select);
static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
rt1011_tdm_l_ch_data_select);
static const char * const rt1011_adc_data_mode_select[] = {
"Stereo", "Mono"
};
static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
rt1011_adc_data_mode_select);
static const char * const rt1011_tdm_adc_data_len_control[] = {
"1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
};
static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
rt1011_tdm_adc_data_len_control);
static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
rt1011_tdm_adc_data_len_control);
static const char * const rt1011_tdm_adc_swap_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
rt1011_tdm_adc_swap_select);
static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4,
rt1011_tdm_adc_swap_select);
static void rt1011_reset(struct regmap *regmap)
{
regmap_write(regmap, RT1011_RESET, 0);
}
static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1011_priv *rt1011 =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
return 0;
}
static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1011_priv *rt1011 =
snd_soc_component_get_drvdata(component);
if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
return 0;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
if (rt1011->recv_spk_mode) {
/* 1: recevier mode on */
snd_soc_component_update_bits(component,
RT1011_CLASSD_INTERNAL_SET_3,
RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
RT1011_REG_GAIN_CLASSD_RI_410K);
snd_soc_component_update_bits(component,
RT1011_CLASSD_INTERNAL_SET_1,
RT1011_RECV_MODE_SPK_MASK,
RT1011_RECV_MODE);
} else {
/* 0: speaker mode on */
snd_soc_component_update_bits(component,
RT1011_CLASSD_INTERNAL_SET_3,
RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
RT1011_REG_GAIN_CLASSD_RI_72P5K);
snd_soc_component_update_bits(component,
RT1011_CLASSD_INTERNAL_SET_1,
RT1011_RECV_MODE_SPK_MASK,
RT1011_SPK_MODE);
}
}
return 0;
}
static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
{
if ((reg == RT1011_DAC_SET_1) ||
(reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) ||
(reg == RT1011_ADC_SET_4) || (reg == RT1011_ADC_SET_5) ||
(reg == RT1011_MIXER_1) ||
(reg == RT1011_A_TIMING_1) ||
(reg >= RT1011_POWER_7 && reg <= RT1011_POWER_8) ||
(reg == RT1011_CLASS_D_POS) || (reg == RT1011_ANALOG_CTRL) ||
(reg >= RT1011_SPK_TEMP_PROTECT_0 && reg <= RT1011_SPK_TEMP_PROTECT_6) ||
(reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) ||
(reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) ||
(reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) ||
(reg >= RT1011_SMART_BOOST_TIMING_1 && reg <= RT1011_SMART_BOOST_TIMING_36) ||
(reg == RT1011_SINE_GEN_REG_1) ||
(reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && reg <= RT1011_BQ_6_PARAMS_CHECK_5) ||
(reg >= RT1011_BQ_7_PARAMS_CHECK_1 && reg <= RT1011_BQ_10_PARAMS_CHECK_5))
return true;
return false;
}
static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1011_priv *rt1011 =
snd_soc_component_get_drvdata(component);
struct rt1011_bq_drc_params *bq_drc_info;
struct rt1011_bq_drc_params *params =
(struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
unsigned int i, mode_idx = 0;
if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
mode_idx = RT1011_ADVMODE_INITIAL_SET;
else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
else
return -EINVAL;
pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
ucontrol->id.name, mode_idx);
bq_drc_info = rt1011->bq_drc_params[mode_idx];
for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
params[i].reg = bq_drc_info[i].reg;
params[i].val = bq_drc_info[i].val;
}
return 0;
}
static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1011_priv *rt1011 =
snd_soc_component_get_drvdata(component);
struct rt1011_bq_drc_params *bq_drc_info;
struct rt1011_bq_drc_params *params =
(struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
unsigned int i, mode_idx = 0;
if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
mode_idx = RT1011_ADVMODE_INITIAL_SET;
else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
else
return -EINVAL;
bq_drc_info = rt1011->bq_drc_params[mode_idx];
memset(bq_drc_info, 0,
sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
ucontrol->id.name, mode_idx);
for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
bq_drc_info[i].reg = params[i].reg;
bq_drc_info[i].val = params[i].val;
}
for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
if (bq_drc_info[i].reg == 0)
break;
else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
snd_soc_component_write(component, bq_drc_info[i].reg,
bq_drc_info[i].val);
}
}
return 0;
}
static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 128;
uinfo->value.integer.max = 0x17ffffff;
return 0;
}
#define RT1011_BQ_DRC(xname) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = rt1011_bq_drc_info, \
.get = rt1011_bq_drc_coeff_get, \
.put = rt1011_bq_drc_coeff_put \
}
static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt1011->cali_done;
return 0;
}
static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
rt1011->cali_done = 0;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
ucontrol->value.integer.value[0])
rt1011_calibrate(rt1011, 1);
return 0;
}
static int rt1011_r0_load(struct rt1011_priv *rt1011)
{
if (!rt1011->r0_reg)
return -EINVAL;
/* write R0 to register */
regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
((rt1011->r0_reg>>16) & 0x1ff));
regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
(rt1011->r0_reg & 0xffff));
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
return 0;
}
static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt1011->r0_reg;
return 0;
}
static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
struct device *dev;
unsigned int r0_integer, r0_factor, format;
if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
return 0;
if (ucontrol->value.integer.value[0] == 0)
return -EINVAL;
dev = regmap_get_device(rt1011->regmap);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
rt1011->r0_reg = ucontrol->value.integer.value[0];
format = 2147483648U; /* 2^24 * 128 */
r0_integer = format / rt1011->r0_reg / 128;
r0_factor = ((format / rt1011->r0_reg * 100) / 128)
- (r0_integer * 100);
dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
r0_integer, r0_factor, rt1011->r0_reg);
if (rt1011->r0_reg)
rt1011_r0_load(rt1011);
}
return 0;
}
static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.max = 0x1ffffff;
return 0;
}
#define RT1011_R0_LOAD(xname) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = rt1011_r0_load_info, \
.get = rt1011_r0_load_mode_get, \
.put = rt1011_r0_load_mode_put \
}
static const char * const rt1011_i2s_ref[] = {
"None", "Left Channel", "Right Channel"
};
static SOC_ENUM_SINGLE_DECL(rt1011_i2s_ref_enum, 0, 0,
rt1011_i2s_ref);
static int rt1011_i2s_ref_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1011_priv *rt1011 =
snd_soc_component_get_drvdata(component);
rt1011->i2s_ref = ucontrol->value.enumerated.item[0];
switch (rt1011->i2s_ref) {
case RT1011_I2S_REF_LEFT_CH:
regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x1022);
regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
break;
case RT1011_I2S_REF_RIGHT_CH:
regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x10a2);
regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
break;
default:
dev_info(component->dev, "I2S Reference: Do nothing\n");
}
return 0;
}
static int rt1011_i2s_ref_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1011_priv *rt1011 =
snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = rt1011->i2s_ref;
return 0;
}
static const struct snd_kcontrol_new rt1011_snd_controls[] = {
/* I2S Data In Selection */
SOC_ENUM("DIN Source", rt1011_din_source_enum),
/* TDM Data In Selection */
SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
/* TDM1 Data Out Selection */
SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum),
SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum),
/* Data Out Mode */
SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
/* Speaker/Receiver Mode */
SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
/* BiQuad/DRC/SmartBoost Settings */
RT1011_BQ_DRC("AdvanceMode Initial Set"),
RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
/* R0 */
SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
rt1011_r0_cali_get, rt1011_r0_cali_put),
RT1011_R0_LOAD("R0 Load Mode"),
/* R0 temperature */
SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP,
2, 255, 0),
/* I2S Reference */
SOC_ENUM_EXT("I2S Reference", rt1011_i2s_ref_enum,
rt1011_i2s_ref_get, rt1011_i2s_ref_put),
};
static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
return 1;
else
return 0;
}
static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component,
RT1011_SPK_TEMP_PROTECT_0,
RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
snd_soc_component_update_bits(component, RT1011_POWER_9,
RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
msleep(50);
snd_soc_component_update_bits(component,
RT1011_CLASSD_INTERNAL_SET_1,
RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT1011_POWER_9,
RT1011_POW_MNL_SDB_MASK, 0);
snd_soc_component_update_bits(component,
RT1011_SPK_TEMP_PROTECT_0,
RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
msleep(200);
snd_soc_component_update_bits(component,
RT1011_CLASSD_INTERNAL_SET_1,
RT1011_DRIVER_READY_SPK, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
RT1011_POW_LDO2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
RT1011_PLLEN_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
RT1011_POW_BG_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
RT1011_POW_ADC_I_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
RT1011_POW_ADC_V_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
RT1011_POW_ADC_T_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
RT1011_POW_MIX_I_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
RT1011_POW_MIX_V_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
RT1011_POW_SUM_I_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
RT1011_POW_SUM_V_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
RT1011_POW_MIX_T_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
RT1011_POW_DAC_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
RT1011_POW_CLK12M_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("SPO"),
};
static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
{ "DAC", NULL, "AIF1RX" },
{ "DAC", NULL, "DAC Power" },
{ "DAC", NULL, "LDO2" },
{ "DAC", NULL, "ISENSE SPK" },
{ "DAC", NULL, "VSENSE SPK" },
{ "DAC", NULL, "CLK12M" },
{ "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
{ "DAC", NULL, "BG" },
{ "DAC", NULL, "BG MBIAS" },
{ "DAC", NULL, "BOOST SWR" },
{ "DAC", NULL, "BGOK SWR" },
{ "DAC", NULL, "VPOK SWR" },
{ "DAC", NULL, "DET VBAT" },
{ "DAC", NULL, "MBIAS" },
{ "DAC", NULL, "VREF" },
{ "DAC", NULL, "ADC I" },
{ "DAC", NULL, "ADC V" },
{ "DAC", NULL, "ADC T" },
{ "DAC", NULL, "DITHER ADC T" },
{ "DAC", NULL, "MIX I" },
{ "DAC", NULL, "MIX V" },
{ "DAC", NULL, "SUM I" },
{ "DAC", NULL, "SUM V" },
{ "DAC", NULL, "MIX T" },
{ "DAC", NULL, "TEMP REG" },
{ "SPO", NULL, "DAC" },
};
static int rt1011_get_clk_info(int sclk, int rate)
{
int i;
static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
if (sclk <= 0 || rate <= 0)
return -EINVAL;
rate = rate << 8;
for (i = 0; i < ARRAY_SIZE(pd); i++)
if (sclk == rate * pd[i])
return i;
return -EINVAL;
}
static int rt1011_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt1011->lrck = params_rate(params);
pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
if (pre_div < 0) {
dev_warn(component->dev, "Force using PLL ");
snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
rt1011->lrck * 64, rt1011->lrck * 256);
snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
rt1011->lrck * 256, SND_SOC_CLOCK_IN);
pre_div = 0;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt1011->lrck, pre_div, dai->id);
switch (params_width(params)) {
case 16:
val_len |= RT1011_I2S_TX_DL_16B;
val_len |= RT1011_I2S_RX_DL_16B;
ch_len |= RT1011_I2S_CH_TX_LEN_16B;
ch_len |= RT1011_I2S_CH_RX_LEN_16B;
break;
case 20:
val_len |= RT1011_I2S_TX_DL_20B;
val_len |= RT1011_I2S_RX_DL_20B;
ch_len |= RT1011_I2S_CH_TX_LEN_20B;
ch_len |= RT1011_I2S_CH_RX_LEN_20B;
break;
case 24:
val_len |= RT1011_I2S_TX_DL_24B;
val_len |= RT1011_I2S_RX_DL_24B;
ch_len |= RT1011_I2S_CH_TX_LEN_24B;
ch_len |= RT1011_I2S_CH_RX_LEN_24B;
break;
case 32:
val_len |= RT1011_I2S_TX_DL_32B;
val_len |= RT1011_I2S_RX_DL_32B;
ch_len |= RT1011_I2S_CH_TX_LEN_32B;
ch_len |= RT1011_I2S_CH_RX_LEN_32B;
break;
case 8:
val_len |= RT1011_I2S_TX_DL_8B;
val_len |= RT1011_I2S_RX_DL_8B;
ch_len |= RT1011_I2S_CH_TX_LEN_8B;
ch_len |= RT1011_I2S_CH_RX_LEN_8B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT1011_AIF1:
mask_clk = RT1011_FS_SYS_DIV_MASK;
val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
val_len);
snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
RT1011_I2S_CH_TX_LEN_MASK |
RT1011_I2S_CH_RX_LEN_MASK,
ch_len);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
snd_soc_component_update_bits(component,
RT1011_CLK_2, mask_clk, val_clk);
return 0;
}
static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
unsigned int reg_val = 0, reg_bclk_inv = 0;
int ret = 0;
snd_soc_dapm_mutex_lock(dapm);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT1011_I2S_TDM_MS_S;
break;
default:
ret = -EINVAL;
goto _set_fmt_err_;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_bclk_inv |= RT1011_TDM_INV_BCLK;
break;
default:
ret = -EINVAL;
goto _set_fmt_err_;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT1011_I2S_TDM_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT1011_I2S_TDM_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT1011_I2S_TDM_DF_PCM_B;
break;
default:
ret = -EINVAL;
goto _set_fmt_err_;
}
switch (dai->id) {
case RT1011_AIF1:
snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
reg_val);
snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
ret = -EINVAL;
}
_set_fmt_err_:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int rt1011_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
return 0;
/* disable MCLK detect in default */
snd_soc_component_update_bits(component, RT1011_CLK_DET,
RT1011_EN_MCLK_DET_MASK, 0);
switch (clk_id) {
case RT1011_FS_SYS_PRE_S_MCLK:
reg_val |= RT1011_FS_SYS_PRE_MCLK;
snd_soc_component_update_bits(component, RT1011_CLK_DET,
RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
break;
case RT1011_FS_SYS_PRE_S_BCLK:
reg_val |= RT1011_FS_SYS_PRE_BCLK;
break;
case RT1011_FS_SYS_PRE_S_PLL1:
reg_val |= RT1011_FS_SYS_PRE_PLL1;
break;
case RT1011_FS_SYS_PRE_S_RCCLK:
reg_val |= RT1011_FS_SYS_PRE_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_FS_SYS_PRE_MASK, reg_val);
rt1011->sysclk = freq;
rt1011->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt1011_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
freq_out == rt1011->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt1011->pll_in = 0;
rt1011->pll_out = 0;
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
return 0;
}
switch (source) {
case RT1011_PLL2_S_MCLK:
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
snd_soc_component_update_bits(component, RT1011_CLK_DET,
RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
break;
case RT1011_PLL1_S_BCLK:
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
break;
case RT1011_PLL2_S_RCCLK:
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
snd_soc_component_update_bits(component, RT1011_CLK_2,
RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n",
freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT1011_PLL_1,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT) |
(pll_code.m_bp << RT1011_PLL1_BPM_SFT) |
pll_code.n_code);
snd_soc_component_write(component, RT1011_PLL_2,
pll_code.k_code);
rt1011->pll_in = freq_in;
rt1011->pll_out = freq_out;
rt1011->pll_src = source;
return 0;
}
static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum;
int ret = 0, first_bit, last_bit;
snd_soc_dapm_mutex_lock(dapm);
if (rx_mask || tx_mask)
tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
switch (slots) {
case 4:
val |= RT1011_I2S_TX_4CH;
val |= RT1011_I2S_RX_4CH;
break;
case 6:
val |= RT1011_I2S_TX_6CH;
val |= RT1011_I2S_RX_6CH;
break;
case 8:
val |= RT1011_I2S_TX_8CH;
val |= RT1011_I2S_RX_8CH;
break;
case 2:
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
switch (slot_width) {
case 20:
val |= RT1011_I2S_CH_TX_LEN_20B;
val |= RT1011_I2S_CH_RX_LEN_20B;
break;
case 24:
val |= RT1011_I2S_CH_TX_LEN_24B;
val |= RT1011_I2S_CH_RX_LEN_24B;
break;
case 32:
val |= RT1011_I2S_CH_TX_LEN_32B;
val |= RT1011_I2S_CH_RX_LEN_32B;
break;
case 16:
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
/* Rx slot configuration */
rx_slotnum = hweight_long(rx_mask);
if (rx_slotnum > 1 || !rx_slotnum) {
ret = -EINVAL;
dev_err(component->dev, "too many rx slots or zero slot\n");
goto _set_tdm_err_;
}
first_bit = __ffs(rx_mask);
switch (first_bit) {
case 0:
case 2:
case 4:
case 6:
snd_soc_component_update_bits(component,
RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
RT1011_MONO_L_CHANNEL);
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_4,
RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
(first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
break;
case 1:
case 3:
case 5:
case 7:
snd_soc_component_update_bits(component,
RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
RT1011_MONO_R_CHANNEL);
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_4,
RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
(first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
/* Tx slot configuration */
tx_slotnum = hweight_long(tx_mask);
if (tx_slotnum > 2 || !tx_slotnum) {
ret = -EINVAL;
dev_err(component->dev, "too many tx slots or zero slot\n");
goto _set_tdm_err_;
}
first_bit = __ffs(tx_mask);
last_bit = __fls(tx_mask);
if (last_bit - first_bit > 1) {
ret = -EINVAL;
dev_err(component->dev, "tx slot location error\n");
goto _set_tdm_err_;
}
if (tx_slotnum == 1) {
snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit);
switch (first_bit) {
case 1:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC1_1_MASK,
RT1011_TDM_I2S_RX_ADC1_1_LL);
break;
case 3:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC2_1_MASK,
RT1011_TDM_I2S_RX_ADC2_1_LL);
break;
case 5:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC3_1_MASK,
RT1011_TDM_I2S_RX_ADC3_1_LL);
break;
case 7:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC4_1_MASK,
RT1011_TDM_I2S_RX_ADC4_1_LL);
break;
case 0:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC1_1_MASK, 0);
break;
case 2:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC2_1_MASK, 0);
break;
case 4:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC3_1_MASK, 0);
break;
case 6:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_3,
RT1011_TDM_I2S_RX_ADC4_1_MASK, 0);
break;
default:
ret = -EINVAL;
dev_dbg(component->dev,
"tx slot location error\n");
goto _set_tdm_err_;
}
} else if (tx_slotnum == 2) {
switch (first_bit) {
case 0:
case 2:
case 4:
case 6:
snd_soc_component_update_bits(component,
RT1011_TDM1_SET_2,
RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
RT1011_TDM_ADCDAT1_DATA_LOCATION,
RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit);
break;
default:
ret = -EINVAL;
dev_dbg(component->dev,
"tx slot location should be paired and start from slot0/2/4/6\n");
goto _set_tdm_err_;
}
}
snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
_set_tdm_err_:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static int rt1011_probe(struct snd_soc_component *component)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
int i;
rt1011->component = component;
schedule_work(&rt1011->cali_work);
rt1011->i2s_ref = 0;
rt1011->bq_drc_params = devm_kcalloc(component->dev,
RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
GFP_KERNEL);
if (!rt1011->bq_drc_params)
return -ENOMEM;
for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
GFP_KERNEL);
if (!rt1011->bq_drc_params[i])
return -ENOMEM;
}
return 0;
}
static void rt1011_remove(struct snd_soc_component *component)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
cancel_work_sync(&rt1011->cali_work);
rt1011_reset(rt1011->regmap);
}
#ifdef CONFIG_PM
static int rt1011_suspend(struct snd_soc_component *component)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1011->regmap, true);
regcache_mark_dirty(rt1011->regmap);
return 0;
}
static int rt1011_resume(struct snd_soc_component *component)
{
struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1011->regmap, false);
regcache_sync(rt1011->regmap);
return 0;
}
#else
#define rt1011_suspend NULL
#define rt1011_resume NULL
#endif
static int rt1011_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component,
RT1011_SYSTEM_RESET_1, 0x0000);
snd_soc_component_write(component,
RT1011_SYSTEM_RESET_2, 0x0000);
snd_soc_component_write(component,
RT1011_SYSTEM_RESET_3, 0x0001);
snd_soc_component_write(component,
RT1011_SYSTEM_RESET_1, 0x003f);
snd_soc_component_write(component,
RT1011_SYSTEM_RESET_2, 0x7fd7);
snd_soc_component_write(component,
RT1011_SYSTEM_RESET_3, 0x770f);
break;
default:
break;
}
return 0;
}
#define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
.hw_params = rt1011_hw_params,
.set_fmt = rt1011_set_dai_fmt,
.set_tdm_slot = rt1011_set_tdm_slot,
};
static struct snd_soc_dai_driver rt1011_dai[] = {
{
.name = "rt1011-aif",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT1011_STEREO_RATES,
.formats = RT1011_FORMATS,
},
.ops = &rt1011_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
.probe = rt1011_probe,
.remove = rt1011_remove,
.suspend = rt1011_suspend,
.resume = rt1011_resume,
.set_bias_level = rt1011_set_bias_level,
.controls = rt1011_snd_controls,
.num_controls = ARRAY_SIZE(rt1011_snd_controls),
.dapm_widgets = rt1011_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
.dapm_routes = rt1011_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
.set_sysclk = rt1011_set_component_sysclk,
.set_pll = rt1011_set_component_pll,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt1011_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = RT1011_MAX_REG + 1,
.volatile_reg = rt1011_volatile_register,
.readable_reg = rt1011_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt1011_reg,
.num_reg_defaults = ARRAY_SIZE(rt1011_reg),
.use_single_read = true,
.use_single_write = true,
};
#if defined(CONFIG_OF)
static const struct of_device_id rt1011_of_match[] = {
{ .compatible = "realtek,rt1011", },
{},
};
MODULE_DEVICE_TABLE(of, rt1011_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1011_acpi_match[] = {
{"10EC1011", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
#endif
static const struct i2c_device_id rt1011_i2c_id[] = {
{ "rt1011", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
{
unsigned int value, count = 0, r0[3];
unsigned int chk_cnt = 50; /* DONT change this */
unsigned int dc_offset;
unsigned int r0_integer, r0_factor, format;
struct device *dev = regmap_get_device(rt1011->regmap);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(rt1011->component);
int ret = 0;
snd_soc_dapm_mutex_lock(dapm);
regcache_cache_bypass(rt1011->regmap, true);
regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
/* RC clock */
regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
/* ADC/DAC setting */
regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
/* DC detection */
regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
/* Power */
regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
/* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
/* DC offset from EFUSE */
regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
/* mixer */
regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
/* EFUSE read */
regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
msleep(30);
regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
dc_offset = value << 16;
regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
dc_offset |= (value & 0xffff);
dev_info(dev, "ADC offset=0x%x\n", dc_offset);
regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
dc_offset = value << 16;
regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
dc_offset |= (value & 0xffff);
dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
dc_offset = value << 16;
regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
dc_offset |= (value & 0xffff);
dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
if (cali_flag) {
regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
/* Class D on */
regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
regmap_write(rt1011->regmap,
RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
/* STP enable */
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
r0[0] = r0[1] = r0[2] = count = 0;
while (count < chk_cnt) {
msleep(100);
regmap_read(rt1011->regmap,
RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
r0[count%3] = value << 16;
regmap_read(rt1011->regmap,
RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
r0[count%3] |= value;
if (r0[count%3] == 0)
continue;
count++;
if (r0[0] == r0[1] && r0[1] == r0[2])
break;
}
if (count > chk_cnt) {
dev_err(dev, "Calibrate R0 Failure\n");
ret = -EAGAIN;
} else {
format = 2147483648U; /* 2^24 * 128 */
r0_integer = format / r0[0] / 128;
r0_factor = ((format / r0[0] * 100) / 128)
- (r0_integer * 100);
rt1011->r0_reg = r0[0];
rt1011->cali_done = 1;
dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
r0_integer, r0_factor, r0[0]);
}
}
/* depop */
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
msleep(400);
regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
if (cali_flag) {
if (count <= chk_cnt) {
regmap_write(rt1011->regmap,
RT1011_INIT_RECIPROCAL_REG_24_16,
((r0[0]>>16) & 0x1ff));
regmap_write(rt1011->regmap,
RT1011_INIT_RECIPROCAL_REG_15_0,
(r0[0] & 0xffff));
regmap_write(rt1011->regmap,
RT1011_SPK_TEMP_PROTECT_4, 0x4080);
}
}
regcache_cache_bypass(rt1011->regmap, false);
regcache_mark_dirty(rt1011->regmap);
regcache_sync(rt1011->regmap);
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static void rt1011_calibration_work(struct work_struct *work)
{
struct rt1011_priv *rt1011 =
container_of(work, struct rt1011_priv, cali_work);
struct snd_soc_component *component = rt1011->component;
unsigned int r0_integer, r0_factor, format;
if (rt1011->r0_calib)
rt1011_calibrate(rt1011, 0);
else
rt1011_calibrate(rt1011, 1);
/*
* This flag should reset after booting.
* The factory test will do calibration again and use this flag to check
* whether the calibration completed
*/
rt1011->cali_done = 0;
/* initial */
rt1011_reg_init(component);
/* Apply temperature and calibration data from device property */
if (rt1011->temperature_calib <= 0xff &&
rt1011->temperature_calib > 0) {
snd_soc_component_update_bits(component,
RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff,
(rt1011->temperature_calib << 2));
}
if (rt1011->r0_calib) {
rt1011->r0_reg = rt1011->r0_calib;
format = 2147483648U; /* 2^24 * 128 */
r0_integer = format / rt1011->r0_reg / 128;
r0_factor = ((format / rt1011->r0_reg * 100) / 128)
- (r0_integer * 100);
dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n",
r0_integer, r0_factor, rt1011->r0_reg);
rt1011_r0_load(rt1011);
}
snd_soc_component_write(component, RT1011_ADC_SET_1, 0x2925);
}
static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev)
{
device_property_read_u32(dev, "realtek,temperature_calib",
&rt1011->temperature_calib);
device_property_read_u32(dev, "realtek,r0_calib",
&rt1011->r0_calib);
dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x",
__func__, rt1011->r0_calib, rt1011->temperature_calib);
return 0;
}
static int rt1011_i2c_probe(struct i2c_client *i2c)
{
struct rt1011_priv *rt1011;
int ret;
unsigned int val;
rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
GFP_KERNEL);
if (!rt1011)
return -ENOMEM;
i2c_set_clientdata(i2c, rt1011);
rt1011_parse_dp(rt1011, &i2c->dev);
rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
if (IS_ERR(rt1011->regmap)) {
ret = PTR_ERR(rt1011->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
if (val != RT1011_DEVICE_ID_NUM) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt1011\n", val);
return -ENODEV;
}
INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt1011,
rt1011_dai, ARRAY_SIZE(rt1011_dai));
}
static void rt1011_i2c_shutdown(struct i2c_client *client)
{
struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
rt1011_reset(rt1011->regmap);
}
static struct i2c_driver rt1011_i2c_driver = {
.driver = {
.name = "rt1011",
.of_match_table = of_match_ptr(rt1011_of_match),
.acpi_match_table = ACPI_PTR(rt1011_acpi_match)
},
.probe = rt1011_i2c_probe,
.shutdown = rt1011_i2c_shutdown,
.id_table = rt1011_i2c_id,
};
module_i2c_driver(rt1011_i2c_driver);
MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt1011.c |
// SPDX-License-Identifier: GPL-2.0+
//
// tfa9879.c -- driver for NXP Semiconductors TFA9879
//
// Copyright (C) 2014 Axentia Technologies AB
// Author: Peter Rosin <[email protected]>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/pcm_params.h>
#include "tfa9879.h"
struct tfa9879_priv {
struct regmap *regmap;
int lsb_justified;
};
static int tfa9879_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tfa9879_priv *tfa9879 = snd_soc_component_get_drvdata(component);
int fs;
int i2s_set = 0;
switch (params_rate(params)) {
case 8000:
fs = TFA9879_I2S_FS_8000;
break;
case 11025:
fs = TFA9879_I2S_FS_11025;
break;
case 12000:
fs = TFA9879_I2S_FS_12000;
break;
case 16000:
fs = TFA9879_I2S_FS_16000;
break;
case 22050:
fs = TFA9879_I2S_FS_22050;
break;
case 24000:
fs = TFA9879_I2S_FS_24000;
break;
case 32000:
fs = TFA9879_I2S_FS_32000;
break;
case 44100:
fs = TFA9879_I2S_FS_44100;
break;
case 48000:
fs = TFA9879_I2S_FS_48000;
break;
case 64000:
fs = TFA9879_I2S_FS_64000;
break;
case 88200:
fs = TFA9879_I2S_FS_88200;
break;
case 96000:
fs = TFA9879_I2S_FS_96000;
break;
default:
return -EINVAL;
}
switch (params_width(params)) {
case 16:
i2s_set = TFA9879_I2S_SET_LSB_J_16;
break;
case 24:
i2s_set = TFA9879_I2S_SET_LSB_J_24;
break;
default:
return -EINVAL;
}
if (tfa9879->lsb_justified)
snd_soc_component_update_bits(component,
TFA9879_SERIAL_INTERFACE_1,
TFA9879_I2S_SET_MASK,
i2s_set << TFA9879_I2S_SET_SHIFT);
snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1,
TFA9879_I2S_FS_MASK,
fs << TFA9879_I2S_FS_SHIFT);
return 0;
}
static int tfa9879_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
snd_soc_component_update_bits(component, TFA9879_MISC_CONTROL,
TFA9879_S_MUTE_MASK,
!!mute << TFA9879_S_MUTE_SHIFT);
return 0;
}
static int tfa9879_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tfa9879_priv *tfa9879 = snd_soc_component_get_drvdata(component);
int i2s_set;
int sck_pol;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
sck_pol = TFA9879_SCK_POL_NORMAL;
break;
case SND_SOC_DAIFMT_IB_NF:
sck_pol = TFA9879_SCK_POL_INVERSE;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
tfa9879->lsb_justified = 0;
i2s_set = TFA9879_I2S_SET_I2S_24;
break;
case SND_SOC_DAIFMT_LEFT_J:
tfa9879->lsb_justified = 0;
i2s_set = TFA9879_I2S_SET_MSB_J_24;
break;
case SND_SOC_DAIFMT_RIGHT_J:
tfa9879->lsb_justified = 1;
i2s_set = TFA9879_I2S_SET_LSB_J_24;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1,
TFA9879_SCK_POL_MASK,
sck_pol << TFA9879_SCK_POL_SHIFT);
snd_soc_component_update_bits(component, TFA9879_SERIAL_INTERFACE_1,
TFA9879_I2S_SET_MASK,
i2s_set << TFA9879_I2S_SET_SHIFT);
return 0;
}
static const struct reg_default tfa9879_regs[] = {
{ TFA9879_DEVICE_CONTROL, 0x0000 }, /* 0x00 */
{ TFA9879_SERIAL_INTERFACE_1, 0x0a18 }, /* 0x01 */
{ TFA9879_PCM_IOM2_FORMAT_1, 0x0007 }, /* 0x02 */
{ TFA9879_SERIAL_INTERFACE_2, 0x0a18 }, /* 0x03 */
{ TFA9879_PCM_IOM2_FORMAT_2, 0x0007 }, /* 0x04 */
{ TFA9879_EQUALIZER_A1, 0x59dd }, /* 0x05 */
{ TFA9879_EQUALIZER_A2, 0xc63e }, /* 0x06 */
{ TFA9879_EQUALIZER_B1, 0x651a }, /* 0x07 */
{ TFA9879_EQUALIZER_B2, 0xe53e }, /* 0x08 */
{ TFA9879_EQUALIZER_C1, 0x4616 }, /* 0x09 */
{ TFA9879_EQUALIZER_C2, 0xd33e }, /* 0x0a */
{ TFA9879_EQUALIZER_D1, 0x4df3 }, /* 0x0b */
{ TFA9879_EQUALIZER_D2, 0xea3e }, /* 0x0c */
{ TFA9879_EQUALIZER_E1, 0x5ee0 }, /* 0x0d */
{ TFA9879_EQUALIZER_E2, 0xf93e }, /* 0x0e */
{ TFA9879_BYPASS_CONTROL, 0x0093 }, /* 0x0f */
{ TFA9879_DYNAMIC_RANGE_COMPR, 0x92ba }, /* 0x10 */
{ TFA9879_BASS_TREBLE, 0x12a5 }, /* 0x11 */
{ TFA9879_HIGH_PASS_FILTER, 0x0004 }, /* 0x12 */
{ TFA9879_VOLUME_CONTROL, 0x10bd }, /* 0x13 */
{ TFA9879_MISC_CONTROL, 0x0000 }, /* 0x14 */
};
static bool tfa9879_volatile_reg(struct device *dev, unsigned int reg)
{
return reg == TFA9879_MISC_STATUS;
}
static const DECLARE_TLV_DB_SCALE(volume_tlv, -7050, 50, 1);
static const DECLARE_TLV_DB_SCALE(tb_gain_tlv, -1800, 200, 0);
static const char * const tb_freq_text[] = {
"Low", "Mid", "High"
};
static const struct soc_enum treble_freq_enum =
SOC_ENUM_SINGLE(TFA9879_BASS_TREBLE, TFA9879_F_TRBLE_SHIFT,
ARRAY_SIZE(tb_freq_text), tb_freq_text);
static const struct soc_enum bass_freq_enum =
SOC_ENUM_SINGLE(TFA9879_BASS_TREBLE, TFA9879_F_BASS_SHIFT,
ARRAY_SIZE(tb_freq_text), tb_freq_text);
static const struct snd_kcontrol_new tfa9879_controls[] = {
SOC_SINGLE_TLV("PCM Playback Volume", TFA9879_VOLUME_CONTROL,
TFA9879_VOL_SHIFT, 0xbd, 1, volume_tlv),
SOC_SINGLE_TLV("Treble Volume", TFA9879_BASS_TREBLE,
TFA9879_G_TRBLE_SHIFT, 18, 0, tb_gain_tlv),
SOC_SINGLE_TLV("Bass Volume", TFA9879_BASS_TREBLE,
TFA9879_G_BASS_SHIFT, 18, 0, tb_gain_tlv),
SOC_ENUM("Treble Corner Freq", treble_freq_enum),
SOC_ENUM("Bass Corner Freq", bass_freq_enum),
};
static const struct snd_soc_dapm_widget tfa9879_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC", NULL, TFA9879_DEVICE_CONTROL, TFA9879_OPMODE_SHIFT, 0),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
SND_SOC_DAPM_SUPPLY("POWER", TFA9879_DEVICE_CONTROL, TFA9879_POWERUP_SHIFT, 0,
NULL, 0),
};
static const struct snd_soc_dapm_route tfa9879_dapm_routes[] = {
{ "DAC", NULL, "AIFINL" },
{ "DAC", NULL, "AIFINR" },
{ "LINEOUT", NULL, "DAC" },
{ "DAC", NULL, "POWER" },
};
static const struct snd_soc_component_driver tfa9879_component = {
.controls = tfa9879_controls,
.num_controls = ARRAY_SIZE(tfa9879_controls),
.dapm_widgets = tfa9879_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tfa9879_dapm_widgets),
.dapm_routes = tfa9879_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tfa9879_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config tfa9879_regmap = {
.reg_bits = 8,
.val_bits = 16,
.volatile_reg = tfa9879_volatile_reg,
.max_register = TFA9879_MISC_STATUS,
.reg_defaults = tfa9879_regs,
.num_reg_defaults = ARRAY_SIZE(tfa9879_regs),
.cache_type = REGCACHE_RBTREE,
};
static const struct snd_soc_dai_ops tfa9879_dai_ops = {
.hw_params = tfa9879_hw_params,
.mute_stream = tfa9879_mute_stream,
.set_fmt = tfa9879_set_fmt,
.no_capture_mute = 1,
};
#define TFA9879_RATES SNDRV_PCM_RATE_8000_96000
#define TFA9879_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver tfa9879_dai = {
.name = "tfa9879-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = TFA9879_RATES,
.formats = TFA9879_FORMATS, },
.ops = &tfa9879_dai_ops,
};
static int tfa9879_i2c_probe(struct i2c_client *i2c)
{
struct tfa9879_priv *tfa9879;
int i;
tfa9879 = devm_kzalloc(&i2c->dev, sizeof(*tfa9879), GFP_KERNEL);
if (!tfa9879)
return -ENOMEM;
i2c_set_clientdata(i2c, tfa9879);
tfa9879->regmap = devm_regmap_init_i2c(i2c, &tfa9879_regmap);
if (IS_ERR(tfa9879->regmap))
return PTR_ERR(tfa9879->regmap);
/* Ensure the device is in reset state */
for (i = 0; i < ARRAY_SIZE(tfa9879_regs); i++)
regmap_write(tfa9879->regmap,
tfa9879_regs[i].reg, tfa9879_regs[i].def);
return devm_snd_soc_register_component(&i2c->dev, &tfa9879_component,
&tfa9879_dai, 1);
}
static const struct i2c_device_id tfa9879_i2c_id[] = {
{ "tfa9879", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tfa9879_i2c_id);
static const struct of_device_id tfa9879_of_match[] = {
{ .compatible = "nxp,tfa9879", },
{ }
};
MODULE_DEVICE_TABLE(of, tfa9879_of_match);
static struct i2c_driver tfa9879_i2c_driver = {
.driver = {
.name = "tfa9879",
.of_match_table = tfa9879_of_match,
},
.probe = tfa9879_i2c_probe,
.id_table = tfa9879_i2c_id,
};
module_i2c_driver(tfa9879_i2c_driver);
MODULE_DESCRIPTION("ASoC NXP Semiconductors TFA9879 driver");
MODULE_AUTHOR("Peter Rosin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tfa9879.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm5102.c -- WM5102 ALSA SoC Audio driver
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include <asm/unaligned.h>
#include "arizona.h"
#include "wm5102.h"
#include "wm_adsp.h"
#define DRV_NAME "wm5102-codec"
struct wm5102_priv {
struct arizona_priv core;
struct arizona_fll fll[2];
};
static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
static const struct cs_dsp_region wm5102_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x180000 },
{ .type = WMFW_ADSP2_XM, .base = 0x190000 },
{ .type = WMFW_ADSP2_YM, .base = 0x1a8000 },
};
static const struct reg_default wm5102_sysclk_reva_patch[] = {
{ 0x3000, 0x2225 },
{ 0x3001, 0x3a03 },
{ 0x3002, 0x0225 },
{ 0x3003, 0x0801 },
{ 0x3004, 0x6249 },
{ 0x3005, 0x0c04 },
{ 0x3006, 0x0225 },
{ 0x3007, 0x5901 },
{ 0x3008, 0xe249 },
{ 0x3009, 0x030d },
{ 0x300a, 0x0249 },
{ 0x300b, 0x2c01 },
{ 0x300c, 0xe249 },
{ 0x300d, 0x4342 },
{ 0x300e, 0xe249 },
{ 0x300f, 0x73c0 },
{ 0x3010, 0x4249 },
{ 0x3011, 0x0c00 },
{ 0x3012, 0x0225 },
{ 0x3013, 0x1f01 },
{ 0x3014, 0x0225 },
{ 0x3015, 0x1e01 },
{ 0x3016, 0x0225 },
{ 0x3017, 0xfa00 },
{ 0x3018, 0x0000 },
{ 0x3019, 0xf000 },
{ 0x301a, 0x0000 },
{ 0x301b, 0xf000 },
{ 0x301c, 0x0000 },
{ 0x301d, 0xf000 },
{ 0x301e, 0x0000 },
{ 0x301f, 0xf000 },
{ 0x3020, 0x0000 },
{ 0x3021, 0xf000 },
{ 0x3022, 0x0000 },
{ 0x3023, 0xf000 },
{ 0x3024, 0x0000 },
{ 0x3025, 0xf000 },
{ 0x3026, 0x0000 },
{ 0x3027, 0xf000 },
{ 0x3028, 0x0000 },
{ 0x3029, 0xf000 },
{ 0x302a, 0x0000 },
{ 0x302b, 0xf000 },
{ 0x302c, 0x0000 },
{ 0x302d, 0xf000 },
{ 0x302e, 0x0000 },
{ 0x302f, 0xf000 },
{ 0x3030, 0x0225 },
{ 0x3031, 0x1a01 },
{ 0x3032, 0x0225 },
{ 0x3033, 0x1e00 },
{ 0x3034, 0x0225 },
{ 0x3035, 0x1f00 },
{ 0x3036, 0x6225 },
{ 0x3037, 0xf800 },
{ 0x3038, 0x0000 },
{ 0x3039, 0xf000 },
{ 0x303a, 0x0000 },
{ 0x303b, 0xf000 },
{ 0x303c, 0x0000 },
{ 0x303d, 0xf000 },
{ 0x303e, 0x0000 },
{ 0x303f, 0xf000 },
{ 0x3040, 0x2226 },
{ 0x3041, 0x3a03 },
{ 0x3042, 0x0226 },
{ 0x3043, 0x0801 },
{ 0x3044, 0x6249 },
{ 0x3045, 0x0c06 },
{ 0x3046, 0x0226 },
{ 0x3047, 0x5901 },
{ 0x3048, 0xe249 },
{ 0x3049, 0x030d },
{ 0x304a, 0x0249 },
{ 0x304b, 0x2c01 },
{ 0x304c, 0xe249 },
{ 0x304d, 0x4342 },
{ 0x304e, 0xe249 },
{ 0x304f, 0x73c0 },
{ 0x3050, 0x4249 },
{ 0x3051, 0x0c00 },
{ 0x3052, 0x0226 },
{ 0x3053, 0x1f01 },
{ 0x3054, 0x0226 },
{ 0x3055, 0x1e01 },
{ 0x3056, 0x0226 },
{ 0x3057, 0xfa00 },
{ 0x3058, 0x0000 },
{ 0x3059, 0xf000 },
{ 0x305a, 0x0000 },
{ 0x305b, 0xf000 },
{ 0x305c, 0x0000 },
{ 0x305d, 0xf000 },
{ 0x305e, 0x0000 },
{ 0x305f, 0xf000 },
{ 0x3060, 0x0000 },
{ 0x3061, 0xf000 },
{ 0x3062, 0x0000 },
{ 0x3063, 0xf000 },
{ 0x3064, 0x0000 },
{ 0x3065, 0xf000 },
{ 0x3066, 0x0000 },
{ 0x3067, 0xf000 },
{ 0x3068, 0x0000 },
{ 0x3069, 0xf000 },
{ 0x306a, 0x0000 },
{ 0x306b, 0xf000 },
{ 0x306c, 0x0000 },
{ 0x306d, 0xf000 },
{ 0x306e, 0x0000 },
{ 0x306f, 0xf000 },
{ 0x3070, 0x0226 },
{ 0x3071, 0x1a01 },
{ 0x3072, 0x0226 },
{ 0x3073, 0x1e00 },
{ 0x3074, 0x0226 },
{ 0x3075, 0x1f00 },
{ 0x3076, 0x6226 },
{ 0x3077, 0xf800 },
{ 0x3078, 0x0000 },
{ 0x3079, 0xf000 },
{ 0x307a, 0x0000 },
{ 0x307b, 0xf000 },
{ 0x307c, 0x0000 },
{ 0x307d, 0xf000 },
{ 0x307e, 0x0000 },
{ 0x307f, 0xf000 },
{ 0x3080, 0x2227 },
{ 0x3081, 0x3a03 },
{ 0x3082, 0x0227 },
{ 0x3083, 0x0801 },
{ 0x3084, 0x6255 },
{ 0x3085, 0x0c04 },
{ 0x3086, 0x0227 },
{ 0x3087, 0x5901 },
{ 0x3088, 0xe255 },
{ 0x3089, 0x030d },
{ 0x308a, 0x0255 },
{ 0x308b, 0x2c01 },
{ 0x308c, 0xe255 },
{ 0x308d, 0x4342 },
{ 0x308e, 0xe255 },
{ 0x308f, 0x73c0 },
{ 0x3090, 0x4255 },
{ 0x3091, 0x0c00 },
{ 0x3092, 0x0227 },
{ 0x3093, 0x1f01 },
{ 0x3094, 0x0227 },
{ 0x3095, 0x1e01 },
{ 0x3096, 0x0227 },
{ 0x3097, 0xfa00 },
{ 0x3098, 0x0000 },
{ 0x3099, 0xf000 },
{ 0x309a, 0x0000 },
{ 0x309b, 0xf000 },
{ 0x309c, 0x0000 },
{ 0x309d, 0xf000 },
{ 0x309e, 0x0000 },
{ 0x309f, 0xf000 },
{ 0x30a0, 0x0000 },
{ 0x30a1, 0xf000 },
{ 0x30a2, 0x0000 },
{ 0x30a3, 0xf000 },
{ 0x30a4, 0x0000 },
{ 0x30a5, 0xf000 },
{ 0x30a6, 0x0000 },
{ 0x30a7, 0xf000 },
{ 0x30a8, 0x0000 },
{ 0x30a9, 0xf000 },
{ 0x30aa, 0x0000 },
{ 0x30ab, 0xf000 },
{ 0x30ac, 0x0000 },
{ 0x30ad, 0xf000 },
{ 0x30ae, 0x0000 },
{ 0x30af, 0xf000 },
{ 0x30b0, 0x0227 },
{ 0x30b1, 0x1a01 },
{ 0x30b2, 0x0227 },
{ 0x30b3, 0x1e00 },
{ 0x30b4, 0x0227 },
{ 0x30b5, 0x1f00 },
{ 0x30b6, 0x6227 },
{ 0x30b7, 0xf800 },
{ 0x30b8, 0x0000 },
{ 0x30b9, 0xf000 },
{ 0x30ba, 0x0000 },
{ 0x30bb, 0xf000 },
{ 0x30bc, 0x0000 },
{ 0x30bd, 0xf000 },
{ 0x30be, 0x0000 },
{ 0x30bf, 0xf000 },
{ 0x30c0, 0x2228 },
{ 0x30c1, 0x3a03 },
{ 0x30c2, 0x0228 },
{ 0x30c3, 0x0801 },
{ 0x30c4, 0x6255 },
{ 0x30c5, 0x0c06 },
{ 0x30c6, 0x0228 },
{ 0x30c7, 0x5901 },
{ 0x30c8, 0xe255 },
{ 0x30c9, 0x030d },
{ 0x30ca, 0x0255 },
{ 0x30cb, 0x2c01 },
{ 0x30cc, 0xe255 },
{ 0x30cd, 0x4342 },
{ 0x30ce, 0xe255 },
{ 0x30cf, 0x73c0 },
{ 0x30d0, 0x4255 },
{ 0x30d1, 0x0c00 },
{ 0x30d2, 0x0228 },
{ 0x30d3, 0x1f01 },
{ 0x30d4, 0x0228 },
{ 0x30d5, 0x1e01 },
{ 0x30d6, 0x0228 },
{ 0x30d7, 0xfa00 },
{ 0x30d8, 0x0000 },
{ 0x30d9, 0xf000 },
{ 0x30da, 0x0000 },
{ 0x30db, 0xf000 },
{ 0x30dc, 0x0000 },
{ 0x30dd, 0xf000 },
{ 0x30de, 0x0000 },
{ 0x30df, 0xf000 },
{ 0x30e0, 0x0000 },
{ 0x30e1, 0xf000 },
{ 0x30e2, 0x0000 },
{ 0x30e3, 0xf000 },
{ 0x30e4, 0x0000 },
{ 0x30e5, 0xf000 },
{ 0x30e6, 0x0000 },
{ 0x30e7, 0xf000 },
{ 0x30e8, 0x0000 },
{ 0x30e9, 0xf000 },
{ 0x30ea, 0x0000 },
{ 0x30eb, 0xf000 },
{ 0x30ec, 0x0000 },
{ 0x30ed, 0xf000 },
{ 0x30ee, 0x0000 },
{ 0x30ef, 0xf000 },
{ 0x30f0, 0x0228 },
{ 0x30f1, 0x1a01 },
{ 0x30f2, 0x0228 },
{ 0x30f3, 0x1e00 },
{ 0x30f4, 0x0228 },
{ 0x30f5, 0x1f00 },
{ 0x30f6, 0x6228 },
{ 0x30f7, 0xf800 },
{ 0x30f8, 0x0000 },
{ 0x30f9, 0xf000 },
{ 0x30fa, 0x0000 },
{ 0x30fb, 0xf000 },
{ 0x30fc, 0x0000 },
{ 0x30fd, 0xf000 },
{ 0x30fe, 0x0000 },
{ 0x30ff, 0xf000 },
{ 0x3100, 0x222b },
{ 0x3101, 0x3a03 },
{ 0x3102, 0x222b },
{ 0x3103, 0x5803 },
{ 0x3104, 0xe26f },
{ 0x3105, 0x030d },
{ 0x3106, 0x626f },
{ 0x3107, 0x2c01 },
{ 0x3108, 0xe26f },
{ 0x3109, 0x4342 },
{ 0x310a, 0xe26f },
{ 0x310b, 0x73c0 },
{ 0x310c, 0x026f },
{ 0x310d, 0x0c00 },
{ 0x310e, 0x022b },
{ 0x310f, 0x1f01 },
{ 0x3110, 0x022b },
{ 0x3111, 0x1e01 },
{ 0x3112, 0x022b },
{ 0x3113, 0xfa00 },
{ 0x3114, 0x0000 },
{ 0x3115, 0xf000 },
{ 0x3116, 0x0000 },
{ 0x3117, 0xf000 },
{ 0x3118, 0x0000 },
{ 0x3119, 0xf000 },
{ 0x311a, 0x0000 },
{ 0x311b, 0xf000 },
{ 0x311c, 0x0000 },
{ 0x311d, 0xf000 },
{ 0x311e, 0x0000 },
{ 0x311f, 0xf000 },
{ 0x3120, 0x022b },
{ 0x3121, 0x0a01 },
{ 0x3122, 0x022b },
{ 0x3123, 0x1e00 },
{ 0x3124, 0x022b },
{ 0x3125, 0x1f00 },
{ 0x3126, 0x622b },
{ 0x3127, 0xf800 },
{ 0x3128, 0x0000 },
{ 0x3129, 0xf000 },
{ 0x312a, 0x0000 },
{ 0x312b, 0xf000 },
{ 0x312c, 0x0000 },
{ 0x312d, 0xf000 },
{ 0x312e, 0x0000 },
{ 0x312f, 0xf000 },
{ 0x3130, 0x0000 },
{ 0x3131, 0xf000 },
{ 0x3132, 0x0000 },
{ 0x3133, 0xf000 },
{ 0x3134, 0x0000 },
{ 0x3135, 0xf000 },
{ 0x3136, 0x0000 },
{ 0x3137, 0xf000 },
{ 0x3138, 0x0000 },
{ 0x3139, 0xf000 },
{ 0x313a, 0x0000 },
{ 0x313b, 0xf000 },
{ 0x313c, 0x0000 },
{ 0x313d, 0xf000 },
{ 0x313e, 0x0000 },
{ 0x313f, 0xf000 },
{ 0x3140, 0x0000 },
{ 0x3141, 0xf000 },
{ 0x3142, 0x0000 },
{ 0x3143, 0xf000 },
{ 0x3144, 0x0000 },
{ 0x3145, 0xf000 },
{ 0x3146, 0x0000 },
{ 0x3147, 0xf000 },
{ 0x3148, 0x0000 },
{ 0x3149, 0xf000 },
{ 0x314a, 0x0000 },
{ 0x314b, 0xf000 },
{ 0x314c, 0x0000 },
{ 0x314d, 0xf000 },
{ 0x314e, 0x0000 },
{ 0x314f, 0xf000 },
{ 0x3150, 0x0000 },
{ 0x3151, 0xf000 },
{ 0x3152, 0x0000 },
{ 0x3153, 0xf000 },
{ 0x3154, 0x0000 },
{ 0x3155, 0xf000 },
{ 0x3156, 0x0000 },
{ 0x3157, 0xf000 },
{ 0x3158, 0x0000 },
{ 0x3159, 0xf000 },
{ 0x315a, 0x0000 },
{ 0x315b, 0xf000 },
{ 0x315c, 0x0000 },
{ 0x315d, 0xf000 },
{ 0x315e, 0x0000 },
{ 0x315f, 0xf000 },
{ 0x3160, 0x0000 },
{ 0x3161, 0xf000 },
{ 0x3162, 0x0000 },
{ 0x3163, 0xf000 },
{ 0x3164, 0x0000 },
{ 0x3165, 0xf000 },
{ 0x3166, 0x0000 },
{ 0x3167, 0xf000 },
{ 0x3168, 0x0000 },
{ 0x3169, 0xf000 },
{ 0x316a, 0x0000 },
{ 0x316b, 0xf000 },
{ 0x316c, 0x0000 },
{ 0x316d, 0xf000 },
{ 0x316e, 0x0000 },
{ 0x316f, 0xf000 },
{ 0x3170, 0x0000 },
{ 0x3171, 0xf000 },
{ 0x3172, 0x0000 },
{ 0x3173, 0xf000 },
{ 0x3174, 0x0000 },
{ 0x3175, 0xf000 },
{ 0x3176, 0x0000 },
{ 0x3177, 0xf000 },
{ 0x3178, 0x0000 },
{ 0x3179, 0xf000 },
{ 0x317a, 0x0000 },
{ 0x317b, 0xf000 },
{ 0x317c, 0x0000 },
{ 0x317d, 0xf000 },
{ 0x317e, 0x0000 },
{ 0x317f, 0xf000 },
{ 0x3180, 0x2001 },
{ 0x3181, 0xf101 },
{ 0x3182, 0x0000 },
{ 0x3183, 0xf000 },
{ 0x3184, 0x0000 },
{ 0x3185, 0xf000 },
{ 0x3186, 0x0000 },
{ 0x3187, 0xf000 },
{ 0x3188, 0x0000 },
{ 0x3189, 0xf000 },
{ 0x318a, 0x0000 },
{ 0x318b, 0xf000 },
{ 0x318c, 0x0000 },
{ 0x318d, 0xf000 },
{ 0x318e, 0x0000 },
{ 0x318f, 0xf000 },
{ 0x3190, 0x0000 },
{ 0x3191, 0xf000 },
{ 0x3192, 0x0000 },
{ 0x3193, 0xf000 },
{ 0x3194, 0x0000 },
{ 0x3195, 0xf000 },
{ 0x3196, 0x0000 },
{ 0x3197, 0xf000 },
{ 0x3198, 0x0000 },
{ 0x3199, 0xf000 },
{ 0x319a, 0x0000 },
{ 0x319b, 0xf000 },
{ 0x319c, 0x0000 },
{ 0x319d, 0xf000 },
{ 0x319e, 0x0000 },
{ 0x319f, 0xf000 },
{ 0x31a0, 0x0000 },
{ 0x31a1, 0xf000 },
{ 0x31a2, 0x0000 },
{ 0x31a3, 0xf000 },
{ 0x31a4, 0x0000 },
{ 0x31a5, 0xf000 },
{ 0x31a6, 0x0000 },
{ 0x31a7, 0xf000 },
{ 0x31a8, 0x0000 },
{ 0x31a9, 0xf000 },
{ 0x31aa, 0x0000 },
{ 0x31ab, 0xf000 },
{ 0x31ac, 0x0000 },
{ 0x31ad, 0xf000 },
{ 0x31ae, 0x0000 },
{ 0x31af, 0xf000 },
{ 0x31b0, 0x0000 },
{ 0x31b1, 0xf000 },
{ 0x31b2, 0x0000 },
{ 0x31b3, 0xf000 },
{ 0x31b4, 0x0000 },
{ 0x31b5, 0xf000 },
{ 0x31b6, 0x0000 },
{ 0x31b7, 0xf000 },
{ 0x31b8, 0x0000 },
{ 0x31b9, 0xf000 },
{ 0x31ba, 0x0000 },
{ 0x31bb, 0xf000 },
{ 0x31bc, 0x0000 },
{ 0x31bd, 0xf000 },
{ 0x31be, 0x0000 },
{ 0x31bf, 0xf000 },
{ 0x31c0, 0x0000 },
{ 0x31c1, 0xf000 },
{ 0x31c2, 0x0000 },
{ 0x31c3, 0xf000 },
{ 0x31c4, 0x0000 },
{ 0x31c5, 0xf000 },
{ 0x31c6, 0x0000 },
{ 0x31c7, 0xf000 },
{ 0x31c8, 0x0000 },
{ 0x31c9, 0xf000 },
{ 0x31ca, 0x0000 },
{ 0x31cb, 0xf000 },
{ 0x31cc, 0x0000 },
{ 0x31cd, 0xf000 },
{ 0x31ce, 0x0000 },
{ 0x31cf, 0xf000 },
{ 0x31d0, 0x0000 },
{ 0x31d1, 0xf000 },
{ 0x31d2, 0x0000 },
{ 0x31d3, 0xf000 },
{ 0x31d4, 0x0000 },
{ 0x31d5, 0xf000 },
{ 0x31d6, 0x0000 },
{ 0x31d7, 0xf000 },
{ 0x31d8, 0x0000 },
{ 0x31d9, 0xf000 },
{ 0x31da, 0x0000 },
{ 0x31db, 0xf000 },
{ 0x31dc, 0x0000 },
{ 0x31dd, 0xf000 },
{ 0x31de, 0x0000 },
{ 0x31df, 0xf000 },
{ 0x31e0, 0x0000 },
{ 0x31e1, 0xf000 },
{ 0x31e2, 0x0000 },
{ 0x31e3, 0xf000 },
{ 0x31e4, 0x0000 },
{ 0x31e5, 0xf000 },
{ 0x31e6, 0x0000 },
{ 0x31e7, 0xf000 },
{ 0x31e8, 0x0000 },
{ 0x31e9, 0xf000 },
{ 0x31ea, 0x0000 },
{ 0x31eb, 0xf000 },
{ 0x31ec, 0x0000 },
{ 0x31ed, 0xf000 },
{ 0x31ee, 0x0000 },
{ 0x31ef, 0xf000 },
{ 0x31f0, 0x0000 },
{ 0x31f1, 0xf000 },
{ 0x31f2, 0x0000 },
{ 0x31f3, 0xf000 },
{ 0x31f4, 0x0000 },
{ 0x31f5, 0xf000 },
{ 0x31f6, 0x0000 },
{ 0x31f7, 0xf000 },
{ 0x31f8, 0x0000 },
{ 0x31f9, 0xf000 },
{ 0x31fa, 0x0000 },
{ 0x31fb, 0xf000 },
{ 0x31fc, 0x0000 },
{ 0x31fd, 0xf000 },
{ 0x31fe, 0x0000 },
{ 0x31ff, 0xf000 },
{ 0x024d, 0xff50 },
{ 0x0252, 0xff50 },
{ 0x0259, 0x0112 },
{ 0x025e, 0x0112 },
};
static const struct reg_default wm5102_sysclk_revb_patch[] = {
{ 0x3081, 0x08FE },
{ 0x3083, 0x00ED },
{ 0x30C1, 0x08FE },
{ 0x30C3, 0x00ED },
};
static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
struct regmap *regmap = arizona->regmap;
const struct reg_default *patch = NULL;
int i, patch_size;
switch (arizona->rev) {
case 0:
patch = wm5102_sysclk_reva_patch;
patch_size = ARRAY_SIZE(wm5102_sysclk_reva_patch);
break;
default:
patch = wm5102_sysclk_revb_patch;
patch_size = ARRAY_SIZE(wm5102_sysclk_revb_patch);
break;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (patch)
for (i = 0; i < patch_size; i++)
regmap_write_async(regmap, patch[i].reg,
patch[i].def);
break;
case SND_SOC_DAPM_PRE_PMD:
break;
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_POST_PMD:
return arizona_clk_ev(w, kcontrol, event);
default:
return 0;
}
return arizona_dvfs_sysclk_ev(w, kcontrol, event);
}
static int wm5102_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
unsigned int v = 0;
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v);
if (ret != 0) {
dev_err(component->dev,
"Failed to read SYSCLK state: %d\n", ret);
return -EIO;
}
v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT;
if (v >= 3) {
ret = arizona_dvfs_up(component, ARIZONA_DVFS_ADSP1_RQ);
if (ret) {
dev_err(component->dev,
"Failed to raise DVFS: %d\n", ret);
return ret;
}
}
wm_adsp2_set_dspclk(w, v);
break;
case SND_SOC_DAPM_POST_PMD:
ret = arizona_dvfs_down(component, ARIZONA_DVFS_ADSP1_RQ);
if (ret)
dev_warn(component->dev,
"Failed to lower DVFS: %d\n", ret);
break;
default:
break;
}
return wm_adsp_early_event(w, kcontrol, event);
}
static int wm5102_out_comp_coeff_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
mutex_lock(&arizona->dac_comp_lock);
put_unaligned_be16(arizona->dac_comp_coeff,
ucontrol->value.bytes.data);
mutex_unlock(&arizona->dac_comp_lock);
return 0;
}
static int wm5102_out_comp_coeff_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
uint16_t dac_comp_coeff = get_unaligned_be16(ucontrol->value.bytes.data);
int ret = 0;
mutex_lock(&arizona->dac_comp_lock);
if (arizona->dac_comp_coeff != dac_comp_coeff) {
arizona->dac_comp_coeff = dac_comp_coeff;
ret = 1;
}
mutex_unlock(&arizona->dac_comp_lock);
return ret;
}
static int wm5102_out_comp_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
mutex_lock(&arizona->dac_comp_lock);
ucontrol->value.integer.value[0] = arizona->dac_comp_enabled;
mutex_unlock(&arizona->dac_comp_lock);
return 0;
}
static int wm5102_out_comp_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct arizona *arizona = dev_get_drvdata(component->dev->parent);
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
int ret = 0;
if (ucontrol->value.integer.value[0] > mc->max)
return -EINVAL;
mutex_lock(&arizona->dac_comp_lock);
if (arizona->dac_comp_enabled != ucontrol->value.integer.value[0]) {
arizona->dac_comp_enabled = ucontrol->value.integer.value[0];
ret = 1;
}
mutex_unlock(&arizona->dac_comp_lock);
return ret;
}
static const char * const wm5102_osr_text[] = {
"Low power", "Normal", "High performance",
};
static const unsigned int wm5102_osr_val[] = {
0x0, 0x3, 0x5,
};
static const struct soc_enum wm5102_hpout_osr[] = {
SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1L,
ARIZONA_OUT1_OSR_SHIFT, 0x7,
ARRAY_SIZE(wm5102_osr_text),
wm5102_osr_text, wm5102_osr_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2L,
ARIZONA_OUT2_OSR_SHIFT, 0x7,
ARRAY_SIZE(wm5102_osr_text),
wm5102_osr_text, wm5102_osr_val),
SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3L,
ARIZONA_OUT3_OSR_SHIFT, 0x7,
ARRAY_SIZE(wm5102_osr_text),
wm5102_osr_text, wm5102_osr_val),
};
#define WM5102_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
static const struct snd_kcontrol_new wm5102_snd_controls[] = {
SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN2 High Performance Switch", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2_OSR_SHIFT, 1, 0),
SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL,
ARIZONA_IN3_OSR_SHIFT, 1, 0),
SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL,
ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL,
ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL,
ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL,
ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL,
ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL,
ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R,
ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L,
ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R,
ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE),
ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT,
24, 0, eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT,
24, 0, eq_tlv),
ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5,
ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA),
ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE),
ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2),
ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2),
ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2),
ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE),
SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv),
ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT2L", ARIZONA_OUT2LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("HPOUT2R", ARIZONA_OUT2RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("EPOUT", ARIZONA_OUT3LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE),
SOC_SINGLE("Speaker High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_4L,
ARIZONA_OUT4_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L,
ARIZONA_OUT5_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1),
SOC_SINGLE("EPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_SINGLE_TLV("EPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_OUT3L_VOL_SHIFT, 0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT,
0xbf, 0, digital_tlv),
SOC_ENUM("HPOUT1 OSR", wm5102_hpout_osr[0]),
SOC_ENUM("HPOUT2 OSR", wm5102_hpout_osr[1]),
SOC_ENUM("EPOUT OSR", wm5102_hpout_osr[2]),
SOC_DOUBLE("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE,
ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0),
SOC_DOUBLE("HPOUT2 DRE Switch", ARIZONA_DRE_ENABLE,
ARIZONA_DRE2L_ENA_SHIFT, ARIZONA_DRE2R_ENA_SHIFT, 1, 0),
SOC_SINGLE("EPOUT DRE Switch", ARIZONA_DRE_ENABLE,
ARIZONA_DRE3L_ENA_SHIFT, 1, 0),
SOC_SINGLE("DRE Threshold", ARIZONA_DRE_CONTROL_2,
ARIZONA_DRE_T_LOW_SHIFT, 63, 0),
SOC_SINGLE("DRE Low Level ABS", ARIZONA_DRE_CONTROL_3,
ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT, 15, 0),
SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT,
ARIZONA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
SND_SOC_BYTES_EXT("Output Compensation Coefficient", 2,
wm5102_out_comp_coeff_get, wm5102_out_comp_coeff_put),
SOC_SINGLE_EXT("Output Compensation Switch", 0, 0, 1, 0,
wm5102_out_comp_switch_get, wm5102_out_comp_switch_put),
WM5102_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L),
WM5102_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R),
WM5102_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L),
WM5102_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R),
WM5102_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L),
WM5102_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L),
WM5102_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R),
WM5102_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L),
WM5102_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R),
ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE),
ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
};
ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(Mic, ARIZONA_MICMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(Noise, ARIZONA_NOISEMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(OUT3, ARIZONA_OUT3LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE);
ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE);
ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE);
ARIZONA_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE);
static const char * const wm5102_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "EPOUT",
"SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R",
};
static const unsigned int wm5102_aec_loopback_values[] = {
0, 1, 2, 3, 4, 6, 7, 8, 9,
};
static const struct soc_enum wm5102_aec_loopback =
SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(wm5102_aec_loopback_texts),
wm5102_aec_loopback_texts,
wm5102_aec_loopback_values);
static const struct snd_kcontrol_new wm5102_aec_loopback_mux =
SOC_DAPM_ENUM("AEC Loopback", wm5102_aec_loopback);
static const struct snd_soc_dapm_widget wm5102_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
0, wm5102_sysclk_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1,
ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, arizona_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK,
ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK,
ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3L_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3R_ENA_SHIFT,
0, NULL, 0, arizona_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1,
ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2,
ARIZONA_MICB2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3,
ARIZONA_MICB3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR,
ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic Mute Mixer", ARIZONA_MIC_NOISE_MIX_CONTROL_1,
ARIZONA_MICMUTE_MIX_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3,
ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3,
ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE,
ARIZONA_SLIMTX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7,
ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
ARIZONA_SLIMRX8_ENA_SHIFT, 0),
ARIZONA_DSP_WIDGETS(DSP1, "DSP1"),
SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, &wm5102_aec_loopback_mux),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1,
ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"),
ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"),
ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"),
ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"),
ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"),
ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"),
ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"),
ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"),
ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"),
ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"),
ARIZONA_MIXER_WIDGETS(Mic, "Mic"),
ARIZONA_MIXER_WIDGETS(Noise, "Noise"),
ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"),
ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"),
ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
ARIZONA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
ARIZONA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
ARIZONA_MIXER_WIDGETS(OUT3, "EPOUT"),
ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"),
ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"),
ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"),
ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"),
ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
WM_ADSP2("DSP1", 0, wm5102_adsp_power_ev),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("EPOUTN"),
SND_SOC_DAPM_OUTPUT("EPOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define ARIZONA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC", "AEC Loopback" }, \
{ name, "IN1L", "IN1L PGA" }, \
{ name, "IN1R", "IN1R PGA" }, \
{ name, "IN2L", "IN2L PGA" }, \
{ name, "IN2R", "IN2R PGA" }, \
{ name, "IN3L", "IN3L PGA" }, \
{ name, "IN3R", "IN3R PGA" }, \
{ name, "Mic Mute Mixer", "Mic Mute Mixer" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "SLIMRX7", "SLIMRX7" }, \
{ name, "SLIMRX8", "SLIMRX8" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1L", "ASRC1L" }, \
{ name, "ASRC1R", "ASRC1R" }, \
{ name, "ASRC2L", "ASRC2L" }, \
{ name, "ASRC2R", "ASRC2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }
static const struct snd_soc_dapm_route wm5102_dapm_routes[] = {
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "AIF3 Capture", NULL, "DBVDD3" },
{ "AIF3 Playback", NULL, "DBVDD3" },
{ "OUT1L", NULL, "CPVDD" },
{ "OUT1R", NULL, "CPVDD" },
{ "OUT2L", NULL, "CPVDD" },
{ "OUT2R", NULL, "CPVDD" },
{ "OUT3L", NULL, "CPVDD" },
{ "OUT4L", NULL, "SPKVDDL" },
{ "OUT4R", NULL, "SPKVDDR" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT4R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "SYSCLK" },
{ "ASRC1R", NULL, "SYSCLK" },
{ "ASRC2L", NULL, "SYSCLK" },
{ "ASRC2R", NULL, "SYSCLK" },
{ "ASRC1L", NULL, "ASYNCCLK" },
{ "ASRC1R", NULL, "ASYNCCLK" },
{ "ASRC2L", NULL, "ASYNCCLK" },
{ "ASRC2R", NULL, "ASYNCCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS3", NULL, "MICVDD" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "Slim3 Capture", NULL, "SLIMTX7" },
{ "Slim3 Capture", NULL, "SLIMTX8" },
{ "SLIMRX7", NULL, "Slim3 Playback" },
{ "SLIMRX8", NULL, "Slim3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "Slim3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Slim3 Capture", NULL, "SYSCLK" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L PGA", NULL, "IN1L" },
{ "IN1R PGA", NULL, "IN1R" },
{ "IN2L PGA", NULL, "IN2L" },
{ "IN2R PGA", NULL, "IN2R" },
{ "IN3L PGA", NULL, "IN3L" },
{ "IN3R PGA", NULL, "IN3R" },
ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
ARIZONA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
ARIZONA_MIXER_ROUTES("OUT3L", "EPOUT"),
ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"),
ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
ARIZONA_MIXER_ROUTES("EQ1", "EQ1"),
ARIZONA_MIXER_ROUTES("EQ2", "EQ2"),
ARIZONA_MIXER_ROUTES("EQ3", "EQ3"),
ARIZONA_MIXER_ROUTES("EQ4", "EQ4"),
ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"),
ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"),
ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"),
ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"),
ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"),
ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"),
ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Noise"),
ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"),
ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"),
ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"),
ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"),
ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"),
ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
ARIZONA_DSP_ROUTES("DSP1"),
{ "AEC Loopback", "HPOUT1L", "OUT1L" },
{ "AEC Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC Loopback", "HPOUT2L", "OUT2L" },
{ "AEC Loopback", "HPOUT2R", "OUT2R" },
{ "HPOUT2L", NULL, "OUT2L" },
{ "HPOUT2R", NULL, "OUT2R" },
{ "AEC Loopback", "EPOUT", "OUT3L" },
{ "EPOUTN", NULL, "OUT3L" },
{ "EPOUTP", NULL, "OUT3L" },
{ "AEC Loopback", "SPKOUTL", "OUT4L" },
{ "SPKOUTLN", NULL, "OUT4L" },
{ "SPKOUTLP", NULL, "OUT4L" },
{ "AEC Loopback", "SPKOUTR", "OUT4R" },
{ "SPKOUTRN", NULL, "OUT4R" },
{ "SPKOUTRP", NULL, "OUT4R" },
{ "AEC Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1L" },
{ "DRC1 Signal Activity", NULL, "DRC1R" },
};
static int wm5102_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int Fref, unsigned int Fout)
{
struct wm5102_priv *wm5102 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case WM5102_FLL1:
return arizona_set_fll(&wm5102->fll[0], source, Fref, Fout);
case WM5102_FLL2:
return arizona_set_fll(&wm5102->fll[1], source, Fref, Fout);
case WM5102_FLL1_REFCLK:
return arizona_set_fll_refclk(&wm5102->fll[0], source, Fref,
Fout);
case WM5102_FLL2_REFCLK:
return arizona_set_fll_refclk(&wm5102->fll[1], source, Fref,
Fout);
default:
return -EINVAL;
}
}
#define WM5102_RATES SNDRV_PCM_RATE_KNOT
#define WM5102_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm5102_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver wm5102_dai[] = {
{
.name = "wm5102-aif1",
.id = 1,
.base = ARIZONA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm5102-aif2",
.id = 2,
.base = ARIZONA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm5102-aif3",
.id = 3,
.base = ARIZONA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &arizona_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "wm5102-slim1",
.id = 4,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm5102-slim2",
.id = 5,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm5102-slim3",
.id = 6,
.playback = {
.stream_name = "Slim3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.capture = {
.stream_name = "Slim3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &arizona_simple_dai_ops,
},
{
.name = "wm5102-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 4,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
.ops = &wm5102_dai_ops,
},
{
.name = "wm5102-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 4,
.rates = WM5102_RATES,
.formats = WM5102_FORMATS,
},
},
};
static int wm5102_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct wm5102_priv *priv = snd_soc_component_get_drvdata(component);
return wm_adsp_compr_open(&priv->core.adsp[0], stream);
}
static irqreturn_t wm5102_adsp2_irq(int irq, void *data)
{
struct wm5102_priv *priv = data;
struct arizona *arizona = priv->core.arizona;
int ret;
ret = wm_adsp_compr_handle_irq(&priv->core.adsp[0]);
if (ret == -ENODEV) {
dev_err(arizona->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int wm5102_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm5102_priv *priv = snd_soc_component_get_drvdata(component);
struct arizona *arizona = priv->core.arizona;
int ret;
snd_soc_component_init_regmap(component, arizona->regmap);
ret = wm_adsp2_component_probe(&priv->core.adsp[0], component);
if (ret)
return ret;
ret = snd_soc_add_component_controls(component,
arizona_adsp2_rate_controls, 1);
if (ret)
goto err_adsp2_codec_probe;
ret = arizona_init_spk(component);
if (ret < 0)
return ret;
arizona_init_gpio(component);
snd_soc_component_disable_pin(component, "HAPTICS");
priv->core.arizona->dapm = dapm;
return 0;
err_adsp2_codec_probe:
wm_adsp2_component_remove(&priv->core.adsp[0], component);
return ret;
}
static void wm5102_component_remove(struct snd_soc_component *component)
{
struct wm5102_priv *priv = snd_soc_component_get_drvdata(component);
wm_adsp2_component_remove(&priv->core.adsp[0], component);
priv->core.arizona->dapm = NULL;
}
#define WM5102_DIG_VU 0x0200
static unsigned int wm5102_digital_vu[] = {
ARIZONA_DAC_DIGITAL_VOLUME_1L,
ARIZONA_DAC_DIGITAL_VOLUME_1R,
ARIZONA_DAC_DIGITAL_VOLUME_2L,
ARIZONA_DAC_DIGITAL_VOLUME_2R,
ARIZONA_DAC_DIGITAL_VOLUME_3L,
ARIZONA_DAC_DIGITAL_VOLUME_4L,
ARIZONA_DAC_DIGITAL_VOLUME_4R,
ARIZONA_DAC_DIGITAL_VOLUME_5L,
ARIZONA_DAC_DIGITAL_VOLUME_5R,
};
static const struct snd_compress_ops wm5102_compress_ops = {
.open = wm5102_open,
.free = wm_adsp_compr_free,
.set_params = wm_adsp_compr_set_params,
.get_caps = wm_adsp_compr_get_caps,
.trigger = wm_adsp_compr_trigger,
.pointer = wm_adsp_compr_pointer,
.copy = wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_wm5102 = {
.probe = wm5102_component_probe,
.remove = wm5102_component_remove,
.set_sysclk = arizona_set_sysclk,
.set_pll = wm5102_set_fll,
.set_jack = arizona_jack_set_jack,
.name = DRV_NAME,
.compress_ops = &wm5102_compress_ops,
.controls = wm5102_snd_controls,
.num_controls = ARRAY_SIZE(wm5102_snd_controls),
.dapm_widgets = wm5102_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm5102_dapm_widgets),
.dapm_routes = wm5102_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm5102_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm5102_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
struct wm5102_priv *wm5102;
int i, ret;
wm5102 = devm_kzalloc(&pdev->dev, sizeof(struct wm5102_priv),
GFP_KERNEL);
if (wm5102 == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, wm5102);
if (IS_ENABLED(CONFIG_OF)) {
if (!dev_get_platdata(arizona->dev)) {
ret = arizona_of_get_audio_pdata(arizona);
if (ret < 0)
return ret;
}
}
mutex_init(&arizona->dac_comp_lock);
wm5102->core.arizona = arizona;
wm5102->core.num_inputs = 6;
arizona_init_dvfs(&wm5102->core);
wm5102->core.adsp[0].part = "wm5102";
wm5102->core.adsp[0].cs_dsp.num = 1;
wm5102->core.adsp[0].cs_dsp.type = WMFW_ADSP2;
wm5102->core.adsp[0].cs_dsp.base = ARIZONA_DSP1_CONTROL_1;
wm5102->core.adsp[0].cs_dsp.dev = arizona->dev;
wm5102->core.adsp[0].cs_dsp.regmap = arizona->regmap;
wm5102->core.adsp[0].cs_dsp.mem = wm5102_dsp1_regions;
wm5102->core.adsp[0].cs_dsp.num_mems = ARRAY_SIZE(wm5102_dsp1_regions);
ret = wm_adsp2_init(&wm5102->core.adsp[0]);
if (ret != 0)
return ret;
/* This may return -EPROBE_DEFER, so do this early on */
ret = arizona_jack_codec_dev_probe(&wm5102->core, &pdev->dev);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(wm5102->fll); i++)
wm5102->fll[i].vco_mult = 1;
arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1,
ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK,
&wm5102->fll[0]);
arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1,
ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK,
&wm5102->fll[1]);
/* SR2 fixed at 8kHz, SR3 fixed at 16kHz */
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_2,
ARIZONA_SAMPLE_RATE_2_MASK, 0x11);
regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_3,
ARIZONA_SAMPLE_RATE_3_MASK, 0x12);
for (i = 0; i < ARRAY_SIZE(wm5102_dai); i++)
arizona_init_dai(&wm5102->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(wm5102_digital_vu); i++)
regmap_update_bits(arizona->regmap, wm5102_digital_vu[i],
WM5102_DIG_VU, WM5102_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", wm5102_adsp2_irq,
wm5102);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto err_jack_codec_dev;
}
ret = arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 1);
if (ret != 0)
dev_warn(&pdev->dev,
"Failed to set compressed IRQ as a wake source: %d\n",
ret);
arizona_init_common(arizona);
ret = arizona_init_vol_limit(arizona);
if (ret < 0)
goto err_dsp_irq;
ret = arizona_init_spk_irqs(arizona);
if (ret < 0)
goto err_dsp_irq;
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm5102,
wm5102_dai,
ARRAY_SIZE(wm5102_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto err_spk_irqs;
}
return ret;
err_spk_irqs:
arizona_free_spk_irqs(arizona);
err_dsp_irq:
arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, wm5102);
err_jack_codec_dev:
pm_runtime_disable(&pdev->dev);
arizona_jack_codec_dev_remove(&wm5102->core);
return ret;
}
static void wm5102_remove(struct platform_device *pdev)
{
struct wm5102_priv *wm5102 = platform_get_drvdata(pdev);
struct arizona *arizona = wm5102->core.arizona;
pm_runtime_disable(&pdev->dev);
wm_adsp2_remove(&wm5102->core.adsp[0]);
arizona_free_spk_irqs(arizona);
arizona_set_irq_wake(arizona, ARIZONA_IRQ_DSP_IRQ1, 0);
arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, wm5102);
arizona_jack_codec_dev_remove(&wm5102->core);
}
static struct platform_driver wm5102_codec_driver = {
.driver = {
.name = "wm5102-codec",
},
.probe = wm5102_probe,
.remove_new = wm5102_remove,
};
module_platform_driver(wm5102_codec_driver);
MODULE_DESCRIPTION("ASoC WM5102 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:wm5102-codec");
| linux-master | sound/soc/codecs/wm5102.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8523.c -- WM8523 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8523.h"
#define WM8523_NUM_SUPPLIES 2
static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = {
"AVDD",
"LINEVDD",
};
#define WM8523_NUM_RATES 7
/* codec private data */
struct wm8523_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES];
unsigned int sysclk;
unsigned int rate_constraint_list[WM8523_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
};
static const struct reg_default wm8523_reg_defaults[] = {
{ 2, 0x0000 }, /* R2 - PSCTRL1 */
{ 3, 0x1812 }, /* R3 - AIF_CTRL1 */
{ 4, 0x0000 }, /* R4 - AIF_CTRL2 */
{ 5, 0x0001 }, /* R5 - DAC_CTRL3 */
{ 6, 0x0190 }, /* R6 - DAC_GAINL */
{ 7, 0x0190 }, /* R7 - DAC_GAINR */
{ 8, 0x0000 }, /* R8 - ZERO_DETECT */
};
static bool wm8523_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8523_DEVICE_ID:
case WM8523_REVISION:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0);
static const char *wm8523_zd_count_text[] = {
"1024",
"2048",
};
static SOC_ENUM_SINGLE_DECL(wm8523_zc_count, WM8523_ZERO_DETECT, 0,
wm8523_zd_count_text);
static const struct snd_kcontrol_new wm8523_controls[] = {
SOC_DOUBLE_R_TLV("Playback Volume", WM8523_DAC_GAINL, WM8523_DAC_GAINR,
0, 448, 0, dac_tlv),
SOC_SINGLE("ZC Switch", WM8523_DAC_CTRL3, 4, 1, 0),
SOC_SINGLE("Playback Deemphasis Switch", WM8523_AIF_CTRL1, 8, 1, 0),
SOC_DOUBLE("Playback Switch", WM8523_DAC_CTRL3, 2, 3, 1, 1),
SOC_SINGLE("Volume Ramp Up Switch", WM8523_DAC_CTRL3, 1, 1, 0),
SOC_SINGLE("Volume Ramp Down Switch", WM8523_DAC_CTRL3, 0, 1, 0),
SOC_ENUM("Zero Detect Count", wm8523_zc_count),
};
static const struct snd_soc_dapm_widget wm8523_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
};
static const struct snd_soc_dapm_route wm8523_dapm_routes[] = {
{ "LINEVOUTL", NULL, "DAC" },
{ "LINEVOUTR", NULL, "DAC" },
};
static const struct {
int value;
int ratio;
} lrclk_ratios[WM8523_NUM_RATES] = {
{ 1, 128 },
{ 2, 192 },
{ 3, 256 },
{ 4, 384 },
{ 5, 512 },
{ 6, 768 },
{ 7, 1152 },
};
static const struct {
int value;
int ratio;
} bclk_ratios[] = {
{ 2, 32 },
{ 3, 64 },
{ 4, 128 },
};
static int wm8523_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!wm8523->sysclk) {
dev_err(component->dev,
"No MCLK configured, call set_sysclk() on init\n");
return -EINVAL;
}
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&wm8523->rate_constraint);
return 0;
}
static int wm8523_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
int i;
u16 aifctrl1 = snd_soc_component_read(component, WM8523_AIF_CTRL1);
u16 aifctrl2 = snd_soc_component_read(component, WM8523_AIF_CTRL2);
/* Find a supported LRCLK ratio */
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
if (wm8523->sysclk / params_rate(params) ==
lrclk_ratios[i].ratio)
break;
}
/* Should never happen, should be handled by constraints */
if (i == ARRAY_SIZE(lrclk_ratios)) {
dev_err(component->dev, "MCLK/fs ratio %d unsupported\n",
wm8523->sysclk / params_rate(params));
return -EINVAL;
}
aifctrl2 &= ~WM8523_SR_MASK;
aifctrl2 |= lrclk_ratios[i].value;
if (aifctrl1 & WM8523_AIF_MSTR) {
/* Find a fs->bclk ratio */
for (i = 0; i < ARRAY_SIZE(bclk_ratios); i++)
if (params_width(params) * 2 <= bclk_ratios[i].ratio)
break;
if (i == ARRAY_SIZE(bclk_ratios)) {
dev_err(component->dev,
"No matching BCLK/fs ratio for word length %d\n",
params_width(params));
return -EINVAL;
}
aifctrl2 &= ~WM8523_BCLKDIV_MASK;
aifctrl2 |= bclk_ratios[i].value << WM8523_BCLKDIV_SHIFT;
}
aifctrl1 &= ~WM8523_WL_MASK;
switch (params_width(params)) {
case 16:
break;
case 20:
aifctrl1 |= 0x8;
break;
case 24:
aifctrl1 |= 0x10;
break;
case 32:
aifctrl1 |= 0x18;
break;
}
snd_soc_component_write(component, WM8523_AIF_CTRL1, aifctrl1);
snd_soc_component_write(component, WM8523_AIF_CTRL2, aifctrl2);
return 0;
}
static int wm8523_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
unsigned int val;
int i;
wm8523->sysclk = freq;
wm8523->rate_constraint.count = 0;
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
val = freq / lrclk_ratios[i].ratio;
/* Check that it's a standard rate since core can't
* cope with others and having the odd rates confuses
* constraint matching.
*/
switch (val) {
case 8000:
case 11025:
case 16000:
case 22050:
case 32000:
case 44100:
case 48000:
case 64000:
case 88200:
case 96000:
case 176400:
case 192000:
dev_dbg(component->dev, "Supported sample rate: %dHz\n",
val);
wm8523->rate_constraint_list[i] = val;
wm8523->rate_constraint.count++;
break;
default:
dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
val);
}
}
/* Need at least one supported rate... */
if (wm8523->rate_constraint.count == 0)
return -EINVAL;
return 0;
}
static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 aifctrl1 = snd_soc_component_read(component, WM8523_AIF_CTRL1);
aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK |
WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aifctrl1 |= WM8523_AIF_MSTR;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aifctrl1 |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aifctrl1 |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
aifctrl1 |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
aifctrl1 |= 0x0023;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aifctrl1 |= WM8523_BCLK_INV | WM8523_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aifctrl1 |= WM8523_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aifctrl1 |= WM8523_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8523_AIF_CTRL1, aifctrl1);
return 0;
}
static int wm8523_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Full power on */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 3);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
/* Sync back default/cached values */
regcache_sync(wm8523->regmap);
/* Initial power up */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 1);
msleep(100);
}
/* Power up to mute */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 2);
break;
case SND_SOC_BIAS_OFF:
/* The chip runs through the power down sequence for us. */
snd_soc_component_update_bits(component, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 0);
msleep(100);
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
break;
}
return 0;
}
#define WM8523_RATES SNDRV_PCM_RATE_8000_192000
#define WM8523_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8523_dai_ops = {
.startup = wm8523_startup,
.hw_params = wm8523_hw_params,
.set_sysclk = wm8523_set_dai_sysclk,
.set_fmt = wm8523_set_dai_fmt,
};
static struct snd_soc_dai_driver wm8523_dai = {
.name = "wm8523-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2, /* Mono modes not yet supported */
.channels_max = 2,
.rates = WM8523_RATES,
.formats = WM8523_FORMATS,
},
.ops = &wm8523_dai_ops,
};
static int wm8523_probe(struct snd_soc_component *component)
{
struct wm8523_priv *wm8523 = snd_soc_component_get_drvdata(component);
wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0];
wm8523->rate_constraint.count =
ARRAY_SIZE(wm8523->rate_constraint_list);
/* Change some default settings - latch VU and enable ZC */
snd_soc_component_update_bits(component, WM8523_DAC_GAINR,
WM8523_DACR_VU, WM8523_DACR_VU);
snd_soc_component_update_bits(component, WM8523_DAC_CTRL3, WM8523_ZC, WM8523_ZC);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8523 = {
.probe = wm8523_probe,
.set_bias_level = wm8523_set_bias_level,
.controls = wm8523_controls,
.num_controls = ARRAY_SIZE(wm8523_controls),
.dapm_widgets = wm8523_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8523_dapm_widgets),
.dapm_routes = wm8523_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8523_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id wm8523_of_match[] = {
{ .compatible = "wlf,wm8523" },
{ },
};
MODULE_DEVICE_TABLE(of, wm8523_of_match);
static const struct regmap_config wm8523_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8523_ZERO_DETECT,
.reg_defaults = wm8523_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8523_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.volatile_reg = wm8523_volatile_register,
};
static int wm8523_i2c_probe(struct i2c_client *i2c)
{
struct wm8523_priv *wm8523;
unsigned int val;
int ret, i;
wm8523 = devm_kzalloc(&i2c->dev, sizeof(struct wm8523_priv),
GFP_KERNEL);
if (wm8523 == NULL)
return -ENOMEM;
wm8523->regmap = devm_regmap_init_i2c(i2c, &wm8523_regmap);
if (IS_ERR(wm8523->regmap)) {
ret = PTR_ERR(wm8523->regmap);
dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++)
wm8523->supplies[i].supply = wm8523_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(wm8523->regmap, WM8523_DEVICE_ID, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register\n");
goto err_enable;
}
if (val != 0x8523) {
dev_err(&i2c->dev, "Device is not a WM8523, ID is %x\n", ret);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_read(wm8523->regmap, WM8523_REVISION, &val);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read revision register\n");
goto err_enable;
}
dev_info(&i2c->dev, "revision %c\n",
(val & WM8523_CHIP_REV_MASK) + 'A');
ret = regmap_write(wm8523->regmap, WM8523_DEVICE_ID, 0x8523);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to reset device: %d\n", ret);
goto err_enable;
}
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
i2c_set_clientdata(i2c, wm8523);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8523, &wm8523_dai, 1);
return ret;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
return ret;
}
static const struct i2c_device_id wm8523_i2c_id[] = {
{ "wm8523", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8523_i2c_id);
static struct i2c_driver wm8523_i2c_driver = {
.driver = {
.name = "wm8523",
.of_match_table = wm8523_of_match,
},
.probe = wm8523_i2c_probe,
.id_table = wm8523_i2c_id,
};
module_i2c_driver(wm8523_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8523 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8523.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MAX9759 Amplifier Driver
*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#define DRV_NAME "max9759"
struct max9759 {
struct gpio_desc *gpiod_shutdown;
struct gpio_desc *gpiod_mute;
struct gpio_descs *gpiod_gain;
bool is_mute;
unsigned int gain;
};
static int pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *control, int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct max9759 *priv = snd_soc_component_get_drvdata(c);
if (SND_SOC_DAPM_EVENT_ON(event))
gpiod_set_value_cansleep(priv->gpiod_shutdown, 0);
else
gpiod_set_value_cansleep(priv->gpiod_shutdown, 1);
return 0;
}
/* From 6dB to 24dB in steps of 6dB */
static const DECLARE_TLV_DB_SCALE(speaker_gain_tlv, 600, 600, 0);
static int speaker_gain_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct max9759 *priv = snd_soc_component_get_drvdata(c);
ucontrol->value.integer.value[0] = priv->gain;
return 0;
}
static const bool speaker_gain_table[4][2] = {
/* G1, G2 */
{true, true}, /* +6dB */
{false, true}, /* +12dB */
{true, false}, /* +18dB */
{false, false}, /* +24dB */
};
static int speaker_gain_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct max9759 *priv = snd_soc_component_get_drvdata(c);
if (ucontrol->value.integer.value[0] < 0 ||
ucontrol->value.integer.value[0] > 3)
return -EINVAL;
priv->gain = ucontrol->value.integer.value[0];
/* G1 */
gpiod_set_value_cansleep(priv->gpiod_gain->desc[0],
speaker_gain_table[priv->gain][0]);
/* G2 */
gpiod_set_value_cansleep(priv->gpiod_gain->desc[1],
speaker_gain_table[priv->gain][1]);
return 1;
}
static int speaker_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct max9759 *priv = snd_soc_component_get_drvdata(c);
ucontrol->value.integer.value[0] = !priv->is_mute;
return 0;
}
static int speaker_mute_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct max9759 *priv = snd_soc_component_get_drvdata(c);
priv->is_mute = !ucontrol->value.integer.value[0];
gpiod_set_value_cansleep(priv->gpiod_mute, priv->is_mute);
return 1;
}
static const struct snd_kcontrol_new max9759_dapm_controls[] = {
SOC_SINGLE_EXT_TLV("Speaker Gain Volume", 0, 0, 3, 0,
speaker_gain_control_get, speaker_gain_control_put,
speaker_gain_tlv),
SOC_SINGLE_BOOL_EXT("Playback Switch", 0,
speaker_mute_get, speaker_mute_put),
};
static const struct snd_soc_dapm_widget max9759_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("INL"),
SND_SOC_DAPM_INPUT("INR"),
SND_SOC_DAPM_PGA_E("PGA", SND_SOC_NOPM, 0, 0, NULL, 0, pga_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
SND_SOC_DAPM_OUTPUT("OUTL"),
SND_SOC_DAPM_OUTPUT("OUTR"),
};
static const struct snd_soc_dapm_route max9759_dapm_routes[] = {
{ "PGA", NULL, "INL" },
{ "PGA", NULL, "INR" },
{ "OUTL", NULL, "PGA" },
{ "OUTR", NULL, "PGA" },
};
static const struct snd_soc_component_driver max9759_component_driver = {
.controls = max9759_dapm_controls,
.num_controls = ARRAY_SIZE(max9759_dapm_controls),
.dapm_widgets = max9759_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max9759_dapm_widgets),
.dapm_routes = max9759_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max9759_dapm_routes),
};
static int max9759_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct max9759 *priv;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->gpiod_shutdown = devm_gpiod_get(dev, "shutdown", GPIOD_OUT_HIGH);
if (IS_ERR(priv->gpiod_shutdown))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_shutdown),
"Failed to get 'shutdown' gpio");
priv->gpiod_mute = devm_gpiod_get(dev, "mute", GPIOD_OUT_HIGH);
if (IS_ERR(priv->gpiod_mute))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_mute),
"Failed to get 'mute' gpio");
priv->is_mute = true;
priv->gpiod_gain = devm_gpiod_get_array(dev, "gain", GPIOD_OUT_HIGH);
if (IS_ERR(priv->gpiod_gain))
return dev_err_probe(dev, PTR_ERR(priv->gpiod_gain),
"Failed to get 'gain' gpios");
priv->gain = 0;
if (priv->gpiod_gain->ndescs != 2) {
dev_err(dev, "Invalid 'gain' gpios count: %d",
priv->gpiod_gain->ndescs);
return -EINVAL;
}
return devm_snd_soc_register_component(dev, &max9759_component_driver,
NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id max9759_ids[] = {
{ .compatible = "maxim,max9759", },
{ }
};
MODULE_DEVICE_TABLE(of, max9759_ids);
#endif
static struct platform_driver max9759_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(max9759_ids),
},
.probe = max9759_probe,
};
module_platform_driver(max9759_driver);
MODULE_DESCRIPTION("ASoC MAX9759 amplifier driver");
MODULE_AUTHOR("Neil Armstrong <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max9759.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8727.c
*
* Created on: 15-Oct-2009
* Author: [email protected]
*
* Copyright (C) 2009 Imagination Technologies Ltd.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
static const struct snd_soc_dapm_widget wm8727_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
};
static const struct snd_soc_dapm_route wm8727_dapm_routes[] = {
{ "VOUTL", NULL, "Playback" },
{ "VOUTR", NULL, "Playback" },
};
/*
* Note this is a simple chip with no configuration interface, sample rate is
* determined automatically by examining the Master clock and Bit clock ratios
*/
#define WM8727_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
static struct snd_soc_dai_driver wm8727_dai = {
.name = "wm8727-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8727_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
},
};
static const struct snd_soc_component_driver soc_component_dev_wm8727 = {
.dapm_widgets = wm8727_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8727_dapm_widgets),
.dapm_routes = wm8727_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8727_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int wm8727_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_wm8727, &wm8727_dai, 1);
}
static struct platform_driver wm8727_codec_driver = {
.driver = {
.name = "wm8727",
},
.probe = wm8727_probe,
};
module_platform_driver(wm8727_codec_driver);
MODULE_DESCRIPTION("ASoC wm8727 driver");
MODULE_AUTHOR("Neil Jones");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8727.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* PCM179X ASoC SPI driver
*
* Copyright (c) Amarula Solutions B.V. 2013
*
* Michael Trimarchi <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include "pcm179x.h"
static int pcm179x_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_spi(spi, &pcm179x_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&spi->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
return pcm179x_common_init(&spi->dev, regmap);
}
static const struct of_device_id pcm179x_of_match[] __maybe_unused = {
{ .compatible = "ti,pcm1792a", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm179x_of_match);
static const struct spi_device_id pcm179x_spi_ids[] = {
{ "pcm1792a", 0 },
{ "pcm179x", 0 },
{ },
};
MODULE_DEVICE_TABLE(spi, pcm179x_spi_ids);
static struct spi_driver pcm179x_spi_driver = {
.driver = {
.name = "pcm179x",
.of_match_table = of_match_ptr(pcm179x_of_match),
},
.id_table = pcm179x_spi_ids,
.probe = pcm179x_spi_probe,
};
module_spi_driver(pcm179x_spi_driver);
MODULE_DESCRIPTION("ASoC PCM179X SPI driver");
MODULE_AUTHOR("Michael Trimarchi <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/pcm179x-spi.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
//
// Copyright 2019-2022 Cirrus Logic, Inc.
//
// Author: James Schulman <[email protected]>
#include <linux/module.h>
#include <linux/regmap.h>
#include "cs35l45.h"
static const struct reg_sequence cs35l45_patch[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x00000044, 0x00000055 },
{ 0x00000044, 0x000000AA },
{ 0x00006480, 0x0830500A },
{ 0x00007C60, 0x1000850B },
{ CS35L45_BOOST_OV_CFG, 0x007000D0 },
{ CS35L45_LDPM_CONFIG, 0x0001B636 },
{ 0x00002C08, 0x00000009 },
{ 0x00006850, 0x0A30FFC4 },
{ 0x00003820, 0x00040100 },
{ 0x00003824, 0x00000000 },
{ 0x00007CFC, 0x62870004 },
{ 0x00007C60, 0x1001850B },
{ 0x00000040, 0x00000000 },
{ 0x00000044, 0x00000000 },
{ CS35L45_BOOST_CCM_CFG, 0xF0000003 },
{ CS35L45_BOOST_DCM_CFG, 0x08710220 },
{ CS35L45_ERROR_RELEASE, 0x00200000 },
};
int cs35l45_apply_patch(struct cs35l45_private *cs35l45)
{
return regmap_register_patch(cs35l45->regmap, cs35l45_patch,
ARRAY_SIZE(cs35l45_patch));
}
EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
static const struct reg_default cs35l45_defaults[] = {
{ CS35L45_BLOCK_ENABLES, 0x00003323 },
{ CS35L45_BLOCK_ENABLES2, 0x00000010 },
{ CS35L45_SYNC_GPIO1, 0x00000007 },
{ CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
{ CS35L45_GPIO3, 0x00000005 },
{ CS35L45_PWRMGT_CTL, 0x00000000 },
{ CS35L45_WAKESRC_CTL, 0x00000008 },
{ CS35L45_WKI2C_CTL, 0x00000030 },
{ CS35L45_REFCLK_INPUT, 0x00000510 },
{ CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
{ CS35L45_ASP_ENABLES1, 0x00000000 },
{ CS35L45_ASP_CONTROL1, 0x00000028 },
{ CS35L45_ASP_CONTROL2, 0x18180200 },
{ CS35L45_ASP_CONTROL3, 0x00000002 },
{ CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
{ CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },
{ CS35L45_ASP_FRAME_CONTROL5, 0x00000100 },
{ CS35L45_ASP_DATA_CONTROL1, 0x00000018 },
{ CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
{ CS35L45_DACPCM1_INPUT, 0x00000008 },
{ CS35L45_ASPTX1_INPUT, 0x00000018 },
{ CS35L45_ASPTX2_INPUT, 0x00000019 },
{ CS35L45_ASPTX3_INPUT, 0x00000020 },
{ CS35L45_ASPTX4_INPUT, 0x00000028 },
{ CS35L45_ASPTX5_INPUT, 0x00000048 },
{ CS35L45_DSP1_RX1_RATE, 0x00000001 },
{ CS35L45_DSP1_RX2_RATE, 0x00000001 },
{ CS35L45_DSP1_RX3_RATE, 0x00000001 },
{ CS35L45_DSP1_RX4_RATE, 0x00000001 },
{ CS35L45_DSP1_RX5_RATE, 0x00000001 },
{ CS35L45_DSP1_RX6_RATE, 0x00000001 },
{ CS35L45_DSP1_RX7_RATE, 0x00000001 },
{ CS35L45_DSP1_RX8_RATE, 0x00000001 },
{ CS35L45_DSP1_TX1_RATE, 0x00000001 },
{ CS35L45_DSP1_TX2_RATE, 0x00000001 },
{ CS35L45_DSP1_TX3_RATE, 0x00000001 },
{ CS35L45_DSP1_TX4_RATE, 0x00000001 },
{ CS35L45_DSP1_TX5_RATE, 0x00000001 },
{ CS35L45_DSP1_TX6_RATE, 0x00000001 },
{ CS35L45_DSP1_TX7_RATE, 0x00000001 },
{ CS35L45_DSP1_TX8_RATE, 0x00000001 },
{ CS35L45_DSP1RX1_INPUT, 0x00000008 },
{ CS35L45_DSP1RX2_INPUT, 0x00000009 },
{ CS35L45_DSP1RX3_INPUT, 0x00000018 },
{ CS35L45_DSP1RX4_INPUT, 0x00000019 },
{ CS35L45_DSP1RX5_INPUT, 0x00000020 },
{ CS35L45_DSP1RX6_INPUT, 0x00000028 },
{ CS35L45_DSP1RX7_INPUT, 0x0000003A },
{ CS35L45_DSP1RX8_INPUT, 0x00000028 },
{ CS35L45_AMP_PCM_CONTROL, 0x00100000 },
{ CS35L45_IRQ1_CFG, 0x00000000 },
{ CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
{ CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
{ CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
{ CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
{ CS35L45_IRQ1_MASK_5, 0x0EF80000 },
{ CS35L45_IRQ1_MASK_6, 0x00000000 },
{ CS35L45_IRQ1_MASK_7, 0xFFFFFF78 },
{ CS35L45_IRQ1_MASK_8, 0x00003FFF },
{ CS35L45_IRQ1_MASK_9, 0x00000000 },
{ CS35L45_IRQ1_MASK_10, 0x00000000 },
{ CS35L45_IRQ1_MASK_11, 0x00000000 },
{ CS35L45_IRQ1_MASK_12, 0x00000000 },
{ CS35L45_IRQ1_MASK_13, 0x00000000 },
{ CS35L45_IRQ1_MASK_14, 0x00000001 },
{ CS35L45_IRQ1_MASK_15, 0x00000000 },
{ CS35L45_IRQ1_MASK_16, 0x00000000 },
{ CS35L45_IRQ1_MASK_17, 0x00000000 },
{ CS35L45_IRQ1_MASK_18, 0x3FE5D0FF },
{ CS35L45_GPIO1_CTRL1, 0x81000001 },
{ CS35L45_GPIO2_CTRL1, 0x81000001 },
{ CS35L45_GPIO3_CTRL1, 0x81000001 },
};
static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L45_DEVID ... CS35L45_OTPID:
case CS35L45_SFT_RESET:
case CS35L45_GLOBAL_ENABLES:
case CS35L45_BLOCK_ENABLES:
case CS35L45_BLOCK_ENABLES2:
case CS35L45_ERROR_RELEASE:
case CS35L45_SYNC_GPIO1:
case CS35L45_INTB_GPIO2_MCLK_REF:
case CS35L45_GPIO3:
case CS35L45_PWRMGT_CTL:
case CS35L45_WAKESRC_CTL:
case CS35L45_WKI2C_CTL:
case CS35L45_PWRMGT_STS:
case CS35L45_REFCLK_INPUT:
case CS35L45_GLOBAL_SAMPLE_RATE:
case CS35L45_ASP_ENABLES1:
case CS35L45_ASP_CONTROL1:
case CS35L45_ASP_CONTROL2:
case CS35L45_ASP_CONTROL3:
case CS35L45_ASP_FRAME_CONTROL1:
case CS35L45_ASP_FRAME_CONTROL2:
case CS35L45_ASP_FRAME_CONTROL5:
case CS35L45_ASP_DATA_CONTROL1:
case CS35L45_ASP_DATA_CONTROL5:
case CS35L45_DACPCM1_INPUT:
case CS35L45_ASPTX1_INPUT:
case CS35L45_ASPTX2_INPUT:
case CS35L45_ASPTX3_INPUT:
case CS35L45_ASPTX4_INPUT:
case CS35L45_ASPTX5_INPUT:
case CS35L45_DSP1RX1_INPUT:
case CS35L45_DSP1RX2_INPUT:
case CS35L45_DSP1RX3_INPUT:
case CS35L45_DSP1RX4_INPUT:
case CS35L45_DSP1RX5_INPUT:
case CS35L45_DSP1RX6_INPUT:
case CS35L45_DSP1RX7_INPUT:
case CS35L45_DSP1RX8_INPUT:
case CS35L45_AMP_PCM_CONTROL:
case CS35L45_AMP_PCM_HPF_TST:
case CS35L45_IRQ1_CFG:
case CS35L45_IRQ1_STATUS:
case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
case CS35L45_GPIO_STATUS1:
case CS35L45_GPIO1_CTRL1:
case CS35L45_GPIO2_CTRL1:
case CS35L45_GPIO3_CTRL1:
case CS35L45_DSP_MBOX_1:
case CS35L45_DSP_MBOX_2:
case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
case CS35L45_DSP1_SYS_ID:
case CS35L45_DSP1_CLOCK_FREQ:
case CS35L45_DSP1_RX1_RATE:
case CS35L45_DSP1_RX2_RATE:
case CS35L45_DSP1_RX3_RATE:
case CS35L45_DSP1_RX4_RATE:
case CS35L45_DSP1_RX5_RATE:
case CS35L45_DSP1_RX6_RATE:
case CS35L45_DSP1_RX7_RATE:
case CS35L45_DSP1_RX8_RATE:
case CS35L45_DSP1_TX1_RATE:
case CS35L45_DSP1_TX2_RATE:
case CS35L45_DSP1_TX3_RATE:
case CS35L45_DSP1_TX4_RATE:
case CS35L45_DSP1_TX5_RATE:
case CS35L45_DSP1_TX6_RATE:
case CS35L45_DSP1_TX7_RATE:
case CS35L45_DSP1_TX8_RATE:
case CS35L45_DSP1_SCRATCH1:
case CS35L45_DSP1_SCRATCH2:
case CS35L45_DSP1_SCRATCH3:
case CS35L45_DSP1_SCRATCH4:
case CS35L45_DSP1_CCM_CORE_CONTROL:
case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
return true;
default:
return false;
}
}
static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L45_DEVID ... CS35L45_OTPID:
case CS35L45_SFT_RESET:
case CS35L45_GLOBAL_ENABLES:
case CS35L45_ERROR_RELEASE:
case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
case CS35L45_PWRMGT_STS:
case CS35L45_IRQ1_STATUS:
case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
case CS35L45_GPIO_STATUS1:
case CS35L45_DSP_MBOX_1:
case CS35L45_DSP_MBOX_2:
case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
case CS35L45_DSP1_SYS_ID:
case CS35L45_DSP1_CLOCK_FREQ:
case CS35L45_DSP1_SCRATCH1:
case CS35L45_DSP1_SCRATCH2:
case CS35L45_DSP1_SCRATCH3:
case CS35L45_DSP1_SCRATCH4:
case CS35L45_DSP1_CCM_CORE_CONTROL:
case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
return true;
default:
return false;
}
}
const struct regmap_config cs35l45_i2c_regmap = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L45_LASTREG,
.reg_defaults = cs35l45_defaults,
.num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
.volatile_reg = cs35l45_volatile_reg,
.readable_reg = cs35l45_readable_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
const struct regmap_config cs35l45_spi_regmap = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = 4,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L45_LASTREG,
.reg_defaults = cs35l45_defaults,
.num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
.volatile_reg = cs35l45_volatile_reg,
.readable_reg = cs35l45_readable_reg,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
static const struct {
u8 cfg_id;
u32 freq;
} cs35l45_pll_refclk_freq[] = {
{ 0x0C, 128000 },
{ 0x0F, 256000 },
{ 0x11, 384000 },
{ 0x12, 512000 },
{ 0x15, 768000 },
{ 0x17, 1024000 },
{ 0x19, 1411200 },
{ 0x1B, 1536000 },
{ 0x1C, 2116800 },
{ 0x1D, 2048000 },
{ 0x1E, 2304000 },
{ 0x1F, 2822400 },
{ 0x21, 3072000 },
{ 0x23, 4233600 },
{ 0x24, 4096000 },
{ 0x25, 4608000 },
{ 0x26, 5644800 },
{ 0x27, 6000000 },
{ 0x28, 6144000 },
{ 0x29, 6350400 },
{ 0x2A, 6912000 },
{ 0x2D, 7526400 },
{ 0x2E, 8467200 },
{ 0x2F, 8192000 },
{ 0x30, 9216000 },
{ 0x31, 11289600 },
{ 0x33, 12288000 },
{ 0x37, 16934400 },
{ 0x38, 18432000 },
{ 0x39, 22579200 },
{ 0x3B, 24576000 },
};
unsigned int cs35l45_get_clk_freq_id(unsigned int freq)
{
int i;
if (freq == 0)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) {
if (cs35l45_pll_refclk_freq[i].freq == freq)
return cs35l45_pll_refclk_freq[i].cfg_id;
}
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45);
| linux-master | sound/soc/codecs/cs35l45-tables.c |
// SPDX-License-Identifier: GPL-2.0-only OR MIT
//
// Analog Devices' SSM3515 audio amp driver
//
// Copyright (C) The Asahi Linux Contributors
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define SSM3515_PWR 0x00
#define SSM3515_PWR_APWDN_EN BIT(7)
#define SSM3515_PWR_BSNS_PWDN BIT(6)
#define SSM3515_PWR_S_RST BIT(1)
#define SSM3515_PWR_SPWDN BIT(0)
#define SSM3515_GEC 0x01
#define SSM3515_GEC_EDGE BIT(4)
#define SSM3515_GEC_EDGE_SHIFT 4
#define SSM3515_GEC_ANA_GAIN GENMASK(1, 0)
#define SSM3515_DAC 0x02
#define SSM3515_DAC_HV BIT(7)
#define SSM3515_DAC_MUTE BIT(6)
#define SSM3515_DAC_HPF BIT(5)
#define SSM3515_DAC_LPM BIT(4)
#define SSM3515_DAC_FS GENMASK(2, 0)
#define SSM3515_DAC_VOL 0x03
#define SSM3515_SAI1 0x04
#define SSM3515_SAI1_DAC_POL BIT(7)
#define SSM3515_SAI1_BCLK_POL BIT(6)
#define SSM3515_SAI1_TDM_BCLKS GENMASK(5, 3)
#define SSM3515_SAI1_FSYNC_MODE BIT(2)
#define SSM3515_SAI1_SDATA_FMT BIT(1)
#define SSM3515_SAI1_SAI_MODE BIT(0)
#define SSM3515_SAI2 0x05
#define SSM3515_SAI2_DATA_WIDTH BIT(7)
#define SSM3515_SAI2_AUTO_SLOT BIT(4)
#define SSM3515_SAI2_TDM_SLOT GENMASK(3, 0)
#define SSM3515_VBAT_OUT 0x06
#define SSM3515_STATUS 0x0a
#define SSM3515_STATUS_UVLO_REG BIT(6)
#define SSM3515_STATUS_LIM_EG BIT(5)
#define SSM3515_STATUS_CLIP BIT(4)
#define SSM3515_STATUS_AMP_OC BIT(3)
#define SSM3515_STATUS_OTF BIT(2)
#define SSM3515_STATUS_OTW BIT(1)
#define SSM3515_STATUS_BAT_WARN BIT(0)
static bool ssm3515_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SSM3515_STATUS:
case SSM3515_VBAT_OUT:
return true;
default:
return false;
}
}
static const struct reg_default ssm3515_reg_defaults[] = {
{ SSM3515_PWR, 0x81 },
{ SSM3515_GEC, 0x01 },
{ SSM3515_DAC, 0x32 },
{ SSM3515_DAC_VOL, 0x40 },
{ SSM3515_SAI1, 0x11 },
{ SSM3515_SAI2, 0x00 },
};
static const struct regmap_config ssm3515_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = ssm3515_volatile_reg,
.max_register = 0xb,
.reg_defaults = ssm3515_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ssm3515_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
struct ssm3515_data {
struct device *dev;
struct regmap *regmap;
};
// The specced range is -71.25...24.00 dB with step size of 0.375 dB,
// and a mute item below that. This is represented by -71.62...24.00 dB
// with the mute item mapped onto the low end.
static DECLARE_TLV_DB_MINMAX_MUTE(ssm3515_dac_volume, -7162, 2400);
static const char * const ssm3515_ana_gain_text[] = {
"8.4 V Span", "12.6 V Span", "14 V Span", "15 V Span",
};
static SOC_ENUM_SINGLE_DECL(ssm3515_ana_gain_enum, SSM3515_GEC,
__bf_shf(SSM3515_GEC_ANA_GAIN),
ssm3515_ana_gain_text);
static const struct snd_kcontrol_new ssm3515_snd_controls[] = {
SOC_SINGLE_TLV("DAC Playback Volume", SSM3515_DAC_VOL,
0, 255, 1, ssm3515_dac_volume),
SOC_SINGLE("Low EMI Mode Switch", SSM3515_GEC,
__bf_shf(SSM3515_GEC_EDGE), 1, 0),
SOC_SINGLE("Soft Volume Ramping Switch", SSM3515_DAC,
__bf_shf(SSM3515_DAC_HV), 1, 1),
SOC_SINGLE("HPF Switch", SSM3515_DAC,
__bf_shf(SSM3515_DAC_HPF), 1, 0),
SOC_SINGLE("DAC Invert Switch", SSM3515_SAI1,
__bf_shf(SSM3515_SAI1_DAC_POL), 1, 0),
SOC_ENUM("DAC Analog Gain Select", ssm3515_ana_gain_enum),
};
static void ssm3515_read_faults(struct snd_soc_component *component)
{
int ret;
ret = snd_soc_component_read(component, SSM3515_STATUS);
if (ret <= 0) {
/*
* If the read was erroneous, ASoC core has printed a message,
* and that's all that's appropriate in handling the error here.
*/
return;
}
dev_err(component->dev, "device reports:%s%s%s%s%s%s%s\n",
FIELD_GET(SSM3515_STATUS_UVLO_REG, ret) ? " voltage regulator fault" : "",
FIELD_GET(SSM3515_STATUS_LIM_EG, ret) ? " limiter engaged" : "",
FIELD_GET(SSM3515_STATUS_CLIP, ret) ? " clipping detected" : "",
FIELD_GET(SSM3515_STATUS_AMP_OC, ret) ? " amp over-current fault" : "",
FIELD_GET(SSM3515_STATUS_OTF, ret) ? " overtemperature fault" : "",
FIELD_GET(SSM3515_STATUS_OTW, ret) ? " overtemperature warning" : "",
FIELD_GET(SSM3515_STATUS_BAT_WARN, ret) ? " bat voltage low warning" : "");
}
static int ssm3515_probe(struct snd_soc_component *component)
{
int ret;
/* Start out muted */
ret = snd_soc_component_update_bits(component, SSM3515_DAC,
SSM3515_DAC_MUTE, SSM3515_DAC_MUTE);
if (ret < 0)
return ret;
/* Disable the 'master power-down' */
ret = snd_soc_component_update_bits(component, SSM3515_PWR,
SSM3515_PWR_SPWDN, 0);
if (ret < 0)
return ret;
return 0;
}
static int ssm3515_mute(struct snd_soc_dai *dai, int mute, int direction)
{
int ret;
ret = snd_soc_component_update_bits(dai->component,
SSM3515_DAC,
SSM3515_DAC_MUTE,
FIELD_PREP(SSM3515_DAC_MUTE, mute));
if (ret < 0)
return ret;
return 0;
}
static int ssm3515_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int ret, rateval;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16:
case SNDRV_PCM_FORMAT_S24:
ret = snd_soc_component_update_bits(component,
SSM3515_SAI2, SSM3515_SAI2_DATA_WIDTH,
FIELD_PREP(SSM3515_SAI2_DATA_WIDTH,
params_width(params) == 16));
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
switch (params_rate(params)) {
case 8000 ... 12000:
rateval = 0;
break;
case 16000 ... 24000:
rateval = 1;
break;
case 32000 ... 48000:
rateval = 2;
break;
case 64000 ... 96000:
rateval = 3;
break;
case 128000 ... 192000:
rateval = 4;
break;
case 48001 ... 63999: /* this is ...72000 but overlaps */
rateval = 5;
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component,
SSM3515_DAC, SSM3515_DAC_FS,
FIELD_PREP(SSM3515_DAC_FS, rateval));
if (ret < 0)
return ret;
return 0;
}
static int ssm3515_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
bool fpol_inv = false; /* non-inverted: frame starts with low-to-high FSYNC */
int ret;
u8 sai1 = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
case SND_SOC_DAIFMT_IB_IF:
sai1 |= SSM3515_SAI1_BCLK_POL;
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
fpol_inv = 1;
sai1 &= ~SSM3515_SAI1_SDATA_FMT; /* 1 bit start delay */
break;
case SND_SOC_DAIFMT_LEFT_J:
fpol_inv = 0;
sai1 |= SSM3515_SAI1_SDATA_FMT; /* no start delay */
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
case SND_SOC_DAIFMT_IB_IF:
fpol_inv ^= 1;
break;
}
/* Set the serial input to 'TDM mode' */
sai1 |= SSM3515_SAI1_SAI_MODE;
if (fpol_inv) {
/*
* We configure the codec in a 'TDM mode', in which the
* FSYNC_MODE bit of SAI1 is supposed to select between
* what the datasheet calls 'Pulsed FSYNC mode' and '50%
* FSYNC mode'.
*
* Experiments suggest that this bit in fact simply selects
* the FSYNC polarity, so go with that.
*/
sai1 |= SSM3515_SAI1_FSYNC_MODE;
}
ret = snd_soc_component_update_bits(component, SSM3515_SAI1,
SSM3515_SAI1_BCLK_POL | SSM3515_SAI1_SDATA_FMT |
SSM3515_SAI1_SAI_MODE | SSM3515_SAI1_FSYNC_MODE, sai1);
if (ret < 0)
return ret;
return 0;
}
static int ssm3515_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
int slot, tdm_bclks_val, ret;
if (tx_mask == 0 || rx_mask != 0)
return -EINVAL;
slot = __ffs(tx_mask);
if (tx_mask & ~BIT(slot))
return -EINVAL;
switch (slot_width) {
case 16:
tdm_bclks_val = 0;
break;
case 24:
tdm_bclks_val = 1;
break;
case 32:
tdm_bclks_val = 2;
break;
case 48:
tdm_bclks_val = 3;
break;
case 64:
tdm_bclks_val = 4;
break;
default:
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, SSM3515_SAI1,
SSM3515_SAI1_TDM_BCLKS,
FIELD_PREP(SSM3515_SAI1_TDM_BCLKS, tdm_bclks_val));
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, SSM3515_SAI2,
SSM3515_SAI2_TDM_SLOT,
FIELD_PREP(SSM3515_SAI2_TDM_SLOT, slot));
if (ret < 0)
return ret;
return 0;
}
static int ssm3515_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
/*
* We don't get live notification of faults, so at least at
* this time, when playback is over, check if we have tripped
* over anything and if so, log it.
*/
ssm3515_read_faults(dai->component);
return 0;
}
static const struct snd_soc_dai_ops ssm3515_dai_ops = {
.mute_stream = ssm3515_mute,
.hw_params = ssm3515_hw_params,
.set_fmt = ssm3515_set_fmt,
.set_tdm_slot = ssm3515_set_tdm_slot,
.hw_free = ssm3515_hw_free,
};
static struct snd_soc_dai_driver ssm3515_dai_driver = {
.name = "SSM3515 SAI",
.id = 0,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &ssm3515_dai_ops,
};
static const struct snd_soc_dapm_widget ssm3515_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route ssm3515_dapm_routes[] = {
{"OUT", NULL, "DAC"},
{"DAC", NULL, "Playback"},
};
static const struct snd_soc_component_driver ssm3515_asoc_component = {
.probe = ssm3515_probe,
.controls = ssm3515_snd_controls,
.num_controls = ARRAY_SIZE(ssm3515_snd_controls),
.dapm_widgets = ssm3515_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ssm3515_dapm_widgets),
.dapm_routes = ssm3515_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ssm3515_dapm_routes),
.endianness = 1,
};
static int ssm3515_i2c_probe(struct i2c_client *client)
{
struct ssm3515_data *data;
int ret;
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->dev = &client->dev;
i2c_set_clientdata(client, data);
data->regmap = devm_regmap_init_i2c(client, &ssm3515_i2c_regmap);
if (IS_ERR(data->regmap))
return dev_err_probe(data->dev, PTR_ERR(data->regmap),
"initializing register map\n");
/* Perform a reset */
ret = regmap_update_bits(data->regmap, SSM3515_PWR,
SSM3515_PWR_S_RST, SSM3515_PWR_S_RST);
if (ret < 0)
return dev_err_probe(data->dev, ret,
"performing software reset\n");
regmap_reinit_cache(data->regmap, &ssm3515_i2c_regmap);
return devm_snd_soc_register_component(data->dev,
&ssm3515_asoc_component,
&ssm3515_dai_driver, 1);
}
static const struct of_device_id ssm3515_of_match[] = {
{ .compatible = "adi,ssm3515" },
{}
};
MODULE_DEVICE_TABLE(of, ssm3515_of_match);
static struct i2c_driver ssm3515_i2c_driver = {
.driver = {
.name = "ssm3515",
.of_match_table = ssm3515_of_match,
},
.probe = ssm3515_i2c_probe,
};
module_i2c_driver(ssm3515_i2c_driver);
MODULE_AUTHOR("Martin Povišer <[email protected]>");
MODULE_DESCRIPTION("ASoC SSM3515 audio amp driver");
MODULE_LICENSE("Dual MIT/GPL");
| linux-master | sound/soc/codecs/ssm3515.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* da7219.c - DA7219 ALSA SoC Codec Driver
*
* Copyright (c) 2015 Dialog Semiconductor
*
* Author: Adam Thomson <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/pm.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include <sound/da7219.h>
#include "da7219.h"
#include "da7219-aad.h"
/*
* TLVs and Enums
*/
/* Input TLVs */
static const DECLARE_TLV_DB_SCALE(da7219_mic_gain_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7219_mixin_gain_tlv, -450, 150, 0);
static const DECLARE_TLV_DB_SCALE(da7219_adc_dig_gain_tlv, -8325, 75, 0);
static const DECLARE_TLV_DB_SCALE(da7219_alc_threshold_tlv, -9450, 150, 0);
static const DECLARE_TLV_DB_SCALE(da7219_alc_gain_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7219_alc_ana_gain_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7219_sidetone_gain_tlv, -4200, 300, 0);
static const DECLARE_TLV_DB_SCALE(da7219_tonegen_gain_tlv, -4500, 300, 0);
/* Output TLVs */
static const DECLARE_TLV_DB_SCALE(da7219_dac_eq_band_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_RANGE(da7219_dac_dig_gain_tlv,
0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* -77.25dB to 12dB */
0x08, 0x7f, TLV_DB_SCALE_ITEM(-7725, 75, 0)
);
static const DECLARE_TLV_DB_SCALE(da7219_dac_ng_threshold_tlv, -10200, 600, 0);
static const DECLARE_TLV_DB_SCALE(da7219_hp_gain_tlv, -5700, 100, 0);
/* Input Enums */
static const char * const da7219_alc_attack_rate_txt[] = {
"7.33/fs", "14.66/fs", "29.32/fs", "58.64/fs", "117.3/fs", "234.6/fs",
"469.1/fs", "938.2/fs", "1876/fs", "3753/fs", "7506/fs", "15012/fs",
"30024/fs"
};
static const struct soc_enum da7219_alc_attack_rate =
SOC_ENUM_SINGLE(DA7219_ALC_CTRL2, DA7219_ALC_ATTACK_SHIFT,
DA7219_ALC_ATTACK_MAX, da7219_alc_attack_rate_txt);
static const char * const da7219_alc_release_rate_txt[] = {
"28.66/fs", "57.33/fs", "114.6/fs", "229.3/fs", "458.6/fs", "917.1/fs",
"1834/fs", "3668/fs", "7337/fs", "14674/fs", "29348/fs"
};
static const struct soc_enum da7219_alc_release_rate =
SOC_ENUM_SINGLE(DA7219_ALC_CTRL2, DA7219_ALC_RELEASE_SHIFT,
DA7219_ALC_RELEASE_MAX, da7219_alc_release_rate_txt);
static const char * const da7219_alc_hold_time_txt[] = {
"62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
"7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
"253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
};
static const struct soc_enum da7219_alc_hold_time =
SOC_ENUM_SINGLE(DA7219_ALC_CTRL3, DA7219_ALC_HOLD_SHIFT,
DA7219_ALC_HOLD_MAX, da7219_alc_hold_time_txt);
static const char * const da7219_alc_env_rate_txt[] = {
"1/4", "1/16", "1/256", "1/65536"
};
static const struct soc_enum da7219_alc_env_attack_rate =
SOC_ENUM_SINGLE(DA7219_ALC_CTRL3, DA7219_ALC_INTEG_ATTACK_SHIFT,
DA7219_ALC_INTEG_MAX, da7219_alc_env_rate_txt);
static const struct soc_enum da7219_alc_env_release_rate =
SOC_ENUM_SINGLE(DA7219_ALC_CTRL3, DA7219_ALC_INTEG_RELEASE_SHIFT,
DA7219_ALC_INTEG_MAX, da7219_alc_env_rate_txt);
static const char * const da7219_alc_anticlip_step_txt[] = {
"0.034dB/fs", "0.068dB/fs", "0.136dB/fs", "0.272dB/fs"
};
static const struct soc_enum da7219_alc_anticlip_step =
SOC_ENUM_SINGLE(DA7219_ALC_ANTICLIP_CTRL,
DA7219_ALC_ANTICLIP_STEP_SHIFT,
DA7219_ALC_ANTICLIP_STEP_MAX,
da7219_alc_anticlip_step_txt);
/* Input/Output Enums */
static const char * const da7219_gain_ramp_rate_txt[] = {
"Nominal Rate * 8", "Nominal Rate", "Nominal Rate / 8",
"Nominal Rate / 16"
};
static const struct soc_enum da7219_gain_ramp_rate =
SOC_ENUM_SINGLE(DA7219_GAIN_RAMP_CTRL, DA7219_GAIN_RAMP_RATE_SHIFT,
DA7219_GAIN_RAMP_RATE_MAX, da7219_gain_ramp_rate_txt);
static const char * const da7219_hpf_mode_txt[] = {
"Disabled", "Audio", "Voice"
};
static const unsigned int da7219_hpf_mode_val[] = {
DA7219_HPF_DISABLED, DA7219_HPF_AUDIO_EN, DA7219_HPF_VOICE_EN,
};
static const struct soc_enum da7219_adc_hpf_mode =
SOC_VALUE_ENUM_SINGLE(DA7219_ADC_FILTERS1, DA7219_HPF_MODE_SHIFT,
DA7219_HPF_MODE_MASK, DA7219_HPF_MODE_MAX,
da7219_hpf_mode_txt, da7219_hpf_mode_val);
static const struct soc_enum da7219_dac_hpf_mode =
SOC_VALUE_ENUM_SINGLE(DA7219_DAC_FILTERS1, DA7219_HPF_MODE_SHIFT,
DA7219_HPF_MODE_MASK, DA7219_HPF_MODE_MAX,
da7219_hpf_mode_txt, da7219_hpf_mode_val);
static const char * const da7219_audio_hpf_corner_txt[] = {
"2Hz", "4Hz", "8Hz", "16Hz"
};
static const struct soc_enum da7219_adc_audio_hpf_corner =
SOC_ENUM_SINGLE(DA7219_ADC_FILTERS1,
DA7219_ADC_AUDIO_HPF_CORNER_SHIFT,
DA7219_AUDIO_HPF_CORNER_MAX,
da7219_audio_hpf_corner_txt);
static const struct soc_enum da7219_dac_audio_hpf_corner =
SOC_ENUM_SINGLE(DA7219_DAC_FILTERS1,
DA7219_DAC_AUDIO_HPF_CORNER_SHIFT,
DA7219_AUDIO_HPF_CORNER_MAX,
da7219_audio_hpf_corner_txt);
static const char * const da7219_voice_hpf_corner_txt[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
};
static const struct soc_enum da7219_adc_voice_hpf_corner =
SOC_ENUM_SINGLE(DA7219_ADC_FILTERS1,
DA7219_ADC_VOICE_HPF_CORNER_SHIFT,
DA7219_VOICE_HPF_CORNER_MAX,
da7219_voice_hpf_corner_txt);
static const struct soc_enum da7219_dac_voice_hpf_corner =
SOC_ENUM_SINGLE(DA7219_DAC_FILTERS1,
DA7219_DAC_VOICE_HPF_CORNER_SHIFT,
DA7219_VOICE_HPF_CORNER_MAX,
da7219_voice_hpf_corner_txt);
static const char * const da7219_tonegen_dtmf_key_txt[] = {
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "A", "B", "C", "D",
"*", "#"
};
static const struct soc_enum da7219_tonegen_dtmf_key =
SOC_ENUM_SINGLE(DA7219_TONE_GEN_CFG1, DA7219_DTMF_REG_SHIFT,
DA7219_DTMF_REG_MAX, da7219_tonegen_dtmf_key_txt);
static const char * const da7219_tonegen_swg_sel_txt[] = {
"Sum", "SWG1", "SWG2", "SWG1_1-Cos"
};
static const struct soc_enum da7219_tonegen_swg_sel =
SOC_ENUM_SINGLE(DA7219_TONE_GEN_CFG2, DA7219_SWG_SEL_SHIFT,
DA7219_SWG_SEL_MAX, da7219_tonegen_swg_sel_txt);
/* Output Enums */
static const char * const da7219_dac_softmute_rate_txt[] = {
"1 Sample", "2 Samples", "4 Samples", "8 Samples", "16 Samples",
"32 Samples", "64 Samples"
};
static const struct soc_enum da7219_dac_softmute_rate =
SOC_ENUM_SINGLE(DA7219_DAC_FILTERS5, DA7219_DAC_SOFTMUTE_RATE_SHIFT,
DA7219_DAC_SOFTMUTE_RATE_MAX,
da7219_dac_softmute_rate_txt);
static const char * const da7219_dac_ng_setup_time_txt[] = {
"256 Samples", "512 Samples", "1024 Samples", "2048 Samples"
};
static const struct soc_enum da7219_dac_ng_setup_time =
SOC_ENUM_SINGLE(DA7219_DAC_NG_SETUP_TIME,
DA7219_DAC_NG_SETUP_TIME_SHIFT,
DA7219_DAC_NG_SETUP_TIME_MAX,
da7219_dac_ng_setup_time_txt);
static const char * const da7219_dac_ng_rampup_txt[] = {
"0.22ms/dB", "0.0138ms/dB"
};
static const struct soc_enum da7219_dac_ng_rampup_rate =
SOC_ENUM_SINGLE(DA7219_DAC_NG_SETUP_TIME,
DA7219_DAC_NG_RAMPUP_RATE_SHIFT,
DA7219_DAC_NG_RAMP_RATE_MAX,
da7219_dac_ng_rampup_txt);
static const char * const da7219_dac_ng_rampdown_txt[] = {
"0.88ms/dB", "14.08ms/dB"
};
static const struct soc_enum da7219_dac_ng_rampdown_rate =
SOC_ENUM_SINGLE(DA7219_DAC_NG_SETUP_TIME,
DA7219_DAC_NG_RAMPDN_RATE_SHIFT,
DA7219_DAC_NG_RAMP_RATE_MAX,
da7219_dac_ng_rampdown_txt);
static const char * const da7219_cp_track_mode_txt[] = {
"Largest Volume", "DAC Volume", "Signal Magnitude"
};
static const unsigned int da7219_cp_track_mode_val[] = {
DA7219_CP_MCHANGE_LARGEST_VOL, DA7219_CP_MCHANGE_DAC_VOL,
DA7219_CP_MCHANGE_SIG_MAG
};
static const struct soc_enum da7219_cp_track_mode =
SOC_VALUE_ENUM_SINGLE(DA7219_CP_CTRL, DA7219_CP_MCHANGE_SHIFT,
DA7219_CP_MCHANGE_REL_MASK, DA7219_CP_MCHANGE_MAX,
da7219_cp_track_mode_txt,
da7219_cp_track_mode_val);
/*
* Control Functions
*/
/* Locked Kcontrol calls */
static int da7219_volsw_locked_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&da7219->ctrl_lock);
ret = snd_soc_get_volsw(kcontrol, ucontrol);
mutex_unlock(&da7219->ctrl_lock);
return ret;
}
static int da7219_volsw_locked_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&da7219->ctrl_lock);
ret = snd_soc_put_volsw(kcontrol, ucontrol);
mutex_unlock(&da7219->ctrl_lock);
return ret;
}
static int da7219_enum_locked_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&da7219->ctrl_lock);
ret = snd_soc_get_enum_double(kcontrol, ucontrol);
mutex_unlock(&da7219->ctrl_lock);
return ret;
}
static int da7219_enum_locked_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&da7219->ctrl_lock);
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
mutex_unlock(&da7219->ctrl_lock);
return ret;
}
/* ALC */
static void da7219_alc_calib(struct snd_soc_component *component)
{
u8 mic_ctrl, mixin_ctrl, adc_ctrl, calib_ctrl;
/* Save current state of mic control register */
mic_ctrl = snd_soc_component_read(component, DA7219_MIC_1_CTRL);
/* Save current state of input mixer control register */
mixin_ctrl = snd_soc_component_read(component, DA7219_MIXIN_L_CTRL);
/* Save current state of input ADC control register */
adc_ctrl = snd_soc_component_read(component, DA7219_ADC_L_CTRL);
/* Enable then Mute MIC PGAs */
snd_soc_component_update_bits(component, DA7219_MIC_1_CTRL, DA7219_MIC_1_AMP_EN_MASK,
DA7219_MIC_1_AMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_MIC_1_CTRL,
DA7219_MIC_1_AMP_MUTE_EN_MASK,
DA7219_MIC_1_AMP_MUTE_EN_MASK);
/* Enable input mixers unmuted */
snd_soc_component_update_bits(component, DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_AMP_EN_MASK |
DA7219_MIXIN_L_AMP_MUTE_EN_MASK,
DA7219_MIXIN_L_AMP_EN_MASK);
/* Enable input filters unmuted */
snd_soc_component_update_bits(component, DA7219_ADC_L_CTRL,
DA7219_ADC_L_MUTE_EN_MASK | DA7219_ADC_L_EN_MASK,
DA7219_ADC_L_EN_MASK);
/* Perform auto calibration */
snd_soc_component_update_bits(component, DA7219_ALC_CTRL1,
DA7219_ALC_AUTO_CALIB_EN_MASK,
DA7219_ALC_AUTO_CALIB_EN_MASK);
do {
calib_ctrl = snd_soc_component_read(component, DA7219_ALC_CTRL1);
} while (calib_ctrl & DA7219_ALC_AUTO_CALIB_EN_MASK);
/* If auto calibration fails, disable DC offset, hybrid ALC */
if (calib_ctrl & DA7219_ALC_CALIB_OVERFLOW_MASK) {
dev_warn(component->dev,
"ALC auto calibration failed with overflow\n");
snd_soc_component_update_bits(component, DA7219_ALC_CTRL1,
DA7219_ALC_OFFSET_EN_MASK |
DA7219_ALC_SYNC_MODE_MASK, 0);
} else {
/* Enable DC offset cancellation, hybrid mode */
snd_soc_component_update_bits(component, DA7219_ALC_CTRL1,
DA7219_ALC_OFFSET_EN_MASK |
DA7219_ALC_SYNC_MODE_MASK,
DA7219_ALC_OFFSET_EN_MASK |
DA7219_ALC_SYNC_MODE_MASK);
}
/* Restore input filter control register to original state */
snd_soc_component_write(component, DA7219_ADC_L_CTRL, adc_ctrl);
/* Restore input mixer control registers to original state */
snd_soc_component_write(component, DA7219_MIXIN_L_CTRL, mixin_ctrl);
/* Restore MIC control registers to original states */
snd_soc_component_write(component, DA7219_MIC_1_CTRL, mic_ctrl);
}
static int da7219_mixin_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
/*
* If ALC in operation and value of control has been updated,
* make sure calibrated offsets are updated.
*/
if ((ret == 1) && (da7219->alc_en))
da7219_alc_calib(component);
return ret;
}
static int da7219_alc_sw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
/* Force ALC offset calibration if enabling ALC */
if ((ucontrol->value.integer.value[0]) && (!da7219->alc_en)) {
da7219_alc_calib(component);
da7219->alc_en = true;
} else {
da7219->alc_en = false;
}
return snd_soc_put_volsw(kcontrol, ucontrol);
}
/* ToneGen */
static int da7219_tonegen_freq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mixer_ctrl =
(struct soc_mixer_control *) kcontrol->private_value;
unsigned int reg = mixer_ctrl->reg;
__le16 val;
int ret;
mutex_lock(&da7219->ctrl_lock);
ret = regmap_raw_read(da7219->regmap, reg, &val, sizeof(val));
mutex_unlock(&da7219->ctrl_lock);
if (ret)
return ret;
/*
* Frequency value spans two 8-bit registers, lower then upper byte.
* Therefore we need to convert to host endianness here.
*/
ucontrol->value.integer.value[0] = le16_to_cpu(val);
return 0;
}
static int da7219_tonegen_freq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mixer_ctrl =
(struct soc_mixer_control *) kcontrol->private_value;
unsigned int reg = mixer_ctrl->reg;
__le16 val_new, val_old;
int ret;
/*
* Frequency value spans two 8-bit registers, lower then upper byte.
* Therefore we need to convert to little endian here to align with
* HW registers.
*/
val_new = cpu_to_le16(ucontrol->value.integer.value[0]);
mutex_lock(&da7219->ctrl_lock);
ret = regmap_raw_read(da7219->regmap, reg, &val_old, sizeof(val_old));
if (ret == 0 && (val_old != val_new))
ret = regmap_raw_write(da7219->regmap, reg,
&val_new, sizeof(val_new));
mutex_unlock(&da7219->ctrl_lock);
if (ret < 0)
return ret;
return val_old != val_new;
}
/*
* KControls
*/
static const struct snd_kcontrol_new da7219_snd_controls[] = {
/* Mics */
SOC_SINGLE_TLV("Mic Volume", DA7219_MIC_1_GAIN,
DA7219_MIC_1_AMP_GAIN_SHIFT, DA7219_MIC_1_AMP_GAIN_MAX,
DA7219_NO_INVERT, da7219_mic_gain_tlv),
SOC_SINGLE("Mic Switch", DA7219_MIC_1_CTRL,
DA7219_MIC_1_AMP_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_INVERT),
/* Mixer Input */
SOC_SINGLE_EXT_TLV("Mixin Volume", DA7219_MIXIN_L_GAIN,
DA7219_MIXIN_L_AMP_GAIN_SHIFT,
DA7219_MIXIN_L_AMP_GAIN_MAX, DA7219_NO_INVERT,
snd_soc_get_volsw, da7219_mixin_gain_put,
da7219_mixin_gain_tlv),
SOC_SINGLE("Mixin Switch", DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_AMP_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_INVERT),
SOC_SINGLE("Mixin Gain Ramp Switch", DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_AMP_RAMP_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT),
SOC_SINGLE("Mixin ZC Gain Switch", DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_AMP_ZC_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT),
/* ADC */
SOC_SINGLE_TLV("Capture Digital Volume", DA7219_ADC_L_GAIN,
DA7219_ADC_L_DIGITAL_GAIN_SHIFT,
DA7219_ADC_L_DIGITAL_GAIN_MAX, DA7219_NO_INVERT,
da7219_adc_dig_gain_tlv),
SOC_SINGLE("Capture Digital Switch", DA7219_ADC_L_CTRL,
DA7219_ADC_L_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_INVERT),
SOC_SINGLE("Capture Digital Gain Ramp Switch", DA7219_ADC_L_CTRL,
DA7219_ADC_L_RAMP_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT),
/* ALC */
SOC_ENUM("ALC Attack Rate", da7219_alc_attack_rate),
SOC_ENUM("ALC Release Rate", da7219_alc_release_rate),
SOC_ENUM("ALC Hold Time", da7219_alc_hold_time),
SOC_ENUM("ALC Envelope Attack Rate", da7219_alc_env_attack_rate),
SOC_ENUM("ALC Envelope Release Rate", da7219_alc_env_release_rate),
SOC_SINGLE_TLV("ALC Noise Threshold", DA7219_ALC_NOISE,
DA7219_ALC_NOISE_SHIFT, DA7219_ALC_THRESHOLD_MAX,
DA7219_INVERT, da7219_alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Min Threshold", DA7219_ALC_TARGET_MIN,
DA7219_ALC_THRESHOLD_MIN_SHIFT, DA7219_ALC_THRESHOLD_MAX,
DA7219_INVERT, da7219_alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Threshold", DA7219_ALC_TARGET_MAX,
DA7219_ALC_THRESHOLD_MAX_SHIFT, DA7219_ALC_THRESHOLD_MAX,
DA7219_INVERT, da7219_alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Attenuation", DA7219_ALC_GAIN_LIMITS,
DA7219_ALC_ATTEN_MAX_SHIFT, DA7219_ALC_ATTEN_GAIN_MAX,
DA7219_NO_INVERT, da7219_alc_gain_tlv),
SOC_SINGLE_TLV("ALC Max Volume", DA7219_ALC_GAIN_LIMITS,
DA7219_ALC_GAIN_MAX_SHIFT, DA7219_ALC_ATTEN_GAIN_MAX,
DA7219_NO_INVERT, da7219_alc_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC Min Analog Volume", DA7219_ALC_ANA_GAIN_LIMITS,
DA7219_ALC_ANA_GAIN_MIN_SHIFT,
DA7219_ALC_ANA_GAIN_MIN, DA7219_ALC_ANA_GAIN_MAX,
DA7219_NO_INVERT, da7219_alc_ana_gain_tlv),
SOC_SINGLE_RANGE_TLV("ALC Max Analog Volume", DA7219_ALC_ANA_GAIN_LIMITS,
DA7219_ALC_ANA_GAIN_MAX_SHIFT,
DA7219_ALC_ANA_GAIN_MIN, DA7219_ALC_ANA_GAIN_MAX,
DA7219_NO_INVERT, da7219_alc_ana_gain_tlv),
SOC_ENUM("ALC Anticlip Step", da7219_alc_anticlip_step),
SOC_SINGLE("ALC Anticlip Switch", DA7219_ALC_ANTICLIP_CTRL,
DA7219_ALC_ANTIPCLIP_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT),
SOC_SINGLE_EXT("ALC Switch", DA7219_ALC_CTRL1, DA7219_ALC_EN_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT,
snd_soc_get_volsw, da7219_alc_sw_put),
/* Input High-Pass Filters */
SOC_ENUM("ADC HPF Mode", da7219_adc_hpf_mode),
SOC_ENUM("ADC HPF Corner Audio", da7219_adc_audio_hpf_corner),
SOC_ENUM("ADC HPF Corner Voice", da7219_adc_voice_hpf_corner),
/* Sidetone Filter */
SOC_SINGLE_TLV("Sidetone Volume", DA7219_SIDETONE_GAIN,
DA7219_SIDETONE_GAIN_SHIFT, DA7219_SIDETONE_GAIN_MAX,
DA7219_NO_INVERT, da7219_sidetone_gain_tlv),
SOC_SINGLE("Sidetone Switch", DA7219_SIDETONE_CTRL,
DA7219_SIDETONE_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_INVERT),
/* Tone Generator */
SOC_SINGLE_EXT_TLV("ToneGen Volume", DA7219_TONE_GEN_CFG2,
DA7219_TONE_GEN_GAIN_SHIFT, DA7219_TONE_GEN_GAIN_MAX,
DA7219_NO_INVERT, da7219_volsw_locked_get,
da7219_volsw_locked_put, da7219_tonegen_gain_tlv),
SOC_ENUM_EXT("ToneGen DTMF Key", da7219_tonegen_dtmf_key,
da7219_enum_locked_get, da7219_enum_locked_put),
SOC_SINGLE_EXT("ToneGen DTMF Switch", DA7219_TONE_GEN_CFG1,
DA7219_DTMF_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT, da7219_volsw_locked_get,
da7219_volsw_locked_put),
SOC_ENUM_EXT("ToneGen Sinewave Gen Type", da7219_tonegen_swg_sel,
da7219_enum_locked_get, da7219_enum_locked_put),
SOC_SINGLE_EXT("ToneGen Sinewave1 Freq", DA7219_TONE_GEN_FREQ1_L,
DA7219_FREQ1_L_SHIFT, DA7219_FREQ_MAX, DA7219_NO_INVERT,
da7219_tonegen_freq_get, da7219_tonegen_freq_put),
SOC_SINGLE_EXT("ToneGen Sinewave2 Freq", DA7219_TONE_GEN_FREQ2_L,
DA7219_FREQ2_L_SHIFT, DA7219_FREQ_MAX, DA7219_NO_INVERT,
da7219_tonegen_freq_get, da7219_tonegen_freq_put),
SOC_SINGLE_EXT("ToneGen On Time", DA7219_TONE_GEN_ON_PER,
DA7219_BEEP_ON_PER_SHIFT, DA7219_BEEP_ON_OFF_MAX,
DA7219_NO_INVERT, da7219_volsw_locked_get,
da7219_volsw_locked_put),
SOC_SINGLE("ToneGen Off Time", DA7219_TONE_GEN_OFF_PER,
DA7219_BEEP_OFF_PER_SHIFT, DA7219_BEEP_ON_OFF_MAX,
DA7219_NO_INVERT),
/* Gain ramping */
SOC_ENUM("Gain Ramp Rate", da7219_gain_ramp_rate),
/* DAC High-Pass Filter */
SOC_ENUM_EXT("DAC HPF Mode", da7219_dac_hpf_mode,
da7219_enum_locked_get, da7219_enum_locked_put),
SOC_ENUM("DAC HPF Corner Audio", da7219_dac_audio_hpf_corner),
SOC_ENUM("DAC HPF Corner Voice", da7219_dac_voice_hpf_corner),
/* DAC 5-Band Equaliser */
SOC_SINGLE_TLV("DAC EQ Band1 Volume", DA7219_DAC_FILTERS2,
DA7219_DAC_EQ_BAND1_SHIFT, DA7219_DAC_EQ_BAND_MAX,
DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
SOC_SINGLE_TLV("DAC EQ Band2 Volume", DA7219_DAC_FILTERS2,
DA7219_DAC_EQ_BAND2_SHIFT, DA7219_DAC_EQ_BAND_MAX,
DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
SOC_SINGLE_TLV("DAC EQ Band3 Volume", DA7219_DAC_FILTERS3,
DA7219_DAC_EQ_BAND3_SHIFT, DA7219_DAC_EQ_BAND_MAX,
DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
SOC_SINGLE_TLV("DAC EQ Band4 Volume", DA7219_DAC_FILTERS3,
DA7219_DAC_EQ_BAND4_SHIFT, DA7219_DAC_EQ_BAND_MAX,
DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
SOC_SINGLE_TLV("DAC EQ Band5 Volume", DA7219_DAC_FILTERS4,
DA7219_DAC_EQ_BAND5_SHIFT, DA7219_DAC_EQ_BAND_MAX,
DA7219_NO_INVERT, da7219_dac_eq_band_tlv),
SOC_SINGLE_EXT("DAC EQ Switch", DA7219_DAC_FILTERS4,
DA7219_DAC_EQ_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT, da7219_volsw_locked_get,
da7219_volsw_locked_put),
/* DAC Softmute */
SOC_ENUM("DAC Soft Mute Rate", da7219_dac_softmute_rate),
SOC_SINGLE_EXT("DAC Soft Mute Switch", DA7219_DAC_FILTERS5,
DA7219_DAC_SOFTMUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_NO_INVERT, da7219_volsw_locked_get,
da7219_volsw_locked_put),
/* DAC Noise Gate */
SOC_ENUM("DAC NG Setup Time", da7219_dac_ng_setup_time),
SOC_ENUM("DAC NG Rampup Rate", da7219_dac_ng_rampup_rate),
SOC_ENUM("DAC NG Rampdown Rate", da7219_dac_ng_rampdown_rate),
SOC_SINGLE_TLV("DAC NG Off Threshold", DA7219_DAC_NG_OFF_THRESH,
DA7219_DAC_NG_OFF_THRESHOLD_SHIFT,
DA7219_DAC_NG_THRESHOLD_MAX, DA7219_NO_INVERT,
da7219_dac_ng_threshold_tlv),
SOC_SINGLE_TLV("DAC NG On Threshold", DA7219_DAC_NG_ON_THRESH,
DA7219_DAC_NG_ON_THRESHOLD_SHIFT,
DA7219_DAC_NG_THRESHOLD_MAX, DA7219_NO_INVERT,
da7219_dac_ng_threshold_tlv),
SOC_SINGLE("DAC NG Switch", DA7219_DAC_NG_CTRL, DA7219_DAC_NG_EN_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
/* DACs */
SOC_DOUBLE_R_EXT_TLV("Playback Digital Volume", DA7219_DAC_L_GAIN,
DA7219_DAC_R_GAIN, DA7219_DAC_L_DIGITAL_GAIN_SHIFT,
DA7219_DAC_DIGITAL_GAIN_MAX, DA7219_NO_INVERT,
da7219_volsw_locked_get, da7219_volsw_locked_put,
da7219_dac_dig_gain_tlv),
SOC_DOUBLE_R_EXT("Playback Digital Switch", DA7219_DAC_L_CTRL,
DA7219_DAC_R_CTRL, DA7219_DAC_L_MUTE_EN_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_INVERT,
da7219_volsw_locked_get, da7219_volsw_locked_put),
SOC_DOUBLE_R("Playback Digital Gain Ramp Switch", DA7219_DAC_L_CTRL,
DA7219_DAC_R_CTRL, DA7219_DAC_L_RAMP_EN_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
/* CP */
SOC_ENUM("Charge Pump Track Mode", da7219_cp_track_mode),
SOC_SINGLE("Charge Pump Threshold", DA7219_CP_VOL_THRESHOLD1,
DA7219_CP_THRESH_VDD2_SHIFT, DA7219_CP_THRESH_VDD2_MAX,
DA7219_NO_INVERT),
/* Headphones */
SOC_DOUBLE_R_EXT_TLV("Headphone Volume", DA7219_HP_L_GAIN,
DA7219_HP_R_GAIN, DA7219_HP_L_AMP_GAIN_SHIFT,
DA7219_HP_AMP_GAIN_MAX, DA7219_NO_INVERT,
da7219_volsw_locked_get, da7219_volsw_locked_put,
da7219_hp_gain_tlv),
SOC_DOUBLE_R_EXT("Headphone Switch", DA7219_HP_L_CTRL, DA7219_HP_R_CTRL,
DA7219_HP_L_AMP_MUTE_EN_SHIFT, DA7219_SWITCH_EN_MAX,
DA7219_INVERT, da7219_volsw_locked_get,
da7219_volsw_locked_put),
SOC_DOUBLE_R("Headphone Gain Ramp Switch", DA7219_HP_L_CTRL,
DA7219_HP_R_CTRL, DA7219_HP_L_AMP_RAMP_EN_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
SOC_DOUBLE_R("Headphone ZC Gain Switch", DA7219_HP_L_CTRL,
DA7219_HP_R_CTRL, DA7219_HP_L_AMP_ZC_EN_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
};
/*
* DAPM Mux Controls
*/
static const char * const da7219_out_sel_txt[] = {
"ADC", "Tone Generator", "DAIL", "DAIR"
};
static const struct soc_enum da7219_out_dail_sel =
SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAI,
DA7219_DAI_L_SRC_SHIFT,
DA7219_OUT_SRC_MAX,
da7219_out_sel_txt);
static const struct snd_kcontrol_new da7219_out_dail_sel_mux =
SOC_DAPM_ENUM("Out DAIL Mux", da7219_out_dail_sel);
static const struct soc_enum da7219_out_dair_sel =
SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAI,
DA7219_DAI_R_SRC_SHIFT,
DA7219_OUT_SRC_MAX,
da7219_out_sel_txt);
static const struct snd_kcontrol_new da7219_out_dair_sel_mux =
SOC_DAPM_ENUM("Out DAIR Mux", da7219_out_dair_sel);
static const struct soc_enum da7219_out_dacl_sel =
SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAC,
DA7219_DAC_L_SRC_SHIFT,
DA7219_OUT_SRC_MAX,
da7219_out_sel_txt);
static const struct snd_kcontrol_new da7219_out_dacl_sel_mux =
SOC_DAPM_ENUM("Out DACL Mux", da7219_out_dacl_sel);
static const struct soc_enum da7219_out_dacr_sel =
SOC_ENUM_SINGLE(DA7219_DIG_ROUTING_DAC,
DA7219_DAC_R_SRC_SHIFT,
DA7219_OUT_SRC_MAX,
da7219_out_sel_txt);
static const struct snd_kcontrol_new da7219_out_dacr_sel_mux =
SOC_DAPM_ENUM("Out DACR Mux", da7219_out_dacr_sel);
/*
* DAPM Mixer Controls
*/
static const struct snd_kcontrol_new da7219_mixin_controls[] = {
SOC_DAPM_SINGLE("Mic Switch", DA7219_MIXIN_L_SELECT,
DA7219_MIXIN_L_MIX_SELECT_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
};
static const struct snd_kcontrol_new da7219_mixout_l_controls[] = {
SOC_DAPM_SINGLE("DACL Switch", DA7219_MIXOUT_L_SELECT,
DA7219_MIXOUT_L_MIX_SELECT_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
};
static const struct snd_kcontrol_new da7219_mixout_r_controls[] = {
SOC_DAPM_SINGLE("DACR Switch", DA7219_MIXOUT_R_SELECT,
DA7219_MIXOUT_R_MIX_SELECT_SHIFT,
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT),
};
#define DA7219_DMIX_ST_CTRLS(reg) \
SOC_DAPM_SINGLE("Out FilterL Switch", reg, \
DA7219_DMIX_ST_SRC_OUTFILT1L_SHIFT, \
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT), \
SOC_DAPM_SINGLE("Out FilterR Switch", reg, \
DA7219_DMIX_ST_SRC_OUTFILT1R_SHIFT, \
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT), \
SOC_DAPM_SINGLE("Sidetone Switch", reg, \
DA7219_DMIX_ST_SRC_SIDETONE_SHIFT, \
DA7219_SWITCH_EN_MAX, DA7219_NO_INVERT) \
static const struct snd_kcontrol_new da7219_st_out_filtl_mix_controls[] = {
DA7219_DMIX_ST_CTRLS(DA7219_DROUTING_ST_OUTFILT_1L),
};
static const struct snd_kcontrol_new da7219_st_out_filtr_mix_controls[] = {
DA7219_DMIX_ST_CTRLS(DA7219_DROUTING_ST_OUTFILT_1R),
};
/*
* DAPM Events
*/
static int da7219_mic_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (da7219->micbias_on_event) {
/*
* Delay only for first capture after bias enabled to
* avoid possible DC offset related noise.
*/
da7219->micbias_on_event = false;
msleep(da7219->mic_pga_delay);
}
break;
default:
break;
}
return 0;
}
static int da7219_dai_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX];
u8 pll_ctrl, pll_status;
int i = 0, ret;
bool srm_lock = false;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (da7219->master) {
/* Enable DAI clks for master mode */
if (bclk) {
ret = clk_prepare_enable(bclk);
if (ret) {
dev_err(component->dev,
"Failed to enable DAI clks\n");
return ret;
}
} else {
snd_soc_component_update_bits(component,
DA7219_DAI_CLK_MODE,
DA7219_DAI_CLK_EN_MASK,
DA7219_DAI_CLK_EN_MASK);
}
}
/* PC synchronised to DAI */
snd_soc_component_update_bits(component, DA7219_PC_COUNT,
DA7219_PC_FREERUN_MASK, 0);
/* Slave mode, if SRM not enabled no need for status checks */
pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL);
if ((pll_ctrl & DA7219_PLL_MODE_MASK) != DA7219_PLL_MODE_SRM)
return 0;
/* Check SRM has locked */
do {
pll_status = snd_soc_component_read(component, DA7219_PLL_SRM_STS);
if (pll_status & DA7219_PLL_SRM_STS_SRM_LOCK) {
srm_lock = true;
} else {
++i;
msleep(50);
}
} while ((i < DA7219_SRM_CHECK_RETRIES) && (!srm_lock));
if (!srm_lock)
dev_warn(component->dev, "SRM failed to lock\n");
return 0;
case SND_SOC_DAPM_POST_PMD:
/* PC free-running */
snd_soc_component_update_bits(component, DA7219_PC_COUNT,
DA7219_PC_FREERUN_MASK,
DA7219_PC_FREERUN_MASK);
/* Disable DAI clks if in master mode */
if (da7219->master) {
if (bclk)
clk_disable_unprepare(bclk);
else
snd_soc_component_update_bits(component,
DA7219_DAI_CLK_MODE,
DA7219_DAI_CLK_EN_MASK,
0);
}
return 0;
default:
return -EINVAL;
}
}
static int da7219_settling_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_POST_PMD:
msleep(DA7219_SETTLING_DELAY);
break;
default:
break;
}
return 0;
}
static int da7219_mixout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u8 hp_ctrl, min_gain_mask;
switch (w->reg) {
case DA7219_MIXOUT_L_CTRL:
hp_ctrl = DA7219_HP_L_CTRL;
min_gain_mask = DA7219_HP_L_AMP_MIN_GAIN_EN_MASK;
break;
case DA7219_MIXOUT_R_CTRL:
hp_ctrl = DA7219_HP_R_CTRL;
min_gain_mask = DA7219_HP_R_AMP_MIN_GAIN_EN_MASK;
break;
default:
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
/* Enable minimum gain on HP to avoid pops */
snd_soc_component_update_bits(component, hp_ctrl, min_gain_mask,
min_gain_mask);
msleep(DA7219_MIN_GAIN_DELAY);
break;
case SND_SOC_DAPM_POST_PMU:
/* Remove minimum gain on HP */
snd_soc_component_update_bits(component, hp_ctrl, min_gain_mask, 0);
break;
}
return 0;
}
static int da7219_gain_ramp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_PRE_PMD:
/* Ensure nominal gain ramping for DAPM sequence */
da7219->gain_ramp_ctrl =
snd_soc_component_read(component, DA7219_GAIN_RAMP_CTRL);
snd_soc_component_write(component, DA7219_GAIN_RAMP_CTRL,
DA7219_GAIN_RAMP_RATE_NOMINAL);
break;
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_POST_PMD:
/* Restore previous gain ramp settings */
snd_soc_component_write(component, DA7219_GAIN_RAMP_CTRL,
da7219->gain_ramp_ctrl);
break;
}
return 0;
}
/*
* DAPM Widgets
*/
static const struct snd_soc_dapm_widget da7219_dapm_widgets[] = {
/* Input Supplies */
SND_SOC_DAPM_SUPPLY("Mic Bias", DA7219_MICBIAS_CTRL,
DA7219_MICBIAS1_EN_SHIFT, DA7219_NO_INVERT,
NULL, 0),
/* Inputs */
SND_SOC_DAPM_INPUT("MIC"),
/* Input PGAs */
SND_SOC_DAPM_PGA_E("Mic PGA", DA7219_MIC_1_CTRL,
DA7219_MIC_1_AMP_EN_SHIFT, DA7219_NO_INVERT,
NULL, 0, da7219_mic_pga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("Mixin PGA", DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_AMP_EN_SHIFT, DA7219_NO_INVERT,
NULL, 0, da7219_settling_event, SND_SOC_DAPM_POST_PMU),
/* Input Filters */
SND_SOC_DAPM_ADC("ADC", NULL, DA7219_ADC_L_CTRL, DA7219_ADC_L_EN_SHIFT,
DA7219_NO_INVERT),
/* Tone Generator */
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_PGA("Tone Generator", DA7219_TONE_GEN_CFG1,
DA7219_START_STOPN_SHIFT, DA7219_NO_INVERT, NULL, 0),
/* Sidetone Input */
SND_SOC_DAPM_ADC("Sidetone Filter", NULL, DA7219_SIDETONE_CTRL,
DA7219_SIDETONE_EN_SHIFT, DA7219_NO_INVERT),
/* Input Mixer Supply */
SND_SOC_DAPM_SUPPLY("Mixer In Supply", DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_MIX_EN_SHIFT, DA7219_NO_INVERT,
NULL, 0),
/* Input Mixer */
SND_SOC_DAPM_MIXER("Mixer In", SND_SOC_NOPM, 0, 0,
da7219_mixin_controls,
ARRAY_SIZE(da7219_mixin_controls)),
/* Input Muxes */
SND_SOC_DAPM_MUX("Out DAIL Mux", SND_SOC_NOPM, 0, 0,
&da7219_out_dail_sel_mux),
SND_SOC_DAPM_MUX("Out DAIR Mux", SND_SOC_NOPM, 0, 0,
&da7219_out_dair_sel_mux),
/* DAI Supply */
SND_SOC_DAPM_SUPPLY("DAI", DA7219_DAI_CTRL, DA7219_DAI_EN_SHIFT,
DA7219_NO_INVERT, da7219_dai_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* DAI */
SND_SOC_DAPM_AIF_OUT("DAIOUT", "Capture", 0, DA7219_DAI_TDM_CTRL,
DA7219_DAI_OE_SHIFT, DA7219_NO_INVERT),
SND_SOC_DAPM_AIF_IN("DAIIN", "Playback", 0, SND_SOC_NOPM, 0, 0),
/* Output Muxes */
SND_SOC_DAPM_MUX("Out DACL Mux", SND_SOC_NOPM, 0, 0,
&da7219_out_dacl_sel_mux),
SND_SOC_DAPM_MUX("Out DACR Mux", SND_SOC_NOPM, 0, 0,
&da7219_out_dacr_sel_mux),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
da7219_mixout_l_controls,
ARRAY_SIZE(da7219_mixout_l_controls)),
SND_SOC_DAPM_MIXER("Mixer Out FilterR", SND_SOC_NOPM, 0, 0,
da7219_mixout_r_controls,
ARRAY_SIZE(da7219_mixout_r_controls)),
/* Sidetone Mixers */
SND_SOC_DAPM_MIXER("ST Mixer Out FilterL", SND_SOC_NOPM, 0, 0,
da7219_st_out_filtl_mix_controls,
ARRAY_SIZE(da7219_st_out_filtl_mix_controls)),
SND_SOC_DAPM_MIXER("ST Mixer Out FilterR", SND_SOC_NOPM, 0,
0, da7219_st_out_filtr_mix_controls,
ARRAY_SIZE(da7219_st_out_filtr_mix_controls)),
/* DACs */
SND_SOC_DAPM_DAC_E("DACL", NULL, DA7219_DAC_L_CTRL,
DA7219_DAC_L_EN_SHIFT, DA7219_NO_INVERT,
da7219_settling_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("DACR", NULL, DA7219_DAC_R_CTRL,
DA7219_DAC_R_EN_SHIFT, DA7219_NO_INVERT,
da7219_settling_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* Output PGAs */
SND_SOC_DAPM_PGA_E("Mixout Left PGA", DA7219_MIXOUT_L_CTRL,
DA7219_MIXOUT_L_AMP_EN_SHIFT, DA7219_NO_INVERT,
NULL, 0, da7219_mixout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("Mixout Right PGA", DA7219_MIXOUT_R_CTRL,
DA7219_MIXOUT_R_AMP_EN_SHIFT, DA7219_NO_INVERT,
NULL, 0, da7219_mixout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("Headphone Left PGA", 1, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_EN_SHIFT, DA7219_NO_INVERT,
da7219_settling_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("Headphone Right PGA", 1, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_EN_SHIFT, DA7219_NO_INVERT,
da7219_settling_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* Output Supplies */
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 0, DA7219_CP_CTRL,
DA7219_CP_EN_SHIFT, DA7219_NO_INVERT,
da7219_settling_event,
SND_SOC_DAPM_POST_PMU),
/* Outputs */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
/* Pre/Post Power */
SND_SOC_DAPM_PRE("Pre Power Gain Ramp", da7219_gain_ramp_event),
SND_SOC_DAPM_POST("Post Power Gain Ramp", da7219_gain_ramp_event),
};
/*
* DAPM Mux Routes
*/
#define DA7219_OUT_DAI_MUX_ROUTES(name) \
{name, "ADC", "Mixer In"}, \
{name, "Tone Generator", "Tone Generator"}, \
{name, "DAIL", "DAIOUT"}, \
{name, "DAIR", "DAIOUT"}
#define DA7219_OUT_DAC_MUX_ROUTES(name) \
{name, "ADC", "Mixer In"}, \
{name, "Tone Generator", "Tone Generator"}, \
{name, "DAIL", "DAIIN"}, \
{name, "DAIR", "DAIIN"}
/*
* DAPM Mixer Routes
*/
#define DA7219_DMIX_ST_ROUTES(name) \
{name, "Out FilterL Switch", "Mixer Out FilterL"}, \
{name, "Out FilterR Switch", "Mixer Out FilterR"}, \
{name, "Sidetone Switch", "Sidetone Filter"}
/*
* DAPM audio route definition
*/
static const struct snd_soc_dapm_route da7219_audio_map[] = {
/* Input paths */
{"MIC", NULL, "Mic Bias"},
{"Mic PGA", NULL, "MIC"},
{"Mixin PGA", NULL, "Mic PGA"},
{"ADC", NULL, "Mixin PGA"},
{"Mixer In", NULL, "Mixer In Supply"},
{"Mixer In", "Mic Switch", "ADC"},
{"Sidetone Filter", NULL, "Mixer In"},
{"Tone Generator", NULL, "TONE"},
DA7219_OUT_DAI_MUX_ROUTES("Out DAIL Mux"),
DA7219_OUT_DAI_MUX_ROUTES("Out DAIR Mux"),
{"DAIOUT", NULL, "Out DAIL Mux"},
{"DAIOUT", NULL, "Out DAIR Mux"},
{"DAIOUT", NULL, "DAI"},
/* Output paths */
{"DAIIN", NULL, "DAI"},
DA7219_OUT_DAC_MUX_ROUTES("Out DACL Mux"),
DA7219_OUT_DAC_MUX_ROUTES("Out DACR Mux"),
{"Mixer Out FilterL", "DACL Switch", "Out DACL Mux"},
{"Mixer Out FilterR", "DACR Switch", "Out DACR Mux"},
DA7219_DMIX_ST_ROUTES("ST Mixer Out FilterL"),
DA7219_DMIX_ST_ROUTES("ST Mixer Out FilterR"),
{"DACL", NULL, "ST Mixer Out FilterL"},
{"DACR", NULL, "ST Mixer Out FilterR"},
{"Mixout Left PGA", NULL, "DACL"},
{"Mixout Right PGA", NULL, "DACR"},
{"HPL", NULL, "Mixout Left PGA"},
{"HPR", NULL, "Mixout Right PGA"},
{"HPL", NULL, "Headphone Left PGA"},
{"HPR", NULL, "Headphone Right PGA"},
{"HPL", NULL, "Charge Pump"},
{"HPR", NULL, "Charge Pump"},
};
/*
* DAI operations
*/
static int da7219_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret = 0;
if ((da7219->clk_src == clk_id) && (da7219->mclk_rate == freq))
return 0;
if ((freq < 2000000) || (freq > 54000000)) {
dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
freq);
return -EINVAL;
}
mutex_lock(&da7219->pll_lock);
switch (clk_id) {
case DA7219_CLKSRC_MCLK_SQR:
snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
DA7219_PLL_MCLK_SQR_EN_MASK,
DA7219_PLL_MCLK_SQR_EN_MASK);
break;
case DA7219_CLKSRC_MCLK:
snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
DA7219_PLL_MCLK_SQR_EN_MASK, 0);
break;
default:
dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
mutex_unlock(&da7219->pll_lock);
return -EINVAL;
}
da7219->clk_src = clk_id;
if (da7219->mclk) {
freq = clk_round_rate(da7219->mclk, freq);
ret = clk_set_rate(da7219->mclk, freq);
if (ret) {
dev_err(codec_dai->dev, "Failed to set clock rate %d\n",
freq);
mutex_unlock(&da7219->pll_lock);
return ret;
}
}
da7219->mclk_rate = freq;
mutex_unlock(&da7219->pll_lock);
return 0;
}
int da7219_set_pll(struct snd_soc_component *component, int source, unsigned int fout)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
u8 pll_ctrl, indiv_bits, indiv;
u8 pll_frac_top, pll_frac_bot, pll_integer;
u32 freq_ref;
u64 frac_div;
/* Verify 2MHz - 54MHz MCLK provided, and set input divider */
if (da7219->mclk_rate < 2000000) {
dev_err(component->dev, "PLL input clock %d below valid range\n",
da7219->mclk_rate);
return -EINVAL;
} else if (da7219->mclk_rate <= 4500000) {
indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
} else if (da7219->mclk_rate <= 9000000) {
indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
} else if (da7219->mclk_rate <= 18000000) {
indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
} else if (da7219->mclk_rate <= 36000000) {
indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
} else if (da7219->mclk_rate <= 54000000) {
indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
} else {
dev_err(component->dev, "PLL input clock %d above valid range\n",
da7219->mclk_rate);
return -EINVAL;
}
freq_ref = (da7219->mclk_rate / indiv);
pll_ctrl = indiv_bits;
/* Configure PLL */
switch (source) {
case DA7219_SYSCLK_MCLK:
pll_ctrl |= DA7219_PLL_MODE_BYPASS;
snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
DA7219_PLL_INDIV_MASK |
DA7219_PLL_MODE_MASK, pll_ctrl);
return 0;
case DA7219_SYSCLK_PLL:
pll_ctrl |= DA7219_PLL_MODE_NORMAL;
break;
case DA7219_SYSCLK_PLL_SRM:
pll_ctrl |= DA7219_PLL_MODE_SRM;
break;
default:
dev_err(component->dev, "Invalid PLL config\n");
return -EINVAL;
}
/* Calculate dividers for PLL */
pll_integer = fout / freq_ref;
frac_div = (u64)(fout % freq_ref) * 8192ULL;
do_div(frac_div, freq_ref);
pll_frac_top = (frac_div >> DA7219_BYTE_SHIFT) & DA7219_BYTE_MASK;
pll_frac_bot = (frac_div) & DA7219_BYTE_MASK;
/* Write PLL config & dividers */
snd_soc_component_write(component, DA7219_PLL_FRAC_TOP, pll_frac_top);
snd_soc_component_write(component, DA7219_PLL_FRAC_BOT, pll_frac_bot);
snd_soc_component_write(component, DA7219_PLL_INTEGER, pll_integer);
snd_soc_component_update_bits(component, DA7219_PLL_CTRL,
DA7219_PLL_INDIV_MASK | DA7219_PLL_MODE_MASK,
pll_ctrl);
return 0;
}
static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int fref, unsigned int fout)
{
struct snd_soc_component *component = codec_dai->component;
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
mutex_lock(&da7219->pll_lock);
ret = da7219_set_pll(component, source, fout);
mutex_unlock(&da7219->pll_lock);
return ret;
}
static int da7219_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
u8 dai_clk_mode = 0, dai_ctrl = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
da7219->master = true;
break;
case SND_SOC_DAIFMT_CBS_CFS:
da7219->master = false;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
dai_clk_mode |= DA7219_DAI_WCLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
dai_clk_mode |= DA7219_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
dai_clk_mode |= DA7219_DAI_WCLK_POL_INV |
DA7219_DAI_CLK_POL_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_DSP_B:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
dai_clk_mode |= DA7219_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
dai_clk_mode |= DA7219_DAI_WCLK_POL_INV |
DA7219_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
dai_clk_mode |= DA7219_DAI_WCLK_POL_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dai_ctrl |= DA7219_DAI_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
dai_ctrl |= DA7219_DAI_FORMAT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
dai_ctrl |= DA7219_DAI_FORMAT_RIGHT_J;
break;
case SND_SOC_DAIFMT_DSP_B:
dai_ctrl |= DA7219_DAI_FORMAT_DSP;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
DA7219_DAI_CLK_POL_MASK | DA7219_DAI_WCLK_POL_MASK,
dai_clk_mode);
snd_soc_component_update_bits(component, DA7219_DAI_CTRL, DA7219_DAI_FORMAT_MASK,
dai_ctrl);
return 0;
}
static int da7219_set_bclks_per_wclk(struct snd_soc_component *component,
unsigned long factor)
{
u8 bclks_per_wclk;
switch (factor) {
case 32:
bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_32;
break;
case 64:
bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_64;
break;
case 128:
bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_128;
break;
case 256:
bclks_per_wclk = DA7219_DAI_BCLKS_PER_WCLK_256;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
DA7219_DAI_BCLKS_PER_WCLK_MASK,
bclks_per_wclk);
return 0;
}
static int da7219_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX];
struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX];
unsigned int ch_mask;
unsigned long sr, bclk_rate;
u8 slot_offset;
u16 offset;
__le16 dai_offset;
u32 frame_size;
int ret;
/* No channels enabled so disable TDM */
if (!tx_mask) {
snd_soc_component_update_bits(component, DA7219_DAI_TDM_CTRL,
DA7219_DAI_TDM_CH_EN_MASK |
DA7219_DAI_TDM_MODE_EN_MASK, 0);
da7219->tdm_en = false;
return 0;
}
/* Check we have valid slots */
slot_offset = ffs(tx_mask) - 1;
ch_mask = (tx_mask >> slot_offset);
if (fls(ch_mask) > DA7219_DAI_TDM_MAX_SLOTS) {
dev_err(component->dev,
"Invalid number of slots, max = %d\n",
DA7219_DAI_TDM_MAX_SLOTS);
return -EINVAL;
}
/*
* Ensure we have a valid offset into the frame, based on slot width
* and slot offset of first slot we're interested in.
*/
offset = slot_offset * slot_width;
if (offset > DA7219_DAI_OFFSET_MAX) {
dev_err(component->dev, "Invalid frame offset %d\n", offset);
return -EINVAL;
}
/*
* If we're master, calculate & validate frame size based on slot info
* provided as we have a limited set of rates available.
*/
if (da7219->master) {
frame_size = slots * slot_width;
if (bclk) {
sr = clk_get_rate(wclk);
bclk_rate = sr * frame_size;
ret = clk_set_rate(bclk, bclk_rate);
if (ret) {
dev_err(component->dev,
"Failed to set TDM BCLK rate %lu: %d\n",
bclk_rate, ret);
return ret;
}
} else {
ret = da7219_set_bclks_per_wclk(component, frame_size);
if (ret) {
dev_err(component->dev,
"Failed to set TDM BCLKs per WCLK %d: %d\n",
frame_size, ret);
return ret;
}
}
}
dai_offset = cpu_to_le16(offset);
regmap_bulk_write(da7219->regmap, DA7219_DAI_OFFSET_LOWER,
&dai_offset, sizeof(dai_offset));
snd_soc_component_update_bits(component, DA7219_DAI_TDM_CTRL,
DA7219_DAI_TDM_CH_EN_MASK |
DA7219_DAI_TDM_MODE_EN_MASK,
(ch_mask << DA7219_DAI_TDM_CH_EN_SHIFT) |
DA7219_DAI_TDM_MODE_EN_MASK);
da7219->tdm_en = true;
return 0;
}
static int da7219_set_sr(struct snd_soc_component *component,
unsigned long rate)
{
u8 fs;
switch (rate) {
case 8000:
fs = DA7219_SR_8000;
break;
case 11025:
fs = DA7219_SR_11025;
break;
case 12000:
fs = DA7219_SR_12000;
break;
case 16000:
fs = DA7219_SR_16000;
break;
case 22050:
fs = DA7219_SR_22050;
break;
case 24000:
fs = DA7219_SR_24000;
break;
case 32000:
fs = DA7219_SR_32000;
break;
case 44100:
fs = DA7219_SR_44100;
break;
case 48000:
fs = DA7219_SR_48000;
break;
case 88200:
fs = DA7219_SR_88200;
break;
case 96000:
fs = DA7219_SR_96000;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, DA7219_SR, fs);
return 0;
}
static int da7219_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX];
struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX];
u8 dai_ctrl = 0;
unsigned int channels;
unsigned long sr, bclk_rate;
int word_len = params_width(params);
int frame_size, ret;
switch (word_len) {
case 16:
dai_ctrl |= DA7219_DAI_WORD_LENGTH_S16_LE;
break;
case 20:
dai_ctrl |= DA7219_DAI_WORD_LENGTH_S20_LE;
break;
case 24:
dai_ctrl |= DA7219_DAI_WORD_LENGTH_S24_LE;
break;
case 32:
dai_ctrl |= DA7219_DAI_WORD_LENGTH_S32_LE;
break;
default:
return -EINVAL;
}
channels = params_channels(params);
if ((channels < 1) || (channels > DA7219_DAI_CH_NUM_MAX)) {
dev_err(component->dev,
"Invalid number of channels, only 1 to %d supported\n",
DA7219_DAI_CH_NUM_MAX);
return -EINVAL;
}
dai_ctrl |= channels << DA7219_DAI_CH_NUM_SHIFT;
sr = params_rate(params);
if (da7219->master && wclk) {
ret = clk_set_rate(wclk, sr);
if (ret) {
dev_err(component->dev,
"Failed to set WCLK SR %lu: %d\n", sr, ret);
return ret;
}
} else {
ret = da7219_set_sr(component, sr);
if (ret) {
dev_err(component->dev,
"Failed to set SR %lu: %d\n", sr, ret);
return ret;
}
}
/*
* If we're master, then we have a limited set of BCLK rates we
* support. For slave mode this isn't the case and the codec can detect
* the BCLK rate automatically.
*/
if (da7219->master && !da7219->tdm_en) {
if ((word_len * DA7219_DAI_CH_NUM_MAX) <= 32)
frame_size = 32;
else
frame_size = 64;
if (bclk) {
bclk_rate = frame_size * sr;
/*
* Rounding the rate here avoids failure trying to set a
* new rate on an already enabled bclk. In that
* instance this will just set the same rate as is
* currently in use, and so should continue without
* problem, as long as the BCLK rate is suitable for the
* desired frame size.
*/
bclk_rate = clk_round_rate(bclk, bclk_rate);
if ((bclk_rate / sr) < frame_size) {
dev_err(component->dev,
"BCLK rate mismatch against frame size");
return -EINVAL;
}
ret = clk_set_rate(bclk, bclk_rate);
if (ret) {
dev_err(component->dev,
"Failed to set BCLK rate %lu: %d\n",
bclk_rate, ret);
return ret;
}
} else {
ret = da7219_set_bclks_per_wclk(component, frame_size);
if (ret) {
dev_err(component->dev,
"Failed to set BCLKs per WCLK %d: %d\n",
frame_size, ret);
return ret;
}
}
}
snd_soc_component_update_bits(component, DA7219_DAI_CTRL,
DA7219_DAI_WORD_LENGTH_MASK |
DA7219_DAI_CH_NUM_MASK,
dai_ctrl);
return 0;
}
static const struct snd_soc_dai_ops da7219_dai_ops = {
.hw_params = da7219_hw_params,
.set_sysclk = da7219_set_dai_sysclk,
.set_pll = da7219_set_dai_pll,
.set_fmt = da7219_set_dai_fmt,
.set_tdm_slot = da7219_set_dai_tdm_slot,
};
#define DA7219_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
#define DA7219_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000)
static struct snd_soc_dai_driver da7219_dai = {
.name = "da7219-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = DA7219_DAI_CH_NUM_MAX,
.rates = DA7219_RATES,
.formats = DA7219_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = DA7219_DAI_CH_NUM_MAX,
.rates = DA7219_RATES,
.formats = DA7219_FORMATS,
},
.ops = &da7219_dai_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
};
/*
* DT/ACPI
*/
#ifdef CONFIG_OF
static const struct of_device_id da7219_of_match[] = {
{ .compatible = "dlg,da7219", },
{ }
};
MODULE_DEVICE_TABLE(of, da7219_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id da7219_acpi_match[] = {
{ .id = "DLGS7219", },
{ }
};
MODULE_DEVICE_TABLE(acpi, da7219_acpi_match);
#endif
static enum da7219_micbias_voltage
da7219_fw_micbias_lvl(struct device *dev, u32 val)
{
switch (val) {
case 1600:
return DA7219_MICBIAS_1_6V;
case 1800:
return DA7219_MICBIAS_1_8V;
case 2000:
return DA7219_MICBIAS_2_0V;
case 2200:
return DA7219_MICBIAS_2_2V;
case 2400:
return DA7219_MICBIAS_2_4V;
case 2600:
return DA7219_MICBIAS_2_6V;
default:
dev_warn(dev, "Invalid micbias level");
return DA7219_MICBIAS_2_2V;
}
}
static enum da7219_mic_amp_in_sel
da7219_fw_mic_amp_in_sel(struct device *dev, const char *str)
{
if (!strcmp(str, "diff")) {
return DA7219_MIC_AMP_IN_SEL_DIFF;
} else if (!strcmp(str, "se_p")) {
return DA7219_MIC_AMP_IN_SEL_SE_P;
} else if (!strcmp(str, "se_n")) {
return DA7219_MIC_AMP_IN_SEL_SE_N;
} else {
dev_warn(dev, "Invalid mic input type selection");
return DA7219_MIC_AMP_IN_SEL_DIFF;
}
}
static struct da7219_pdata *da7219_fw_to_pdata(struct device *dev)
{
struct da7219_pdata *pdata;
const char *of_str;
u32 of_val32;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
pdata->wakeup_source = device_property_read_bool(dev, "wakeup-source");
pdata->dai_clk_names[DA7219_DAI_WCLK_IDX] = "da7219-dai-wclk";
pdata->dai_clk_names[DA7219_DAI_BCLK_IDX] = "da7219-dai-bclk";
if (device_property_read_string_array(dev, "clock-output-names",
pdata->dai_clk_names,
DA7219_DAI_NUM_CLKS) < 0)
dev_warn(dev, "Using default DAI clk names: %s, %s\n",
pdata->dai_clk_names[DA7219_DAI_WCLK_IDX],
pdata->dai_clk_names[DA7219_DAI_BCLK_IDX]);
if (device_property_read_u32(dev, "dlg,micbias-lvl", &of_val32) >= 0)
pdata->micbias_lvl = da7219_fw_micbias_lvl(dev, of_val32);
else
pdata->micbias_lvl = DA7219_MICBIAS_2_2V;
if (!device_property_read_string(dev, "dlg,mic-amp-in-sel", &of_str))
pdata->mic_amp_in_sel = da7219_fw_mic_amp_in_sel(dev, of_str);
else
pdata->mic_amp_in_sel = DA7219_MIC_AMP_IN_SEL_DIFF;
return pdata;
}
/*
* Codec driver functions
*/
static int da7219_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Enable MCLK for transition to ON state */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
if (da7219->mclk) {
ret = clk_prepare_enable(da7219->mclk);
if (ret) {
dev_err(component->dev,
"Failed to enable mclk\n");
return ret;
}
}
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
/* Master bias */
snd_soc_component_update_bits(component, DA7219_REFERENCES,
DA7219_BIAS_EN_MASK,
DA7219_BIAS_EN_MASK);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
/* Remove MCLK */
if (da7219->mclk)
clk_disable_unprepare(da7219->mclk);
}
break;
case SND_SOC_BIAS_OFF:
/* Only disable master bias if we're not a wake-up source */
if (!da7219->wakeup_source)
snd_soc_component_update_bits(component, DA7219_REFERENCES,
DA7219_BIAS_EN_MASK, 0);
break;
}
return 0;
}
static const char *da7219_supply_names[DA7219_NUM_SUPPLIES] = {
[DA7219_SUPPLY_VDD] = "VDD",
[DA7219_SUPPLY_VDDMIC] = "VDDMIC",
[DA7219_SUPPLY_VDDIO] = "VDDIO",
};
static int da7219_handle_supplies(struct snd_soc_component *component,
u8 *io_voltage_lvl)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct regulator *vddio;
int i, ret;
/* Get required supplies */
for (i = 0; i < DA7219_NUM_SUPPLIES; ++i)
da7219->supplies[i].supply = da7219_supply_names[i];
ret = regulator_bulk_get(component->dev, DA7219_NUM_SUPPLIES,
da7219->supplies);
if (ret) {
dev_err(component->dev, "Failed to get supplies");
return ret;
}
/* Default to upper range */
*io_voltage_lvl = DA7219_IO_VOLTAGE_LEVEL_2_5V_3_6V;
/* Determine VDDIO voltage provided */
vddio = da7219->supplies[DA7219_SUPPLY_VDDIO].consumer;
ret = regulator_get_voltage(vddio);
if (ret < 1200000)
dev_warn(component->dev, "Invalid VDDIO voltage\n");
else if (ret < 2800000)
*io_voltage_lvl = DA7219_IO_VOLTAGE_LEVEL_1_2V_2_8V;
/* Enable main supplies */
ret = regulator_bulk_enable(DA7219_NUM_SUPPLIES, da7219->supplies);
if (ret) {
dev_err(component->dev, "Failed to enable supplies");
regulator_bulk_free(DA7219_NUM_SUPPLIES, da7219->supplies);
return ret;
}
return 0;
}
#ifdef CONFIG_COMMON_CLK
static int da7219_wclk_prepare(struct clk_hw *hw)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_WCLK_IDX]);
struct snd_soc_component *component = da7219->component;
if (!da7219->master)
return -EINVAL;
snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
DA7219_DAI_CLK_EN_MASK,
DA7219_DAI_CLK_EN_MASK);
return 0;
}
static void da7219_wclk_unprepare(struct clk_hw *hw)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_WCLK_IDX]);
struct snd_soc_component *component = da7219->component;
if (!da7219->master)
return;
snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE,
DA7219_DAI_CLK_EN_MASK, 0);
}
static int da7219_wclk_is_prepared(struct clk_hw *hw)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_WCLK_IDX]);
struct snd_soc_component *component = da7219->component;
u8 clk_reg;
if (!da7219->master)
return -EINVAL;
clk_reg = snd_soc_component_read(component, DA7219_DAI_CLK_MODE);
return !!(clk_reg & DA7219_DAI_CLK_EN_MASK);
}
static unsigned long da7219_wclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_WCLK_IDX]);
struct snd_soc_component *component = da7219->component;
u8 fs = snd_soc_component_read(component, DA7219_SR);
switch (fs & DA7219_SR_MASK) {
case DA7219_SR_8000:
return 8000;
case DA7219_SR_11025:
return 11025;
case DA7219_SR_12000:
return 12000;
case DA7219_SR_16000:
return 16000;
case DA7219_SR_22050:
return 22050;
case DA7219_SR_24000:
return 24000;
case DA7219_SR_32000:
return 32000;
case DA7219_SR_44100:
return 44100;
case DA7219_SR_48000:
return 48000;
case DA7219_SR_88200:
return 88200;
case DA7219_SR_96000:
return 96000;
default:
return 0;
}
}
static long da7219_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_WCLK_IDX]);
if (!da7219->master)
return -EINVAL;
if (rate < 11025)
return 8000;
else if (rate < 12000)
return 11025;
else if (rate < 16000)
return 12000;
else if (rate < 22050)
return 16000;
else if (rate < 24000)
return 22050;
else if (rate < 32000)
return 24000;
else if (rate < 44100)
return 32000;
else if (rate < 48000)
return 44100;
else if (rate < 88200)
return 48000;
else if (rate < 96000)
return 88200;
else
return 96000;
}
static int da7219_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_WCLK_IDX]);
struct snd_soc_component *component = da7219->component;
if (!da7219->master)
return -EINVAL;
return da7219_set_sr(component, rate);
}
static unsigned long da7219_bclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_BCLK_IDX]);
struct snd_soc_component *component = da7219->component;
u8 bclks_per_wclk = snd_soc_component_read(component,
DA7219_DAI_CLK_MODE);
switch (bclks_per_wclk & DA7219_DAI_BCLKS_PER_WCLK_MASK) {
case DA7219_DAI_BCLKS_PER_WCLK_32:
return parent_rate * 32;
case DA7219_DAI_BCLKS_PER_WCLK_64:
return parent_rate * 64;
case DA7219_DAI_BCLKS_PER_WCLK_128:
return parent_rate * 128;
case DA7219_DAI_BCLKS_PER_WCLK_256:
return parent_rate * 256;
default:
return 0;
}
}
static unsigned long da7219_bclk_get_factor(unsigned long rate,
unsigned long parent_rate)
{
unsigned long factor;
factor = rate / parent_rate;
if (factor < 64)
return 32;
else if (factor < 128)
return 64;
else if (factor < 256)
return 128;
else
return 256;
}
static long da7219_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_BCLK_IDX]);
unsigned long factor;
if (!*parent_rate || !da7219->master)
return -EINVAL;
/*
* We don't allow changing the parent rate as some BCLK rates can be
* derived from multiple parent WCLK rates (BCLK rates are set as a
* multiplier of WCLK in HW). We just do some rounding down based on the
* parent WCLK rate set and find the appropriate multiplier of BCLK to
* get the rounded down BCLK value.
*/
factor = da7219_bclk_get_factor(rate, *parent_rate);
return *parent_rate * factor;
}
static int da7219_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct da7219_priv *da7219 =
container_of(hw, struct da7219_priv,
dai_clks_hw[DA7219_DAI_BCLK_IDX]);
struct snd_soc_component *component = da7219->component;
unsigned long factor;
if (!da7219->master)
return -EINVAL;
factor = da7219_bclk_get_factor(rate, parent_rate);
return da7219_set_bclks_per_wclk(component, factor);
}
static const struct clk_ops da7219_dai_clk_ops[DA7219_DAI_NUM_CLKS] = {
[DA7219_DAI_WCLK_IDX] = {
.prepare = da7219_wclk_prepare,
.unprepare = da7219_wclk_unprepare,
.is_prepared = da7219_wclk_is_prepared,
.recalc_rate = da7219_wclk_recalc_rate,
.round_rate = da7219_wclk_round_rate,
.set_rate = da7219_wclk_set_rate,
},
[DA7219_DAI_BCLK_IDX] = {
.recalc_rate = da7219_bclk_recalc_rate,
.round_rate = da7219_bclk_round_rate,
.set_rate = da7219_bclk_set_rate,
},
};
static int da7219_register_dai_clks(struct snd_soc_component *component)
{
struct device *dev = component->dev;
struct device_node *np = dev->of_node;
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_pdata *pdata = da7219->pdata;
const char *parent_name;
struct clk_hw_onecell_data *clk_data;
int i, ret;
/* For DT platforms allocate onecell data for clock registration */
if (np) {
clk_data = kzalloc(struct_size(clk_data, hws, DA7219_DAI_NUM_CLKS),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = DA7219_DAI_NUM_CLKS;
da7219->clk_hw_data = clk_data;
}
for (i = 0; i < DA7219_DAI_NUM_CLKS; ++i) {
struct clk_init_data init = {};
struct clk_lookup *dai_clk_lookup;
struct clk_hw *dai_clk_hw = &da7219->dai_clks_hw[i];
switch (i) {
case DA7219_DAI_WCLK_IDX:
/*
* If we can, make MCLK the parent of WCLK to ensure
* it's enabled as required.
*/
if (da7219->mclk) {
parent_name = __clk_get_name(da7219->mclk);
init.parent_names = &parent_name;
init.num_parents = 1;
} else {
init.parent_names = NULL;
init.num_parents = 0;
}
break;
case DA7219_DAI_BCLK_IDX:
/* Make WCLK the parent of BCLK */
parent_name = __clk_get_name(da7219->dai_clks[DA7219_DAI_WCLK_IDX]);
init.parent_names = &parent_name;
init.num_parents = 1;
break;
default:
dev_err(dev, "Invalid clock index\n");
ret = -EINVAL;
goto err;
}
init.name = pdata->dai_clk_names[i];
init.ops = &da7219_dai_clk_ops[i];
init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
dai_clk_hw->init = &init;
ret = clk_hw_register(dev, dai_clk_hw);
if (ret) {
dev_warn(dev, "Failed to register %s: %d\n", init.name,
ret);
goto err;
}
da7219->dai_clks[i] = dai_clk_hw->clk;
/* For DT setup onecell data, otherwise create lookup */
if (np) {
da7219->clk_hw_data->hws[i] = dai_clk_hw;
} else {
dai_clk_lookup = clkdev_hw_create(dai_clk_hw, init.name,
"%s", dev_name(dev));
if (!dai_clk_lookup) {
clk_hw_unregister(dai_clk_hw);
ret = -ENOMEM;
goto err;
} else {
da7219->dai_clks_lookup[i] = dai_clk_lookup;
}
}
}
/* If we're using DT, then register as provider accordingly */
if (np) {
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
da7219->clk_hw_data);
if (ret) {
dev_err(dev, "Failed to register clock provider\n");
goto err;
}
}
return 0;
err:
while (--i >= 0) {
if (da7219->dai_clks_lookup[i])
clkdev_drop(da7219->dai_clks_lookup[i]);
clk_hw_unregister(&da7219->dai_clks_hw[i]);
}
if (np)
kfree(da7219->clk_hw_data);
return ret;
}
static void da7219_free_dai_clks(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct device_node *np = component->dev->of_node;
int i;
if (np)
of_clk_del_provider(np);
for (i = DA7219_DAI_NUM_CLKS - 1; i >= 0; --i) {
if (da7219->dai_clks_lookup[i])
clkdev_drop(da7219->dai_clks_lookup[i]);
clk_hw_unregister(&da7219->dai_clks_hw[i]);
}
if (np)
kfree(da7219->clk_hw_data);
}
#else
static inline int da7219_register_dai_clks(struct snd_soc_component *component)
{
return 0;
}
static void da7219_free_dai_clks(struct snd_soc_component *component) {}
#endif /* CONFIG_COMMON_CLK */
static void da7219_handle_pdata(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
struct da7219_pdata *pdata = da7219->pdata;
if (pdata) {
u8 micbias_lvl = 0;
da7219->wakeup_source = pdata->wakeup_source;
/* Mic Bias voltages */
switch (pdata->micbias_lvl) {
case DA7219_MICBIAS_1_6V:
case DA7219_MICBIAS_1_8V:
case DA7219_MICBIAS_2_0V:
case DA7219_MICBIAS_2_2V:
case DA7219_MICBIAS_2_4V:
case DA7219_MICBIAS_2_6V:
micbias_lvl |= (pdata->micbias_lvl <<
DA7219_MICBIAS1_LEVEL_SHIFT);
break;
}
snd_soc_component_write(component, DA7219_MICBIAS_CTRL, micbias_lvl);
/*
* Calculate delay required to compensate for DC offset in
* Mic PGA, based on Mic Bias voltage.
*/
da7219->mic_pga_delay = DA7219_MIC_PGA_BASE_DELAY +
(pdata->micbias_lvl *
DA7219_MIC_PGA_OFFSET_DELAY);
/* Mic */
switch (pdata->mic_amp_in_sel) {
case DA7219_MIC_AMP_IN_SEL_DIFF:
case DA7219_MIC_AMP_IN_SEL_SE_P:
case DA7219_MIC_AMP_IN_SEL_SE_N:
snd_soc_component_write(component, DA7219_MIC_1_SELECT,
pdata->mic_amp_in_sel);
break;
}
}
}
/*
* Regmap configs
*/
static struct reg_default da7219_reg_defaults[] = {
{ DA7219_MIC_1_SELECT, 0x00 },
{ DA7219_CIF_TIMEOUT_CTRL, 0x01 },
{ DA7219_SR_24_48, 0x00 },
{ DA7219_SR, 0x0A },
{ DA7219_CIF_I2C_ADDR_CFG, 0x02 },
{ DA7219_PLL_CTRL, 0x10 },
{ DA7219_PLL_FRAC_TOP, 0x00 },
{ DA7219_PLL_FRAC_BOT, 0x00 },
{ DA7219_PLL_INTEGER, 0x20 },
{ DA7219_DIG_ROUTING_DAI, 0x10 },
{ DA7219_DAI_CLK_MODE, 0x01 },
{ DA7219_DAI_CTRL, 0x28 },
{ DA7219_DAI_TDM_CTRL, 0x40 },
{ DA7219_DIG_ROUTING_DAC, 0x32 },
{ DA7219_DAI_OFFSET_LOWER, 0x00 },
{ DA7219_DAI_OFFSET_UPPER, 0x00 },
{ DA7219_REFERENCES, 0x08 },
{ DA7219_MIXIN_L_SELECT, 0x00 },
{ DA7219_MIXIN_L_GAIN, 0x03 },
{ DA7219_ADC_L_GAIN, 0x6F },
{ DA7219_ADC_FILTERS1, 0x80 },
{ DA7219_MIC_1_GAIN, 0x01 },
{ DA7219_SIDETONE_CTRL, 0x40 },
{ DA7219_SIDETONE_GAIN, 0x0E },
{ DA7219_DROUTING_ST_OUTFILT_1L, 0x01 },
{ DA7219_DROUTING_ST_OUTFILT_1R, 0x02 },
{ DA7219_DAC_FILTERS5, 0x00 },
{ DA7219_DAC_FILTERS2, 0x88 },
{ DA7219_DAC_FILTERS3, 0x88 },
{ DA7219_DAC_FILTERS4, 0x08 },
{ DA7219_DAC_FILTERS1, 0x80 },
{ DA7219_DAC_L_GAIN, 0x6F },
{ DA7219_DAC_R_GAIN, 0x6F },
{ DA7219_CP_CTRL, 0x20 },
{ DA7219_HP_L_GAIN, 0x39 },
{ DA7219_HP_R_GAIN, 0x39 },
{ DA7219_MIXOUT_L_SELECT, 0x00 },
{ DA7219_MIXOUT_R_SELECT, 0x00 },
{ DA7219_MICBIAS_CTRL, 0x03 },
{ DA7219_MIC_1_CTRL, 0x40 },
{ DA7219_MIXIN_L_CTRL, 0x40 },
{ DA7219_ADC_L_CTRL, 0x40 },
{ DA7219_DAC_L_CTRL, 0x40 },
{ DA7219_DAC_R_CTRL, 0x40 },
{ DA7219_HP_L_CTRL, 0x40 },
{ DA7219_HP_R_CTRL, 0x40 },
{ DA7219_MIXOUT_L_CTRL, 0x10 },
{ DA7219_MIXOUT_R_CTRL, 0x10 },
{ DA7219_CHIP_ID1, 0x23 },
{ DA7219_CHIP_ID2, 0x93 },
{ DA7219_IO_CTRL, 0x00 },
{ DA7219_GAIN_RAMP_CTRL, 0x00 },
{ DA7219_PC_COUNT, 0x02 },
{ DA7219_CP_VOL_THRESHOLD1, 0x0E },
{ DA7219_DIG_CTRL, 0x00 },
{ DA7219_ALC_CTRL2, 0x00 },
{ DA7219_ALC_CTRL3, 0x00 },
{ DA7219_ALC_NOISE, 0x3F },
{ DA7219_ALC_TARGET_MIN, 0x3F },
{ DA7219_ALC_TARGET_MAX, 0x00 },
{ DA7219_ALC_GAIN_LIMITS, 0xFF },
{ DA7219_ALC_ANA_GAIN_LIMITS, 0x71 },
{ DA7219_ALC_ANTICLIP_CTRL, 0x00 },
{ DA7219_ALC_ANTICLIP_LEVEL, 0x00 },
{ DA7219_DAC_NG_SETUP_TIME, 0x00 },
{ DA7219_DAC_NG_OFF_THRESH, 0x00 },
{ DA7219_DAC_NG_ON_THRESH, 0x00 },
{ DA7219_DAC_NG_CTRL, 0x00 },
{ DA7219_TONE_GEN_CFG1, 0x00 },
{ DA7219_TONE_GEN_CFG2, 0x00 },
{ DA7219_TONE_GEN_CYCLES, 0x00 },
{ DA7219_TONE_GEN_FREQ1_L, 0x55 },
{ DA7219_TONE_GEN_FREQ1_U, 0x15 },
{ DA7219_TONE_GEN_FREQ2_L, 0x00 },
{ DA7219_TONE_GEN_FREQ2_U, 0x40 },
{ DA7219_TONE_GEN_ON_PER, 0x02 },
{ DA7219_TONE_GEN_OFF_PER, 0x01 },
{ DA7219_ACCDET_IRQ_MASK_A, 0x00 },
{ DA7219_ACCDET_IRQ_MASK_B, 0x00 },
{ DA7219_ACCDET_CONFIG_1, 0xD6 },
{ DA7219_ACCDET_CONFIG_2, 0x34 },
{ DA7219_ACCDET_CONFIG_3, 0x0A },
{ DA7219_ACCDET_CONFIG_4, 0x16 },
{ DA7219_ACCDET_CONFIG_5, 0x21 },
{ DA7219_ACCDET_CONFIG_6, 0x3E },
{ DA7219_ACCDET_CONFIG_7, 0x01 },
{ DA7219_SYSTEM_ACTIVE, 0x00 },
};
static bool da7219_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA7219_MIC_1_GAIN_STATUS:
case DA7219_MIXIN_L_GAIN_STATUS:
case DA7219_ADC_L_GAIN_STATUS:
case DA7219_DAC_L_GAIN_STATUS:
case DA7219_DAC_R_GAIN_STATUS:
case DA7219_HP_L_GAIN_STATUS:
case DA7219_HP_R_GAIN_STATUS:
case DA7219_CIF_CTRL:
case DA7219_PLL_SRM_STS:
case DA7219_ALC_CTRL1:
case DA7219_SYSTEM_MODES_INPUT:
case DA7219_SYSTEM_MODES_OUTPUT:
case DA7219_ALC_OFFSET_AUTO_M_L:
case DA7219_ALC_OFFSET_AUTO_U_L:
case DA7219_TONE_GEN_CFG1:
case DA7219_ACCDET_STATUS_A:
case DA7219_ACCDET_STATUS_B:
case DA7219_ACCDET_IRQ_EVENT_A:
case DA7219_ACCDET_IRQ_EVENT_B:
case DA7219_ACCDET_CONFIG_8:
case DA7219_SYSTEM_STATUS:
return true;
default:
return false;
}
}
static const struct regmap_config da7219_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = DA7219_SYSTEM_ACTIVE,
.reg_defaults = da7219_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(da7219_reg_defaults),
.volatile_reg = da7219_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static struct reg_sequence da7219_rev_aa_patch[] = {
{ DA7219_REFERENCES, 0x08 },
};
static int da7219_probe(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
unsigned int system_active, system_status, rev;
u8 io_voltage_lvl;
int i, ret;
da7219->component = component;
mutex_init(&da7219->ctrl_lock);
mutex_init(&da7219->pll_lock);
/* Regulator configuration */
ret = da7219_handle_supplies(component, &io_voltage_lvl);
if (ret)
return ret;
regcache_cache_bypass(da7219->regmap, true);
/* Disable audio paths if still active from previous start */
regmap_read(da7219->regmap, DA7219_SYSTEM_ACTIVE, &system_active);
if (system_active) {
regmap_write(da7219->regmap, DA7219_GAIN_RAMP_CTRL,
DA7219_GAIN_RAMP_RATE_NOMINAL);
regmap_write(da7219->regmap, DA7219_SYSTEM_MODES_INPUT, 0x00);
regmap_write(da7219->regmap, DA7219_SYSTEM_MODES_OUTPUT, 0x01);
for (i = 0; i < DA7219_SYS_STAT_CHECK_RETRIES; ++i) {
regmap_read(da7219->regmap, DA7219_SYSTEM_STATUS,
&system_status);
if (!system_status)
break;
msleep(DA7219_SYS_STAT_CHECK_DELAY);
}
}
/* Soft reset component */
regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
DA7219_ACCDET_EN_MASK, 0);
regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
DA7219_CIF_REG_SOFT_RESET_MASK,
DA7219_CIF_REG_SOFT_RESET_MASK);
regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
DA7219_SYSTEM_ACTIVE_MASK, 0);
regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
DA7219_SYSTEM_ACTIVE_MASK, 1);
regcache_cache_bypass(da7219->regmap, false);
regmap_reinit_cache(da7219->regmap, &da7219_regmap_config);
/* Update IO voltage level range based on supply level */
snd_soc_component_write(component, DA7219_IO_CTRL, io_voltage_lvl);
ret = regmap_read(da7219->regmap, DA7219_CHIP_REVISION, &rev);
if (ret) {
dev_err(component->dev, "Failed to read chip revision: %d\n", ret);
goto err_disable_reg;
}
switch (rev & DA7219_CHIP_MINOR_MASK) {
case 0:
ret = regmap_register_patch(da7219->regmap, da7219_rev_aa_patch,
ARRAY_SIZE(da7219_rev_aa_patch));
if (ret) {
dev_err(component->dev, "Failed to register AA patch: %d\n",
ret);
goto err_disable_reg;
}
break;
default:
break;
}
/* Handle DT/ACPI/Platform data */
da7219_handle_pdata(component);
/* Check if MCLK provided */
da7219->mclk = clk_get(component->dev, "mclk");
if (IS_ERR(da7219->mclk)) {
if (PTR_ERR(da7219->mclk) != -ENOENT) {
ret = PTR_ERR(da7219->mclk);
goto err_disable_reg;
} else {
da7219->mclk = NULL;
}
}
/* Register CCF DAI clock control */
ret = da7219_register_dai_clks(component);
if (ret)
goto err_put_clk;
/* Default PC counter to free-running */
snd_soc_component_update_bits(component, DA7219_PC_COUNT, DA7219_PC_FREERUN_MASK,
DA7219_PC_FREERUN_MASK);
/* Default gain ramping */
snd_soc_component_update_bits(component, DA7219_MIXIN_L_CTRL,
DA7219_MIXIN_L_AMP_RAMP_EN_MASK,
DA7219_MIXIN_L_AMP_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_ADC_L_CTRL, DA7219_ADC_L_RAMP_EN_MASK,
DA7219_ADC_L_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_DAC_L_CTRL, DA7219_DAC_L_RAMP_EN_MASK,
DA7219_DAC_L_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_DAC_R_CTRL, DA7219_DAC_R_RAMP_EN_MASK,
DA7219_DAC_R_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_RAMP_EN_MASK,
DA7219_HP_L_AMP_RAMP_EN_MASK);
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_RAMP_EN_MASK,
DA7219_HP_R_AMP_RAMP_EN_MASK);
/* Default minimum gain on HP to avoid pops during DAPM sequencing */
snd_soc_component_update_bits(component, DA7219_HP_L_CTRL,
DA7219_HP_L_AMP_MIN_GAIN_EN_MASK,
DA7219_HP_L_AMP_MIN_GAIN_EN_MASK);
snd_soc_component_update_bits(component, DA7219_HP_R_CTRL,
DA7219_HP_R_AMP_MIN_GAIN_EN_MASK,
DA7219_HP_R_AMP_MIN_GAIN_EN_MASK);
/* Default infinite tone gen, start/stop by Kcontrol */
snd_soc_component_write(component, DA7219_TONE_GEN_CYCLES, DA7219_BEEP_CYCLES_MASK);
/* Initialise AAD block */
ret = da7219_aad_init(component);
if (ret)
goto err_free_dai_clks;
return 0;
err_free_dai_clks:
da7219_free_dai_clks(component);
err_put_clk:
clk_put(da7219->mclk);
err_disable_reg:
regulator_bulk_disable(DA7219_NUM_SUPPLIES, da7219->supplies);
regulator_bulk_free(DA7219_NUM_SUPPLIES, da7219->supplies);
return ret;
}
static void da7219_remove(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
da7219_aad_exit(component);
da7219_free_dai_clks(component);
clk_put(da7219->mclk);
/* Supplies */
regulator_bulk_disable(DA7219_NUM_SUPPLIES, da7219->supplies);
regulator_bulk_free(DA7219_NUM_SUPPLIES, da7219->supplies);
}
#ifdef CONFIG_PM
static int da7219_suspend(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
/* Suspend AAD if we're not a wake-up source */
if (!da7219->wakeup_source)
da7219_aad_suspend(component);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
static int da7219_resume(struct snd_soc_component *component)
{
struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Resume AAD if previously suspended */
if (!da7219->wakeup_source)
da7219_aad_resume(component);
return 0;
}
#else
#define da7219_suspend NULL
#define da7219_resume NULL
#endif
static int da7219_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jack,
void *data)
{
da7219_aad_jack_det(component, jack);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_da7219 = {
.probe = da7219_probe,
.remove = da7219_remove,
.suspend = da7219_suspend,
.resume = da7219_resume,
.set_jack = da7219_set_jack,
.set_bias_level = da7219_set_bias_level,
.controls = da7219_snd_controls,
.num_controls = ARRAY_SIZE(da7219_snd_controls),
.dapm_widgets = da7219_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da7219_dapm_widgets),
.dapm_routes = da7219_audio_map,
.num_dapm_routes = ARRAY_SIZE(da7219_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/*
* I2C layer
*/
static int da7219_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct da7219_priv *da7219;
int ret;
da7219 = devm_kzalloc(dev, sizeof(struct da7219_priv),
GFP_KERNEL);
if (!da7219)
return -ENOMEM;
i2c_set_clientdata(i2c, da7219);
da7219->regmap = devm_regmap_init_i2c(i2c, &da7219_regmap_config);
if (IS_ERR(da7219->regmap)) {
ret = PTR_ERR(da7219->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
return ret;
}
/* Retrieve DT/ACPI/Platform data */
da7219->pdata = dev_get_platdata(dev);
if (!da7219->pdata)
da7219->pdata = da7219_fw_to_pdata(dev);
/* AAD */
ret = da7219_aad_probe(i2c);
if (ret)
return ret;
ret = devm_snd_soc_register_component(dev, &soc_component_dev_da7219,
&da7219_dai, 1);
if (ret < 0) {
dev_err(dev, "Failed to register da7219 component: %d\n", ret);
}
return ret;
}
static const struct i2c_device_id da7219_i2c_id[] = {
{ "da7219", },
{ }
};
MODULE_DEVICE_TABLE(i2c, da7219_i2c_id);
static struct i2c_driver da7219_i2c_driver = {
.driver = {
.name = "da7219",
.of_match_table = of_match_ptr(da7219_of_match),
.acpi_match_table = ACPI_PTR(da7219_acpi_match),
},
.probe = da7219_i2c_probe,
.id_table = da7219_i2c_id,
};
module_i2c_driver(da7219_i2c_driver);
MODULE_DESCRIPTION("ASoC DA7219 Codec Driver");
MODULE_AUTHOR("Adam Thomson <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da7219.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SSM2602 SPI audio driver
*
* Copyright 2014 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "ssm2602.h"
static int ssm2602_spi_probe(struct spi_device *spi)
{
return ssm2602_probe(&spi->dev, SSM2602,
devm_regmap_init_spi(spi, &ssm2602_regmap_config));
}
static const struct of_device_id ssm2602_of_match[] = {
{ .compatible = "adi,ssm2602", },
{ }
};
MODULE_DEVICE_TABLE(of, ssm2602_of_match);
static struct spi_driver ssm2602_spi_driver = {
.driver = {
.name = "ssm2602",
.of_match_table = ssm2602_of_match,
},
.probe = ssm2602_spi_probe,
};
module_spi_driver(ssm2602_spi_driver);
MODULE_DESCRIPTION("ASoC SSM2602 SPI driver");
MODULE_AUTHOR("Cliff Cai");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ssm2602-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt722-sdca-sdw.c -- rt722 SDCA ALSA SoC audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw_registers.h>
#include "rt722-sdca.h"
#include "rt722-sdca-sdw.h"
static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f01 ... 0x2f0a:
case 0x2f35 ... 0x2f36:
case 0x2f50:
case 0x2f54:
case 0x2f58 ... 0x2f5d:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_SELECTED_MODE,
0):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt722_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f01:
case 0x2f54:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt722_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000 ... 0x2000024:
case 0x2000029 ... 0x200004a:
case 0x2000051 ... 0x2000052:
case 0x200005a ... 0x200005b:
case 0x2000061 ... 0x2000069:
case 0x200006b:
case 0x2000070:
case 0x200007f:
case 0x2000082 ... 0x200008e:
case 0x2000090 ... 0x2000094:
case 0x5300000 ... 0x5300002:
case 0x5400002:
case 0x5600000 ... 0x5600007:
case 0x5700000 ... 0x5700004:
case 0x5800000 ... 0x5800004:
case 0x5b00003:
case 0x5c00011:
case 0x5d00006:
case 0x5f00000 ... 0x5f0000d:
case 0x5f00030:
case 0x6100000 ... 0x6100051:
case 0x6100055 ... 0x6100057:
case 0x6100062:
case 0x6100064 ... 0x6100065:
case 0x6100067:
case 0x6100070 ... 0x610007c:
case 0x6100080:
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_01):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_02):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_03):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_04):
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
RT722_SDCA_CTL_FU_CH_GAIN, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
RT722_SDCA_CTL_FU_CH_GAIN, CH_R):
return true;
default:
return false;
}
}
static bool rt722_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200000d:
case 0x2000019:
case 0x2000020:
case 0x2000030:
case 0x2000046:
case 0x2000067:
case 0x2000084:
case 0x2000086:
return true;
default:
return false;
}
}
static const struct regmap_config rt722_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt722_sdca_readable_register,
.volatile_reg = rt722_sdca_volatile_register,
.max_register = 0x44ffffff,
.reg_defaults = rt722_sdca_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_reg_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt722_sdca_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt722_sdca_mbq_readable_register,
.volatile_reg = rt722_sdca_mbq_volatile_register,
.max_register = 0x41000312,
.reg_defaults = rt722_sdca_mbq_defaults,
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_mbq_defaults),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt722_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
if (status == SDW_SLAVE_UNATTACHED)
rt722->hw_init = false;
if (status == SDW_SLAVE_ATTACHED) {
if (rt722->hs_jack) {
/*
* Due to the SCP_SDCA_INTMASK will be cleared by any reset, and then
* if the device attached again, we will need to set the setting back.
* It could avoid losing the jack detection interrupt.
* This also could sync with the cache value as the rt722_sdca_jack_init set.
*/
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_6);
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
}
}
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt722->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt722_sdca_io_init(&slave->dev, slave);
}
static int rt722_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/*
* port = 1 for headphone playback
* port = 2 for headset-mic capture
* port = 3 for speaker playback
* port = 6 for digital-mic capture
*/
prop->source_ports = BIT(6) | BIT(2); /* BITMAP: 01000100 */
prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 200;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt722_sdca_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
int ret, stat;
int count = 0, retry = 3;
unsigned int sdca_cascade, scp_sdca_stat1, scp_sdca_stat2 = 0;
if (cancel_delayed_work_sync(&rt722->jack_detect_work)) {
dev_warn(&slave->dev, "%s the pending delayed_work was cancelled", __func__);
/* avoid the HID owner doesn't change to device */
if (rt722->scp_sdca_stat2)
scp_sdca_stat2 = rt722->scp_sdca_stat2;
}
/*
* The critical section below intentionally protects a rather large piece of code.
* We don't want to allow the system suspend to disable an interrupt while we are
* processing it, which could be problematic given the quirky SoundWire interrupt
* scheme. We do want however to prevent new workqueues from being scheduled if
* the disable_irq flag was set during system suspend.
*/
mutex_lock(&rt722->disable_irq_lock);
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
rt722->scp_sdca_stat1 = ret;
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
rt722->scp_sdca_stat2 = ret;
if (scp_sdca_stat2)
rt722->scp_sdca_stat2 |= scp_sdca_stat2;
do {
/* clear flag */
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_0) {
ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1,
SDW_SCP_SDCA_INT_SDCA_0, SDW_SCP_SDCA_INT_SDCA_0);
if (ret < 0)
goto io_error;
} else if (ret & SDW_SCP_SDCA_INTMASK_SDCA_6) {
ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1,
SDW_SCP_SDCA_INT_SDCA_6, SDW_SCP_SDCA_INT_SDCA_6);
if (ret < 0)
goto io_error;
}
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_8) {
ret = sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INT2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
if (ret < 0)
goto io_error;
}
/* check if flag clear or not */
ret = sdw_read_no_pm(rt722->slave, SDW_DP0_INT);
if (ret < 0)
goto io_error;
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
scp_sdca_stat1 = ret & SDW_SCP_SDCA_INTMASK_SDCA_0;
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
scp_sdca_stat2 = ret & SDW_SCP_SDCA_INTMASK_SDCA_8;
stat = scp_sdca_stat1 || scp_sdca_stat2 || sdca_cascade;
count++;
} while (stat != 0 && count < retry);
if (stat)
dev_warn(&slave->dev,
"%s scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
if (status->sdca_cascade && !rt722->disable_irq)
mod_delayed_work(system_power_efficient_wq,
&rt722->jack_detect_work, msecs_to_jiffies(30));
mutex_unlock(&rt722->disable_irq_lock);
return 0;
io_error:
mutex_unlock(&rt722->disable_irq_lock);
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static struct sdw_slave_ops rt722_sdca_slave_ops = {
.read_prop = rt722_sdca_read_prop,
.interrupt_callback = rt722_sdca_interrupt_callback,
.update_status = rt722_sdca_update_status,
};
static int rt722_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap, *mbq_regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt722_sdca_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt722_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt722_sdca_init(&slave->dev, regmap, mbq_regmap, slave);
}
static int rt722_sdca_sdw_remove(struct sdw_slave *slave)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
if (rt722->hw_init) {
cancel_delayed_work_sync(&rt722->jack_detect_work);
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
}
if (rt722->first_hw_init)
pm_runtime_disable(&slave->dev);
mutex_destroy(&rt722->calibrate_mutex);
mutex_destroy(&rt722->disable_irq_lock);
return 0;
}
static const struct sdw_device_id rt722_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x722, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt722_sdca_id);
static int __maybe_unused rt722_sdca_dev_suspend(struct device *dev)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
if (!rt722->hw_init)
return 0;
cancel_delayed_work_sync(&rt722->jack_detect_work);
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
regcache_cache_only(rt722->regmap, true);
regcache_cache_only(rt722->mbq_regmap, true);
return 0;
}
static int __maybe_unused rt722_sdca_dev_system_suspend(struct device *dev)
{
struct rt722_sdca_priv *rt722_sdca = dev_get_drvdata(dev);
struct sdw_slave *slave = dev_to_sdw_dev(dev);
int ret1, ret2;
if (!rt722_sdca->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt722_sdca->disable_irq_lock);
rt722_sdca->disable_irq = true;
ret1 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6, 0);
ret2 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8, 0);
mutex_unlock(&rt722_sdca->disable_irq_lock);
if (ret1 < 0 || ret2 < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable SDCA interrupts\n:", __func__);
}
return rt722_sdca_dev_suspend(dev);
}
#define RT722_PROBE_TIMEOUT 5000
static int __maybe_unused rt722_sdca_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
unsigned long time;
if (!rt722->first_hw_init)
return 0;
if (!slave->unattach_request) {
if (rt722->disable_irq == true) {
mutex_lock(&rt722->disable_irq_lock);
sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK1, SDW_SCP_SDCA_INTMASK_SDCA_6);
sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK2, SDW_SCP_SDCA_INTMASK_SDCA_8);
rt722->disable_irq = false;
mutex_unlock(&rt722->disable_irq_lock);
}
goto regmap_sync;
}
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT722_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt722->regmap, false);
regcache_sync(rt722->regmap);
regcache_cache_only(rt722->mbq_regmap, false);
regcache_sync(rt722->mbq_regmap);
return 0;
}
static const struct dev_pm_ops rt722_sdca_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt722_sdca_dev_system_suspend, rt722_sdca_dev_resume)
SET_RUNTIME_PM_OPS(rt722_sdca_dev_suspend, rt722_sdca_dev_resume, NULL)
};
static struct sdw_driver rt722_sdca_sdw_driver = {
.driver = {
.name = "rt722-sdca",
.owner = THIS_MODULE,
.pm = &rt722_sdca_pm,
},
.probe = rt722_sdca_sdw_probe,
.remove = rt722_sdca_sdw_remove,
.ops = &rt722_sdca_slave_ops,
.id_table = rt722_sdca_id,
};
module_sdw_driver(rt722_sdca_sdw_driver);
MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt722-sdca-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_clk.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "lpass-macro-common.h"
/* VA macro registers */
#define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
#define CDC_VA_MCLK_CONTROL_EN BIT(0)
#define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
#define CDC_VA_FS_CONTROL_EN BIT(0)
#define CDC_VA_FS_COUNTER_CLR BIT(1)
#define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008)
#define CDC_VA_SWR_RESET_MASK BIT(1)
#define CDC_VA_SWR_RESET_ENABLE BIT(1)
#define CDC_VA_SWR_CLK_EN_MASK BIT(0)
#define CDC_VA_SWR_CLK_ENABLE BIT(0)
#define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080)
#define CDC_VA_FS_BROADCAST_EN BIT(1)
#define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084)
#define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088)
#define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C)
#define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090)
#define CDC_VA_DMIC_EN_MASK BIT(0)
#define CDC_VA_DMIC_ENABLE BIT(0)
#define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1)
#define CDC_VA_DMIC_CLK_SEL_SHFT 1
#define CDC_VA_DMIC_CLK_SEL_DIV0 0x0
#define CDC_VA_DMIC_CLK_SEL_DIV1 0x2
#define CDC_VA_DMIC_CLK_SEL_DIV2 0x4
#define CDC_VA_DMIC_CLK_SEL_DIV3 0x6
#define CDC_VA_DMIC_CLK_SEL_DIV4 0x8
#define CDC_VA_DMIC_CLK_SEL_DIV5 0xa
#define CDC_VA_TOP_CSR_DMIC_CFG (0x0094)
#define CDC_VA_RESET_ALL_DMICS_MASK BIT(7)
#define CDC_VA_RESET_ALL_DMICS_RESET BIT(7)
#define CDC_VA_RESET_ALL_DMICS_DISABLE 0
#define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3)
#define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3)
#define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2)
#define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2)
#define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1)
#define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1)
#define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0)
#define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0)
#define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0
#define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C)
#define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0)
#define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4)
#define CDC_VA_TOP_CSR_I2S_CLK (0x00A8)
#define CDC_VA_TOP_CSR_I2S_RESET (0x00AC)
#define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0)
#define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4)
#define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8)
#define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC)
#define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0)
#define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4)
#define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8)
#define CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK (0xEE)
#define CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1 (0xCC)
#define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC)
#define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100)
#define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104)
#define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108)
#define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C)
#define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110)
#define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114)
#define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118)
#define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C)
#define CDC_VA_TX0_TX_PATH_CTL (0x0400)
#define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5)
#define CDC_VA_TX_PATH_CLK_EN BIT(5)
#define CDC_VA_TX_PATH_CLK_DISABLE 0
#define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4)
#define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4)
#define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0
#define CDC_VA_TX0_TX_PATH_CFG0 (0x0404)
#define CDC_VA_ADC_MODE_MASK GENMASK(2, 1)
#define CDC_VA_ADC_MODE_SHIFT 1
#define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5)
#define CF_MIN_3DB_4HZ 0x0
#define CF_MIN_3DB_75HZ 0x1
#define CF_MIN_3DB_150HZ 0x2
#define CDC_VA_TX0_TX_PATH_CFG1 (0x0408)
#define CDC_VA_TX0_TX_VOL_CTL (0x040C)
#define CDC_VA_TX0_TX_PATH_SEC0 (0x0410)
#define CDC_VA_TX0_TX_PATH_SEC1 (0x0414)
#define CDC_VA_TX0_TX_PATH_SEC2 (0x0418)
#define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1)
#define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1)
#define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0)
#define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0)
#define CDC_VA_TX_HPF_ZERO_GATE 0
#define CDC_VA_TX0_TX_PATH_SEC3 (0x041C)
#define CDC_VA_TX0_TX_PATH_SEC4 (0x0420)
#define CDC_VA_TX0_TX_PATH_SEC5 (0x0424)
#define CDC_VA_TX0_TX_PATH_SEC6 (0x0428)
#define CDC_VA_TX0_TX_PATH_SEC7 (0x042C)
#define CDC_VA_TX1_TX_PATH_CTL (0x0480)
#define CDC_VA_TX1_TX_PATH_CFG0 (0x0484)
#define CDC_VA_TX1_TX_PATH_CFG1 (0x0488)
#define CDC_VA_TX1_TX_VOL_CTL (0x048C)
#define CDC_VA_TX1_TX_PATH_SEC0 (0x0490)
#define CDC_VA_TX1_TX_PATH_SEC1 (0x0494)
#define CDC_VA_TX1_TX_PATH_SEC2 (0x0498)
#define CDC_VA_TX1_TX_PATH_SEC3 (0x049C)
#define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0)
#define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4)
#define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8)
#define CDC_VA_TX2_TX_PATH_CTL (0x0500)
#define CDC_VA_TX2_TX_PATH_CFG0 (0x0504)
#define CDC_VA_TX2_TX_PATH_CFG1 (0x0508)
#define CDC_VA_TX2_TX_VOL_CTL (0x050C)
#define CDC_VA_TX2_TX_PATH_SEC0 (0x0510)
#define CDC_VA_TX2_TX_PATH_SEC1 (0x0514)
#define CDC_VA_TX2_TX_PATH_SEC2 (0x0518)
#define CDC_VA_TX2_TX_PATH_SEC3 (0x051C)
#define CDC_VA_TX2_TX_PATH_SEC4 (0x0520)
#define CDC_VA_TX2_TX_PATH_SEC5 (0x0524)
#define CDC_VA_TX2_TX_PATH_SEC6 (0x0528)
#define CDC_VA_TX3_TX_PATH_CTL (0x0580)
#define CDC_VA_TX3_TX_PATH_CFG0 (0x0584)
#define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7)
#define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7)
#define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0
#define CDC_VA_TX3_TX_PATH_CFG1 (0x0588)
#define CDC_VA_TX3_TX_VOL_CTL (0x058C)
#define CDC_VA_TX3_TX_PATH_SEC0 (0x0590)
#define CDC_VA_TX3_TX_PATH_SEC1 (0x0594)
#define CDC_VA_TX3_TX_PATH_SEC2 (0x0598)
#define CDC_VA_TX3_TX_PATH_SEC3 (0x059C)
#define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0)
#define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4)
#define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8)
#define VA_MAX_OFFSET (0x07A8)
#define VA_MACRO_NUM_DECIMATORS 4
#define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE)
#define VA_MACRO_MCLK_FREQ 9600000
#define VA_MACRO_TX_PATH_OFFSET 0x80
#define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
#define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
enum {
VA_MACRO_AIF_INVALID = 0,
VA_MACRO_AIF1_CAP,
VA_MACRO_AIF2_CAP,
VA_MACRO_AIF3_CAP,
VA_MACRO_MAX_DAIS,
};
enum {
VA_MACRO_DEC0,
VA_MACRO_DEC1,
VA_MACRO_DEC2,
VA_MACRO_DEC3,
VA_MACRO_DEC4,
VA_MACRO_DEC5,
VA_MACRO_DEC6,
VA_MACRO_DEC7,
VA_MACRO_DEC_MAX,
};
enum {
VA_MACRO_CLK_DIV_2,
VA_MACRO_CLK_DIV_3,
VA_MACRO_CLK_DIV_4,
VA_MACRO_CLK_DIV_6,
VA_MACRO_CLK_DIV_8,
VA_MACRO_CLK_DIV_16,
};
#define VA_NUM_CLKS_MAX 3
struct va_macro {
struct device *dev;
unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
u16 dmic_clk_div;
bool has_swr_master;
int dec_mode[VA_MACRO_NUM_DECIMATORS];
struct regmap *regmap;
struct clk *mclk;
struct clk *macro;
struct clk *dcodec;
struct clk *fsgen;
struct clk_hw hw;
struct lpass_macro *pds;
s32 dmic_0_1_clk_cnt;
s32 dmic_2_3_clk_cnt;
s32 dmic_4_5_clk_cnt;
s32 dmic_6_7_clk_cnt;
u8 dmic_0_1_clk_div;
u8 dmic_2_3_clk_div;
u8 dmic_4_5_clk_div;
u8 dmic_6_7_clk_div;
};
#define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
struct va_macro_data {
bool has_swr_master;
};
static const struct va_macro_data sm8250_va_data = {
.has_swr_master = false,
};
static const struct va_macro_data sm8450_va_data = {
.has_swr_master = true,
};
static bool va_is_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_VA_TOP_CSR_CORE_ID_0:
case CDC_VA_TOP_CSR_CORE_ID_1:
case CDC_VA_TOP_CSR_CORE_ID_2:
case CDC_VA_TOP_CSR_CORE_ID_3:
case CDC_VA_TOP_CSR_DMIC0_CTL:
case CDC_VA_TOP_CSR_DMIC1_CTL:
case CDC_VA_TOP_CSR_DMIC2_CTL:
case CDC_VA_TOP_CSR_DMIC3_CTL:
return true;
}
return false;
}
static const struct reg_default va_defaults[] = {
/* VA macro */
{ CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
{ CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
{ CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
{ CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
{ CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
{ CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
{ CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
{ CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
{ CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
{ CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
{ CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
{ CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
{ CDC_VA_TOP_CSR_I2S_CLK, 0x00},
{ CDC_VA_TOP_CSR_I2S_RESET, 0x00},
{ CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
{ CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
{ CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
{ CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
{ CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
{ CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
{ CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
{ CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
/* VA core */
{ CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
{ CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
{ CDC_VA_TX0_TX_PATH_CTL, 0x04},
{ CDC_VA_TX0_TX_PATH_CFG0, 0x10},
{ CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
{ CDC_VA_TX0_TX_VOL_CTL, 0x00},
{ CDC_VA_TX0_TX_PATH_SEC0, 0x00},
{ CDC_VA_TX0_TX_PATH_SEC1, 0x00},
{ CDC_VA_TX0_TX_PATH_SEC2, 0x01},
{ CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
{ CDC_VA_TX0_TX_PATH_SEC4, 0x20},
{ CDC_VA_TX0_TX_PATH_SEC5, 0x00},
{ CDC_VA_TX0_TX_PATH_SEC6, 0x00},
{ CDC_VA_TX0_TX_PATH_SEC7, 0x25},
{ CDC_VA_TX1_TX_PATH_CTL, 0x04},
{ CDC_VA_TX1_TX_PATH_CFG0, 0x10},
{ CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
{ CDC_VA_TX1_TX_VOL_CTL, 0x00},
{ CDC_VA_TX1_TX_PATH_SEC0, 0x00},
{ CDC_VA_TX1_TX_PATH_SEC1, 0x00},
{ CDC_VA_TX1_TX_PATH_SEC2, 0x01},
{ CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
{ CDC_VA_TX1_TX_PATH_SEC4, 0x20},
{ CDC_VA_TX1_TX_PATH_SEC5, 0x00},
{ CDC_VA_TX1_TX_PATH_SEC6, 0x00},
{ CDC_VA_TX2_TX_PATH_CTL, 0x04},
{ CDC_VA_TX2_TX_PATH_CFG0, 0x10},
{ CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
{ CDC_VA_TX2_TX_VOL_CTL, 0x00},
{ CDC_VA_TX2_TX_PATH_SEC0, 0x00},
{ CDC_VA_TX2_TX_PATH_SEC1, 0x00},
{ CDC_VA_TX2_TX_PATH_SEC2, 0x01},
{ CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
{ CDC_VA_TX2_TX_PATH_SEC4, 0x20},
{ CDC_VA_TX2_TX_PATH_SEC5, 0x00},
{ CDC_VA_TX2_TX_PATH_SEC6, 0x00},
{ CDC_VA_TX3_TX_PATH_CTL, 0x04},
{ CDC_VA_TX3_TX_PATH_CFG0, 0x10},
{ CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
{ CDC_VA_TX3_TX_VOL_CTL, 0x00},
{ CDC_VA_TX3_TX_PATH_SEC0, 0x00},
{ CDC_VA_TX3_TX_PATH_SEC1, 0x00},
{ CDC_VA_TX3_TX_PATH_SEC2, 0x01},
{ CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
{ CDC_VA_TX3_TX_PATH_SEC4, 0x20},
{ CDC_VA_TX3_TX_PATH_SEC5, 0x00},
{ CDC_VA_TX3_TX_PATH_SEC6, 0x00},
};
static bool va_is_rw_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL:
case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL:
case CDC_VA_CLK_RST_CTRL_SWR_CONTROL:
case CDC_VA_TOP_CSR_TOP_CFG0:
case CDC_VA_TOP_CSR_DMIC0_CTL:
case CDC_VA_TOP_CSR_DMIC1_CTL:
case CDC_VA_TOP_CSR_DMIC2_CTL:
case CDC_VA_TOP_CSR_DMIC3_CTL:
case CDC_VA_TOP_CSR_DMIC_CFG:
case CDC_VA_TOP_CSR_SWR_MIC_CTL0:
case CDC_VA_TOP_CSR_SWR_MIC_CTL1:
case CDC_VA_TOP_CSR_SWR_MIC_CTL2:
case CDC_VA_TOP_CSR_DEBUG_BUS:
case CDC_VA_TOP_CSR_DEBUG_EN:
case CDC_VA_TOP_CSR_TX_I2S_CTL:
case CDC_VA_TOP_CSR_I2S_CLK:
case CDC_VA_TOP_CSR_I2S_RESET:
case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
case CDC_VA_INP_MUX_ADC_MUX0_CFG1:
case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
case CDC_VA_INP_MUX_ADC_MUX1_CFG1:
case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
case CDC_VA_INP_MUX_ADC_MUX2_CFG1:
case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
case CDC_VA_INP_MUX_ADC_MUX3_CFG1:
case CDC_VA_TX0_TX_PATH_CTL:
case CDC_VA_TX0_TX_PATH_CFG0:
case CDC_VA_TX0_TX_PATH_CFG1:
case CDC_VA_TX0_TX_VOL_CTL:
case CDC_VA_TX0_TX_PATH_SEC0:
case CDC_VA_TX0_TX_PATH_SEC1:
case CDC_VA_TX0_TX_PATH_SEC2:
case CDC_VA_TX0_TX_PATH_SEC3:
case CDC_VA_TX0_TX_PATH_SEC4:
case CDC_VA_TX0_TX_PATH_SEC5:
case CDC_VA_TX0_TX_PATH_SEC6:
case CDC_VA_TX0_TX_PATH_SEC7:
case CDC_VA_TX1_TX_PATH_CTL:
case CDC_VA_TX1_TX_PATH_CFG0:
case CDC_VA_TX1_TX_PATH_CFG1:
case CDC_VA_TX1_TX_VOL_CTL:
case CDC_VA_TX1_TX_PATH_SEC0:
case CDC_VA_TX1_TX_PATH_SEC1:
case CDC_VA_TX1_TX_PATH_SEC2:
case CDC_VA_TX1_TX_PATH_SEC3:
case CDC_VA_TX1_TX_PATH_SEC4:
case CDC_VA_TX1_TX_PATH_SEC5:
case CDC_VA_TX1_TX_PATH_SEC6:
case CDC_VA_TX2_TX_PATH_CTL:
case CDC_VA_TX2_TX_PATH_CFG0:
case CDC_VA_TX2_TX_PATH_CFG1:
case CDC_VA_TX2_TX_VOL_CTL:
case CDC_VA_TX2_TX_PATH_SEC0:
case CDC_VA_TX2_TX_PATH_SEC1:
case CDC_VA_TX2_TX_PATH_SEC2:
case CDC_VA_TX2_TX_PATH_SEC3:
case CDC_VA_TX2_TX_PATH_SEC4:
case CDC_VA_TX2_TX_PATH_SEC5:
case CDC_VA_TX2_TX_PATH_SEC6:
case CDC_VA_TX3_TX_PATH_CTL:
case CDC_VA_TX3_TX_PATH_CFG0:
case CDC_VA_TX3_TX_PATH_CFG1:
case CDC_VA_TX3_TX_VOL_CTL:
case CDC_VA_TX3_TX_PATH_SEC0:
case CDC_VA_TX3_TX_PATH_SEC1:
case CDC_VA_TX3_TX_PATH_SEC2:
case CDC_VA_TX3_TX_PATH_SEC3:
case CDC_VA_TX3_TX_PATH_SEC4:
case CDC_VA_TX3_TX_PATH_SEC5:
case CDC_VA_TX3_TX_PATH_SEC6:
return true;
}
return false;
}
static bool va_is_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_VA_TOP_CSR_CORE_ID_0:
case CDC_VA_TOP_CSR_CORE_ID_1:
case CDC_VA_TOP_CSR_CORE_ID_2:
case CDC_VA_TOP_CSR_CORE_ID_3:
return true;
}
return va_is_rw_register(dev, reg);
}
static const struct regmap_config va_regmap_config = {
.name = "va_macro",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.cache_type = REGCACHE_FLAT,
.reg_defaults = va_defaults,
.num_reg_defaults = ARRAY_SIZE(va_defaults),
.max_register = VA_MAX_OFFSET,
.volatile_reg = va_is_volatile_register,
.readable_reg = va_is_readable_register,
.writeable_reg = va_is_rw_register,
};
static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
{
struct regmap *regmap = va->regmap;
if (enable) {
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
CDC_VA_MCLK_CONTROL_EN,
CDC_VA_MCLK_CONTROL_EN);
/* clear the fs counter */
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR,
CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR);
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR,
CDC_VA_FS_CONTROL_EN);
regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
CDC_VA_FS_BROADCAST_EN,
CDC_VA_FS_BROADCAST_EN);
} else {
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
CDC_VA_MCLK_CONTROL_EN, 0x0);
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_VA_FS_CONTROL_EN, 0x0);
regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
CDC_VA_FS_BROADCAST_EN, 0x0);
}
return 0;
}
static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
{
struct regmap *regmap = va->regmap;
if (mclk_enable) {
va_clk_rsc_fs_gen_request(va, true);
regcache_mark_dirty(regmap);
regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET);
} else {
va_clk_rsc_fs_gen_request(va, false);
}
return 0;
}
static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct va_macro *va = snd_soc_component_get_drvdata(comp);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return clk_prepare_enable(va->fsgen);
case SND_SOC_DAPM_POST_PMD:
clk_disable_unprepare(va->fsgen);
}
return 0;
}
static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget =
snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component =
snd_soc_dapm_to_component(widget->dapm);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int val;
u16 mic_sel_reg;
val = ucontrol->value.enumerated.item[0];
switch (e->reg) {
case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
break;
case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
break;
case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
break;
case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
break;
default:
dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
__func__, e->reg);
return -EINVAL;
}
if (val != 0)
snd_soc_component_update_bits(component, mic_sel_reg,
CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
}
static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget =
snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component =
snd_soc_dapm_to_component(widget->dapm);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
u32 dai_id = widget->shift;
u32 dec_id = mc->shift;
struct va_macro *va = snd_soc_component_get_drvdata(component);
if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
ucontrol->value.integer.value[0] = 1;
else
ucontrol->value.integer.value[0] = 0;
return 0;
}
static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget =
snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component =
snd_soc_dapm_to_component(widget->dapm);
struct snd_soc_dapm_update *update = NULL;
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
u32 dai_id = widget->shift;
u32 dec_id = mc->shift;
u32 enable = ucontrol->value.integer.value[0];
struct va_macro *va = snd_soc_component_get_drvdata(component);
if (enable) {
set_bit(dec_id, &va->active_ch_mask[dai_id]);
va->active_ch_cnt[dai_id]++;
} else {
clear_bit(dec_id, &va->active_ch_mask[dai_id]);
va->active_ch_cnt[dai_id]--;
}
snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
return 0;
}
static int va_dmic_clk_enable(struct snd_soc_component *component,
u32 dmic, bool enable)
{
struct va_macro *va = snd_soc_component_get_drvdata(component);
u16 dmic_clk_reg;
s32 *dmic_clk_cnt;
u8 *dmic_clk_div;
u8 freq_change_mask;
u8 clk_div;
switch (dmic) {
case 0:
case 1:
dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
dmic_clk_div = &(va->dmic_0_1_clk_div);
dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL;
freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK;
break;
case 2:
case 3:
dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
dmic_clk_div = &(va->dmic_2_3_clk_div);
dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL;
freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK;
break;
case 4:
case 5:
dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
dmic_clk_div = &(va->dmic_4_5_clk_div);
dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL;
freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK;
break;
case 6:
case 7:
dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
dmic_clk_div = &(va->dmic_6_7_clk_div);
dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL;
freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK;
break;
default:
dev_err(component->dev, "%s: Invalid DMIC Selection\n",
__func__);
return -EINVAL;
}
if (enable) {
clk_div = va->dmic_clk_div;
(*dmic_clk_cnt)++;
if (*dmic_clk_cnt == 1) {
snd_soc_component_update_bits(component,
CDC_VA_TOP_CSR_DMIC_CFG,
CDC_VA_RESET_ALL_DMICS_MASK,
CDC_VA_RESET_ALL_DMICS_DISABLE);
snd_soc_component_update_bits(component, dmic_clk_reg,
CDC_VA_DMIC_CLK_SEL_MASK,
clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
snd_soc_component_update_bits(component, dmic_clk_reg,
CDC_VA_DMIC_EN_MASK,
CDC_VA_DMIC_ENABLE);
} else {
if (*dmic_clk_div > clk_div) {
snd_soc_component_update_bits(component,
CDC_VA_TOP_CSR_DMIC_CFG,
freq_change_mask,
freq_change_mask);
snd_soc_component_update_bits(component, dmic_clk_reg,
CDC_VA_DMIC_CLK_SEL_MASK,
clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
snd_soc_component_update_bits(component,
CDC_VA_TOP_CSR_DMIC_CFG,
freq_change_mask,
CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
} else {
clk_div = *dmic_clk_div;
}
}
*dmic_clk_div = clk_div;
} else {
(*dmic_clk_cnt)--;
if (*dmic_clk_cnt == 0) {
snd_soc_component_update_bits(component, dmic_clk_reg,
CDC_VA_DMIC_EN_MASK, 0);
clk_div = 0;
snd_soc_component_update_bits(component, dmic_clk_reg,
CDC_VA_DMIC_CLK_SEL_MASK,
clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
} else {
clk_div = va->dmic_clk_div;
if (*dmic_clk_div > clk_div) {
clk_div = va->dmic_clk_div;
snd_soc_component_update_bits(component,
CDC_VA_TOP_CSR_DMIC_CFG,
freq_change_mask,
freq_change_mask);
snd_soc_component_update_bits(component, dmic_clk_reg,
CDC_VA_DMIC_CLK_SEL_MASK,
clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
snd_soc_component_update_bits(component,
CDC_VA_TOP_CSR_DMIC_CFG,
freq_change_mask,
CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
} else {
clk_div = *dmic_clk_div;
}
}
*dmic_clk_div = clk_div;
}
return 0;
}
static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
unsigned int dmic = w->shift;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
va_dmic_clk_enable(comp, dmic, true);
break;
case SND_SOC_DAPM_POST_PMD:
va_dmic_clk_enable(comp, dmic, false);
break;
}
return 0;
}
static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
unsigned int decimator;
u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
u16 tx_gain_ctl_reg;
u8 hpf_cut_off_freq;
struct va_macro *va = snd_soc_component_get_drvdata(comp);
decimator = w->shift;
tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
VA_MACRO_TX_PATH_OFFSET * decimator;
hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 +
VA_MACRO_TX_PATH_OFFSET * decimator;
dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 +
VA_MACRO_TX_PATH_OFFSET * decimator;
tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL +
VA_MACRO_TX_PATH_OFFSET * decimator;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(comp,
dec_cfg_reg, CDC_VA_ADC_MODE_MASK,
va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
/* Enable TX PGA Mute */
break;
case SND_SOC_DAPM_POST_PMU:
/* Enable TX CLK */
snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
CDC_VA_TX_PATH_CLK_EN_MASK,
CDC_VA_TX_PATH_CLK_EN);
snd_soc_component_update_bits(comp, hpf_gate_reg,
CDC_VA_TX_HPF_ZERO_GATE_MASK,
CDC_VA_TX_HPF_ZERO_GATE);
usleep_range(1000, 1010);
hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
snd_soc_component_update_bits(comp, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
CF_MIN_3DB_150HZ << 5);
snd_soc_component_update_bits(comp, hpf_gate_reg,
CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
snd_soc_component_update_bits(comp,
hpf_gate_reg,
CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
0x0);
}
usleep_range(1000, 1010);
snd_soc_component_update_bits(comp, hpf_gate_reg,
CDC_VA_TX_HPF_ZERO_GATE_MASK,
CDC_VA_TX_HPF_ZERO_NO_GATE);
/*
* 6ms delay is required as per HW spec
*/
usleep_range(6000, 6010);
/* apply gain after decimator is enabled */
snd_soc_component_write(comp, tx_gain_ctl_reg,
snd_soc_component_read(comp, tx_gain_ctl_reg));
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable TX CLK */
snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
CDC_VA_TX_PATH_CLK_EN_MASK,
CDC_VA_TX_PATH_CLK_DISABLE);
break;
}
return 0;
}
static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct va_macro *va = snd_soc_component_get_drvdata(comp);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int path = e->shift_l;
ucontrol->value.enumerated.item[0] = va->dec_mode[path];
return 0;
}
static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
int value = ucontrol->value.enumerated.item[0];
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int path = e->shift_l;
struct va_macro *va = snd_soc_component_get_drvdata(comp);
va->dec_mode[path] = value;
return 0;
}
static int va_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int tx_fs_rate;
struct snd_soc_component *component = dai->component;
u32 decimator, sample_rate;
u16 tx_fs_reg;
struct device *va_dev = component->dev;
struct va_macro *va = snd_soc_component_get_drvdata(component);
sample_rate = params_rate(params);
switch (sample_rate) {
case 8000:
tx_fs_rate = 0;
break;
case 16000:
tx_fs_rate = 1;
break;
case 32000:
tx_fs_rate = 3;
break;
case 48000:
tx_fs_rate = 4;
break;
case 96000:
tx_fs_rate = 5;
break;
case 192000:
tx_fs_rate = 6;
break;
case 384000:
tx_fs_rate = 7;
break;
default:
dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
__func__, params_rate(params));
return -EINVAL;
}
for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
VA_MACRO_DEC_MAX) {
tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL +
VA_MACRO_TX_PATH_OFFSET * decimator;
snd_soc_component_update_bits(component, tx_fs_reg, 0x0F,
tx_fs_rate);
}
return 0;
}
static int va_macro_get_channel_map(struct snd_soc_dai *dai,
unsigned int *tx_num, unsigned int *tx_slot,
unsigned int *rx_num, unsigned int *rx_slot)
{
struct snd_soc_component *component = dai->component;
struct device *va_dev = component->dev;
struct va_macro *va = snd_soc_component_get_drvdata(component);
switch (dai->id) {
case VA_MACRO_AIF1_CAP:
case VA_MACRO_AIF2_CAP:
case VA_MACRO_AIF3_CAP:
*tx_slot = va->active_ch_mask[dai->id];
*tx_num = va->active_ch_cnt[dai->id];
break;
default:
dev_err(va_dev, "%s: Invalid AIF\n", __func__);
break;
}
return 0;
}
static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
struct va_macro *va = snd_soc_component_get_drvdata(component);
u16 tx_vol_ctl_reg, decimator;
for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
VA_MACRO_DEC_MAX) {
tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
VA_MACRO_TX_PATH_OFFSET * decimator;
if (mute)
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
CDC_VA_TX_PATH_PGA_MUTE_EN);
else
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
}
return 0;
}
static const struct snd_soc_dai_ops va_macro_dai_ops = {
.hw_params = va_macro_hw_params,
.get_channel_map = va_macro_get_channel_map,
.mute_stream = va_macro_digital_mute,
};
static struct snd_soc_dai_driver va_macro_dais[] = {
{
.name = "va_macro_tx1",
.id = VA_MACRO_AIF1_CAP,
.capture = {
.stream_name = "VA_AIF1 Capture",
.rates = VA_MACRO_RATES,
.formats = VA_MACRO_FORMATS,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &va_macro_dai_ops,
},
{
.name = "va_macro_tx2",
.id = VA_MACRO_AIF2_CAP,
.capture = {
.stream_name = "VA_AIF2 Capture",
.rates = VA_MACRO_RATES,
.formats = VA_MACRO_FORMATS,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &va_macro_dai_ops,
},
{
.name = "va_macro_tx3",
.id = VA_MACRO_AIF3_CAP,
.capture = {
.stream_name = "VA_AIF3 Capture",
.rates = VA_MACRO_RATES,
.formats = VA_MACRO_FORMATS,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &va_macro_dai_ops,
},
};
static const char * const adc_mux_text[] = {
"VA_DMIC", "SWR_MIC"
};
static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1,
0, adc_mux_text);
static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1,
0, adc_mux_text);
static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0",
va_dec0_enum);
static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1",
va_dec1_enum);
static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2",
va_dec2_enum);
static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3",
va_dec3_enum);
static const char * const dmic_mux_text[] = {
"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
"DMIC4", "DMIC5", "DMIC6", "DMIC7"
};
static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0,
4, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0,
4, dmic_mux_text);
static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0",
va_dmic0_enum, snd_soc_dapm_get_enum_double,
va_macro_put_dec_enum);
static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1",
va_dmic1_enum, snd_soc_dapm_get_enum_double,
va_macro_put_dec_enum);
static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2",
va_dmic2_enum, snd_soc_dapm_get_enum_double,
va_macro_put_dec_enum);
static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3",
va_dmic3_enum, snd_soc_dapm_get_enum_double,
va_macro_put_dec_enum);
static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
};
static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
};
static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
va_macro_tx_mixer_get, va_macro_tx_mixer_put),
};
static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0),
SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0),
SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0),
SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
VA_MACRO_AIF1_CAP, 0,
va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
VA_MACRO_AIF2_CAP, 0,
va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
VA_MACRO_AIF3_CAP, 0,
va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
SND_SOC_DAPM_INPUT("DMIC0 Pin"),
SND_SOC_DAPM_INPUT("DMIC1 Pin"),
SND_SOC_DAPM_INPUT("DMIC2 Pin"),
SND_SOC_DAPM_INPUT("DMIC3 Pin"),
SND_SOC_DAPM_INPUT("DMIC4 Pin"),
SND_SOC_DAPM_INPUT("DMIC5 Pin"),
SND_SOC_DAPM_INPUT("DMIC6 Pin"),
SND_SOC_DAPM_INPUT("DMIC7 Pin"),
SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
&va_dec0_mux, va_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
&va_dec1_mux, va_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
&va_dec2_mux, va_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
&va_dec3_mux, va_macro_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
va_macro_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route va_audio_map[] = {
{"VA_AIF1 CAP", NULL, "VA_MCLK"},
{"VA_AIF2 CAP", NULL, "VA_MCLK"},
{"VA_AIF3 CAP", NULL, "VA_MCLK"},
{"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
{"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
{"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
{"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
{"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
{"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
{"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
{"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
{"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
{"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
{"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
{"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
{"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
{"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
{"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
{"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
{"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
{"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
{"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
{"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
{"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
{"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
{"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
{"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
{"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
{"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
{"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
{"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
{"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
{"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
{"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
{"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
{"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
{"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
{"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
{"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
{"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
{"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
{"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
{"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
{"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
{"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
{"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
{"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
{"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
{"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
{"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
{"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
{"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
{"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
{"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
{ "VA DMIC0", NULL, "DMIC0 Pin" },
{ "VA DMIC1", NULL, "DMIC1 Pin" },
{ "VA DMIC2", NULL, "DMIC2 Pin" },
{ "VA DMIC3", NULL, "DMIC3 Pin" },
{ "VA DMIC4", NULL, "DMIC4 Pin" },
{ "VA DMIC5", NULL, "DMIC5 Pin" },
{ "VA DMIC6", NULL, "DMIC6 Pin" },
{ "VA DMIC7", NULL, "DMIC7 Pin" },
};
static const char * const dec_mode_mux_text[] = {
"ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
};
static const struct soc_enum dec_mode_mux_enum[] = {
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
dec_mode_mux_text),
};
static const struct snd_kcontrol_new va_macro_snd_controls[] = {
SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL,
-84, 40, digital_gain),
SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0],
va_macro_dec_mode_get, va_macro_dec_mode_put),
SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1],
va_macro_dec_mode_get, va_macro_dec_mode_put),
SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2],
va_macro_dec_mode_get, va_macro_dec_mode_put),
SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3],
va_macro_dec_mode_get, va_macro_dec_mode_put),
};
static int va_macro_component_probe(struct snd_soc_component *component)
{
struct va_macro *va = snd_soc_component_get_drvdata(component);
snd_soc_component_init_regmap(component, va->regmap);
return 0;
}
static const struct snd_soc_component_driver va_macro_component_drv = {
.name = "VA MACRO",
.probe = va_macro_component_probe,
.controls = va_macro_snd_controls,
.num_controls = ARRAY_SIZE(va_macro_snd_controls),
.dapm_widgets = va_macro_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets),
.dapm_routes = va_audio_map,
.num_dapm_routes = ARRAY_SIZE(va_audio_map),
};
static int fsgen_gate_enable(struct clk_hw *hw)
{
struct va_macro *va = to_va_macro(hw);
struct regmap *regmap = va->regmap;
int ret;
ret = va_macro_mclk_enable(va, true);
if (va->has_swr_master)
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
return ret;
}
static void fsgen_gate_disable(struct clk_hw *hw)
{
struct va_macro *va = to_va_macro(hw);
struct regmap *regmap = va->regmap;
if (va->has_swr_master)
regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
CDC_VA_SWR_CLK_EN_MASK, 0x0);
va_macro_mclk_enable(va, false);
}
static int fsgen_gate_is_enabled(struct clk_hw *hw)
{
struct va_macro *va = to_va_macro(hw);
int val;
regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
return !!(val & CDC_VA_FS_BROADCAST_EN);
}
static const struct clk_ops fsgen_gate_ops = {
.prepare = fsgen_gate_enable,
.unprepare = fsgen_gate_disable,
.is_enabled = fsgen_gate_is_enabled,
};
static int va_macro_register_fsgen_output(struct va_macro *va)
{
struct clk *parent = va->mclk;
struct device *dev = va->dev;
struct device_node *np = dev->of_node;
const char *parent_clk_name;
const char *clk_name = "fsgen";
struct clk_init_data init;
int ret;
parent_clk_name = __clk_get_name(parent);
of_property_read_string(np, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = &fsgen_gate_ops;
init.flags = 0;
init.parent_names = &parent_clk_name;
init.num_parents = 1;
va->hw.init = &init;
ret = devm_clk_hw_register(va->dev, &va->hw);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
}
static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
struct va_macro *va)
{
u32 div_factor;
u32 mclk_rate = VA_MACRO_MCLK_FREQ;
if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0)
goto undefined_rate;
div_factor = mclk_rate / dmic_sample_rate;
switch (div_factor) {
case 2:
va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
break;
case 3:
va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
break;
case 4:
va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
break;
case 6:
va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
break;
case 8:
va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
break;
case 16:
va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
break;
default:
/* Any other DIV factor is invalid */
goto undefined_rate;
}
return dmic_sample_rate;
undefined_rate:
dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
__func__, dmic_sample_rate, mclk_rate);
dmic_sample_rate = 0;
return dmic_sample_rate;
}
static int va_macro_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct va_macro_data *data;
struct va_macro *va;
void __iomem *base;
u32 sample_rate = 0;
int ret;
va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
if (!va)
return -ENOMEM;
va->dev = dev;
va->macro = devm_clk_get_optional(dev, "macro");
if (IS_ERR(va->macro))
return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n");
va->dcodec = devm_clk_get_optional(dev, "dcodec");
if (IS_ERR(va->dcodec))
return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n");
va->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(va->mclk))
return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n");
va->pds = lpass_macro_pds_init(dev);
if (IS_ERR(va->pds))
return PTR_ERR(va->pds);
ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
&sample_rate);
if (ret) {
dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
} else {
ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
if (!ret) {
ret = -EINVAL;
goto err;
}
}
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
ret = PTR_ERR(base);
goto err;
}
va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config);
if (IS_ERR(va->regmap)) {
ret = -EINVAL;
goto err;
}
dev_set_drvdata(dev, va);
data = of_device_get_match_data(dev);
va->has_swr_master = data->has_swr_master;
/* mclk rate */
clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
ret = clk_prepare_enable(va->macro);
if (ret)
goto err;
ret = clk_prepare_enable(va->dcodec);
if (ret)
goto err_dcodec;
ret = clk_prepare_enable(va->mclk);
if (ret)
goto err_mclk;
if (va->has_swr_master) {
/* Set default CLK div to 1 */
regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,
CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,
CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
}
if (va->has_swr_master) {
regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
CDC_VA_SWR_RESET_MASK, CDC_VA_SWR_RESET_ENABLE);
regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
CDC_VA_SWR_RESET_MASK, 0x0);
}
ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
va_macro_dais,
ARRAY_SIZE(va_macro_dais));
if (ret)
goto err_clkout;
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = va_macro_register_fsgen_output(va);
if (ret)
goto err_clkout;
va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
if (IS_ERR(va->fsgen)) {
ret = PTR_ERR(va->fsgen);
goto err_clkout;
}
return 0;
err_clkout:
clk_disable_unprepare(va->mclk);
err_mclk:
clk_disable_unprepare(va->dcodec);
err_dcodec:
clk_disable_unprepare(va->macro);
err:
lpass_macro_pds_exit(va->pds);
return ret;
}
static void va_macro_remove(struct platform_device *pdev)
{
struct va_macro *va = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(va->mclk);
clk_disable_unprepare(va->dcodec);
clk_disable_unprepare(va->macro);
lpass_macro_pds_exit(va->pds);
}
static int __maybe_unused va_macro_runtime_suspend(struct device *dev)
{
struct va_macro *va = dev_get_drvdata(dev);
regcache_cache_only(va->regmap, true);
regcache_mark_dirty(va->regmap);
clk_disable_unprepare(va->mclk);
return 0;
}
static int __maybe_unused va_macro_runtime_resume(struct device *dev)
{
struct va_macro *va = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(va->mclk);
if (ret) {
dev_err(va->dev, "unable to prepare mclk\n");
return ret;
}
regcache_cache_only(va->regmap, false);
regcache_sync(va->regmap);
return 0;
}
static const struct dev_pm_ops va_macro_pm_ops = {
SET_RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL)
};
static const struct of_device_id va_macro_dt_match[] = {
{ .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
{ .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
{ .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
{ .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },
{}
};
MODULE_DEVICE_TABLE(of, va_macro_dt_match);
static struct platform_driver va_macro_driver = {
.driver = {
.name = "va_macro",
.of_match_table = va_macro_dt_match,
.suppress_bind_attrs = true,
.pm = &va_macro_pm_ops,
},
.probe = va_macro_probe,
.remove_new = va_macro_remove,
};
module_platform_driver(va_macro_driver);
MODULE_DESCRIPTION("VA macro driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/lpass-va-macro.c |
// SPDX-License-Identifier: GPL-2.0
//
// ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
//
// Copyright (C) 2009 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
//
// Based on wm8731.c by Richard Purdie
// Based on ak4535.c by Richard Purdie
// Based on wm8753.c by Liam Girdwood
/* ** CAUTION **
*
* This is very simple driver.
* It can use headphone output / stereo input only
*
* AK4642 is tested.
* AK4643 is tested.
* AK4648 is tested.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#define PW_MGMT1 0x00
#define PW_MGMT2 0x01
#define SG_SL1 0x02
#define SG_SL2 0x03
#define MD_CTL1 0x04
#define MD_CTL2 0x05
#define TIMER 0x06
#define ALC_CTL1 0x07
#define ALC_CTL2 0x08
#define L_IVC 0x09
#define L_DVC 0x0a
#define ALC_CTL3 0x0b
#define R_IVC 0x0c
#define R_DVC 0x0d
#define MD_CTL3 0x0e
#define MD_CTL4 0x0f
#define PW_MGMT3 0x10
#define DF_S 0x11
#define FIL3_0 0x12
#define FIL3_1 0x13
#define FIL3_2 0x14
#define FIL3_3 0x15
#define EQ_0 0x16
#define EQ_1 0x17
#define EQ_2 0x18
#define EQ_3 0x19
#define EQ_4 0x1a
#define EQ_5 0x1b
#define FIL1_0 0x1c
#define FIL1_1 0x1d
#define FIL1_2 0x1e
#define FIL1_3 0x1f /* The maximum valid register for ak4642 */
#define PW_MGMT4 0x20
#define MD_CTL5 0x21
#define LO_MS 0x22
#define HP_MS 0x23
#define SPK_MS 0x24 /* The maximum valid register for ak4643 */
#define EQ_FBEQAB 0x25
#define EQ_FBEQCD 0x26
#define EQ_FBEQE 0x27 /* The maximum valid register for ak4648 */
/* PW_MGMT1*/
#define PMVCM (1 << 6) /* VCOM Power Management */
#define PMMIN (1 << 5) /* MIN Input Power Management */
#define PMDAC (1 << 2) /* DAC Power Management */
#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
/* PW_MGMT2 */
#define HPMTN (1 << 6)
#define PMHPL (1 << 5)
#define PMHPR (1 << 4)
#define MS (1 << 3) /* master/slave select */
#define MCKO (1 << 1)
#define PMPLL (1 << 0)
#define PMHP_MASK (PMHPL | PMHPR)
#define PMHP PMHP_MASK
/* PW_MGMT3 */
#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
/* SG_SL1 */
#define MINS (1 << 6) /* Switch from MIN to Speaker */
#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
#define PMMP (1 << 2) /* MPWR pin Power Management */
#define MGAIN0 (1 << 0) /* MIC amp gain*/
/* SG_SL2 */
#define LOPS (1 << 6) /* Stero Line-out Power Save Mode */
/* TIMER */
#define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
#define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
/* ALC_CTL1 */
#define ALC (1 << 5) /* ALC Enable */
#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
/* MD_CTL1 */
#define PLL3 (1 << 7)
#define PLL2 (1 << 6)
#define PLL1 (1 << 5)
#define PLL0 (1 << 4)
#define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
#define BCKO_MASK (1 << 3)
#define BCKO_64 BCKO_MASK
#define DIF_MASK (3 << 0)
#define DSP (0 << 0)
#define RIGHT_J (1 << 0)
#define LEFT_J (2 << 0)
#define I2S (3 << 0)
/* MD_CTL2 */
#define FSs(val) (((val & 0x7) << 0) | ((val & 0x8) << 2))
#define PSs(val) ((val & 0x3) << 6)
/* MD_CTL3 */
#define BST1 (1 << 3)
/* MD_CTL4 */
#define DACH (1 << 0)
struct ak4642_drvdata {
const struct regmap_config *regmap_config;
int extended_frequencies;
};
struct ak4642_priv {
const struct ak4642_drvdata *drvdata;
struct clk *mcko;
};
/*
* Playback Volume (table 39)
*
* max : 0x00 : +12.0 dB
* ( 0.5 dB step )
* min : 0xFE : -115.0 dB
* mute: 0xFF
*/
static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
static const struct snd_kcontrol_new ak4642_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
0, 0xFF, 1, out_tlv),
SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
};
static const struct snd_kcontrol_new ak4642_headphone_control =
SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
};
/* event handlers */
static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
case SND_SOC_DAPM_PRE_PMU:
/* Power save mode ON */
snd_soc_component_update_bits(component, SG_SL2, LOPS, LOPS);
break;
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_POST_PMD:
/* Power save mode OFF */
msleep(300);
snd_soc_component_update_bits(component, SG_SL2, LOPS, 0);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
/* Outputs */
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
&ak4642_headphone_control),
SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
&ak4642_lout_mixer_controls[0],
ARRAY_SIZE(ak4642_lout_mixer_controls),
ak4642_lout_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
/* DAC */
SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
};
static const struct snd_soc_dapm_route ak4642_intercon[] = {
/* Outputs */
{"HPOUTL", NULL, "HPL Out"},
{"HPOUTR", NULL, "HPR Out"},
{"LINEOUT", NULL, "LINEOUT Mixer"},
{"HPL Out", NULL, "Headphone Enable"},
{"HPR Out", NULL, "Headphone Enable"},
{"Headphone Enable", "Switch", "DACH"},
{"DACH", NULL, "DAC"},
{"LINEOUT Mixer", "DACL", "DAC"},
{ "DAC", NULL, "Playback" },
};
/*
* ak4642 register cache
*/
static const struct reg_default ak4643_reg[] = {
{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
{ 36, 0x00 },
};
/* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
and ak4643. So we reuse the ak4643 reg_default for ak4642.
The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
so define NUM_AK4642_REG_DEFAULTS for ak4642.
*/
#define ak4642_reg ak4643_reg
#define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1)
static const struct reg_default ak4648_reg[] = {
{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
};
static int ak4642_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_soc_component *component = dai->component;
if (is_play) {
/*
* start headphone output
*
* PLL, Master Mode
* Audio I/F Format :MSB justified (ADC & DAC)
* Bass Boost Level : Middle
*
* This operation came from example code of
* "ASAHI KASEI AK4642" (japanese) manual p97.
*/
snd_soc_component_write(component, L_IVC, 0x91); /* volume */
snd_soc_component_write(component, R_IVC, 0x91); /* volume */
} else {
/*
* start stereo input
*
* PLL Master Mode
* Audio I/F Format:MSB justified (ADC & DAC)
* Pre MIC AMP:+20dB
* MIC Power On
* ALC setting:Refer to Table 35
* ALC bit=“1”
*
* This operation came from example code of
* "ASAHI KASEI AK4642" (japanese) manual p94.
*/
snd_soc_component_update_bits(component, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
snd_soc_component_write(component, TIMER, ZTM(0x3) | WTM(0x3));
snd_soc_component_write(component, ALC_CTL1, ALC | LMTH0);
snd_soc_component_update_bits(component, PW_MGMT1, PMADL, PMADL);
snd_soc_component_update_bits(component, PW_MGMT3, PMADR, PMADR);
}
return 0;
}
static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_soc_component *component = dai->component;
if (is_play) {
} else {
/* stop stereo input */
snd_soc_component_update_bits(component, PW_MGMT1, PMADL, 0);
snd_soc_component_update_bits(component, PW_MGMT3, PMADR, 0);
snd_soc_component_update_bits(component, ALC_CTL1, ALC, 0);
}
}
static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
u8 pll;
int extended_freq = 0;
switch (freq) {
case 11289600:
pll = PLL2;
break;
case 12288000:
pll = PLL2 | PLL0;
break;
case 12000000:
pll = PLL2 | PLL1;
break;
case 24000000:
pll = PLL2 | PLL1 | PLL0;
break;
case 13500000:
pll = PLL3 | PLL2;
break;
case 27000000:
pll = PLL3 | PLL2 | PLL0;
break;
case 19200000:
pll = PLL3;
extended_freq = 1;
break;
case 13000000:
pll = PLL3 | PLL2 | PLL1;
extended_freq = 1;
break;
case 26000000:
pll = PLL3 | PLL2 | PLL1 | PLL0;
extended_freq = 1;
break;
default:
return -EINVAL;
}
if (extended_freq && !priv->drvdata->extended_frequencies)
return -EINVAL;
snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll);
return 0;
}
static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u8 data;
u8 bcko;
data = MCKO | PMPLL; /* use MCKO */
bcko = 0;
/* set clocking for audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
data |= MS;
bcko = BCKO_64;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, PW_MGMT2, MS | MCKO | PMPLL, data);
snd_soc_component_update_bits(component, MD_CTL1, BCKO_MASK, bcko);
/* format type */
data = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
data = LEFT_J;
break;
case SND_SOC_DAIFMT_I2S:
data = I2S;
break;
/* FIXME
* Please add RIGHT_J / DSP support here
*/
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, MD_CTL1, DIF_MASK, data);
return 0;
}
static int ak4642_set_mcko(struct snd_soc_component *component,
u32 frequency)
{
static const u32 fs_list[] = {
[0] = 8000,
[1] = 12000,
[2] = 16000,
[3] = 24000,
[4] = 7350,
[5] = 11025,
[6] = 14700,
[7] = 22050,
[10] = 32000,
[11] = 48000,
[14] = 29400,
[15] = 44100,
};
static const u32 ps_list[] = {
[0] = 256,
[1] = 128,
[2] = 64,
[3] = 32
};
int ps, fs;
for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {
for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {
if (frequency == ps_list[ps] * fs_list[fs]) {
snd_soc_component_write(component, MD_CTL2,
PSs(ps) | FSs(fs));
return 0;
}
}
}
return 0;
}
static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
u32 rate = clk_get_rate(priv->mcko);
if (!rate)
rate = params_rate(params) * 256;
return ak4642_set_mcko(component, rate);
}
static int ak4642_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component, PW_MGMT1, 0x00);
break;
default:
snd_soc_component_update_bits(component, PW_MGMT1, PMVCM, PMVCM);
break;
}
return 0;
}
static const struct snd_soc_dai_ops ak4642_dai_ops = {
.startup = ak4642_dai_startup,
.shutdown = ak4642_dai_shutdown,
.set_sysclk = ak4642_dai_set_sysclk,
.set_fmt = ak4642_dai_set_fmt,
.hw_params = ak4642_dai_hw_params,
};
static struct snd_soc_dai_driver ak4642_dai = {
.name = "ak4642-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE },
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE },
.ops = &ak4642_dai_ops,
.symmetric_rate = 1,
};
static int ak4642_suspend(struct snd_soc_component *component)
{
struct regmap *regmap = dev_get_regmap(component->dev, NULL);
regcache_cache_only(regmap, true);
regcache_mark_dirty(regmap);
return 0;
}
static int ak4642_resume(struct snd_soc_component *component)
{
struct regmap *regmap = dev_get_regmap(component->dev, NULL);
regcache_cache_only(regmap, false);
regcache_sync(regmap);
return 0;
}
static int ak4642_probe(struct snd_soc_component *component)
{
struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
if (priv->mcko)
ak4642_set_mcko(component, clk_get_rate(priv->mcko));
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_ak4642 = {
.probe = ak4642_probe,
.suspend = ak4642_suspend,
.resume = ak4642_resume,
.set_bias_level = ak4642_set_bias_level,
.controls = ak4642_snd_controls,
.num_controls = ARRAY_SIZE(ak4642_snd_controls),
.dapm_widgets = ak4642_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
.dapm_routes = ak4642_intercon,
.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
.idle_bias_on = 1,
.endianness = 1,
};
static const struct regmap_config ak4642_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = FIL1_3,
.reg_defaults = ak4642_reg,
.num_reg_defaults = NUM_AK4642_REG_DEFAULTS,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config ak4643_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = SPK_MS,
.reg_defaults = ak4643_reg,
.num_reg_defaults = ARRAY_SIZE(ak4643_reg),
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config ak4648_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = EQ_FBEQE,
.reg_defaults = ak4648_reg,
.num_reg_defaults = ARRAY_SIZE(ak4648_reg),
.cache_type = REGCACHE_RBTREE,
};
static const struct ak4642_drvdata ak4642_drvdata = {
.regmap_config = &ak4642_regmap,
};
static const struct ak4642_drvdata ak4643_drvdata = {
.regmap_config = &ak4643_regmap,
};
static const struct ak4642_drvdata ak4648_drvdata = {
.regmap_config = &ak4648_regmap,
.extended_frequencies = 1,
};
#ifdef CONFIG_COMMON_CLK
static struct clk *ak4642_of_parse_mcko(struct device *dev)
{
struct device_node *np = dev->of_node;
struct clk *clk;
const char *clk_name = np->name;
const char *parent_clk_name = NULL;
u32 rate;
if (of_property_read_u32(np, "clock-frequency", &rate))
return NULL;
if (of_property_read_bool(np, "clocks"))
parent_clk_name = of_clk_get_parent_name(np, 0);
of_property_read_string(np, "clock-output-names", &clk_name);
clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);
if (!IS_ERR(clk))
of_clk_add_provider(np, of_clk_src_simple_get, clk);
return clk;
}
#else
#define ak4642_of_parse_mcko(d) 0
#endif
static const struct of_device_id ak4642_of_match[];
static const struct i2c_device_id ak4642_i2c_id[];
static int ak4642_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct device_node *np = dev->of_node;
const struct ak4642_drvdata *drvdata = NULL;
struct regmap *regmap;
struct ak4642_priv *priv;
struct clk *mcko = NULL;
if (np) {
const struct of_device_id *of_id;
mcko = ak4642_of_parse_mcko(dev);
if (IS_ERR(mcko))
mcko = NULL;
of_id = of_match_device(ak4642_of_match, dev);
if (of_id)
drvdata = of_id->data;
} else {
const struct i2c_device_id *id =
i2c_match_id(ak4642_i2c_id, i2c);
drvdata = (const struct ak4642_drvdata *)id->driver_data;
}
if (!drvdata) {
dev_err(dev, "Unknown device type\n");
return -EINVAL;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->drvdata = drvdata;
priv->mcko = mcko;
i2c_set_clientdata(i2c, priv);
regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return devm_snd_soc_register_component(dev,
&soc_component_dev_ak4642, &ak4642_dai, 1);
}
static const struct of_device_id ak4642_of_match[] = {
{ .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata},
{ .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata},
{ .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata},
{},
};
MODULE_DEVICE_TABLE(of, ak4642_of_match);
static const struct i2c_device_id ak4642_i2c_id[] = {
{ "ak4642", (kernel_ulong_t)&ak4642_drvdata },
{ "ak4643", (kernel_ulong_t)&ak4643_drvdata },
{ "ak4648", (kernel_ulong_t)&ak4648_drvdata },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
static struct i2c_driver ak4642_i2c_driver = {
.driver = {
.name = "ak4642-codec",
.of_match_table = ak4642_of_match,
},
.probe = ak4642_i2c_probe,
.id_table = ak4642_i2c_id,
};
module_i2c_driver(ak4642_i2c_driver);
MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/ak4642.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt715-sdca-sdw.c -- rt715 ALSA SoC audio driver
//
// Copyright(c) 2020 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "rt715-sdca.h"
#include "rt715-sdca-sdw.h"
static bool rt715_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201a ... 0x2027:
case 0x2029 ... 0x202a:
case 0x202d ... 0x2034:
case 0x2200 ... 0x2204:
case 0x2206 ... 0x2212:
case 0x2230 ... 0x2239:
case 0x2f5b:
case SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00):
return true;
default:
return false;
}
}
static bool rt715_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x201b:
case 0x201c:
case 0x201d:
case 0x201f:
case 0x2021:
case 0x2023:
case 0x2230:
case 0x202d ... 0x202f: /* BRA */
case 0x2200 ... 0x2212: /* i2c debug */
case 0x2f07:
case 0x2f1b ... 0x2f1e:
case 0x2f30 ... 0x2f34:
case 0x2f50 ... 0x2f51:
case 0x2f53 ... 0x2f59:
case 0x2f5c ... 0x2f5f:
case SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00): /* VAD Searching status */
return true;
default:
return false;
}
}
static bool rt715_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200002b:
case 0x2000036:
case 0x2000037:
case 0x2000039:
case 0x2000044:
case 0x6100000:
return true;
default:
return false;
}
}
static bool rt715_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
return true;
default:
return false;
}
}
static const struct regmap_config rt715_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt715_sdca_readable_register,
.volatile_reg = rt715_sdca_volatile_register,
.max_register = 0x43ffffff,
.reg_defaults = rt715_reg_defaults_sdca,
.num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults_sdca),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt715_sdca_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt715_sdca_mbq_readable_register,
.volatile_reg = rt715_sdca_mbq_volatile_register,
.max_register = 0x43ffffff,
.reg_defaults = rt715_mbq_reg_defaults_sdca,
.num_reg_defaults = ARRAY_SIZE(rt715_mbq_reg_defaults_sdca),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int rt715_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt715_sdca_priv *rt715 = dev_get_drvdata(&slave->dev);
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt715->hw_init || status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt715_sdca_io_init(&slave->dev, slave);
}
static int rt715_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval, i;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->paging_support = true;
/* first we need to allocate memory for set bits in port lists */
prop->source_ports = 0x50;/* BITMAP: 01010000 */
prop->sink_ports = 0x0; /* BITMAP: 00000000 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
dpn = prop->src_dpn_prop;
i = 0;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* set the timeout values */
prop->clk_stop_timeout = 200;
return 0;
}
static const struct sdw_slave_ops rt715_sdca_slave_ops = {
.read_prop = rt715_sdca_read_prop,
.update_status = rt715_sdca_update_status,
};
static int rt715_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *mbq_regmap, *regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt715_sdca_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt715_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt715_sdca_init(&slave->dev, mbq_regmap, regmap, slave);
}
static int rt715_sdca_sdw_remove(struct sdw_slave *slave)
{
pm_runtime_disable(&slave->dev);
return 0;
}
static const struct sdw_device_id rt715_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x3, 0x1, 0),
SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt715_sdca_id);
static int __maybe_unused rt715_dev_suspend(struct device *dev)
{
struct rt715_sdca_priv *rt715 = dev_get_drvdata(dev);
if (!rt715->hw_init)
return 0;
regcache_cache_only(rt715->regmap, true);
regcache_mark_dirty(rt715->regmap);
regcache_cache_only(rt715->mbq_regmap, true);
regcache_mark_dirty(rt715->mbq_regmap);
return 0;
}
#define RT715_PROBE_TIMEOUT 5000
static int __maybe_unused rt715_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt715_sdca_priv *rt715 = dev_get_drvdata(dev);
unsigned long time;
if (!rt715->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->enumeration_complete,
msecs_to_jiffies(RT715_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Enumeration not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt715->regmap, false);
regcache_sync_region(rt715->regmap,
SDW_SDCA_CTL(FUN_JACK_CODEC, RT715_SDCA_ST_EN, RT715_SDCA_ST_CTRL,
CH_00),
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00));
regcache_cache_only(rt715->mbq_regmap, false);
regcache_sync_region(rt715->mbq_regmap, 0x2000000, 0x61020ff);
regcache_sync_region(rt715->mbq_regmap,
SDW_SDCA_CTL(FUN_JACK_CODEC, RT715_SDCA_ST_EN, RT715_SDCA_ST_CTRL,
CH_00),
SDW_SDCA_CTL(FUN_MIC_ARRAY, RT715_SDCA_SMPU_TRIG_ST_EN,
RT715_SDCA_SMPU_TRIG_ST_CTRL, CH_00));
return 0;
}
static const struct dev_pm_ops rt715_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume)
SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL)
};
static struct sdw_driver rt715_sdw_driver = {
.driver = {
.name = "rt715-sdca",
.owner = THIS_MODULE,
.pm = &rt715_pm,
},
.probe = rt715_sdca_sdw_probe,
.remove = rt715_sdca_sdw_remove,
.ops = &rt715_sdca_slave_ops,
.id_table = rt715_sdca_id,
};
module_sdw_driver(rt715_sdw_driver);
MODULE_DESCRIPTION("ASoC RT715 driver SDW SDCA");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt715-sdca-sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l56.c -- CS42L51 ALSA SoC I2C audio driver
*
* Copyright 2014 CirrusLogic, Inc.
*
* Author: Brian Austin <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <sound/soc.h>
#include "cs42l51.h"
static struct i2c_device_id cs42l51_i2c_id[] = {
{"cs42l51", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs42l51_i2c_id);
static const struct of_device_id cs42l51_of_match[] = {
{ .compatible = "cirrus,cs42l51", },
{ }
};
MODULE_DEVICE_TABLE(of, cs42l51_of_match);
static int cs42l51_i2c_probe(struct i2c_client *i2c)
{
struct regmap_config config;
config = cs42l51_regmap;
return cs42l51_probe(&i2c->dev, devm_regmap_init_i2c(i2c, &config));
}
static void cs42l51_i2c_remove(struct i2c_client *i2c)
{
cs42l51_remove(&i2c->dev);
}
static const struct dev_pm_ops cs42l51_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(cs42l51_suspend, cs42l51_resume)
};
static struct i2c_driver cs42l51_i2c_driver = {
.driver = {
.name = "cs42l51",
.of_match_table = cs42l51_of_match,
.pm = &cs42l51_pm_ops,
},
.probe = cs42l51_i2c_probe,
.remove = cs42l51_i2c_remove,
.id_table = cs42l51_i2c_id,
};
module_i2c_driver(cs42l51_i2c_driver);
MODULE_DESCRIPTION("ASoC CS42L51 I2C Driver");
MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l51-i2c.c |
// SPDX-License-Identifier: GPL-2.0
//
// Analog Devices ADAU7118 8 channel PDM-to-I2S/TDM Converter driver
//
// Copyright 2019 Analog Devices Inc.
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "adau7118.h"
#define ADAU7118_DEC_RATIO_MASK GENMASK(1, 0)
#define ADAU7118_DEC_RATIO(x) FIELD_PREP(ADAU7118_DEC_RATIO_MASK, x)
#define ADAU7118_CLK_MAP_MASK GENMASK(7, 4)
#define ADAU7118_SLOT_WIDTH_MASK GENMASK(5, 4)
#define ADAU7118_SLOT_WIDTH(x) FIELD_PREP(ADAU7118_SLOT_WIDTH_MASK, x)
#define ADAU7118_TRISTATE_MASK BIT(6)
#define ADAU7118_TRISTATE(x) FIELD_PREP(ADAU7118_TRISTATE_MASK, x)
#define ADAU7118_DATA_FMT_MASK GENMASK(3, 1)
#define ADAU7118_DATA_FMT(x) FIELD_PREP(ADAU7118_DATA_FMT_MASK, x)
#define ADAU7118_SAI_MODE_MASK BIT(0)
#define ADAU7118_SAI_MODE(x) FIELD_PREP(ADAU7118_SAI_MODE_MASK, x)
#define ADAU7118_LRCLK_BCLK_POL_MASK GENMASK(1, 0)
#define ADAU7118_LRCLK_BCLK_POL(x) \
FIELD_PREP(ADAU7118_LRCLK_BCLK_POL_MASK, x)
#define ADAU7118_SPT_SLOT_MASK GENMASK(7, 4)
#define ADAU7118_SPT_SLOT(x) FIELD_PREP(ADAU7118_SPT_SLOT_MASK, x)
#define ADAU7118_FULL_SOFT_R_MASK BIT(1)
#define ADAU7118_FULL_SOFT_R(x) FIELD_PREP(ADAU7118_FULL_SOFT_R_MASK, x)
struct adau7118_data {
struct regmap *map;
struct device *dev;
struct regulator *iovdd;
struct regulator *dvdd;
u32 slot_width;
u32 slots;
bool hw_mode;
bool right_j;
};
/* Input Enable */
static const struct snd_kcontrol_new adau7118_dapm_pdm_control[4] = {
SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 0, 1, 0),
SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 1, 1, 0),
SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 2, 1, 0),
SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 3, 1, 0),
};
static const struct snd_soc_dapm_widget adau7118_widgets_sw[] = {
/* Input Enable Switches */
SND_SOC_DAPM_SWITCH("PDM0", SND_SOC_NOPM, 0, 0,
&adau7118_dapm_pdm_control[0]),
SND_SOC_DAPM_SWITCH("PDM1", SND_SOC_NOPM, 0, 0,
&adau7118_dapm_pdm_control[1]),
SND_SOC_DAPM_SWITCH("PDM2", SND_SOC_NOPM, 0, 0,
&adau7118_dapm_pdm_control[2]),
SND_SOC_DAPM_SWITCH("PDM3", SND_SOC_NOPM, 0, 0,
&adau7118_dapm_pdm_control[3]),
/* PDM Clocks */
SND_SOC_DAPM_SUPPLY("PDM_CLK0", ADAU7118_REG_ENABLES, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PDM_CLK1", ADAU7118_REG_ENABLES, 5, 0, NULL, 0),
/* Output channels */
SND_SOC_DAPM_AIF_OUT("AIF1TX1", "Capture", 0, ADAU7118_REG_SPT_CX(0),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", "Capture", 0, ADAU7118_REG_SPT_CX(1),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", "Capture", 0, ADAU7118_REG_SPT_CX(2),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", "Capture", 0, ADAU7118_REG_SPT_CX(3),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", "Capture", 0, ADAU7118_REG_SPT_CX(4),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", "Capture", 0, ADAU7118_REG_SPT_CX(5),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", "Capture", 0, ADAU7118_REG_SPT_CX(6),
0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", "Capture", 0, ADAU7118_REG_SPT_CX(7),
0, 0),
};
static const struct snd_soc_dapm_route adau7118_routes_sw[] = {
{ "PDM0", "Capture Switch", "PDM_DAT0" },
{ "PDM1", "Capture Switch", "PDM_DAT1" },
{ "PDM2", "Capture Switch", "PDM_DAT2" },
{ "PDM3", "Capture Switch", "PDM_DAT3" },
{ "AIF1TX1", NULL, "PDM0" },
{ "AIF1TX2", NULL, "PDM0" },
{ "AIF1TX3", NULL, "PDM1" },
{ "AIF1TX4", NULL, "PDM1" },
{ "AIF1TX5", NULL, "PDM2" },
{ "AIF1TX6", NULL, "PDM2" },
{ "AIF1TX7", NULL, "PDM3" },
{ "AIF1TX8", NULL, "PDM3" },
{ "Capture", NULL, "PDM_CLK0" },
{ "Capture", NULL, "PDM_CLK1" },
};
static const struct snd_soc_dapm_widget adau7118_widgets_hw[] = {
SND_SOC_DAPM_AIF_OUT("AIF1TX", "Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route adau7118_routes_hw[] = {
{ "AIF1TX", NULL, "PDM_DAT0" },
{ "AIF1TX", NULL, "PDM_DAT1" },
{ "AIF1TX", NULL, "PDM_DAT2" },
{ "AIF1TX", NULL, "PDM_DAT3" },
};
static const struct snd_soc_dapm_widget adau7118_widgets[] = {
SND_SOC_DAPM_INPUT("PDM_DAT0"),
SND_SOC_DAPM_INPUT("PDM_DAT1"),
SND_SOC_DAPM_INPUT("PDM_DAT2"),
SND_SOC_DAPM_INPUT("PDM_DAT3"),
};
static int adau7118_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
struct adau7118_data *st =
snd_soc_component_get_drvdata(dai->component);
int chan, ret;
dev_dbg(st->dev, "Set channel map, %d", tx_num);
for (chan = 0; chan < tx_num; chan++) {
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CX(chan),
ADAU7118_SPT_SLOT_MASK,
ADAU7118_SPT_SLOT(tx_slot[chan]));
if (ret < 0)
return ret;
}
return 0;
}
static int adau7118_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct adau7118_data *st =
snd_soc_component_get_drvdata(dai->component);
int ret = 0;
u32 regval;
dev_dbg(st->dev, "Set format, fmt:%d\n", fmt);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL1,
ADAU7118_DATA_FMT_MASK,
ADAU7118_DATA_FMT(0));
break;
case SND_SOC_DAIFMT_LEFT_J:
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL1,
ADAU7118_DATA_FMT_MASK,
ADAU7118_DATA_FMT(1));
break;
case SND_SOC_DAIFMT_RIGHT_J:
st->right_j = true;
break;
default:
dev_err(st->dev, "Invalid format %d",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
if (ret < 0)
return ret;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
regval = ADAU7118_LRCLK_BCLK_POL(0);
break;
case SND_SOC_DAIFMT_NB_IF:
regval = ADAU7118_LRCLK_BCLK_POL(2);
break;
case SND_SOC_DAIFMT_IB_NF:
regval = ADAU7118_LRCLK_BCLK_POL(1);
break;
case SND_SOC_DAIFMT_IB_IF:
regval = ADAU7118_LRCLK_BCLK_POL(3);
break;
default:
dev_err(st->dev, "Invalid Inv mask %d",
fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL2,
ADAU7118_LRCLK_BCLK_POL_MASK,
regval);
if (ret < 0)
return ret;
return 0;
}
static int adau7118_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct adau7118_data *st =
snd_soc_component_get_drvdata(dai->component);
int ret;
dev_dbg(st->dev, "Set tristate, %d\n", tristate);
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL1,
ADAU7118_TRISTATE_MASK,
ADAU7118_TRISTATE(tristate));
if (ret < 0)
return ret;
return 0;
}
static int adau7118_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots,
int slot_width)
{
struct adau7118_data *st =
snd_soc_component_get_drvdata(dai->component);
int ret = 0;
u32 regval;
dev_dbg(st->dev, "Set tdm, slots:%d width:%d\n", slots, slot_width);
switch (slot_width) {
case 32:
regval = ADAU7118_SLOT_WIDTH(0);
break;
case 24:
regval = ADAU7118_SLOT_WIDTH(2);
break;
case 16:
regval = ADAU7118_SLOT_WIDTH(1);
break;
default:
dev_err(st->dev, "Invalid slot width:%d\n", slot_width);
return -EINVAL;
}
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL1,
ADAU7118_SLOT_WIDTH_MASK, regval);
if (ret < 0)
return ret;
st->slot_width = slot_width;
st->slots = slots;
return 0;
}
static int adau7118_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct adau7118_data *st =
snd_soc_component_get_drvdata(dai->component);
u32 data_width = params_width(params), slots_width;
int ret;
u32 regval;
if (!st->slots) {
/* set stereo mode */
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL1,
ADAU7118_SAI_MODE_MASK,
ADAU7118_SAI_MODE(0));
if (ret < 0)
return ret;
slots_width = 32;
} else {
slots_width = st->slot_width;
}
if (data_width > slots_width) {
dev_err(st->dev, "Invalid data_width:%d, slots_width:%d",
data_width, slots_width);
return -EINVAL;
}
if (st->right_j) {
switch (slots_width - data_width) {
case 8:
/* delay bclck by 8 */
regval = ADAU7118_DATA_FMT(2);
break;
case 12:
/* delay bclck by 12 */
regval = ADAU7118_DATA_FMT(3);
break;
case 16:
/* delay bclck by 16 */
regval = ADAU7118_DATA_FMT(4);
break;
default:
dev_err(st->dev,
"Cannot set right_j setting, slot_w:%d, data_w:%d\n",
slots_width, data_width);
return -EINVAL;
}
ret = snd_soc_component_update_bits(dai->component,
ADAU7118_REG_SPT_CTRL1,
ADAU7118_DATA_FMT_MASK,
regval);
if (ret < 0)
return ret;
}
return 0;
}
static int adau7118_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct adau7118_data *st = snd_soc_component_get_drvdata(component);
int ret = 0;
dev_dbg(st->dev, "Set bias level %d\n", level);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) ==
SND_SOC_BIAS_OFF) {
/* power on */
ret = regulator_enable(st->iovdd);
if (ret)
return ret;
/* there's no timing constraints before enabling dvdd */
ret = regulator_enable(st->dvdd);
if (ret) {
regulator_disable(st->iovdd);
return ret;
}
if (st->hw_mode)
return 0;
regcache_cache_only(st->map, false);
/* sync cache */
ret = snd_soc_component_cache_sync(component);
}
break;
case SND_SOC_BIAS_OFF:
/* power off */
ret = regulator_disable(st->dvdd);
if (ret)
return ret;
ret = regulator_disable(st->iovdd);
if (ret)
return ret;
if (st->hw_mode)
return 0;
/* cache only */
regcache_mark_dirty(st->map);
regcache_cache_only(st->map, true);
break;
}
return ret;
}
static int adau7118_component_probe(struct snd_soc_component *component)
{
struct adau7118_data *st = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
int ret = 0;
if (st->hw_mode) {
ret = snd_soc_dapm_new_controls(dapm, adau7118_widgets_hw,
ARRAY_SIZE(adau7118_widgets_hw));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, adau7118_routes_hw,
ARRAY_SIZE(adau7118_routes_hw));
} else {
snd_soc_component_init_regmap(component, st->map);
ret = snd_soc_dapm_new_controls(dapm, adau7118_widgets_sw,
ARRAY_SIZE(adau7118_widgets_sw));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, adau7118_routes_sw,
ARRAY_SIZE(adau7118_routes_sw));
}
return ret;
}
static const struct snd_soc_dai_ops adau7118_ops = {
.hw_params = adau7118_hw_params,
.set_channel_map = adau7118_set_channel_map,
.set_fmt = adau7118_set_fmt,
.set_tdm_slot = adau7118_set_tdm_slot,
.set_tristate = adau7118_set_tristate,
};
static struct snd_soc_dai_driver adau7118_dai = {
.name = "adau7118-hifi-capture",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S24_3LE,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 4000,
.rate_max = 192000,
.sig_bits = 24,
},
};
static const struct snd_soc_component_driver adau7118_component_driver = {
.probe = adau7118_component_probe,
.set_bias_level = adau7118_set_bias_level,
.dapm_widgets = adau7118_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau7118_widgets),
.use_pmdown_time = 1,
.endianness = 1,
};
static int adau7118_regulator_setup(struct adau7118_data *st)
{
st->iovdd = devm_regulator_get(st->dev, "iovdd");
if (IS_ERR(st->iovdd)) {
dev_err(st->dev, "Could not get iovdd: %ld\n",
PTR_ERR(st->iovdd));
return PTR_ERR(st->iovdd);
}
st->dvdd = devm_regulator_get(st->dev, "dvdd");
if (IS_ERR(st->dvdd)) {
dev_err(st->dev, "Could not get dvdd: %ld\n",
PTR_ERR(st->dvdd));
return PTR_ERR(st->dvdd);
}
/* just assume the device is in reset */
if (!st->hw_mode) {
regcache_mark_dirty(st->map);
regcache_cache_only(st->map, true);
}
return 0;
}
static int adau7118_parset_dt(const struct adau7118_data *st)
{
int ret;
u32 dec_ratio = 0;
/* 4 inputs */
u32 clk_map[4], regval;
if (st->hw_mode)
return 0;
ret = device_property_read_u32(st->dev, "adi,decimation-ratio",
&dec_ratio);
if (!ret) {
switch (dec_ratio) {
case 64:
regval = ADAU7118_DEC_RATIO(0);
break;
case 32:
regval = ADAU7118_DEC_RATIO(1);
break;
case 16:
regval = ADAU7118_DEC_RATIO(2);
break;
default:
dev_err(st->dev, "Invalid dec ratio: %u", dec_ratio);
return -EINVAL;
}
ret = regmap_update_bits(st->map,
ADAU7118_REG_DEC_RATIO_CLK_MAP,
ADAU7118_DEC_RATIO_MASK, regval);
if (ret)
return ret;
}
ret = device_property_read_u32_array(st->dev, "adi,pdm-clk-map",
clk_map, ARRAY_SIZE(clk_map));
if (!ret) {
int pdm;
u32 _clk_map = 0;
for (pdm = 0; pdm < ARRAY_SIZE(clk_map); pdm++)
_clk_map |= (clk_map[pdm] << (pdm + 4));
ret = regmap_update_bits(st->map,
ADAU7118_REG_DEC_RATIO_CLK_MAP,
ADAU7118_CLK_MAP_MASK, _clk_map);
if (ret)
return ret;
}
return 0;
}
int adau7118_probe(struct device *dev, struct regmap *map, bool hw_mode)
{
struct adau7118_data *st;
int ret;
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
if (!st)
return -ENOMEM;
st->dev = dev;
st->hw_mode = hw_mode;
dev_set_drvdata(dev, st);
if (!hw_mode) {
st->map = map;
adau7118_dai.ops = &adau7118_ops;
/*
* Perform a full soft reset. This will set all register's
* with their reset values.
*/
ret = regmap_update_bits(map, ADAU7118_REG_RESET,
ADAU7118_FULL_SOFT_R_MASK,
ADAU7118_FULL_SOFT_R(1));
if (ret)
return ret;
}
ret = adau7118_parset_dt(st);
if (ret)
return ret;
ret = adau7118_regulator_setup(st);
if (ret)
return ret;
return devm_snd_soc_register_component(dev,
&adau7118_component_driver,
&adau7118_dai, 1);
}
EXPORT_SYMBOL_GPL(adau7118_probe);
MODULE_AUTHOR("Nuno Sa <[email protected]>");
MODULE_DESCRIPTION("ADAU7118 8 channel PDM-to-I2S/TDM Converter driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau7118.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// CS35L56 ALSA SoC audio driver SoundWire binding
//
// Copyright (C) 2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/swab.h>
#include <linux/types.h>
#include <linux/workqueue.h>
#include "cs35l56.h"
/* Register addresses are offset when sent over SoundWire */
#define CS35L56_SDW_ADDR_OFFSET 0x8000
static int cs35l56_sdw_read_one(struct sdw_slave *peripheral, unsigned int reg, void *buf)
{
int ret;
ret = sdw_nread_no_pm(peripheral, reg, 4, (u8 *)buf);
if (ret != 0) {
dev_err(&peripheral->dev, "Read failed @%#x:%d\n", reg, ret);
return ret;
}
swab32s((u32 *)buf);
return 0;
}
static int cs35l56_sdw_read(void *context, const void *reg_buf,
const size_t reg_size, void *val_buf,
size_t val_size)
{
struct sdw_slave *peripheral = context;
u8 *buf8 = val_buf;
unsigned int reg, bytes;
int ret;
reg = le32_to_cpu(*(const __le32 *)reg_buf);
reg += CS35L56_SDW_ADDR_OFFSET;
if (val_size == 4)
return cs35l56_sdw_read_one(peripheral, reg, val_buf);
while (val_size) {
bytes = SDW_REG_NO_PAGE - (reg & SDW_REGADDR); /* to end of page */
if (bytes > val_size)
bytes = val_size;
ret = sdw_nread_no_pm(peripheral, reg, bytes, buf8);
if (ret != 0) {
dev_err(&peripheral->dev, "Read failed @%#x..%#x:%d\n",
reg, reg + bytes - 1, ret);
return ret;
}
swab32_array((u32 *)buf8, bytes / 4);
val_size -= bytes;
reg += bytes;
buf8 += bytes;
}
return 0;
}
static inline void cs35l56_swab_copy(void *dest, const void *src, size_t nbytes)
{
u32 *dest32 = dest;
const u32 *src32 = src;
for (; nbytes > 0; nbytes -= 4)
*dest32++ = swab32(*src32++);
}
static int cs35l56_sdw_write_one(struct sdw_slave *peripheral, unsigned int reg, const void *buf)
{
u32 val_le = swab32(*(u32 *)buf);
int ret;
ret = sdw_nwrite_no_pm(peripheral, reg, 4, (u8 *)&val_le);
if (ret != 0) {
dev_err(&peripheral->dev, "Write failed @%#x:%d\n", reg, ret);
return ret;
}
return 0;
}
static int cs35l56_sdw_gather_write(void *context,
const void *reg_buf, size_t reg_size,
const void *val_buf, size_t val_size)
{
struct sdw_slave *peripheral = context;
const u8 *src_be = val_buf;
u32 val_le_buf[64]; /* Define u32 so it is 32-bit aligned */
unsigned int reg, bytes;
int ret;
reg = le32_to_cpu(*(const __le32 *)reg_buf);
reg += CS35L56_SDW_ADDR_OFFSET;
if (val_size == 4)
return cs35l56_sdw_write_one(peripheral, reg, src_be);
while (val_size) {
bytes = SDW_REG_NO_PAGE - (reg & SDW_REGADDR); /* to end of page */
if (bytes > val_size)
bytes = val_size;
if (bytes > sizeof(val_le_buf))
bytes = sizeof(val_le_buf);
cs35l56_swab_copy(val_le_buf, src_be, bytes);
ret = sdw_nwrite_no_pm(peripheral, reg, bytes, (u8 *)val_le_buf);
if (ret != 0) {
dev_err(&peripheral->dev, "Write failed @%#x..%#x:%d\n",
reg, reg + bytes - 1, ret);
return ret;
}
val_size -= bytes;
reg += bytes;
src_be += bytes;
}
return 0;
}
static int cs35l56_sdw_write(void *context, const void *val_buf, size_t val_size)
{
const u8 *src_buf = val_buf;
/* First word of val_buf contains the destination address */
return cs35l56_sdw_gather_write(context, &src_buf[0], 4, &src_buf[4], val_size - 4);
}
/*
* Registers are big-endian on I2C and SPI but little-endian on SoundWire.
* Exported firmware controls are big-endian on I2C/SPI but little-endian on
* SoundWire. Firmware files are always big-endian and are opaque blobs.
* Present a big-endian regmap and hide the endianness swap, so that the ALSA
* byte controls always have the same byte order, and firmware file blobs
* can be written verbatim.
*/
static const struct regmap_bus cs35l56_regmap_bus_sdw = {
.read = cs35l56_sdw_read,
.write = cs35l56_sdw_write,
.gather_write = cs35l56_sdw_gather_write,
.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
.val_format_endian_default = REGMAP_ENDIAN_BIG,
};
static void cs35l56_sdw_init(struct sdw_slave *peripheral)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
int ret;
pm_runtime_get_noresume(cs35l56->base.dev);
regcache_cache_only(cs35l56->base.regmap, false);
ret = cs35l56_init(cs35l56);
if (ret < 0) {
regcache_cache_only(cs35l56->base.regmap, true);
goto out;
}
/*
* cs35l56_init can return with !init_done if it triggered
* a soft reset.
*/
if (cs35l56->base.init_done) {
/* Enable SoundWire interrupts */
sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_MASK_1,
CS35L56_SDW_INT_MASK_CODEC_IRQ);
}
out:
pm_runtime_mark_last_busy(cs35l56->base.dev);
pm_runtime_put_autosuspend(cs35l56->base.dev);
}
static int cs35l56_sdw_interrupt(struct sdw_slave *peripheral,
struct sdw_slave_intr_status *status)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
/* SoundWire core holds our pm_runtime when calling this function. */
dev_dbg(cs35l56->base.dev, "int control_port=%#x\n", status->control_port);
if ((status->control_port & SDW_SCP_INT1_IMPL_DEF) == 0)
return 0;
/*
* Prevent bus manager suspending and possibly issuing a
* bus-reset before the queued work has run.
*/
pm_runtime_get_noresume(cs35l56->base.dev);
/*
* Mask and clear until it has been handled. The read of GEN_INT_STAT_1
* is required as per the SoundWire spec for interrupt status bits
* to clear. GEN_INT_MASK_1 masks the _inputs_ to GEN_INT_STAT1.
* None of the interrupts are time-critical so use the
* power-efficient queue.
*/
sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
sdw_read_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1);
sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
queue_work(system_power_efficient_wq, &cs35l56->sdw_irq_work);
return 0;
}
static void cs35l56_sdw_irq_work(struct work_struct *work)
{
struct cs35l56_private *cs35l56 = container_of(work,
struct cs35l56_private,
sdw_irq_work);
cs35l56_irq(-1, &cs35l56->base);
/* unmask interrupts */
if (!cs35l56->sdw_irq_no_unmask)
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1,
CS35L56_SDW_INT_MASK_CODEC_IRQ);
pm_runtime_put_autosuspend(cs35l56->base.dev);
}
static int cs35l56_sdw_read_prop(struct sdw_slave *peripheral)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
struct sdw_slave_prop *prop = &peripheral->prop;
struct sdw_dpn_prop *ports;
ports = devm_kcalloc(cs35l56->base.dev, 2, sizeof(*ports), GFP_KERNEL);
if (!ports)
return -ENOMEM;
prop->source_ports = BIT(CS35L56_SDW1_CAPTURE_PORT);
prop->sink_ports = BIT(CS35L56_SDW1_PLAYBACK_PORT);
prop->paging_support = true;
prop->clk_stop_mode1 = false;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY | SDW_SCP_INT1_IMPL_DEF;
/* DP1 - playback */
ports[0].num = CS35L56_SDW1_PLAYBACK_PORT;
ports[0].type = SDW_DPN_FULL;
ports[0].ch_prep_timeout = 10;
prop->sink_dpn_prop = &ports[0];
/* DP3 - capture */
ports[1].num = CS35L56_SDW1_CAPTURE_PORT;
ports[1].type = SDW_DPN_FULL;
ports[1].ch_prep_timeout = 10;
prop->src_dpn_prop = &ports[1];
return 0;
}
static int cs35l56_sdw_update_status(struct sdw_slave *peripheral,
enum sdw_slave_status status)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
switch (status) {
case SDW_SLAVE_ATTACHED:
dev_dbg(cs35l56->base.dev, "%s: ATTACHED\n", __func__);
if (cs35l56->sdw_attached)
break;
if (!cs35l56->base.init_done || cs35l56->soft_resetting)
cs35l56_sdw_init(peripheral);
cs35l56->sdw_attached = true;
break;
case SDW_SLAVE_UNATTACHED:
dev_dbg(cs35l56->base.dev, "%s: UNATTACHED\n", __func__);
cs35l56->sdw_attached = false;
break;
default:
break;
}
return 0;
}
static int cs35l56_a1_kick_divider(struct cs35l56_private *cs35l56,
struct sdw_slave *peripheral)
{
unsigned int curr_scale_reg, next_scale_reg;
int curr_scale, next_scale, ret;
if (!cs35l56->base.init_done)
return 0;
if (peripheral->bus->params.curr_bank) {
curr_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B1;
next_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B0;
} else {
curr_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B0;
next_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B1;
}
/*
* Current clock scale value must be different to new value.
* Modify current to guarantee this. If next still has the dummy
* value we wrote when it was current, the core code has not set
* a new scale so restore its original good value
*/
curr_scale = sdw_read_no_pm(peripheral, curr_scale_reg);
if (curr_scale < 0) {
dev_err(cs35l56->base.dev, "Failed to read current clock scale: %d\n", curr_scale);
return curr_scale;
}
next_scale = sdw_read_no_pm(peripheral, next_scale_reg);
if (next_scale < 0) {
dev_err(cs35l56->base.dev, "Failed to read next clock scale: %d\n", next_scale);
return next_scale;
}
if (next_scale == CS35L56_SDW_INVALID_BUS_SCALE) {
next_scale = cs35l56->old_sdw_clock_scale;
ret = sdw_write_no_pm(peripheral, next_scale_reg, next_scale);
if (ret < 0) {
dev_err(cs35l56->base.dev, "Failed to modify current clock scale: %d\n",
ret);
return ret;
}
}
cs35l56->old_sdw_clock_scale = curr_scale;
ret = sdw_write_no_pm(peripheral, curr_scale_reg, CS35L56_SDW_INVALID_BUS_SCALE);
if (ret < 0) {
dev_err(cs35l56->base.dev, "Failed to modify current clock scale: %d\n", ret);
return ret;
}
dev_dbg(cs35l56->base.dev, "Next bus scale: %#x\n", next_scale);
return 0;
}
static int cs35l56_sdw_bus_config(struct sdw_slave *peripheral,
struct sdw_bus_params *params)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
int sclk;
sclk = params->curr_dr_freq / 2;
dev_dbg(cs35l56->base.dev, "%s: sclk=%u c=%u r=%u\n",
__func__, sclk, params->col, params->row);
if (cs35l56->base.rev < 0xb0)
return cs35l56_a1_kick_divider(cs35l56, peripheral);
return 0;
}
static int __maybe_unused cs35l56_sdw_clk_stop(struct sdw_slave *peripheral,
enum sdw_clk_stop_mode mode,
enum sdw_clk_stop_type type)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
dev_dbg(cs35l56->base.dev, "%s: mode:%d type:%d\n", __func__, mode, type);
return 0;
}
static const struct sdw_slave_ops cs35l56_sdw_ops = {
.read_prop = cs35l56_sdw_read_prop,
.interrupt_callback = cs35l56_sdw_interrupt,
.update_status = cs35l56_sdw_update_status,
.bus_config = cs35l56_sdw_bus_config,
#ifdef DEBUG
.clk_stop = cs35l56_sdw_clk_stop,
#endif
};
static int __maybe_unused cs35l56_sdw_handle_unattach(struct cs35l56_private *cs35l56)
{
struct sdw_slave *peripheral = cs35l56->sdw_peripheral;
if (peripheral->unattach_request) {
/* Cannot access registers until bus is re-initialized. */
dev_dbg(cs35l56->base.dev, "Wait for initialization_complete\n");
if (!wait_for_completion_timeout(&peripheral->initialization_complete,
msecs_to_jiffies(5000))) {
dev_err(cs35l56->base.dev, "initialization_complete timed out\n");
return -ETIMEDOUT;
}
peripheral->unattach_request = 0;
/*
* Don't call regcache_mark_dirty(), we can't be sure that the
* Manager really did issue a Bus Reset.
*/
}
return 0;
}
static int __maybe_unused cs35l56_sdw_runtime_suspend(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
if (!cs35l56->base.init_done)
return 0;
return cs35l56_runtime_suspend_common(&cs35l56->base);
}
static int __maybe_unused cs35l56_sdw_runtime_resume(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "Runtime resume\n");
if (!cs35l56->base.init_done)
return 0;
ret = cs35l56_sdw_handle_unattach(cs35l56);
if (ret < 0)
return ret;
ret = cs35l56_runtime_resume_common(&cs35l56->base, true);
if (ret)
return ret;
/* Re-enable SoundWire interrupts */
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1,
CS35L56_SDW_INT_MASK_CODEC_IRQ);
return 0;
}
static int __maybe_unused cs35l56_sdw_system_suspend(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
if (!cs35l56->base.init_done)
return 0;
/*
* Disable SoundWire interrupts.
* Flush - don't cancel because that could leave an unbalanced pm_runtime_get.
*/
cs35l56->sdw_irq_no_unmask = true;
flush_work(&cs35l56->sdw_irq_work);
/* Mask interrupts and flush in case sdw_irq_work was queued again */
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1);
sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
flush_work(&cs35l56->sdw_irq_work);
return cs35l56_system_suspend(dev);
}
static int __maybe_unused cs35l56_sdw_system_resume(struct device *dev)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(dev);
cs35l56->sdw_irq_no_unmask = false;
/* runtime_resume re-enables the interrupt */
return cs35l56_system_resume(dev);
}
static int cs35l56_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id)
{
struct device *dev = &peripheral->dev;
struct cs35l56_private *cs35l56;
int ret;
cs35l56 = devm_kzalloc(dev, sizeof(*cs35l56), GFP_KERNEL);
if (!cs35l56)
return -ENOMEM;
cs35l56->base.dev = dev;
cs35l56->sdw_peripheral = peripheral;
INIT_WORK(&cs35l56->sdw_irq_work, cs35l56_sdw_irq_work);
dev_set_drvdata(dev, cs35l56);
cs35l56->base.regmap = devm_regmap_init(dev, &cs35l56_regmap_bus_sdw,
peripheral, &cs35l56_regmap_sdw);
if (IS_ERR(cs35l56->base.regmap)) {
ret = PTR_ERR(cs35l56->base.regmap);
return dev_err_probe(dev, ret, "Failed to allocate register map\n");
}
/* Start in cache-only until device is enumerated */
regcache_cache_only(cs35l56->base.regmap, true);
ret = cs35l56_common_probe(cs35l56);
if (ret != 0)
return ret;
return 0;
}
static int cs35l56_sdw_remove(struct sdw_slave *peripheral)
{
struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);
/* Disable SoundWire interrupts */
cs35l56->sdw_irq_no_unmask = true;
cancel_work_sync(&cs35l56->sdw_irq_work);
sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0);
sdw_read_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1);
sdw_write_no_pm(peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF);
cs35l56_remove(cs35l56);
return 0;
}
static const struct dev_pm_ops cs35l56_sdw_pm = {
SET_RUNTIME_PM_OPS(cs35l56_sdw_runtime_suspend, cs35l56_sdw_runtime_resume, NULL)
SYSTEM_SLEEP_PM_OPS(cs35l56_sdw_system_suspend, cs35l56_sdw_system_resume)
LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early)
/* NOIRQ stage not needed, SoundWire doesn't use a hard IRQ */
};
static const struct sdw_device_id cs35l56_sdw_id[] = {
SDW_SLAVE_ENTRY(0x01FA, 0x3556, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, cs35l56_sdw_id);
static struct sdw_driver cs35l56_sdw_driver = {
.driver = {
.name = "cs35l56",
.pm = &cs35l56_sdw_pm,
},
.probe = cs35l56_sdw_probe,
.remove = cs35l56_sdw_remove,
.ops = &cs35l56_sdw_ops,
.id_table = cs35l56_sdw_id,
};
module_sdw_driver(cs35l56_sdw_driver);
MODULE_DESCRIPTION("ASoC CS35L56 SoundWire driver");
MODULE_IMPORT_NS(SND_SOC_CS35L56_CORE);
MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Simon Trimmer <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l56-sdw.c |
// SPDX-License-Identifier: GPL-2.0
//
// MAX9867 ALSA SoC codec driver
//
// Copyright 2013-2015 Maxim Integrated Products
// Copyright 2018 Ladislav Michl <[email protected]>
//
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max9867.h"
struct max9867_priv {
struct clk *mclk;
struct regmap *regmap;
const struct snd_pcm_hw_constraint_list *constraints;
unsigned int sysclk, pclk;
bool provider, dsp_a;
unsigned int adc_dac_active;
};
static const char *const max9867_spmode[] = {
"Stereo Diff", "Mono Diff",
"Stereo Cap", "Mono Cap",
"Stereo Single", "Mono Single",
"Stereo Single Fast", "Mono Single Fast"
};
static const char *const max9867_filter_text[] = {"IIR", "FIR"};
static const char *const max9867_adc_dac_filter_text[] = {
"Disabled",
"Elliptical/16/256",
"Butterworth/16/500",
"Elliptical/8/256",
"Butterworth/8/500",
"Butterworth/8-24"
};
enum max9867_adc_dac {
MAX9867_ADC_LEFT,
MAX9867_ADC_RIGHT,
MAX9867_DAC_LEFT,
MAX9867_DAC_RIGHT,
};
static int max9867_adc_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
enum max9867_adc_dac adc_dac;
if (!strcmp(w->name, "ADCL"))
adc_dac = MAX9867_ADC_LEFT;
else if (!strcmp(w->name, "ADCR"))
adc_dac = MAX9867_ADC_RIGHT;
else if (!strcmp(w->name, "DACL"))
adc_dac = MAX9867_DAC_LEFT;
else if (!strcmp(w->name, "DACR"))
adc_dac = MAX9867_DAC_RIGHT;
else
return 0;
if (SND_SOC_DAPM_EVENT_ON(event))
max9867->adc_dac_active |= BIT(adc_dac);
else if (SND_SOC_DAPM_EVENT_OFF(event))
max9867->adc_dac_active &= ~BIT(adc_dac);
return 0;
}
static int max9867_filter_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
unsigned int reg;
int ret;
ret = regmap_read(max9867->regmap, MAX9867_CODECFLTR, ®);
if (ret)
return -EINVAL;
if (reg & MAX9867_CODECFLTR_MODE)
ucontrol->value.enumerated.item[0] = 1;
else
ucontrol->value.enumerated.item[0] = 0;
return 0;
}
static int max9867_filter_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
unsigned int reg, mode = ucontrol->value.enumerated.item[0];
int ret;
if (mode > 1)
return -EINVAL;
/* don't allow change if ADC/DAC active */
if (max9867->adc_dac_active)
return -EBUSY;
/* read current filter mode */
ret = regmap_read(max9867->regmap, MAX9867_CODECFLTR, ®);
if (ret)
return -EINVAL;
if (mode)
mode = MAX9867_CODECFLTR_MODE;
/* check if change is needed */
if ((reg & MAX9867_CODECFLTR_MODE) == mode)
return 0;
/* shutdown codec before switching filter mode */
regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
MAX9867_PWRMAN_SHDN, 0);
/* switch filter mode */
regmap_update_bits(max9867->regmap, MAX9867_CODECFLTR,
MAX9867_CODECFLTR_MODE, mode);
/* out of shutdown now */
regmap_update_bits(max9867->regmap, MAX9867_PWRMAN,
MAX9867_PWRMAN_SHDN, MAX9867_PWRMAN_SHDN);
return 0;
}
static SOC_ENUM_SINGLE_EXT_DECL(max9867_filter, max9867_filter_text);
static SOC_ENUM_SINGLE_DECL(max9867_dac_filter, MAX9867_CODECFLTR, 0,
max9867_adc_dac_filter_text);
static SOC_ENUM_SINGLE_DECL(max9867_adc_filter, MAX9867_CODECFLTR, 4,
max9867_adc_dac_filter_text);
static SOC_ENUM_SINGLE_DECL(max9867_spkmode, MAX9867_MODECONFIG, 0,
max9867_spmode);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(max9867_master_tlv,
0, 2, TLV_DB_SCALE_ITEM(-8600, 200, 1),
3, 17, TLV_DB_SCALE_ITEM(-7800, 400, 0),
18, 25, TLV_DB_SCALE_ITEM(-2000, 200, 0),
26, 34, TLV_DB_SCALE_ITEM( -500, 100, 0),
35, 40, TLV_DB_SCALE_ITEM( 350, 50, 0),
);
static DECLARE_TLV_DB_SCALE(max9867_mic_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(max9867_line_tlv, -600, 200, 0);
static DECLARE_TLV_DB_SCALE(max9867_adc_tlv, -1200, 100, 0);
static DECLARE_TLV_DB_SCALE(max9867_dac_tlv, -1500, 100, 0);
static DECLARE_TLV_DB_SCALE(max9867_dacboost_tlv, 0, 600, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(max9867_micboost_tlv,
0, 2, TLV_DB_SCALE_ITEM(-2000, 2000, 1),
3, 3, TLV_DB_SCALE_ITEM(3000, 0, 0),
);
static const struct snd_kcontrol_new max9867_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", MAX9867_LEFTVOL,
MAX9867_RIGHTVOL, 0, 40, 1, max9867_master_tlv),
SOC_DOUBLE_R_TLV("Line Capture Volume", MAX9867_LEFTLINELVL,
MAX9867_RIGHTLINELVL, 0, 15, 1, max9867_line_tlv),
SOC_DOUBLE_R_TLV("Mic Capture Volume", MAX9867_LEFTMICGAIN,
MAX9867_RIGHTMICGAIN, 0, 20, 1, max9867_mic_tlv),
SOC_DOUBLE_R_TLV("Mic Boost Capture Volume", MAX9867_LEFTMICGAIN,
MAX9867_RIGHTMICGAIN, 5, 3, 0, max9867_micboost_tlv),
SOC_SINGLE("Digital Sidetone Volume", MAX9867_SIDETONE, 0, 31, 1),
SOC_SINGLE_TLV("Digital Playback Volume", MAX9867_DACLEVEL, 0, 15, 1,
max9867_dac_tlv),
SOC_SINGLE_TLV("Digital Boost Playback Volume", MAX9867_DACLEVEL, 4, 3, 0,
max9867_dacboost_tlv),
SOC_DOUBLE_TLV("Digital Capture Volume", MAX9867_ADCLEVEL, 4, 0, 15, 1,
max9867_adc_tlv),
SOC_ENUM("Speaker Mode", max9867_spkmode),
SOC_SINGLE("Volume Smoothing Switch", MAX9867_MODECONFIG, 6, 1, 0),
SOC_SINGLE("Line ZC Switch", MAX9867_MODECONFIG, 5, 1, 0),
SOC_ENUM_EXT("DSP Filter", max9867_filter, max9867_filter_get, max9867_filter_set),
SOC_ENUM("ADC Filter", max9867_adc_filter),
SOC_ENUM("DAC Filter", max9867_dac_filter),
SOC_SINGLE("Mono Playback Switch", MAX9867_IFC1B, 3, 1, 0),
};
/* Input mixer */
static const struct snd_kcontrol_new max9867_input_mixer_controls[] = {
SOC_DAPM_DOUBLE("Line Capture Switch", MAX9867_INPUTCONFIG, 7, 5, 1, 0),
SOC_DAPM_DOUBLE("Mic Capture Switch", MAX9867_INPUTCONFIG, 6, 4, 1, 0),
};
/* Output mixer */
static const struct snd_kcontrol_new max9867_output_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("Line Bypass Switch",
MAX9867_LEFTLINELVL, MAX9867_RIGHTLINELVL, 6, 1, 1),
};
/* Sidetone mixer */
static const struct snd_kcontrol_new max9867_sidetone_mixer_controls[] = {
SOC_DAPM_DOUBLE("Sidetone Switch", MAX9867_SIDETONE, 6, 7, 1, 0),
};
/* Line out switch */
static const struct snd_kcontrol_new max9867_line_out_control =
SOC_DAPM_DOUBLE_R("Switch",
MAX9867_LEFTVOL, MAX9867_RIGHTVOL, 6, 1, 1);
/* DMIC mux */
static const char *const dmic_mux_text[] = {
"ADC", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(left_dmic_mux_enum,
MAX9867_MICCONFIG, 5, dmic_mux_text);
static SOC_ENUM_SINGLE_DECL(right_dmic_mux_enum,
MAX9867_MICCONFIG, 4, dmic_mux_text);
static const struct snd_kcontrol_new max9867_left_dmic_mux =
SOC_DAPM_ENUM("DMICL Mux", left_dmic_mux_enum);
static const struct snd_kcontrol_new max9867_right_dmic_mux =
SOC_DAPM_ENUM("DMICR Mux", right_dmic_mux_enum);
static const struct snd_soc_dapm_widget max9867_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_INPUT("DMICL"),
SND_SOC_DAPM_INPUT("DMICR"),
SND_SOC_DAPM_INPUT("LINL"),
SND_SOC_DAPM_INPUT("LINR"),
SND_SOC_DAPM_PGA("Left Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
max9867_input_mixer_controls,
ARRAY_SIZE(max9867_input_mixer_controls)),
SND_SOC_DAPM_MUX("DMICL Mux", SND_SOC_NOPM, 0, 0,
&max9867_left_dmic_mux),
SND_SOC_DAPM_MUX("DMICR Mux", SND_SOC_NOPM, 0, 0,
&max9867_right_dmic_mux),
SND_SOC_DAPM_ADC_E("ADCL", "HiFi Capture", SND_SOC_NOPM, 0, 0,
max9867_adc_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADCR", "HiFi Capture", SND_SOC_NOPM, 0, 0,
max9867_adc_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("Digital", SND_SOC_NOPM, 0, 0,
max9867_sidetone_mixer_controls,
ARRAY_SIZE(max9867_sidetone_mixer_controls)),
SND_SOC_DAPM_MIXER_NAMED_CTL("Output Mixer", SND_SOC_NOPM, 0, 0,
max9867_output_mixer_controls,
ARRAY_SIZE(max9867_output_mixer_controls)),
SND_SOC_DAPM_DAC_E("DACL", "HiFi Playback", SND_SOC_NOPM, 0, 0,
max9867_adc_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("DACR", "HiFi Playback", SND_SOC_NOPM, 0, 0,
max9867_adc_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("Master Playback", SND_SOC_NOPM, 0, 0,
&max9867_line_out_control),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
};
static const struct snd_soc_dapm_route max9867_audio_map[] = {
{"Left Line Input", NULL, "LINL"},
{"Right Line Input", NULL, "LINR"},
{"Input Mixer", "Mic Capture Switch", "MICL"},
{"Input Mixer", "Mic Capture Switch", "MICR"},
{"Input Mixer", "Line Capture Switch", "Left Line Input"},
{"Input Mixer", "Line Capture Switch", "Right Line Input"},
{"DMICL Mux", "DMIC", "DMICL"},
{"DMICR Mux", "DMIC", "DMICR"},
{"DMICL Mux", "ADC", "Input Mixer"},
{"DMICR Mux", "ADC", "Input Mixer"},
{"ADCL", NULL, "DMICL Mux"},
{"ADCR", NULL, "DMICR Mux"},
{"Digital", "Sidetone Switch", "ADCL"},
{"Digital", "Sidetone Switch", "ADCR"},
{"DACL", NULL, "Digital"},
{"DACR", NULL, "Digital"},
{"Output Mixer", "Line Bypass Switch", "Left Line Input"},
{"Output Mixer", "Line Bypass Switch", "Right Line Input"},
{"Output Mixer", NULL, "DACL"},
{"Output Mixer", NULL, "DACR"},
{"Master Playback", "Switch", "Output Mixer"},
{"LOUT", NULL, "Master Playback"},
{"ROUT", NULL, "Master Playback"},
};
static const unsigned int max9867_rates_44k1[] = {
11025, 22050, 44100,
};
static const struct snd_pcm_hw_constraint_list max9867_constraints_44k1 = {
.list = max9867_rates_44k1,
.count = ARRAY_SIZE(max9867_rates_44k1),
};
static const unsigned int max9867_rates_48k[] = {
8000, 16000, 32000, 48000,
};
static const struct snd_pcm_hw_constraint_list max9867_constraints_48k = {
.list = max9867_rates_48k,
.count = ARRAY_SIZE(max9867_rates_48k),
};
static int max9867_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct max9867_priv *max9867 =
snd_soc_component_get_drvdata(dai->component);
if (max9867->constraints)
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, max9867->constraints);
return 0;
}
static int max9867_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
int value, freq = 0;
unsigned long int rate, ratio;
struct snd_soc_component *component = dai->component;
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
unsigned int ni = DIV_ROUND_CLOSEST_ULL(96ULL * 0x10000 * params_rate(params),
max9867->pclk);
/* set up the ni value */
regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
MAX9867_NI_HIGH_MASK, (0xFF00 & ni) >> 8);
regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
MAX9867_NI_LOW_MASK, 0x00FF & ni);
if (max9867->provider) {
if (max9867->dsp_a) {
value = MAX9867_IFC1B_48X;
} else {
rate = params_rate(params) * 2 * params_width(params);
ratio = max9867->pclk / rate;
switch (params_width(params)) {
case 8:
case 16:
switch (ratio) {
case 2:
value = MAX9867_IFC1B_PCLK_2;
break;
case 4:
value = MAX9867_IFC1B_PCLK_4;
break;
case 8:
value = MAX9867_IFC1B_PCLK_8;
break;
case 16:
value = MAX9867_IFC1B_PCLK_16;
break;
default:
return -EINVAL;
}
break;
case 24:
value = MAX9867_IFC1B_48X;
break;
case 32:
value = MAX9867_IFC1B_64X;
break;
default:
return -EINVAL;
}
}
regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
MAX9867_IFC1B_BCLK_MASK, value);
/* Exact integer mode available for 8kHz and 16kHz sample rates
* and certain PCLK (prescaled MCLK) values.
*/
if (params_rate(params) == 8000 ||
params_rate(params) == 16000) {
switch (max9867->pclk) {
case 12000000:
freq = 0x08;
break;
case 13000000:
freq = 0x0A;
break;
case 16000000:
freq = 0x0C;
break;
case 19200000:
freq = 0x0E;
break;
}
}
if (freq && params_rate(params) == 16000)
freq++;
/* If exact integer mode not available, the freq value
* remains zero, i.e. normal mode is used.
*/
regmap_update_bits(max9867->regmap, MAX9867_SYSCLK,
MAX9867_FREQ_MASK, freq);
} else {
/*
* digital pll locks on to any externally supplied LRCLK signal
* and also enable rapid lock mode.
*/
regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
MAX9867_RAPID_LOCK, MAX9867_RAPID_LOCK);
regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
MAX9867_PLL, MAX9867_PLL);
}
return 0;
}
static int max9867_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
return regmap_update_bits(max9867->regmap, MAX9867_DACLEVEL,
1 << 6, !!mute << 6);
}
static int max9867_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
int value = 0;
/* Set the prescaler based on the master clock frequency*/
if (freq >= 10000000 && freq <= 20000000) {
value |= MAX9867_PSCLK_10_20;
max9867->pclk = freq;
} else if (freq >= 20000000 && freq <= 40000000) {
value |= MAX9867_PSCLK_20_40;
max9867->pclk = freq / 2;
} else if (freq >= 40000000 && freq <= 60000000) {
value |= MAX9867_PSCLK_40_60;
max9867->pclk = freq / 4;
} else {
dev_err(component->dev,
"Invalid clock frequency %uHz (required 10-60MHz)\n",
freq);
return -EINVAL;
}
if (freq % 48000 == 0)
max9867->constraints = &max9867_constraints_48k;
else if (freq % 44100 == 0)
max9867->constraints = &max9867_constraints_44k1;
else
dev_warn(component->dev,
"Unable to set exact rate with %uHz clock frequency\n",
freq);
max9867->sysclk = freq;
value = value << MAX9867_PSCLK_SHIFT;
regmap_update_bits(max9867->regmap, MAX9867_SYSCLK,
MAX9867_PSCLK_MASK, value);
return 0;
}
static int max9867_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
u8 iface1A, iface1B;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
max9867->provider = true;
iface1A = MAX9867_MASTER;
iface1B = MAX9867_IFC1B_48X;
break;
case SND_SOC_DAIFMT_CBC_CFC:
max9867->provider = false;
iface1A = iface1B = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
max9867->dsp_a = false;
iface1A |= MAX9867_I2S_DLY;
break;
case SND_SOC_DAIFMT_DSP_A:
max9867->dsp_a = true;
iface1A |= MAX9867_TDM_MODE | MAX9867_SDOUT_HIZ;
break;
default:
return -EINVAL;
}
/* Clock inversion bits, BCI and WCI */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface1A |= MAX9867_WCI_MODE | MAX9867_BCI_MODE;
break;
case SND_SOC_DAIFMT_IB_NF:
iface1A |= MAX9867_BCI_MODE;
break;
case SND_SOC_DAIFMT_NB_IF:
iface1A |= MAX9867_WCI_MODE;
break;
default:
return -EINVAL;
}
regmap_write(max9867->regmap, MAX9867_IFC1A, iface1A);
regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
MAX9867_IFC1B_BCLK_MASK, iface1B);
return 0;
}
static const struct snd_soc_dai_ops max9867_dai_ops = {
.set_sysclk = max9867_set_dai_sysclk,
.set_fmt = max9867_dai_set_fmt,
.mute_stream = max9867_mute,
.startup = max9867_startup,
.hw_params = max9867_dai_hw_params,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver max9867_dai[] = {
{
.name = "max9867-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &max9867_dai_ops,
.symmetric_rate = 1,
}
};
#ifdef CONFIG_PM
static int max9867_suspend(struct snd_soc_component *component)
{
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
return 0;
}
static int max9867_resume(struct snd_soc_component *component)
{
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define max9867_suspend NULL
#define max9867_resume NULL
#endif
static int max9867_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int err;
struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
err = clk_prepare_enable(max9867->mclk);
if (err)
return err;
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
err = regcache_sync(max9867->regmap);
if (err)
return err;
err = regmap_write(max9867->regmap,
MAX9867_PWRMAN, 0xff);
if (err)
return err;
}
break;
case SND_SOC_BIAS_OFF:
err = regmap_write(max9867->regmap, MAX9867_PWRMAN, 0);
if (err)
return err;
regcache_mark_dirty(max9867->regmap);
clk_disable_unprepare(max9867->mclk);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_component_driver max9867_component = {
.controls = max9867_snd_controls,
.num_controls = ARRAY_SIZE(max9867_snd_controls),
.dapm_routes = max9867_audio_map,
.num_dapm_routes = ARRAY_SIZE(max9867_audio_map),
.dapm_widgets = max9867_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max9867_dapm_widgets),
.suspend = max9867_suspend,
.resume = max9867_resume,
.set_bias_level = max9867_set_bias_level,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static bool max9867_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX9867_STATUS:
case MAX9867_JACKSTATUS:
case MAX9867_AUXHIGH:
case MAX9867_AUXLOW:
return true;
default:
return false;
}
}
static const struct regmap_config max9867_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX9867_REVISION,
.volatile_reg = max9867_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static int max9867_i2c_probe(struct i2c_client *i2c)
{
struct max9867_priv *max9867;
int ret, reg;
max9867 = devm_kzalloc(&i2c->dev, sizeof(*max9867), GFP_KERNEL);
if (!max9867)
return -ENOMEM;
i2c_set_clientdata(i2c, max9867);
max9867->regmap = devm_regmap_init_i2c(i2c, &max9867_regmap);
if (IS_ERR(max9867->regmap)) {
ret = PTR_ERR(max9867->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
ret = regmap_read(max9867->regmap, MAX9867_REVISION, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read: %d\n", ret);
return ret;
}
dev_info(&i2c->dev, "device revision: %x\n", reg);
ret = devm_snd_soc_register_component(&i2c->dev, &max9867_component,
max9867_dai, ARRAY_SIZE(max9867_dai));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
return ret;
}
max9867->mclk = devm_clk_get(&i2c->dev, NULL);
if (IS_ERR(max9867->mclk))
return PTR_ERR(max9867->mclk);
return 0;
}
static const struct i2c_device_id max9867_i2c_id[] = {
{ "max9867", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9867_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id max9867_of_match[] = {
{ .compatible = "maxim,max9867", },
{ }
};
MODULE_DEVICE_TABLE(of, max9867_of_match);
#endif
static struct i2c_driver max9867_i2c_driver = {
.driver = {
.name = "max9867",
.of_match_table = of_match_ptr(max9867_of_match),
},
.probe = max9867_i2c_probe,
.id_table = max9867_i2c_id,
};
module_i2c_driver(max9867_i2c_driver);
MODULE_AUTHOR("Ladislav Michl <[email protected]>");
MODULE_DESCRIPTION("ASoC MAX9867 driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max9867.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DA7213 ALSA SoC Codec Driver
*
* Copyright (c) 2013 Dialog Semiconductor
*
* Author: Adam Thomson <[email protected]>
* Based on DA9055 ALSA SoC codec driver.
*/
#include <linux/acpi.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/da7213.h>
#include "da7213.h"
/* Gain and Volume */
static const DECLARE_TLV_DB_RANGE(aux_vol_tlv,
/* -54dB */
0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
/* -52.5dB to 15dB */
0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
);
static const DECLARE_TLV_DB_RANGE(digital_gain_tlv,
0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* -78dB to 12dB */
0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
);
static const DECLARE_TLV_DB_RANGE(alc_analog_gain_tlv,
0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
/* 0dB to 36dB */
0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0)
);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0);
/* ADC and DAC voice mode (8kHz) high pass cutoff value */
static const char * const da7213_voice_hpf_corner_txt[] = {
"2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_voice_hpf_corner,
DA7213_DAC_FILTERS1,
DA7213_VOICE_HPF_CORNER_SHIFT,
da7213_voice_hpf_corner_txt);
static SOC_ENUM_SINGLE_DECL(da7213_adc_voice_hpf_corner,
DA7213_ADC_FILTERS1,
DA7213_VOICE_HPF_CORNER_SHIFT,
da7213_voice_hpf_corner_txt);
/* ADC and DAC high pass filter cutoff value */
static const char * const da7213_audio_hpf_corner_txt[] = {
"Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_audio_hpf_corner,
DA7213_DAC_FILTERS1
, DA7213_AUDIO_HPF_CORNER_SHIFT,
da7213_audio_hpf_corner_txt);
static SOC_ENUM_SINGLE_DECL(da7213_adc_audio_hpf_corner,
DA7213_ADC_FILTERS1,
DA7213_AUDIO_HPF_CORNER_SHIFT,
da7213_audio_hpf_corner_txt);
/* Gain ramping rate value */
static const char * const da7213_gain_ramp_rate_txt[] = {
"nominal rate * 8", "nominal rate * 16", "nominal rate / 16",
"nominal rate / 32"
};
static SOC_ENUM_SINGLE_DECL(da7213_gain_ramp_rate,
DA7213_GAIN_RAMP_CTRL,
DA7213_GAIN_RAMP_RATE_SHIFT,
da7213_gain_ramp_rate_txt);
/* DAC noise gate setup time value */
static const char * const da7213_dac_ng_setup_time_txt[] = {
"256 samples", "512 samples", "1024 samples", "2048 samples"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_ng_setup_time,
DA7213_DAC_NG_SETUP_TIME,
DA7213_DAC_NG_SETUP_TIME_SHIFT,
da7213_dac_ng_setup_time_txt);
/* DAC noise gate rampup rate value */
static const char * const da7213_dac_ng_rampup_txt[] = {
"0.02 ms/dB", "0.16 ms/dB"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_ng_rampup_rate,
DA7213_DAC_NG_SETUP_TIME,
DA7213_DAC_NG_RAMPUP_RATE_SHIFT,
da7213_dac_ng_rampup_txt);
/* DAC noise gate rampdown rate value */
static const char * const da7213_dac_ng_rampdown_txt[] = {
"0.64 ms/dB", "20.48 ms/dB"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_ng_rampdown_rate,
DA7213_DAC_NG_SETUP_TIME,
DA7213_DAC_NG_RAMPDN_RATE_SHIFT,
da7213_dac_ng_rampdown_txt);
/* DAC soft mute rate value */
static const char * const da7213_dac_soft_mute_rate_txt[] = {
"1", "2", "4", "8", "16", "32", "64"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_soft_mute_rate,
DA7213_DAC_FILTERS5,
DA7213_DAC_SOFTMUTE_RATE_SHIFT,
da7213_dac_soft_mute_rate_txt);
/* ALC Attack Rate select */
static const char * const da7213_alc_attack_rate_txt[] = {
"44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
"5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
};
static SOC_ENUM_SINGLE_DECL(da7213_alc_attack_rate,
DA7213_ALC_CTRL2,
DA7213_ALC_ATTACK_SHIFT,
da7213_alc_attack_rate_txt);
/* ALC Release Rate select */
static const char * const da7213_alc_release_rate_txt[] = {
"176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
"11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
};
static SOC_ENUM_SINGLE_DECL(da7213_alc_release_rate,
DA7213_ALC_CTRL2,
DA7213_ALC_RELEASE_SHIFT,
da7213_alc_release_rate_txt);
/* ALC Hold Time select */
static const char * const da7213_alc_hold_time_txt[] = {
"62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
"7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
"253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
};
static SOC_ENUM_SINGLE_DECL(da7213_alc_hold_time,
DA7213_ALC_CTRL3,
DA7213_ALC_HOLD_SHIFT,
da7213_alc_hold_time_txt);
/* ALC Input Signal Tracking rate select */
static const char * const da7213_alc_integ_rate_txt[] = {
"1/4", "1/16", "1/256", "1/65536"
};
static SOC_ENUM_SINGLE_DECL(da7213_alc_integ_attack_rate,
DA7213_ALC_CTRL3,
DA7213_ALC_INTEG_ATTACK_SHIFT,
da7213_alc_integ_rate_txt);
static SOC_ENUM_SINGLE_DECL(da7213_alc_integ_release_rate,
DA7213_ALC_CTRL3,
DA7213_ALC_INTEG_RELEASE_SHIFT,
da7213_alc_integ_rate_txt);
/*
* Control Functions
*/
static int da7213_get_alc_data(struct snd_soc_component *component, u8 reg_val)
{
int mid_data, top_data;
int sum = 0;
u8 iteration;
for (iteration = 0; iteration < DA7213_ALC_AVG_ITERATIONS;
iteration++) {
/* Select the left or right channel and capture data */
snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL, reg_val);
/* Select middle 8 bits for read back from data register */
snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL,
reg_val | DA7213_ALC_DATA_MIDDLE);
mid_data = snd_soc_component_read(component, DA7213_ALC_CIC_OP_LVL_DATA);
/* Select top 8 bits for read back from data register */
snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL,
reg_val | DA7213_ALC_DATA_TOP);
top_data = snd_soc_component_read(component, DA7213_ALC_CIC_OP_LVL_DATA);
sum += ((mid_data << 8) | (top_data << 16));
}
return sum / DA7213_ALC_AVG_ITERATIONS;
}
static void da7213_alc_calib_man(struct snd_soc_component *component)
{
u8 reg_val;
int avg_left_data, avg_right_data, offset_l, offset_r;
/* Calculate average for Left and Right data */
/* Left Data */
avg_left_data = da7213_get_alc_data(component,
DA7213_ALC_CIC_OP_CHANNEL_LEFT);
/* Right Data */
avg_right_data = da7213_get_alc_data(component,
DA7213_ALC_CIC_OP_CHANNEL_RIGHT);
/* Calculate DC offset */
offset_l = -avg_left_data;
offset_r = -avg_right_data;
reg_val = (offset_l & DA7213_ALC_OFFSET_15_8) >> 8;
snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_L, reg_val);
reg_val = (offset_l & DA7213_ALC_OFFSET_19_16) >> 16;
snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_L, reg_val);
reg_val = (offset_r & DA7213_ALC_OFFSET_15_8) >> 8;
snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_R, reg_val);
reg_val = (offset_r & DA7213_ALC_OFFSET_19_16) >> 16;
snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_R, reg_val);
/* Enable analog/digital gain mode & offset cancellation */
snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE,
DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE);
}
static void da7213_alc_calib_auto(struct snd_soc_component *component)
{
u8 alc_ctrl1;
/* Begin auto calibration and wait for completion */
snd_soc_component_update_bits(component, DA7213_ALC_CTRL1, DA7213_ALC_AUTO_CALIB_EN,
DA7213_ALC_AUTO_CALIB_EN);
do {
alc_ctrl1 = snd_soc_component_read(component, DA7213_ALC_CTRL1);
} while (alc_ctrl1 & DA7213_ALC_AUTO_CALIB_EN);
/* If auto calibration fails, fall back to digital gain only mode */
if (alc_ctrl1 & DA7213_ALC_CALIB_OVERFLOW) {
dev_warn(component->dev,
"ALC auto calibration failed with overflow\n");
snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE,
0);
} else {
/* Enable analog/digital gain mode & offset cancellation */
snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE,
DA7213_ALC_OFFSET_EN | DA7213_ALC_SYNC_MODE);
}
}
static void da7213_alc_calib(struct snd_soc_component *component)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
u8 adc_l_ctrl, adc_r_ctrl;
u8 mixin_l_sel, mixin_r_sel;
u8 mic_1_ctrl, mic_2_ctrl;
/* Save current values from ADC control registers */
adc_l_ctrl = snd_soc_component_read(component, DA7213_ADC_L_CTRL);
adc_r_ctrl = snd_soc_component_read(component, DA7213_ADC_R_CTRL);
/* Save current values from MIXIN_L/R_SELECT registers */
mixin_l_sel = snd_soc_component_read(component, DA7213_MIXIN_L_SELECT);
mixin_r_sel = snd_soc_component_read(component, DA7213_MIXIN_R_SELECT);
/* Save current values from MIC control registers */
mic_1_ctrl = snd_soc_component_read(component, DA7213_MIC_1_CTRL);
mic_2_ctrl = snd_soc_component_read(component, DA7213_MIC_2_CTRL);
/* Enable ADC Left and Right */
snd_soc_component_update_bits(component, DA7213_ADC_L_CTRL, DA7213_ADC_EN,
DA7213_ADC_EN);
snd_soc_component_update_bits(component, DA7213_ADC_R_CTRL, DA7213_ADC_EN,
DA7213_ADC_EN);
/* Enable MIC paths */
snd_soc_component_update_bits(component, DA7213_MIXIN_L_SELECT,
DA7213_MIXIN_L_MIX_SELECT_MIC_1 |
DA7213_MIXIN_L_MIX_SELECT_MIC_2,
DA7213_MIXIN_L_MIX_SELECT_MIC_1 |
DA7213_MIXIN_L_MIX_SELECT_MIC_2);
snd_soc_component_update_bits(component, DA7213_MIXIN_R_SELECT,
DA7213_MIXIN_R_MIX_SELECT_MIC_2 |
DA7213_MIXIN_R_MIX_SELECT_MIC_1,
DA7213_MIXIN_R_MIX_SELECT_MIC_2 |
DA7213_MIXIN_R_MIX_SELECT_MIC_1);
/* Mute MIC PGAs */
snd_soc_component_update_bits(component, DA7213_MIC_1_CTRL, DA7213_MUTE_EN,
DA7213_MUTE_EN);
snd_soc_component_update_bits(component, DA7213_MIC_2_CTRL, DA7213_MUTE_EN,
DA7213_MUTE_EN);
/* Perform calibration */
if (da7213->alc_calib_auto)
da7213_alc_calib_auto(component);
else
da7213_alc_calib_man(component);
/* Restore MIXIN_L/R_SELECT registers to their original states */
snd_soc_component_write(component, DA7213_MIXIN_L_SELECT, mixin_l_sel);
snd_soc_component_write(component, DA7213_MIXIN_R_SELECT, mixin_r_sel);
/* Restore ADC control registers to their original states */
snd_soc_component_write(component, DA7213_ADC_L_CTRL, adc_l_ctrl);
snd_soc_component_write(component, DA7213_ADC_R_CTRL, adc_r_ctrl);
/* Restore original values of MIC control registers */
snd_soc_component_write(component, DA7213_MIC_1_CTRL, mic_1_ctrl);
snd_soc_component_write(component, DA7213_MIC_2_CTRL, mic_2_ctrl);
}
static int da7213_put_mixin_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
/* If ALC in operation, make sure calibrated offsets are updated */
if ((!ret) && (da7213->alc_en))
da7213_alc_calib(component);
return ret;
}
static int da7213_put_alc_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
/* Force ALC offset calibration if enabling ALC */
if (ucontrol->value.integer.value[0] ||
ucontrol->value.integer.value[1]) {
if (!da7213->alc_en) {
da7213_alc_calib(component);
da7213->alc_en = true;
}
} else {
da7213->alc_en = false;
}
return snd_soc_put_volsw(kcontrol, ucontrol);
}
/*
* KControls
*/
static const struct snd_kcontrol_new da7213_snd_controls[] = {
/* Volume controls */
SOC_SINGLE_TLV("Mic 1 Volume", DA7213_MIC_1_GAIN,
DA7213_MIC_AMP_GAIN_SHIFT, DA7213_MIC_AMP_GAIN_MAX,
DA7213_NO_INVERT, mic_vol_tlv),
SOC_SINGLE_TLV("Mic 2 Volume", DA7213_MIC_2_GAIN,
DA7213_MIC_AMP_GAIN_SHIFT, DA7213_MIC_AMP_GAIN_MAX,
DA7213_NO_INVERT, mic_vol_tlv),
SOC_DOUBLE_R_TLV("Aux Volume", DA7213_AUX_L_GAIN, DA7213_AUX_R_GAIN,
DA7213_AUX_AMP_GAIN_SHIFT, DA7213_AUX_AMP_GAIN_MAX,
DA7213_NO_INVERT, aux_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("Mixin PGA Volume", DA7213_MIXIN_L_GAIN,
DA7213_MIXIN_R_GAIN, DA7213_MIXIN_AMP_GAIN_SHIFT,
DA7213_MIXIN_AMP_GAIN_MAX, DA7213_NO_INVERT,
snd_soc_get_volsw_2r, da7213_put_mixin_gain,
mixin_gain_tlv),
SOC_DOUBLE_R_TLV("ADC Volume", DA7213_ADC_L_GAIN, DA7213_ADC_R_GAIN,
DA7213_ADC_AMP_GAIN_SHIFT, DA7213_ADC_AMP_GAIN_MAX,
DA7213_NO_INVERT, digital_gain_tlv),
SOC_DOUBLE_R_TLV("DAC Volume", DA7213_DAC_L_GAIN, DA7213_DAC_R_GAIN,
DA7213_DAC_AMP_GAIN_SHIFT, DA7213_DAC_AMP_GAIN_MAX,
DA7213_NO_INVERT, digital_gain_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", DA7213_HP_L_GAIN, DA7213_HP_R_GAIN,
DA7213_HP_AMP_GAIN_SHIFT, DA7213_HP_AMP_GAIN_MAX,
DA7213_NO_INVERT, hp_vol_tlv),
SOC_SINGLE_TLV("Lineout Volume", DA7213_LINE_GAIN,
DA7213_LINE_AMP_GAIN_SHIFT, DA7213_LINE_AMP_GAIN_MAX,
DA7213_NO_INVERT, lineout_vol_tlv),
/* DAC Equalizer controls */
SOC_SINGLE("DAC EQ Switch", DA7213_DAC_FILTERS4, DA7213_DAC_EQ_EN_SHIFT,
DA7213_DAC_EQ_EN_MAX, DA7213_NO_INVERT),
SOC_SINGLE_TLV("DAC EQ1 Volume", DA7213_DAC_FILTERS2,
DA7213_DAC_EQ_BAND1_SHIFT, DA7213_DAC_EQ_BAND_MAX,
DA7213_NO_INVERT, eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ2 Volume", DA7213_DAC_FILTERS2,
DA7213_DAC_EQ_BAND2_SHIFT, DA7213_DAC_EQ_BAND_MAX,
DA7213_NO_INVERT, eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ3 Volume", DA7213_DAC_FILTERS3,
DA7213_DAC_EQ_BAND3_SHIFT, DA7213_DAC_EQ_BAND_MAX,
DA7213_NO_INVERT, eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ4 Volume", DA7213_DAC_FILTERS3,
DA7213_DAC_EQ_BAND4_SHIFT, DA7213_DAC_EQ_BAND_MAX,
DA7213_NO_INVERT, eq_gain_tlv),
SOC_SINGLE_TLV("DAC EQ5 Volume", DA7213_DAC_FILTERS4,
DA7213_DAC_EQ_BAND5_SHIFT, DA7213_DAC_EQ_BAND_MAX,
DA7213_NO_INVERT, eq_gain_tlv),
/* High Pass Filter and Voice Mode controls */
SOC_SINGLE("ADC HPF Switch", DA7213_ADC_FILTERS1, DA7213_HPF_EN_SHIFT,
DA7213_HPF_EN_MAX, DA7213_NO_INVERT),
SOC_ENUM("ADC HPF Cutoff", da7213_adc_audio_hpf_corner),
SOC_SINGLE("ADC Voice Mode Switch", DA7213_ADC_FILTERS1,
DA7213_VOICE_EN_SHIFT, DA7213_VOICE_EN_MAX,
DA7213_NO_INVERT),
SOC_ENUM("ADC Voice Cutoff", da7213_adc_voice_hpf_corner),
SOC_SINGLE("DAC HPF Switch", DA7213_DAC_FILTERS1, DA7213_HPF_EN_SHIFT,
DA7213_HPF_EN_MAX, DA7213_NO_INVERT),
SOC_ENUM("DAC HPF Cutoff", da7213_dac_audio_hpf_corner),
SOC_SINGLE("DAC Voice Mode Switch", DA7213_DAC_FILTERS1,
DA7213_VOICE_EN_SHIFT, DA7213_VOICE_EN_MAX,
DA7213_NO_INVERT),
SOC_ENUM("DAC Voice Cutoff", da7213_dac_voice_hpf_corner),
/* Mute controls */
SOC_SINGLE("Mic 1 Switch", DA7213_MIC_1_CTRL, DA7213_MUTE_EN_SHIFT,
DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_SINGLE("Mic 2 Switch", DA7213_MIC_2_CTRL, DA7213_MUTE_EN_SHIFT,
DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_DOUBLE_R("Aux Switch", DA7213_AUX_L_CTRL, DA7213_AUX_R_CTRL,
DA7213_MUTE_EN_SHIFT, DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_DOUBLE_R("Mixin PGA Switch", DA7213_MIXIN_L_CTRL,
DA7213_MIXIN_R_CTRL, DA7213_MUTE_EN_SHIFT,
DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_DOUBLE_R("ADC Switch", DA7213_ADC_L_CTRL, DA7213_ADC_R_CTRL,
DA7213_MUTE_EN_SHIFT, DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_DOUBLE_R("Headphone Switch", DA7213_HP_L_CTRL, DA7213_HP_R_CTRL,
DA7213_MUTE_EN_SHIFT, DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_SINGLE("Lineout Switch", DA7213_LINE_CTRL, DA7213_MUTE_EN_SHIFT,
DA7213_MUTE_EN_MAX, DA7213_INVERT),
SOC_SINGLE("DAC Soft Mute Switch", DA7213_DAC_FILTERS5,
DA7213_DAC_SOFTMUTE_EN_SHIFT, DA7213_DAC_SOFTMUTE_EN_MAX,
DA7213_NO_INVERT),
SOC_ENUM("DAC Soft Mute Rate", da7213_dac_soft_mute_rate),
/* Zero Cross controls */
SOC_DOUBLE_R("Aux ZC Switch", DA7213_AUX_L_CTRL, DA7213_AUX_R_CTRL,
DA7213_ZC_EN_SHIFT, DA7213_ZC_EN_MAX, DA7213_NO_INVERT),
SOC_DOUBLE_R("Mixin PGA ZC Switch", DA7213_MIXIN_L_CTRL,
DA7213_MIXIN_R_CTRL, DA7213_ZC_EN_SHIFT, DA7213_ZC_EN_MAX,
DA7213_NO_INVERT),
SOC_DOUBLE_R("Headphone ZC Switch", DA7213_HP_L_CTRL, DA7213_HP_R_CTRL,
DA7213_ZC_EN_SHIFT, DA7213_ZC_EN_MAX, DA7213_NO_INVERT),
/* Gain Ramping controls */
SOC_DOUBLE_R("Aux Gain Ramping Switch", DA7213_AUX_L_CTRL,
DA7213_AUX_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA7213_MIXIN_L_CTRL,
DA7213_MIXIN_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
SOC_DOUBLE_R("ADC Gain Ramping Switch", DA7213_ADC_L_CTRL,
DA7213_ADC_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
SOC_DOUBLE_R("DAC Gain Ramping Switch", DA7213_DAC_L_CTRL,
DA7213_DAC_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA7213_HP_L_CTRL,
DA7213_HP_R_CTRL, DA7213_GAIN_RAMP_EN_SHIFT,
DA7213_GAIN_RAMP_EN_MAX, DA7213_NO_INVERT),
SOC_SINGLE("Lineout Gain Ramping Switch", DA7213_LINE_CTRL,
DA7213_GAIN_RAMP_EN_SHIFT, DA7213_GAIN_RAMP_EN_MAX,
DA7213_NO_INVERT),
SOC_ENUM("Gain Ramping Rate", da7213_gain_ramp_rate),
/* DAC Noise Gate controls */
SOC_SINGLE("DAC NG Switch", DA7213_DAC_NG_CTRL, DA7213_DAC_NG_EN_SHIFT,
DA7213_DAC_NG_EN_MAX, DA7213_NO_INVERT),
SOC_ENUM("DAC NG Setup Time", da7213_dac_ng_setup_time),
SOC_ENUM("DAC NG Rampup Rate", da7213_dac_ng_rampup_rate),
SOC_ENUM("DAC NG Rampdown Rate", da7213_dac_ng_rampdown_rate),
SOC_SINGLE("DAC NG OFF Threshold", DA7213_DAC_NG_OFF_THRESHOLD,
DA7213_DAC_NG_THRESHOLD_SHIFT, DA7213_DAC_NG_THRESHOLD_MAX,
DA7213_NO_INVERT),
SOC_SINGLE("DAC NG ON Threshold", DA7213_DAC_NG_ON_THRESHOLD,
DA7213_DAC_NG_THRESHOLD_SHIFT, DA7213_DAC_NG_THRESHOLD_MAX,
DA7213_NO_INVERT),
/* DAC Routing & Inversion */
SOC_DOUBLE("DAC Mono Switch", DA7213_DIG_ROUTING_DAC,
DA7213_DAC_L_MONO_SHIFT, DA7213_DAC_R_MONO_SHIFT,
DA7213_DAC_MONO_MAX, DA7213_NO_INVERT),
SOC_DOUBLE("DAC Invert Switch", DA7213_DIG_CTRL, DA7213_DAC_L_INV_SHIFT,
DA7213_DAC_R_INV_SHIFT, DA7213_DAC_INV_MAX,
DA7213_NO_INVERT),
/* DMIC controls */
SOC_DOUBLE_R("DMIC Switch", DA7213_MIXIN_L_SELECT,
DA7213_MIXIN_R_SELECT, DA7213_DMIC_EN_SHIFT,
DA7213_DMIC_EN_MAX, DA7213_NO_INVERT),
/* ALC Controls */
SOC_DOUBLE_EXT("ALC Switch", DA7213_ALC_CTRL1, DA7213_ALC_L_EN_SHIFT,
DA7213_ALC_R_EN_SHIFT, DA7213_ALC_EN_MAX,
DA7213_NO_INVERT, snd_soc_get_volsw, da7213_put_alc_sw),
SOC_ENUM("ALC Attack Rate", da7213_alc_attack_rate),
SOC_ENUM("ALC Release Rate", da7213_alc_release_rate),
SOC_ENUM("ALC Hold Time", da7213_alc_hold_time),
/*
* Rate at which input signal envelope is tracked as the signal gets
* larger
*/
SOC_ENUM("ALC Integ Attack Rate", da7213_alc_integ_attack_rate),
/*
* Rate at which input signal envelope is tracked as the signal gets
* smaller
*/
SOC_ENUM("ALC Integ Release Rate", da7213_alc_integ_release_rate),
SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA7213_ALC_NOISE,
DA7213_ALC_THRESHOLD_SHIFT, DA7213_ALC_THRESHOLD_MAX,
DA7213_INVERT, alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Min Threshold Volume", DA7213_ALC_TARGET_MIN,
DA7213_ALC_THRESHOLD_SHIFT, DA7213_ALC_THRESHOLD_MAX,
DA7213_INVERT, alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Threshold Volume", DA7213_ALC_TARGET_MAX,
DA7213_ALC_THRESHOLD_SHIFT, DA7213_ALC_THRESHOLD_MAX,
DA7213_INVERT, alc_threshold_tlv),
SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA7213_ALC_GAIN_LIMITS,
DA7213_ALC_ATTEN_MAX_SHIFT,
DA7213_ALC_ATTEN_GAIN_MAX_MAX, DA7213_NO_INVERT,
alc_gain_tlv),
SOC_SINGLE_TLV("ALC Max Gain Volume", DA7213_ALC_GAIN_LIMITS,
DA7213_ALC_GAIN_MAX_SHIFT, DA7213_ALC_ATTEN_GAIN_MAX_MAX,
DA7213_NO_INVERT, alc_gain_tlv),
SOC_SINGLE_TLV("ALC Min Analog Gain Volume", DA7213_ALC_ANA_GAIN_LIMITS,
DA7213_ALC_ANA_GAIN_MIN_SHIFT, DA7213_ALC_ANA_GAIN_MAX,
DA7213_NO_INVERT, alc_analog_gain_tlv),
SOC_SINGLE_TLV("ALC Max Analog Gain Volume", DA7213_ALC_ANA_GAIN_LIMITS,
DA7213_ALC_ANA_GAIN_MAX_SHIFT, DA7213_ALC_ANA_GAIN_MAX,
DA7213_NO_INVERT, alc_analog_gain_tlv),
SOC_SINGLE("ALC Anticlip Mode Switch", DA7213_ALC_ANTICLIP_CTRL,
DA7213_ALC_ANTICLIP_EN_SHIFT, DA7213_ALC_ANTICLIP_EN_MAX,
DA7213_NO_INVERT),
SOC_SINGLE("ALC Anticlip Level", DA7213_ALC_ANTICLIP_LEVEL,
DA7213_ALC_ANTICLIP_LEVEL_SHIFT,
DA7213_ALC_ANTICLIP_LEVEL_MAX, DA7213_NO_INVERT),
};
/*
* DAPM
*/
/*
* Enums
*/
/* MIC PGA source select */
static const char * const da7213_mic_amp_in_sel_txt[] = {
"Differential", "MIC_P", "MIC_N"
};
static SOC_ENUM_SINGLE_DECL(da7213_mic_1_amp_in_sel,
DA7213_MIC_1_CTRL,
DA7213_MIC_AMP_IN_SEL_SHIFT,
da7213_mic_amp_in_sel_txt);
static const struct snd_kcontrol_new da7213_mic_1_amp_in_sel_mux =
SOC_DAPM_ENUM("Mic 1 Amp Source MUX", da7213_mic_1_amp_in_sel);
static SOC_ENUM_SINGLE_DECL(da7213_mic_2_amp_in_sel,
DA7213_MIC_2_CTRL,
DA7213_MIC_AMP_IN_SEL_SHIFT,
da7213_mic_amp_in_sel_txt);
static const struct snd_kcontrol_new da7213_mic_2_amp_in_sel_mux =
SOC_DAPM_ENUM("Mic 2 Amp Source MUX", da7213_mic_2_amp_in_sel);
/* DAI routing select */
static const char * const da7213_dai_src_txt[] = {
"ADC Left", "ADC Right", "DAI Input Left", "DAI Input Right"
};
static SOC_ENUM_SINGLE_DECL(da7213_dai_l_src,
DA7213_DIG_ROUTING_DAI,
DA7213_DAI_L_SRC_SHIFT,
da7213_dai_src_txt);
static const struct snd_kcontrol_new da7213_dai_l_src_mux =
SOC_DAPM_ENUM("DAI Left Source MUX", da7213_dai_l_src);
static SOC_ENUM_SINGLE_DECL(da7213_dai_r_src,
DA7213_DIG_ROUTING_DAI,
DA7213_DAI_R_SRC_SHIFT,
da7213_dai_src_txt);
static const struct snd_kcontrol_new da7213_dai_r_src_mux =
SOC_DAPM_ENUM("DAI Right Source MUX", da7213_dai_r_src);
/* DAC routing select */
static const char * const da7213_dac_src_txt[] = {
"ADC Output Left", "ADC Output Right", "DAI Input Left",
"DAI Input Right"
};
static SOC_ENUM_SINGLE_DECL(da7213_dac_l_src,
DA7213_DIG_ROUTING_DAC,
DA7213_DAC_L_SRC_SHIFT,
da7213_dac_src_txt);
static const struct snd_kcontrol_new da7213_dac_l_src_mux =
SOC_DAPM_ENUM("DAC Left Source MUX", da7213_dac_l_src);
static SOC_ENUM_SINGLE_DECL(da7213_dac_r_src,
DA7213_DIG_ROUTING_DAC,
DA7213_DAC_R_SRC_SHIFT,
da7213_dac_src_txt);
static const struct snd_kcontrol_new da7213_dac_r_src_mux =
SOC_DAPM_ENUM("DAC Right Source MUX", da7213_dac_r_src);
/*
* Mixer Controls
*/
/* Mixin Left */
static const struct snd_kcontrol_new da7213_dapm_mixinl_controls[] = {
SOC_DAPM_SINGLE("Aux Left Switch", DA7213_MIXIN_L_SELECT,
DA7213_MIXIN_L_MIX_SELECT_AUX_L_SHIFT,
DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mic 1 Switch", DA7213_MIXIN_L_SELECT,
DA7213_MIXIN_L_MIX_SELECT_MIC_1_SHIFT,
DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mic 2 Switch", DA7213_MIXIN_L_SELECT,
DA7213_MIXIN_L_MIX_SELECT_MIC_2_SHIFT,
DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Right Switch", DA7213_MIXIN_L_SELECT,
DA7213_MIXIN_L_MIX_SELECT_MIXIN_R_SHIFT,
DA7213_MIXIN_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
};
/* Mixin Right */
static const struct snd_kcontrol_new da7213_dapm_mixinr_controls[] = {
SOC_DAPM_SINGLE("Aux Right Switch", DA7213_MIXIN_R_SELECT,
DA7213_MIXIN_R_MIX_SELECT_AUX_R_SHIFT,
DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mic 2 Switch", DA7213_MIXIN_R_SELECT,
DA7213_MIXIN_R_MIX_SELECT_MIC_2_SHIFT,
DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mic 1 Switch", DA7213_MIXIN_R_SELECT,
DA7213_MIXIN_R_MIX_SELECT_MIC_1_SHIFT,
DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Left Switch", DA7213_MIXIN_R_SELECT,
DA7213_MIXIN_R_MIX_SELECT_MIXIN_L_SHIFT,
DA7213_MIXIN_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
};
/* Mixout Left */
static const struct snd_kcontrol_new da7213_dapm_mixoutl_controls[] = {
SOC_DAPM_SINGLE("Aux Left Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_AUX_L_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Left Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_MIXIN_L_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Right Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_MIXIN_R_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("DAC Left Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_DAC_L_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Aux Left Invert Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_AUX_L_INVERTED_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_MIXIN_L_INVERTED_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA7213_MIXOUT_L_SELECT,
DA7213_MIXOUT_L_MIX_SELECT_MIXIN_R_INVERTED_SHIFT,
DA7213_MIXOUT_L_MIX_SELECT_MAX, DA7213_NO_INVERT),
};
/* Mixout Right */
static const struct snd_kcontrol_new da7213_dapm_mixoutr_controls[] = {
SOC_DAPM_SINGLE("Aux Right Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_AUX_R_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Right Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_MIXIN_R_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Left Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_MIXIN_L_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("DAC Right Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_DAC_R_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Aux Right Invert Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_AUX_R_INVERTED_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_MIXIN_R_INVERTED_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA7213_MIXOUT_R_SELECT,
DA7213_MIXOUT_R_MIX_SELECT_MIXIN_L_INVERTED_SHIFT,
DA7213_MIXOUT_R_MIX_SELECT_MAX, DA7213_NO_INVERT),
};
/*
* DAPM Events
*/
static int da7213_dai_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
u8 pll_ctrl, pll_status;
int i = 0;
bool srm_lock = false;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Enable DAI clks for master mode */
if (da7213->master)
snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
DA7213_DAI_CLK_EN_MASK,
DA7213_DAI_CLK_EN_MASK);
/* PC synchronised to DAI */
snd_soc_component_update_bits(component, DA7213_PC_COUNT,
DA7213_PC_FREERUN_MASK, 0);
/* If SRM not enabled then nothing more to do */
pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL);
if (!(pll_ctrl & DA7213_PLL_SRM_EN))
return 0;
/* Assist 32KHz mode PLL lock */
if (pll_ctrl & DA7213_PLL_32K_MODE) {
snd_soc_component_write(component, 0xF0, 0x8B);
snd_soc_component_write(component, 0xF2, 0x03);
snd_soc_component_write(component, 0xF0, 0x00);
}
/* Check SRM has locked */
do {
pll_status = snd_soc_component_read(component, DA7213_PLL_STATUS);
if (pll_status & DA7219_PLL_SRM_LOCK) {
srm_lock = true;
} else {
++i;
msleep(50);
}
} while ((i < DA7213_SRM_CHECK_RETRIES) && (!srm_lock));
if (!srm_lock)
dev_warn(component->dev, "SRM failed to lock\n");
return 0;
case SND_SOC_DAPM_POST_PMD:
/* Revert 32KHz PLL lock udpates if applied previously */
pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL);
if (pll_ctrl & DA7213_PLL_32K_MODE) {
snd_soc_component_write(component, 0xF0, 0x8B);
snd_soc_component_write(component, 0xF2, 0x01);
snd_soc_component_write(component, 0xF0, 0x00);
}
/* PC free-running */
snd_soc_component_update_bits(component, DA7213_PC_COUNT,
DA7213_PC_FREERUN_MASK,
DA7213_PC_FREERUN_MASK);
/* Disable DAI clks if in master mode */
if (da7213->master)
snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
DA7213_DAI_CLK_EN_MASK, 0);
return 0;
default:
return -EINVAL;
}
}
/*
* DAPM widgets
*/
static const struct snd_soc_dapm_widget da7213_dapm_widgets[] = {
/*
* Power Supply
*/
SND_SOC_DAPM_REGULATOR_SUPPLY("VDDMIC", 0, 0),
/*
* Input & Output
*/
/* Use a supply here as this controls both input & output DAIs */
SND_SOC_DAPM_SUPPLY("DAI", DA7213_DAI_CTRL, DA7213_DAI_EN_SHIFT,
DA7213_NO_INVERT, da7213_dai_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/*
* Input
*/
/* Input Lines */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("AUXL"),
SND_SOC_DAPM_INPUT("AUXR"),
/* MUXs for Mic PGA source selection */
SND_SOC_DAPM_MUX("Mic 1 Amp Source MUX", SND_SOC_NOPM, 0, 0,
&da7213_mic_1_amp_in_sel_mux),
SND_SOC_DAPM_MUX("Mic 2 Amp Source MUX", SND_SOC_NOPM, 0, 0,
&da7213_mic_2_amp_in_sel_mux),
/* Input PGAs */
SND_SOC_DAPM_PGA("Mic 1 PGA", DA7213_MIC_1_CTRL, DA7213_AMP_EN_SHIFT,
DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Mic 2 PGA", DA7213_MIC_2_CTRL, DA7213_AMP_EN_SHIFT,
DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Aux Left PGA", DA7213_AUX_L_CTRL, DA7213_AMP_EN_SHIFT,
DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Aux Right PGA", DA7213_AUX_R_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Mixin Left PGA", DA7213_MIXIN_L_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Mixin Right PGA", DA7213_MIXIN_R_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
/* Mic Biases */
SND_SOC_DAPM_SUPPLY("Mic Bias 1", DA7213_MICBIAS_CTRL,
DA7213_MICBIAS1_EN_SHIFT, DA7213_NO_INVERT,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias 2", DA7213_MICBIAS_CTRL,
DA7213_MICBIAS2_EN_SHIFT, DA7213_NO_INVERT,
NULL, 0),
/* Input Mixers */
SND_SOC_DAPM_MIXER("Mixin Left", SND_SOC_NOPM, 0, 0,
&da7213_dapm_mixinl_controls[0],
ARRAY_SIZE(da7213_dapm_mixinl_controls)),
SND_SOC_DAPM_MIXER("Mixin Right", SND_SOC_NOPM, 0, 0,
&da7213_dapm_mixinr_controls[0],
ARRAY_SIZE(da7213_dapm_mixinr_controls)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC Left", NULL, DA7213_ADC_L_CTRL,
DA7213_ADC_EN_SHIFT, DA7213_NO_INVERT),
SND_SOC_DAPM_ADC("ADC Right", NULL, DA7213_ADC_R_CTRL,
DA7213_ADC_EN_SHIFT, DA7213_NO_INVERT),
/* DAI */
SND_SOC_DAPM_MUX("DAI Left Source MUX", SND_SOC_NOPM, 0, 0,
&da7213_dai_l_src_mux),
SND_SOC_DAPM_MUX("DAI Right Source MUX", SND_SOC_NOPM, 0, 0,
&da7213_dai_r_src_mux),
SND_SOC_DAPM_AIF_OUT("DAIOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DAIOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
/*
* Output
*/
/* DAI */
SND_SOC_DAPM_AIF_IN("DAIINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("DAIINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DAC Left Source MUX", SND_SOC_NOPM, 0, 0,
&da7213_dac_l_src_mux),
SND_SOC_DAPM_MUX("DAC Right Source MUX", SND_SOC_NOPM, 0, 0,
&da7213_dac_r_src_mux),
/* DACs */
SND_SOC_DAPM_DAC("DAC Left", NULL, DA7213_DAC_L_CTRL,
DA7213_DAC_EN_SHIFT, DA7213_NO_INVERT),
SND_SOC_DAPM_DAC("DAC Right", NULL, DA7213_DAC_R_CTRL,
DA7213_DAC_EN_SHIFT, DA7213_NO_INVERT),
/* Output Mixers */
SND_SOC_DAPM_MIXER("Mixout Left", SND_SOC_NOPM, 0, 0,
&da7213_dapm_mixoutl_controls[0],
ARRAY_SIZE(da7213_dapm_mixoutl_controls)),
SND_SOC_DAPM_MIXER("Mixout Right", SND_SOC_NOPM, 0, 0,
&da7213_dapm_mixoutr_controls[0],
ARRAY_SIZE(da7213_dapm_mixoutr_controls)),
/* Output PGAs */
SND_SOC_DAPM_PGA("Mixout Left PGA", DA7213_MIXOUT_L_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Mixout Right PGA", DA7213_MIXOUT_R_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Lineout PGA", DA7213_LINE_CTRL, DA7213_AMP_EN_SHIFT,
DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Headphone Left PGA", DA7213_HP_L_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
SND_SOC_DAPM_PGA("Headphone Right PGA", DA7213_HP_R_CTRL,
DA7213_AMP_EN_SHIFT, DA7213_NO_INVERT, NULL, 0),
/* Charge Pump */
SND_SOC_DAPM_SUPPLY("Charge Pump", DA7213_CP_CTRL, DA7213_CP_EN_SHIFT,
DA7213_NO_INVERT, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("LINE"),
};
/*
* DAPM audio route definition
*/
static const struct snd_soc_dapm_route da7213_audio_map[] = {
/* Dest Connecting Widget source */
/* Input path */
{"Mic Bias 1", NULL, "VDDMIC"},
{"Mic Bias 2", NULL, "VDDMIC"},
{"MIC1", NULL, "Mic Bias 1"},
{"MIC2", NULL, "Mic Bias 2"},
{"Mic 1 Amp Source MUX", "Differential", "MIC1"},
{"Mic 1 Amp Source MUX", "MIC_P", "MIC1"},
{"Mic 1 Amp Source MUX", "MIC_N", "MIC1"},
{"Mic 2 Amp Source MUX", "Differential", "MIC2"},
{"Mic 2 Amp Source MUX", "MIC_P", "MIC2"},
{"Mic 2 Amp Source MUX", "MIC_N", "MIC2"},
{"Mic 1 PGA", NULL, "Mic 1 Amp Source MUX"},
{"Mic 2 PGA", NULL, "Mic 2 Amp Source MUX"},
{"Aux Left PGA", NULL, "AUXL"},
{"Aux Right PGA", NULL, "AUXR"},
{"Mixin Left", "Aux Left Switch", "Aux Left PGA"},
{"Mixin Left", "Mic 1 Switch", "Mic 1 PGA"},
{"Mixin Left", "Mic 2 Switch", "Mic 2 PGA"},
{"Mixin Left", "Mixin Right Switch", "Mixin Right PGA"},
{"Mixin Right", "Aux Right Switch", "Aux Right PGA"},
{"Mixin Right", "Mic 2 Switch", "Mic 2 PGA"},
{"Mixin Right", "Mic 1 Switch", "Mic 1 PGA"},
{"Mixin Right", "Mixin Left Switch", "Mixin Left PGA"},
{"Mixin Left PGA", NULL, "Mixin Left"},
{"ADC Left", NULL, "Mixin Left PGA"},
{"Mixin Right PGA", NULL, "Mixin Right"},
{"ADC Right", NULL, "Mixin Right PGA"},
{"DAI Left Source MUX", "ADC Left", "ADC Left"},
{"DAI Left Source MUX", "ADC Right", "ADC Right"},
{"DAI Left Source MUX", "DAI Input Left", "DAIINL"},
{"DAI Left Source MUX", "DAI Input Right", "DAIINR"},
{"DAI Right Source MUX", "ADC Left", "ADC Left"},
{"DAI Right Source MUX", "ADC Right", "ADC Right"},
{"DAI Right Source MUX", "DAI Input Left", "DAIINL"},
{"DAI Right Source MUX", "DAI Input Right", "DAIINR"},
{"DAIOUTL", NULL, "DAI Left Source MUX"},
{"DAIOUTR", NULL, "DAI Right Source MUX"},
{"DAIOUTL", NULL, "DAI"},
{"DAIOUTR", NULL, "DAI"},
/* Output path */
{"DAIINL", NULL, "DAI"},
{"DAIINR", NULL, "DAI"},
{"DAC Left Source MUX", "ADC Output Left", "ADC Left"},
{"DAC Left Source MUX", "ADC Output Right", "ADC Right"},
{"DAC Left Source MUX", "DAI Input Left", "DAIINL"},
{"DAC Left Source MUX", "DAI Input Right", "DAIINR"},
{"DAC Right Source MUX", "ADC Output Left", "ADC Left"},
{"DAC Right Source MUX", "ADC Output Right", "ADC Right"},
{"DAC Right Source MUX", "DAI Input Left", "DAIINL"},
{"DAC Right Source MUX", "DAI Input Right", "DAIINR"},
{"DAC Left", NULL, "DAC Left Source MUX"},
{"DAC Right", NULL, "DAC Right Source MUX"},
{"Mixout Left", "Aux Left Switch", "Aux Left PGA"},
{"Mixout Left", "Mixin Left Switch", "Mixin Left PGA"},
{"Mixout Left", "Mixin Right Switch", "Mixin Right PGA"},
{"Mixout Left", "DAC Left Switch", "DAC Left"},
{"Mixout Left", "Aux Left Invert Switch", "Aux Left PGA"},
{"Mixout Left", "Mixin Left Invert Switch", "Mixin Left PGA"},
{"Mixout Left", "Mixin Right Invert Switch", "Mixin Right PGA"},
{"Mixout Right", "Aux Right Switch", "Aux Right PGA"},
{"Mixout Right", "Mixin Right Switch", "Mixin Right PGA"},
{"Mixout Right", "Mixin Left Switch", "Mixin Left PGA"},
{"Mixout Right", "DAC Right Switch", "DAC Right"},
{"Mixout Right", "Aux Right Invert Switch", "Aux Right PGA"},
{"Mixout Right", "Mixin Right Invert Switch", "Mixin Right PGA"},
{"Mixout Right", "Mixin Left Invert Switch", "Mixin Left PGA"},
{"Mixout Left PGA", NULL, "Mixout Left"},
{"Mixout Right PGA", NULL, "Mixout Right"},
{"Headphone Left PGA", NULL, "Mixout Left PGA"},
{"Headphone Left PGA", NULL, "Charge Pump"},
{"HPL", NULL, "Headphone Left PGA"},
{"Headphone Right PGA", NULL, "Mixout Right PGA"},
{"Headphone Right PGA", NULL, "Charge Pump"},
{"HPR", NULL, "Headphone Right PGA"},
{"Lineout PGA", NULL, "Mixout Right PGA"},
{"LINE", NULL, "Lineout PGA"},
};
static const struct reg_default da7213_reg_defaults[] = {
{ DA7213_DIG_ROUTING_DAI, 0x10 },
{ DA7213_SR, 0x0A },
{ DA7213_REFERENCES, 0x80 },
{ DA7213_PLL_FRAC_TOP, 0x00 },
{ DA7213_PLL_FRAC_BOT, 0x00 },
{ DA7213_PLL_INTEGER, 0x20 },
{ DA7213_PLL_CTRL, 0x0C },
{ DA7213_DAI_CLK_MODE, 0x01 },
{ DA7213_DAI_CTRL, 0x08 },
{ DA7213_DIG_ROUTING_DAC, 0x32 },
{ DA7213_AUX_L_GAIN, 0x35 },
{ DA7213_AUX_R_GAIN, 0x35 },
{ DA7213_MIXIN_L_SELECT, 0x00 },
{ DA7213_MIXIN_R_SELECT, 0x00 },
{ DA7213_MIXIN_L_GAIN, 0x03 },
{ DA7213_MIXIN_R_GAIN, 0x03 },
{ DA7213_ADC_L_GAIN, 0x6F },
{ DA7213_ADC_R_GAIN, 0x6F },
{ DA7213_ADC_FILTERS1, 0x80 },
{ DA7213_MIC_1_GAIN, 0x01 },
{ DA7213_MIC_2_GAIN, 0x01 },
{ DA7213_DAC_FILTERS5, 0x00 },
{ DA7213_DAC_FILTERS2, 0x88 },
{ DA7213_DAC_FILTERS3, 0x88 },
{ DA7213_DAC_FILTERS4, 0x08 },
{ DA7213_DAC_FILTERS1, 0x80 },
{ DA7213_DAC_L_GAIN, 0x6F },
{ DA7213_DAC_R_GAIN, 0x6F },
{ DA7213_CP_CTRL, 0x61 },
{ DA7213_HP_L_GAIN, 0x39 },
{ DA7213_HP_R_GAIN, 0x39 },
{ DA7213_LINE_GAIN, 0x30 },
{ DA7213_MIXOUT_L_SELECT, 0x00 },
{ DA7213_MIXOUT_R_SELECT, 0x00 },
{ DA7213_SYSTEM_MODES_INPUT, 0x00 },
{ DA7213_SYSTEM_MODES_OUTPUT, 0x00 },
{ DA7213_AUX_L_CTRL, 0x44 },
{ DA7213_AUX_R_CTRL, 0x44 },
{ DA7213_MICBIAS_CTRL, 0x11 },
{ DA7213_MIC_1_CTRL, 0x40 },
{ DA7213_MIC_2_CTRL, 0x40 },
{ DA7213_MIXIN_L_CTRL, 0x40 },
{ DA7213_MIXIN_R_CTRL, 0x40 },
{ DA7213_ADC_L_CTRL, 0x40 },
{ DA7213_ADC_R_CTRL, 0x40 },
{ DA7213_DAC_L_CTRL, 0x48 },
{ DA7213_DAC_R_CTRL, 0x40 },
{ DA7213_HP_L_CTRL, 0x41 },
{ DA7213_HP_R_CTRL, 0x40 },
{ DA7213_LINE_CTRL, 0x40 },
{ DA7213_MIXOUT_L_CTRL, 0x10 },
{ DA7213_MIXOUT_R_CTRL, 0x10 },
{ DA7213_LDO_CTRL, 0x00 },
{ DA7213_IO_CTRL, 0x00 },
{ DA7213_GAIN_RAMP_CTRL, 0x00},
{ DA7213_MIC_CONFIG, 0x00 },
{ DA7213_PC_COUNT, 0x00 },
{ DA7213_CP_VOL_THRESHOLD1, 0x32 },
{ DA7213_CP_DELAY, 0x95 },
{ DA7213_CP_DETECTOR, 0x00 },
{ DA7213_DAI_OFFSET, 0x00 },
{ DA7213_DIG_CTRL, 0x00 },
{ DA7213_ALC_CTRL2, 0x00 },
{ DA7213_ALC_CTRL3, 0x00 },
{ DA7213_ALC_NOISE, 0x3F },
{ DA7213_ALC_TARGET_MIN, 0x3F },
{ DA7213_ALC_TARGET_MAX, 0x00 },
{ DA7213_ALC_GAIN_LIMITS, 0xFF },
{ DA7213_ALC_ANA_GAIN_LIMITS, 0x71 },
{ DA7213_ALC_ANTICLIP_CTRL, 0x00 },
{ DA7213_ALC_ANTICLIP_LEVEL, 0x00 },
{ DA7213_ALC_OFFSET_MAN_M_L, 0x00 },
{ DA7213_ALC_OFFSET_MAN_U_L, 0x00 },
{ DA7213_ALC_OFFSET_MAN_M_R, 0x00 },
{ DA7213_ALC_OFFSET_MAN_U_R, 0x00 },
{ DA7213_ALC_CIC_OP_LVL_CTRL, 0x00 },
{ DA7213_DAC_NG_SETUP_TIME, 0x00 },
{ DA7213_DAC_NG_OFF_THRESHOLD, 0x00 },
{ DA7213_DAC_NG_ON_THRESHOLD, 0x00 },
{ DA7213_DAC_NG_CTRL, 0x00 },
};
static bool da7213_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA7213_STATUS1:
case DA7213_PLL_STATUS:
case DA7213_AUX_L_GAIN_STATUS:
case DA7213_AUX_R_GAIN_STATUS:
case DA7213_MIC_1_GAIN_STATUS:
case DA7213_MIC_2_GAIN_STATUS:
case DA7213_MIXIN_L_GAIN_STATUS:
case DA7213_MIXIN_R_GAIN_STATUS:
case DA7213_ADC_L_GAIN_STATUS:
case DA7213_ADC_R_GAIN_STATUS:
case DA7213_DAC_L_GAIN_STATUS:
case DA7213_DAC_R_GAIN_STATUS:
case DA7213_HP_L_GAIN_STATUS:
case DA7213_HP_R_GAIN_STATUS:
case DA7213_LINE_GAIN_STATUS:
case DA7213_ALC_CTRL1:
case DA7213_ALC_OFFSET_AUTO_M_L:
case DA7213_ALC_OFFSET_AUTO_U_L:
case DA7213_ALC_OFFSET_AUTO_M_R:
case DA7213_ALC_OFFSET_AUTO_U_R:
case DA7213_ALC_CIC_OP_LVL_DATA:
return true;
default:
return false;
}
}
static int da7213_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
u8 dai_clk_mode = DA7213_DAI_BCLKS_PER_WCLK_64;
u8 dai_ctrl = 0;
u8 fs;
/* Set channels */
switch (params_channels(params)) {
case 1:
if (da7213->fmt != DA7213_DAI_FORMAT_DSP) {
dev_err(component->dev, "Mono supported only in DSP mode\n");
return -EINVAL;
}
dai_ctrl |= DA7213_DAI_MONO_MODE_EN;
break;
case 2:
dai_ctrl &= ~(DA7213_DAI_MONO_MODE_EN);
break;
default:
return -EINVAL;
}
/* Set DAI format */
switch (params_width(params)) {
case 16:
dai_ctrl |= DA7213_DAI_WORD_LENGTH_S16_LE;
dai_clk_mode = DA7213_DAI_BCLKS_PER_WCLK_32; /* 32bit for 1ch and 2ch */
break;
case 20:
dai_ctrl |= DA7213_DAI_WORD_LENGTH_S20_LE;
break;
case 24:
dai_ctrl |= DA7213_DAI_WORD_LENGTH_S24_LE;
break;
case 32:
dai_ctrl |= DA7213_DAI_WORD_LENGTH_S32_LE;
break;
default:
return -EINVAL;
}
/* Set sampling rate */
switch (params_rate(params)) {
case 8000:
fs = DA7213_SR_8000;
da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
break;
case 11025:
fs = DA7213_SR_11025;
da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
break;
case 12000:
fs = DA7213_SR_12000;
da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
break;
case 16000:
fs = DA7213_SR_16000;
da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
break;
case 22050:
fs = DA7213_SR_22050;
da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
break;
case 32000:
fs = DA7213_SR_32000;
da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
break;
case 44100:
fs = DA7213_SR_44100;
da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
break;
case 48000:
fs = DA7213_SR_48000;
da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
break;
case 88200:
fs = DA7213_SR_88200;
da7213->out_rate = DA7213_PLL_FREQ_OUT_90316800;
break;
case 96000:
fs = DA7213_SR_96000;
da7213->out_rate = DA7213_PLL_FREQ_OUT_98304000;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
DA7213_DAI_BCLKS_PER_WCLK_MASK, dai_clk_mode);
snd_soc_component_update_bits(component, DA7213_DAI_CTRL,
DA7213_DAI_WORD_LENGTH_MASK | DA7213_DAI_MONO_MODE_MASK, dai_ctrl);
snd_soc_component_write(component, DA7213_SR, fs);
return 0;
}
static int da7213_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
u8 dai_clk_mode = 0, dai_ctrl = 0;
u8 dai_offset = 0;
/* Set master/slave mode */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
da7213->master = true;
break;
case SND_SOC_DAIFMT_CBS_CFS:
da7213->master = false;
break;
default:
return -EINVAL;
}
/* Set clock normal/inverted */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
dai_clk_mode |= DA7213_DAI_WCLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
dai_clk_mode |= DA7213_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
dai_clk_mode |= DA7213_DAI_WCLK_POL_INV |
DA7213_DAI_CLK_POL_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAI_FORMAT_DSP_A:
case SND_SOC_DAI_FORMAT_DSP_B:
/* The bclk is inverted wrt ASoC conventions */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
dai_clk_mode |= DA7213_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
dai_clk_mode |= DA7213_DAI_WCLK_POL_INV |
DA7213_DAI_CLK_POL_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
dai_clk_mode |= DA7213_DAI_WCLK_POL_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
/* Only I2S is supported */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dai_ctrl |= DA7213_DAI_FORMAT_I2S_MODE;
da7213->fmt = DA7213_DAI_FORMAT_I2S_MODE;
break;
case SND_SOC_DAIFMT_LEFT_J:
dai_ctrl |= DA7213_DAI_FORMAT_LEFT_J;
da7213->fmt = DA7213_DAI_FORMAT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
dai_ctrl |= DA7213_DAI_FORMAT_RIGHT_J;
da7213->fmt = DA7213_DAI_FORMAT_RIGHT_J;
break;
case SND_SOC_DAI_FORMAT_DSP_A: /* L data MSB after FRM LRC */
dai_ctrl |= DA7213_DAI_FORMAT_DSP;
dai_offset = 1;
da7213->fmt = DA7213_DAI_FORMAT_DSP;
break;
case SND_SOC_DAI_FORMAT_DSP_B: /* L data MSB during FRM LRC */
dai_ctrl |= DA7213_DAI_FORMAT_DSP;
da7213->fmt = DA7213_DAI_FORMAT_DSP;
break;
default:
return -EINVAL;
}
/* By default only 64 BCLK per WCLK is supported */
dai_clk_mode |= DA7213_DAI_BCLKS_PER_WCLK_64;
snd_soc_component_update_bits(component, DA7213_DAI_CLK_MODE,
DA7213_DAI_BCLKS_PER_WCLK_MASK |
DA7213_DAI_CLK_POL_MASK | DA7213_DAI_WCLK_POL_MASK,
dai_clk_mode);
snd_soc_component_update_bits(component, DA7213_DAI_CTRL, DA7213_DAI_FORMAT_MASK,
dai_ctrl);
snd_soc_component_write(component, DA7213_DAI_OFFSET, dai_offset);
return 0;
}
static int da7213_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
if (mute) {
snd_soc_component_update_bits(component, DA7213_DAC_L_CTRL,
DA7213_MUTE_EN, DA7213_MUTE_EN);
snd_soc_component_update_bits(component, DA7213_DAC_R_CTRL,
DA7213_MUTE_EN, DA7213_MUTE_EN);
} else {
snd_soc_component_update_bits(component, DA7213_DAC_L_CTRL,
DA7213_MUTE_EN, 0);
snd_soc_component_update_bits(component, DA7213_DAC_R_CTRL,
DA7213_MUTE_EN, 0);
}
return 0;
}
#define DA7213_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static int da7213_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source,
unsigned int freq, int dir)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
int ret = 0;
if ((da7213->clk_src == clk_id) && (da7213->mclk_rate == freq))
return 0;
if (((freq < 5000000) && (freq != 32768)) || (freq > 54000000)) {
dev_err(component->dev, "Unsupported MCLK value %d\n",
freq);
return -EINVAL;
}
switch (clk_id) {
case DA7213_CLKSRC_MCLK:
snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
DA7213_PLL_MCLK_SQR_EN, 0);
break;
case DA7213_CLKSRC_MCLK_SQR:
snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
DA7213_PLL_MCLK_SQR_EN,
DA7213_PLL_MCLK_SQR_EN);
break;
default:
dev_err(component->dev, "Unknown clock source %d\n", clk_id);
return -EINVAL;
}
da7213->clk_src = clk_id;
if (da7213->mclk) {
freq = clk_round_rate(da7213->mclk, freq);
ret = clk_set_rate(da7213->mclk, freq);
if (ret) {
dev_err(component->dev, "Failed to set clock rate %d\n",
freq);
return ret;
}
}
da7213->mclk_rate = freq;
return 0;
}
/* Supported PLL input frequencies are 32KHz, 5MHz - 54MHz. */
static int _da7213_set_component_pll(struct snd_soc_component *component,
int pll_id, int source,
unsigned int fref, unsigned int fout)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
u8 pll_ctrl, indiv_bits, indiv;
u8 pll_frac_top, pll_frac_bot, pll_integer;
u32 freq_ref;
u64 frac_div;
/* Workout input divider based on MCLK rate */
if (da7213->mclk_rate == 32768) {
if (!da7213->master) {
dev_err(component->dev,
"32KHz only valid if codec is clock master\n");
return -EINVAL;
}
/* 32KHz PLL Mode */
indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
source = DA7213_SYSCLK_PLL_32KHZ;
freq_ref = 3750000;
} else {
if (da7213->mclk_rate < 5000000) {
dev_err(component->dev,
"PLL input clock %d below valid range\n",
da7213->mclk_rate);
return -EINVAL;
} else if (da7213->mclk_rate <= 9000000) {
indiv_bits = DA7213_PLL_INDIV_5_TO_9_MHZ;
indiv = DA7213_PLL_INDIV_5_TO_9_MHZ_VAL;
} else if (da7213->mclk_rate <= 18000000) {
indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
} else if (da7213->mclk_rate <= 36000000) {
indiv_bits = DA7213_PLL_INDIV_18_TO_36_MHZ;
indiv = DA7213_PLL_INDIV_18_TO_36_MHZ_VAL;
} else if (da7213->mclk_rate <= 54000000) {
indiv_bits = DA7213_PLL_INDIV_36_TO_54_MHZ;
indiv = DA7213_PLL_INDIV_36_TO_54_MHZ_VAL;
} else {
dev_err(component->dev,
"PLL input clock %d above valid range\n",
da7213->mclk_rate);
return -EINVAL;
}
freq_ref = (da7213->mclk_rate / indiv);
}
pll_ctrl = indiv_bits;
/* Configure PLL */
switch (source) {
case DA7213_SYSCLK_MCLK:
snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
DA7213_PLL_INDIV_MASK |
DA7213_PLL_MODE_MASK, pll_ctrl);
return 0;
case DA7213_SYSCLK_PLL:
break;
case DA7213_SYSCLK_PLL_SRM:
pll_ctrl |= DA7213_PLL_SRM_EN;
fout = DA7213_PLL_FREQ_OUT_94310400;
break;
case DA7213_SYSCLK_PLL_32KHZ:
if (da7213->mclk_rate != 32768) {
dev_err(component->dev,
"32KHz mode only valid with 32KHz MCLK\n");
return -EINVAL;
}
pll_ctrl |= DA7213_PLL_32K_MODE | DA7213_PLL_SRM_EN;
fout = DA7213_PLL_FREQ_OUT_94310400;
break;
default:
dev_err(component->dev, "Invalid PLL config\n");
return -EINVAL;
}
/* Calculate dividers for PLL */
pll_integer = fout / freq_ref;
frac_div = (u64)(fout % freq_ref) * 8192ULL;
do_div(frac_div, freq_ref);
pll_frac_top = (frac_div >> DA7213_BYTE_SHIFT) & DA7213_BYTE_MASK;
pll_frac_bot = (frac_div) & DA7213_BYTE_MASK;
/* Write PLL dividers */
snd_soc_component_write(component, DA7213_PLL_FRAC_TOP, pll_frac_top);
snd_soc_component_write(component, DA7213_PLL_FRAC_BOT, pll_frac_bot);
snd_soc_component_write(component, DA7213_PLL_INTEGER, pll_integer);
/* Enable PLL */
pll_ctrl |= DA7213_PLL_EN;
snd_soc_component_update_bits(component, DA7213_PLL_CTRL,
DA7213_PLL_INDIV_MASK | DA7213_PLL_MODE_MASK,
pll_ctrl);
/* Assist 32KHz mode PLL lock */
if (source == DA7213_SYSCLK_PLL_32KHZ) {
snd_soc_component_write(component, 0xF0, 0x8B);
snd_soc_component_write(component, 0xF1, 0x03);
snd_soc_component_write(component, 0xF1, 0x01);
snd_soc_component_write(component, 0xF0, 0x00);
}
return 0;
}
static int da7213_set_component_pll(struct snd_soc_component *component,
int pll_id, int source,
unsigned int fref, unsigned int fout)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
da7213->fixed_clk_auto_pll = false;
return _da7213_set_component_pll(component, pll_id, source, fref, fout);
}
/* DAI operations */
static const struct snd_soc_dai_ops da7213_dai_ops = {
.hw_params = da7213_hw_params,
.set_fmt = da7213_set_dai_fmt,
.mute_stream = da7213_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver da7213_dai = {
.name = "da7213-hifi",
/* Playback Capabilities */
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA7213_FORMATS,
},
/* Capture Capabilities */
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = DA7213_FORMATS,
},
.ops = &da7213_dai_ops,
.symmetric_rate = 1,
};
static int da7213_set_auto_pll(struct snd_soc_component *component, bool enable)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
int mode;
if (!da7213->fixed_clk_auto_pll)
return 0;
da7213->mclk_rate = clk_get_rate(da7213->mclk);
if (enable) {
/* Slave mode needs SRM for non-harmonic frequencies */
if (da7213->master)
mode = DA7213_SYSCLK_PLL;
else
mode = DA7213_SYSCLK_PLL_SRM;
/* PLL is not required for harmonic frequencies */
switch (da7213->out_rate) {
case DA7213_PLL_FREQ_OUT_90316800:
if (da7213->mclk_rate == 11289600 ||
da7213->mclk_rate == 22579200 ||
da7213->mclk_rate == 45158400)
mode = DA7213_SYSCLK_MCLK;
break;
case DA7213_PLL_FREQ_OUT_98304000:
if (da7213->mclk_rate == 12288000 ||
da7213->mclk_rate == 24576000 ||
da7213->mclk_rate == 49152000)
mode = DA7213_SYSCLK_MCLK;
break;
default:
return -1;
}
} else {
/* Disable PLL in standby */
mode = DA7213_SYSCLK_MCLK;
}
return _da7213_set_component_pll(component, 0, mode,
da7213->mclk_rate, da7213->out_rate);
}
static int da7213_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Enable MCLK for transition to ON state */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
if (da7213->mclk) {
ret = clk_prepare_enable(da7213->mclk);
if (ret) {
dev_err(component->dev,
"Failed to enable mclk\n");
return ret;
}
da7213_set_auto_pll(component, true);
}
}
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Enable VMID reference & master bias */
snd_soc_component_update_bits(component, DA7213_REFERENCES,
DA7213_VMID_EN | DA7213_BIAS_EN,
DA7213_VMID_EN | DA7213_BIAS_EN);
} else {
/* Remove MCLK */
if (da7213->mclk) {
da7213_set_auto_pll(component, false);
clk_disable_unprepare(da7213->mclk);
}
}
break;
case SND_SOC_BIAS_OFF:
/* Disable VMID reference & master bias */
snd_soc_component_update_bits(component, DA7213_REFERENCES,
DA7213_VMID_EN | DA7213_BIAS_EN, 0);
break;
}
return 0;
}
#if defined(CONFIG_OF)
/* DT */
static const struct of_device_id da7213_of_match[] = {
{ .compatible = "dlg,da7212", },
{ .compatible = "dlg,da7213", },
{ }
};
MODULE_DEVICE_TABLE(of, da7213_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id da7213_acpi_match[] = {
{ "DLGS7212", 0},
{ "DLGS7213", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, da7213_acpi_match);
#endif
static enum da7213_micbias_voltage
da7213_of_micbias_lvl(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 1600:
return DA7213_MICBIAS_1_6V;
case 2200:
return DA7213_MICBIAS_2_2V;
case 2500:
return DA7213_MICBIAS_2_5V;
case 3000:
return DA7213_MICBIAS_3_0V;
default:
dev_warn(component->dev, "Invalid micbias level\n");
return DA7213_MICBIAS_2_2V;
}
}
static enum da7213_dmic_data_sel
da7213_of_dmic_data_sel(struct snd_soc_component *component, const char *str)
{
if (!strcmp(str, "lrise_rfall")) {
return DA7213_DMIC_DATA_LRISE_RFALL;
} else if (!strcmp(str, "lfall_rrise")) {
return DA7213_DMIC_DATA_LFALL_RRISE;
} else {
dev_warn(component->dev, "Invalid DMIC data select type\n");
return DA7213_DMIC_DATA_LRISE_RFALL;
}
}
static enum da7213_dmic_samplephase
da7213_of_dmic_samplephase(struct snd_soc_component *component, const char *str)
{
if (!strcmp(str, "on_clkedge")) {
return DA7213_DMIC_SAMPLE_ON_CLKEDGE;
} else if (!strcmp(str, "between_clkedge")) {
return DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE;
} else {
dev_warn(component->dev, "Invalid DMIC sample phase\n");
return DA7213_DMIC_SAMPLE_ON_CLKEDGE;
}
}
static enum da7213_dmic_clk_rate
da7213_of_dmic_clkrate(struct snd_soc_component *component, u32 val)
{
switch (val) {
case 1500000:
return DA7213_DMIC_CLK_1_5MHZ;
case 3000000:
return DA7213_DMIC_CLK_3_0MHZ;
default:
dev_warn(component->dev, "Invalid DMIC clock rate\n");
return DA7213_DMIC_CLK_1_5MHZ;
}
}
static struct da7213_platform_data
*da7213_fw_to_pdata(struct snd_soc_component *component)
{
struct device *dev = component->dev;
struct da7213_platform_data *pdata;
const char *fw_str;
u32 fw_val32;
pdata = devm_kzalloc(component->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return NULL;
if (device_property_read_u32(dev, "dlg,micbias1-lvl", &fw_val32) >= 0)
pdata->micbias1_lvl = da7213_of_micbias_lvl(component, fw_val32);
else
pdata->micbias1_lvl = DA7213_MICBIAS_2_2V;
if (device_property_read_u32(dev, "dlg,micbias2-lvl", &fw_val32) >= 0)
pdata->micbias2_lvl = da7213_of_micbias_lvl(component, fw_val32);
else
pdata->micbias2_lvl = DA7213_MICBIAS_2_2V;
if (!device_property_read_string(dev, "dlg,dmic-data-sel", &fw_str))
pdata->dmic_data_sel = da7213_of_dmic_data_sel(component, fw_str);
else
pdata->dmic_data_sel = DA7213_DMIC_DATA_LRISE_RFALL;
if (!device_property_read_string(dev, "dlg,dmic-samplephase", &fw_str))
pdata->dmic_samplephase =
da7213_of_dmic_samplephase(component, fw_str);
else
pdata->dmic_samplephase = DA7213_DMIC_SAMPLE_ON_CLKEDGE;
if (device_property_read_u32(dev, "dlg,dmic-clkrate", &fw_val32) >= 0)
pdata->dmic_clk_rate = da7213_of_dmic_clkrate(component, fw_val32);
else
pdata->dmic_clk_rate = DA7213_DMIC_CLK_3_0MHZ;
return pdata;
}
static int da7213_probe(struct snd_soc_component *component)
{
struct da7213_priv *da7213 = snd_soc_component_get_drvdata(component);
pm_runtime_get_sync(component->dev);
/* Default to using ALC auto offset calibration mode. */
snd_soc_component_update_bits(component, DA7213_ALC_CTRL1,
DA7213_ALC_CALIB_MODE_MAN, 0);
da7213->alc_calib_auto = true;
/* Default PC counter to free-running */
snd_soc_component_update_bits(component, DA7213_PC_COUNT, DA7213_PC_FREERUN_MASK,
DA7213_PC_FREERUN_MASK);
/* Enable all Gain Ramps */
snd_soc_component_update_bits(component, DA7213_AUX_L_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_AUX_R_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_MIXIN_L_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_MIXIN_R_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_ADC_L_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_ADC_R_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_DAC_L_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_DAC_R_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_HP_L_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_HP_R_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
snd_soc_component_update_bits(component, DA7213_LINE_CTRL,
DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN);
/*
* There are two separate control bits for input and output mixers as
* well as headphone and line outs.
* One to enable corresponding amplifier and other to enable its
* output. As amplifier bits are related to power control, they are
* being managed by DAPM while other (non power related) bits are
* enabled here
*/
snd_soc_component_update_bits(component, DA7213_MIXIN_L_CTRL,
DA7213_MIXIN_MIX_EN, DA7213_MIXIN_MIX_EN);
snd_soc_component_update_bits(component, DA7213_MIXIN_R_CTRL,
DA7213_MIXIN_MIX_EN, DA7213_MIXIN_MIX_EN);
snd_soc_component_update_bits(component, DA7213_MIXOUT_L_CTRL,
DA7213_MIXOUT_MIX_EN, DA7213_MIXOUT_MIX_EN);
snd_soc_component_update_bits(component, DA7213_MIXOUT_R_CTRL,
DA7213_MIXOUT_MIX_EN, DA7213_MIXOUT_MIX_EN);
snd_soc_component_update_bits(component, DA7213_HP_L_CTRL,
DA7213_HP_AMP_OE, DA7213_HP_AMP_OE);
snd_soc_component_update_bits(component, DA7213_HP_R_CTRL,
DA7213_HP_AMP_OE, DA7213_HP_AMP_OE);
snd_soc_component_update_bits(component, DA7213_LINE_CTRL,
DA7213_LINE_AMP_OE, DA7213_LINE_AMP_OE);
/* Handle DT/Platform data */
da7213->pdata = dev_get_platdata(component->dev);
if (!da7213->pdata)
da7213->pdata = da7213_fw_to_pdata(component);
/* Set platform data values */
if (da7213->pdata) {
struct da7213_platform_data *pdata = da7213->pdata;
u8 micbias_lvl = 0, dmic_cfg = 0;
/* Set Mic Bias voltages */
switch (pdata->micbias1_lvl) {
case DA7213_MICBIAS_1_6V:
case DA7213_MICBIAS_2_2V:
case DA7213_MICBIAS_2_5V:
case DA7213_MICBIAS_3_0V:
micbias_lvl |= (pdata->micbias1_lvl <<
DA7213_MICBIAS1_LEVEL_SHIFT);
break;
}
switch (pdata->micbias2_lvl) {
case DA7213_MICBIAS_1_6V:
case DA7213_MICBIAS_2_2V:
case DA7213_MICBIAS_2_5V:
case DA7213_MICBIAS_3_0V:
micbias_lvl |= (pdata->micbias2_lvl <<
DA7213_MICBIAS2_LEVEL_SHIFT);
break;
}
snd_soc_component_update_bits(component, DA7213_MICBIAS_CTRL,
DA7213_MICBIAS1_LEVEL_MASK |
DA7213_MICBIAS2_LEVEL_MASK, micbias_lvl);
/* Set DMIC configuration */
switch (pdata->dmic_data_sel) {
case DA7213_DMIC_DATA_LFALL_RRISE:
case DA7213_DMIC_DATA_LRISE_RFALL:
dmic_cfg |= (pdata->dmic_data_sel <<
DA7213_DMIC_DATA_SEL_SHIFT);
break;
}
switch (pdata->dmic_samplephase) {
case DA7213_DMIC_SAMPLE_ON_CLKEDGE:
case DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE:
dmic_cfg |= (pdata->dmic_samplephase <<
DA7213_DMIC_SAMPLEPHASE_SHIFT);
break;
}
switch (pdata->dmic_clk_rate) {
case DA7213_DMIC_CLK_3_0MHZ:
case DA7213_DMIC_CLK_1_5MHZ:
dmic_cfg |= (pdata->dmic_clk_rate <<
DA7213_DMIC_CLK_RATE_SHIFT);
break;
}
snd_soc_component_update_bits(component, DA7213_MIC_CONFIG,
DA7213_DMIC_DATA_SEL_MASK |
DA7213_DMIC_SAMPLEPHASE_MASK |
DA7213_DMIC_CLK_RATE_MASK, dmic_cfg);
}
pm_runtime_put_sync(component->dev);
/* Check if MCLK provided */
da7213->mclk = devm_clk_get(component->dev, "mclk");
if (IS_ERR(da7213->mclk)) {
if (PTR_ERR(da7213->mclk) != -ENOENT)
return PTR_ERR(da7213->mclk);
else
da7213->mclk = NULL;
} else {
/* Do automatic PLL handling assuming fixed clock until
* set_pll() has been called. This makes the codec usable
* with the simple-audio-card driver. */
da7213->fixed_clk_auto_pll = true;
}
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_da7213 = {
.probe = da7213_probe,
.set_bias_level = da7213_set_bias_level,
.controls = da7213_snd_controls,
.num_controls = ARRAY_SIZE(da7213_snd_controls),
.dapm_widgets = da7213_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(da7213_dapm_widgets),
.dapm_routes = da7213_audio_map,
.num_dapm_routes = ARRAY_SIZE(da7213_audio_map),
.set_sysclk = da7213_set_component_sysclk,
.set_pll = da7213_set_component_pll,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config da7213_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = da7213_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(da7213_reg_defaults),
.volatile_reg = da7213_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
static void da7213_power_off(void *data)
{
struct da7213_priv *da7213 = data;
regulator_bulk_disable(DA7213_NUM_SUPPLIES, da7213->supplies);
}
static const char *da7213_supply_names[DA7213_NUM_SUPPLIES] = {
[DA7213_SUPPLY_VDDA] = "VDDA",
[DA7213_SUPPLY_VDDIO] = "VDDIO",
};
static int da7213_i2c_probe(struct i2c_client *i2c)
{
struct da7213_priv *da7213;
int i, ret;
da7213 = devm_kzalloc(&i2c->dev, sizeof(*da7213), GFP_KERNEL);
if (!da7213)
return -ENOMEM;
i2c_set_clientdata(i2c, da7213);
/* Get required supplies */
for (i = 0; i < DA7213_NUM_SUPPLIES; ++i)
da7213->supplies[i].supply = da7213_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, DA7213_NUM_SUPPLIES,
da7213->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(DA7213_NUM_SUPPLIES, da7213->supplies);
if (ret < 0)
return ret;
ret = devm_add_action_or_reset(&i2c->dev, da7213_power_off, da7213);
if (ret < 0)
return ret;
da7213->regmap = devm_regmap_init_i2c(i2c, &da7213_regmap_config);
if (IS_ERR(da7213->regmap)) {
ret = PTR_ERR(da7213->regmap);
dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
pm_runtime_set_autosuspend_delay(&i2c->dev, 100);
pm_runtime_use_autosuspend(&i2c->dev);
pm_runtime_set_active(&i2c->dev);
pm_runtime_enable(&i2c->dev);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_da7213, &da7213_dai, 1);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to register da7213 component: %d\n",
ret);
}
return ret;
}
static void da7213_i2c_remove(struct i2c_client *i2c)
{
pm_runtime_disable(&i2c->dev);
}
static int __maybe_unused da7213_runtime_suspend(struct device *dev)
{
struct da7213_priv *da7213 = dev_get_drvdata(dev);
regcache_cache_only(da7213->regmap, true);
regcache_mark_dirty(da7213->regmap);
regulator_bulk_disable(DA7213_NUM_SUPPLIES, da7213->supplies);
return 0;
}
static int __maybe_unused da7213_runtime_resume(struct device *dev)
{
struct da7213_priv *da7213 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(DA7213_NUM_SUPPLIES, da7213->supplies);
if (ret < 0)
return ret;
regcache_cache_only(da7213->regmap, false);
regcache_sync(da7213->regmap);
return 0;
}
static const struct dev_pm_ops da7213_pm = {
SET_RUNTIME_PM_OPS(da7213_runtime_suspend, da7213_runtime_resume, NULL)
};
static const struct i2c_device_id da7213_i2c_id[] = {
{ "da7213", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, da7213_i2c_id);
/* I2C codec control layer */
static struct i2c_driver da7213_i2c_driver = {
.driver = {
.name = "da7213",
.of_match_table = of_match_ptr(da7213_of_match),
.acpi_match_table = ACPI_PTR(da7213_acpi_match),
.pm = &da7213_pm,
},
.probe = da7213_i2c_probe,
.remove = da7213_i2c_remove,
.id_table = da7213_i2c_id,
};
module_i2c_driver(da7213_i2c_driver);
MODULE_DESCRIPTION("ASoC DA7213 Codec driver");
MODULE_AUTHOR("Adam Thomson <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/da7213.c |
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Cirrus Logic CS4341A ALSA SoC Codec Driver
* Author: Alexander Shiyan <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define CS4341_REG_MODE1 0x00
#define CS4341_REG_MODE2 0x01
#define CS4341_REG_MIX 0x02
#define CS4341_REG_VOLA 0x03
#define CS4341_REG_VOLB 0x04
#define CS4341_MODE2_DIF (7 << 4)
#define CS4341_MODE2_DIF_I2S_24 (0 << 4)
#define CS4341_MODE2_DIF_I2S_16 (1 << 4)
#define CS4341_MODE2_DIF_LJ_24 (2 << 4)
#define CS4341_MODE2_DIF_RJ_24 (3 << 4)
#define CS4341_MODE2_DIF_RJ_16 (5 << 4)
#define CS4341_VOLX_MUTE (1 << 7)
struct cs4341_priv {
unsigned int fmt;
struct regmap *regmap;
struct regmap_config regcfg;
};
static const struct reg_default cs4341_reg_defaults[] = {
{ CS4341_REG_MODE1, 0x00 },
{ CS4341_REG_MODE2, 0x82 },
{ CS4341_REG_MIX, 0x49 },
{ CS4341_REG_VOLA, 0x80 },
{ CS4341_REG_VOLB, 0x80 },
};
static int cs4341_set_fmt(struct snd_soc_dai *dai, unsigned int format)
{
struct snd_soc_component *component = dai->component;
struct cs4341_priv *cs4341 = snd_soc_component_get_drvdata(component);
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
cs4341->fmt = format & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
return -EINVAL;
}
return 0;
}
static int cs4341_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs4341_priv *cs4341 = snd_soc_component_get_drvdata(component);
unsigned int mode = 0;
int b24 = 0;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S24_LE:
b24 = 1;
break;
case SNDRV_PCM_FORMAT_S16_LE:
break;
default:
dev_err(component->dev, "Unsupported PCM format 0x%08x.\n",
params_format(params));
return -EINVAL;
}
switch (cs4341->fmt) {
case SND_SOC_DAIFMT_I2S:
mode = b24 ? CS4341_MODE2_DIF_I2S_24 : CS4341_MODE2_DIF_I2S_16;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode = CS4341_MODE2_DIF_LJ_24;
break;
case SND_SOC_DAIFMT_RIGHT_J:
mode = b24 ? CS4341_MODE2_DIF_RJ_24 : CS4341_MODE2_DIF_RJ_16;
break;
default:
dev_err(component->dev, "Unsupported DAI format 0x%08x.\n",
cs4341->fmt);
return -EINVAL;
}
return snd_soc_component_update_bits(component, CS4341_REG_MODE2,
CS4341_MODE2_DIF, mode);
}
static int cs4341_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
int ret;
ret = snd_soc_component_update_bits(component, CS4341_REG_VOLA,
CS4341_VOLX_MUTE,
mute ? CS4341_VOLX_MUTE : 0);
if (ret < 0)
return ret;
return snd_soc_component_update_bits(component, CS4341_REG_VOLB,
CS4341_VOLX_MUTE,
mute ? CS4341_VOLX_MUTE : 0);
}
static DECLARE_TLV_DB_SCALE(out_tlv, -9000, 100, 0);
static const char * const deemph[] = {
"None", "44.1k", "48k", "32k",
};
static const struct soc_enum deemph_enum =
SOC_ENUM_SINGLE(CS4341_REG_MODE2, 2, 4, deemph);
static const char * const srzc[] = {
"Immediate", "Zero Cross", "Soft Ramp", "SR on ZC",
};
static const struct soc_enum srzc_enum =
SOC_ENUM_SINGLE(CS4341_REG_MIX, 5, 4, srzc);
static const struct snd_soc_dapm_widget cs4341_dapm_widgets[] = {
SND_SOC_DAPM_DAC("HiFi DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OutA"),
SND_SOC_DAPM_OUTPUT("OutB"),
};
static const struct snd_soc_dapm_route cs4341_routes[] = {
{ "OutA", NULL, "HiFi DAC" },
{ "OutB", NULL, "HiFi DAC" },
{ "DAC Playback", NULL, "OutA" },
{ "DAC Playback", NULL, "OutB" },
};
static const struct snd_kcontrol_new cs4341_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume",
CS4341_REG_VOLA, CS4341_REG_VOLB, 0, 90, 1, out_tlv),
SOC_ENUM("De-Emphasis Control", deemph_enum),
SOC_ENUM("Soft Ramp Zero Cross Control", srzc_enum),
SOC_SINGLE("Auto-Mute Switch", CS4341_REG_MODE2, 7, 1, 0),
SOC_SINGLE("Popguard Transient Switch", CS4341_REG_MODE2, 1, 1, 0),
};
static const struct snd_soc_dai_ops cs4341_dai_ops = {
.set_fmt = cs4341_set_fmt,
.hw_params = cs4341_hw_params,
.mute_stream = cs4341_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs4341_dai = {
.name = "cs4341a-hifi",
.playback = {
.stream_name = "DAC Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &cs4341_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver soc_component_cs4341 = {
.controls = cs4341_controls,
.num_controls = ARRAY_SIZE(cs4341_controls),
.dapm_widgets = cs4341_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs4341_dapm_widgets),
.dapm_routes = cs4341_routes,
.num_dapm_routes = ARRAY_SIZE(cs4341_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id __maybe_unused cs4341_dt_ids[] = {
{ .compatible = "cirrus,cs4341a", },
{ }
};
MODULE_DEVICE_TABLE(of, cs4341_dt_ids);
static int cs4341_probe(struct device *dev)
{
struct cs4341_priv *cs4341 = dev_get_drvdata(dev);
int i;
for (i = 0; i < ARRAY_SIZE(cs4341_reg_defaults); i++)
regmap_write(cs4341->regmap, cs4341_reg_defaults[i].reg,
cs4341_reg_defaults[i].def);
return devm_snd_soc_register_component(dev, &soc_component_cs4341,
&cs4341_dai, 1);
}
#if IS_ENABLED(CONFIG_I2C)
static int cs4341_i2c_probe(struct i2c_client *i2c)
{
struct cs4341_priv *cs4341;
cs4341 = devm_kzalloc(&i2c->dev, sizeof(*cs4341), GFP_KERNEL);
if (!cs4341)
return -ENOMEM;
i2c_set_clientdata(i2c, cs4341);
cs4341->regcfg.reg_bits = 8;
cs4341->regcfg.val_bits = 8;
cs4341->regcfg.max_register = CS4341_REG_VOLB;
cs4341->regcfg.cache_type = REGCACHE_FLAT;
cs4341->regcfg.reg_defaults = cs4341_reg_defaults;
cs4341->regcfg.num_reg_defaults = ARRAY_SIZE(cs4341_reg_defaults);
cs4341->regmap = devm_regmap_init_i2c(i2c, &cs4341->regcfg);
if (IS_ERR(cs4341->regmap))
return PTR_ERR(cs4341->regmap);
return cs4341_probe(&i2c->dev);
}
static const struct i2c_device_id cs4341_i2c_id[] = {
{ "cs4341", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cs4341_i2c_id);
static struct i2c_driver cs4341_i2c_driver = {
.driver = {
.name = "cs4341-i2c",
.of_match_table = of_match_ptr(cs4341_dt_ids),
},
.probe = cs4341_i2c_probe,
.id_table = cs4341_i2c_id,
};
#endif
#if defined(CONFIG_SPI_MASTER)
static bool cs4341_reg_readable(struct device *dev, unsigned int reg)
{
return false;
}
static int cs4341_spi_probe(struct spi_device *spi)
{
struct cs4341_priv *cs4341;
int ret;
cs4341 = devm_kzalloc(&spi->dev, sizeof(*cs4341), GFP_KERNEL);
if (!cs4341)
return -ENOMEM;
if (!spi->bits_per_word)
spi->bits_per_word = 8;
if (!spi->max_speed_hz)
spi->max_speed_hz = 6000000;
ret = spi_setup(spi);
if (ret)
return ret;
spi_set_drvdata(spi, cs4341);
cs4341->regcfg.reg_bits = 16;
cs4341->regcfg.val_bits = 8;
cs4341->regcfg.write_flag_mask = 0x20;
cs4341->regcfg.max_register = CS4341_REG_VOLB;
cs4341->regcfg.cache_type = REGCACHE_FLAT;
cs4341->regcfg.readable_reg = cs4341_reg_readable;
cs4341->regcfg.reg_defaults = cs4341_reg_defaults;
cs4341->regcfg.num_reg_defaults = ARRAY_SIZE(cs4341_reg_defaults);
cs4341->regmap = devm_regmap_init_spi(spi, &cs4341->regcfg);
if (IS_ERR(cs4341->regmap))
return PTR_ERR(cs4341->regmap);
return cs4341_probe(&spi->dev);
}
static const struct spi_device_id cs4341_spi_ids[] = {
{ "cs4341a" },
{ }
};
MODULE_DEVICE_TABLE(spi, cs4341_spi_ids);
static struct spi_driver cs4341_spi_driver = {
.driver = {
.name = "cs4341-spi",
.of_match_table = of_match_ptr(cs4341_dt_ids),
},
.probe = cs4341_spi_probe,
.id_table = cs4341_spi_ids,
};
#endif
static int __init cs4341_init(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&cs4341_i2c_driver);
if (ret)
return ret;
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&cs4341_spi_driver);
#endif
return ret;
}
module_init(cs4341_init);
static void __exit cs4341_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&cs4341_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&cs4341_spi_driver);
#endif
}
module_exit(cs4341_exit);
MODULE_AUTHOR("Alexander Shiyan <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CS4341 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4341.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <linux/printk.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "wcd-mbhc-v2.h"
#define HS_DETECT_PLUG_TIME_MS (3 * 1000)
#define MBHC_BUTTON_PRESS_THRESHOLD_MIN 250
#define GND_MIC_SWAP_THRESHOLD 4
#define WCD_FAKE_REMOVAL_MIN_PERIOD_MS 100
#define HPHL_CROSS_CONN_THRESHOLD 100
#define HS_VREF_MIN_VAL 1400
#define FAKE_REM_RETRY_ATTEMPTS 3
#define WCD_MBHC_ADC_HS_THRESHOLD_MV 1700
#define WCD_MBHC_ADC_HPH_THRESHOLD_MV 75
#define WCD_MBHC_ADC_MICBIAS_MV 1800
#define WCD_MBHC_FAKE_INS_RETRY 4
#define WCD_MBHC_JACK_MASK (SND_JACK_HEADSET | SND_JACK_LINEOUT | \
SND_JACK_MECHANICAL)
#define WCD_MBHC_JACK_BUTTON_MASK (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3 | \
SND_JACK_BTN_4 | SND_JACK_BTN_5)
enum wcd_mbhc_adc_mux_ctl {
MUX_CTL_AUTO = 0,
MUX_CTL_IN2P,
MUX_CTL_IN3P,
MUX_CTL_IN4P,
MUX_CTL_HPH_L,
MUX_CTL_HPH_R,
MUX_CTL_NONE,
};
struct wcd_mbhc {
struct device *dev;
struct snd_soc_component *component;
struct snd_soc_jack *jack;
struct wcd_mbhc_config *cfg;
const struct wcd_mbhc_cb *mbhc_cb;
const struct wcd_mbhc_intr *intr_ids;
struct wcd_mbhc_field *fields;
/* Delayed work to report long button press */
struct delayed_work mbhc_btn_dwork;
/* Work to correct accessory type */
struct work_struct correct_plug_swch;
struct mutex lock;
int buttons_pressed;
u32 hph_status; /* track headhpone status */
u8 current_plug;
bool is_btn_press;
bool in_swch_irq_handler;
bool hs_detect_work_stop;
bool is_hs_recording;
bool extn_cable_hph_rem;
bool force_linein;
bool impedance_detect;
unsigned long event_state;
unsigned long jiffies_atreport;
/* impedance of hphl and hphr */
uint32_t zl, zr;
/* Holds type of Headset - Mono/Stereo */
enum wcd_mbhc_hph_type hph_type;
/* Holds mbhc detection method - ADC/Legacy */
int mbhc_detection_logic;
};
static inline int wcd_mbhc_write_field(const struct wcd_mbhc *mbhc,
int field, int val)
{
if (!mbhc->fields[field].reg)
return 0;
return snd_soc_component_write_field(mbhc->component,
mbhc->fields[field].reg,
mbhc->fields[field].mask, val);
}
static inline int wcd_mbhc_read_field(const struct wcd_mbhc *mbhc, int field)
{
if (!mbhc->fields[field].reg)
return 0;
return snd_soc_component_read_field(mbhc->component,
mbhc->fields[field].reg,
mbhc->fields[field].mask);
}
static void wcd_program_hs_vref(struct wcd_mbhc *mbhc)
{
u32 reg_val = ((mbhc->cfg->v_hs_max - HS_VREF_MIN_VAL) / 100);
wcd_mbhc_write_field(mbhc, WCD_MBHC_HS_VREF, reg_val);
}
static void wcd_program_btn_threshold(const struct wcd_mbhc *mbhc, bool micbias)
{
struct snd_soc_component *component = mbhc->component;
mbhc->mbhc_cb->set_btn_thr(component, mbhc->cfg->btn_low,
mbhc->cfg->btn_high,
mbhc->cfg->num_btn, micbias);
}
static void wcd_mbhc_curr_micbias_control(const struct wcd_mbhc *mbhc,
const enum wcd_mbhc_cs_mb_en_flag cs_mb_en)
{
/*
* Some codecs handle micbias/pullup enablement in codec
* drivers itself and micbias is not needed for regular
* plug type detection. So if micbias_control callback function
* is defined, just return.
*/
if (mbhc->mbhc_cb->mbhc_micbias_control)
return;
switch (cs_mb_en) {
case WCD_MBHC_EN_CS:
wcd_mbhc_write_field(mbhc, WCD_MBHC_MICB_CTRL, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 3);
/* Program Button threshold registers as per CS */
wcd_program_btn_threshold(mbhc, false);
break;
case WCD_MBHC_EN_MB:
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
/* Disable PULL_UP_EN & enable MICBIAS */
wcd_mbhc_write_field(mbhc, WCD_MBHC_MICB_CTRL, 2);
/* Program Button threshold registers as per MICBIAS */
wcd_program_btn_threshold(mbhc, true);
break;
case WCD_MBHC_EN_PULLUP:
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 3);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
wcd_mbhc_write_field(mbhc, WCD_MBHC_MICB_CTRL, 1);
/* Program Button threshold registers as per MICBIAS */
wcd_program_btn_threshold(mbhc, true);
break;
case WCD_MBHC_EN_NONE:
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
wcd_mbhc_write_field(mbhc, WCD_MBHC_MICB_CTRL, 0);
break;
default:
dev_err(mbhc->dev, "%s: Invalid parameter", __func__);
break;
}
}
int wcd_mbhc_event_notify(struct wcd_mbhc *mbhc, unsigned long event)
{
struct snd_soc_component *component;
bool micbias2 = false;
if (!mbhc)
return 0;
component = mbhc->component;
if (mbhc->mbhc_cb->micbias_enable_status)
micbias2 = mbhc->mbhc_cb->micbias_enable_status(component, MIC_BIAS_2);
switch (event) {
/* MICBIAS usage change */
case WCD_EVENT_POST_DAPM_MICBIAS_2_ON:
mbhc->is_hs_recording = true;
break;
case WCD_EVENT_POST_MICBIAS_2_ON:
/* Disable current source if micbias2 enabled */
if (mbhc->mbhc_cb->mbhc_micbias_control) {
if (wcd_mbhc_read_field(mbhc, WCD_MBHC_FSM_EN))
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 0);
} else {
mbhc->is_hs_recording = true;
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_MB);
}
break;
case WCD_EVENT_PRE_MICBIAS_2_OFF:
/*
* Before MICBIAS_2 is turned off, if FSM is enabled,
* make sure current source is enabled so as to detect
* button press/release events
*/
if (mbhc->mbhc_cb->mbhc_micbias_control/* && !mbhc->micbias_enable*/) {
if (wcd_mbhc_read_field(mbhc, WCD_MBHC_FSM_EN))
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 3);
}
break;
/* MICBIAS usage change */
case WCD_EVENT_POST_DAPM_MICBIAS_2_OFF:
mbhc->is_hs_recording = false;
break;
case WCD_EVENT_POST_MICBIAS_2_OFF:
if (!mbhc->mbhc_cb->mbhc_micbias_control)
mbhc->is_hs_recording = false;
/* Enable PULL UP if PA's are enabled */
if ((test_bit(WCD_MBHC_EVENT_PA_HPHL, &mbhc->event_state)) ||
(test_bit(WCD_MBHC_EVENT_PA_HPHR, &mbhc->event_state)))
/* enable pullup and cs, disable mb */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_PULLUP);
else
/* enable current source and disable mb, pullup*/
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_CS);
break;
case WCD_EVENT_POST_HPHL_PA_OFF:
clear_bit(WCD_MBHC_EVENT_PA_HPHL, &mbhc->event_state);
/* check if micbias is enabled */
if (micbias2)
/* Disable cs, pullup & enable micbias */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_MB);
else
/* Disable micbias, pullup & enable cs */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_CS);
break;
case WCD_EVENT_POST_HPHR_PA_OFF:
clear_bit(WCD_MBHC_EVENT_PA_HPHR, &mbhc->event_state);
/* check if micbias is enabled */
if (micbias2)
/* Disable cs, pullup & enable micbias */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_MB);
else
/* Disable micbias, pullup & enable cs */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_CS);
break;
case WCD_EVENT_PRE_HPHL_PA_ON:
set_bit(WCD_MBHC_EVENT_PA_HPHL, &mbhc->event_state);
/* check if micbias is enabled */
if (micbias2)
/* Disable cs, pullup & enable micbias */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_MB);
else
/* Disable micbias, enable pullup & cs */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_PULLUP);
break;
case WCD_EVENT_PRE_HPHR_PA_ON:
set_bit(WCD_MBHC_EVENT_PA_HPHR, &mbhc->event_state);
/* check if micbias is enabled */
if (micbias2)
/* Disable cs, pullup & enable micbias */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_MB);
else
/* Disable micbias, enable pullup & cs */
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_PULLUP);
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(wcd_mbhc_event_notify);
static int wcd_cancel_btn_work(struct wcd_mbhc *mbhc)
{
return cancel_delayed_work_sync(&mbhc->mbhc_btn_dwork);
}
static void wcd_micbias_disable(struct wcd_mbhc *mbhc)
{
struct snd_soc_component *component = mbhc->component;
if (mbhc->mbhc_cb->mbhc_micbias_control)
mbhc->mbhc_cb->mbhc_micbias_control(component, MIC_BIAS_2, MICB_DISABLE);
if (mbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic)
mbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic(component, MIC_BIAS_2, false);
if (mbhc->mbhc_cb->set_micbias_value) {
mbhc->mbhc_cb->set_micbias_value(component);
wcd_mbhc_write_field(mbhc, WCD_MBHC_MICB_CTRL, 0);
}
}
static void wcd_mbhc_report_plug_removal(struct wcd_mbhc *mbhc,
enum snd_jack_types jack_type)
{
mbhc->hph_status &= ~jack_type;
/*
* cancel possibly scheduled btn work and
* report release if we reported button press
*/
if (!wcd_cancel_btn_work(mbhc) && mbhc->buttons_pressed) {
snd_soc_jack_report(mbhc->jack, 0, mbhc->buttons_pressed);
mbhc->buttons_pressed &= ~WCD_MBHC_JACK_BUTTON_MASK;
}
wcd_micbias_disable(mbhc);
mbhc->hph_type = WCD_MBHC_HPH_NONE;
mbhc->zl = mbhc->zr = 0;
snd_soc_jack_report(mbhc->jack, mbhc->hph_status, WCD_MBHC_JACK_MASK);
mbhc->current_plug = MBHC_PLUG_TYPE_NONE;
mbhc->force_linein = false;
}
static void wcd_mbhc_compute_impedance(struct wcd_mbhc *mbhc)
{
if (!mbhc->impedance_detect)
return;
if (mbhc->cfg->linein_th != 0) {
u8 fsm_en = wcd_mbhc_read_field(mbhc, WCD_MBHC_FSM_EN);
/* Set MUX_CTL to AUTO for Z-det */
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_MUX_CTL, MUX_CTL_AUTO);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
mbhc->mbhc_cb->compute_impedance(mbhc->component, &mbhc->zl, &mbhc->zr);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, fsm_en);
}
}
static void wcd_mbhc_report_plug_insertion(struct wcd_mbhc *mbhc,
enum snd_jack_types jack_type)
{
bool is_pa_on;
/*
* Report removal of current jack type.
* Headphone to headset shouldn't report headphone
* removal.
*/
if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADSET &&
jack_type == SND_JACK_HEADPHONE)
mbhc->hph_status &= ~SND_JACK_HEADSET;
/* Report insertion */
switch (jack_type) {
case SND_JACK_HEADPHONE:
mbhc->current_plug = MBHC_PLUG_TYPE_HEADPHONE;
break;
case SND_JACK_HEADSET:
mbhc->current_plug = MBHC_PLUG_TYPE_HEADSET;
mbhc->jiffies_atreport = jiffies;
break;
case SND_JACK_LINEOUT:
mbhc->current_plug = MBHC_PLUG_TYPE_HIGH_HPH;
break;
default:
break;
}
is_pa_on = wcd_mbhc_read_field(mbhc, WCD_MBHC_HPH_PA_EN);
if (!is_pa_on) {
wcd_mbhc_compute_impedance(mbhc);
if ((mbhc->zl > mbhc->cfg->linein_th) &&
(mbhc->zr > mbhc->cfg->linein_th) &&
(jack_type == SND_JACK_HEADPHONE)) {
jack_type = SND_JACK_LINEOUT;
mbhc->force_linein = true;
mbhc->current_plug = MBHC_PLUG_TYPE_HIGH_HPH;
if (mbhc->hph_status) {
mbhc->hph_status &= ~(SND_JACK_HEADSET |
SND_JACK_LINEOUT);
snd_soc_jack_report(mbhc->jack, mbhc->hph_status,
WCD_MBHC_JACK_MASK);
}
}
}
/* Do not calculate impedance again for lineout
* as during playback pa is on and impedance values
* will not be correct resulting in lineout detected
* as headphone.
*/
if (is_pa_on && mbhc->force_linein) {
jack_type = SND_JACK_LINEOUT;
mbhc->current_plug = MBHC_PLUG_TYPE_HIGH_HPH;
if (mbhc->hph_status) {
mbhc->hph_status &= ~(SND_JACK_HEADSET |
SND_JACK_LINEOUT);
snd_soc_jack_report(mbhc->jack, mbhc->hph_status,
WCD_MBHC_JACK_MASK);
}
}
mbhc->hph_status |= jack_type;
if (jack_type == SND_JACK_HEADPHONE && mbhc->mbhc_cb->mbhc_micb_ramp_control)
mbhc->mbhc_cb->mbhc_micb_ramp_control(mbhc->component, false);
snd_soc_jack_report(mbhc->jack, (mbhc->hph_status | SND_JACK_MECHANICAL),
WCD_MBHC_JACK_MASK);
}
static void wcd_mbhc_report_plug(struct wcd_mbhc *mbhc, int insertion,
enum snd_jack_types jack_type)
{
WARN_ON(!mutex_is_locked(&mbhc->lock));
if (!insertion) /* Report removal */
wcd_mbhc_report_plug_removal(mbhc, jack_type);
else
wcd_mbhc_report_plug_insertion(mbhc, jack_type);
}
static void wcd_cancel_hs_detect_plug(struct wcd_mbhc *mbhc,
struct work_struct *work)
{
mbhc->hs_detect_work_stop = true;
mutex_unlock(&mbhc->lock);
cancel_work_sync(work);
mutex_lock(&mbhc->lock);
}
static void wcd_mbhc_cancel_pending_work(struct wcd_mbhc *mbhc)
{
/* cancel pending button press */
wcd_cancel_btn_work(mbhc);
/* cancel correct work function */
wcd_cancel_hs_detect_plug(mbhc, &mbhc->correct_plug_swch);
}
static void wcd_mbhc_elec_hs_report_unplug(struct wcd_mbhc *mbhc)
{
wcd_mbhc_cancel_pending_work(mbhc);
/* Report extension cable */
wcd_mbhc_report_plug(mbhc, 1, SND_JACK_LINEOUT);
/*
* Disable HPHL trigger and MIC Schmitt triggers.
* Setup for insertion detection.
*/
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_rem_intr);
wcd_mbhc_curr_micbias_control(mbhc, WCD_MBHC_EN_NONE);
/* Disable HW FSM */
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC, 3);
/* Set the detection type appropriately */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_DETECTION_TYPE, 1);
enable_irq(mbhc->intr_ids->mbhc_hs_ins_intr);
}
static void wcd_mbhc_find_plug_and_report(struct wcd_mbhc *mbhc,
enum wcd_mbhc_plug_type plug_type)
{
if (mbhc->current_plug == plug_type)
return;
mutex_lock(&mbhc->lock);
switch (plug_type) {
case MBHC_PLUG_TYPE_HEADPHONE:
wcd_mbhc_report_plug(mbhc, 1, SND_JACK_HEADPHONE);
break;
case MBHC_PLUG_TYPE_HEADSET:
wcd_mbhc_report_plug(mbhc, 1, SND_JACK_HEADSET);
break;
case MBHC_PLUG_TYPE_HIGH_HPH:
wcd_mbhc_report_plug(mbhc, 1, SND_JACK_LINEOUT);
break;
case MBHC_PLUG_TYPE_GND_MIC_SWAP:
if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADPHONE)
wcd_mbhc_report_plug(mbhc, 0, SND_JACK_HEADPHONE);
if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADSET)
wcd_mbhc_report_plug(mbhc, 0, SND_JACK_HEADSET);
break;
default:
WARN(1, "Unexpected current plug_type %d, plug_type %d\n",
mbhc->current_plug, plug_type);
break;
}
mutex_unlock(&mbhc->lock);
}
static void wcd_schedule_hs_detect_plug(struct wcd_mbhc *mbhc,
struct work_struct *work)
{
WARN_ON(!mutex_is_locked(&mbhc->lock));
mbhc->hs_detect_work_stop = false;
schedule_work(work);
}
static void wcd_mbhc_adc_detect_plug_type(struct wcd_mbhc *mbhc)
{
struct snd_soc_component *component = mbhc->component;
WARN_ON(!mutex_is_locked(&mbhc->lock));
if (mbhc->mbhc_cb->hph_pull_down_ctrl)
mbhc->mbhc_cb->hph_pull_down_ctrl(component, false);
wcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 0);
if (mbhc->mbhc_cb->mbhc_micbias_control) {
mbhc->mbhc_cb->mbhc_micbias_control(component, MIC_BIAS_2,
MICB_ENABLE);
wcd_schedule_hs_detect_plug(mbhc, &mbhc->correct_plug_swch);
}
}
static irqreturn_t wcd_mbhc_mech_plug_detect_irq(int irq, void *data)
{
struct snd_soc_component *component;
enum snd_jack_types jack_type;
struct wcd_mbhc *mbhc = data;
bool detection_type;
component = mbhc->component;
mutex_lock(&mbhc->lock);
mbhc->in_swch_irq_handler = true;
wcd_mbhc_cancel_pending_work(mbhc);
detection_type = wcd_mbhc_read_field(mbhc, WCD_MBHC_MECH_DETECTION_TYPE);
/* Set the detection type appropriately */
wcd_mbhc_write_field(mbhc, WCD_MBHC_MECH_DETECTION_TYPE, !detection_type);
/* Enable micbias ramp */
if (mbhc->mbhc_cb->mbhc_micb_ramp_control)
mbhc->mbhc_cb->mbhc_micb_ramp_control(component, true);
if (detection_type) {
if (mbhc->current_plug != MBHC_PLUG_TYPE_NONE)
goto exit;
/* Make sure MASTER_BIAS_CTL is enabled */
mbhc->mbhc_cb->mbhc_bias(component, true);
mbhc->is_btn_press = false;
wcd_mbhc_adc_detect_plug_type(mbhc);
} else {
/* Disable HW FSM */
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 0);
mbhc->extn_cable_hph_rem = false;
if (mbhc->current_plug == MBHC_PLUG_TYPE_NONE)
goto exit;
mbhc->is_btn_press = false;
switch (mbhc->current_plug) {
case MBHC_PLUG_TYPE_HEADPHONE:
jack_type = SND_JACK_HEADPHONE;
break;
case MBHC_PLUG_TYPE_HEADSET:
jack_type = SND_JACK_HEADSET;
break;
case MBHC_PLUG_TYPE_HIGH_HPH:
if (mbhc->mbhc_detection_logic == WCD_DETECTION_ADC)
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_ISRC_EN, 0);
jack_type = SND_JACK_LINEOUT;
break;
case MBHC_PLUG_TYPE_GND_MIC_SWAP:
dev_err(mbhc->dev, "Ground and Mic Swapped on plug\n");
goto exit;
default:
dev_err(mbhc->dev, "Invalid current plug: %d\n",
mbhc->current_plug);
goto exit;
}
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_rem_intr);
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_ins_intr);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_DETECTION_TYPE, 1);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC, 0);
wcd_mbhc_report_plug(mbhc, 0, jack_type);
}
exit:
mbhc->in_swch_irq_handler = false;
mutex_unlock(&mbhc->lock);
return IRQ_HANDLED;
}
static int wcd_mbhc_get_button_mask(struct wcd_mbhc *mbhc)
{
int mask = 0;
int btn;
btn = wcd_mbhc_read_field(mbhc, WCD_MBHC_BTN_RESULT);
switch (btn) {
case 0:
mask = SND_JACK_BTN_0;
break;
case 1:
mask = SND_JACK_BTN_1;
break;
case 2:
mask = SND_JACK_BTN_2;
break;
case 3:
mask = SND_JACK_BTN_3;
break;
case 4:
mask = SND_JACK_BTN_4;
break;
case 5:
mask = SND_JACK_BTN_5;
break;
default:
break;
}
return mask;
}
static void wcd_btn_long_press_fn(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct wcd_mbhc *mbhc = container_of(dwork, struct wcd_mbhc, mbhc_btn_dwork);
if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADSET)
snd_soc_jack_report(mbhc->jack, mbhc->buttons_pressed,
mbhc->buttons_pressed);
}
static irqreturn_t wcd_mbhc_btn_press_handler(int irq, void *data)
{
struct wcd_mbhc *mbhc = data;
int mask;
unsigned long msec_val;
mutex_lock(&mbhc->lock);
wcd_cancel_btn_work(mbhc);
mbhc->is_btn_press = true;
msec_val = jiffies_to_msecs(jiffies - mbhc->jiffies_atreport);
/* Too short, ignore button press */
if (msec_val < MBHC_BUTTON_PRESS_THRESHOLD_MIN)
goto done;
/* If switch interrupt already kicked in, ignore button press */
if (mbhc->in_swch_irq_handler)
goto done;
/* Plug isn't headset, ignore button press */
if (mbhc->current_plug != MBHC_PLUG_TYPE_HEADSET)
goto done;
mask = wcd_mbhc_get_button_mask(mbhc);
mbhc->buttons_pressed |= mask;
if (schedule_delayed_work(&mbhc->mbhc_btn_dwork, msecs_to_jiffies(400)) == 0)
WARN(1, "Button pressed twice without release event\n");
done:
mutex_unlock(&mbhc->lock);
return IRQ_HANDLED;
}
static irqreturn_t wcd_mbhc_btn_release_handler(int irq, void *data)
{
struct wcd_mbhc *mbhc = data;
int ret;
mutex_lock(&mbhc->lock);
if (mbhc->is_btn_press)
mbhc->is_btn_press = false;
else /* fake btn press */
goto exit;
if (!(mbhc->buttons_pressed & WCD_MBHC_JACK_BUTTON_MASK))
goto exit;
ret = wcd_cancel_btn_work(mbhc);
if (ret == 0) { /* Reporting long button release event */
snd_soc_jack_report(mbhc->jack, 0, mbhc->buttons_pressed);
} else {
if (!mbhc->in_swch_irq_handler) {
/* Reporting btn press n Release */
snd_soc_jack_report(mbhc->jack, mbhc->buttons_pressed,
mbhc->buttons_pressed);
snd_soc_jack_report(mbhc->jack, 0, mbhc->buttons_pressed);
}
}
mbhc->buttons_pressed &= ~WCD_MBHC_JACK_BUTTON_MASK;
exit:
mutex_unlock(&mbhc->lock);
return IRQ_HANDLED;
}
static irqreturn_t wcd_mbhc_hph_ocp_irq(struct wcd_mbhc *mbhc, bool hphr)
{
/* TODO Find a better way to report this to Userspace */
dev_err(mbhc->dev, "MBHC Over Current on %s detected\n",
hphr ? "HPHR" : "HPHL");
wcd_mbhc_write_field(mbhc, WCD_MBHC_OCP_FSM_EN, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_OCP_FSM_EN, 1);
return IRQ_HANDLED;
}
static irqreturn_t wcd_mbhc_hphl_ocp_irq(int irq, void *data)
{
return wcd_mbhc_hph_ocp_irq(data, false);
}
static irqreturn_t wcd_mbhc_hphr_ocp_irq(int irq, void *data)
{
return wcd_mbhc_hph_ocp_irq(data, true);
}
static int wcd_mbhc_initialise(struct wcd_mbhc *mbhc)
{
struct snd_soc_component *component = mbhc->component;
int ret;
ret = pm_runtime_get_sync(component->dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(component->dev,
"pm_runtime_get_sync failed in %s, ret %d\n",
__func__, ret);
pm_runtime_put_noidle(component->dev);
return ret;
}
mutex_lock(&mbhc->lock);
/* enable HS detection */
if (mbhc->mbhc_cb->hph_pull_up_control_v2)
mbhc->mbhc_cb->hph_pull_up_control_v2(component,
HS_PULLUP_I_DEFAULT);
else if (mbhc->mbhc_cb->hph_pull_up_control)
mbhc->mbhc_cb->hph_pull_up_control(component, I_DEFAULT);
else
wcd_mbhc_write_field(mbhc, WCD_MBHC_HS_L_DET_PULL_UP_CTRL, 3);
wcd_mbhc_write_field(mbhc, WCD_MBHC_HPHL_PLUG_TYPE, mbhc->cfg->hphl_swh);
wcd_mbhc_write_field(mbhc, WCD_MBHC_GND_PLUG_TYPE, mbhc->cfg->gnd_swh);
wcd_mbhc_write_field(mbhc, WCD_MBHC_SW_HPH_LP_100K_TO_GND, 1);
if (mbhc->cfg->gnd_det_en && mbhc->mbhc_cb->mbhc_gnd_det_ctrl)
mbhc->mbhc_cb->mbhc_gnd_det_ctrl(component, true);
wcd_mbhc_write_field(mbhc, WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, 1);
wcd_mbhc_write_field(mbhc, WCD_MBHC_L_DET_EN, 1);
/* Insertion debounce set to 96ms */
wcd_mbhc_write_field(mbhc, WCD_MBHC_INSREM_DBNC, 6);
/* Button Debounce set to 16ms */
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_DBNC, 2);
/* enable bias */
mbhc->mbhc_cb->mbhc_bias(component, true);
/* enable MBHC clock */
if (mbhc->mbhc_cb->clk_setup)
mbhc->mbhc_cb->clk_setup(component, true);
/* program HS_VREF value */
wcd_program_hs_vref(mbhc);
wcd_program_btn_threshold(mbhc, false);
mutex_unlock(&mbhc->lock);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return 0;
}
static int wcd_mbhc_get_micbias(struct wcd_mbhc *mbhc)
{
int micbias = 0;
if (mbhc->mbhc_cb->get_micbias_val) {
mbhc->mbhc_cb->get_micbias_val(mbhc->component, &micbias);
} else {
u8 vout_ctl = 0;
/* Read MBHC Micbias (Mic Bias2) voltage */
vout_ctl = wcd_mbhc_read_field(mbhc, WCD_MBHC_MICB2_VOUT);
/* Formula for getting micbias from vout
* micbias = 1.0V + VOUT_CTL * 50mV
*/
micbias = 1000 + (vout_ctl * 50);
}
return micbias;
}
static int wcd_get_voltage_from_adc(u8 val, int micbias)
{
/* Formula for calculating voltage from ADC
* Voltage = ADC_RESULT*12.5mV*V_MICBIAS/1.8
*/
return ((val * 125 * micbias)/(WCD_MBHC_ADC_MICBIAS_MV * 10));
}
static int wcd_measure_adc_continuous(struct wcd_mbhc *mbhc)
{
u8 adc_result;
int output_mv;
int retry = 3;
u8 adc_en;
/* Pre-requisites for ADC continuous measurement */
/* Read legacy electircal detection and disable */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC, 0x00);
/* Set ADC to continuous measurement */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 1);
/* Read ADC Enable bit to restore after adc measurement */
adc_en = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_EN);
/* Disable ADC_ENABLE bit */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);
/* Disable MBHC FSM */
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);
/* Set the MUX selection to IN2P */
wcd_mbhc_write_field(mbhc, WCD_MBHC_MUX_CTL, MUX_CTL_IN2P);
/* Enable MBHC FSM */
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
/* Enable ADC_ENABLE bit */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 1);
while (retry--) {
/* wait for 3 msec before reading ADC result */
usleep_range(3000, 3100);
adc_result = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_RESULT);
}
/* Restore ADC Enable */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, adc_en);
/* Get voltage from ADC result */
output_mv = wcd_get_voltage_from_adc(adc_result, wcd_mbhc_get_micbias(mbhc));
return output_mv;
}
static int wcd_measure_adc_once(struct wcd_mbhc *mbhc, int mux_ctl)
{
struct device *dev = mbhc->dev;
u8 adc_timeout = 0;
u8 adc_complete = 0;
u8 adc_result;
int retry = 6;
int ret;
int output_mv = 0;
u8 adc_en;
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 0);
/* Read ADC Enable bit to restore after adc measurement */
adc_en = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_EN);
/* Trigger ADC one time measurement */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);
/* Set the appropriate MUX selection */
wcd_mbhc_write_field(mbhc, WCD_MBHC_MUX_CTL, mux_ctl);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 1);
while (retry--) {
/* wait for 600usec to get adc results */
usleep_range(600, 610);
/* check for ADC Timeout */
adc_timeout = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_TIMEOUT);
if (adc_timeout)
continue;
/* Read ADC complete bit */
adc_complete = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_COMPLETE);
if (!adc_complete)
continue;
/* Read ADC result */
adc_result = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_RESULT);
/* Get voltage from ADC result */
output_mv = wcd_get_voltage_from_adc(adc_result,
wcd_mbhc_get_micbias(mbhc));
break;
}
/* Restore ADC Enable */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, adc_en);
if (retry <= 0) {
dev_err(dev, "%s: adc complete: %d, adc timeout: %d\n",
__func__, adc_complete, adc_timeout);
ret = -EINVAL;
} else {
ret = output_mv;
}
return ret;
}
/* To determine if cross connection occurred */
static int wcd_check_cross_conn(struct wcd_mbhc *mbhc)
{
u8 adc_mode, elect_ctl, adc_en, fsm_en;
int hphl_adc_res, hphr_adc_res;
bool is_cross_conn = false;
/* If PA is enabled, dont check for cross-connection */
if (wcd_mbhc_read_field(mbhc, WCD_MBHC_HPH_PA_EN))
return -EINVAL;
/* Read legacy electircal detection and disable */
elect_ctl = wcd_mbhc_read_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC, 0);
/* Read and set ADC to single measurement */
adc_mode = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_MODE);
/* Read ADC Enable bit to restore after adc measurement */
adc_en = wcd_mbhc_read_field(mbhc, WCD_MBHC_ADC_EN);
/* Read FSM status */
fsm_en = wcd_mbhc_read_field(mbhc, WCD_MBHC_FSM_EN);
/* Get adc result for HPH L */
hphl_adc_res = wcd_measure_adc_once(mbhc, MUX_CTL_HPH_L);
if (hphl_adc_res < 0)
return hphl_adc_res;
/* Get adc result for HPH R in mV */
hphr_adc_res = wcd_measure_adc_once(mbhc, MUX_CTL_HPH_R);
if (hphr_adc_res < 0)
return hphr_adc_res;
if (hphl_adc_res > HPHL_CROSS_CONN_THRESHOLD ||
hphr_adc_res > HPHL_CROSS_CONN_THRESHOLD)
is_cross_conn = true;
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 0);
/* Set the MUX selection to Auto */
wcd_mbhc_write_field(mbhc, WCD_MBHC_MUX_CTL, MUX_CTL_AUTO);
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, 1);
/* Restore ADC Enable */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, adc_en);
/* Restore ADC mode */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, adc_mode);
/* Restore FSM state */
wcd_mbhc_write_field(mbhc, WCD_MBHC_FSM_EN, fsm_en);
/* Restore electrical detection */
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_SCHMT_ISRC, elect_ctl);
return is_cross_conn;
}
static int wcd_mbhc_adc_get_hs_thres(struct wcd_mbhc *mbhc)
{
int hs_threshold, micbias_mv;
micbias_mv = wcd_mbhc_get_micbias(mbhc);
if (mbhc->cfg->hs_thr) {
if (mbhc->cfg->micb_mv == micbias_mv)
hs_threshold = mbhc->cfg->hs_thr;
else
hs_threshold = (mbhc->cfg->hs_thr *
micbias_mv) / mbhc->cfg->micb_mv;
} else {
hs_threshold = ((WCD_MBHC_ADC_HS_THRESHOLD_MV *
micbias_mv) / WCD_MBHC_ADC_MICBIAS_MV);
}
return hs_threshold;
}
static int wcd_mbhc_adc_get_hph_thres(struct wcd_mbhc *mbhc)
{
int hph_threshold, micbias_mv;
micbias_mv = wcd_mbhc_get_micbias(mbhc);
if (mbhc->cfg->hph_thr) {
if (mbhc->cfg->micb_mv == micbias_mv)
hph_threshold = mbhc->cfg->hph_thr;
else
hph_threshold = (mbhc->cfg->hph_thr *
micbias_mv) / mbhc->cfg->micb_mv;
} else {
hph_threshold = ((WCD_MBHC_ADC_HPH_THRESHOLD_MV *
micbias_mv) / WCD_MBHC_ADC_MICBIAS_MV);
}
return hph_threshold;
}
static void wcd_mbhc_adc_update_fsm_source(struct wcd_mbhc *mbhc,
enum wcd_mbhc_plug_type plug_type)
{
bool micbias2 = false;
switch (plug_type) {
case MBHC_PLUG_TYPE_HEADPHONE:
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 3);
break;
case MBHC_PLUG_TYPE_HEADSET:
if (mbhc->mbhc_cb->micbias_enable_status)
micbias2 = mbhc->mbhc_cb->micbias_enable_status(mbhc->component,
MIC_BIAS_2);
if (!mbhc->is_hs_recording && !micbias2)
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 3);
break;
default:
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 0);
break;
}
}
static void wcd_mbhc_bcs_enable(struct wcd_mbhc *mbhc, int plug_type, bool enable)
{
switch (plug_type) {
case MBHC_PLUG_TYPE_HEADSET:
case MBHC_PLUG_TYPE_HEADPHONE:
if (mbhc->mbhc_cb->bcs_enable)
mbhc->mbhc_cb->bcs_enable(mbhc->component, enable);
break;
default:
break;
}
}
static int wcd_mbhc_get_plug_from_adc(struct wcd_mbhc *mbhc, int adc_result)
{
enum wcd_mbhc_plug_type plug_type;
u32 hph_thr, hs_thr;
hs_thr = wcd_mbhc_adc_get_hs_thres(mbhc);
hph_thr = wcd_mbhc_adc_get_hph_thres(mbhc);
if (adc_result < hph_thr)
plug_type = MBHC_PLUG_TYPE_HEADPHONE;
else if (adc_result > hs_thr)
plug_type = MBHC_PLUG_TYPE_HIGH_HPH;
else
plug_type = MBHC_PLUG_TYPE_HEADSET;
return plug_type;
}
static int wcd_mbhc_get_spl_hs_thres(struct wcd_mbhc *mbhc)
{
int hs_threshold, micbias_mv;
micbias_mv = wcd_mbhc_get_micbias(mbhc);
if (mbhc->cfg->hs_thr && mbhc->cfg->micb_mv != WCD_MBHC_ADC_MICBIAS_MV) {
if (mbhc->cfg->micb_mv == micbias_mv)
hs_threshold = mbhc->cfg->hs_thr;
else
hs_threshold = (mbhc->cfg->hs_thr * micbias_mv) / mbhc->cfg->micb_mv;
} else {
hs_threshold = ((WCD_MBHC_ADC_HS_THRESHOLD_MV * micbias_mv) /
WCD_MBHC_ADC_MICBIAS_MV);
}
return hs_threshold;
}
static bool wcd_mbhc_check_for_spl_headset(struct wcd_mbhc *mbhc)
{
bool is_spl_hs = false;
int output_mv, hs_threshold, hph_threshold;
if (!mbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic)
return false;
/* Bump up MIC_BIAS2 to 2.7V */
mbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic(mbhc->component, MIC_BIAS_2, true);
usleep_range(10000, 10100);
output_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);
hs_threshold = wcd_mbhc_get_spl_hs_thres(mbhc);
hph_threshold = wcd_mbhc_adc_get_hph_thres(mbhc);
if (!(output_mv > hs_threshold || output_mv < hph_threshold))
is_spl_hs = true;
/* Back MIC_BIAS2 to 1.8v if the type is not special headset */
if (!is_spl_hs) {
mbhc->mbhc_cb->mbhc_micb_ctrl_thr_mic(mbhc->component, MIC_BIAS_2, false);
/* Add 10ms delay for micbias to settle */
usleep_range(10000, 10100);
}
return is_spl_hs;
}
static void wcd_correct_swch_plug(struct work_struct *work)
{
struct wcd_mbhc *mbhc;
struct snd_soc_component *component;
enum wcd_mbhc_plug_type plug_type = MBHC_PLUG_TYPE_INVALID;
unsigned long timeout;
int pt_gnd_mic_swap_cnt = 0;
int output_mv, cross_conn, hs_threshold, try = 0, micbias_mv;
bool is_spl_hs = false;
bool is_pa_on;
int ret;
mbhc = container_of(work, struct wcd_mbhc, correct_plug_swch);
component = mbhc->component;
ret = pm_runtime_get_sync(component->dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(component->dev,
"pm_runtime_get_sync failed in %s, ret %d\n",
__func__, ret);
pm_runtime_put_noidle(component->dev);
return;
}
micbias_mv = wcd_mbhc_get_micbias(mbhc);
hs_threshold = wcd_mbhc_adc_get_hs_thres(mbhc);
/* Mask ADC COMPLETE interrupt */
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_ins_intr);
/* Check for cross connection */
do {
cross_conn = wcd_check_cross_conn(mbhc);
try++;
} while (try < GND_MIC_SWAP_THRESHOLD);
if (cross_conn > 0) {
plug_type = MBHC_PLUG_TYPE_GND_MIC_SWAP;
dev_err(mbhc->dev, "cross connection found, Plug type %d\n",
plug_type);
goto correct_plug_type;
}
/* Find plug type */
output_mv = wcd_measure_adc_continuous(mbhc);
plug_type = wcd_mbhc_get_plug_from_adc(mbhc, output_mv);
/*
* Report plug type if it is either headset or headphone
* else start the 3 sec loop
*/
switch (plug_type) {
case MBHC_PLUG_TYPE_HEADPHONE:
wcd_mbhc_find_plug_and_report(mbhc, plug_type);
break;
case MBHC_PLUG_TYPE_HEADSET:
wcd_mbhc_find_plug_and_report(mbhc, plug_type);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 1);
break;
default:
break;
}
correct_plug_type:
/* Disable BCS slow insertion detection */
wcd_mbhc_bcs_enable(mbhc, plug_type, false);
timeout = jiffies + msecs_to_jiffies(HS_DETECT_PLUG_TIME_MS);
while (!time_after(jiffies, timeout)) {
if (mbhc->hs_detect_work_stop) {
wcd_micbias_disable(mbhc);
goto exit;
}
msleep(180);
/*
* Use ADC single mode to minimize the chance of missing out
* btn press/release for HEADSET type during correct work.
*/
output_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);
plug_type = wcd_mbhc_get_plug_from_adc(mbhc, output_mv);
is_pa_on = wcd_mbhc_read_field(mbhc, WCD_MBHC_HPH_PA_EN);
if (output_mv > hs_threshold && !is_spl_hs) {
is_spl_hs = wcd_mbhc_check_for_spl_headset(mbhc);
output_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);
if (is_spl_hs) {
hs_threshold *= wcd_mbhc_get_micbias(mbhc);
hs_threshold /= micbias_mv;
}
}
if ((output_mv <= hs_threshold) && !is_pa_on) {
/* Check for cross connection*/
cross_conn = wcd_check_cross_conn(mbhc);
if (cross_conn > 0) { /* cross-connection */
pt_gnd_mic_swap_cnt++;
if (pt_gnd_mic_swap_cnt < GND_MIC_SWAP_THRESHOLD)
continue;
else
plug_type = MBHC_PLUG_TYPE_GND_MIC_SWAP;
} else if (!cross_conn) { /* no cross connection */
pt_gnd_mic_swap_cnt = 0;
plug_type = wcd_mbhc_get_plug_from_adc(mbhc, output_mv);
continue;
} else /* Error if (cross_conn < 0) */
continue;
if (pt_gnd_mic_swap_cnt == GND_MIC_SWAP_THRESHOLD) {
/* US_EU gpio present, flip switch */
if (mbhc->cfg->swap_gnd_mic) {
if (mbhc->cfg->swap_gnd_mic(component, true))
continue;
}
}
}
/* cable is extension cable */
if (output_mv > hs_threshold || mbhc->force_linein)
plug_type = MBHC_PLUG_TYPE_HIGH_HPH;
}
wcd_mbhc_bcs_enable(mbhc, plug_type, true);
if (plug_type == MBHC_PLUG_TYPE_HIGH_HPH) {
if (is_spl_hs)
plug_type = MBHC_PLUG_TYPE_HEADSET;
else
wcd_mbhc_write_field(mbhc, WCD_MBHC_ELECT_ISRC_EN, 1);
}
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);
wcd_mbhc_find_plug_and_report(mbhc, plug_type);
/*
* Set DETECTION_DONE bit for HEADSET
* so that btn press/release interrupt can be generated.
* For other plug type, clear the bit.
*/
if (plug_type == MBHC_PLUG_TYPE_HEADSET)
wcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 1);
else
wcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 0);
if (mbhc->mbhc_cb->mbhc_micbias_control)
wcd_mbhc_adc_update_fsm_source(mbhc, plug_type);
exit:
if (mbhc->mbhc_cb->mbhc_micbias_control/* && !mbhc->micbias_enable*/)
mbhc->mbhc_cb->mbhc_micbias_control(component, MIC_BIAS_2, MICB_DISABLE);
/*
* If plug type is corrected from special headset to headphone,
* clear the micbias enable flag, set micbias back to 1.8V and
* disable micbias.
*/
if (plug_type == MBHC_PLUG_TYPE_HEADPHONE) {
wcd_micbias_disable(mbhc);
/*
* Enable ADC COMPLETE interrupt for HEADPHONE.
* Btn release may happen after the correct work, ADC COMPLETE
* interrupt needs to be captured to correct plug type.
*/
enable_irq(mbhc->intr_ids->mbhc_hs_ins_intr);
}
if (mbhc->mbhc_cb->hph_pull_down_ctrl)
mbhc->mbhc_cb->hph_pull_down_ctrl(component, true);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
}
static irqreturn_t wcd_mbhc_adc_hs_rem_irq(int irq, void *data)
{
struct wcd_mbhc *mbhc = data;
unsigned long timeout;
int adc_threshold, output_mv, retry = 0;
mutex_lock(&mbhc->lock);
timeout = jiffies + msecs_to_jiffies(WCD_FAKE_REMOVAL_MIN_PERIOD_MS);
adc_threshold = wcd_mbhc_adc_get_hs_thres(mbhc);
do {
retry++;
/*
* read output_mv every 10ms to look for
* any change in IN2_P
*/
usleep_range(10000, 10100);
output_mv = wcd_measure_adc_once(mbhc, MUX_CTL_IN2P);
/* Check for fake removal */
if ((output_mv <= adc_threshold) && retry > FAKE_REM_RETRY_ATTEMPTS)
goto exit;
} while (!time_after(jiffies, timeout));
/*
* ADC COMPLETE and ELEC_REM interrupts are both enabled for
* HEADPHONE, need to reject the ADC COMPLETE interrupt which
* follows ELEC_REM one when HEADPHONE is removed.
*/
if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADPHONE)
mbhc->extn_cable_hph_rem = true;
wcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_MODE, 0);
wcd_mbhc_write_field(mbhc, WCD_MBHC_ADC_EN, 0);
wcd_mbhc_elec_hs_report_unplug(mbhc);
wcd_mbhc_write_field(mbhc, WCD_MBHC_BTN_ISRC_CTL, 0);
exit:
mutex_unlock(&mbhc->lock);
return IRQ_HANDLED;
}
static irqreturn_t wcd_mbhc_adc_hs_ins_irq(int irq, void *data)
{
struct wcd_mbhc *mbhc = data;
u8 clamp_state;
u8 clamp_retry = WCD_MBHC_FAKE_INS_RETRY;
/*
* ADC COMPLETE and ELEC_REM interrupts are both enabled for HEADPHONE,
* need to reject the ADC COMPLETE interrupt which follows ELEC_REM one
* when HEADPHONE is removed.
*/
if (mbhc->extn_cable_hph_rem == true) {
mbhc->extn_cable_hph_rem = false;
return IRQ_HANDLED;
}
do {
clamp_state = wcd_mbhc_read_field(mbhc, WCD_MBHC_IN2P_CLAMP_STATE);
if (clamp_state)
return IRQ_HANDLED;
/*
* check clamp for 120ms but at 30ms chunks to leave
* room for other interrupts to be processed
*/
usleep_range(30000, 30100);
} while (--clamp_retry);
/*
* If current plug is headphone then there is no chance to
* get ADC complete interrupt, so connected cable should be
* headset not headphone.
*/
if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADPHONE) {
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_ins_intr);
wcd_mbhc_write_field(mbhc, WCD_MBHC_DETECTION_DONE, 1);
wcd_mbhc_find_plug_and_report(mbhc, MBHC_PLUG_TYPE_HEADSET);
return IRQ_HANDLED;
}
return IRQ_HANDLED;
}
int wcd_mbhc_get_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, uint32_t *zr)
{
*zl = mbhc->zl;
*zr = mbhc->zr;
if (*zl && *zr)
return 0;
else
return -EINVAL;
}
EXPORT_SYMBOL(wcd_mbhc_get_impedance);
void wcd_mbhc_set_hph_type(struct wcd_mbhc *mbhc, int hph_type)
{
mbhc->hph_type = hph_type;
}
EXPORT_SYMBOL(wcd_mbhc_set_hph_type);
int wcd_mbhc_get_hph_type(struct wcd_mbhc *mbhc)
{
return mbhc->hph_type;
}
EXPORT_SYMBOL(wcd_mbhc_get_hph_type);
int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *cfg,
struct snd_soc_jack *jack)
{
if (!mbhc || !cfg || !jack)
return -EINVAL;
mbhc->cfg = cfg;
mbhc->jack = jack;
return wcd_mbhc_initialise(mbhc);
}
EXPORT_SYMBOL(wcd_mbhc_start);
void wcd_mbhc_stop(struct wcd_mbhc *mbhc)
{
mbhc->current_plug = MBHC_PLUG_TYPE_NONE;
mbhc->hph_status = 0;
disable_irq_nosync(mbhc->intr_ids->hph_left_ocp);
disable_irq_nosync(mbhc->intr_ids->hph_right_ocp);
}
EXPORT_SYMBOL(wcd_mbhc_stop);
int wcd_dt_parse_mbhc_data(struct device *dev, struct wcd_mbhc_config *cfg)
{
struct device_node *np = dev->of_node;
int ret, i, microvolt;
if (of_property_read_bool(np, "qcom,hphl-jack-type-normally-closed"))
cfg->hphl_swh = false;
else
cfg->hphl_swh = true;
if (of_property_read_bool(np, "qcom,ground-jack-type-normally-closed"))
cfg->gnd_swh = false;
else
cfg->gnd_swh = true;
ret = of_property_read_u32(np, "qcom,mbhc-headset-vthreshold-microvolt",
µvolt);
if (ret)
dev_dbg(dev, "missing qcom,mbhc-hs-mic-max-vthreshold--microvolt in dt node\n");
else
cfg->hs_thr = microvolt/1000;
ret = of_property_read_u32(np, "qcom,mbhc-headphone-vthreshold-microvolt",
µvolt);
if (ret)
dev_dbg(dev, "missing qcom,mbhc-hs-mic-min-vthreshold-microvolt entry\n");
else
cfg->hph_thr = microvolt/1000;
ret = of_property_read_u32_array(np,
"qcom,mbhc-buttons-vthreshold-microvolt",
&cfg->btn_high[0],
WCD_MBHC_DEF_BUTTONS);
if (ret)
dev_err(dev, "missing qcom,mbhc-buttons-vthreshold-microvolt entry\n");
for (i = 0; i < WCD_MBHC_DEF_BUTTONS; i++) {
if (ret) /* default voltage */
cfg->btn_high[i] = 500000;
else
/* Micro to Milli Volts */
cfg->btn_high[i] = cfg->btn_high[i]/1000;
}
return 0;
}
EXPORT_SYMBOL(wcd_dt_parse_mbhc_data);
struct wcd_mbhc *wcd_mbhc_init(struct snd_soc_component *component,
const struct wcd_mbhc_cb *mbhc_cb,
const struct wcd_mbhc_intr *intr_ids,
struct wcd_mbhc_field *fields,
bool impedance_det_en)
{
struct device *dev = component->dev;
struct wcd_mbhc *mbhc;
int ret;
if (!intr_ids || !fields || !mbhc_cb || !mbhc_cb->mbhc_bias || !mbhc_cb->set_btn_thr) {
dev_err(dev, "%s: Insufficient mbhc configuration\n", __func__);
return ERR_PTR(-EINVAL);
}
mbhc = kzalloc(sizeof(*mbhc), GFP_KERNEL);
if (!mbhc)
return ERR_PTR(-ENOMEM);
mbhc->component = component;
mbhc->dev = dev;
mbhc->intr_ids = intr_ids;
mbhc->mbhc_cb = mbhc_cb;
mbhc->fields = fields;
mbhc->mbhc_detection_logic = WCD_DETECTION_ADC;
if (mbhc_cb->compute_impedance)
mbhc->impedance_detect = impedance_det_en;
INIT_DELAYED_WORK(&mbhc->mbhc_btn_dwork, wcd_btn_long_press_fn);
mutex_init(&mbhc->lock);
INIT_WORK(&mbhc->correct_plug_swch, wcd_correct_swch_plug);
ret = request_threaded_irq(mbhc->intr_ids->mbhc_sw_intr, NULL,
wcd_mbhc_mech_plug_detect_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"mbhc sw intr", mbhc);
if (ret)
goto err_free_mbhc;
ret = request_threaded_irq(mbhc->intr_ids->mbhc_btn_press_intr, NULL,
wcd_mbhc_btn_press_handler,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"Button Press detect", mbhc);
if (ret)
goto err_free_sw_intr;
ret = request_threaded_irq(mbhc->intr_ids->mbhc_btn_release_intr, NULL,
wcd_mbhc_btn_release_handler,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"Button Release detect", mbhc);
if (ret)
goto err_free_btn_press_intr;
ret = request_threaded_irq(mbhc->intr_ids->mbhc_hs_ins_intr, NULL,
wcd_mbhc_adc_hs_ins_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"Elect Insert", mbhc);
if (ret)
goto err_free_btn_release_intr;
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_ins_intr);
ret = request_threaded_irq(mbhc->intr_ids->mbhc_hs_rem_intr, NULL,
wcd_mbhc_adc_hs_rem_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"Elect Remove", mbhc);
if (ret)
goto err_free_hs_ins_intr;
disable_irq_nosync(mbhc->intr_ids->mbhc_hs_rem_intr);
ret = request_threaded_irq(mbhc->intr_ids->hph_left_ocp, NULL,
wcd_mbhc_hphl_ocp_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"HPH_L OCP detect", mbhc);
if (ret)
goto err_free_hs_rem_intr;
ret = request_threaded_irq(mbhc->intr_ids->hph_right_ocp, NULL,
wcd_mbhc_hphr_ocp_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"HPH_R OCP detect", mbhc);
if (ret)
goto err_free_hph_left_ocp;
return mbhc;
err_free_hph_left_ocp:
free_irq(mbhc->intr_ids->hph_left_ocp, mbhc);
err_free_hs_rem_intr:
free_irq(mbhc->intr_ids->mbhc_hs_rem_intr, mbhc);
err_free_hs_ins_intr:
free_irq(mbhc->intr_ids->mbhc_hs_ins_intr, mbhc);
err_free_btn_release_intr:
free_irq(mbhc->intr_ids->mbhc_btn_release_intr, mbhc);
err_free_btn_press_intr:
free_irq(mbhc->intr_ids->mbhc_btn_press_intr, mbhc);
err_free_sw_intr:
free_irq(mbhc->intr_ids->mbhc_sw_intr, mbhc);
err_free_mbhc:
kfree(mbhc);
dev_err(dev, "Failed to request mbhc interrupts %d\n", ret);
return ERR_PTR(ret);
}
EXPORT_SYMBOL(wcd_mbhc_init);
void wcd_mbhc_deinit(struct wcd_mbhc *mbhc)
{
free_irq(mbhc->intr_ids->hph_right_ocp, mbhc);
free_irq(mbhc->intr_ids->hph_left_ocp, mbhc);
free_irq(mbhc->intr_ids->mbhc_hs_rem_intr, mbhc);
free_irq(mbhc->intr_ids->mbhc_hs_ins_intr, mbhc);
free_irq(mbhc->intr_ids->mbhc_btn_release_intr, mbhc);
free_irq(mbhc->intr_ids->mbhc_btn_press_intr, mbhc);
free_irq(mbhc->intr_ids->mbhc_sw_intr, mbhc);
mutex_lock(&mbhc->lock);
wcd_cancel_hs_detect_plug(mbhc, &mbhc->correct_plug_swch);
mutex_unlock(&mbhc->lock);
kfree(mbhc);
}
EXPORT_SYMBOL(wcd_mbhc_deinit);
static int __init mbhc_init(void)
{
return 0;
}
static void __exit mbhc_exit(void)
{
}
module_init(mbhc_init);
module_exit(mbhc_exit);
MODULE_DESCRIPTION("wcd MBHC v2 module");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wcd-mbhc-v2.c |
/* SPDX-License-Identifier: GPL-2.0-only
*
* ALSA SoC TLV320AIC3x codec driver I2C interface
*
* Author: Arun KS, <[email protected]>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd.,
*
* Based on sound/soc/codecs/wm8731.c by Richard Purdie
*
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tlv320aic3x.h"
static const struct i2c_device_id aic3x_i2c_id[] = {
{ "tlv320aic3x", AIC3X_MODEL_3X },
{ "tlv320aic33", AIC3X_MODEL_33 },
{ "tlv320aic3007", AIC3X_MODEL_3007 },
{ "tlv320aic3104", AIC3X_MODEL_3104 },
{ "tlv320aic3106", AIC3X_MODEL_3106 },
{ }
};
MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
static int aic3x_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
struct regmap_config config;
const struct i2c_device_id *id = i2c_match_id(aic3x_i2c_id, i2c);
config = aic3x_regmap;
config.reg_bits = 8;
config.val_bits = 8;
regmap = devm_regmap_init_i2c(i2c, &config);
return aic3x_probe(&i2c->dev, regmap, id->driver_data);
}
static void aic3x_i2c_remove(struct i2c_client *i2c)
{
aic3x_remove(&i2c->dev);
}
static const struct of_device_id aic3x_of_id[] = {
{ .compatible = "ti,tlv320aic3x", },
{ .compatible = "ti,tlv320aic33" },
{ .compatible = "ti,tlv320aic3007" },
{ .compatible = "ti,tlv320aic3104" },
{ .compatible = "ti,tlv320aic3106" },
{},
};
MODULE_DEVICE_TABLE(of, aic3x_of_id);
static struct i2c_driver aic3x_i2c_driver = {
.driver = {
.name = "tlv320aic3x",
.of_match_table = aic3x_of_id,
},
.probe = aic3x_i2c_probe,
.remove = aic3x_i2c_remove,
.id_table = aic3x_i2c_id,
};
module_i2c_driver(aic3x_i2c_driver);
MODULE_DESCRIPTION("ASoC TLV320AIC3x codec driver I2C");
MODULE_AUTHOR("Arun KS <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic3x-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// ALSA SoC Audio driver for CS47L85 codec
//
// Copyright (C) 2015-2019 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/irqchip/irq-madera.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
#include "wm_adsp.h"
#define DRV_NAME "cs47l85-codec"
#define CS47L85_NUM_ADSP 7
#define CS47L85_MONO_OUTPUTS 4
struct cs47l85 {
struct madera_priv core;
struct madera_fll fll[3];
};
static const struct cs_dsp_region cs47l85_dsp1_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x080000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
};
static const struct cs_dsp_region cs47l85_dsp2_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x100000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x160000 },
{ .type = WMFW_ADSP2_XM, .base = 0x120000 },
{ .type = WMFW_ADSP2_YM, .base = 0x140000 },
};
static const struct cs_dsp_region cs47l85_dsp3_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x180000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x1a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x1c0000 },
};
static const struct cs_dsp_region cs47l85_dsp4_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x200000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x260000 },
{ .type = WMFW_ADSP2_XM, .base = 0x220000 },
{ .type = WMFW_ADSP2_YM, .base = 0x240000 },
};
static const struct cs_dsp_region cs47l85_dsp5_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x280000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x2e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x2a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x2c0000 },
};
static const struct cs_dsp_region cs47l85_dsp6_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x300000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x360000 },
{ .type = WMFW_ADSP2_XM, .base = 0x320000 },
{ .type = WMFW_ADSP2_YM, .base = 0x340000 },
};
static const struct cs_dsp_region cs47l85_dsp7_regions[] = {
{ .type = WMFW_ADSP2_PM, .base = 0x380000 },
{ .type = WMFW_ADSP2_ZM, .base = 0x3e0000 },
{ .type = WMFW_ADSP2_XM, .base = 0x3a0000 },
{ .type = WMFW_ADSP2_YM, .base = 0x3c0000 },
};
static const struct cs_dsp_region *cs47l85_dsp_regions[] = {
cs47l85_dsp1_regions,
cs47l85_dsp2_regions,
cs47l85_dsp3_regions,
cs47l85_dsp4_regions,
cs47l85_dsp5_regions,
cs47l85_dsp6_regions,
cs47l85_dsp7_regions,
};
static const unsigned int wm_adsp2_control_bases[] = {
MADERA_DSP1_CONFIG_1,
MADERA_DSP2_CONFIG_1,
MADERA_DSP3_CONFIG_1,
MADERA_DSP4_CONFIG_1,
MADERA_DSP5_CONFIG_1,
MADERA_DSP6_CONFIG_1,
MADERA_DSP7_CONFIG_1,
};
static int cs47l85_adsp_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l85->core;
struct madera *madera = priv->madera;
unsigned int freq;
int ret;
ret = regmap_read(madera->regmap, MADERA_DSP_CLOCK_1, &freq);
if (ret != 0) {
dev_err(madera->dev,
"Failed to read MADERA_DSP_CLOCK_1: %d\n", ret);
return ret;
}
freq &= MADERA_DSP_CLK_FREQ_LEGACY_MASK;
freq >>= MADERA_DSP_CLK_FREQ_LEGACY_SHIFT;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = madera_set_adsp_clk(&cs47l85->core, w->shift, freq);
if (ret)
return ret;
break;
default:
break;
}
return wm_adsp_early_event(w, kcontrol, event);
}
#define CS47L85_NG_SRC(name, base) \
SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \
SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \
SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0)
#define CS47L85_RXANC_INPUT_ROUTES(widget, name) \
{ widget, NULL, name " NG Mux" }, \
{ name " NG Internal", NULL, "RXANC NG Clock" }, \
{ name " NG Internal", NULL, name " Channel" }, \
{ name " NG External", NULL, "RXANC NG External Clock" }, \
{ name " NG External", NULL, name " Channel" }, \
{ name " NG Mux", "None", name " Channel" }, \
{ name " NG Mux", "Internal", name " NG Internal" }, \
{ name " NG Mux", "External", name " NG External" }, \
{ name " Channel", "Left", name " Left Input" }, \
{ name " Channel", "Combine", name " Left Input" }, \
{ name " Channel", "Right", name " Right Input" }, \
{ name " Channel", "Combine", name " Right Input" }, \
{ name " Left Input", "IN1", "IN1L" }, \
{ name " Right Input", "IN1", "IN1R" }, \
{ name " Left Input", "IN2", "IN2L" }, \
{ name " Right Input", "IN2", "IN2R" }, \
{ name " Left Input", "IN3", "IN3L" }, \
{ name " Right Input", "IN3", "IN3R" }, \
{ name " Left Input", "IN4", "IN4L" }, \
{ name " Right Input", "IN4", "IN4R" }, \
{ name " Left Input", "IN5", "IN5L" }, \
{ name " Right Input", "IN5", "IN5R" }, \
{ name " Left Input", "IN6", "IN6L" }, \
{ name " Right Input", "IN6", "IN6R" }
#define CS47L85_RXANC_OUTPUT_ROUTES(widget, name) \
{ widget, NULL, name " ANC Source" }, \
{ name " ANC Source", "RXANCL", "RXANCL" }, \
{ name " ANC Source", "RXANCR", "RXANCR" }
static void cs47l85_hp_post_enable(struct snd_soc_dapm_widget *w)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
unsigned int val;
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
case MADERA_OUT1R_ENA_SHIFT:
val = snd_soc_component_read(component, MADERA_OUTPUT_ENABLES_1);
val &= (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA);
if (val != (MADERA_OUT1L_ENA | MADERA_OUT1R_ENA))
break;
snd_soc_component_update_bits(component,
MADERA_EDRE_HP_STEREO_CONTROL,
0x0001, 1);
break;
default:
break;
}
}
static void cs47l85_hp_post_disable(struct snd_soc_dapm_widget *w)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case MADERA_OUT1L_ENA_SHIFT:
snd_soc_component_write(component, MADERA_DCS_HP1L_CONTROL,
0x2006);
break;
case MADERA_OUT1R_ENA_SHIFT:
snd_soc_component_write(component, MADERA_DCS_HP1R_CONTROL,
0x2006);
break;
default:
return;
}
/* Only get to here for OUT1L and OUT1R */
snd_soc_component_update_bits(component,
MADERA_EDRE_HP_STEREO_CONTROL,
0x0001, 0);
}
static int cs47l85_hp_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
case SND_SOC_DAPM_PRE_PMD:
return madera_hp_ev(w, kcontrol, event);
case SND_SOC_DAPM_POST_PMU:
ret = madera_hp_ev(w, kcontrol, event);
if (ret < 0)
return ret;
cs47l85_hp_post_enable(w);
return 0;
case SND_SOC_DAPM_POST_PMD:
ret = madera_hp_ev(w, kcontrol, event);
cs47l85_hp_post_disable(w);
return ret;
default:
return -EINVAL;
}
}
static const struct snd_kcontrol_new cs47l85_snd_controls[] = {
SOC_ENUM("IN1 OSR", madera_in_dmic_osr[0]),
SOC_ENUM("IN2 OSR", madera_in_dmic_osr[1]),
SOC_ENUM("IN3 OSR", madera_in_dmic_osr[2]),
SOC_ENUM("IN4 OSR", madera_in_dmic_osr[3]),
SOC_ENUM("IN5 OSR", madera_in_dmic_osr[4]),
SOC_ENUM("IN6 OSR", madera_in_dmic_osr[5]),
SOC_SINGLE_RANGE_TLV("IN1L Volume", MADERA_IN1L_CONTROL,
MADERA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN1R Volume", MADERA_IN1R_CONTROL,
MADERA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2L Volume", MADERA_IN2L_CONTROL,
MADERA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN2R Volume", MADERA_IN2R_CONTROL,
MADERA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN3L Volume", MADERA_IN3L_CONTROL,
MADERA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_SINGLE_RANGE_TLV("IN3R Volume", MADERA_IN3R_CONTROL,
MADERA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, madera_ana_tlv),
SOC_ENUM("IN HPF Cutoff Frequency", madera_in_hpf_cut_enum),
SOC_SINGLE("IN1L HPF Switch", MADERA_IN1L_CONTROL,
MADERA_IN1L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN1R HPF Switch", MADERA_IN1R_CONTROL,
MADERA_IN1R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2L HPF Switch", MADERA_IN2L_CONTROL,
MADERA_IN2L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN2R HPF Switch", MADERA_IN2R_CONTROL,
MADERA_IN2R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3L HPF Switch", MADERA_IN3L_CONTROL,
MADERA_IN3L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN3R HPF Switch", MADERA_IN3R_CONTROL,
MADERA_IN3R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4L HPF Switch", MADERA_IN4L_CONTROL,
MADERA_IN4L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN4R HPF Switch", MADERA_IN4R_CONTROL,
MADERA_IN4R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN5L HPF Switch", MADERA_IN5L_CONTROL,
MADERA_IN5L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN5R HPF Switch", MADERA_IN5R_CONTROL,
MADERA_IN5R_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN6L HPF Switch", MADERA_IN6L_CONTROL,
MADERA_IN6L_HPF_SHIFT, 1, 0),
SOC_SINGLE("IN6R HPF Switch", MADERA_IN6R_CONTROL,
MADERA_IN6R_HPF_SHIFT, 1, 0),
SOC_SINGLE_TLV("IN1L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1L,
MADERA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN1R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_1R,
MADERA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2L,
MADERA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN2R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_2R,
MADERA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN3L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3L,
MADERA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN3R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_3R,
MADERA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN4L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4L,
MADERA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN4R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_4R,
MADERA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN5L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5L,
MADERA_IN5L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN5R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_5R,
MADERA_IN5R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN6L Digital Volume", MADERA_ADC_DIGITAL_VOLUME_6L,
MADERA_IN6L_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_SINGLE_TLV("IN6R Digital Volume", MADERA_ADC_DIGITAL_VOLUME_6R,
MADERA_IN6R_DIG_VOL_SHIFT, 0xbf, 0, madera_digital_tlv),
SOC_ENUM("Input Ramp Up", madera_in_vi_ramp),
SOC_ENUM("Input Ramp Down", madera_in_vd_ramp),
SND_SOC_BYTES("RXANC Coefficients", MADERA_ANC_COEFF_START,
MADERA_ANC_COEFF_END - MADERA_ANC_COEFF_START + 1),
SND_SOC_BYTES("RXANCL Config", MADERA_FCL_FILTER_CONTROL, 1),
SND_SOC_BYTES("RXANCL Coefficients", MADERA_FCL_COEFF_START,
MADERA_FCL_COEFF_END - MADERA_FCL_COEFF_START + 1),
SND_SOC_BYTES("RXANCR Config", MADERA_FCR_FILTER_CONTROL, 1),
SND_SOC_BYTES("RXANCR Coefficients", MADERA_FCR_COEFF_START,
MADERA_FCR_COEFF_END - MADERA_FCR_COEFF_START + 1),
MADERA_MIXER_CONTROLS("EQ1", MADERA_EQ1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ2", MADERA_EQ2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ3", MADERA_EQ3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("EQ4", MADERA_EQ4MIX_INPUT_1_SOURCE),
MADERA_EQ_CONTROL("EQ1 Coefficients", MADERA_EQ1_2),
SOC_SINGLE_TLV("EQ1 B1 Volume", MADERA_EQ1_1, MADERA_EQ1_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B2 Volume", MADERA_EQ1_1, MADERA_EQ1_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B3 Volume", MADERA_EQ1_1, MADERA_EQ1_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B4 Volume", MADERA_EQ1_2, MADERA_EQ1_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ1 B5 Volume", MADERA_EQ1_2, MADERA_EQ1_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ2 Coefficients", MADERA_EQ2_2),
SOC_SINGLE_TLV("EQ2 B1 Volume", MADERA_EQ2_1, MADERA_EQ2_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B2 Volume", MADERA_EQ2_1, MADERA_EQ2_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B3 Volume", MADERA_EQ2_1, MADERA_EQ2_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B4 Volume", MADERA_EQ2_2, MADERA_EQ2_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ2 B5 Volume", MADERA_EQ2_2, MADERA_EQ2_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ3 Coefficients", MADERA_EQ3_2),
SOC_SINGLE_TLV("EQ3 B1 Volume", MADERA_EQ3_1, MADERA_EQ3_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B2 Volume", MADERA_EQ3_1, MADERA_EQ3_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B3 Volume", MADERA_EQ3_1, MADERA_EQ3_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B4 Volume", MADERA_EQ3_2, MADERA_EQ3_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ3 B5 Volume", MADERA_EQ3_2, MADERA_EQ3_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_EQ_CONTROL("EQ4 Coefficients", MADERA_EQ4_2),
SOC_SINGLE_TLV("EQ4 B1 Volume", MADERA_EQ4_1, MADERA_EQ4_B1_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B2 Volume", MADERA_EQ4_1, MADERA_EQ4_B2_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B3 Volume", MADERA_EQ4_1, MADERA_EQ4_B3_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B4 Volume", MADERA_EQ4_2, MADERA_EQ4_B4_GAIN_SHIFT,
24, 0, madera_eq_tlv),
SOC_SINGLE_TLV("EQ4 B5 Volume", MADERA_EQ4_2, MADERA_EQ4_B5_GAIN_SHIFT,
24, 0, madera_eq_tlv),
MADERA_MIXER_CONTROLS("DRC1L", MADERA_DRC1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC1R", MADERA_DRC1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2L", MADERA_DRC2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DRC2R", MADERA_DRC2RMIX_INPUT_1_SOURCE),
SND_SOC_BYTES_MASK("DRC1", MADERA_DRC1_CTRL1, 5,
MADERA_DRC1R_ENA | MADERA_DRC1L_ENA),
SND_SOC_BYTES_MASK("DRC2", MADERA_DRC2_CTRL1, 5,
MADERA_DRC2R_ENA | MADERA_DRC2L_ENA),
MADERA_MIXER_CONTROLS("LHPF1", MADERA_HPLP1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF2", MADERA_HPLP2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF3", MADERA_HPLP3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("LHPF4", MADERA_HPLP4MIX_INPUT_1_SOURCE),
MADERA_LHPF_CONTROL("LHPF1 Coefficients", MADERA_HPLPF1_2),
MADERA_LHPF_CONTROL("LHPF2 Coefficients", MADERA_HPLPF2_2),
MADERA_LHPF_CONTROL("LHPF3 Coefficients", MADERA_HPLPF3_2),
MADERA_LHPF_CONTROL("LHPF4 Coefficients", MADERA_HPLPF4_2),
SOC_ENUM("LHPF1 Mode", madera_lhpf1_mode),
SOC_ENUM("LHPF2 Mode", madera_lhpf2_mode),
SOC_ENUM("LHPF3 Mode", madera_lhpf3_mode),
SOC_ENUM("LHPF4 Mode", madera_lhpf4_mode),
MADERA_RATE_ENUM("ISRC1 FSL", madera_isrc_fsl[0]),
MADERA_RATE_ENUM("ISRC2 FSL", madera_isrc_fsl[1]),
MADERA_RATE_ENUM("ISRC3 FSL", madera_isrc_fsl[2]),
MADERA_RATE_ENUM("ISRC4 FSL", madera_isrc_fsl[3]),
MADERA_RATE_ENUM("ISRC1 FSH", madera_isrc_fsh[0]),
MADERA_RATE_ENUM("ISRC2 FSH", madera_isrc_fsh[1]),
MADERA_RATE_ENUM("ISRC3 FSH", madera_isrc_fsh[2]),
MADERA_RATE_ENUM("ISRC4 FSH", madera_isrc_fsh[3]),
MADERA_RATE_ENUM("ASRC1 Rate 1", madera_asrc1_rate[0]),
MADERA_RATE_ENUM("ASRC1 Rate 2", madera_asrc1_rate[1]),
MADERA_RATE_ENUM("ASRC2 Rate 1", madera_asrc2_rate[0]),
MADERA_RATE_ENUM("ASRC2 Rate 2", madera_asrc2_rate[1]),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
WM_ADSP2_PRELOAD_SWITCH("DSP2", 2),
WM_ADSP2_PRELOAD_SWITCH("DSP3", 3),
WM_ADSP2_PRELOAD_SWITCH("DSP4", 4),
WM_ADSP2_PRELOAD_SWITCH("DSP5", 5),
WM_ADSP2_PRELOAD_SWITCH("DSP6", 6),
WM_ADSP2_PRELOAD_SWITCH("DSP7", 7),
MADERA_MIXER_CONTROLS("DSP1L", MADERA_DSP1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP1R", MADERA_DSP1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP2L", MADERA_DSP2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP2R", MADERA_DSP2RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP3L", MADERA_DSP3LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP3R", MADERA_DSP3RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP4L", MADERA_DSP4LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP4R", MADERA_DSP4RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP5L", MADERA_DSP5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP5R", MADERA_DSP5RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP6L", MADERA_DSP6LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP6R", MADERA_DSP6RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP7L", MADERA_DSP7LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("DSP7R", MADERA_DSP7RMIX_INPUT_1_SOURCE),
SOC_SINGLE_TLV("Noise Generator Volume", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, madera_noise_tlv),
MADERA_MIXER_CONTROLS("HPOUT1L", MADERA_OUT1LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT1R", MADERA_OUT1RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT2L", MADERA_OUT2LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT2R", MADERA_OUT2RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT3L", MADERA_OUT3LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("HPOUT3R", MADERA_OUT3RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKOUTL", MADERA_OUT4LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKOUTR", MADERA_OUT4RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1L", MADERA_OUT5LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT1R", MADERA_OUT5RMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT2L", MADERA_OUT6LMIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SPKDAT2R", MADERA_OUT6RMIX_INPUT_1_SOURCE),
SOC_SINGLE("HPOUT1 SC Protect Switch", MADERA_HP1_SHORT_CIRCUIT_CTRL,
MADERA_HP1_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT2 SC Protect Switch", MADERA_HP2_SHORT_CIRCUIT_CTRL,
MADERA_HP2_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("HPOUT3 SC Protect Switch", MADERA_HP3_SHORT_CIRCUIT_CTRL,
MADERA_HP3_SC_ENA_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT1 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_5L,
MADERA_OUT5_OSR_SHIFT, 1, 0),
SOC_SINGLE("SPKDAT2 High Performance Switch", MADERA_OUTPUT_PATH_CONFIG_6L,
MADERA_OUT6_OSR_SHIFT, 1, 0),
SOC_DOUBLE_R("HPOUT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("HPOUT3 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("Speaker Digital Switch", MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_DAC_DIGITAL_VOLUME_4R, MADERA_OUT4L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT1 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R("SPKDAT2 Digital Switch", MADERA_DAC_DIGITAL_VOLUME_6L,
MADERA_DAC_DIGITAL_VOLUME_6R, MADERA_OUT6L_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R, MADERA_OUT1L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R, MADERA_OUT2L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R, MADERA_OUT3L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("Speaker Digital Volume", MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_DAC_DIGITAL_VOLUME_4R, MADERA_OUT4L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R, MADERA_OUT5L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", MADERA_DAC_DIGITAL_VOLUME_6L,
MADERA_DAC_DIGITAL_VOLUME_6R, MADERA_OUT6L_VOL_SHIFT,
0xbf, 0, madera_digital_tlv),
SOC_DOUBLE("SPKDAT1 Switch", MADERA_PDM_SPK1_CTRL_1, MADERA_SPK1L_MUTE_SHIFT,
MADERA_SPK1R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE("SPKDAT2 Switch", MADERA_PDM_SPK2_CTRL_1, MADERA_SPK2L_MUTE_SHIFT,
MADERA_SPK2R_MUTE_SHIFT, 1, 1),
SOC_ENUM("Output Ramp Up", madera_out_vi_ramp),
SOC_ENUM("Output Ramp Down", madera_out_vd_ramp),
SOC_SINGLE("Noise Gate Switch", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_ENA_SHIFT, 1, 0),
SOC_SINGLE_TLV("Noise Gate Threshold Volume", MADERA_NOISE_GATE_CONTROL,
MADERA_NGATE_THR_SHIFT, 7, 1, madera_ng_tlv),
SOC_ENUM("Noise Gate Hold", madera_ng_hold),
CS47L85_NG_SRC("HPOUT1L", MADERA_NOISE_GATE_SELECT_1L),
CS47L85_NG_SRC("HPOUT1R", MADERA_NOISE_GATE_SELECT_1R),
CS47L85_NG_SRC("HPOUT2L", MADERA_NOISE_GATE_SELECT_2L),
CS47L85_NG_SRC("HPOUT2R", MADERA_NOISE_GATE_SELECT_2R),
CS47L85_NG_SRC("HPOUT3L", MADERA_NOISE_GATE_SELECT_3L),
CS47L85_NG_SRC("HPOUT3R", MADERA_NOISE_GATE_SELECT_3R),
CS47L85_NG_SRC("SPKOUTL", MADERA_NOISE_GATE_SELECT_4L),
CS47L85_NG_SRC("SPKOUTR", MADERA_NOISE_GATE_SELECT_4R),
CS47L85_NG_SRC("SPKDAT1L", MADERA_NOISE_GATE_SELECT_5L),
CS47L85_NG_SRC("SPKDAT1R", MADERA_NOISE_GATE_SELECT_5R),
CS47L85_NG_SRC("SPKDAT2L", MADERA_NOISE_GATE_SELECT_6L),
CS47L85_NG_SRC("SPKDAT2R", MADERA_NOISE_GATE_SELECT_6R),
MADERA_MIXER_CONTROLS("AIF1TX1", MADERA_AIF1TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX2", MADERA_AIF1TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX3", MADERA_AIF1TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX4", MADERA_AIF1TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX5", MADERA_AIF1TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX6", MADERA_AIF1TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX7", MADERA_AIF1TX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF1TX8", MADERA_AIF1TX8MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX1", MADERA_AIF2TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX2", MADERA_AIF2TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX3", MADERA_AIF2TX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX4", MADERA_AIF2TX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX5", MADERA_AIF2TX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX6", MADERA_AIF2TX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX7", MADERA_AIF2TX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF2TX8", MADERA_AIF2TX8MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX1", MADERA_AIF3TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF3TX2", MADERA_AIF3TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF4TX1", MADERA_AIF4TX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("AIF4TX2", MADERA_AIF4TX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX1", MADERA_SLIMTX1MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX2", MADERA_SLIMTX2MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX3", MADERA_SLIMTX3MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX4", MADERA_SLIMTX4MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX5", MADERA_SLIMTX5MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX6", MADERA_SLIMTX6MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX7", MADERA_SLIMTX7MIX_INPUT_1_SOURCE),
MADERA_MIXER_CONTROLS("SLIMTX8", MADERA_SLIMTX8MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX1", MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE),
MADERA_GAINMUX_CONTROLS("SPDIF1TX2", MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE),
WM_ADSP_FW_CONTROL("DSP1", 0),
WM_ADSP_FW_CONTROL("DSP2", 1),
WM_ADSP_FW_CONTROL("DSP3", 2),
WM_ADSP_FW_CONTROL("DSP4", 3),
WM_ADSP_FW_CONTROL("DSP5", 4),
WM_ADSP_FW_CONTROL("DSP6", 5),
WM_ADSP_FW_CONTROL("DSP7", 6),
};
MADERA_MIXER_ENUMS(EQ1, MADERA_EQ1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ2, MADERA_EQ2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ3, MADERA_EQ3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(EQ4, MADERA_EQ4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1L, MADERA_DRC1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC1R, MADERA_DRC1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2L, MADERA_DRC2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DRC2R, MADERA_DRC2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF1, MADERA_HPLP1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF2, MADERA_HPLP2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF3, MADERA_HPLP3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(LHPF4, MADERA_HPLP4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1L, MADERA_DSP1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP1R, MADERA_DSP1RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP1, MADERA_DSP1AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP2L, MADERA_DSP2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP2R, MADERA_DSP2RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP2, MADERA_DSP2AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP3L, MADERA_DSP3LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP3R, MADERA_DSP3RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP3, MADERA_DSP3AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP4L, MADERA_DSP4LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP4R, MADERA_DSP4RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP4, MADERA_DSP4AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP5L, MADERA_DSP5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP5R, MADERA_DSP5RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP5, MADERA_DSP5AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP6L, MADERA_DSP6LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP6R, MADERA_DSP6RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP6, MADERA_DSP6AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP7L, MADERA_DSP7LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(DSP7R, MADERA_DSP7RMIX_INPUT_1_SOURCE);
MADERA_DSP_AUX_ENUMS(DSP7, MADERA_DSP7AUX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM1, MADERA_PWM1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(PWM2, MADERA_PWM2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1L, MADERA_OUT1LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT1R, MADERA_OUT1RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT2L, MADERA_OUT2LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT2R, MADERA_OUT2RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT3L, MADERA_OUT3LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(OUT3R, MADERA_OUT3RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKOUTL, MADERA_OUT4LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKOUTR, MADERA_OUT4RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1L, MADERA_OUT5LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT1R, MADERA_OUT5RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT2L, MADERA_OUT6LMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SPKDAT2R, MADERA_OUT6RMIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX1, MADERA_AIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX2, MADERA_AIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX3, MADERA_AIF1TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX4, MADERA_AIF1TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX5, MADERA_AIF1TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX6, MADERA_AIF1TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX7, MADERA_AIF1TX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF1TX8, MADERA_AIF1TX8MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX1, MADERA_AIF2TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX2, MADERA_AIF2TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX3, MADERA_AIF2TX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX4, MADERA_AIF2TX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX5, MADERA_AIF2TX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX6, MADERA_AIF2TX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX7, MADERA_AIF2TX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF2TX8, MADERA_AIF2TX8MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX1, MADERA_AIF3TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF3TX2, MADERA_AIF3TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF4TX1, MADERA_AIF4TX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(AIF4TX2, MADERA_AIF4TX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX1, MADERA_SLIMTX1MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX2, MADERA_SLIMTX2MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX3, MADERA_SLIMTX3MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX4, MADERA_SLIMTX4MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX5, MADERA_SLIMTX5MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX6, MADERA_SLIMTX6MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX7, MADERA_SLIMTX7MIX_INPUT_1_SOURCE);
MADERA_MIXER_ENUMS(SLIMTX8, MADERA_SLIMTX8MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX1, MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(SPD1TX2, MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN1L, MADERA_ASRC1_1LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN1R, MADERA_ASRC1_1RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN2L, MADERA_ASRC1_2LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC1IN2R, MADERA_ASRC1_2RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN1L, MADERA_ASRC2_1LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN1R, MADERA_ASRC2_1RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN2L, MADERA_ASRC2_2LMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ASRC2IN2R, MADERA_ASRC2_2RMIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT1, MADERA_ISRC1INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT2, MADERA_ISRC1INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT3, MADERA_ISRC1INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1INT4, MADERA_ISRC1INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC1, MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC2, MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC3, MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC1DEC4, MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT1, MADERA_ISRC2INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT2, MADERA_ISRC2INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT3, MADERA_ISRC2INT3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2INT4, MADERA_ISRC2INT4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC1, MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC2, MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC3, MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC2DEC4, MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3INT1, MADERA_ISRC3INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3INT2, MADERA_ISRC3INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3DEC1, MADERA_ISRC3DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC3DEC2, MADERA_ISRC3DEC2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4INT1, MADERA_ISRC4INT1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4INT2, MADERA_ISRC4INT2MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4DEC1, MADERA_ISRC4DEC1MIX_INPUT_1_SOURCE);
MADERA_MUX_ENUMS(ISRC4DEC2, MADERA_ISRC4DEC2MIX_INPUT_1_SOURCE);
static const char * const cs47l85_aec_loopback_texts[] = {
"HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R",
"SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", "SPKDAT2L", "SPKDAT2R",
};
static const unsigned int cs47l85_aec_loopback_values[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
};
static const struct soc_enum cs47l85_aec1_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l85_aec_loopback_texts),
cs47l85_aec_loopback_texts,
cs47l85_aec_loopback_values);
static const struct soc_enum cs47l85_aec2_loopback =
SOC_VALUE_ENUM_SINGLE(MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_SRC_SHIFT, 0xf,
ARRAY_SIZE(cs47l85_aec_loopback_texts),
cs47l85_aec_loopback_texts,
cs47l85_aec_loopback_values);
static const struct snd_kcontrol_new cs47l85_aec_loopback_mux[] = {
SOC_DAPM_ENUM("AEC1 Loopback", cs47l85_aec1_loopback),
SOC_DAPM_ENUM("AEC2 Loopback", cs47l85_aec2_loopback),
};
static const struct snd_kcontrol_new cs47l85_anc_input_mux[] = {
SOC_DAPM_ENUM("RXANCL Input", madera_anc_input_src[0]),
SOC_DAPM_ENUM("RXANCL Channel", madera_anc_input_src[1]),
SOC_DAPM_ENUM("RXANCR Input", madera_anc_input_src[2]),
SOC_DAPM_ENUM("RXANCR Channel", madera_anc_input_src[3]),
};
static const struct snd_kcontrol_new cs47l85_anc_ng_mux =
SOC_DAPM_ENUM("RXANC NG Source", madera_anc_ng_enum);
static const struct snd_kcontrol_new cs47l85_output_anc_src[] = {
SOC_DAPM_ENUM("HPOUT1L ANC Source", madera_output_anc_src[0]),
SOC_DAPM_ENUM("HPOUT1R ANC Source", madera_output_anc_src[1]),
SOC_DAPM_ENUM("HPOUT2L ANC Source", madera_output_anc_src[2]),
SOC_DAPM_ENUM("HPOUT2R ANC Source", madera_output_anc_src[3]),
SOC_DAPM_ENUM("HPOUT3L ANC Source", madera_output_anc_src[4]),
SOC_DAPM_ENUM("HPOUT3R ANC Source", madera_output_anc_src[5]),
SOC_DAPM_ENUM("SPKOUTL ANC Source", madera_output_anc_src[6]),
SOC_DAPM_ENUM("SPKOUTR ANC Source", madera_output_anc_src[7]),
SOC_DAPM_ENUM("SPKDAT1L ANC Source", madera_output_anc_src[8]),
SOC_DAPM_ENUM("SPKDAT1R ANC Source", madera_output_anc_src[9]),
SOC_DAPM_ENUM("SPKDAT2L ANC Source", madera_output_anc_src[10]),
SOC_DAPM_ENUM("SPKDAT2R ANC Source", madera_output_anc_src[11]),
};
static const struct snd_soc_dapm_widget cs47l85_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("SYSCLK", MADERA_SYSTEM_CLOCK_1, MADERA_SYSCLK_ENA_SHIFT,
0, madera_sysclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASYNCCLK", MADERA_ASYNC_CLOCK_1,
MADERA_ASYNC_CLK_ENA_SHIFT, 0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OPCLK", MADERA_OUTPUT_SYSTEM_CLOCK,
MADERA_OPCLK_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", MADERA_OUTPUT_ASYNC_CLOCK,
MADERA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSPCLK", MADERA_DSP_CLOCK_1, MADERA_DSP_CLK_ENA_SHIFT,
0, madera_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD4", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD1", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD2", 20, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", MADERA_MIC_BIAS_CTRL_1,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", MADERA_MIC_BIAS_CTRL_2,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", MADERA_MIC_BIAS_CTRL_3,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS4", MADERA_MIC_BIAS_CTRL_4,
MADERA_MICB1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("FXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_FX, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ASRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ASRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ASRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC3CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("ISRC4CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_ISRC4, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("OUTCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_OUT, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SPDCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SPD, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP3CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP4CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP4, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP5CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP5, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP6CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP6, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DSP7CLK", SND_SOC_NOPM,
MADERA_DOM_GRP_DSP7, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF1TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF1, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF2TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF2, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF3TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF3, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("AIF4TXCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_AIF4, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SLIMBUSCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_SLIMBUS, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PWMCLK", SND_SOC_NOPM,
MADERA_DOM_GRP_PWM, 0,
madera_domain_clk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM,
MADERA_EXT_NG_SEL_SET_SHIFT, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM,
MADERA_CLK_NG_ENA_SET_SHIFT, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SIGGEN("TONE"),
SND_SOC_DAPM_SIGGEN("NOISE"),
SND_SOC_DAPM_INPUT("IN1ALN"),
SND_SOC_DAPM_INPUT("IN1ALP"),
SND_SOC_DAPM_INPUT("IN1BN"),
SND_SOC_DAPM_INPUT("IN1BP"),
SND_SOC_DAPM_INPUT("IN1RN"),
SND_SOC_DAPM_INPUT("IN1RP"),
SND_SOC_DAPM_INPUT("IN2ALN"),
SND_SOC_DAPM_INPUT("IN2ALP"),
SND_SOC_DAPM_INPUT("IN2ARN"),
SND_SOC_DAPM_INPUT("IN2ARP"),
SND_SOC_DAPM_INPUT("IN2BLN"),
SND_SOC_DAPM_INPUT("IN2BLP"),
SND_SOC_DAPM_INPUT("IN2BRN"),
SND_SOC_DAPM_INPUT("IN2BRP"),
SND_SOC_DAPM_INPUT("IN3LN"),
SND_SOC_DAPM_INPUT("IN3LP"),
SND_SOC_DAPM_INPUT("IN3RN"),
SND_SOC_DAPM_INPUT("IN3RP"),
SND_SOC_DAPM_INPUT("DMICCLK4"),
SND_SOC_DAPM_INPUT("DMICDAT4"),
SND_SOC_DAPM_INPUT("DMICCLK5"),
SND_SOC_DAPM_INPUT("DMICDAT5"),
SND_SOC_DAPM_INPUT("DMICCLK6"),
SND_SOC_DAPM_INPUT("DMICDAT6"),
SND_SOC_DAPM_MUX("IN1L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[0]),
SND_SOC_DAPM_MUX("IN2L Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[2]),
SND_SOC_DAPM_MUX("IN2R Analog Mux", SND_SOC_NOPM, 0, 0, &madera_inmux[3]),
SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[0]),
SND_SOC_DAPM_MUX("IN2L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_MUX("IN2R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[1]),
SND_SOC_DAPM_MUX("IN3L Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[2]),
SND_SOC_DAPM_MUX("IN3R Mode", SND_SOC_NOPM, 0, 0, &madera_inmode[2]),
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
SND_SOC_DAPM_OUTPUT("DSP Trigger Out"),
SND_SOC_DAPM_PGA("PWM1 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM1_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("PWM2 Driver", MADERA_PWM_DRIVE_1, MADERA_PWM2_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0,
&cs47l85_anc_input_mux[0]),
SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0,
&cs47l85_anc_input_mux[0]),
SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0,
&cs47l85_anc_input_mux[1]),
SND_SOC_DAPM_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &cs47l85_anc_ng_mux),
SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0,
&cs47l85_anc_input_mux[2]),
SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0,
&cs47l85_anc_input_mux[2]),
SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0,
&cs47l85_anc_input_mux[3]),
SND_SOC_DAPM_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &cs47l85_anc_ng_mux),
SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, MADERA_CLK_L_ENA_SET_SHIFT,
0, NULL, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, MADERA_CLK_R_ENA_SET_SHIFT,
0, NULL, 0, madera_anc_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[0]),
SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[1]),
SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[2]),
SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[3]),
SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[4]),
SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[5]),
SND_SOC_DAPM_MUX("SPKOUTL ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[6]),
SND_SOC_DAPM_MUX("SPKOUTR ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[7]),
SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[8]),
SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[9]),
SND_SOC_DAPM_MUX("SPKDAT2L ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[10]),
SND_SOC_DAPM_MUX("SPKDAT2R ANC Source", SND_SOC_NOPM, 0, 0,
&cs47l85_output_anc_src[11]),
SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 1,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 2,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 3,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 4,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 5,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 6,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 7,
MADERA_AIF1_TX_ENABLES, MADERA_AIF1TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 1,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 2,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 3,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 4,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 5,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 6,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 7,
MADERA_AIF2_TX_ENABLES, MADERA_AIF2TX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 1,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 2,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 3,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 4,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 5,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 6,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 7,
MADERA_SLIMBUS_TX_CHANNEL_ENABLE,
MADERA_SLIMTX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 1,
MADERA_AIF3_TX_ENABLES, MADERA_AIF3TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF4TX1", NULL, 0,
MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("AIF4TX2", NULL, 1,
MADERA_AIF4_TX_ENABLES, MADERA_AIF4TX2_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
MADERA_OUT1L_ENA_SHIFT, 0, NULL, 0, cs47l85_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM,
MADERA_OUT1R_ENA_SHIFT, 0, NULL, 0, cs47l85_hp_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT2L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT2R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT2R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT3L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT3R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT3R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
MADERA_OUT4L_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
MADERA_OUT4R_ENA_SHIFT, 0, NULL, 0, madera_spk_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("OUT5L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT5R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT5R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT6L", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT6L_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("OUT6R", MADERA_OUTPUT_ENABLES_1,
MADERA_OUT6R_ENA_SHIFT, 0, NULL, 0, madera_out_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPD1TX1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPD1TX2", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_VAL2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPD1", MADERA_SPD1_TX_CONTROL,
MADERA_SPD1_ENA_SHIFT, 0, NULL, 0),
/*
* Input mux widgets arranged in order of sources in MADERA_MIXER_INPUT_ROUTES
* to take advantage of cache lookup in DAPM
*/
SND_SOC_DAPM_PGA("Noise Generator", MADERA_COMFORT_NOISE_GENERATOR,
MADERA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 1", MADERA_TONE_GENERATOR_1,
MADERA_TONE1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("Tone Generator 2", MADERA_TONE_GENERATOR_1,
MADERA_TONE2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("HAPTICS"),
SND_SOC_DAPM_MUX("AEC1 Loopback", MADERA_DAC_AEC_CONTROL_1,
MADERA_AEC1_LOOPBACK_ENA_SHIFT, 0,
&cs47l85_aec_loopback_mux[0]),
SND_SOC_DAPM_MUX("AEC2 Loopback", MADERA_DAC_AEC_CONTROL_2,
MADERA_AEC2_LOOPBACK_ENA_SHIFT, 0,
&cs47l85_aec_loopback_mux[1]),
SND_SOC_DAPM_PGA_E("IN1L", MADERA_INPUT_ENABLES, MADERA_IN1L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN1R", MADERA_INPUT_ENABLES, MADERA_IN1R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2L", MADERA_INPUT_ENABLES, MADERA_IN2L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN2R", MADERA_INPUT_ENABLES, MADERA_IN2R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3L", MADERA_INPUT_ENABLES, MADERA_IN3L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN3R", MADERA_INPUT_ENABLES, MADERA_IN3R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4L", MADERA_INPUT_ENABLES, MADERA_IN4L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN4R", MADERA_INPUT_ENABLES, MADERA_IN4R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN5L", MADERA_INPUT_ENABLES, MADERA_IN5L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN5R", MADERA_INPUT_ENABLES, MADERA_IN5R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN6L", MADERA_INPUT_ENABLES, MADERA_IN6L_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("IN6R", MADERA_INPUT_ENABLES, MADERA_IN6R_ENA_SHIFT,
0, NULL, 0, madera_in_ev,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 1,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 2,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 3,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 4,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 5,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 6,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 7,
MADERA_AIF1_RX_ENABLES, MADERA_AIF1RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 1,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 2,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 3,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 4,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 5,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 6,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 7,
MADERA_AIF2_RX_ENABLES, MADERA_AIF2RX8_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 1,
MADERA_AIF3_RX_ENABLES, MADERA_AIF3RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF4RX1", NULL, 0,
MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("AIF4RX2", NULL, 1,
MADERA_AIF4_RX_ENABLES, MADERA_AIF4RX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX1_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 1,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX2_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 2,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX3_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 3,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX4_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 4,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX5_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 5,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX6_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 6,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX7_ENA_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 7,
MADERA_SLIMBUS_RX_CHANNEL_ENABLE,
MADERA_SLIMRX8_ENA_SHIFT, 0),
SND_SOC_DAPM_PGA("EQ1", MADERA_EQ1_1, MADERA_EQ1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ2", MADERA_EQ2_1, MADERA_EQ2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ3", MADERA_EQ3_1, MADERA_EQ3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("EQ4", MADERA_EQ4_1, MADERA_EQ4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DRC1L", MADERA_DRC1_CTRL1, MADERA_DRC1L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC1R", MADERA_DRC1_CTRL1, MADERA_DRC1R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2L", MADERA_DRC2_CTRL1, MADERA_DRC2L_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("DRC2R", MADERA_DRC2_CTRL1, MADERA_DRC2R_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF1", MADERA_HPLPF1_1, MADERA_LHPF1_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF2", MADERA_HPLPF2_1, MADERA_LHPF2_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF3", MADERA_HPLPF3_1, MADERA_LHPF3_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LHPF4", MADERA_HPLPF4_1, MADERA_LHPF4_ENA_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN1L", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN1L_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN1R", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN1R_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN2L", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN2L_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC1IN2R", MADERA_ASRC1_ENABLE, MADERA_ASRC1_IN2R_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN1L", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN1L_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN1R", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN1R_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN2L", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN2L_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ASRC2IN2R", MADERA_ASRC2_ENABLE, MADERA_ASRC2_IN2R_ENA_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1DEC4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT1", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT2", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT3", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC1INT4", MADERA_ISRC_1_CTRL_3,
MADERA_ISRC1_INT4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2DEC4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_DEC4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT1", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT2", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT3", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC2INT4", MADERA_ISRC_2_CTRL_3,
MADERA_ISRC2_INT4_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC1", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3DEC2", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT1", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC3INT2", MADERA_ISRC_3_CTRL_3,
MADERA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4DEC1", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_DEC1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4DEC2", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_DEC2_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4INT1", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_INT1_ENA_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("ISRC4INT2", MADERA_ISRC_4_CTRL_3,
MADERA_ISRC4_INT2_ENA_SHIFT, 0, NULL, 0),
WM_ADSP2("DSP1", 0, cs47l85_adsp_power_ev),
WM_ADSP2("DSP2", 1, cs47l85_adsp_power_ev),
WM_ADSP2("DSP3", 2, cs47l85_adsp_power_ev),
WM_ADSP2("DSP4", 3, cs47l85_adsp_power_ev),
WM_ADSP2("DSP5", 4, cs47l85_adsp_power_ev),
WM_ADSP2("DSP6", 5, cs47l85_adsp_power_ev),
WM_ADSP2("DSP7", 6, cs47l85_adsp_power_ev),
/* End of ordered input mux widgets */
MADERA_MIXER_WIDGETS(EQ1, "EQ1"),
MADERA_MIXER_WIDGETS(EQ2, "EQ2"),
MADERA_MIXER_WIDGETS(EQ3, "EQ3"),
MADERA_MIXER_WIDGETS(EQ4, "EQ4"),
MADERA_MIXER_WIDGETS(DRC1L, "DRC1L"),
MADERA_MIXER_WIDGETS(DRC1R, "DRC1R"),
MADERA_MIXER_WIDGETS(DRC2L, "DRC2L"),
MADERA_MIXER_WIDGETS(DRC2R, "DRC2R"),
SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[0]),
SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0,
&madera_drc_activity_output_mux[1]),
MADERA_MIXER_WIDGETS(LHPF1, "LHPF1"),
MADERA_MIXER_WIDGETS(LHPF2, "LHPF2"),
MADERA_MIXER_WIDGETS(LHPF3, "LHPF3"),
MADERA_MIXER_WIDGETS(LHPF4, "LHPF4"),
MADERA_MIXER_WIDGETS(PWM1, "PWM1"),
MADERA_MIXER_WIDGETS(PWM2, "PWM2"),
MADERA_MIXER_WIDGETS(OUT1L, "HPOUT1L"),
MADERA_MIXER_WIDGETS(OUT1R, "HPOUT1R"),
MADERA_MIXER_WIDGETS(OUT2L, "HPOUT2L"),
MADERA_MIXER_WIDGETS(OUT2R, "HPOUT2R"),
MADERA_MIXER_WIDGETS(OUT3L, "HPOUT3L"),
MADERA_MIXER_WIDGETS(OUT3R, "HPOUT3R"),
MADERA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
MADERA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
MADERA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
MADERA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
MADERA_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
MADERA_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
MADERA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
MADERA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
MADERA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
MADERA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
MADERA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
MADERA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
MADERA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
MADERA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
MADERA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
MADERA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
MADERA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"),
MADERA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"),
MADERA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"),
MADERA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"),
MADERA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"),
MADERA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"),
MADERA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
MADERA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
MADERA_MIXER_WIDGETS(AIF4TX1, "AIF4TX1"),
MADERA_MIXER_WIDGETS(AIF4TX2, "AIF4TX2"),
MADERA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"),
MADERA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"),
MADERA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"),
MADERA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"),
MADERA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"),
MADERA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"),
MADERA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"),
MADERA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"),
MADERA_MUX_WIDGETS(SPD1TX1, "SPDIF1TX1"),
MADERA_MUX_WIDGETS(SPD1TX2, "SPDIF1TX2"),
MADERA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"),
MADERA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"),
MADERA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"),
MADERA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"),
MADERA_MUX_WIDGETS(ASRC2IN1L, "ASRC2IN1L"),
MADERA_MUX_WIDGETS(ASRC2IN1R, "ASRC2IN1R"),
MADERA_MUX_WIDGETS(ASRC2IN2L, "ASRC2IN2L"),
MADERA_MUX_WIDGETS(ASRC2IN2R, "ASRC2IN2R"),
MADERA_DSP_WIDGETS(DSP1, "DSP1"),
MADERA_DSP_WIDGETS(DSP2, "DSP2"),
MADERA_DSP_WIDGETS(DSP3, "DSP3"),
MADERA_DSP_WIDGETS(DSP4, "DSP4"),
MADERA_DSP_WIDGETS(DSP5, "DSP5"),
MADERA_DSP_WIDGETS(DSP6, "DSP6"),
MADERA_DSP_WIDGETS(DSP7, "DSP7"),
SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[0]),
SND_SOC_DAPM_SWITCH("DSP2 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[1]),
SND_SOC_DAPM_SWITCH("DSP3 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[2]),
SND_SOC_DAPM_SWITCH("DSP4 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[3]),
SND_SOC_DAPM_SWITCH("DSP5 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[4]),
SND_SOC_DAPM_SWITCH("DSP6 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[5]),
SND_SOC_DAPM_SWITCH("DSP7 Trigger Output", SND_SOC_NOPM, 0, 0,
&madera_dsp_trigger_output_mux[6]),
MADERA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
MADERA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
MADERA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"),
MADERA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"),
MADERA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
MADERA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
MADERA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"),
MADERA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"),
MADERA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
MADERA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
MADERA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"),
MADERA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"),
MADERA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
MADERA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
MADERA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"),
MADERA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"),
MADERA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"),
MADERA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"),
MADERA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"),
MADERA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"),
MADERA_MUX_WIDGETS(ISRC4DEC1, "ISRC4DEC1"),
MADERA_MUX_WIDGETS(ISRC4DEC2, "ISRC4DEC2"),
MADERA_MUX_WIDGETS(ISRC4INT1, "ISRC4INT1"),
MADERA_MUX_WIDGETS(ISRC4INT2, "ISRC4INT2"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2L"),
SND_SOC_DAPM_OUTPUT("HPOUT2R"),
SND_SOC_DAPM_OUTPUT("HPOUT3L"),
SND_SOC_DAPM_OUTPUT("HPOUT3R"),
SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
SND_SOC_DAPM_OUTPUT("SPKDAT1L"),
SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
SND_SOC_DAPM_OUTPUT("SPKDAT2L"),
SND_SOC_DAPM_OUTPUT("SPKDAT2R"),
SND_SOC_DAPM_OUTPUT("SPDIF1"),
SND_SOC_DAPM_OUTPUT("MICSUPP"),
};
#define MADERA_MIXER_INPUT_ROUTES(name) \
{ name, "Noise Generator", "Noise Generator" }, \
{ name, "Tone Generator 1", "Tone Generator 1" }, \
{ name, "Tone Generator 2", "Tone Generator 2" }, \
{ name, "Haptics", "HAPTICS" }, \
{ name, "AEC1", "AEC1 Loopback" }, \
{ name, "AEC2", "AEC2 Loopback" }, \
{ name, "IN1L", "IN1L" }, \
{ name, "IN1R", "IN1R" }, \
{ name, "IN2L", "IN2L" }, \
{ name, "IN2R", "IN2R" }, \
{ name, "IN3L", "IN3L" }, \
{ name, "IN3R", "IN3R" }, \
{ name, "IN4L", "IN4L" }, \
{ name, "IN4R", "IN4R" }, \
{ name, "IN5L", "IN5L" }, \
{ name, "IN5R", "IN5R" }, \
{ name, "IN6L", "IN6L" }, \
{ name, "IN6R", "IN6R" }, \
{ name, "AIF1RX1", "AIF1RX1" }, \
{ name, "AIF1RX2", "AIF1RX2" }, \
{ name, "AIF1RX3", "AIF1RX3" }, \
{ name, "AIF1RX4", "AIF1RX4" }, \
{ name, "AIF1RX5", "AIF1RX5" }, \
{ name, "AIF1RX6", "AIF1RX6" }, \
{ name, "AIF1RX7", "AIF1RX7" }, \
{ name, "AIF1RX8", "AIF1RX8" }, \
{ name, "AIF2RX1", "AIF2RX1" }, \
{ name, "AIF2RX2", "AIF2RX2" }, \
{ name, "AIF2RX3", "AIF2RX3" }, \
{ name, "AIF2RX4", "AIF2RX4" }, \
{ name, "AIF2RX5", "AIF2RX5" }, \
{ name, "AIF2RX6", "AIF2RX6" }, \
{ name, "AIF2RX7", "AIF2RX7" }, \
{ name, "AIF2RX8", "AIF2RX8" }, \
{ name, "AIF3RX1", "AIF3RX1" }, \
{ name, "AIF3RX2", "AIF3RX2" }, \
{ name, "AIF4RX1", "AIF4RX1" }, \
{ name, "AIF4RX2", "AIF4RX2" }, \
{ name, "SLIMRX1", "SLIMRX1" }, \
{ name, "SLIMRX2", "SLIMRX2" }, \
{ name, "SLIMRX3", "SLIMRX3" }, \
{ name, "SLIMRX4", "SLIMRX4" }, \
{ name, "SLIMRX5", "SLIMRX5" }, \
{ name, "SLIMRX6", "SLIMRX6" }, \
{ name, "SLIMRX7", "SLIMRX7" }, \
{ name, "SLIMRX8", "SLIMRX8" }, \
{ name, "EQ1", "EQ1" }, \
{ name, "EQ2", "EQ2" }, \
{ name, "EQ3", "EQ3" }, \
{ name, "EQ4", "EQ4" }, \
{ name, "DRC1L", "DRC1L" }, \
{ name, "DRC1R", "DRC1R" }, \
{ name, "DRC2L", "DRC2L" }, \
{ name, "DRC2R", "DRC2R" }, \
{ name, "LHPF1", "LHPF1" }, \
{ name, "LHPF2", "LHPF2" }, \
{ name, "LHPF3", "LHPF3" }, \
{ name, "LHPF4", "LHPF4" }, \
{ name, "ASRC1IN1L", "ASRC1IN1L" }, \
{ name, "ASRC1IN1R", "ASRC1IN1R" }, \
{ name, "ASRC1IN2L", "ASRC1IN2L" }, \
{ name, "ASRC1IN2R", "ASRC1IN2R" }, \
{ name, "ASRC2IN1L", "ASRC2IN1L" }, \
{ name, "ASRC2IN1R", "ASRC2IN1R" }, \
{ name, "ASRC2IN2L", "ASRC2IN2L" }, \
{ name, "ASRC2IN2R", "ASRC2IN2R" }, \
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
{ name, "ISRC1INT1", "ISRC1INT1" }, \
{ name, "ISRC1INT2", "ISRC1INT2" }, \
{ name, "ISRC1INT3", "ISRC1INT3" }, \
{ name, "ISRC1INT4", "ISRC1INT4" }, \
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
{ name, "ISRC2DEC3", "ISRC2DEC3" }, \
{ name, "ISRC2DEC4", "ISRC2DEC4" }, \
{ name, "ISRC2INT1", "ISRC2INT1" }, \
{ name, "ISRC2INT2", "ISRC2INT2" }, \
{ name, "ISRC2INT3", "ISRC2INT3" }, \
{ name, "ISRC2INT4", "ISRC2INT4" }, \
{ name, "ISRC3DEC1", "ISRC3DEC1" }, \
{ name, "ISRC3DEC2", "ISRC3DEC2" }, \
{ name, "ISRC3INT1", "ISRC3INT1" }, \
{ name, "ISRC3INT2", "ISRC3INT2" }, \
{ name, "ISRC4DEC1", "ISRC4DEC1" }, \
{ name, "ISRC4DEC2", "ISRC4DEC2" }, \
{ name, "ISRC4INT1", "ISRC4INT1" }, \
{ name, "ISRC4INT2", "ISRC4INT2" }, \
{ name, "DSP1.1", "DSP1" }, \
{ name, "DSP1.2", "DSP1" }, \
{ name, "DSP1.3", "DSP1" }, \
{ name, "DSP1.4", "DSP1" }, \
{ name, "DSP1.5", "DSP1" }, \
{ name, "DSP1.6", "DSP1" }, \
{ name, "DSP2.1", "DSP2" }, \
{ name, "DSP2.2", "DSP2" }, \
{ name, "DSP2.3", "DSP2" }, \
{ name, "DSP2.4", "DSP2" }, \
{ name, "DSP2.5", "DSP2" }, \
{ name, "DSP2.6", "DSP2" }, \
{ name, "DSP3.1", "DSP3" }, \
{ name, "DSP3.2", "DSP3" }, \
{ name, "DSP3.3", "DSP3" }, \
{ name, "DSP3.4", "DSP3" }, \
{ name, "DSP3.5", "DSP3" }, \
{ name, "DSP3.6", "DSP3" }, \
{ name, "DSP4.1", "DSP4" }, \
{ name, "DSP4.2", "DSP4" }, \
{ name, "DSP4.3", "DSP4" }, \
{ name, "DSP4.4", "DSP4" }, \
{ name, "DSP4.5", "DSP4" }, \
{ name, "DSP4.6", "DSP4" }, \
{ name, "DSP5.1", "DSP5" }, \
{ name, "DSP5.2", "DSP5" }, \
{ name, "DSP5.3", "DSP5" }, \
{ name, "DSP5.4", "DSP5" }, \
{ name, "DSP5.5", "DSP5" }, \
{ name, "DSP5.6", "DSP5" }, \
{ name, "DSP6.1", "DSP6" }, \
{ name, "DSP6.2", "DSP6" }, \
{ name, "DSP6.3", "DSP6" }, \
{ name, "DSP6.4", "DSP6" }, \
{ name, "DSP6.5", "DSP6" }, \
{ name, "DSP6.6", "DSP6" }, \
{ name, "DSP7.1", "DSP7" }, \
{ name, "DSP7.2", "DSP7" }, \
{ name, "DSP7.3", "DSP7" }, \
{ name, "DSP7.4", "DSP7" }, \
{ name, "DSP7.5", "DSP7" }, \
{ name, "DSP7.6", "DSP7" }
static const struct snd_soc_dapm_route cs47l85_dapm_routes[] = {
/* Internal clock domains */
{ "EQ1", NULL, "FXCLK" },
{ "EQ2", NULL, "FXCLK" },
{ "EQ3", NULL, "FXCLK" },
{ "EQ4", NULL, "FXCLK" },
{ "DRC1L", NULL, "FXCLK" },
{ "DRC1R", NULL, "FXCLK" },
{ "DRC2L", NULL, "FXCLK" },
{ "DRC2R", NULL, "FXCLK" },
{ "LHPF1", NULL, "FXCLK" },
{ "LHPF2", NULL, "FXCLK" },
{ "LHPF3", NULL, "FXCLK" },
{ "LHPF4", NULL, "FXCLK" },
{ "PWM1 Mixer", NULL, "PWMCLK" },
{ "PWM2 Mixer", NULL, "PWMCLK" },
{ "OUT1L", NULL, "OUTCLK" },
{ "OUT1R", NULL, "OUTCLK" },
{ "OUT2L", NULL, "OUTCLK" },
{ "OUT2R", NULL, "OUTCLK" },
{ "OUT3L", NULL, "OUTCLK" },
{ "OUT3R", NULL, "OUTCLK" },
{ "OUT4L", NULL, "OUTCLK" },
{ "OUT4R", NULL, "OUTCLK" },
{ "OUT5L", NULL, "OUTCLK" },
{ "OUT5R", NULL, "OUTCLK" },
{ "OUT6L", NULL, "OUTCLK" },
{ "OUT6R", NULL, "OUTCLK" },
{ "AIF1TX1", NULL, "AIF1TXCLK" },
{ "AIF1TX2", NULL, "AIF1TXCLK" },
{ "AIF1TX3", NULL, "AIF1TXCLK" },
{ "AIF1TX4", NULL, "AIF1TXCLK" },
{ "AIF1TX5", NULL, "AIF1TXCLK" },
{ "AIF1TX6", NULL, "AIF1TXCLK" },
{ "AIF1TX7", NULL, "AIF1TXCLK" },
{ "AIF1TX8", NULL, "AIF1TXCLK" },
{ "AIF2TX1", NULL, "AIF2TXCLK" },
{ "AIF2TX2", NULL, "AIF2TXCLK" },
{ "AIF2TX3", NULL, "AIF2TXCLK" },
{ "AIF2TX4", NULL, "AIF2TXCLK" },
{ "AIF2TX5", NULL, "AIF2TXCLK" },
{ "AIF2TX6", NULL, "AIF2TXCLK" },
{ "AIF2TX7", NULL, "AIF2TXCLK" },
{ "AIF2TX8", NULL, "AIF2TXCLK" },
{ "AIF3TX1", NULL, "AIF3TXCLK" },
{ "AIF3TX2", NULL, "AIF3TXCLK" },
{ "AIF4TX1", NULL, "AIF4TXCLK" },
{ "AIF4TX2", NULL, "AIF4TXCLK" },
{ "SLIMTX1", NULL, "SLIMBUSCLK" },
{ "SLIMTX2", NULL, "SLIMBUSCLK" },
{ "SLIMTX3", NULL, "SLIMBUSCLK" },
{ "SLIMTX4", NULL, "SLIMBUSCLK" },
{ "SLIMTX5", NULL, "SLIMBUSCLK" },
{ "SLIMTX6", NULL, "SLIMBUSCLK" },
{ "SLIMTX7", NULL, "SLIMBUSCLK" },
{ "SLIMTX8", NULL, "SLIMBUSCLK" },
{ "SPD1TX1", NULL, "SPDCLK" },
{ "SPD1TX2", NULL, "SPDCLK" },
{ "DSP1", NULL, "DSP1CLK" },
{ "DSP2", NULL, "DSP2CLK" },
{ "DSP3", NULL, "DSP3CLK" },
{ "DSP4", NULL, "DSP4CLK" },
{ "DSP5", NULL, "DSP5CLK" },
{ "DSP6", NULL, "DSP6CLK" },
{ "DSP7", NULL, "DSP7CLK" },
{ "ISRC1DEC1", NULL, "ISRC1CLK" },
{ "ISRC1DEC2", NULL, "ISRC1CLK" },
{ "ISRC1DEC3", NULL, "ISRC1CLK" },
{ "ISRC1DEC4", NULL, "ISRC1CLK" },
{ "ISRC1INT1", NULL, "ISRC1CLK" },
{ "ISRC1INT2", NULL, "ISRC1CLK" },
{ "ISRC1INT3", NULL, "ISRC1CLK" },
{ "ISRC1INT4", NULL, "ISRC1CLK" },
{ "ISRC2DEC1", NULL, "ISRC2CLK" },
{ "ISRC2DEC2", NULL, "ISRC2CLK" },
{ "ISRC2DEC3", NULL, "ISRC2CLK" },
{ "ISRC2DEC4", NULL, "ISRC2CLK" },
{ "ISRC2INT1", NULL, "ISRC2CLK" },
{ "ISRC2INT2", NULL, "ISRC2CLK" },
{ "ISRC2INT3", NULL, "ISRC2CLK" },
{ "ISRC2INT4", NULL, "ISRC2CLK" },
{ "ISRC3DEC1", NULL, "ISRC3CLK" },
{ "ISRC3DEC2", NULL, "ISRC3CLK" },
{ "ISRC3INT1", NULL, "ISRC3CLK" },
{ "ISRC3INT2", NULL, "ISRC3CLK" },
{ "ISRC4DEC1", NULL, "ISRC4CLK" },
{ "ISRC4DEC2", NULL, "ISRC4CLK" },
{ "ISRC4INT1", NULL, "ISRC4CLK" },
{ "ISRC4INT2", NULL, "ISRC4CLK" },
{ "ASRC1IN1L", NULL, "ASRC1CLK" },
{ "ASRC1IN1R", NULL, "ASRC1CLK" },
{ "ASRC1IN2L", NULL, "ASRC1CLK" },
{ "ASRC1IN2R", NULL, "ASRC1CLK" },
{ "ASRC2IN1L", NULL, "ASRC2CLK" },
{ "ASRC2IN1R", NULL, "ASRC2CLK" },
{ "ASRC2IN2L", NULL, "ASRC2CLK" },
{ "ASRC2IN2R", NULL, "ASRC2CLK" },
{ "AIF2 Capture", NULL, "DBVDD2" },
{ "AIF2 Playback", NULL, "DBVDD2" },
{ "AIF3 Capture", NULL, "DBVDD3" },
{ "AIF3 Playback", NULL, "DBVDD3" },
{ "AIF4 Capture", NULL, "DBVDD3" },
{ "AIF4 Playback", NULL, "DBVDD3" },
{ "OUT1L", NULL, "CPVDD1" },
{ "OUT1L", NULL, "CPVDD2" },
{ "OUT1R", NULL, "CPVDD1" },
{ "OUT1R", NULL, "CPVDD2" },
{ "OUT2L", NULL, "CPVDD1" },
{ "OUT2L", NULL, "CPVDD2" },
{ "OUT2R", NULL, "CPVDD1" },
{ "OUT2R", NULL, "CPVDD2" },
{ "OUT3L", NULL, "CPVDD1" },
{ "OUT3L", NULL, "CPVDD2" },
{ "OUT3R", NULL, "CPVDD1" },
{ "OUT3R", NULL, "CPVDD2" },
{ "OUT4L", NULL, "SPKVDDL" },
{ "OUT4R", NULL, "SPKVDDR" },
{ "OUT1L", NULL, "SYSCLK" },
{ "OUT1R", NULL, "SYSCLK" },
{ "OUT2L", NULL, "SYSCLK" },
{ "OUT2R", NULL, "SYSCLK" },
{ "OUT3L", NULL, "SYSCLK" },
{ "OUT3R", NULL, "SYSCLK" },
{ "OUT4L", NULL, "SYSCLK" },
{ "OUT4R", NULL, "SYSCLK" },
{ "OUT5L", NULL, "SYSCLK" },
{ "OUT5R", NULL, "SYSCLK" },
{ "OUT6L", NULL, "SYSCLK" },
{ "OUT6R", NULL, "SYSCLK" },
{ "SPD1", NULL, "SYSCLK" },
{ "SPD1", NULL, "SPD1TX1" },
{ "SPD1", NULL, "SPD1TX2" },
{ "IN1L", NULL, "SYSCLK" },
{ "IN1R", NULL, "SYSCLK" },
{ "IN2L", NULL, "SYSCLK" },
{ "IN2R", NULL, "SYSCLK" },
{ "IN3L", NULL, "SYSCLK" },
{ "IN3R", NULL, "SYSCLK" },
{ "IN4L", NULL, "SYSCLK" },
{ "IN4R", NULL, "SYSCLK" },
{ "IN5L", NULL, "SYSCLK" },
{ "IN5R", NULL, "SYSCLK" },
{ "IN6L", NULL, "SYSCLK" },
{ "IN6R", NULL, "SYSCLK" },
{ "IN4L", NULL, "DBVDD4" },
{ "IN4R", NULL, "DBVDD4" },
{ "IN5L", NULL, "DBVDD4" },
{ "IN5R", NULL, "DBVDD4" },
{ "IN6L", NULL, "DBVDD4" },
{ "IN6R", NULL, "DBVDD4" },
{ "ASRC1IN1L", NULL, "SYSCLK" },
{ "ASRC1IN1R", NULL, "SYSCLK" },
{ "ASRC1IN2L", NULL, "SYSCLK" },
{ "ASRC1IN2R", NULL, "SYSCLK" },
{ "ASRC2IN1L", NULL, "SYSCLK" },
{ "ASRC2IN1R", NULL, "SYSCLK" },
{ "ASRC2IN2L", NULL, "SYSCLK" },
{ "ASRC2IN2R", NULL, "SYSCLK" },
{ "ASRC1IN1L", NULL, "ASYNCCLK" },
{ "ASRC1IN1R", NULL, "ASYNCCLK" },
{ "ASRC1IN2L", NULL, "ASYNCCLK" },
{ "ASRC1IN2R", NULL, "ASYNCCLK" },
{ "ASRC2IN1L", NULL, "ASYNCCLK" },
{ "ASRC2IN1R", NULL, "ASYNCCLK" },
{ "ASRC2IN2L", NULL, "ASYNCCLK" },
{ "ASRC2IN2R", NULL, "ASYNCCLK" },
{ "MICBIAS1", NULL, "MICVDD" },
{ "MICBIAS2", NULL, "MICVDD" },
{ "MICBIAS3", NULL, "MICVDD" },
{ "MICBIAS4", NULL, "MICVDD" },
{ "Noise Generator", NULL, "SYSCLK" },
{ "Tone Generator 1", NULL, "SYSCLK" },
{ "Tone Generator 2", NULL, "SYSCLK" },
{ "Noise Generator", NULL, "NOISE" },
{ "Tone Generator 1", NULL, "TONE" },
{ "Tone Generator 2", NULL, "TONE" },
{ "AIF1 Capture", NULL, "AIF1TX1" },
{ "AIF1 Capture", NULL, "AIF1TX2" },
{ "AIF1 Capture", NULL, "AIF1TX3" },
{ "AIF1 Capture", NULL, "AIF1TX4" },
{ "AIF1 Capture", NULL, "AIF1TX5" },
{ "AIF1 Capture", NULL, "AIF1TX6" },
{ "AIF1 Capture", NULL, "AIF1TX7" },
{ "AIF1 Capture", NULL, "AIF1TX8" },
{ "AIF1RX1", NULL, "AIF1 Playback" },
{ "AIF1RX2", NULL, "AIF1 Playback" },
{ "AIF1RX3", NULL, "AIF1 Playback" },
{ "AIF1RX4", NULL, "AIF1 Playback" },
{ "AIF1RX5", NULL, "AIF1 Playback" },
{ "AIF1RX6", NULL, "AIF1 Playback" },
{ "AIF1RX7", NULL, "AIF1 Playback" },
{ "AIF1RX8", NULL, "AIF1 Playback" },
{ "AIF2 Capture", NULL, "AIF2TX1" },
{ "AIF2 Capture", NULL, "AIF2TX2" },
{ "AIF2 Capture", NULL, "AIF2TX3" },
{ "AIF2 Capture", NULL, "AIF2TX4" },
{ "AIF2 Capture", NULL, "AIF2TX5" },
{ "AIF2 Capture", NULL, "AIF2TX6" },
{ "AIF2 Capture", NULL, "AIF2TX7" },
{ "AIF2 Capture", NULL, "AIF2TX8" },
{ "AIF2RX1", NULL, "AIF2 Playback" },
{ "AIF2RX2", NULL, "AIF2 Playback" },
{ "AIF2RX3", NULL, "AIF2 Playback" },
{ "AIF2RX4", NULL, "AIF2 Playback" },
{ "AIF2RX5", NULL, "AIF2 Playback" },
{ "AIF2RX6", NULL, "AIF2 Playback" },
{ "AIF2RX7", NULL, "AIF2 Playback" },
{ "AIF2RX8", NULL, "AIF2 Playback" },
{ "AIF3 Capture", NULL, "AIF3TX1" },
{ "AIF3 Capture", NULL, "AIF3TX2" },
{ "AIF3RX1", NULL, "AIF3 Playback" },
{ "AIF3RX2", NULL, "AIF3 Playback" },
{ "AIF4 Capture", NULL, "AIF4TX1" },
{ "AIF4 Capture", NULL, "AIF4TX2" },
{ "AIF4RX1", NULL, "AIF4 Playback" },
{ "AIF4RX2", NULL, "AIF4 Playback" },
{ "Slim1 Capture", NULL, "SLIMTX1" },
{ "Slim1 Capture", NULL, "SLIMTX2" },
{ "Slim1 Capture", NULL, "SLIMTX3" },
{ "Slim1 Capture", NULL, "SLIMTX4" },
{ "SLIMRX1", NULL, "Slim1 Playback" },
{ "SLIMRX2", NULL, "Slim1 Playback" },
{ "SLIMRX3", NULL, "Slim1 Playback" },
{ "SLIMRX4", NULL, "Slim1 Playback" },
{ "Slim2 Capture", NULL, "SLIMTX5" },
{ "Slim2 Capture", NULL, "SLIMTX6" },
{ "SLIMRX5", NULL, "Slim2 Playback" },
{ "SLIMRX6", NULL, "Slim2 Playback" },
{ "Slim3 Capture", NULL, "SLIMTX7" },
{ "Slim3 Capture", NULL, "SLIMTX8" },
{ "SLIMRX7", NULL, "Slim3 Playback" },
{ "SLIMRX8", NULL, "Slim3 Playback" },
{ "AIF1 Playback", NULL, "SYSCLK" },
{ "AIF2 Playback", NULL, "SYSCLK" },
{ "AIF3 Playback", NULL, "SYSCLK" },
{ "AIF4 Playback", NULL, "SYSCLK" },
{ "Slim1 Playback", NULL, "SYSCLK" },
{ "Slim2 Playback", NULL, "SYSCLK" },
{ "Slim3 Playback", NULL, "SYSCLK" },
{ "AIF1 Capture", NULL, "SYSCLK" },
{ "AIF2 Capture", NULL, "SYSCLK" },
{ "AIF3 Capture", NULL, "SYSCLK" },
{ "AIF4 Capture", NULL, "SYSCLK" },
{ "Slim1 Capture", NULL, "SYSCLK" },
{ "Slim2 Capture", NULL, "SYSCLK" },
{ "Slim3 Capture", NULL, "SYSCLK" },
{ "Voice Control DSP", NULL, "DSP6" },
{ "Audio Trace DSP", NULL, "DSP1" },
{ "IN1L Analog Mux", "A", "IN1ALN" },
{ "IN1L Analog Mux", "A", "IN1ALP" },
{ "IN1L Analog Mux", "B", "IN1BN" },
{ "IN1L Analog Mux", "B", "IN1BP" },
{ "IN1L Mode", "Analog", "IN1L Analog Mux" },
{ "IN1R Mode", "Analog", "IN1RN" },
{ "IN1R Mode", "Analog", "IN1RP" },
{ "IN1L Mode", "Digital", "IN1ALN" },
{ "IN1L Mode", "Digital", "IN1RN" },
{ "IN1R Mode", "Digital", "IN1ALN" },
{ "IN1R Mode", "Digital", "IN1RN" },
{ "IN1L", NULL, "IN1L Mode" },
{ "IN1R", NULL, "IN1R Mode" },
{ "IN2L Analog Mux", "A", "IN2ALN" },
{ "IN2L Analog Mux", "A", "IN2ALP" },
{ "IN2L Analog Mux", "B", "IN2BLN" },
{ "IN2L Analog Mux", "B", "IN2BLP" },
{ "IN2R Analog Mux", "A", "IN2ARN" },
{ "IN2R Analog Mux", "A", "IN2ARP" },
{ "IN2R Analog Mux", "B", "IN2BRN" },
{ "IN2R Analog Mux", "B", "IN2BRP" },
{ "IN2L Mode", "Analog", "IN2L Analog Mux" },
{ "IN2R Mode", "Analog", "IN2R Analog Mux" },
{ "IN2L Mode", "Digital", "IN2ALN" },
{ "IN2L Mode", "Digital", "IN2ARN" },
{ "IN2R Mode", "Digital", "IN2ALN" },
{ "IN2R Mode", "Digital", "IN2ARN" },
{ "IN2L", NULL, "IN2L Mode" },
{ "IN2R", NULL, "IN2R Mode" },
{ "IN3L Mode", "Analog", "IN3LN" },
{ "IN3L Mode", "Analog", "IN3LP" },
{ "IN3R Mode", "Analog", "IN3RN" },
{ "IN3R Mode", "Analog", "IN3RP" },
{ "IN3L Mode", "Digital", "IN3LN" },
{ "IN3L Mode", "Digital", "IN3RN" },
{ "IN3R Mode", "Digital", "IN3LN" },
{ "IN3R Mode", "Digital", "IN3RN" },
{ "IN3L", NULL, "IN3L Mode" },
{ "IN3R", NULL, "IN3R Mode" },
{ "IN4L", NULL, "DMICCLK4" },
{ "IN4L", NULL, "DMICDAT4" },
{ "IN4R", NULL, "DMICCLK4" },
{ "IN4R", NULL, "DMICDAT4" },
{ "IN5L", NULL, "DMICCLK5" },
{ "IN5L", NULL, "DMICDAT5" },
{ "IN5R", NULL, "DMICCLK5" },
{ "IN5R", NULL, "DMICDAT5" },
{ "IN6L", NULL, "DMICCLK6" },
{ "IN6L", NULL, "DMICDAT6" },
{ "IN6R", NULL, "DMICCLK6" },
{ "IN6R", NULL, "DMICDAT6" },
MADERA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
MADERA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
MADERA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
MADERA_MIXER_ROUTES("OUT2R", "HPOUT2R"),
MADERA_MIXER_ROUTES("OUT3L", "HPOUT3L"),
MADERA_MIXER_ROUTES("OUT3R", "HPOUT3R"),
MADERA_MIXER_ROUTES("OUT4L", "SPKOUTL"),
MADERA_MIXER_ROUTES("OUT4R", "SPKOUTR"),
MADERA_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
MADERA_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
MADERA_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
MADERA_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
MADERA_MIXER_ROUTES("PWM1 Driver", "PWM1"),
MADERA_MIXER_ROUTES("PWM2 Driver", "PWM2"),
MADERA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
MADERA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
MADERA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
MADERA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
MADERA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
MADERA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
MADERA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
MADERA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
MADERA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
MADERA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
MADERA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"),
MADERA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"),
MADERA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"),
MADERA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"),
MADERA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"),
MADERA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"),
MADERA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
MADERA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
MADERA_MIXER_ROUTES("AIF4TX1", "AIF4TX1"),
MADERA_MIXER_ROUTES("AIF4TX2", "AIF4TX2"),
MADERA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"),
MADERA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"),
MADERA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"),
MADERA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"),
MADERA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"),
MADERA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"),
MADERA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"),
MADERA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"),
MADERA_MUX_ROUTES("SPD1TX1", "SPDIF1TX1"),
MADERA_MUX_ROUTES("SPD1TX2", "SPDIF1TX2"),
MADERA_MIXER_ROUTES("EQ1", "EQ1"),
MADERA_MIXER_ROUTES("EQ2", "EQ2"),
MADERA_MIXER_ROUTES("EQ3", "EQ3"),
MADERA_MIXER_ROUTES("EQ4", "EQ4"),
MADERA_MIXER_ROUTES("DRC1L", "DRC1L"),
MADERA_MIXER_ROUTES("DRC1R", "DRC1R"),
MADERA_MIXER_ROUTES("DRC2L", "DRC2L"),
MADERA_MIXER_ROUTES("DRC2R", "DRC2R"),
MADERA_MIXER_ROUTES("LHPF1", "LHPF1"),
MADERA_MIXER_ROUTES("LHPF2", "LHPF2"),
MADERA_MIXER_ROUTES("LHPF3", "LHPF3"),
MADERA_MIXER_ROUTES("LHPF4", "LHPF4"),
MADERA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"),
MADERA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"),
MADERA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"),
MADERA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"),
MADERA_MUX_ROUTES("ASRC2IN1L", "ASRC2IN1L"),
MADERA_MUX_ROUTES("ASRC2IN1R", "ASRC2IN1R"),
MADERA_MUX_ROUTES("ASRC2IN2L", "ASRC2IN2L"),
MADERA_MUX_ROUTES("ASRC2IN2R", "ASRC2IN2R"),
MADERA_DSP_ROUTES("DSP1"),
MADERA_DSP_ROUTES("DSP2"),
MADERA_DSP_ROUTES("DSP3"),
MADERA_DSP_ROUTES("DSP4"),
MADERA_DSP_ROUTES("DSP5"),
MADERA_DSP_ROUTES("DSP6"),
MADERA_DSP_ROUTES("DSP7"),
{ "DSP Trigger Out", NULL, "DSP1 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP2 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP3 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP4 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP5 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP6 Trigger Output" },
{ "DSP Trigger Out", NULL, "DSP7 Trigger Output" },
{ "DSP1 Trigger Output", "Switch", "DSP1" },
{ "DSP2 Trigger Output", "Switch", "DSP2" },
{ "DSP3 Trigger Output", "Switch", "DSP3" },
{ "DSP4 Trigger Output", "Switch", "DSP4" },
{ "DSP5 Trigger Output", "Switch", "DSP5" },
{ "DSP6 Trigger Output", "Switch", "DSP6" },
{ "DSP7 Trigger Output", "Switch", "DSP7" },
MADERA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
MADERA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
MADERA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"),
MADERA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"),
MADERA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
MADERA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
MADERA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
MADERA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
MADERA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
MADERA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
MADERA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"),
MADERA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"),
MADERA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
MADERA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
MADERA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
MADERA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
MADERA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"),
MADERA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"),
MADERA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"),
MADERA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"),
MADERA_MUX_ROUTES("ISRC4INT1", "ISRC4INT1"),
MADERA_MUX_ROUTES("ISRC4INT2", "ISRC4INT2"),
MADERA_MUX_ROUTES("ISRC4DEC1", "ISRC4DEC1"),
MADERA_MUX_ROUTES("ISRC4DEC2", "ISRC4DEC2"),
{ "AEC1 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC1 Loopback", "HPOUT1R", "OUT1R" },
{ "AEC2 Loopback", "HPOUT1L", "OUT1L" },
{ "AEC2 Loopback", "HPOUT1R", "OUT1R" },
{ "HPOUT1L", NULL, "OUT1L" },
{ "HPOUT1R", NULL, "OUT1R" },
{ "AEC1 Loopback", "HPOUT2L", "OUT2L" },
{ "AEC1 Loopback", "HPOUT2R", "OUT2R" },
{ "AEC2 Loopback", "HPOUT2L", "OUT2L" },
{ "AEC2 Loopback", "HPOUT2R", "OUT2R" },
{ "HPOUT2L", NULL, "OUT2L" },
{ "HPOUT2R", NULL, "OUT2R" },
{ "AEC1 Loopback", "HPOUT3L", "OUT3L" },
{ "AEC1 Loopback", "HPOUT3R", "OUT3R" },
{ "AEC2 Loopback", "HPOUT3L", "OUT3L" },
{ "AEC2 Loopback", "HPOUT3R", "OUT3R" },
{ "HPOUT3L", NULL, "OUT3L" },
{ "HPOUT3R", NULL, "OUT3R" },
{ "AEC1 Loopback", "SPKOUTL", "OUT4L" },
{ "AEC2 Loopback", "SPKOUTL", "OUT4L" },
{ "SPKOUTLN", NULL, "OUT4L" },
{ "SPKOUTLP", NULL, "OUT4L" },
{ "AEC1 Loopback", "SPKOUTR", "OUT4R" },
{ "AEC2 Loopback", "SPKOUTR", "OUT4R" },
{ "SPKOUTRN", NULL, "OUT4R" },
{ "SPKOUTRP", NULL, "OUT4R" },
{ "AEC1 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC1 Loopback", "SPKDAT1R", "OUT5R" },
{ "AEC2 Loopback", "SPKDAT1L", "OUT5L" },
{ "AEC2 Loopback", "SPKDAT1R", "OUT5R" },
{ "SPKDAT1L", NULL, "OUT5L" },
{ "SPKDAT1R", NULL, "OUT5R" },
{ "AEC1 Loopback", "SPKDAT2L", "OUT6L" },
{ "AEC1 Loopback", "SPKDAT2R", "OUT6R" },
{ "AEC2 Loopback", "SPKDAT2L", "OUT6L" },
{ "AEC2 Loopback", "SPKDAT2R", "OUT6R" },
{ "SPKDAT2L", NULL, "OUT6L" },
{ "SPKDAT2R", NULL, "OUT6R" },
CS47L85_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"),
CS47L85_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT4L", "SPKOUTL"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT4R", "SPKOUTR"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT6L", "SPKDAT2L"),
CS47L85_RXANC_OUTPUT_ROUTES("OUT6R", "SPKDAT2R"),
{ "SPDIF1", NULL, "SPD1" },
{ "MICSUPP", NULL, "SYSCLK" },
{ "DRC1 Signal Activity", NULL, "DRC1 Activity Output" },
{ "DRC2 Signal Activity", NULL, "DRC2 Activity Output" },
{ "DRC1 Activity Output", "Switch", "DRC1L" },
{ "DRC1 Activity Output", "Switch", "DRC1R" },
{ "DRC2 Activity Output", "Switch", "DRC2L" },
{ "DRC2 Activity Output", "Switch", "DRC2R" },
};
static int cs47l85_set_fll(struct snd_soc_component *component, int fll_id,
int source, unsigned int fref, unsigned int fout)
{
struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
switch (fll_id) {
case MADERA_FLL1_REFCLK:
return madera_set_fll_refclk(&cs47l85->fll[0], source, fref,
fout);
case MADERA_FLL2_REFCLK:
return madera_set_fll_refclk(&cs47l85->fll[1], source, fref,
fout);
case MADERA_FLL3_REFCLK:
return madera_set_fll_refclk(&cs47l85->fll[2], source, fref,
fout);
case MADERA_FLL1_SYNCCLK:
return madera_set_fll_syncclk(&cs47l85->fll[0], source, fref,
fout);
case MADERA_FLL2_SYNCCLK:
return madera_set_fll_syncclk(&cs47l85->fll[1], source, fref,
fout);
case MADERA_FLL3_SYNCCLK:
return madera_set_fll_syncclk(&cs47l85->fll[2], source, fref,
fout);
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops cs47l85_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver cs47l85_dai[] = {
{
.name = "cs47l85-aif1",
.id = 1,
.base = MADERA_AIF1_BCLK_CTRL,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l85-aif2",
.id = 2,
.base = MADERA_AIF2_BCLK_CTRL,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 8,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l85-aif3",
.id = 3,
.base = MADERA_AIF3_BCLK_CTRL,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l85-aif4",
.id = 4,
.base = MADERA_AIF4_BCLK_CTRL,
.playback = {
.stream_name = "AIF4 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "AIF4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "cs47l85-slim1",
.id = 5,
.playback = {
.stream_name = "Slim1 Playback",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim1 Capture",
.channels_min = 1,
.channels_max = 4,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l85-slim2",
.id = 6,
.playback = {
.stream_name = "Slim2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l85-slim3",
.id = 7,
.playback = {
.stream_name = "Slim3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.capture = {
.stream_name = "Slim3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &madera_simple_dai_ops,
},
{
.name = "cs47l85-cpu-voicectrl",
.capture = {
.stream_name = "Voice Control CPU",
.channels_min = 1,
.channels_max = 1,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l85_dai_ops,
},
{
.name = "cs47l85-dsp-voicectrl",
.capture = {
.stream_name = "Voice Control DSP",
.channels_min = 1,
.channels_max = 1,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
{
.name = "cs47l85-cpu-trace",
.capture = {
.stream_name = "Audio Trace CPU",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
.ops = &cs47l85_dai_ops,
},
{
.name = "cs47l85-dsp-trace",
.capture = {
.stream_name = "Audio Trace DSP",
.channels_min = 1,
.channels_max = 6,
.rates = MADERA_RATES,
.formats = MADERA_FORMATS,
},
},
};
static int cs47l85_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
struct madera_priv *priv = &cs47l85->core;
struct madera *madera = priv->madera;
int n_adsp;
if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l85-dsp-voicectrl") == 0) {
n_adsp = 5;
} else if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs47l85-dsp-trace") == 0) {
n_adsp = 0;
} else {
dev_err(madera->dev,
"No suitable compressed stream for DAI '%s'\n",
asoc_rtd_to_codec(rtd, 0)->name);
return -EINVAL;
}
return wm_adsp_compr_open(&priv->adsp[n_adsp], stream);
}
static irqreturn_t cs47l85_adsp2_irq(int irq, void *data)
{
struct cs47l85 *cs47l85 = data;
struct madera_priv *priv = &cs47l85->core;
struct madera *madera = priv->madera;
struct madera_voice_trigger_info trig_info;
int serviced = 0;
int i, ret;
for (i = 0; i < CS47L85_NUM_ADSP; ++i) {
ret = wm_adsp_compr_handle_irq(&priv->adsp[i]);
if (ret != -ENODEV)
serviced++;
if (ret == WM_ADSP_COMPR_VOICE_TRIGGER) {
trig_info.core_num = i + 1;
blocking_notifier_call_chain(&madera->notifier,
MADERA_NOTIFY_VOICE_TRIGGER,
&trig_info);
}
}
if (!serviced) {
dev_err(madera->dev, "Spurious compressed data IRQ\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int cs47l85_component_probe(struct snd_soc_component *component)
{
struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l85->core.madera;
int i, ret;
snd_soc_component_init_regmap(component, madera->regmap);
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = snd_soc_component_get_dapm(component);
mutex_unlock(&madera->dapm_ptr_lock);
ret = madera_init_inputs(component);
if (ret)
return ret;
ret = madera_init_outputs(component, NULL, CS47L85_MONO_OUTPUTS,
CS47L85_MONO_OUTPUTS);
if (ret)
return ret;
snd_soc_component_disable_pin(component, "HAPTICS");
ret = snd_soc_add_component_controls(component,
madera_adsp_rate_controls,
CS47L85_NUM_ADSP);
if (ret)
return ret;
for (i = 0; i < CS47L85_NUM_ADSP; i++)
wm_adsp2_component_probe(&cs47l85->core.adsp[i], component);
return 0;
}
static void cs47l85_component_remove(struct snd_soc_component *component)
{
struct cs47l85 *cs47l85 = snd_soc_component_get_drvdata(component);
struct madera *madera = cs47l85->core.madera;
int i;
mutex_lock(&madera->dapm_ptr_lock);
madera->dapm = NULL;
mutex_unlock(&madera->dapm_ptr_lock);
for (i = 0; i < CS47L85_NUM_ADSP; i++)
wm_adsp2_component_remove(&cs47l85->core.adsp[i], component);
}
#define MADERA_DIG_VU 0x0200
static const unsigned int cs47l85_digital_vu[] = {
MADERA_DAC_DIGITAL_VOLUME_1L,
MADERA_DAC_DIGITAL_VOLUME_1R,
MADERA_DAC_DIGITAL_VOLUME_2L,
MADERA_DAC_DIGITAL_VOLUME_2R,
MADERA_DAC_DIGITAL_VOLUME_3L,
MADERA_DAC_DIGITAL_VOLUME_3R,
MADERA_DAC_DIGITAL_VOLUME_4L,
MADERA_DAC_DIGITAL_VOLUME_4R,
MADERA_DAC_DIGITAL_VOLUME_5L,
MADERA_DAC_DIGITAL_VOLUME_5R,
MADERA_DAC_DIGITAL_VOLUME_6L,
MADERA_DAC_DIGITAL_VOLUME_6R,
};
static const struct snd_compress_ops cs47l85_compress_ops = {
.open = &cs47l85_open,
.free = &wm_adsp_compr_free,
.set_params = &wm_adsp_compr_set_params,
.get_caps = &wm_adsp_compr_get_caps,
.trigger = &wm_adsp_compr_trigger,
.pointer = &wm_adsp_compr_pointer,
.copy = &wm_adsp_compr_copy,
};
static const struct snd_soc_component_driver soc_component_dev_cs47l85 = {
.probe = &cs47l85_component_probe,
.remove = &cs47l85_component_remove,
.set_sysclk = &madera_set_sysclk,
.set_pll = &cs47l85_set_fll,
.name = DRV_NAME,
.compress_ops = &cs47l85_compress_ops,
.controls = cs47l85_snd_controls,
.num_controls = ARRAY_SIZE(cs47l85_snd_controls),
.dapm_widgets = cs47l85_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs47l85_dapm_widgets),
.dapm_routes = cs47l85_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs47l85_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int cs47l85_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
struct cs47l85 *cs47l85;
int i, ret;
BUILD_BUG_ON(ARRAY_SIZE(cs47l85_dai) > MADERA_MAX_DAI);
/* quick exit if Madera irqchip driver hasn't completed probe */
if (!madera->irq_dev) {
dev_dbg(&pdev->dev, "irqchip driver not ready\n");
return -EPROBE_DEFER;
}
cs47l85 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l85),
GFP_KERNEL);
if (!cs47l85)
return -ENOMEM;
platform_set_drvdata(pdev, cs47l85);
cs47l85->core.madera = madera;
cs47l85->core.dev = &pdev->dev;
cs47l85->core.num_inputs = 12;
ret = madera_core_init(&cs47l85->core);
if (ret)
return ret;
ret = madera_init_overheat(&cs47l85->core);
if (ret)
goto error_core;
ret = madera_request_irq(madera, MADERA_IRQ_DSP_IRQ1,
"ADSP2 Compressed IRQ", cs47l85_adsp2_irq,
cs47l85);
if (ret) {
dev_err(&pdev->dev, "Failed to request DSP IRQ: %d\n", ret);
goto error_overheat;
}
ret = madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 1);
if (ret)
dev_warn(&pdev->dev, "Failed to set DSP IRQ wake: %d\n", ret);
for (i = 0; i < CS47L85_NUM_ADSP; i++) {
cs47l85->core.adsp[i].part = "cs47l85";
cs47l85->core.adsp[i].cs_dsp.num = i + 1;
cs47l85->core.adsp[i].cs_dsp.type = WMFW_ADSP2;
cs47l85->core.adsp[i].cs_dsp.rev = 1;
cs47l85->core.adsp[i].cs_dsp.dev = madera->dev;
cs47l85->core.adsp[i].cs_dsp.regmap = madera->regmap_32bit;
cs47l85->core.adsp[i].cs_dsp.base = wm_adsp2_control_bases[i];
cs47l85->core.adsp[i].cs_dsp.mem = cs47l85_dsp_regions[i];
cs47l85->core.adsp[i].cs_dsp.num_mems =
ARRAY_SIZE(cs47l85_dsp1_regions);
ret = wm_adsp2_init(&cs47l85->core.adsp[i]);
if (ret) {
for (--i; i >= 0; --i)
wm_adsp2_remove(&cs47l85->core.adsp[i]);
goto error_dsp_irq;
}
}
madera_init_fll(madera, 1, MADERA_FLL1_CONTROL_1 - 1,
&cs47l85->fll[0]);
madera_init_fll(madera, 2, MADERA_FLL2_CONTROL_1 - 1,
&cs47l85->fll[1]);
madera_init_fll(madera, 3, MADERA_FLL3_CONTROL_1 - 1,
&cs47l85->fll[2]);
for (i = 0; i < ARRAY_SIZE(cs47l85_dai); i++)
madera_init_dai(&cs47l85->core, i);
/* Latch volume update bits */
for (i = 0; i < ARRAY_SIZE(cs47l85_digital_vu); i++)
regmap_update_bits(madera->regmap, cs47l85_digital_vu[i],
MADERA_DIG_VU, MADERA_DIG_VU);
pm_runtime_enable(&pdev->dev);
pm_runtime_idle(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cs47l85,
cs47l85_dai,
ARRAY_SIZE(cs47l85_dai));
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
goto error_pm_runtime;
}
return ret;
error_pm_runtime:
pm_runtime_disable(&pdev->dev);
for (i = 0; i < CS47L85_NUM_ADSP; i++)
wm_adsp2_remove(&cs47l85->core.adsp[i]);
error_dsp_irq:
madera_set_irq_wake(madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(madera, MADERA_IRQ_DSP_IRQ1, cs47l85);
error_overheat:
madera_free_overheat(&cs47l85->core);
error_core:
madera_core_free(&cs47l85->core);
return ret;
}
static void cs47l85_remove(struct platform_device *pdev)
{
struct cs47l85 *cs47l85 = platform_get_drvdata(pdev);
int i;
pm_runtime_disable(&pdev->dev);
for (i = 0; i < CS47L85_NUM_ADSP; i++)
wm_adsp2_remove(&cs47l85->core.adsp[i]);
madera_set_irq_wake(cs47l85->core.madera, MADERA_IRQ_DSP_IRQ1, 0);
madera_free_irq(cs47l85->core.madera, MADERA_IRQ_DSP_IRQ1, cs47l85);
madera_free_overheat(&cs47l85->core);
madera_core_free(&cs47l85->core);
}
static struct platform_driver cs47l85_codec_driver = {
.driver = {
.name = "cs47l85-codec",
},
.probe = &cs47l85_probe,
.remove_new = cs47l85_remove,
};
module_platform_driver(cs47l85_codec_driver);
MODULE_SOFTDEP("pre: madera irq-madera arizona-micsupp");
MODULE_DESCRIPTION("ASoC CS47L85 driver");
MODULE_AUTHOR("Nariman Poushin <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cs47l85-codec");
| linux-master | sound/soc/codecs/cs47l85.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "ml26124.h"
#define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */
#define DVOL_CTL_DVMUTE_OFF 0 /* Digital volume MUTE Off */
#define ML26124_SAI_NO_DELAY BIT(1)
#define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */
#define ML26134_CACHESIZE 212
#define ML26124_VMID BIT(1)
#define ML26124_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define ML26124_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
#define ML26124_NUM_REGISTER ML26134_CACHESIZE
struct ml26124_priv {
u32 mclk;
u32 rate;
struct regmap *regmap;
int clk_in;
struct snd_pcm_substream *substream;
};
struct clk_coeff {
u32 mclk;
u32 rate;
u8 pllnl;
u8 pllnh;
u8 pllml;
u8 pllmh;
u8 plldiv;
};
/* ML26124 configuration */
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(maxgain, -675, 600, 0);
static const DECLARE_TLV_DB_SCALE(boost_vol, -1200, 75, 0);
static const char * const ml26124_companding[] = {"16bit PCM", "u-law",
"A-law"};
static SOC_ENUM_SINGLE_DECL(ml26124_adc_companding_enum,
ML26124_SAI_TRANS_CTL, 6, ml26124_companding);
static SOC_ENUM_SINGLE_DECL(ml26124_dac_companding_enum,
ML26124_SAI_RCV_CTL, 6, ml26124_companding);
static const struct snd_kcontrol_new ml26124_snd_controls[] = {
SOC_SINGLE_TLV("Capture Digital Volume", ML26124_RECORD_DIG_VOL, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("Playback Digital Volume", ML26124_PLBAK_DIG_VOL, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("Digital Boost Volume", ML26124_DIGI_BOOST_VOL, 0,
0x3f, 0, boost_vol),
SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
0xff, 1, digital_tlv),
SOC_SINGLE_TLV("ALC Target Level", ML26124_ALC_TARGET_LEV, 0,
0xf, 1, alclvl),
SOC_SINGLE_TLV("ALC Min Input Volume", ML26124_ALC_MAXMIN_GAIN, 0,
7, 0, mingain),
SOC_SINGLE_TLV("ALC Max Input Volume", ML26124_ALC_MAXMIN_GAIN, 4,
7, 1, maxgain),
SOC_SINGLE_TLV("Playback Limiter Min Input Volume",
ML26124_PL_MAXMIN_GAIN, 0, 7, 0, mingain),
SOC_SINGLE_TLV("Playback Limiter Max Input Volume",
ML26124_PL_MAXMIN_GAIN, 4, 7, 1, maxgain),
SOC_SINGLE_TLV("Playback Boost Volume", ML26124_PLYBAK_BOST_VOL, 0,
0x3f, 0, boost_vol),
SOC_SINGLE("DC High Pass Filter Switch", ML26124_FILTER_EN, 0, 1, 0),
SOC_SINGLE("Noise High Pass Filter Switch", ML26124_FILTER_EN, 1, 1, 0),
SOC_SINGLE("ZC Switch", ML26124_PW_ZCCMP_PW_MNG, 1,
1, 0),
SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
SOC_SINGLE("Play Limiter", ML26124_DVOL_CTL, 0, 1, 0),
SOC_SINGLE("Capture Limiter", ML26124_DVOL_CTL, 1, 1, 0),
SOC_SINGLE("Digital Volume Fade Switch", ML26124_DVOL_CTL, 3, 1, 0),
SOC_SINGLE("Digital Switch", ML26124_DVOL_CTL, 4, 1, 0),
SOC_ENUM("DAC Companding", ml26124_dac_companding_enum),
SOC_ENUM("ADC Companding", ml26124_adc_companding_enum),
};
static const struct snd_kcontrol_new ml26124_output_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC Switch", ML26124_SPK_AMP_OUT, 1, 1, 0),
SOC_DAPM_SINGLE("Line in loopback Switch", ML26124_SPK_AMP_OUT, 3, 1,
0),
SOC_DAPM_SINGLE("PGA Switch", ML26124_SPK_AMP_OUT, 5, 1, 0),
};
/* Input mux */
static const char * const ml26124_input_select[] = {"Analog MIC SingleEnded in",
"Digital MIC in", "Analog MIC Differential in"};
static SOC_ENUM_SINGLE_DECL(ml26124_insel_enum,
ML26124_MIC_IF_CTL, 0, ml26124_input_select);
static const struct snd_kcontrol_new ml26124_input_mux_controls =
SOC_DAPM_ENUM("Input Select", ml26124_insel_enum);
static const struct snd_kcontrol_new ml26124_line_control =
SOC_DAPM_SINGLE("Switch", ML26124_PW_LOUT_PW_MNG, 1, 1, 0);
static const struct snd_soc_dapm_widget ml26124_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MCLKEN", ML26124_CLK_EN, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLLEN", ML26124_CLK_EN, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLLOE", ML26124_CLK_EN, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS", ML26124_PW_REF_PW_MNG, 2, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
&ml26124_output_mixer_controls[0],
ARRAY_SIZE(ml26124_output_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "Playback", ML26124_PW_DAC_PW_MNG, 1, 0),
SND_SOC_DAPM_ADC("ADC", "Capture", ML26124_PW_IN_PW_MNG, 1, 0),
SND_SOC_DAPM_PGA("PGA", ML26124_PW_IN_PW_MNG, 3, 0, NULL, 0),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&ml26124_input_mux_controls),
SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
&ml26124_line_control),
SND_SOC_DAPM_INPUT("MDIN"),
SND_SOC_DAPM_INPUT("MIN"),
SND_SOC_DAPM_INPUT("LIN"),
SND_SOC_DAPM_OUTPUT("SPOUT"),
SND_SOC_DAPM_OUTPUT("LOUT"),
};
static const struct snd_soc_dapm_route ml26124_intercon[] = {
/* Supply */
{"DAC", NULL, "MCLKEN"},
{"ADC", NULL, "MCLKEN"},
{"DAC", NULL, "PLLEN"},
{"ADC", NULL, "PLLEN"},
{"DAC", NULL, "PLLOE"},
{"ADC", NULL, "PLLOE"},
/* output mixer */
{"Output Mixer", "DAC Switch", "DAC"},
{"Output Mixer", "Line in loopback Switch", "LIN"},
/* outputs */
{"LOUT", NULL, "Output Mixer"},
{"SPOUT", NULL, "Output Mixer"},
{"Line Out Enable", NULL, "LOUT"},
/* input */
{"ADC", NULL, "Input Mux"},
{"Input Mux", "Analog MIC SingleEnded in", "PGA"},
{"Input Mux", "Analog MIC Differential in", "PGA"},
{"PGA", NULL, "MIN"},
};
/* PLLOutputFreq(Hz) = InputMclkFreq(Hz) * PLLM / (PLLN * PLLDIV) */
static const struct clk_coeff coeff_div[] = {
{12288000, 16000, 0xc, 0x0, 0x20, 0x0, 0x4},
{12288000, 32000, 0xc, 0x0, 0x20, 0x0, 0x4},
{12288000, 48000, 0xc, 0x0, 0x30, 0x0, 0x4},
};
static const struct reg_default ml26124_reg[] = {
/* CLOCK control Register */
{0x00, 0x00 }, /* Sampling Rate */
{0x02, 0x00}, /* PLL NL */
{0x04, 0x00}, /* PLLNH */
{0x06, 0x00}, /* PLLML */
{0x08, 0x00}, /* MLLMH */
{0x0a, 0x00}, /* PLLDIV */
{0x0c, 0x00}, /* Clock Enable */
{0x0e, 0x00}, /* CLK Input/Output Control */
/* System Control Register */
{0x10, 0x00}, /* Software RESET */
{0x12, 0x00}, /* Record/Playback Run */
{0x14, 0x00}, /* Mic Input/Output control */
/* Power Management Register */
{0x20, 0x00}, /* Reference Power Management */
{0x22, 0x00}, /* Input Power Management */
{0x24, 0x00}, /* DAC Power Management */
{0x26, 0x00}, /* SP-AMP Power Management */
{0x28, 0x00}, /* LINEOUT Power Management */
{0x2a, 0x00}, /* VIDEO Power Management */
{0x2e, 0x00}, /* AC-CMP Power Management */
/* Analog reference Control Register */
{0x30, 0x04}, /* MICBIAS Voltage Control */
/* Input/Output Amplifier Control Register */
{0x32, 0x10}, /* MIC Input Volume */
{0x38, 0x00}, /* Mic Boost Volume */
{0x3a, 0x33}, /* Speaker AMP Volume */
{0x48, 0x00}, /* AMP Volume Control Function Enable */
{0x4a, 0x00}, /* Amplifier Volume Fader Control */
/* Analog Path Control Register */
{0x54, 0x00}, /* Speaker AMP Output Control */
{0x5a, 0x00}, /* Mic IF Control */
{0xe8, 0x01}, /* Mic Select Control */
/* Audio Interface Control Register */
{0x60, 0x00}, /* SAI-Trans Control */
{0x62, 0x00}, /* SAI-Receive Control */
{0x64, 0x00}, /* SAI Mode select */
/* DSP Control Register */
{0x66, 0x01}, /* Filter Func Enable */
{0x68, 0x00}, /* Volume Control Func Enable */
{0x6A, 0x00}, /* Mixer & Volume Control*/
{0x6C, 0xff}, /* Record Digital Volume */
{0x70, 0xff}, /* Playback Digital Volume */
{0x72, 0x10}, /* Digital Boost Volume */
{0x74, 0xe7}, /* EQ gain Band0 */
{0x76, 0xe7}, /* EQ gain Band1 */
{0x78, 0xe7}, /* EQ gain Band2 */
{0x7A, 0xe7}, /* EQ gain Band3 */
{0x7C, 0xe7}, /* EQ gain Band4 */
{0x7E, 0x00}, /* HPF2 CutOff*/
{0x80, 0x00}, /* EQ Band0 Coef0L */
{0x82, 0x00}, /* EQ Band0 Coef0H */
{0x84, 0x00}, /* EQ Band0 Coef0L */
{0x86, 0x00}, /* EQ Band0 Coef0H */
{0x88, 0x00}, /* EQ Band1 Coef0L */
{0x8A, 0x00}, /* EQ Band1 Coef0H */
{0x8C, 0x00}, /* EQ Band1 Coef0L */
{0x8E, 0x00}, /* EQ Band1 Coef0H */
{0x90, 0x00}, /* EQ Band2 Coef0L */
{0x92, 0x00}, /* EQ Band2 Coef0H */
{0x94, 0x00}, /* EQ Band2 Coef0L */
{0x96, 0x00}, /* EQ Band2 Coef0H */
{0x98, 0x00}, /* EQ Band3 Coef0L */
{0x9A, 0x00}, /* EQ Band3 Coef0H */
{0x9C, 0x00}, /* EQ Band3 Coef0L */
{0x9E, 0x00}, /* EQ Band3 Coef0H */
{0xA0, 0x00}, /* EQ Band4 Coef0L */
{0xA2, 0x00}, /* EQ Band4 Coef0H */
{0xA4, 0x00}, /* EQ Band4 Coef0L */
{0xA6, 0x00}, /* EQ Band4 Coef0H */
/* ALC Control Register */
{0xb0, 0x00}, /* ALC Mode */
{0xb2, 0x02}, /* ALC Attack Time */
{0xb4, 0x03}, /* ALC Decay Time */
{0xb6, 0x00}, /* ALC Hold Time */
{0xb8, 0x0b}, /* ALC Target Level */
{0xba, 0x70}, /* ALC Max/Min Gain */
{0xbc, 0x00}, /* Noise Gate Threshold */
{0xbe, 0x00}, /* ALC ZeroCross TimeOut */
/* Playback Limiter Control Register */
{0xc0, 0x04}, /* PL Attack Time */
{0xc2, 0x05}, /* PL Decay Time */
{0xc4, 0x0d}, /* PL Target Level */
{0xc6, 0x70}, /* PL Max/Min Gain */
{0xc8, 0x10}, /* Playback Boost Volume */
{0xca, 0x00}, /* PL ZeroCross TimeOut */
/* Video Amplifier Control Register */
{0xd0, 0x01}, /* VIDEO AMP Gain Control */
{0xd2, 0x01}, /* VIDEO AMP Setup 1 */
{0xd4, 0x01}, /* VIDEO AMP Control2 */
};
/* Get sampling rate value of sampling rate setting register (0x0) */
static inline int get_srate(int rate)
{
int srate;
switch (rate) {
case 16000:
srate = 3;
break;
case 32000:
srate = 6;
break;
case 48000:
srate = 8;
break;
default:
return -EINVAL;
}
return srate;
}
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return -EINVAL;
}
static int ml26124_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
int i = get_coeff(priv->mclk, params_rate(hw_params));
int srate;
if (i < 0)
return i;
priv->substream = substream;
priv->rate = params_rate(hw_params);
if (priv->clk_in) {
switch (priv->mclk / params_rate(hw_params)) {
case 256:
snd_soc_component_update_bits(component, ML26124_CLK_CTL,
BIT(0) | BIT(1), 1);
break;
case 512:
snd_soc_component_update_bits(component, ML26124_CLK_CTL,
BIT(0) | BIT(1), 2);
break;
case 1024:
snd_soc_component_update_bits(component, ML26124_CLK_CTL,
BIT(0) | BIT(1), 3);
break;
default:
dev_err(component->dev, "Unsupported MCLKI\n");
break;
}
} else {
snd_soc_component_update_bits(component, ML26124_CLK_CTL,
BIT(0) | BIT(1), 0);
}
srate = get_srate(params_rate(hw_params));
if (srate < 0)
return srate;
snd_soc_component_update_bits(component, ML26124_SMPLING_RATE, 0xf, srate);
snd_soc_component_update_bits(component, ML26124_PLLNL, 0xff, coeff_div[i].pllnl);
snd_soc_component_update_bits(component, ML26124_PLLNH, 0x1, coeff_div[i].pllnh);
snd_soc_component_update_bits(component, ML26124_PLLML, 0xff, coeff_div[i].pllml);
snd_soc_component_update_bits(component, ML26124_PLLMH, 0x3f, coeff_div[i].pllmh);
snd_soc_component_update_bits(component, ML26124_PLLDIV, 0x1f, coeff_div[i].plldiv);
return 0;
}
static int ml26124_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
switch (priv->substream->stream) {
case SNDRV_PCM_STREAM_CAPTURE:
snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(0), 1);
break;
case SNDRV_PCM_STREAM_PLAYBACK:
snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(1), 2);
break;
}
if (mute)
snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
DVOL_CTL_DVMUTE_ON);
else
snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
DVOL_CTL_DVMUTE_OFF);
return 0;
}
static int ml26124_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
unsigned char mode;
struct snd_soc_component *component = codec_dai->component;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
mode = 1;
break;
case SND_SOC_DAIFMT_CBC_CFC:
mode = 0;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, ML26124_SAI_MODE_SEL, BIT(0), mode);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
return 0;
}
static int ml26124_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case ML26124_USE_PLLOUT:
priv->clk_in = ML26124_USE_PLLOUT;
break;
case ML26124_USE_MCLKI:
priv->clk_in = ML26124_USE_MCLKI;
break;
default:
return -EINVAL;
}
priv->mclk = freq;
return 0;
}
static int ml26124_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
ML26124_R26_MASK, ML26124_BLT_PREAMP_ON);
msleep(100);
snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
ML26124_R26_MASK,
ML26124_MICBEN_ON | ML26124_BLT_ALL_ON);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* VMID ON */
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
ML26124_VMID, ML26124_VMID);
msleep(500);
regcache_sync(priv->regmap);
}
break;
case SND_SOC_BIAS_OFF:
/* VMID OFF */
snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
ML26124_VMID, 0);
break;
}
return 0;
}
static const struct snd_soc_dai_ops ml26124_dai_ops = {
.hw_params = ml26124_hw_params,
.mute_stream = ml26124_mute,
.set_fmt = ml26124_set_dai_fmt,
.set_sysclk = ml26124_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver ml26124_dai = {
.name = "ml26124-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = ML26124_RATES,
.formats = ML26124_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = ML26124_RATES,
.formats = ML26124_FORMATS,},
.ops = &ml26124_dai_ops,
.symmetric_rate = 1,
};
static int ml26124_probe(struct snd_soc_component *component)
{
/* Software Reset */
snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 1);
snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 0);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_ml26124 = {
.probe = ml26124_probe,
.set_bias_level = ml26124_set_bias_level,
.controls = ml26124_snd_controls,
.num_controls = ARRAY_SIZE(ml26124_snd_controls),
.dapm_widgets = ml26124_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ml26124_dapm_widgets),
.dapm_routes = ml26124_intercon,
.num_dapm_routes = ARRAY_SIZE(ml26124_intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ml26124_i2c_regmap = {
.val_bits = 8,
.reg_bits = 8,
.max_register = ML26124_NUM_REGISTER,
.reg_defaults = ml26124_reg,
.num_reg_defaults = ARRAY_SIZE(ml26124_reg),
.cache_type = REGCACHE_RBTREE,
.write_flag_mask = 0x01,
};
static int ml26124_i2c_probe(struct i2c_client *i2c)
{
struct ml26124_priv *priv;
int ret;
priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
i2c_set_clientdata(i2c, priv);
priv->regmap = devm_regmap_init_i2c(i2c, &ml26124_i2c_regmap);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
dev_err(&i2c->dev, "regmap_init_i2c() failed: %d\n", ret);
return ret;
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_ml26124, &ml26124_dai, 1);
}
static const struct i2c_device_id ml26124_i2c_id[] = {
{ "ml26124", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ml26124_i2c_id);
static struct i2c_driver ml26124_i2c_driver = {
.driver = {
.name = "ml26124",
},
.probe = ml26124_i2c_probe,
.id_table = ml26124_i2c_id,
};
module_i2c_driver(ml26124_i2c_driver);
MODULE_AUTHOR("Tomoya MORINAGA <[email protected]>");
MODULE_DESCRIPTION("LAPIS Semiconductor ML26124 ALSA SoC codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ml26124.c |
// SPDX-License-Identifier: GPL-2.0
//
// rt1015.c -- RT1015 ALSA SoC audio amplifier driver
//
// Copyright 2019 Realtek Semiconductor Corp.
//
// Author: Jack Yu <[email protected]>
//
//
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/fs.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/rt1015.h>
#include <sound/soc-dapm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt1015.h"
static const struct rt1015_platform_data i2s_default_platform_data = {
.power_up_delay_ms = 50,
};
static const struct reg_default rt1015_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0004, 0xa000 },
{ 0x0006, 0x0003 },
{ 0x000a, 0x081e },
{ 0x000c, 0x0006 },
{ 0x000e, 0x0000 },
{ 0x0010, 0x0000 },
{ 0x0012, 0x0000 },
{ 0x0014, 0x0000 },
{ 0x0016, 0x0000 },
{ 0x0018, 0x0000 },
{ 0x0020, 0x8000 },
{ 0x0022, 0x8043 },
{ 0x0076, 0x0000 },
{ 0x0078, 0x0000 },
{ 0x007a, 0x0002 },
{ 0x007c, 0x10ec },
{ 0x007d, 0x1015 },
{ 0x00f0, 0x5000 },
{ 0x00f2, 0x004c },
{ 0x00f3, 0xecfe },
{ 0x00f4, 0x0000 },
{ 0x00f6, 0x0400 },
{ 0x0100, 0x0028 },
{ 0x0102, 0xff02 },
{ 0x0104, 0xa213 },
{ 0x0106, 0x200c },
{ 0x010c, 0x0000 },
{ 0x010e, 0x0058 },
{ 0x0111, 0x0200 },
{ 0x0112, 0x0400 },
{ 0x0114, 0x0022 },
{ 0x0116, 0x0000 },
{ 0x0118, 0x0000 },
{ 0x011a, 0x0123 },
{ 0x011c, 0x4567 },
{ 0x0300, 0x203d },
{ 0x0302, 0x001e },
{ 0x0311, 0x0000 },
{ 0x0313, 0x6014 },
{ 0x0314, 0x00a2 },
{ 0x031a, 0x00a0 },
{ 0x031c, 0x001f },
{ 0x031d, 0xffff },
{ 0x031e, 0x0000 },
{ 0x031f, 0x0000 },
{ 0x0320, 0x0000 },
{ 0x0321, 0x0000 },
{ 0x0322, 0xd7df },
{ 0x0328, 0x10b2 },
{ 0x0329, 0x0175 },
{ 0x032a, 0x36ad },
{ 0x032b, 0x7e55 },
{ 0x032c, 0x0520 },
{ 0x032d, 0xaa00 },
{ 0x032e, 0x570e },
{ 0x0330, 0xe180 },
{ 0x0332, 0x0034 },
{ 0x0334, 0x0001 },
{ 0x0336, 0x0010 },
{ 0x0338, 0x0000 },
{ 0x04fa, 0x0030 },
{ 0x04fc, 0x35c8 },
{ 0x04fe, 0x0800 },
{ 0x0500, 0x0400 },
{ 0x0502, 0x1000 },
{ 0x0504, 0x0000 },
{ 0x0506, 0x04ff },
{ 0x0508, 0x0010 },
{ 0x050a, 0x001a },
{ 0x0519, 0x1c68 },
{ 0x051a, 0x0ccc },
{ 0x051b, 0x0666 },
{ 0x051d, 0x0000 },
{ 0x051f, 0x0000 },
{ 0x0536, 0x061c },
{ 0x0538, 0x0000 },
{ 0x053a, 0x0000 },
{ 0x053c, 0x0000 },
{ 0x053d, 0x0000 },
{ 0x053e, 0x0000 },
{ 0x053f, 0x0000 },
{ 0x0540, 0x0000 },
{ 0x0541, 0x0000 },
{ 0x0542, 0x0000 },
{ 0x0543, 0x0000 },
{ 0x0544, 0x0000 },
{ 0x0568, 0x0000 },
{ 0x056a, 0x0000 },
{ 0x1000, 0x0040 },
{ 0x1002, 0x5405 },
{ 0x1006, 0x5515 },
{ 0x1007, 0x05f7 },
{ 0x1009, 0x0b0a },
{ 0x100a, 0x00ef },
{ 0x100d, 0x0003 },
{ 0x1010, 0xa433 },
{ 0x1020, 0x0000 },
{ 0x1200, 0x5a01 },
{ 0x1202, 0x6524 },
{ 0x1204, 0x1f00 },
{ 0x1206, 0x0000 },
{ 0x1208, 0x0000 },
{ 0x120a, 0x0000 },
{ 0x120c, 0x0000 },
{ 0x120e, 0x0000 },
{ 0x1210, 0x0000 },
{ 0x1212, 0x0000 },
{ 0x1300, 0x10a1 },
{ 0x1302, 0x12ff },
{ 0x1304, 0x0400 },
{ 0x1305, 0x0844 },
{ 0x1306, 0x4611 },
{ 0x1308, 0x555e },
{ 0x130a, 0x0000 },
{ 0x130c, 0x2000 },
{ 0x130e, 0x0100 },
{ 0x130f, 0x0001 },
{ 0x1310, 0x0000 },
{ 0x1312, 0x0000 },
{ 0x1314, 0x0000 },
{ 0x1316, 0x0000 },
{ 0x1318, 0x0000 },
{ 0x131a, 0x0000 },
{ 0x1322, 0x0029 },
{ 0x1323, 0x4a52 },
{ 0x1324, 0x002c },
{ 0x1325, 0x0b02 },
{ 0x1326, 0x002d },
{ 0x1327, 0x6b5a },
{ 0x1328, 0x002e },
{ 0x1329, 0xcbb2 },
{ 0x132a, 0x0030 },
{ 0x132b, 0x2c0b },
{ 0x1330, 0x0031 },
{ 0x1331, 0x8c63 },
{ 0x1332, 0x0032 },
{ 0x1333, 0xecbb },
{ 0x1334, 0x0034 },
{ 0x1335, 0x4d13 },
{ 0x1336, 0x0037 },
{ 0x1337, 0x0dc3 },
{ 0x1338, 0x003d },
{ 0x1339, 0xef7b },
{ 0x133a, 0x0044 },
{ 0x133b, 0xd134 },
{ 0x133c, 0x0047 },
{ 0x133d, 0x91e4 },
{ 0x133e, 0x004d },
{ 0x133f, 0xc370 },
{ 0x1340, 0x0053 },
{ 0x1341, 0xf4fd },
{ 0x1342, 0x0060 },
{ 0x1343, 0x5816 },
{ 0x1344, 0x006c },
{ 0x1345, 0xbb2e },
{ 0x1346, 0x0072 },
{ 0x1347, 0xecbb },
{ 0x1348, 0x0076 },
{ 0x1349, 0x5d97 },
};
static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1015_RESET:
case RT1015_CLK_DET:
case RT1015_SIL_DET:
case RT1015_VER_ID:
case RT1015_VENDOR_ID:
case RT1015_DEVICE_ID:
case RT1015_PRO_ALT:
case RT1015_MAN_I2C:
case RT1015_DAC3:
case RT1015_VBAT_TEST_OUT1:
case RT1015_VBAT_TEST_OUT2:
case RT1015_VBAT_PROT_ATT:
case RT1015_VBAT_DET_CODE:
case RT1015_SMART_BST_CTRL1:
case RT1015_SPK_DC_DETECT1:
case RT1015_SPK_DC_DETECT4:
case RT1015_SPK_DC_DETECT5:
case RT1015_DC_CALIB_CLSD1:
case RT1015_DC_CALIB_CLSD5:
case RT1015_DC_CALIB_CLSD6:
case RT1015_DC_CALIB_CLSD7:
case RT1015_DC_CALIB_CLSD8:
case RT1015_S_BST_TIMING_INTER1:
case RT1015_OSCK_STA:
case RT1015_MONO_DYNA_CTRL1:
case RT1015_MONO_DYNA_CTRL5:
return true;
default:
return false;
}
}
static bool rt1015_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT1015_RESET:
case RT1015_CLK2:
case RT1015_CLK3:
case RT1015_PLL1:
case RT1015_PLL2:
case RT1015_DUM_RW1:
case RT1015_DUM_RW2:
case RT1015_DUM_RW3:
case RT1015_DUM_RW4:
case RT1015_DUM_RW5:
case RT1015_DUM_RW6:
case RT1015_CLK_DET:
case RT1015_SIL_DET:
case RT1015_CUSTOMER_ID:
case RT1015_PCODE_FWVER:
case RT1015_VER_ID:
case RT1015_VENDOR_ID:
case RT1015_DEVICE_ID:
case RT1015_PAD_DRV1:
case RT1015_PAD_DRV2:
case RT1015_GAT_BOOST:
case RT1015_PRO_ALT:
case RT1015_OSCK_STA:
case RT1015_MAN_I2C:
case RT1015_DAC1:
case RT1015_DAC2:
case RT1015_DAC3:
case RT1015_ADC1:
case RT1015_ADC2:
case RT1015_TDM_MASTER:
case RT1015_TDM_TCON:
case RT1015_TDM1_1:
case RT1015_TDM1_2:
case RT1015_TDM1_3:
case RT1015_TDM1_4:
case RT1015_TDM1_5:
case RT1015_MIXER1:
case RT1015_MIXER2:
case RT1015_ANA_PROTECT1:
case RT1015_ANA_CTRL_SEQ1:
case RT1015_ANA_CTRL_SEQ2:
case RT1015_VBAT_DET_DEB:
case RT1015_VBAT_VOLT_DET1:
case RT1015_VBAT_VOLT_DET2:
case RT1015_VBAT_TEST_OUT1:
case RT1015_VBAT_TEST_OUT2:
case RT1015_VBAT_PROT_ATT:
case RT1015_VBAT_DET_CODE:
case RT1015_PWR1:
case RT1015_PWR4:
case RT1015_PWR5:
case RT1015_PWR6:
case RT1015_PWR7:
case RT1015_PWR8:
case RT1015_PWR9:
case RT1015_CLASSD_SEQ:
case RT1015_SMART_BST_CTRL1:
case RT1015_SMART_BST_CTRL2:
case RT1015_ANA_CTRL1:
case RT1015_ANA_CTRL2:
case RT1015_PWR_STATE_CTRL:
case RT1015_MONO_DYNA_CTRL:
case RT1015_MONO_DYNA_CTRL1:
case RT1015_MONO_DYNA_CTRL2:
case RT1015_MONO_DYNA_CTRL3:
case RT1015_MONO_DYNA_CTRL4:
case RT1015_MONO_DYNA_CTRL5:
case RT1015_SPK_VOL:
case RT1015_SHORT_DETTOP1:
case RT1015_SHORT_DETTOP2:
case RT1015_SPK_DC_DETECT1:
case RT1015_SPK_DC_DETECT2:
case RT1015_SPK_DC_DETECT3:
case RT1015_SPK_DC_DETECT4:
case RT1015_SPK_DC_DETECT5:
case RT1015_BAT_RPO_STEP1:
case RT1015_BAT_RPO_STEP2:
case RT1015_BAT_RPO_STEP3:
case RT1015_BAT_RPO_STEP4:
case RT1015_BAT_RPO_STEP5:
case RT1015_BAT_RPO_STEP6:
case RT1015_BAT_RPO_STEP7:
case RT1015_BAT_RPO_STEP8:
case RT1015_BAT_RPO_STEP9:
case RT1015_BAT_RPO_STEP10:
case RT1015_BAT_RPO_STEP11:
case RT1015_BAT_RPO_STEP12:
case RT1015_SPREAD_SPEC1:
case RT1015_SPREAD_SPEC2:
case RT1015_PAD_STATUS:
case RT1015_PADS_PULLING_CTRL1:
case RT1015_PADS_DRIVING:
case RT1015_SYS_RST1:
case RT1015_SYS_RST2:
case RT1015_SYS_GATING1:
case RT1015_TEST_MODE1:
case RT1015_TEST_MODE2:
case RT1015_TIMING_CTRL1:
case RT1015_PLL_INT:
case RT1015_TEST_OUT1:
case RT1015_DC_CALIB_CLSD1:
case RT1015_DC_CALIB_CLSD2:
case RT1015_DC_CALIB_CLSD3:
case RT1015_DC_CALIB_CLSD4:
case RT1015_DC_CALIB_CLSD5:
case RT1015_DC_CALIB_CLSD6:
case RT1015_DC_CALIB_CLSD7:
case RT1015_DC_CALIB_CLSD8:
case RT1015_DC_CALIB_CLSD9:
case RT1015_DC_CALIB_CLSD10:
case RT1015_CLSD_INTERNAL1:
case RT1015_CLSD_INTERNAL2:
case RT1015_CLSD_INTERNAL3:
case RT1015_CLSD_INTERNAL4:
case RT1015_CLSD_INTERNAL5:
case RT1015_CLSD_INTERNAL6:
case RT1015_CLSD_INTERNAL7:
case RT1015_CLSD_INTERNAL8:
case RT1015_CLSD_INTERNAL9:
case RT1015_CLSD_OCP_CTRL:
case RT1015_VREF_LV:
case RT1015_MBIAS1:
case RT1015_MBIAS2:
case RT1015_MBIAS3:
case RT1015_MBIAS4:
case RT1015_VREF_LV1:
case RT1015_S_BST_TIMING_INTER1:
case RT1015_S_BST_TIMING_INTER2:
case RT1015_S_BST_TIMING_INTER3:
case RT1015_S_BST_TIMING_INTER4:
case RT1015_S_BST_TIMING_INTER5:
case RT1015_S_BST_TIMING_INTER6:
case RT1015_S_BST_TIMING_INTER7:
case RT1015_S_BST_TIMING_INTER8:
case RT1015_S_BST_TIMING_INTER9:
case RT1015_S_BST_TIMING_INTER10:
case RT1015_S_BST_TIMING_INTER11:
case RT1015_S_BST_TIMING_INTER12:
case RT1015_S_BST_TIMING_INTER13:
case RT1015_S_BST_TIMING_INTER14:
case RT1015_S_BST_TIMING_INTER15:
case RT1015_S_BST_TIMING_INTER16:
case RT1015_S_BST_TIMING_INTER17:
case RT1015_S_BST_TIMING_INTER18:
case RT1015_S_BST_TIMING_INTER19:
case RT1015_S_BST_TIMING_INTER20:
case RT1015_S_BST_TIMING_INTER21:
case RT1015_S_BST_TIMING_INTER22:
case RT1015_S_BST_TIMING_INTER23:
case RT1015_S_BST_TIMING_INTER24:
case RT1015_S_BST_TIMING_INTER25:
case RT1015_S_BST_TIMING_INTER26:
case RT1015_S_BST_TIMING_INTER27:
case RT1015_S_BST_TIMING_INTER28:
case RT1015_S_BST_TIMING_INTER29:
case RT1015_S_BST_TIMING_INTER30:
case RT1015_S_BST_TIMING_INTER31:
case RT1015_S_BST_TIMING_INTER32:
case RT1015_S_BST_TIMING_INTER33:
case RT1015_S_BST_TIMING_INTER34:
case RT1015_S_BST_TIMING_INTER35:
case RT1015_S_BST_TIMING_INTER36:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
static const char * const rt1015_din_source_select[] = {
"Left",
"Right",
"Left + Right average",
};
static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
rt1015_din_source_select);
static const char * const rt1015_boost_mode[] = {
"Bypass", "Adaptive", "Fixed Adaptive"
};
static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
rt1015_boost_mode);
static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1015_priv *rt1015 =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt1015->boost_mode;
return 0;
}
static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1015_priv *rt1015 =
snd_soc_component_get_drvdata(component);
int boost_mode = ucontrol->value.integer.value[0];
switch (boost_mode) {
case BYPASS:
snd_soc_component_update_bits(component,
RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
RT1015_BYPASS_SWRREG_BYPASS);
break;
case ADAPTIVE:
snd_soc_component_update_bits(component,
RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
RT1015_BYPASS_SWRREG_PASS);
break;
case FIXED_ADAPTIVE:
snd_soc_component_update_bits(component,
RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
RT1015_BYPASS_SWRREG_PASS);
break;
default:
dev_err(component->dev, "Unknown boost control.\n");
return -EINVAL;
}
rt1015->boost_mode = boost_mode;
return 0;
}
static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1015_priv *rt1015 =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt1015->bypass_boost;
return 0;
}
static void rt1015_calibrate(struct rt1015_priv *rt1015)
{
struct snd_soc_component *component = rt1015->component;
struct regmap *regmap = rt1015->regmap;
snd_soc_dapm_mutex_lock(&component->dapm);
regcache_cache_bypass(regmap, true);
regmap_write(regmap, RT1015_CLK_DET, 0x0000);
regmap_write(regmap, RT1015_PWR4, 0x00B2);
regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0009);
msleep(100);
regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000A);
msleep(100);
regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000C);
msleep(100);
regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000D);
msleep(300);
regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0008);
regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
regmap_write(regmap, RT1015_CLK_DET, 0x8000);
regcache_cache_bypass(regmap, false);
regcache_mark_dirty(regmap);
regcache_sync(regmap);
snd_soc_dapm_mutex_unlock(&component->dapm);
}
static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct rt1015_priv *rt1015 =
snd_soc_component_get_drvdata(component);
if (rt1015->dac_is_used) {
dev_err(component->dev, "DAC is being used!\n");
return -EBUSY;
}
rt1015->bypass_boost = ucontrol->value.integer.value[0];
if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
!rt1015->cali_done) {
rt1015_calibrate(rt1015);
rt1015->cali_done = 1;
regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
}
return 0;
}
static const struct snd_kcontrol_new rt1015_snd_controls[] = {
SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
127, 0, dac_vol_tlv),
SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
rt1015_boost_mode_get, rt1015_boost_mode_put),
SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
rt1015_bypass_boost_get, rt1015_bypass_boost_put),
};
static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
return 1;
else
return 0;
}
static int r1015_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rt1015->dac_is_used = 1;
if (rt1015->bypass_boost == RT1015_Enable_Boost) {
snd_soc_component_write(component,
RT1015_SYS_RST1, 0x05f7);
snd_soc_component_write(component,
RT1015_SYS_RST2, 0x0b0a);
snd_soc_component_write(component,
RT1015_GAT_BOOST, 0xacfe);
snd_soc_component_write(component,
RT1015_PWR9, 0xaa00);
snd_soc_component_write(component,
RT1015_GAT_BOOST, 0xecfe);
} else {
snd_soc_component_write(component,
0x032d, 0xaa60);
snd_soc_component_write(component,
RT1015_SYS_RST1, 0x05f7);
snd_soc_component_write(component,
RT1015_SYS_RST2, 0x0b0a);
snd_soc_component_write(component,
RT1015_PWR_STATE_CTRL, 0x008e);
}
break;
case SND_SOC_DAPM_POST_PMD:
if (rt1015->bypass_boost == RT1015_Enable_Boost) {
snd_soc_component_write(component,
RT1015_PWR9, 0xa800);
snd_soc_component_write(component,
RT1015_SYS_RST1, 0x05f5);
snd_soc_component_write(component,
RT1015_SYS_RST2, 0x0b9a);
} else {
snd_soc_component_write(component,
0x032d, 0xaa60);
snd_soc_component_write(component,
RT1015_PWR_STATE_CTRL, 0x0088);
snd_soc_component_write(component,
RT1015_SYS_RST1, 0x05f5);
snd_soc_component_write(component,
RT1015_SYS_RST2, 0x0b9a);
}
rt1015->dac_is_used = 0;
break;
default:
break;
}
return 0;
}
static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
unsigned int ret, ret2;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = snd_soc_component_read(component, RT1015_CLK_DET);
ret2 = snd_soc_component_read(component, RT1015_SPK_DC_DETECT1);
if (!((ret >> 15) & 0x1)) {
snd_soc_component_update_bits(component, RT1015_CLK_DET,
RT1015_EN_BCLK_DET_MASK, RT1015_EN_BCLK_DET);
dev_dbg(component->dev, "BCLK Detection Enabled.\n");
}
if (!((ret2 >> 12) & 0x1)) {
snd_soc_component_update_bits(component, RT1015_SPK_DC_DETECT1,
RT1015_EN_CLA_D_DC_DET_MASK, RT1015_EN_CLA_D_DC_DET);
dev_dbg(component->dev, "Class-D DC Detection Enabled.\n");
}
break;
case SND_SOC_DAPM_POST_PMU:
msleep(rt1015->pdata.power_up_delay_ms);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
NULL, 0),
SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
r1015_dac_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPO"),
};
static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
{ "DAC", NULL, "AIFRX" },
{ "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
{ "Amp Drv", NULL, "DAC" },
{ "SPO", NULL, "Amp Drv" },
};
static int rt1015_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
int pre_div, frame_size, lrck;
unsigned int val_len = 0;
lrck = params_rate(params);
pre_div = rl6231_get_clk_info(rt1015->sysclk, lrck);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock rate\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n",
frame_size);
return -EINVAL;
}
dev_dbg(component->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
lrck, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len = RT1015_I2S_DL_20;
break;
case 24:
val_len = RT1015_I2S_DL_24;
break;
case 8:
val_len = RT1015_I2S_DL_8;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
RT1015_I2S_DL_MASK, val_len);
snd_soc_component_update_bits(component, RT1015_CLK2,
RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
return 0;
}
static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int reg_val = 0, reg_val2 = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
reg_val |= RT1015_TCON_TDM_MS_M;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT1015_TCON_TDM_MS_S;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val2 |= RT1015_TDM_INV_BCLK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT1015_I2S_M_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT1015_I2S_M_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT1015_I2S_M_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
reg_val);
snd_soc_component_update_bits(component, RT1015_TDM1_1,
RT1015_TDM_INV_BCLK_MASK, reg_val2);
return 0;
}
static int rt1015_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
return 0;
switch (clk_id) {
case RT1015_SCLK_S_MCLK:
reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
break;
case RT1015_SCLK_S_PLL:
reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
rt1015->sysclk = freq;
rt1015->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
snd_soc_component_update_bits(component, RT1015_CLK2,
RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
return 0;
}
static int rt1015_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt1015->pll_in = 0;
rt1015->pll_out = 0;
return 0;
}
if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
freq_out == rt1015->pll_out)
return 0;
switch (source) {
case RT1015_PLL_S_MCLK:
snd_soc_component_update_bits(component, RT1015_CLK2,
RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
break;
case RT1015_PLL_S_BCLK:
snd_soc_component_update_bits(component, RT1015_CLK2,
RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT1015_PLL1,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT) |
(pll_code.m_bp << RT1015_PLL_M_BP_SFT) |
pll_code.n_code);
snd_soc_component_write(component, RT1015_PLL2,
pll_code.k_code);
rt1015->pll_in = freq_in;
rt1015->pll_out = freq_out;
rt1015->pll_src = source;
return 0;
}
static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0, rx_slotnum, tx_slotnum;
int ret = 0, first_bit;
switch (slots) {
case 2:
val |= RT1015_I2S_TX_2CH;
break;
case 4:
val |= RT1015_I2S_TX_4CH;
break;
case 6:
val |= RT1015_I2S_TX_6CH;
break;
case 8:
val |= RT1015_I2S_TX_8CH;
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
switch (slot_width) {
case 16:
val |= RT1015_I2S_CH_TX_LEN_16B;
break;
case 20:
val |= RT1015_I2S_CH_TX_LEN_20B;
break;
case 24:
val |= RT1015_I2S_CH_TX_LEN_24B;
break;
case 32:
val |= RT1015_I2S_CH_TX_LEN_32B;
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
/* Rx slot configuration */
rx_slotnum = hweight_long(rx_mask);
if (rx_slotnum != 1) {
ret = -EINVAL;
dev_err(component->dev, "too many rx slots or zero slot\n");
goto _set_tdm_err_;
}
/* This is an assumption that the system sends stereo audio to the amplifier typically.
* And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
* The users could select the channel from L/R/L+R by "Mono LR Select" control.
*/
first_bit = __ffs(rx_mask);
switch (first_bit) {
case 0:
case 2:
case 4:
case 6:
snd_soc_component_update_bits(component,
RT1015_TDM1_4,
RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
(first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
break;
case 1:
case 3:
case 5:
case 7:
snd_soc_component_update_bits(component,
RT1015_TDM1_4,
RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
(first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
break;
default:
ret = -EINVAL;
goto _set_tdm_err_;
}
/* Tx slot configuration */
tx_slotnum = hweight_long(tx_mask);
if (tx_slotnum) {
ret = -EINVAL;
dev_err(component->dev, "doesn't need to support tx slots\n");
goto _set_tdm_err_;
}
snd_soc_component_update_bits(component, RT1015_TDM1_1,
RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
_set_tdm_err_:
return ret;
}
static int rt1015_probe(struct snd_soc_component *component)
{
struct rt1015_priv *rt1015 =
snd_soc_component_get_drvdata(component);
rt1015->component = component;
return 0;
}
static void rt1015_remove(struct snd_soc_component *component)
{
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
regmap_write(rt1015->regmap, RT1015_RESET, 0);
}
#define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt1015_aif_dai_ops = {
.hw_params = rt1015_hw_params,
.set_fmt = rt1015_set_dai_fmt,
.set_tdm_slot = rt1015_set_tdm_slot,
};
static struct snd_soc_dai_driver rt1015_dai[] = {
{
.name = "rt1015-aif",
.id = 0,
.playback = {
.stream_name = "AIF Playback",
.channels_min = 1,
.channels_max = 4,
.rates = RT1015_STEREO_RATES,
.formats = RT1015_FORMATS,
},
.ops = &rt1015_aif_dai_ops,
}
};
#ifdef CONFIG_PM
static int rt1015_suspend(struct snd_soc_component *component)
{
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1015->regmap, true);
regcache_mark_dirty(rt1015->regmap);
return 0;
}
static int rt1015_resume(struct snd_soc_component *component)
{
struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt1015->regmap, false);
regcache_sync(rt1015->regmap);
if (rt1015->cali_done)
rt1015_calibrate(rt1015);
return 0;
}
#else
#define rt1015_suspend NULL
#define rt1015_resume NULL
#endif
static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
.probe = rt1015_probe,
.remove = rt1015_remove,
.suspend = rt1015_suspend,
.resume = rt1015_resume,
.controls = rt1015_snd_controls,
.num_controls = ARRAY_SIZE(rt1015_snd_controls),
.dapm_widgets = rt1015_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
.dapm_routes = rt1015_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
.set_sysclk = rt1015_set_component_sysclk,
.set_pll = rt1015_set_component_pll,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt1015_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = RT1015_S_BST_TIMING_INTER36,
.volatile_reg = rt1015_volatile_register,
.readable_reg = rt1015_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt1015_reg,
.num_reg_defaults = ARRAY_SIZE(rt1015_reg),
};
static const struct i2c_device_id rt1015_i2c_id[] = {
{ "rt1015", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt1015_of_match[] = {
{ .compatible = "realtek,rt1015", },
{},
};
MODULE_DEVICE_TABLE(of, rt1015_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt1015_acpi_match[] = {
{"10EC1015", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
#endif
static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
{
device_property_read_u32(dev, "realtek,power-up-delay-ms",
&rt1015->pdata.power_up_delay_ms);
}
static int rt1015_i2c_probe(struct i2c_client *i2c)
{
struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt1015_priv *rt1015;
int ret;
unsigned int val;
rt1015 = devm_kzalloc(&i2c->dev, sizeof(*rt1015), GFP_KERNEL);
if (!rt1015)
return -ENOMEM;
i2c_set_clientdata(i2c, rt1015);
rt1015->pdata = i2s_default_platform_data;
if (pdata)
rt1015->pdata = *pdata;
else
rt1015_parse_dt(rt1015, &i2c->dev);
rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
if (IS_ERR(rt1015->regmap)) {
ret = PTR_ERR(rt1015->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
if (ret) {
dev_err(&i2c->dev,
"Failed to read device register: %d\n", ret);
return ret;
} else if ((val != RT1015_DEVICE_ID_VAL) &&
(val != RT1015_DEVICE_ID_VAL2)) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt1015\n", val);
return -ENODEV;
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt1015,
rt1015_dai, ARRAY_SIZE(rt1015_dai));
}
static void rt1015_i2c_shutdown(struct i2c_client *client)
{
struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
regmap_write(rt1015->regmap, RT1015_RESET, 0);
}
static struct i2c_driver rt1015_i2c_driver = {
.driver = {
.name = "rt1015",
.of_match_table = of_match_ptr(rt1015_of_match),
.acpi_match_table = ACPI_PTR(rt1015_acpi_match),
},
.probe = rt1015_i2c_probe,
.shutdown = rt1015_i2c_shutdown,
.id_table = rt1015_i2c_id,
};
module_i2c_driver(rt1015_i2c_driver);
MODULE_DESCRIPTION("ASoC RT1015 driver");
MODULE_AUTHOR("Jack Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt1015.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC SPDIF DIR (Digital Interface Reciever) driver
*
* Based on ALSA SoC SPDIF DIT driver
*
* This driver is used by controllers which can operate in DIR (SPDI/F) where
* no codec is needed. This file provides stub codec that can be used
* in these configurations. SPEAr SPDIF IN Audio controller uses this driver.
*
* Author: Vipin Kumar, <[email protected]>
* Copyright: (C) 2012 ST Microelectronics
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <linux/of.h>
static const struct snd_soc_dapm_widget dir_widgets[] = {
SND_SOC_DAPM_INPUT("spdif-in"),
};
static const struct snd_soc_dapm_route dir_routes[] = {
{ "Capture", NULL, "spdif-in" },
};
#define STUB_RATES SNDRV_PCM_RATE_8000_192000
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
static struct snd_soc_component_driver soc_codec_spdif_dir = {
.dapm_widgets = dir_widgets,
.num_dapm_widgets = ARRAY_SIZE(dir_widgets),
.dapm_routes = dir_routes,
.num_dapm_routes = ARRAY_SIZE(dir_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver dir_stub_dai = {
.name = "dir-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 384,
.rates = STUB_RATES,
.formats = STUB_FORMATS,
},
};
static int spdif_dir_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_codec_spdif_dir,
&dir_stub_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id spdif_dir_dt_ids[] = {
{ .compatible = "linux,spdif-dir", },
{ }
};
MODULE_DEVICE_TABLE(of, spdif_dir_dt_ids);
#endif
static struct platform_driver spdif_dir_driver = {
.probe = spdif_dir_probe,
.driver = {
.name = "spdif-dir",
.of_match_table = of_match_ptr(spdif_dir_dt_ids),
},
};
module_platform_driver(spdif_dir_driver);
MODULE_DESCRIPTION("ASoC SPDIF DIR driver");
MODULE_AUTHOR("Vipin Kumar <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/spdif_receiver.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* sound/soc/codecs/si476x.c -- Codec driver for SI476X chips
*
* Copyright (C) 2012 Innovative Converged Devices(ICD)
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <linux/i2c.h>
#include <linux/mfd/si476x-core.h>
enum si476x_audio_registers {
SI476X_DIGITAL_IO_OUTPUT_FORMAT = 0x0203,
SI476X_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202,
};
enum si476x_digital_io_output_format {
SI476X_DIGITAL_IO_SLOT_SIZE_SHIFT = 11,
SI476X_DIGITAL_IO_SAMPLE_SIZE_SHIFT = 8,
};
#define SI476X_DIGITAL_IO_OUTPUT_WIDTH_MASK ((0x7 << SI476X_DIGITAL_IO_SLOT_SIZE_SHIFT) | \
(0x7 << SI476X_DIGITAL_IO_SAMPLE_SIZE_SHIFT))
#define SI476X_DIGITAL_IO_OUTPUT_FORMAT_MASK (0x7e)
enum si476x_daudio_formats {
SI476X_DAUDIO_MODE_I2S = (0x0 << 1),
SI476X_DAUDIO_MODE_DSP_A = (0x6 << 1),
SI476X_DAUDIO_MODE_DSP_B = (0x7 << 1),
SI476X_DAUDIO_MODE_LEFT_J = (0x8 << 1),
SI476X_DAUDIO_MODE_RIGHT_J = (0x9 << 1),
SI476X_DAUDIO_MODE_IB = (1 << 5),
SI476X_DAUDIO_MODE_IF = (1 << 6),
};
enum si476x_pcm_format {
SI476X_PCM_FORMAT_S8 = 2,
SI476X_PCM_FORMAT_S16_LE = 4,
SI476X_PCM_FORMAT_S20_3LE = 5,
SI476X_PCM_FORMAT_S24_LE = 6,
};
static const struct snd_soc_dapm_widget si476x_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
};
static const struct snd_soc_dapm_route si476x_dapm_routes[] = {
{ "Capture", NULL, "LOUT" },
{ "Capture", NULL, "ROUT" },
};
static int si476x_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct si476x_core *core = i2c_mfd_cell_to_core(codec_dai->dev);
int err;
u16 format = 0;
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)
return -EINVAL;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
format |= SI476X_DAUDIO_MODE_DSP_A;
break;
case SND_SOC_DAIFMT_DSP_B:
format |= SI476X_DAUDIO_MODE_DSP_B;
break;
case SND_SOC_DAIFMT_I2S:
format |= SI476X_DAUDIO_MODE_I2S;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format |= SI476X_DAUDIO_MODE_RIGHT_J;
break;
case SND_SOC_DAIFMT_LEFT_J:
format |= SI476X_DAUDIO_MODE_LEFT_J;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
format |= SI476X_DAUDIO_MODE_IB;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
format |= SI476X_DAUDIO_MODE_IB |
SI476X_DAUDIO_MODE_IF;
break;
case SND_SOC_DAIFMT_IB_NF:
format |= SI476X_DAUDIO_MODE_IB;
break;
case SND_SOC_DAIFMT_NB_IF:
format |= SI476X_DAUDIO_MODE_IF;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
si476x_core_lock(core);
err = snd_soc_component_update_bits(codec_dai->component, SI476X_DIGITAL_IO_OUTPUT_FORMAT,
SI476X_DIGITAL_IO_OUTPUT_FORMAT_MASK,
format);
si476x_core_unlock(core);
if (err < 0) {
dev_err(codec_dai->component->dev, "Failed to set output format\n");
return err;
}
return 0;
}
static int si476x_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct si476x_core *core = i2c_mfd_cell_to_core(dai->dev);
int rate, width, err;
rate = params_rate(params);
if (rate < 32000 || rate > 48000) {
dev_err(dai->component->dev, "Rate: %d is not supported\n", rate);
return -EINVAL;
}
switch (params_width(params)) {
case 8:
width = SI476X_PCM_FORMAT_S8;
break;
case 16:
width = SI476X_PCM_FORMAT_S16_LE;
break;
case 20:
width = SI476X_PCM_FORMAT_S20_3LE;
break;
case 24:
width = SI476X_PCM_FORMAT_S24_LE;
break;
default:
return -EINVAL;
}
si476x_core_lock(core);
err = snd_soc_component_write(dai->component, SI476X_DIGITAL_IO_OUTPUT_SAMPLE_RATE,
rate);
if (err < 0) {
dev_err(dai->component->dev, "Failed to set sample rate\n");
goto out;
}
err = snd_soc_component_update_bits(dai->component, SI476X_DIGITAL_IO_OUTPUT_FORMAT,
SI476X_DIGITAL_IO_OUTPUT_WIDTH_MASK,
(width << SI476X_DIGITAL_IO_SLOT_SIZE_SHIFT) |
(width << SI476X_DIGITAL_IO_SAMPLE_SIZE_SHIFT));
if (err < 0) {
dev_err(dai->component->dev, "Failed to set output width\n");
goto out;
}
out:
si476x_core_unlock(core);
return err;
}
static const struct snd_soc_dai_ops si476x_dai_ops = {
.hw_params = si476x_codec_hw_params,
.set_fmt = si476x_codec_set_dai_fmt,
};
static struct snd_soc_dai_driver si476x_dai = {
.name = "si476x-codec",
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE
},
.ops = &si476x_dai_ops,
};
static int si476x_probe(struct snd_soc_component *component)
{
snd_soc_component_init_regmap(component,
dev_get_regmap(component->dev->parent, NULL));
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_si476x = {
.probe = si476x_probe,
.dapm_widgets = si476x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(si476x_dapm_widgets),
.dapm_routes = si476x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(si476x_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int si476x_platform_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_si476x,
&si476x_dai, 1);
}
MODULE_ALIAS("platform:si476x-codec");
static struct platform_driver si476x_platform_driver = {
.driver = {
.name = "si476x-codec",
},
.probe = si476x_platform_probe,
};
module_platform_driver(si476x_platform_driver);
MODULE_AUTHOR("Andrey Smirnov <[email protected]>");
MODULE_DESCRIPTION("ASoC Si4761/64 codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/si476x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm_hubs.c -- WM8993/4 common code
*
* Copyright 2009-12 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/mfd/wm8994/registers.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8993.h"
#include "wm_hubs.h"
const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_RANGE(spkboost_tlv,
0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
static const char *speaker_ref_text[] = {
"SPKVDD/2",
"VMID",
};
static SOC_ENUM_SINGLE_DECL(speaker_ref,
WM8993_SPEAKER_MIXER, 8, speaker_ref_text);
static const char *speaker_mode_text[] = {
"Class D",
"Class AB",
};
static SOC_ENUM_SINGLE_DECL(speaker_mode,
WM8993_SPKMIXR_ATTENUATION, 8, speaker_mode_text);
static void wait_for_dc_servo(struct snd_soc_component *component, unsigned int op)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
unsigned int reg;
int count = 0;
int timeout;
unsigned int val;
val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
/* Trigger the command */
snd_soc_component_write(component, WM8993_DC_SERVO_0, val);
dev_dbg(component->dev, "Waiting for DC servo...\n");
if (hubs->dcs_done_irq)
timeout = 4;
else
timeout = 400;
do {
count++;
if (hubs->dcs_done_irq)
wait_for_completion_timeout(&hubs->dcs_done,
msecs_to_jiffies(250));
else
msleep(1);
reg = snd_soc_component_read(component, WM8993_DC_SERVO_0);
dev_dbg(component->dev, "DC servo: %x\n", reg);
} while (reg & op && count < timeout);
if (reg & op)
dev_err(component->dev, "Timed out waiting for DC Servo %x\n",
op);
}
irqreturn_t wm_hubs_dcs_done(int irq, void *data)
{
struct wm_hubs_data *hubs = data;
complete(&hubs->dcs_done);
return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
static bool wm_hubs_dac_hp_direct(struct snd_soc_component *component)
{
int reg;
/* If we're going via the mixer we'll need to do additional checks */
reg = snd_soc_component_read(component, WM8993_OUTPUT_MIXER1);
if (!(reg & WM8993_DACL_TO_HPOUT1L)) {
if (reg & ~WM8993_DACL_TO_MIXOUTL) {
dev_vdbg(component->dev, "Analogue paths connected: %x\n",
reg & ~WM8993_DACL_TO_HPOUT1L);
return false;
} else {
dev_vdbg(component->dev, "HPL connected to mixer\n");
}
} else {
dev_vdbg(component->dev, "HPL connected to DAC\n");
}
reg = snd_soc_component_read(component, WM8993_OUTPUT_MIXER2);
if (!(reg & WM8993_DACR_TO_HPOUT1R)) {
if (reg & ~WM8993_DACR_TO_MIXOUTR) {
dev_vdbg(component->dev, "Analogue paths connected: %x\n",
reg & ~WM8993_DACR_TO_HPOUT1R);
return false;
} else {
dev_vdbg(component->dev, "HPR connected to mixer\n");
}
} else {
dev_vdbg(component->dev, "HPR connected to DAC\n");
}
return true;
}
struct wm_hubs_dcs_cache {
struct list_head list;
unsigned int left;
unsigned int right;
u16 dcs_cfg;
};
static bool wm_hubs_dcs_cache_get(struct snd_soc_component *component,
struct wm_hubs_dcs_cache **entry)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
struct wm_hubs_dcs_cache *cache;
unsigned int left, right;
left = snd_soc_component_read(component, WM8993_LEFT_OUTPUT_VOLUME);
left &= WM8993_HPOUT1L_VOL_MASK;
right = snd_soc_component_read(component, WM8993_RIGHT_OUTPUT_VOLUME);
right &= WM8993_HPOUT1R_VOL_MASK;
list_for_each_entry(cache, &hubs->dcs_cache, list) {
if (cache->left != left || cache->right != right)
continue;
*entry = cache;
return true;
}
return false;
}
static void wm_hubs_dcs_cache_set(struct snd_soc_component *component, u16 dcs_cfg)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
struct wm_hubs_dcs_cache *cache;
if (hubs->no_cache_dac_hp_direct)
return;
cache = devm_kzalloc(component->dev, sizeof(*cache), GFP_KERNEL);
if (!cache)
return;
cache->left = snd_soc_component_read(component, WM8993_LEFT_OUTPUT_VOLUME);
cache->left &= WM8993_HPOUT1L_VOL_MASK;
cache->right = snd_soc_component_read(component, WM8993_RIGHT_OUTPUT_VOLUME);
cache->right &= WM8993_HPOUT1R_VOL_MASK;
cache->dcs_cfg = dcs_cfg;
list_add_tail(&cache->list, &hubs->dcs_cache);
}
static int wm_hubs_read_dc_servo(struct snd_soc_component *component,
u16 *reg_l, u16 *reg_r)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
u16 dcs_reg, reg;
int ret = 0;
switch (hubs->dcs_readback_mode) {
case 2:
dcs_reg = WM8994_DC_SERVO_4E;
break;
case 1:
dcs_reg = WM8994_DC_SERVO_READBACK;
break;
default:
dcs_reg = WM8993_DC_SERVO_3;
break;
}
/* Different chips in the family support different readback
* methods.
*/
switch (hubs->dcs_readback_mode) {
case 0:
*reg_l = snd_soc_component_read(component, WM8993_DC_SERVO_READBACK_1)
& WM8993_DCS_INTEG_CHAN_0_MASK;
*reg_r = snd_soc_component_read(component, WM8993_DC_SERVO_READBACK_2)
& WM8993_DCS_INTEG_CHAN_1_MASK;
break;
case 2:
case 1:
reg = snd_soc_component_read(component, dcs_reg);
*reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
>> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
*reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
break;
default:
WARN(1, "Unknown DCS readback method\n");
ret = -1;
}
return ret;
}
/*
* Startup calibration of the DC servo
*/
static void enable_dc_servo(struct snd_soc_component *component)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
struct wm_hubs_dcs_cache *cache;
s8 offset;
u16 reg_l, reg_r, dcs_cfg, dcs_reg;
switch (hubs->dcs_readback_mode) {
case 2:
dcs_reg = WM8994_DC_SERVO_4E;
break;
default:
dcs_reg = WM8993_DC_SERVO_3;
break;
}
/* If we're using a digital only path and have a previously
* callibrated DC servo offset stored then use that. */
if (wm_hubs_dac_hp_direct(component) &&
wm_hubs_dcs_cache_get(component, &cache)) {
dev_dbg(component->dev, "Using cached DCS offset %x for %d,%d\n",
cache->dcs_cfg, cache->left, cache->right);
snd_soc_component_write(component, dcs_reg, cache->dcs_cfg);
wait_for_dc_servo(component,
WM8993_DCS_TRIG_DAC_WR_0 |
WM8993_DCS_TRIG_DAC_WR_1);
return;
}
if (hubs->series_startup) {
/* Set for 32 series updates */
snd_soc_component_update_bits(component, WM8993_DC_SERVO_1,
WM8993_DCS_SERIES_NO_01_MASK,
32 << WM8993_DCS_SERIES_NO_01_SHIFT);
wait_for_dc_servo(component,
WM8993_DCS_TRIG_SERIES_0 |
WM8993_DCS_TRIG_SERIES_1);
} else {
wait_for_dc_servo(component,
WM8993_DCS_TRIG_STARTUP_0 |
WM8993_DCS_TRIG_STARTUP_1);
}
if (wm_hubs_read_dc_servo(component, ®_l, ®_r) < 0)
return;
dev_dbg(component->dev, "DCS input: %x %x\n", reg_l, reg_r);
/* Apply correction to DC servo result */
if (hubs->dcs_codes_l || hubs->dcs_codes_r) {
dev_dbg(component->dev,
"Applying %d/%d code DC servo correction\n",
hubs->dcs_codes_l, hubs->dcs_codes_r);
/* HPOUT1R */
offset = (s8)reg_r;
dev_dbg(component->dev, "DCS right %d->%d\n", offset,
offset + hubs->dcs_codes_r);
offset += hubs->dcs_codes_r;
dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
/* HPOUT1L */
offset = (s8)reg_l;
dev_dbg(component->dev, "DCS left %d->%d\n", offset,
offset + hubs->dcs_codes_l);
offset += hubs->dcs_codes_l;
dcs_cfg |= (u8)offset;
dev_dbg(component->dev, "DCS result: %x\n", dcs_cfg);
/* Do it */
snd_soc_component_write(component, dcs_reg, dcs_cfg);
wait_for_dc_servo(component,
WM8993_DCS_TRIG_DAC_WR_0 |
WM8993_DCS_TRIG_DAC_WR_1);
} else {
dcs_cfg = reg_r << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
dcs_cfg |= reg_l;
}
/* Save the callibrated offset if we're in class W mode and
* therefore don't have any analogue signal mixed in. */
if (wm_hubs_dac_hp_direct(component))
wm_hubs_dcs_cache_set(component, dcs_cfg);
}
/*
* Update the DC servo calibration on gain changes
*/
static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
int ret;
ret = snd_soc_put_volsw(kcontrol, ucontrol);
/* If we're applying an offset correction then updating the
* callibration would be likely to introduce further offsets. */
if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
return ret;
/* Only need to do this if the outputs are active */
if (snd_soc_component_read(component, WM8993_POWER_MANAGEMENT_1)
& (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
snd_soc_component_update_bits(component,
WM8993_DC_SERVO_0,
WM8993_DCS_TRIG_SINGLE_0 |
WM8993_DCS_TRIG_SINGLE_1,
WM8993_DCS_TRIG_SINGLE_0 |
WM8993_DCS_TRIG_SINGLE_1);
return ret;
}
static const struct snd_kcontrol_new analogue_snd_controls[] = {
SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
inmix_tlv),
SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
inmix_tlv),
SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
inmix_tlv),
SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
inmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
5, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
4, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
3, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
5, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
4, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
3, 1, 1, wm_hubs_spkmix_tlv),
SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
0, 3, 1, spkmixout_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume",
WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
0, 63, 0, outpga_tlv),
SOC_DOUBLE_R("Speaker Switch",
WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
6, 1, 0),
SOC_DOUBLE_R("Speaker ZC Switch",
WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
7, 1, 0),
SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
spkboost_tlv),
SOC_ENUM("Speaker Reference", speaker_ref),
SOC_ENUM("Speaker Mode", speaker_mode),
SOC_DOUBLE_R_EXT_TLV("Headphone Volume",
WM8993_LEFT_OUTPUT_VOLUME, WM8993_RIGHT_OUTPUT_VOLUME,
0, 63, 0, snd_soc_get_volsw, wm8993_put_dc_servo,
outpga_tlv),
SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
line_tlv),
SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
line_tlv),
};
static int hp_supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (hubs->hp_startup_mode) {
case 0:
break;
case 1:
/* Enable the headphone amp */
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_HPOUT1L_ENA |
WM8993_HPOUT1R_ENA,
WM8993_HPOUT1L_ENA |
WM8993_HPOUT1R_ENA);
/* Enable the second stage */
snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
WM8993_HPOUT1L_DLY |
WM8993_HPOUT1R_DLY,
WM8993_HPOUT1L_DLY |
WM8993_HPOUT1R_DLY);
break;
default:
dev_err(component->dev, "Unknown HP startup mode %d\n",
hubs->hp_startup_mode);
break;
}
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, WM8993_CHARGE_PUMP_1,
WM8993_CP_ENA, 0);
break;
}
return 0;
}
static int hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int reg = snd_soc_component_read(component, WM8993_ANALOGUE_HP_0);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, WM8993_CHARGE_PUMP_1,
WM8993_CP_ENA, WM8993_CP_ENA);
msleep(5);
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
snd_soc_component_write(component, WM8993_ANALOGUE_HP_0, reg);
snd_soc_component_update_bits(component, WM8993_DC_SERVO_1,
WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
enable_dc_servo(component);
reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
snd_soc_component_write(component, WM8993_ANALOGUE_HP_0, reg);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
WM8993_HPOUT1L_OUTP |
WM8993_HPOUT1R_OUTP |
WM8993_HPOUT1L_RMV_SHORT |
WM8993_HPOUT1R_RMV_SHORT, 0);
snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
WM8993_HPOUT1L_DLY |
WM8993_HPOUT1R_DLY, 0);
snd_soc_component_write(component, WM8993_DC_SERVO_0, 0);
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
0);
break;
}
return 0;
}
static int earpiece_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *control, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 reg = snd_soc_component_read(component, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
reg |= WM8993_HPOUT2_IN_ENA;
snd_soc_component_write(component, WM8993_ANTIPOP1, reg);
udelay(50);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, WM8993_ANTIPOP1, reg);
break;
default:
WARN(1, "Invalid event %d\n", event);
break;
}
return 0;
}
static int lineout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *control, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
bool *flag;
switch (w->shift) {
case WM8993_LINEOUT1N_ENA_SHIFT:
flag = &hubs->lineout1n_ena;
break;
case WM8993_LINEOUT1P_ENA_SHIFT:
flag = &hubs->lineout1p_ena;
break;
case WM8993_LINEOUT2N_ENA_SHIFT:
flag = &hubs->lineout2n_ena;
break;
case WM8993_LINEOUT2P_ENA_SHIFT:
flag = &hubs->lineout2p_ena;
break;
default:
WARN(1, "Unknown line output");
return -EINVAL;
}
*flag = SND_SOC_DAPM_EVENT_ON(event);
return 0;
}
static int micbias_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
switch (w->shift) {
case WM8993_MICB1_ENA_SHIFT:
if (hubs->micb1_delay)
msleep(hubs->micb1_delay);
break;
case WM8993_MICB2_ENA_SHIFT:
if (hubs->micb2_delay)
msleep(hubs->micb2_delay);
break;
default:
return -EINVAL;
}
return 0;
}
void wm_hubs_update_class_w(struct snd_soc_component *component)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
int enable = WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ;
if (!wm_hubs_dac_hp_direct(component))
enable = false;
if (hubs->check_class_w_digital && !hubs->check_class_w_digital(component))
enable = false;
dev_vdbg(component->dev, "Class W %s\n", enable ? "enabled" : "disabled");
snd_soc_component_update_bits(component, WM8993_CLASS_W_0,
WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ, enable);
snd_soc_component_write(component, WM8993_LEFT_OUTPUT_VOLUME,
snd_soc_component_read(component, WM8993_LEFT_OUTPUT_VOLUME));
snd_soc_component_write(component, WM8993_RIGHT_OUTPUT_VOLUME,
snd_soc_component_read(component, WM8993_RIGHT_OUTPUT_VOLUME));
}
EXPORT_SYMBOL_GPL(wm_hubs_update_class_w);
#define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \
SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
snd_soc_dapm_get_volsw, class_w_put_volsw)
static int class_w_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
int ret;
ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
wm_hubs_update_class_w(component);
return ret;
}
#define WM_HUBS_ENUM_W(xname, xenum) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_enum_double, \
.get = snd_soc_dapm_get_enum_double, \
.put = class_w_put_double, \
.private_value = (unsigned long)&xenum }
static int class_w_put_double(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
int ret;
ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
wm_hubs_update_class_w(component);
return ret;
}
static const char *hp_mux_text[] = {
"Mixer",
"DAC",
};
static SOC_ENUM_SINGLE_DECL(hpl_enum,
WM8993_OUTPUT_MIXER1, 8, hp_mux_text);
const struct snd_kcontrol_new wm_hubs_hpl_mux =
WM_HUBS_ENUM_W("Left Headphone Mux", hpl_enum);
EXPORT_SYMBOL_GPL(wm_hubs_hpl_mux);
static SOC_ENUM_SINGLE_DECL(hpr_enum,
WM8993_OUTPUT_MIXER2, 8, hp_mux_text);
const struct snd_kcontrol_new wm_hubs_hpr_mux =
WM_HUBS_ENUM_W("Right Headphone Mux", hpr_enum);
EXPORT_SYMBOL_GPL(wm_hubs_hpr_mux);
static const struct snd_kcontrol_new in1l_pga[] = {
SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
};
static const struct snd_kcontrol_new in1r_pga[] = {
SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
};
static const struct snd_kcontrol_new in2l_pga[] = {
SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
};
static const struct snd_kcontrol_new in2r_pga[] = {
SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
};
static const struct snd_kcontrol_new mixinl[] = {
SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
};
static const struct snd_kcontrol_new mixinr[] = {
SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
};
static const struct snd_kcontrol_new left_output_mixer[] = {
WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
WM_HUBS_SINGLE_W("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new right_output_mixer[] = {
WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
WM_HUBS_SINGLE_W("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
};
static const struct snd_kcontrol_new earpiece_mixer[] = {
SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
};
static const struct snd_kcontrol_new left_speaker_boost[] = {
SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
};
static const struct snd_kcontrol_new right_speaker_boost[] = {
SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
};
static const struct snd_kcontrol_new line1_mix[] = {
SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new line1n_mix[] = {
SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
};
static const struct snd_kcontrol_new line1p_mix[] = {
SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new line2_mix[] = {
SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER2, 2, 1, 0),
SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER2, 1, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
};
static const struct snd_kcontrol_new line2n_mix[] = {
SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
};
static const struct snd_kcontrol_new line2p_mix[] = {
SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
};
static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1LN"),
SND_SOC_DAPM_INPUT("IN1LP"),
SND_SOC_DAPM_INPUT("IN2LN"),
SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
SND_SOC_DAPM_INPUT("IN1RN"),
SND_SOC_DAPM_INPUT("IN1RP"),
SND_SOC_DAPM_INPUT("IN2RN"),
SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0,
micbias_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0,
micbias_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
in1l_pga, ARRAY_SIZE(in1l_pga)),
SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
in1r_pga, ARRAY_SIZE(in1r_pga)),
SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
in2l_pga, ARRAY_SIZE(in2l_pga)),
SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
in2r_pga, ARRAY_SIZE(in2r_pga)),
SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
mixinl, ARRAY_SIZE(mixinl)),
SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
mixinr, ARRAY_SIZE(mixinr)),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
left_output_mixer, ARRAY_SIZE(left_output_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
right_output_mixer, ARRAY_SIZE(right_output_mixer)),
SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUT_DRV_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
NULL, 0, earpiece_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
SND_SOC_DAPM_SUPPLY("TSHUT", WM8993_POWER_MANAGEMENT_2, 14, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
NULL, 0),
SND_SOC_DAPM_OUT_DRV("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
line1_mix, ARRAY_SIZE(line1_mix)),
SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
line2_mix, ARRAY_SIZE(line2_mix)),
SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
line1n_mix, ARRAY_SIZE(line1n_mix)),
SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
line1p_mix, ARRAY_SIZE(line1p_mix)),
SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
line2n_mix, ARRAY_SIZE(line2n_mix)),
SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
line2p_mix, ARRAY_SIZE(line2p_mix)),
SND_SOC_DAPM_OUT_DRV_E("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
NULL, 0, lineout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUT_DRV_E("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
NULL, 0, lineout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUT_DRV_E("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
NULL, 0, lineout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUT_DRV_E("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
NULL, 0, lineout_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2P"),
SND_SOC_DAPM_OUTPUT("HPOUT2N"),
SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
};
static const struct snd_soc_dapm_route analogue_routes[] = {
{ "MICBIAS1", NULL, "CLK_SYS" },
{ "MICBIAS2", NULL, "CLK_SYS" },
{ "IN1L PGA", "IN1LP Switch", "IN1LP" },
{ "IN1L PGA", "IN1LN Switch", "IN1LN" },
{ "IN1L PGA", NULL, "VMID" },
{ "IN1R PGA", NULL, "VMID" },
{ "IN2L PGA", NULL, "VMID" },
{ "IN2R PGA", NULL, "VMID" },
{ "IN1R PGA", "IN1RP Switch", "IN1RP" },
{ "IN1R PGA", "IN1RN Switch", "IN1RN" },
{ "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
{ "IN2L PGA", "IN2LN Switch", "IN2LN" },
{ "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
{ "IN2R PGA", "IN2RN Switch", "IN2RN" },
{ "Direct Voice", NULL, "IN2LP:VXRN" },
{ "Direct Voice", NULL, "IN2RP:VXRP" },
{ "MIXINL", "IN1L Switch", "IN1L PGA" },
{ "MIXINL", "IN2L Switch", "IN2L PGA" },
{ "MIXINL", NULL, "Direct Voice" },
{ "MIXINL", NULL, "IN1LP" },
{ "MIXINL", NULL, "Left Output Mixer" },
{ "MIXINL", NULL, "VMID" },
{ "MIXINR", "IN1R Switch", "IN1R PGA" },
{ "MIXINR", "IN2R Switch", "IN2R PGA" },
{ "MIXINR", NULL, "Direct Voice" },
{ "MIXINR", NULL, "IN1RP" },
{ "MIXINR", NULL, "Right Output Mixer" },
{ "MIXINR", NULL, "VMID" },
{ "ADCL", NULL, "MIXINL" },
{ "ADCR", NULL, "MIXINR" },
{ "Left Output Mixer", "Left Input Switch", "MIXINL" },
{ "Left Output Mixer", "Right Input Switch", "MIXINR" },
{ "Left Output Mixer", "IN2RN Switch", "IN2RN" },
{ "Left Output Mixer", "IN2LN Switch", "IN2LN" },
{ "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
{ "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
{ "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
{ "Right Output Mixer", "Left Input Switch", "MIXINL" },
{ "Right Output Mixer", "Right Input Switch", "MIXINR" },
{ "Right Output Mixer", "IN2LN Switch", "IN2LN" },
{ "Right Output Mixer", "IN2RN Switch", "IN2RN" },
{ "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
{ "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
{ "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
{ "Left Output PGA", NULL, "Left Output Mixer" },
{ "Left Output PGA", NULL, "TOCLK" },
{ "Right Output PGA", NULL, "Right Output Mixer" },
{ "Right Output PGA", NULL, "TOCLK" },
{ "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
{ "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
{ "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
{ "Earpiece Driver", NULL, "VMID" },
{ "Earpiece Driver", NULL, "Earpiece Mixer" },
{ "HPOUT2N", NULL, "Earpiece Driver" },
{ "HPOUT2P", NULL, "Earpiece Driver" },
{ "SPKL", "Input Switch", "MIXINL" },
{ "SPKL", "IN1LP Switch", "IN1LP" },
{ "SPKL", "Output Switch", "Left Output PGA" },
{ "SPKL", NULL, "TOCLK" },
{ "SPKR", "Input Switch", "MIXINR" },
{ "SPKR", "IN1RP Switch", "IN1RP" },
{ "SPKR", "Output Switch", "Right Output PGA" },
{ "SPKR", NULL, "TOCLK" },
{ "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
{ "SPKL Boost", "SPKL Switch", "SPKL" },
{ "SPKL Boost", "SPKR Switch", "SPKR" },
{ "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
{ "SPKR Boost", "SPKR Switch", "SPKR" },
{ "SPKR Boost", "SPKL Switch", "SPKL" },
{ "SPKL Driver", NULL, "VMID" },
{ "SPKL Driver", NULL, "SPKL Boost" },
{ "SPKL Driver", NULL, "CLK_SYS" },
{ "SPKL Driver", NULL, "TSHUT" },
{ "SPKR Driver", NULL, "VMID" },
{ "SPKR Driver", NULL, "SPKR Boost" },
{ "SPKR Driver", NULL, "CLK_SYS" },
{ "SPKR Driver", NULL, "TSHUT" },
{ "SPKOUTLP", NULL, "SPKL Driver" },
{ "SPKOUTLN", NULL, "SPKL Driver" },
{ "SPKOUTRP", NULL, "SPKR Driver" },
{ "SPKOUTRN", NULL, "SPKR Driver" },
{ "Left Headphone Mux", "Mixer", "Left Output PGA" },
{ "Right Headphone Mux", "Mixer", "Right Output PGA" },
{ "Headphone PGA", NULL, "Left Headphone Mux" },
{ "Headphone PGA", NULL, "Right Headphone Mux" },
{ "Headphone PGA", NULL, "VMID" },
{ "Headphone PGA", NULL, "CLK_SYS" },
{ "Headphone PGA", NULL, "Headphone Supply" },
{ "HPOUT1L", NULL, "Headphone PGA" },
{ "HPOUT1R", NULL, "Headphone PGA" },
{ "LINEOUT1N Driver", NULL, "VMID" },
{ "LINEOUT1P Driver", NULL, "VMID" },
{ "LINEOUT2N Driver", NULL, "VMID" },
{ "LINEOUT2P Driver", NULL, "VMID" },
{ "LINEOUT1N", NULL, "LINEOUT1N Driver" },
{ "LINEOUT1P", NULL, "LINEOUT1P Driver" },
{ "LINEOUT2N", NULL, "LINEOUT2N Driver" },
{ "LINEOUT2P", NULL, "LINEOUT2P Driver" },
};
static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
{ "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
{ "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
{ "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
{ "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
{ "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
};
static const struct snd_soc_dapm_route lineout1_se_routes[] = {
{ "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
{ "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
{ "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
{ "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
{ "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
};
static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
{ "LINEOUT2 Mixer", "IN1L Switch", "IN1L PGA" },
{ "LINEOUT2 Mixer", "IN1R Switch", "IN1R PGA" },
{ "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
{ "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
{ "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
};
static const struct snd_soc_dapm_route lineout2_se_routes[] = {
{ "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
{ "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
{ "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
{ "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
{ "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
};
int wm_hubs_add_analogue_controls(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
/* Latch volume update bits & default ZC on */
snd_soc_component_update_bits(component, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
WM8993_IN1_VU, WM8993_IN1_VU);
snd_soc_component_update_bits(component, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8993_IN1_VU, WM8993_IN1_VU);
snd_soc_component_update_bits(component, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
WM8993_IN2_VU, WM8993_IN2_VU);
snd_soc_component_update_bits(component, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8993_IN2_VU, WM8993_IN2_VU);
snd_soc_component_update_bits(component, WM8993_SPEAKER_VOLUME_LEFT,
WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
snd_soc_component_update_bits(component, WM8993_SPEAKER_VOLUME_RIGHT,
WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
snd_soc_component_update_bits(component, WM8993_LEFT_OUTPUT_VOLUME,
WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
snd_soc_component_update_bits(component, WM8993_RIGHT_OUTPUT_VOLUME,
WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
snd_soc_component_update_bits(component, WM8993_LEFT_OPGA_VOLUME,
WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
snd_soc_component_update_bits(component, WM8993_RIGHT_OPGA_VOLUME,
WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
snd_soc_add_component_controls(component, analogue_snd_controls,
ARRAY_SIZE(analogue_snd_controls));
snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
ARRAY_SIZE(analogue_dapm_widgets));
return 0;
}
EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
int wm_hubs_add_analogue_routes(struct snd_soc_component *component,
int lineout1_diff, int lineout2_diff)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
hubs->component = component;
INIT_LIST_HEAD(&hubs->dcs_cache);
init_completion(&hubs->dcs_done);
snd_soc_dapm_add_routes(dapm, analogue_routes,
ARRAY_SIZE(analogue_routes));
if (lineout1_diff)
snd_soc_dapm_add_routes(dapm,
lineout1_diff_routes,
ARRAY_SIZE(lineout1_diff_routes));
else
snd_soc_dapm_add_routes(dapm,
lineout1_se_routes,
ARRAY_SIZE(lineout1_se_routes));
if (lineout2_diff)
snd_soc_dapm_add_routes(dapm,
lineout2_diff_routes,
ARRAY_SIZE(lineout2_diff_routes));
else
snd_soc_dapm_add_routes(dapm,
lineout2_se_routes,
ARRAY_SIZE(lineout2_se_routes));
return 0;
}
EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
int wm_hubs_handle_analogue_pdata(struct snd_soc_component *component,
int lineout1_diff, int lineout2_diff,
int lineout1fb, int lineout2fb,
int jd_scthr, int jd_thr,
int micbias1_delay, int micbias2_delay,
int micbias1_lvl, int micbias2_lvl)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
hubs->lineout1_se = !lineout1_diff;
hubs->lineout2_se = !lineout2_diff;
hubs->micb1_delay = micbias1_delay;
hubs->micb2_delay = micbias2_delay;
if (!lineout1_diff)
snd_soc_component_update_bits(component, WM8993_LINE_MIXER1,
WM8993_LINEOUT1_MODE,
WM8993_LINEOUT1_MODE);
if (!lineout2_diff)
snd_soc_component_update_bits(component, WM8993_LINE_MIXER2,
WM8993_LINEOUT2_MODE,
WM8993_LINEOUT2_MODE);
if (!lineout1_diff && !lineout2_diff)
snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
WM8993_LINEOUT_VMID_BUF_ENA,
WM8993_LINEOUT_VMID_BUF_ENA);
if (lineout1fb)
snd_soc_component_update_bits(component, WM8993_ADDITIONAL_CONTROL,
WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
if (lineout2fb)
snd_soc_component_update_bits(component, WM8993_ADDITIONAL_CONTROL,
WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
if (!hubs->micd_scthr)
return 0;
snd_soc_component_update_bits(component, WM8993_MICBIAS,
WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
WM8993_MICB1_LVL | WM8993_MICB2_LVL,
jd_scthr << WM8993_JD_SCTHR_SHIFT |
jd_thr << WM8993_JD_THR_SHIFT |
micbias1_lvl |
micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
return 0;
}
EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
void wm_hubs_vmid_ena(struct snd_soc_component *component)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
int val = 0;
if (hubs->lineout1_se)
val |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
if (hubs->lineout2_se)
val |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
/* Enable the line outputs while we power up */
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_3, val, val);
}
EXPORT_SYMBOL_GPL(wm_hubs_vmid_ena);
void wm_hubs_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
int mask, val;
switch (level) {
case SND_SOC_BIAS_STANDBY:
/* Clamp the inputs to VMID while we ramp to charge caps */
snd_soc_component_update_bits(component, WM8993_INPUTS_CLAMP_REG,
WM8993_INPUTS_CLAMP, WM8993_INPUTS_CLAMP);
break;
case SND_SOC_BIAS_ON:
/* Turn off any unneeded single ended outputs */
val = 0;
mask = 0;
if (hubs->lineout1_se)
mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
if (hubs->lineout2_se)
mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
if (hubs->lineout1_se && hubs->lineout1n_ena)
val |= WM8993_LINEOUT1N_ENA;
if (hubs->lineout1_se && hubs->lineout1p_ena)
val |= WM8993_LINEOUT1P_ENA;
if (hubs->lineout2_se && hubs->lineout2n_ena)
val |= WM8993_LINEOUT2N_ENA;
if (hubs->lineout2_se && hubs->lineout2p_ena)
val |= WM8993_LINEOUT2P_ENA;
snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_3,
mask, val);
/* Remove the input clamps */
snd_soc_component_update_bits(component, WM8993_INPUTS_CLAMP_REG,
WM8993_INPUTS_CLAMP, 0);
break;
default:
break;
}
}
EXPORT_SYMBOL_GPL(wm_hubs_set_bias_level);
MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm_hubs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8995.c -- WM8995 ALSA SoC Audio driver
*
* Copyright 2010 Wolfson Microelectronics plc
*
* Author: Dimitris Papastamos <[email protected]>
*
* Based on wm8994.c and wm_hubs.c by Mark Brown
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8995.h"
#define WM8995_NUM_SUPPLIES 8
static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD1",
"DBVDD2",
"DBVDD3",
"AVDD1",
"AVDD2",
"CPVDD",
"MICVDD"
};
static const struct reg_default wm8995_reg_defaults[] = {
{ 0, 0x8995 },
{ 5, 0x0100 },
{ 16, 0x000b },
{ 17, 0x000b },
{ 24, 0x02c0 },
{ 25, 0x02c0 },
{ 26, 0x02c0 },
{ 27, 0x02c0 },
{ 28, 0x000f },
{ 32, 0x0005 },
{ 33, 0x0005 },
{ 40, 0x0003 },
{ 41, 0x0013 },
{ 48, 0x0004 },
{ 56, 0x09f8 },
{ 64, 0x1f25 },
{ 69, 0x0004 },
{ 82, 0xaaaa },
{ 84, 0x2a2a },
{ 146, 0x0060 },
{ 256, 0x0002 },
{ 257, 0x8004 },
{ 520, 0x0010 },
{ 528, 0x0083 },
{ 529, 0x0083 },
{ 548, 0x0c80 },
{ 580, 0x0c80 },
{ 768, 0x4050 },
{ 769, 0x4000 },
{ 771, 0x0040 },
{ 772, 0x0040 },
{ 773, 0x0040 },
{ 774, 0x0004 },
{ 775, 0x0100 },
{ 784, 0x4050 },
{ 785, 0x4000 },
{ 787, 0x0040 },
{ 788, 0x0040 },
{ 789, 0x0040 },
{ 1024, 0x00c0 },
{ 1025, 0x00c0 },
{ 1026, 0x00c0 },
{ 1027, 0x00c0 },
{ 1028, 0x00c0 },
{ 1029, 0x00c0 },
{ 1030, 0x00c0 },
{ 1031, 0x00c0 },
{ 1056, 0x0200 },
{ 1057, 0x0010 },
{ 1058, 0x0200 },
{ 1059, 0x0010 },
{ 1088, 0x0098 },
{ 1089, 0x0845 },
{ 1104, 0x0098 },
{ 1105, 0x0845 },
{ 1152, 0x6318 },
{ 1153, 0x6300 },
{ 1154, 0x0fca },
{ 1155, 0x0400 },
{ 1156, 0x00d8 },
{ 1157, 0x1eb5 },
{ 1158, 0xf145 },
{ 1159, 0x0b75 },
{ 1160, 0x01c5 },
{ 1161, 0x1c58 },
{ 1162, 0xf373 },
{ 1163, 0x0a54 },
{ 1164, 0x0558 },
{ 1165, 0x168e },
{ 1166, 0xf829 },
{ 1167, 0x07ad },
{ 1168, 0x1103 },
{ 1169, 0x0564 },
{ 1170, 0x0559 },
{ 1171, 0x4000 },
{ 1184, 0x6318 },
{ 1185, 0x6300 },
{ 1186, 0x0fca },
{ 1187, 0x0400 },
{ 1188, 0x00d8 },
{ 1189, 0x1eb5 },
{ 1190, 0xf145 },
{ 1191, 0x0b75 },
{ 1192, 0x01c5 },
{ 1193, 0x1c58 },
{ 1194, 0xf373 },
{ 1195, 0x0a54 },
{ 1196, 0x0558 },
{ 1197, 0x168e },
{ 1198, 0xf829 },
{ 1199, 0x07ad },
{ 1200, 0x1103 },
{ 1201, 0x0564 },
{ 1202, 0x0559 },
{ 1203, 0x4000 },
{ 1280, 0x00c0 },
{ 1281, 0x00c0 },
{ 1282, 0x00c0 },
{ 1283, 0x00c0 },
{ 1312, 0x0200 },
{ 1313, 0x0010 },
{ 1344, 0x0098 },
{ 1345, 0x0845 },
{ 1408, 0x6318 },
{ 1409, 0x6300 },
{ 1410, 0x0fca },
{ 1411, 0x0400 },
{ 1412, 0x00d8 },
{ 1413, 0x1eb5 },
{ 1414, 0xf145 },
{ 1415, 0x0b75 },
{ 1416, 0x01c5 },
{ 1417, 0x1c58 },
{ 1418, 0xf373 },
{ 1419, 0x0a54 },
{ 1420, 0x0558 },
{ 1421, 0x168e },
{ 1422, 0xf829 },
{ 1423, 0x07ad },
{ 1424, 0x1103 },
{ 1425, 0x0564 },
{ 1426, 0x0559 },
{ 1427, 0x4000 },
{ 1568, 0x0002 },
{ 1792, 0xa100 },
{ 1793, 0xa101 },
{ 1794, 0xa101 },
{ 1795, 0xa101 },
{ 1796, 0xa101 },
{ 1797, 0xa101 },
{ 1798, 0xa101 },
{ 1799, 0xa101 },
{ 1800, 0xa101 },
{ 1801, 0xa101 },
{ 1802, 0xa101 },
{ 1803, 0xa101 },
{ 1804, 0xa101 },
{ 1805, 0xa101 },
{ 1825, 0x0055 },
{ 1848, 0x3fff },
{ 1849, 0x1fff },
{ 2049, 0x0001 },
{ 2050, 0x0069 },
{ 2056, 0x0002 },
{ 2057, 0x0003 },
{ 2058, 0x0069 },
{ 12288, 0x0001 },
{ 12289, 0x0001 },
{ 12291, 0x0006 },
{ 12292, 0x0040 },
{ 12293, 0x0001 },
{ 12294, 0x000f },
{ 12295, 0x0006 },
{ 12296, 0x0001 },
{ 12297, 0x0003 },
{ 12298, 0x0104 },
{ 12300, 0x0060 },
{ 12301, 0x0011 },
{ 12302, 0x0401 },
{ 12304, 0x0050 },
{ 12305, 0x0003 },
{ 12306, 0x0100 },
{ 12308, 0x0051 },
{ 12309, 0x0003 },
{ 12310, 0x0104 },
{ 12311, 0x000a },
{ 12312, 0x0060 },
{ 12313, 0x003b },
{ 12314, 0x0502 },
{ 12315, 0x0100 },
{ 12316, 0x2fff },
{ 12320, 0x2fff },
{ 12324, 0x2fff },
{ 12328, 0x2fff },
{ 12332, 0x2fff },
{ 12336, 0x2fff },
{ 12340, 0x2fff },
{ 12344, 0x2fff },
{ 12348, 0x2fff },
{ 12352, 0x0001 },
{ 12353, 0x0001 },
{ 12355, 0x0006 },
{ 12356, 0x0040 },
{ 12357, 0x0001 },
{ 12358, 0x000f },
{ 12359, 0x0006 },
{ 12360, 0x0001 },
{ 12361, 0x0003 },
{ 12362, 0x0104 },
{ 12364, 0x0060 },
{ 12365, 0x0011 },
{ 12366, 0x0401 },
{ 12368, 0x0050 },
{ 12369, 0x0003 },
{ 12370, 0x0100 },
{ 12372, 0x0060 },
{ 12373, 0x003b },
{ 12374, 0x0502 },
{ 12375, 0x0100 },
{ 12376, 0x2fff },
{ 12380, 0x2fff },
{ 12384, 0x2fff },
{ 12388, 0x2fff },
{ 12392, 0x2fff },
{ 12396, 0x2fff },
{ 12400, 0x2fff },
{ 12404, 0x2fff },
{ 12408, 0x2fff },
{ 12412, 0x2fff },
{ 12416, 0x0001 },
{ 12417, 0x0001 },
{ 12419, 0x0006 },
{ 12420, 0x0040 },
{ 12421, 0x0001 },
{ 12422, 0x000f },
{ 12423, 0x0006 },
{ 12424, 0x0001 },
{ 12425, 0x0003 },
{ 12426, 0x0106 },
{ 12428, 0x0061 },
{ 12429, 0x0011 },
{ 12430, 0x0401 },
{ 12432, 0x0050 },
{ 12433, 0x0003 },
{ 12434, 0x0102 },
{ 12436, 0x0051 },
{ 12437, 0x0003 },
{ 12438, 0x0106 },
{ 12439, 0x000a },
{ 12440, 0x0061 },
{ 12441, 0x003b },
{ 12442, 0x0502 },
{ 12443, 0x0100 },
{ 12444, 0x2fff },
{ 12448, 0x2fff },
{ 12452, 0x2fff },
{ 12456, 0x2fff },
{ 12460, 0x2fff },
{ 12464, 0x2fff },
{ 12468, 0x2fff },
{ 12472, 0x2fff },
{ 12476, 0x2fff },
{ 12480, 0x0001 },
{ 12481, 0x0001 },
{ 12483, 0x0006 },
{ 12484, 0x0040 },
{ 12485, 0x0001 },
{ 12486, 0x000f },
{ 12487, 0x0006 },
{ 12488, 0x0001 },
{ 12489, 0x0003 },
{ 12490, 0x0106 },
{ 12492, 0x0061 },
{ 12493, 0x0011 },
{ 12494, 0x0401 },
{ 12496, 0x0050 },
{ 12497, 0x0003 },
{ 12498, 0x0102 },
{ 12500, 0x0061 },
{ 12501, 0x003b },
{ 12502, 0x0502 },
{ 12503, 0x0100 },
{ 12504, 0x2fff },
{ 12508, 0x2fff },
{ 12512, 0x2fff },
{ 12516, 0x2fff },
{ 12520, 0x2fff },
{ 12524, 0x2fff },
{ 12528, 0x2fff },
{ 12532, 0x2fff },
{ 12536, 0x2fff },
{ 12540, 0x2fff },
{ 12544, 0x0060 },
{ 12546, 0x0601 },
{ 12548, 0x0050 },
{ 12550, 0x0100 },
{ 12552, 0x0001 },
{ 12554, 0x0104 },
{ 12555, 0x0100 },
{ 12556, 0x2fff },
{ 12560, 0x2fff },
{ 12564, 0x2fff },
{ 12568, 0x2fff },
{ 12572, 0x2fff },
{ 12576, 0x2fff },
{ 12580, 0x2fff },
{ 12584, 0x2fff },
{ 12588, 0x2fff },
{ 12592, 0x2fff },
{ 12596, 0x2fff },
{ 12600, 0x2fff },
{ 12604, 0x2fff },
{ 12608, 0x0061 },
{ 12610, 0x0601 },
{ 12612, 0x0050 },
{ 12614, 0x0102 },
{ 12616, 0x0001 },
{ 12618, 0x0106 },
{ 12619, 0x0100 },
{ 12620, 0x2fff },
{ 12624, 0x2fff },
{ 12628, 0x2fff },
{ 12632, 0x2fff },
{ 12636, 0x2fff },
{ 12640, 0x2fff },
{ 12644, 0x2fff },
{ 12648, 0x2fff },
{ 12652, 0x2fff },
{ 12656, 0x2fff },
{ 12660, 0x2fff },
{ 12664, 0x2fff },
{ 12668, 0x2fff },
{ 12672, 0x0060 },
{ 12674, 0x0601 },
{ 12676, 0x0061 },
{ 12678, 0x0601 },
{ 12680, 0x0050 },
{ 12682, 0x0300 },
{ 12684, 0x0001 },
{ 12686, 0x0304 },
{ 12688, 0x0040 },
{ 12690, 0x000f },
{ 12692, 0x0001 },
{ 12695, 0x0100 },
};
struct fll_config {
int src;
int in;
int out;
};
struct wm8995_priv {
struct regmap *regmap;
int sysclk[2];
int mclk[2];
int aifclk[2];
struct fll_config fll[2], fll_suspend[2];
struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
struct snd_soc_component *component;
};
/*
* We can't use the same notifier block for more than one supply and
* there's no way I can see to get from a callback to the caller
* except container_of().
*/
#define WM8995_REGULATOR_EVENT(n) \
static int wm8995_regulator_event_##n(struct notifier_block *nb, \
unsigned long event, void *data) \
{ \
struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
disable_nb[n]); \
if (event & REGULATOR_EVENT_DISABLE) { \
regcache_mark_dirty(wm8995->regmap); \
} \
return 0; \
}
WM8995_REGULATOR_EVENT(0)
WM8995_REGULATOR_EVENT(1)
WM8995_REGULATOR_EVENT(2)
WM8995_REGULATOR_EVENT(3)
WM8995_REGULATOR_EVENT(4)
WM8995_REGULATOR_EVENT(5)
WM8995_REGULATOR_EVENT(6)
WM8995_REGULATOR_EVENT(7)
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
static const char *in1l_text[] = {
"Differential", "Single-ended IN1LN", "Single-ended IN1LP"
};
static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
2, in1l_text);
static const char *in1r_text[] = {
"Differential", "Single-ended IN1RN", "Single-ended IN1RP"
};
static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
0, in1r_text);
static const char *dmic_src_text[] = {
"DMICDAT1", "DMICDAT2", "DMICDAT3"
};
static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
8, dmic_src_text);
static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
6, dmic_src_text);
static const struct snd_kcontrol_new wm8995_snd_controls[] = {
SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
4, 3, 0, in1l_boost_tlv),
SOC_ENUM("IN1L Mode", in1l_enum),
SOC_ENUM("IN1R Mode", in1r_enum),
SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
24, 0, sidetone_tlv),
SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
24, 0, sidetone_tlv),
SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
};
static void wm8995_update_class_w(struct snd_soc_component *component)
{
int enable = 1;
int source = 0; /* GCC flow analysis can't track enable */
int reg, reg_r;
/* We also need the same setting for L/R and only one path */
reg = snd_soc_component_read(component, WM8995_DAC1_LEFT_MIXER_ROUTING);
switch (reg) {
case WM8995_AIF2DACL_TO_DAC1L:
dev_dbg(component->dev, "Class W source AIF2DAC\n");
source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
break;
case WM8995_AIF1DAC2L_TO_DAC1L:
dev_dbg(component->dev, "Class W source AIF1DAC2\n");
source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
break;
case WM8995_AIF1DAC1L_TO_DAC1L:
dev_dbg(component->dev, "Class W source AIF1DAC1\n");
source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
break;
default:
dev_dbg(component->dev, "DAC mixer setting: %x\n", reg);
enable = 0;
break;
}
reg_r = snd_soc_component_read(component, WM8995_DAC1_RIGHT_MIXER_ROUTING);
if (reg_r != reg) {
dev_dbg(component->dev, "Left and right DAC mixers different\n");
enable = 0;
}
if (enable) {
dev_dbg(component->dev, "Class W enabled\n");
snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
WM8995_CP_DYN_PWR_MASK |
WM8995_CP_DYN_SRC_SEL_MASK,
source | WM8995_CP_DYN_PWR);
} else {
dev_dbg(component->dev, "Class W disabled\n");
snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
WM8995_CP_DYN_PWR_MASK, 0);
}
}
static int check_clk_sys(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
unsigned int reg;
const char *clk;
reg = snd_soc_component_read(component, WM8995_CLOCKING_1);
/* Check what we're currently using for CLK_SYS */
if (reg & WM8995_SYSCLK_SRC)
clk = "AIF2CLK";
else
clk = "AIF1CLK";
return !strcmp(source->name, clk);
}
static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
int ret;
ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
wm8995_update_class_w(component);
return ret;
}
static int hp_supply_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Enable the headphone amp */
snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
WM8995_HPOUT1L_ENA_MASK |
WM8995_HPOUT1R_ENA_MASK,
WM8995_HPOUT1L_ENA |
WM8995_HPOUT1R_ENA);
/* Enable the second stage */
snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
WM8995_HPOUT1L_DLY_MASK |
WM8995_HPOUT1R_DLY_MASK,
WM8995_HPOUT1L_DLY |
WM8995_HPOUT1R_DLY);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
WM8995_CP_ENA_MASK, 0);
break;
}
return 0;
}
static void dc_servo_cmd(struct snd_soc_component *component,
unsigned int reg, unsigned int val, unsigned int mask)
{
int timeout = 10;
dev_dbg(component->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
__func__, reg, val, mask);
snd_soc_component_write(component, reg, val);
while (timeout--) {
msleep(10);
val = snd_soc_component_read(component, WM8995_DC_SERVO_READBACK_0);
if ((val & mask) == mask)
return;
}
dev_err(component->dev, "Timed out waiting for DC Servo\n");
}
static int hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int reg;
reg = snd_soc_component_read(component, WM8995_ANALOGUE_HP_1);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
WM8995_CP_ENA_MASK, WM8995_CP_ENA);
msleep(5);
snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
WM8995_HPOUT1L_ENA_MASK |
WM8995_HPOUT1R_ENA_MASK,
WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
udelay(20);
reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
snd_soc_component_write(component, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
WM8995_DCS_ENA_CHAN_1);
dc_servo_cmd(component, WM8995_DC_SERVO_2,
WM8995_DCS_TRIG_STARTUP_0 |
WM8995_DCS_TRIG_STARTUP_1,
WM8995_DCS_TRIG_DAC_WR_0 |
WM8995_DCS_TRIG_DAC_WR_1);
reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
WM8995_HPOUT1L_OUTP_MASK |
WM8995_HPOUT1R_OUTP_MASK |
WM8995_HPOUT1L_RMV_SHORT_MASK |
WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
WM8995_HPOUT1L_DLY_MASK |
WM8995_HPOUT1R_DLY_MASK, 0);
snd_soc_component_write(component, WM8995_DC_SERVO_1, 0);
snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
WM8995_HPOUT1L_ENA_MASK |
WM8995_HPOUT1R_ENA_MASK,
0);
break;
}
return 0;
}
static int configure_aif_clock(struct snd_soc_component *component, int aif)
{
struct wm8995_priv *wm8995;
int rate;
int reg1 = 0;
int offset;
wm8995 = snd_soc_component_get_drvdata(component);
if (aif)
offset = 4;
else
offset = 0;
switch (wm8995->sysclk[aif]) {
case WM8995_SYSCLK_MCLK1:
rate = wm8995->mclk[0];
break;
case WM8995_SYSCLK_MCLK2:
reg1 |= 0x8;
rate = wm8995->mclk[1];
break;
case WM8995_SYSCLK_FLL1:
reg1 |= 0x10;
rate = wm8995->fll[0].out;
break;
case WM8995_SYSCLK_FLL2:
reg1 |= 0x18;
rate = wm8995->fll[1].out;
break;
default:
return -EINVAL;
}
if (rate >= 13500000) {
rate /= 2;
reg1 |= WM8995_AIF1CLK_DIV;
dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
aif + 1, rate);
}
wm8995->aifclk[aif] = rate;
snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1 + offset,
WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
reg1);
return 0;
}
static int configure_clock(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct wm8995_priv *wm8995;
int change, new;
wm8995 = snd_soc_component_get_drvdata(component);
/* Bring up the AIF clocks first */
configure_aif_clock(component, 0);
configure_aif_clock(component, 1);
/*
* Then switch CLK_SYS over to the higher of them; a change
* can only happen as a result of a clocking change which can
* only be made outside of DAPM so we can safely redo the
* clocking.
*/
/* If they're equal it doesn't matter which is used */
if (wm8995->aifclk[0] == wm8995->aifclk[1])
return 0;
if (wm8995->aifclk[0] < wm8995->aifclk[1])
new = WM8995_SYSCLK_SRC;
else
new = 0;
change = snd_soc_component_update_bits(component, WM8995_CLOCKING_1,
WM8995_SYSCLK_SRC_MASK, new);
if (!change)
return 0;
snd_soc_dapm_sync(dapm);
return 0;
}
static int clk_sys_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return configure_clock(component);
case SND_SOC_DAPM_POST_PMD:
configure_clock(component);
break;
}
return 0;
}
static const char *sidetone_text[] = {
"ADC/DMIC1", "DMIC2",
};
static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text);
static const struct snd_kcontrol_new sidetone1_mux =
SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text);
static const struct snd_kcontrol_new sidetone2_mux =
SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
static const struct snd_kcontrol_new aif1adc1l_mix[] = {
SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif1adc1r_mix[] = {
SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif1adc2l_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif1adc2r_mix[] = {
SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new dac1l_mix[] = {
WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
5, 1, 0),
WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
4, 1, 0),
WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
2, 1, 0),
WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
1, 1, 0),
WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new dac1r_mix[] = {
WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
5, 1, 0),
WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
4, 1, 0),
WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
2, 1, 0),
WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
1, 1, 0),
WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif2dac2l_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
2, 1, 0),
SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new aif2dac2r_mix[] = {
SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
5, 1, 0),
SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
4, 1, 0),
SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
2, 1, 0),
SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
1, 1, 0),
SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
0, 1, 0),
};
static const struct snd_kcontrol_new in1l_pga =
SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
static const struct snd_kcontrol_new in1r_pga =
SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
static const char *adc_mux_text[] = {
"ADC",
"DMIC",
};
static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
static const struct snd_kcontrol_new adcl_mux =
SOC_DAPM_ENUM("ADCL Mux", adc_enum);
static const struct snd_kcontrol_new adcr_mux =
SOC_DAPM_ENUM("ADCR Mux", adc_enum);
static const char *spk_src_text[] = {
"DAC1L", "DAC1R", "DAC2L", "DAC2R"
};
static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
0, spk_src_text);
static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
0, spk_src_text);
static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
0, spk_src_text);
static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
0, spk_src_text);
static const struct snd_kcontrol_new spk1l_mux =
SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
static const struct snd_kcontrol_new spk1r_mux =
SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
static const struct snd_kcontrol_new spk2l_mux =
SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
static const struct snd_kcontrol_new spk2r_mux =
SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("DMIC1DAT"),
SND_SOC_DAPM_INPUT("DMIC2DAT"),
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
&in1l_pga, 1),
SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
&in1r_pga, 1),
SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
WM8995_POWER_MANAGEMENT_3, 9, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
WM8995_POWER_MANAGEMENT_3, 8, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
0, WM8995_POWER_MANAGEMENT_3, 11, 0),
SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
0, WM8995_POWER_MANAGEMENT_3, 10, 0),
SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux),
SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
9, 0),
SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
8, 0),
SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
11, 0),
SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
10, 0),
SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
ARRAY_SIZE(dac1l_mix)),
SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
ARRAY_SIZE(dac1r_mix)),
SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
4, 0, &spk1l_mux),
SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
4, 0, &spk1r_mux),
SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
4, 0, &spk2l_mux),
SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
4, 0, &spk2r_mux),
SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HP1L"),
SND_SOC_DAPM_OUTPUT("HP1R"),
SND_SOC_DAPM_OUTPUT("SPK1L"),
SND_SOC_DAPM_OUTPUT("SPK1R"),
SND_SOC_DAPM_OUTPUT("SPK2L"),
SND_SOC_DAPM_OUTPUT("SPK2R")
};
static const struct snd_soc_dapm_route wm8995_intercon[] = {
{ "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
{ "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
{ "DSP1CLK", NULL, "CLK_SYS" },
{ "DSP2CLK", NULL, "CLK_SYS" },
{ "SYSDSPCLK", NULL, "CLK_SYS" },
{ "AIF1ADC1L", NULL, "AIF1CLK" },
{ "AIF1ADC1L", NULL, "DSP1CLK" },
{ "AIF1ADC1R", NULL, "AIF1CLK" },
{ "AIF1ADC1R", NULL, "DSP1CLK" },
{ "AIF1ADC1R", NULL, "SYSDSPCLK" },
{ "AIF1ADC2L", NULL, "AIF1CLK" },
{ "AIF1ADC2L", NULL, "DSP1CLK" },
{ "AIF1ADC2R", NULL, "AIF1CLK" },
{ "AIF1ADC2R", NULL, "DSP1CLK" },
{ "AIF1ADC2R", NULL, "SYSDSPCLK" },
{ "DMIC1L", NULL, "DMIC1DAT" },
{ "DMIC1L", NULL, "CLK_SYS" },
{ "DMIC1R", NULL, "DMIC1DAT" },
{ "DMIC1R", NULL, "CLK_SYS" },
{ "DMIC2L", NULL, "DMIC2DAT" },
{ "DMIC2L", NULL, "CLK_SYS" },
{ "DMIC2R", NULL, "DMIC2DAT" },
{ "DMIC2R", NULL, "CLK_SYS" },
{ "ADCL", NULL, "AIF1CLK" },
{ "ADCL", NULL, "DSP1CLK" },
{ "ADCL", NULL, "SYSDSPCLK" },
{ "ADCR", NULL, "AIF1CLK" },
{ "ADCR", NULL, "DSP1CLK" },
{ "ADCR", NULL, "SYSDSPCLK" },
{ "IN1L PGA", "IN1L Switch", "IN1L" },
{ "IN1R PGA", "IN1R Switch", "IN1R" },
{ "IN1L PGA", NULL, "LDO2" },
{ "IN1R PGA", NULL, "LDO2" },
{ "ADCL", NULL, "IN1L PGA" },
{ "ADCR", NULL, "IN1R PGA" },
{ "ADCL Mux", "ADC", "ADCL" },
{ "ADCL Mux", "DMIC", "DMIC1L" },
{ "ADCR Mux", "ADC", "ADCR" },
{ "ADCR Mux", "DMIC", "DMIC1R" },
/* AIF1 outputs */
{ "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
{ "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
{ "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
{ "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
{ "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
{ "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
{ "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
{ "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
/* Sidetone */
{ "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
{ "Left Sidetone", "DMIC2", "AIF1ADC2L" },
{ "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
{ "Right Sidetone", "DMIC2", "AIF1ADC2R" },
{ "AIF1DAC1L", NULL, "AIF1CLK" },
{ "AIF1DAC1L", NULL, "DSP1CLK" },
{ "AIF1DAC1R", NULL, "AIF1CLK" },
{ "AIF1DAC1R", NULL, "DSP1CLK" },
{ "AIF1DAC1R", NULL, "SYSDSPCLK" },
{ "AIF1DAC2L", NULL, "AIF1CLK" },
{ "AIF1DAC2L", NULL, "DSP1CLK" },
{ "AIF1DAC2R", NULL, "AIF1CLK" },
{ "AIF1DAC2R", NULL, "DSP1CLK" },
{ "AIF1DAC2R", NULL, "SYSDSPCLK" },
{ "DAC1L", NULL, "AIF1CLK" },
{ "DAC1L", NULL, "DSP1CLK" },
{ "DAC1L", NULL, "SYSDSPCLK" },
{ "DAC1R", NULL, "AIF1CLK" },
{ "DAC1R", NULL, "DSP1CLK" },
{ "DAC1R", NULL, "SYSDSPCLK" },
{ "AIF1DAC1L", NULL, "AIF1DACDAT" },
{ "AIF1DAC1R", NULL, "AIF1DACDAT" },
{ "AIF1DAC2L", NULL, "AIF1DACDAT" },
{ "AIF1DAC2R", NULL, "AIF1DACDAT" },
/* DAC1 inputs */
{ "DAC1L", NULL, "DAC1L Mixer" },
{ "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
{ "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
{ "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
{ "DAC1R", NULL, "DAC1R Mixer" },
{ "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
{ "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
{ "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
{ "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
/* DAC2/AIF2 outputs */
{ "DAC2L", NULL, "AIF2DAC2L Mixer" },
{ "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
{ "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
{ "DAC2R", NULL, "AIF2DAC2R Mixer" },
{ "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
{ "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
/* Output stages */
{ "Headphone PGA", NULL, "DAC1L" },
{ "Headphone PGA", NULL, "DAC1R" },
{ "Headphone PGA", NULL, "DAC2L" },
{ "Headphone PGA", NULL, "DAC2R" },
{ "Headphone PGA", NULL, "Headphone Supply" },
{ "Headphone PGA", NULL, "CLK_SYS" },
{ "Headphone PGA", NULL, "LDO2" },
{ "HP1L", NULL, "Headphone PGA" },
{ "HP1R", NULL, "Headphone PGA" },
{ "SPK1L Driver", "DAC1L", "DAC1L" },
{ "SPK1L Driver", "DAC1R", "DAC1R" },
{ "SPK1L Driver", "DAC2L", "DAC2L" },
{ "SPK1L Driver", "DAC2R", "DAC2R" },
{ "SPK1L Driver", NULL, "CLK_SYS" },
{ "SPK1R Driver", "DAC1L", "DAC1L" },
{ "SPK1R Driver", "DAC1R", "DAC1R" },
{ "SPK1R Driver", "DAC2L", "DAC2L" },
{ "SPK1R Driver", "DAC2R", "DAC2R" },
{ "SPK1R Driver", NULL, "CLK_SYS" },
{ "SPK2L Driver", "DAC1L", "DAC1L" },
{ "SPK2L Driver", "DAC1R", "DAC1R" },
{ "SPK2L Driver", "DAC2L", "DAC2L" },
{ "SPK2L Driver", "DAC2R", "DAC2R" },
{ "SPK2L Driver", NULL, "CLK_SYS" },
{ "SPK2R Driver", "DAC1L", "DAC1L" },
{ "SPK2R Driver", "DAC1R", "DAC1R" },
{ "SPK2R Driver", "DAC2L", "DAC2L" },
{ "SPK2R Driver", "DAC2R", "DAC2R" },
{ "SPK2R Driver", NULL, "CLK_SYS" },
{ "SPK1L", NULL, "SPK1L Driver" },
{ "SPK1R", NULL, "SPK1R Driver" },
{ "SPK2L", NULL, "SPK2L Driver" },
{ "SPK2R", NULL, "SPK2R Driver" }
};
static bool wm8995_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8995_SOFTWARE_RESET:
case WM8995_POWER_MANAGEMENT_1:
case WM8995_POWER_MANAGEMENT_2:
case WM8995_POWER_MANAGEMENT_3:
case WM8995_POWER_MANAGEMENT_4:
case WM8995_POWER_MANAGEMENT_5:
case WM8995_LEFT_LINE_INPUT_1_VOLUME:
case WM8995_RIGHT_LINE_INPUT_1_VOLUME:
case WM8995_LEFT_LINE_INPUT_CONTROL:
case WM8995_DAC1_LEFT_VOLUME:
case WM8995_DAC1_RIGHT_VOLUME:
case WM8995_DAC2_LEFT_VOLUME:
case WM8995_DAC2_RIGHT_VOLUME:
case WM8995_OUTPUT_VOLUME_ZC_1:
case WM8995_MICBIAS_1:
case WM8995_MICBIAS_2:
case WM8995_LDO_1:
case WM8995_LDO_2:
case WM8995_ACCESSORY_DETECT_MODE1:
case WM8995_ACCESSORY_DETECT_MODE2:
case WM8995_HEADPHONE_DETECT1:
case WM8995_HEADPHONE_DETECT2:
case WM8995_MIC_DETECT_1:
case WM8995_MIC_DETECT_2:
case WM8995_CHARGE_PUMP_1:
case WM8995_CLASS_W_1:
case WM8995_DC_SERVO_1:
case WM8995_DC_SERVO_2:
case WM8995_DC_SERVO_3:
case WM8995_DC_SERVO_5:
case WM8995_DC_SERVO_6:
case WM8995_DC_SERVO_7:
case WM8995_DC_SERVO_READBACK_0:
case WM8995_ANALOGUE_HP_1:
case WM8995_ANALOGUE_HP_2:
case WM8995_CHIP_REVISION:
case WM8995_CONTROL_INTERFACE_1:
case WM8995_CONTROL_INTERFACE_2:
case WM8995_WRITE_SEQUENCER_CTRL_1:
case WM8995_WRITE_SEQUENCER_CTRL_2:
case WM8995_AIF1_CLOCKING_1:
case WM8995_AIF1_CLOCKING_2:
case WM8995_AIF2_CLOCKING_1:
case WM8995_AIF2_CLOCKING_2:
case WM8995_CLOCKING_1:
case WM8995_CLOCKING_2:
case WM8995_AIF1_RATE:
case WM8995_AIF2_RATE:
case WM8995_RATE_STATUS:
case WM8995_FLL1_CONTROL_1:
case WM8995_FLL1_CONTROL_2:
case WM8995_FLL1_CONTROL_3:
case WM8995_FLL1_CONTROL_4:
case WM8995_FLL1_CONTROL_5:
case WM8995_FLL2_CONTROL_1:
case WM8995_FLL2_CONTROL_2:
case WM8995_FLL2_CONTROL_3:
case WM8995_FLL2_CONTROL_4:
case WM8995_FLL2_CONTROL_5:
case WM8995_AIF1_CONTROL_1:
case WM8995_AIF1_CONTROL_2:
case WM8995_AIF1_MASTER_SLAVE:
case WM8995_AIF1_BCLK:
case WM8995_AIF1ADC_LRCLK:
case WM8995_AIF1DAC_LRCLK:
case WM8995_AIF1DAC_DATA:
case WM8995_AIF1ADC_DATA:
case WM8995_AIF2_CONTROL_1:
case WM8995_AIF2_CONTROL_2:
case WM8995_AIF2_MASTER_SLAVE:
case WM8995_AIF2_BCLK:
case WM8995_AIF2ADC_LRCLK:
case WM8995_AIF2DAC_LRCLK:
case WM8995_AIF2DAC_DATA:
case WM8995_AIF2ADC_DATA:
case WM8995_AIF1_ADC1_LEFT_VOLUME:
case WM8995_AIF1_ADC1_RIGHT_VOLUME:
case WM8995_AIF1_DAC1_LEFT_VOLUME:
case WM8995_AIF1_DAC1_RIGHT_VOLUME:
case WM8995_AIF1_ADC2_LEFT_VOLUME:
case WM8995_AIF1_ADC2_RIGHT_VOLUME:
case WM8995_AIF1_DAC2_LEFT_VOLUME:
case WM8995_AIF1_DAC2_RIGHT_VOLUME:
case WM8995_AIF1_ADC1_FILTERS:
case WM8995_AIF1_ADC2_FILTERS:
case WM8995_AIF1_DAC1_FILTERS_1:
case WM8995_AIF1_DAC1_FILTERS_2:
case WM8995_AIF1_DAC2_FILTERS_1:
case WM8995_AIF1_DAC2_FILTERS_2:
case WM8995_AIF1_DRC1_1:
case WM8995_AIF1_DRC1_2:
case WM8995_AIF1_DRC1_3:
case WM8995_AIF1_DRC1_4:
case WM8995_AIF1_DRC1_5:
case WM8995_AIF1_DRC2_1:
case WM8995_AIF1_DRC2_2:
case WM8995_AIF1_DRC2_3:
case WM8995_AIF1_DRC2_4:
case WM8995_AIF1_DRC2_5:
case WM8995_AIF1_DAC1_EQ_GAINS_1:
case WM8995_AIF1_DAC1_EQ_GAINS_2:
case WM8995_AIF1_DAC1_EQ_BAND_1_A:
case WM8995_AIF1_DAC1_EQ_BAND_1_B:
case WM8995_AIF1_DAC1_EQ_BAND_1_PG:
case WM8995_AIF1_DAC1_EQ_BAND_2_A:
case WM8995_AIF1_DAC1_EQ_BAND_2_B:
case WM8995_AIF1_DAC1_EQ_BAND_2_C:
case WM8995_AIF1_DAC1_EQ_BAND_2_PG:
case WM8995_AIF1_DAC1_EQ_BAND_3_A:
case WM8995_AIF1_DAC1_EQ_BAND_3_B:
case WM8995_AIF1_DAC1_EQ_BAND_3_C:
case WM8995_AIF1_DAC1_EQ_BAND_3_PG:
case WM8995_AIF1_DAC1_EQ_BAND_4_A:
case WM8995_AIF1_DAC1_EQ_BAND_4_B:
case WM8995_AIF1_DAC1_EQ_BAND_4_C:
case WM8995_AIF1_DAC1_EQ_BAND_4_PG:
case WM8995_AIF1_DAC1_EQ_BAND_5_A:
case WM8995_AIF1_DAC1_EQ_BAND_5_B:
case WM8995_AIF1_DAC1_EQ_BAND_5_PG:
case WM8995_AIF1_DAC2_EQ_GAINS_1:
case WM8995_AIF1_DAC2_EQ_GAINS_2:
case WM8995_AIF1_DAC2_EQ_BAND_1_A:
case WM8995_AIF1_DAC2_EQ_BAND_1_B:
case WM8995_AIF1_DAC2_EQ_BAND_1_PG:
case WM8995_AIF1_DAC2_EQ_BAND_2_A:
case WM8995_AIF1_DAC2_EQ_BAND_2_B:
case WM8995_AIF1_DAC2_EQ_BAND_2_C:
case WM8995_AIF1_DAC2_EQ_BAND_2_PG:
case WM8995_AIF1_DAC2_EQ_BAND_3_A:
case WM8995_AIF1_DAC2_EQ_BAND_3_B:
case WM8995_AIF1_DAC2_EQ_BAND_3_C:
case WM8995_AIF1_DAC2_EQ_BAND_3_PG:
case WM8995_AIF1_DAC2_EQ_BAND_4_A:
case WM8995_AIF1_DAC2_EQ_BAND_4_B:
case WM8995_AIF1_DAC2_EQ_BAND_4_C:
case WM8995_AIF1_DAC2_EQ_BAND_4_PG:
case WM8995_AIF1_DAC2_EQ_BAND_5_A:
case WM8995_AIF1_DAC2_EQ_BAND_5_B:
case WM8995_AIF1_DAC2_EQ_BAND_5_PG:
case WM8995_AIF2_ADC_LEFT_VOLUME:
case WM8995_AIF2_ADC_RIGHT_VOLUME:
case WM8995_AIF2_DAC_LEFT_VOLUME:
case WM8995_AIF2_DAC_RIGHT_VOLUME:
case WM8995_AIF2_ADC_FILTERS:
case WM8995_AIF2_DAC_FILTERS_1:
case WM8995_AIF2_DAC_FILTERS_2:
case WM8995_AIF2_DRC_1:
case WM8995_AIF2_DRC_2:
case WM8995_AIF2_DRC_3:
case WM8995_AIF2_DRC_4:
case WM8995_AIF2_DRC_5:
case WM8995_AIF2_EQ_GAINS_1:
case WM8995_AIF2_EQ_GAINS_2:
case WM8995_AIF2_EQ_BAND_1_A:
case WM8995_AIF2_EQ_BAND_1_B:
case WM8995_AIF2_EQ_BAND_1_PG:
case WM8995_AIF2_EQ_BAND_2_A:
case WM8995_AIF2_EQ_BAND_2_B:
case WM8995_AIF2_EQ_BAND_2_C:
case WM8995_AIF2_EQ_BAND_2_PG:
case WM8995_AIF2_EQ_BAND_3_A:
case WM8995_AIF2_EQ_BAND_3_B:
case WM8995_AIF2_EQ_BAND_3_C:
case WM8995_AIF2_EQ_BAND_3_PG:
case WM8995_AIF2_EQ_BAND_4_A:
case WM8995_AIF2_EQ_BAND_4_B:
case WM8995_AIF2_EQ_BAND_4_C:
case WM8995_AIF2_EQ_BAND_4_PG:
case WM8995_AIF2_EQ_BAND_5_A:
case WM8995_AIF2_EQ_BAND_5_B:
case WM8995_AIF2_EQ_BAND_5_PG:
case WM8995_DAC1_MIXER_VOLUMES:
case WM8995_DAC1_LEFT_MIXER_ROUTING:
case WM8995_DAC1_RIGHT_MIXER_ROUTING:
case WM8995_DAC2_MIXER_VOLUMES:
case WM8995_DAC2_LEFT_MIXER_ROUTING:
case WM8995_DAC2_RIGHT_MIXER_ROUTING:
case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING:
case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING:
case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING:
case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING:
case WM8995_DAC_SOFTMUTE:
case WM8995_OVERSAMPLING:
case WM8995_SIDETONE:
case WM8995_GPIO_1:
case WM8995_GPIO_2:
case WM8995_GPIO_3:
case WM8995_GPIO_4:
case WM8995_GPIO_5:
case WM8995_GPIO_6:
case WM8995_GPIO_7:
case WM8995_GPIO_8:
case WM8995_GPIO_9:
case WM8995_GPIO_10:
case WM8995_GPIO_11:
case WM8995_GPIO_12:
case WM8995_GPIO_13:
case WM8995_GPIO_14:
case WM8995_PULL_CONTROL_1:
case WM8995_PULL_CONTROL_2:
case WM8995_INTERRUPT_STATUS_1:
case WM8995_INTERRUPT_STATUS_2:
case WM8995_INTERRUPT_RAW_STATUS_2:
case WM8995_INTERRUPT_STATUS_1_MASK:
case WM8995_INTERRUPT_STATUS_2_MASK:
case WM8995_INTERRUPT_CONTROL:
case WM8995_LEFT_PDM_SPEAKER_1:
case WM8995_RIGHT_PDM_SPEAKER_1:
case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE:
case WM8995_LEFT_PDM_SPEAKER_2:
case WM8995_RIGHT_PDM_SPEAKER_2:
case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE:
return true;
default:
return false;
}
}
static bool wm8995_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8995_SOFTWARE_RESET:
case WM8995_DC_SERVO_READBACK_0:
case WM8995_INTERRUPT_STATUS_1:
case WM8995_INTERRUPT_STATUS_2:
case WM8995_INTERRUPT_CONTROL:
case WM8995_ACCESSORY_DETECT_MODE1:
case WM8995_ACCESSORY_DETECT_MODE2:
case WM8995_HEADPHONE_DETECT1:
case WM8995_HEADPHONE_DETECT2:
case WM8995_RATE_STATUS:
return true;
default:
return false;
}
}
static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
int mute_reg;
switch (dai->id) {
case 0:
mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
break;
case 1:
mute_reg = WM8995_AIF2_DAC_FILTERS_1;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
!!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
return 0;
}
static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component;
int master;
int aif;
component = dai->component;
master = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
master = WM8995_AIF1_MSTR;
break;
default:
dev_err(dai->dev, "Unknown master/slave configuration\n");
return -EINVAL;
}
aif = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif |= WM8995_AIF1_LRCLK_INV;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
break;
case SND_SOC_DAIFMT_I2S:
aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
break;
default:
dev_err(dai->dev, "Unknown dai format\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif |= WM8995_AIF1_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif |= WM8995_AIF1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif |= WM8995_AIF1_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8995_AIF1_CONTROL_1,
WM8995_AIF1_BCLK_INV_MASK |
WM8995_AIF1_LRCLK_INV_MASK |
WM8995_AIF1_FMT_MASK, aif);
snd_soc_component_update_bits(component, WM8995_AIF1_MASTER_SLAVE,
WM8995_AIF1_MSTR_MASK, master);
return 0;
}
static const int srs[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
48000, 88200, 96000
};
static const int fs_ratios[] = {
-1 /* reserved */,
128, 192, 256, 384, 512, 768, 1024, 1408, 1536
};
static const int bclk_divs[] = {
10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
};
static int wm8995_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component;
struct wm8995_priv *wm8995;
int aif1_reg;
int bclk_reg;
int lrclk_reg;
int rate_reg;
int bclk_rate;
int aif1;
int lrclk, bclk;
int i, rate_val, best, best_val, cur_val;
component = dai->component;
wm8995 = snd_soc_component_get_drvdata(component);
switch (dai->id) {
case 0:
aif1_reg = WM8995_AIF1_CONTROL_1;
bclk_reg = WM8995_AIF1_BCLK;
rate_reg = WM8995_AIF1_RATE;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
wm8995->lrclk_shared[0] */) {
lrclk_reg = WM8995_AIF1DAC_LRCLK;
} else {
lrclk_reg = WM8995_AIF1ADC_LRCLK;
dev_dbg(component->dev, "AIF1 using split LRCLK\n");
}
break;
case 1:
aif1_reg = WM8995_AIF2_CONTROL_1;
bclk_reg = WM8995_AIF2_BCLK;
rate_reg = WM8995_AIF2_RATE;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
wm8995->lrclk_shared[1] */) {
lrclk_reg = WM8995_AIF2DAC_LRCLK;
} else {
lrclk_reg = WM8995_AIF2ADC_LRCLK;
dev_dbg(component->dev, "AIF2 using split LRCLK\n");
}
break;
default:
return -EINVAL;
}
bclk_rate = snd_soc_params_to_bclk(params);
if (bclk_rate < 0)
return bclk_rate;
aif1 = 0;
switch (params_width(params)) {
case 16:
break;
case 20:
aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
break;
case 24:
aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
break;
case 32:
aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
break;
default:
dev_err(dai->dev, "Unsupported word length %u\n",
params_width(params));
return -EINVAL;
}
/* try to find a suitable sample rate */
for (i = 0; i < ARRAY_SIZE(srs); ++i)
if (srs[i] == params_rate(params))
break;
if (i == ARRAY_SIZE(srs)) {
dev_err(dai->dev, "Sample rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
rate_val = i << WM8995_AIF1_SR_SHIFT;
dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
/* AIFCLK/fs ratio; look for a close match in either direction */
best = 1;
best_val = abs((fs_ratios[1] * params_rate(params))
- wm8995->aifclk[dai->id]);
for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
cur_val = abs((fs_ratios[i] * params_rate(params))
- wm8995->aifclk[dai->id]);
if (cur_val >= best_val)
continue;
best = i;
best_val = cur_val;
}
rate_val |= best;
dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
dai->id + 1, fs_ratios[best]);
/*
* We may not get quite the right frequency if using
* approximate clocks so look for the closest match that is
* higher than the target (we need to ensure that there enough
* BCLKs to clock out the samples).
*/
best = 0;
bclk = 0;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
if (cur_val < 0) /* BCLK table is sorted */
break;
best = i;
}
bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
bclk_divs[best], bclk_rate);
lrclk = bclk_rate / params_rate(params);
dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
lrclk, bclk_rate / lrclk);
snd_soc_component_update_bits(component, aif1_reg,
WM8995_AIF1_WL_MASK, aif1);
snd_soc_component_update_bits(component, bclk_reg,
WM8995_AIF1_BCLK_DIV_MASK, bclk);
snd_soc_component_update_bits(component, lrclk_reg,
WM8995_AIF1DAC_RATE_MASK, lrclk);
snd_soc_component_update_bits(component, rate_reg,
WM8995_AIF1_SR_MASK |
WM8995_AIF1CLK_RATE_MASK, rate_val);
return 0;
}
static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
{
struct snd_soc_component *component = codec_dai->component;
int reg, val, mask;
switch (codec_dai->id) {
case 0:
reg = WM8995_AIF1_MASTER_SLAVE;
mask = WM8995_AIF1_TRI;
break;
case 1:
reg = WM8995_AIF2_MASTER_SLAVE;
mask = WM8995_AIF2_TRI;
break;
case 2:
reg = WM8995_POWER_MANAGEMENT_5;
mask = WM8995_AIF3_TRI;
break;
default:
return -EINVAL;
}
if (tristate)
val = mask;
else
val = 0;
return snd_soc_component_update_bits(component, reg, mask, val);
}
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
struct fll_div {
u16 outdiv;
u16 n;
u16 k;
u16 clk_ref_div;
u16 fll_fratio;
};
static int wm8995_get_fll_config(struct fll_div *fll,
int freq_in, int freq_out)
{
u64 Kpart;
unsigned int K, Ndiv, Nmod;
pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
/* Scale the input frequency down to <= 13.5MHz */
fll->clk_ref_div = 0;
while (freq_in > 13500000) {
fll->clk_ref_div++;
freq_in /= 2;
if (fll->clk_ref_div > 3)
return -EINVAL;
}
pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
/* Scale the output to give 90MHz<=Fvco<=100MHz */
fll->outdiv = 3;
while (freq_out * (fll->outdiv + 1) < 90000000) {
fll->outdiv++;
if (fll->outdiv > 63)
return -EINVAL;
}
freq_out *= fll->outdiv + 1;
pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
if (freq_in > 1000000) {
fll->fll_fratio = 0;
} else if (freq_in > 256000) {
fll->fll_fratio = 1;
freq_in *= 2;
} else if (freq_in > 128000) {
fll->fll_fratio = 2;
freq_in *= 4;
} else if (freq_in > 64000) {
fll->fll_fratio = 3;
freq_in *= 8;
} else {
fll->fll_fratio = 4;
freq_in *= 16;
}
pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
/* Now, calculate N.K */
Ndiv = freq_out / freq_in;
fll->n = Ndiv;
Nmod = freq_out % freq_in;
pr_debug("Nmod=%d\n", Nmod);
/* Calculate fractional part - scale up so we can round. */
Kpart = FIXED_FLL_SIZE * (long long)Nmod;
do_div(Kpart, freq_in);
K = Kpart & 0xFFFFFFFF;
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
fll->k = K / 10;
pr_debug("N=%x K=%x\n", fll->n, fll->k);
return 0;
}
static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
int src, unsigned int freq_in,
unsigned int freq_out)
{
struct snd_soc_component *component;
struct wm8995_priv *wm8995;
int reg_offset, ret;
struct fll_div fll;
u16 reg, aif1, aif2;
component = dai->component;
wm8995 = snd_soc_component_get_drvdata(component);
aif1 = snd_soc_component_read(component, WM8995_AIF1_CLOCKING_1)
& WM8995_AIF1CLK_ENA;
aif2 = snd_soc_component_read(component, WM8995_AIF2_CLOCKING_1)
& WM8995_AIF2CLK_ENA;
switch (id) {
case WM8995_FLL1:
reg_offset = 0;
id = 0;
break;
case WM8995_FLL2:
reg_offset = 0x20;
id = 1;
break;
default:
return -EINVAL;
}
switch (src) {
case 0:
/* Allow no source specification when stopping */
if (freq_out)
return -EINVAL;
break;
case WM8995_FLL_SRC_MCLK1:
case WM8995_FLL_SRC_MCLK2:
case WM8995_FLL_SRC_LRCLK:
case WM8995_FLL_SRC_BCLK:
break;
default:
return -EINVAL;
}
/* Are we changing anything? */
if (wm8995->fll[id].src == src &&
wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
return 0;
/* If we're stopping the FLL redo the old config - no
* registers will actually be written but we avoid GCC flow
* analysis bugs spewing warnings.
*/
if (freq_out)
ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
else
ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
wm8995->fll[id].out);
if (ret < 0)
return ret;
/* Gate the AIF clocks while we reclock */
snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
WM8995_AIF1CLK_ENA_MASK, 0);
snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
WM8995_AIF2CLK_ENA_MASK, 0);
/* We always need to disable the FLL while reconfiguring */
snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
WM8995_FLL1_ENA_MASK, 0);
reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
(fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,
WM8995_FLL1_OUTDIV_MASK |
WM8995_FLL1_FRATIO_MASK, reg);
snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,
WM8995_FLL1_N_MASK,
fll.n << WM8995_FLL1_N_SHIFT);
snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,
WM8995_FLL1_REFCLK_DIV_MASK |
WM8995_FLL1_REFCLK_SRC_MASK,
(fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
(src - 1));
if (freq_out)
snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
wm8995->fll[id].in = freq_in;
wm8995->fll[id].out = freq_out;
wm8995->fll[id].src = src;
/* Enable any gated AIF clocks */
snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
WM8995_AIF1CLK_ENA_MASK, aif1);
snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
WM8995_AIF2CLK_ENA_MASK, aif2);
configure_clock(component);
return 0;
}
static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component;
struct wm8995_priv *wm8995;
component = dai->component;
wm8995 = snd_soc_component_get_drvdata(component);
switch (dai->id) {
case 0:
case 1:
break;
default:
/* AIF3 shares clocking with AIF1/2 */
return -EINVAL;
}
switch (clk_id) {
case WM8995_SYSCLK_MCLK1:
wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
wm8995->mclk[0] = freq;
dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
dai->id + 1, freq);
break;
case WM8995_SYSCLK_MCLK2:
wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2;
wm8995->mclk[1] = freq;
dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
dai->id + 1, freq);
break;
case WM8995_SYSCLK_FLL1:
wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
break;
case WM8995_SYSCLK_FLL2:
wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
break;
case WM8995_SYSCLK_OPCLK:
default:
dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
return -EINVAL;
}
configure_clock(component);
return 0;
}
static int wm8995_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm8995_priv *wm8995;
int ret;
wm8995 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
wm8995->supplies);
if (ret)
return ret;
ret = regcache_sync(wm8995->regmap);
if (ret) {
dev_err(component->dev,
"Failed to sync cache: %d\n", ret);
return ret;
}
snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
WM8995_BG_ENA_MASK, WM8995_BG_ENA);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
WM8995_BG_ENA_MASK, 0);
regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
wm8995->supplies);
break;
}
return 0;
}
static int wm8995_probe(struct snd_soc_component *component)
{
struct wm8995_priv *wm8995;
int i;
int ret;
wm8995 = snd_soc_component_get_drvdata(component);
wm8995->component = component;
for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
wm8995->supplies[i].supply = wm8995_supply_names[i];
ret = devm_regulator_bulk_get(component->dev,
ARRAY_SIZE(wm8995->supplies),
wm8995->supplies);
if (ret) {
dev_err(component->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
/* This should really be moved into the regulator core */
for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
ret = devm_regulator_register_notifier(
wm8995->supplies[i].consumer,
&wm8995->disable_nb[i]);
if (ret) {
dev_err(component->dev,
"Failed to register regulator notifier: %d\n",
ret);
}
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
wm8995->supplies);
if (ret) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = snd_soc_component_read(component, WM8995_SOFTWARE_RESET);
if (ret < 0) {
dev_err(component->dev, "Failed to read device ID: %d\n", ret);
goto err_reg_enable;
}
if (ret != 0x8995) {
dev_err(component->dev, "Invalid device ID: %#x\n", ret);
ret = -EINVAL;
goto err_reg_enable;
}
ret = snd_soc_component_write(component, WM8995_SOFTWARE_RESET, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
goto err_reg_enable;
}
/* Latch volume updates (right only; we always do left then right). */
snd_soc_component_update_bits(component, WM8995_AIF1_DAC1_RIGHT_VOLUME,
WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
snd_soc_component_update_bits(component, WM8995_AIF1_DAC2_RIGHT_VOLUME,
WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
snd_soc_component_update_bits(component, WM8995_AIF2_DAC_RIGHT_VOLUME,
WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
snd_soc_component_update_bits(component, WM8995_AIF1_ADC1_RIGHT_VOLUME,
WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
snd_soc_component_update_bits(component, WM8995_AIF1_ADC2_RIGHT_VOLUME,
WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
snd_soc_component_update_bits(component, WM8995_AIF2_ADC_RIGHT_VOLUME,
WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
snd_soc_component_update_bits(component, WM8995_DAC1_RIGHT_VOLUME,
WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
snd_soc_component_update_bits(component, WM8995_DAC2_RIGHT_VOLUME,
WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
snd_soc_component_update_bits(component, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
WM8995_IN1_VU_MASK, WM8995_IN1_VU);
wm8995_update_class_w(component);
return 0;
err_reg_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
return ret;
}
#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
.set_sysclk = wm8995_set_dai_sysclk,
.set_fmt = wm8995_set_dai_fmt,
.hw_params = wm8995_hw_params,
.mute_stream = wm8995_aif_mute,
.set_pll = wm8995_set_fll,
.set_tristate = wm8995_set_tristate,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
.set_sysclk = wm8995_set_dai_sysclk,
.set_fmt = wm8995_set_dai_fmt,
.hw_params = wm8995_hw_params,
.mute_stream = wm8995_aif_mute,
.set_pll = wm8995_set_fll,
.set_tristate = wm8995_set_tristate,
.no_capture_mute = 1,
};
static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
.set_tristate = wm8995_set_tristate,
};
static struct snd_soc_dai_driver wm8995_dai[] = {
{
.name = "wm8995-aif1",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = WM8995_FORMATS
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8995_FORMATS
},
.ops = &wm8995_aif1_dai_ops
},
{
.name = "wm8995-aif2",
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = WM8995_FORMATS
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8995_FORMATS
},
.ops = &wm8995_aif2_dai_ops
},
{
.name = "wm8995-aif3",
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = WM8995_FORMATS
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8995_FORMATS
},
.ops = &wm8995_aif3_dai_ops
}
};
static const struct snd_soc_component_driver soc_component_dev_wm8995 = {
.probe = wm8995_probe,
.set_bias_level = wm8995_set_bias_level,
.controls = wm8995_snd_controls,
.num_controls = ARRAY_SIZE(wm8995_snd_controls),
.dapm_widgets = wm8995_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets),
.dapm_routes = wm8995_intercon,
.num_dapm_routes = ARRAY_SIZE(wm8995_intercon),
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8995_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = WM8995_MAX_REGISTER,
.reg_defaults = wm8995_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults),
.volatile_reg = wm8995_volatile,
.readable_reg = wm8995_readable,
.cache_type = REGCACHE_MAPLE,
};
#if defined(CONFIG_SPI_MASTER)
static int wm8995_spi_probe(struct spi_device *spi)
{
struct wm8995_priv *wm8995;
int ret;
wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL);
if (!wm8995)
return -ENOMEM;
spi_set_drvdata(spi, wm8995);
wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap);
if (IS_ERR(wm8995->regmap)) {
ret = PTR_ERR(wm8995->regmap);
dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8995, wm8995_dai,
ARRAY_SIZE(wm8995_dai));
return ret;
}
static struct spi_driver wm8995_spi_driver = {
.driver = {
.name = "wm8995",
},
.probe = wm8995_spi_probe,
};
#endif
#if IS_ENABLED(CONFIG_I2C)
static int wm8995_i2c_probe(struct i2c_client *i2c)
{
struct wm8995_priv *wm8995;
int ret;
wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL);
if (!wm8995)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8995);
wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap);
if (IS_ERR(wm8995->regmap)) {
ret = PTR_ERR(wm8995->regmap);
dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8995, wm8995_dai,
ARRAY_SIZE(wm8995_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
static const struct i2c_device_id wm8995_i2c_id[] = {
{"wm8995", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
static struct i2c_driver wm8995_i2c_driver = {
.driver = {
.name = "wm8995",
},
.probe = wm8995_i2c_probe,
.id_table = wm8995_i2c_id
};
#endif
static int __init wm8995_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8995_i2c_driver);
if (ret) {
printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8995_spi_driver);
if (ret) {
printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8995_modinit);
static void __exit wm8995_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8995_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8995_spi_driver);
#endif
}
module_exit(wm8995_exit);
MODULE_DESCRIPTION("ASoC WM8995 driver");
MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8995.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm0010.c -- WM0010 DSP Driver
*
* Copyright 2012 Wolfson Microelectronics PLC.
*
* Authors: Mark Brown <[email protected]>
* Dimitris Papastamos <[email protected]>
* Scott Ling <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/interrupt.h>
#include <linux/irqreturn.h>
#include <linux/init.h>
#include <linux/spi/spi.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <sound/soc.h>
#include <sound/wm0010.h>
#define DEVICE_ID_WM0010 10
/* We only support v1 of the .dfw INFO record */
#define INFO_VERSION 1
enum dfw_cmd {
DFW_CMD_FUSE = 0x01,
DFW_CMD_CODE_HDR,
DFW_CMD_CODE_DATA,
DFW_CMD_PLL,
DFW_CMD_INFO = 0xff
};
struct dfw_binrec {
u8 command;
u32 length:24;
u32 address;
uint8_t data[];
} __packed;
struct dfw_inforec {
u8 info_version;
u8 tool_major_version;
u8 tool_minor_version;
u8 dsp_target;
};
struct dfw_pllrec {
u8 command;
u32 length:24;
u32 address;
u32 clkctrl1;
u32 clkctrl2;
u32 clkctrl3;
u32 ldetctrl;
u32 uart_div;
u32 spi_div;
} __packed;
static struct pll_clock_map {
int max_sysclk;
int max_pll_spi_speed;
u32 pll_clkctrl1;
} pll_clock_map[] = { /* Dividers */
{ 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
{ 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
{ 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
{ 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
{ 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
{ 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
};
enum wm0010_state {
WM0010_POWER_OFF,
WM0010_OUT_OF_RESET,
WM0010_BOOTROM,
WM0010_STAGE2,
WM0010_FIRMWARE,
};
struct wm0010_priv {
struct snd_soc_component *component;
struct mutex lock;
struct device *dev;
struct wm0010_pdata pdata;
int gpio_reset;
int gpio_reset_value;
struct regulator_bulk_data core_supplies[2];
struct regulator *dbvdd;
int sysclk;
enum wm0010_state state;
bool boot_failed;
bool ready;
bool pll_running;
int max_spi_freq;
int board_max_spi_speed;
u32 pll_clkctrl1;
spinlock_t irq_lock;
int irq;
struct completion boot_completion;
};
struct wm0010_spi_msg {
struct spi_message m;
struct spi_transfer t;
u8 *tx_buf;
u8 *rx_buf;
size_t len;
};
static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
{ "SDI2 Capture", NULL, "SDI1 Playback" },
{ "SDI1 Capture", NULL, "SDI2 Playback" },
{ "SDI1 Capture", NULL, "CLKIN" },
{ "SDI2 Capture", NULL, "CLKIN" },
{ "SDI1 Playback", NULL, "CLKIN" },
{ "SDI2 Playback", NULL, "CLKIN" },
};
static const char *wm0010_state_to_str(enum wm0010_state state)
{
static const char * const state_to_str[] = {
"Power off",
"Out of reset",
"Boot ROM",
"Stage2",
"Firmware"
};
if (state < 0 || state >= ARRAY_SIZE(state_to_str))
return "null";
return state_to_str[state];
}
/* Called with wm0010->lock held */
static void wm0010_halt(struct snd_soc_component *component)
{
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
unsigned long flags;
enum wm0010_state state;
/* Fetch the wm0010 state */
spin_lock_irqsave(&wm0010->irq_lock, flags);
state = wm0010->state;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
switch (state) {
case WM0010_POWER_OFF:
/* If there's nothing to do, bail out */
return;
case WM0010_OUT_OF_RESET:
case WM0010_BOOTROM:
case WM0010_STAGE2:
case WM0010_FIRMWARE:
/* Remember to put chip back into reset */
gpio_set_value_cansleep(wm0010->gpio_reset,
wm0010->gpio_reset_value);
/* Disable the regulators */
regulator_disable(wm0010->dbvdd);
regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
wm0010->core_supplies);
break;
}
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_POWER_OFF;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
}
struct wm0010_boot_xfer {
struct list_head list;
struct snd_soc_component *component;
struct completion *done;
struct spi_message m;
struct spi_transfer t;
};
/* Called with wm0010->lock held */
static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
{
enum wm0010_state state;
unsigned long flags;
spin_lock_irqsave(&wm0010->irq_lock, flags);
state = wm0010->state;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
wm0010->boot_failed = true;
}
static void wm0010_boot_xfer_complete(void *data)
{
struct wm0010_boot_xfer *xfer = data;
struct snd_soc_component *component = xfer->component;
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
u32 *out32 = xfer->t.rx_buf;
int i;
if (xfer->m.status != 0) {
dev_err(component->dev, "SPI transfer failed: %d\n",
xfer->m.status);
wm0010_mark_boot_failure(wm0010);
if (xfer->done)
complete(xfer->done);
return;
}
for (i = 0; i < xfer->t.len / 4; i++) {
dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
switch (be32_to_cpu(out32[i])) {
case 0xe0e0e0e0:
dev_err(component->dev,
"%d: ROM error reported in stage 2\n", i);
wm0010_mark_boot_failure(wm0010);
break;
case 0x55555555:
if (wm0010->state < WM0010_STAGE2)
break;
dev_err(component->dev,
"%d: ROM bootloader running in stage 2\n", i);
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0000:
dev_dbg(component->dev, "Stage2 loader running\n");
break;
case 0x0fed0007:
dev_dbg(component->dev, "CODE_HDR packet received\n");
break;
case 0x0fed0008:
dev_dbg(component->dev, "CODE_DATA packet received\n");
break;
case 0x0fed0009:
dev_dbg(component->dev, "Download complete\n");
break;
case 0x0fed000c:
dev_dbg(component->dev, "Application start\n");
break;
case 0x0fed000e:
dev_dbg(component->dev, "PLL packet received\n");
wm0010->pll_running = true;
break;
case 0x0fed0025:
dev_err(component->dev, "Device reports image too long\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed002c:
dev_err(component->dev, "Device reports bad SPI packet\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0031:
dev_err(component->dev, "Device reports SPI read overflow\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0032:
dev_err(component->dev, "Device reports SPI underclock\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0033:
dev_err(component->dev, "Device reports bad header packet\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0034:
dev_err(component->dev, "Device reports invalid packet type\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0035:
dev_err(component->dev, "Device reports data before header error\n");
wm0010_mark_boot_failure(wm0010);
break;
case 0x0fed0038:
dev_err(component->dev, "Device reports invalid PLL packet\n");
break;
case 0x0fed003a:
dev_err(component->dev, "Device reports packet alignment error\n");
wm0010_mark_boot_failure(wm0010);
break;
default:
dev_err(component->dev, "Unrecognised return 0x%x\n",
be32_to_cpu(out32[i]));
wm0010_mark_boot_failure(wm0010);
break;
}
if (wm0010->boot_failed)
break;
}
if (xfer->done)
complete(xfer->done);
}
static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
{
int i;
for (i = 0; i < len / 8; i++)
data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
}
static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
{
struct spi_device *spi = to_spi_device(component->dev);
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
struct list_head xfer_list;
struct wm0010_boot_xfer *xfer;
int ret;
DECLARE_COMPLETION_ONSTACK(done);
const struct firmware *fw;
const struct dfw_binrec *rec;
const struct dfw_inforec *inforec;
u64 *img;
u8 *out, dsp;
u32 len, offset;
INIT_LIST_HEAD(&xfer_list);
ret = request_firmware(&fw, name, component->dev);
if (ret != 0) {
dev_err(component->dev, "Failed to request application(%s): %d\n",
name, ret);
return ret;
}
rec = (const struct dfw_binrec *)fw->data;
inforec = (const struct dfw_inforec *)rec->data;
offset = 0;
dsp = inforec->dsp_target;
wm0010->boot_failed = false;
if (WARN_ON(!list_empty(&xfer_list)))
return -EINVAL;
/* First record should be INFO */
if (rec->command != DFW_CMD_INFO) {
dev_err(component->dev, "First record not INFO\r\n");
ret = -EINVAL;
goto abort;
}
if (inforec->info_version != INFO_VERSION) {
dev_err(component->dev,
"Unsupported version (%02d) of INFO record\r\n",
inforec->info_version);
ret = -EINVAL;
goto abort;
}
dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
inforec->info_version);
/* Check it's a DSP file */
if (dsp != DEVICE_ID_WM0010) {
dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
ret = -EINVAL;
goto abort;
}
/* Skip the info record as we don't need to send it */
offset += ((rec->length) + 8);
rec = (void *)&rec->data[rec->length];
while (offset < fw->size) {
dev_dbg(component->dev,
"Packet: command %d, data length = 0x%x\r\n",
rec->command, rec->length);
len = rec->length + 8;
xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
if (!xfer) {
ret = -ENOMEM;
goto abort;
}
xfer->component = component;
list_add_tail(&xfer->list, &xfer_list);
out = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!out) {
ret = -ENOMEM;
goto abort1;
}
xfer->t.rx_buf = out;
img = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!img) {
ret = -ENOMEM;
goto abort1;
}
xfer->t.tx_buf = img;
byte_swap_64((u64 *)&rec->command, img, len);
spi_message_init(&xfer->m);
xfer->m.complete = wm0010_boot_xfer_complete;
xfer->m.context = xfer;
xfer->t.len = len;
xfer->t.bits_per_word = 8;
if (!wm0010->pll_running) {
xfer->t.speed_hz = wm0010->sysclk / 6;
} else {
xfer->t.speed_hz = wm0010->max_spi_freq;
if (wm0010->board_max_spi_speed &&
(wm0010->board_max_spi_speed < wm0010->max_spi_freq))
xfer->t.speed_hz = wm0010->board_max_spi_speed;
}
/* Store max usable spi frequency for later use */
wm0010->max_spi_freq = xfer->t.speed_hz;
spi_message_add_tail(&xfer->t, &xfer->m);
offset += ((rec->length) + 8);
rec = (void *)&rec->data[rec->length];
if (offset >= fw->size) {
dev_dbg(component->dev, "All transfers scheduled\n");
xfer->done = &done;
}
ret = spi_async(spi, &xfer->m);
if (ret != 0) {
dev_err(component->dev, "Write failed: %d\n", ret);
goto abort1;
}
if (wm0010->boot_failed) {
dev_dbg(component->dev, "Boot fail!\n");
ret = -EINVAL;
goto abort1;
}
}
wait_for_completion(&done);
ret = 0;
abort1:
while (!list_empty(&xfer_list)) {
xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
list);
kfree(xfer->t.rx_buf);
kfree(xfer->t.tx_buf);
list_del(&xfer->list);
kfree(xfer);
}
abort:
release_firmware(fw);
return ret;
}
static int wm0010_stage2_load(struct snd_soc_component *component)
{
struct spi_device *spi = to_spi_device(component->dev);
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
const struct firmware *fw;
struct spi_message m;
struct spi_transfer t;
u32 *img;
u8 *out;
int i;
int ret = 0;
ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev);
if (ret != 0) {
dev_err(component->dev, "Failed to request stage2 loader: %d\n",
ret);
return ret;
}
dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
/* Copy to local buffer first as vmalloc causes problems for dma */
img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA);
if (!img) {
ret = -ENOMEM;
goto abort2;
}
out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
if (!out) {
ret = -ENOMEM;
goto abort1;
}
spi_message_init(&m);
memset(&t, 0, sizeof(t));
t.rx_buf = out;
t.tx_buf = img;
t.len = fw->size;
t.bits_per_word = 8;
t.speed_hz = wm0010->sysclk / 10;
spi_message_add_tail(&t, &m);
dev_dbg(component->dev, "Starting initial download at %dHz\n",
t.speed_hz);
ret = spi_sync(spi, &m);
if (ret != 0) {
dev_err(component->dev, "Initial download failed: %d\n", ret);
goto abort;
}
/* Look for errors from the boot ROM */
for (i = 0; i < fw->size; i++) {
if (out[i] != 0x55) {
dev_err(component->dev, "Boot ROM error: %x in %d\n",
out[i], i);
wm0010_mark_boot_failure(wm0010);
ret = -EBUSY;
goto abort;
}
}
abort:
kfree(out);
abort1:
kfree(img);
abort2:
release_firmware(fw);
return ret;
}
static int wm0010_boot(struct snd_soc_component *component)
{
struct spi_device *spi = to_spi_device(component->dev);
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
unsigned long flags;
int ret;
struct spi_message m;
struct spi_transfer t;
struct dfw_pllrec pll_rec;
u32 *p, len;
u64 *img_swap;
u8 *out;
int i;
spin_lock_irqsave(&wm0010->irq_lock, flags);
if (wm0010->state != WM0010_POWER_OFF)
dev_warn(wm0010->dev, "DSP already powered up!\n");
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
if (wm0010->sysclk > 26000000) {
dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
ret = -ECANCELED;
goto err;
}
mutex_lock(&wm0010->lock);
wm0010->pll_running = false;
dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
wm0010->core_supplies);
if (ret != 0) {
dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
ret);
mutex_unlock(&wm0010->lock);
goto err;
}
ret = regulator_enable(wm0010->dbvdd);
if (ret != 0) {
dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
goto err_core;
}
/* Release reset */
gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_OUT_OF_RESET;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
if (!wait_for_completion_timeout(&wm0010->boot_completion,
msecs_to_jiffies(20)))
dev_err(component->dev, "Failed to get interrupt from DSP\n");
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_BOOTROM;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
ret = wm0010_stage2_load(component);
if (ret)
goto abort;
if (!wait_for_completion_timeout(&wm0010->boot_completion,
msecs_to_jiffies(20)))
dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_STAGE2;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
/* Only initialise PLL if max_spi_freq initialised */
if (wm0010->max_spi_freq) {
/* Initialise a PLL record */
memset(&pll_rec, 0, sizeof(pll_rec));
pll_rec.command = DFW_CMD_PLL;
pll_rec.length = (sizeof(pll_rec) - 8);
/* On wm0010 only the CLKCTRL1 value is used */
pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
ret = -ENOMEM;
len = pll_rec.length + 8;
out = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!out)
goto abort;
img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
if (!img_swap)
goto abort_out;
/* We need to re-order for 0010 */
byte_swap_64((u64 *)&pll_rec, img_swap, len);
spi_message_init(&m);
memset(&t, 0, sizeof(t));
t.rx_buf = out;
t.tx_buf = img_swap;
t.len = len;
t.bits_per_word = 8;
t.speed_hz = wm0010->sysclk / 6;
spi_message_add_tail(&t, &m);
ret = spi_sync(spi, &m);
if (ret) {
dev_err(component->dev, "First PLL write failed: %d\n", ret);
goto abort_swap;
}
/* Use a second send of the message to get the return status */
ret = spi_sync(spi, &m);
if (ret) {
dev_err(component->dev, "Second PLL write failed: %d\n", ret);
goto abort_swap;
}
p = (u32 *)out;
/* Look for PLL active code from the DSP */
for (i = 0; i < len / 4; i++) {
if (*p == 0x0e00ed0f) {
dev_dbg(component->dev, "PLL packet received\n");
wm0010->pll_running = true;
break;
}
p++;
}
kfree(img_swap);
kfree(out);
} else
dev_dbg(component->dev, "Not enabling DSP PLL.");
ret = wm0010_firmware_load("wm0010.dfw", component);
if (ret != 0)
goto abort;
spin_lock_irqsave(&wm0010->irq_lock, flags);
wm0010->state = WM0010_FIRMWARE;
spin_unlock_irqrestore(&wm0010->irq_lock, flags);
mutex_unlock(&wm0010->lock);
return 0;
abort_swap:
kfree(img_swap);
abort_out:
kfree(out);
abort:
/* Put the chip back into reset */
wm0010_halt(component);
mutex_unlock(&wm0010->lock);
return ret;
err_core:
mutex_unlock(&wm0010->lock);
regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
wm0010->core_supplies);
err:
return ret;
}
static int wm0010_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
wm0010_boot(component);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
mutex_lock(&wm0010->lock);
wm0010_halt(component);
mutex_unlock(&wm0010->lock);
}
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
int clk_id, unsigned int freq, int dir)
{
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
unsigned int i;
wm0010->sysclk = freq;
if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
wm0010->max_spi_freq = 0;
} else {
for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
if (freq >= pll_clock_map[i].max_sysclk) {
wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
break;
}
}
return 0;
}
static int wm0010_probe(struct snd_soc_component *component);
static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
.probe = wm0010_probe,
.set_bias_level = wm0010_set_bias_level,
.set_sysclk = wm0010_set_sysclk,
.dapm_widgets = wm0010_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
.dapm_routes = wm0010_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm0010_dai[] = {
{
.name = "wm0010-sdi1",
.playback = {
.stream_name = "SDI1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM0010_RATES,
.formats = WM0010_FORMATS,
},
.capture = {
.stream_name = "SDI1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM0010_RATES,
.formats = WM0010_FORMATS,
},
},
{
.name = "wm0010-sdi2",
.playback = {
.stream_name = "SDI2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM0010_RATES,
.formats = WM0010_FORMATS,
},
.capture = {
.stream_name = "SDI2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM0010_RATES,
.formats = WM0010_FORMATS,
},
},
};
static irqreturn_t wm0010_irq(int irq, void *data)
{
struct wm0010_priv *wm0010 = data;
switch (wm0010->state) {
case WM0010_OUT_OF_RESET:
case WM0010_BOOTROM:
case WM0010_STAGE2:
spin_lock(&wm0010->irq_lock);
complete(&wm0010->boot_completion);
spin_unlock(&wm0010->irq_lock);
return IRQ_HANDLED;
default:
return IRQ_NONE;
}
return IRQ_NONE;
}
static int wm0010_probe(struct snd_soc_component *component)
{
struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
wm0010->component = component;
return 0;
}
static int wm0010_spi_probe(struct spi_device *spi)
{
unsigned long gpio_flags;
int ret;
int trigger;
int irq;
struct wm0010_priv *wm0010;
wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
GFP_KERNEL);
if (!wm0010)
return -ENOMEM;
mutex_init(&wm0010->lock);
spin_lock_init(&wm0010->irq_lock);
spi_set_drvdata(spi, wm0010);
wm0010->dev = &spi->dev;
if (dev_get_platdata(&spi->dev))
memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
sizeof(wm0010->pdata));
init_completion(&wm0010->boot_completion);
wm0010->core_supplies[0].supply = "AVDD";
wm0010->core_supplies[1].supply = "DCVDD";
ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
wm0010->core_supplies);
if (ret != 0) {
dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
ret);
return ret;
}
wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
if (IS_ERR(wm0010->dbvdd)) {
ret = PTR_ERR(wm0010->dbvdd);
dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
return ret;
}
if (wm0010->pdata.gpio_reset) {
wm0010->gpio_reset = wm0010->pdata.gpio_reset;
if (wm0010->pdata.reset_active_high)
wm0010->gpio_reset_value = 1;
else
wm0010->gpio_reset_value = 0;
if (wm0010->gpio_reset_value)
gpio_flags = GPIOF_OUT_INIT_HIGH;
else
gpio_flags = GPIOF_OUT_INIT_LOW;
ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
gpio_flags, "wm0010 reset");
if (ret < 0) {
dev_err(wm0010->dev,
"Failed to request GPIO for DSP reset: %d\n",
ret);
return ret;
}
} else {
dev_err(wm0010->dev, "No reset GPIO configured\n");
return -EINVAL;
}
wm0010->state = WM0010_POWER_OFF;
irq = spi->irq;
if (wm0010->pdata.irq_flags)
trigger = wm0010->pdata.irq_flags;
else
trigger = IRQF_TRIGGER_FALLING;
trigger |= IRQF_ONESHOT;
ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
"wm0010", wm0010);
if (ret) {
dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
irq, ret);
return ret;
}
wm0010->irq = irq;
ret = irq_set_irq_wake(irq, 1);
if (ret) {
dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
irq, ret);
return ret;
}
if (spi->max_speed_hz)
wm0010->board_max_spi_speed = spi->max_speed_hz;
else
wm0010->board_max_spi_speed = 0;
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm0010, wm0010_dai,
ARRAY_SIZE(wm0010_dai));
if (ret < 0)
return ret;
return 0;
}
static void wm0010_spi_remove(struct spi_device *spi)
{
struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
gpio_set_value_cansleep(wm0010->gpio_reset,
wm0010->gpio_reset_value);
irq_set_irq_wake(wm0010->irq, 0);
if (wm0010->irq)
free_irq(wm0010->irq, wm0010);
}
static struct spi_driver wm0010_spi_driver = {
.driver = {
.name = "wm0010",
},
.probe = wm0010_spi_probe,
.remove = wm0010_spi_remove,
};
module_spi_driver(wm0010_spi_driver);
MODULE_DESCRIPTION("ASoC WM0010 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("wm0010.dfw");
MODULE_FIRMWARE("wm0010_stage2.bin");
| linux-master | sound/soc/codecs/wm0010.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ak4118.c -- Asahi Kasei ALSA Soc Audio driver
*
* Copyright 2018 DEVIALET
*/
#include <linux/i2c.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/asoundef.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/soc.h>
#define AK4118_REG_CLK_PWR_CTL 0x00
#define AK4118_REG_FORMAT_CTL 0x01
#define AK4118_REG_IO_CTL0 0x02
#define AK4118_REG_IO_CTL1 0x03
#define AK4118_REG_INT0_MASK 0x04
#define AK4118_REG_INT1_MASK 0x05
#define AK4118_REG_RCV_STATUS0 0x06
#define AK4118_REG_RCV_STATUS1 0x07
#define AK4118_REG_RXCHAN_STATUS0 0x08
#define AK4118_REG_RXCHAN_STATUS1 0x09
#define AK4118_REG_RXCHAN_STATUS2 0x0a
#define AK4118_REG_RXCHAN_STATUS3 0x0b
#define AK4118_REG_RXCHAN_STATUS4 0x0c
#define AK4118_REG_TXCHAN_STATUS0 0x0d
#define AK4118_REG_TXCHAN_STATUS1 0x0e
#define AK4118_REG_TXCHAN_STATUS2 0x0f
#define AK4118_REG_TXCHAN_STATUS3 0x10
#define AK4118_REG_TXCHAN_STATUS4 0x11
#define AK4118_REG_BURST_PREAMB_PC0 0x12
#define AK4118_REG_BURST_PREAMB_PC1 0x13
#define AK4118_REG_BURST_PREAMB_PD0 0x14
#define AK4118_REG_BURST_PREAMB_PD1 0x15
#define AK4118_REG_QSUB_CTL 0x16
#define AK4118_REG_QSUB_TRACK 0x17
#define AK4118_REG_QSUB_INDEX 0x18
#define AK4118_REG_QSUB_MIN 0x19
#define AK4118_REG_QSUB_SEC 0x1a
#define AK4118_REG_QSUB_FRAME 0x1b
#define AK4118_REG_QSUB_ZERO 0x1c
#define AK4118_REG_QSUB_ABS_MIN 0x1d
#define AK4118_REG_QSUB_ABS_SEC 0x1e
#define AK4118_REG_QSUB_ABS_FRAME 0x1f
#define AK4118_REG_GPE 0x20
#define AK4118_REG_GPDR 0x21
#define AK4118_REG_GPSCR 0x22
#define AK4118_REG_GPLR 0x23
#define AK4118_REG_DAT_MASK_DTS 0x24
#define AK4118_REG_RX_DETECT 0x25
#define AK4118_REG_STC_DAT_DETECT 0x26
#define AK4118_REG_RXCHAN_STATUS5 0x27
#define AK4118_REG_TXCHAN_STATUS5 0x28
#define AK4118_REG_MAX 0x29
#define AK4118_REG_FORMAT_CTL_DIF0 (1 << 4)
#define AK4118_REG_FORMAT_CTL_DIF1 (1 << 5)
#define AK4118_REG_FORMAT_CTL_DIF2 (1 << 6)
struct ak4118_priv {
struct regmap *regmap;
struct gpio_desc *reset;
struct gpio_desc *irq;
struct snd_soc_component *component;
};
static const struct reg_default ak4118_reg_defaults[] = {
{AK4118_REG_CLK_PWR_CTL, 0x43},
{AK4118_REG_FORMAT_CTL, 0x6a},
{AK4118_REG_IO_CTL0, 0x88},
{AK4118_REG_IO_CTL1, 0x48},
{AK4118_REG_INT0_MASK, 0xee},
{AK4118_REG_INT1_MASK, 0xb5},
{AK4118_REG_RCV_STATUS0, 0x00},
{AK4118_REG_RCV_STATUS1, 0x10},
{AK4118_REG_TXCHAN_STATUS0, 0x00},
{AK4118_REG_TXCHAN_STATUS1, 0x00},
{AK4118_REG_TXCHAN_STATUS2, 0x00},
{AK4118_REG_TXCHAN_STATUS3, 0x00},
{AK4118_REG_TXCHAN_STATUS4, 0x00},
{AK4118_REG_GPE, 0x77},
{AK4118_REG_GPDR, 0x00},
{AK4118_REG_GPSCR, 0x00},
{AK4118_REG_GPLR, 0x00},
{AK4118_REG_DAT_MASK_DTS, 0x3f},
{AK4118_REG_RX_DETECT, 0x00},
{AK4118_REG_STC_DAT_DETECT, 0x00},
{AK4118_REG_TXCHAN_STATUS5, 0x00},
};
static const char * const ak4118_input_select_txt[] = {
"RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7",
};
static SOC_ENUM_SINGLE_DECL(ak4118_insel_enum, AK4118_REG_IO_CTL1, 0x0,
ak4118_input_select_txt);
static const struct snd_kcontrol_new ak4118_input_mux_controls =
SOC_DAPM_ENUM("Input Select", ak4118_insel_enum);
static const char * const ak4118_iec958_fs_txt[] = {
"44100", "48000", "32000", "22050", "11025", "24000", "16000", "88200",
"8000", "96000", "64000", "176400", "192000",
};
static const int ak4118_iec958_fs_val[] = {
0x0, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xE,
};
static SOC_VALUE_ENUM_SINGLE_DECL(ak4118_iec958_fs_enum, AK4118_REG_RCV_STATUS1,
0x4, 0x4, ak4118_iec958_fs_txt,
ak4118_iec958_fs_val);
static struct snd_kcontrol_new ak4118_iec958_controls[] = {
SOC_SINGLE("IEC958 Parity Errors", AK4118_REG_RCV_STATUS0, 0, 1, 0),
SOC_SINGLE("IEC958 No Audio", AK4118_REG_RCV_STATUS0, 1, 1, 0),
SOC_SINGLE("IEC958 PLL Lock", AK4118_REG_RCV_STATUS0, 4, 1, 1),
SOC_SINGLE("IEC958 Non PCM", AK4118_REG_RCV_STATUS0, 6, 1, 0),
SOC_ENUM("IEC958 Sampling Freq", ak4118_iec958_fs_enum),
};
static const struct snd_soc_dapm_widget ak4118_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("INRX0"),
SND_SOC_DAPM_INPUT("INRX1"),
SND_SOC_DAPM_INPUT("INRX2"),
SND_SOC_DAPM_INPUT("INRX3"),
SND_SOC_DAPM_INPUT("INRX4"),
SND_SOC_DAPM_INPUT("INRX5"),
SND_SOC_DAPM_INPUT("INRX6"),
SND_SOC_DAPM_INPUT("INRX7"),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&ak4118_input_mux_controls),
};
static const struct snd_soc_dapm_route ak4118_dapm_routes[] = {
{"Input Mux", "RX0", "INRX0"},
{"Input Mux", "RX1", "INRX1"},
{"Input Mux", "RX2", "INRX2"},
{"Input Mux", "RX3", "INRX3"},
{"Input Mux", "RX4", "INRX4"},
{"Input Mux", "RX5", "INRX5"},
{"Input Mux", "RX6", "INRX6"},
{"Input Mux", "RX7", "INRX7"},
};
static int ak4118_set_dai_fmt_provider(struct ak4118_priv *ak4118,
unsigned int format)
{
int dif;
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dif = AK4118_REG_FORMAT_CTL_DIF0 | AK4118_REG_FORMAT_CTL_DIF2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
dif = AK4118_REG_FORMAT_CTL_DIF0 | AK4118_REG_FORMAT_CTL_DIF1;
break;
case SND_SOC_DAIFMT_LEFT_J:
dif = AK4118_REG_FORMAT_CTL_DIF2;
break;
default:
return -ENOTSUPP;
}
return dif;
}
static int ak4118_set_dai_fmt_consumer(struct ak4118_priv *ak4118,
unsigned int format)
{
int dif;
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
dif = AK4118_REG_FORMAT_CTL_DIF0 | AK4118_REG_FORMAT_CTL_DIF1 |
AK4118_REG_FORMAT_CTL_DIF2;
break;
case SND_SOC_DAIFMT_LEFT_J:
dif = AK4118_REG_FORMAT_CTL_DIF1 | AK4118_REG_FORMAT_CTL_DIF2;
break;
default:
return -ENOTSUPP;
}
return dif;
}
static int ak4118_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int format)
{
struct snd_soc_component *component = dai->component;
struct ak4118_priv *ak4118 = snd_soc_component_get_drvdata(component);
int dif;
int ret = 0;
switch (format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
dif = ak4118_set_dai_fmt_provider(ak4118, format);
break;
case SND_SOC_DAIFMT_CBC_CFC:
dif = ak4118_set_dai_fmt_consumer(ak4118, format);
break;
default:
ret = -ENOTSUPP;
goto exit;
}
/* format not supported */
if (dif < 0) {
ret = dif;
goto exit;
}
ret = regmap_update_bits(ak4118->regmap, AK4118_REG_FORMAT_CTL,
AK4118_REG_FORMAT_CTL_DIF0 |
AK4118_REG_FORMAT_CTL_DIF1 |
AK4118_REG_FORMAT_CTL_DIF2, dif);
if (ret < 0)
goto exit;
exit:
return ret;
}
static int ak4118_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
return 0;
}
static const struct snd_soc_dai_ops ak4118_dai_ops = {
.hw_params = ak4118_hw_params,
.set_fmt = ak4118_set_dai_fmt,
};
static struct snd_soc_dai_driver ak4118_dai = {
.name = "ak4118-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE
},
.ops = &ak4118_dai_ops,
};
static irqreturn_t ak4118_irq_handler(int irq, void *data)
{
struct ak4118_priv *ak4118 = data;
struct snd_soc_component *component = ak4118->component;
struct snd_kcontrol_new *kctl_new;
unsigned int i;
if (!component)
return IRQ_NONE;
for (i = 0; i < ARRAY_SIZE(ak4118_iec958_controls); i++) {
kctl_new = &ak4118_iec958_controls[i];
snd_soc_component_notify_control(component, kctl_new->name);
}
return IRQ_HANDLED;
}
static int ak4118_probe(struct snd_soc_component *component)
{
struct ak4118_priv *ak4118 = snd_soc_component_get_drvdata(component);
int ret = 0;
ak4118->component = component;
/* release reset */
gpiod_set_value(ak4118->reset, 0);
/* unmask all int1 sources */
ret = regmap_write(ak4118->regmap, AK4118_REG_INT1_MASK, 0x00);
if (ret < 0) {
dev_err(component->dev,
"failed to write regmap 0x%x 0x%x: %d\n",
AK4118_REG_INT1_MASK, 0x00, ret);
return ret;
}
/* rx detect enable on all channels */
ret = regmap_write(ak4118->regmap, AK4118_REG_RX_DETECT, 0xff);
if (ret < 0) {
dev_err(component->dev,
"failed to write regmap 0x%x 0x%x: %d\n",
AK4118_REG_RX_DETECT, 0xff, ret);
return ret;
}
ret = snd_soc_add_component_controls(component, ak4118_iec958_controls,
ARRAY_SIZE(ak4118_iec958_controls));
if (ret) {
dev_err(component->dev,
"failed to add component kcontrols: %d\n", ret);
return ret;
}
return 0;
}
static void ak4118_remove(struct snd_soc_component *component)
{
struct ak4118_priv *ak4118 = snd_soc_component_get_drvdata(component);
/* hold reset */
gpiod_set_value(ak4118->reset, 1);
}
static const struct snd_soc_component_driver soc_component_drv_ak4118 = {
.probe = ak4118_probe,
.remove = ak4118_remove,
.dapm_widgets = ak4118_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(ak4118_dapm_widgets),
.dapm_routes = ak4118_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(ak4118_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config ak4118_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = ak4118_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(ak4118_reg_defaults),
.cache_type = REGCACHE_NONE,
.max_register = AK4118_REG_MAX - 1,
};
static int ak4118_i2c_probe(struct i2c_client *i2c)
{
struct ak4118_priv *ak4118;
int ret;
ak4118 = devm_kzalloc(&i2c->dev, sizeof(struct ak4118_priv),
GFP_KERNEL);
if (ak4118 == NULL)
return -ENOMEM;
ak4118->regmap = devm_regmap_init_i2c(i2c, &ak4118_regmap);
if (IS_ERR(ak4118->regmap))
return PTR_ERR(ak4118->regmap);
i2c_set_clientdata(i2c, ak4118);
ak4118->reset = devm_gpiod_get(&i2c->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(ak4118->reset))
return dev_err_probe(&i2c->dev, PTR_ERR(ak4118->reset),
"Failed to get reset\n");
ak4118->irq = devm_gpiod_get(&i2c->dev, "irq", GPIOD_IN);
if (IS_ERR(ak4118->irq))
return dev_err_probe(&i2c->dev, PTR_ERR(ak4118->irq),
"Failed to get IRQ\n");
ret = devm_request_threaded_irq(&i2c->dev, gpiod_to_irq(ak4118->irq),
NULL, ak4118_irq_handler,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"ak4118-irq", ak4118);
if (ret < 0) {
dev_err(&i2c->dev, "Fail to request_irq: %d\n", ret);
return ret;
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_drv_ak4118, &ak4118_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id ak4118_of_match[] = {
{ .compatible = "asahi-kasei,ak4118", },
{}
};
MODULE_DEVICE_TABLE(of, ak4118_of_match);
#endif
static const struct i2c_device_id ak4118_id_table[] = {
{ "ak4118", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, ak4118_id_table);
static struct i2c_driver ak4118_i2c_driver = {
.driver = {
.name = "ak4118",
.of_match_table = of_match_ptr(ak4118_of_match),
},
.id_table = ak4118_id_table,
.probe = ak4118_i2c_probe,
};
module_i2c_driver(ak4118_i2c_driver);
MODULE_DESCRIPTION("Asahi Kasei AK4118 ALSA SoC driver");
MODULE_AUTHOR("Adrien Charruel <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/ak4118.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ac97.c -- ALSA Soc AC97 codec support
*
* Copyright 2005 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <[email protected]>
*
* Generic AC97 support.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
static const struct snd_soc_dapm_widget ac97_widgets[] = {
SND_SOC_DAPM_INPUT("RX"),
SND_SOC_DAPM_OUTPUT("TX"),
};
static const struct snd_soc_dapm_route ac97_routes[] = {
{ "AC97 Capture", NULL, "RX" },
{ "TX", NULL, "AC97 Playback" },
};
static int ac97_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
return snd_ac97_set_rate(ac97, reg, substream->runtime->rate);
}
static const struct snd_soc_dai_ops ac97_dai_ops = {
.prepare = ac97_prepare,
};
static struct snd_soc_dai_driver ac97_dai = {
.name = "ac97-hifi",
.playback = {
.stream_name = "AC97 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SND_SOC_STD_AC97_FMTS,},
.capture = {
.stream_name = "AC97 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &ac97_dai_ops,
};
static int ac97_soc_probe(struct snd_soc_component *component)
{
struct snd_ac97 *ac97;
struct snd_ac97_bus *ac97_bus;
struct snd_ac97_template ac97_template;
int ret;
/* add codec as bus device for standard ac97 */
ret = snd_ac97_bus(component->card->snd_card, 0, soc_ac97_ops,
NULL, &ac97_bus);
if (ret < 0)
return ret;
memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
if (ret < 0)
return ret;
snd_soc_component_set_drvdata(component, ac97);
return 0;
}
#ifdef CONFIG_PM
static int ac97_soc_suspend(struct snd_soc_component *component)
{
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
snd_ac97_suspend(ac97);
return 0;
}
static int ac97_soc_resume(struct snd_soc_component *component)
{
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
snd_ac97_resume(ac97);
return 0;
}
#else
#define ac97_soc_suspend NULL
#define ac97_soc_resume NULL
#endif
static const struct snd_soc_component_driver soc_component_dev_ac97 = {
.probe = ac97_soc_probe,
.suspend = ac97_soc_suspend,
.resume = ac97_soc_resume,
.dapm_widgets = ac97_widgets,
.num_dapm_widgets = ARRAY_SIZE(ac97_widgets),
.dapm_routes = ac97_routes,
.num_dapm_routes = ARRAY_SIZE(ac97_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int ac97_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_ac97, &ac97_dai, 1);
}
static struct platform_driver ac97_codec_driver = {
.driver = {
.name = "ac97-codec",
},
.probe = ac97_probe,
};
module_platform_driver(ac97_codec_driver);
MODULE_DESCRIPTION("Soc Generic AC97 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ac97-codec");
| linux-master | sound/soc/codecs/ac97.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs35l34.c -- CS35l34 ALSA SoC audio driver
*
* Copyright 2016 Cirrus Logic, Inc.
*
* Author: Paul Handrigan <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/machine.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs35l34.h>
#include "cs35l34.h"
#include "cirrus_legacy.h"
#define PDN_DONE_ATTEMPTS 10
#define CS35L34_START_DELAY 50
struct cs35l34_private {
struct snd_soc_component *component;
struct cs35l34_platform_data pdata;
struct regmap *regmap;
struct regulator_bulk_data core_supplies[2];
int num_core_supplies;
int mclk_int;
bool tdm_mode;
struct gpio_desc *reset_gpio; /* Active-low reset GPIO */
};
static const struct reg_default cs35l34_reg[] = {
{CS35L34_PWRCTL1, 0x01},
{CS35L34_PWRCTL2, 0x19},
{CS35L34_PWRCTL3, 0x01},
{CS35L34_ADSP_CLK_CTL, 0x08},
{CS35L34_MCLK_CTL, 0x11},
{CS35L34_AMP_INP_DRV_CTL, 0x01},
{CS35L34_AMP_DIG_VOL_CTL, 0x12},
{CS35L34_AMP_DIG_VOL, 0x00},
{CS35L34_AMP_ANLG_GAIN_CTL, 0x0F},
{CS35L34_PROTECT_CTL, 0x06},
{CS35L34_AMP_KEEP_ALIVE_CTL, 0x04},
{CS35L34_BST_CVTR_V_CTL, 0x00},
{CS35L34_BST_PEAK_I, 0x10},
{CS35L34_BST_RAMP_CTL, 0x87},
{CS35L34_BST_CONV_COEF_1, 0x24},
{CS35L34_BST_CONV_COEF_2, 0x24},
{CS35L34_BST_CONV_SLOPE_COMP, 0x4E},
{CS35L34_BST_CONV_SW_FREQ, 0x08},
{CS35L34_CLASS_H_CTL, 0x0D},
{CS35L34_CLASS_H_HEADRM_CTL, 0x0D},
{CS35L34_CLASS_H_RELEASE_RATE, 0x08},
{CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41},
{CS35L34_CLASS_H_STATUS, 0x05},
{CS35L34_VPBR_CTL, 0x0A},
{CS35L34_VPBR_VOL_CTL, 0x90},
{CS35L34_VPBR_TIMING_CTL, 0x6A},
{CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95},
{CS35L34_PRED_BROWNOUT_THRESH, 0x1C},
{CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00},
{CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10},
{CS35L34_PRED_WAIT_CTL, 0x10},
{CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08},
{CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80},
{CS35L34_VPBR_ATTEN_STATUS, 0x00},
{CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00},
{CS35L34_SPKR_MON_CTL, 0xC6},
{CS35L34_ADSP_I2S_CTL, 0x00},
{CS35L34_ADSP_TDM_CTL, 0x00},
{CS35L34_TDM_TX_CTL_1_VMON, 0x00},
{CS35L34_TDM_TX_CTL_2_IMON, 0x04},
{CS35L34_TDM_TX_CTL_3_VPMON, 0x03},
{CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07},
{CS35L34_TDM_TX_CTL_5_FLAG1, 0x08},
{CS35L34_TDM_TX_CTL_6_FLAG2, 0x09},
{CS35L34_TDM_TX_SLOT_EN_1, 0x00},
{CS35L34_TDM_TX_SLOT_EN_2, 0x00},
{CS35L34_TDM_TX_SLOT_EN_3, 0x00},
{CS35L34_TDM_TX_SLOT_EN_4, 0x00},
{CS35L34_TDM_RX_CTL_1_AUDIN, 0x40},
{CS35L34_TDM_RX_CTL_3_ALIVE, 0x04},
{CS35L34_MULT_DEV_SYNCH1, 0x00},
{CS35L34_MULT_DEV_SYNCH2, 0x80},
{CS35L34_PROT_RELEASE_CTL, 0x00},
{CS35L34_DIAG_MODE_REG_LOCK, 0x00},
{CS35L34_DIAG_MODE_CTL_1, 0x00},
{CS35L34_DIAG_MODE_CTL_2, 0x00},
{CS35L34_INT_MASK_1, 0xFF},
{CS35L34_INT_MASK_2, 0xFF},
{CS35L34_INT_MASK_3, 0xFF},
{CS35L34_INT_MASK_4, 0xFF},
{CS35L34_INT_STATUS_1, 0x30},
{CS35L34_INT_STATUS_2, 0x05},
{CS35L34_INT_STATUS_3, 0x00},
{CS35L34_INT_STATUS_4, 0x00},
{CS35L34_OTP_TRIM_STATUS, 0x00},
};
static bool cs35l34_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L34_DEVID_AB:
case CS35L34_DEVID_CD:
case CS35L34_DEVID_E:
case CS35L34_FAB_ID:
case CS35L34_REV_ID:
case CS35L34_INT_STATUS_1:
case CS35L34_INT_STATUS_2:
case CS35L34_INT_STATUS_3:
case CS35L34_INT_STATUS_4:
case CS35L34_CLASS_H_STATUS:
case CS35L34_VPBR_ATTEN_STATUS:
case CS35L34_OTP_TRIM_STATUS:
return true;
default:
return false;
}
}
static bool cs35l34_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L34_DEVID_AB:
case CS35L34_DEVID_CD:
case CS35L34_DEVID_E:
case CS35L34_FAB_ID:
case CS35L34_REV_ID:
case CS35L34_PWRCTL1:
case CS35L34_PWRCTL2:
case CS35L34_PWRCTL3:
case CS35L34_ADSP_CLK_CTL:
case CS35L34_MCLK_CTL:
case CS35L34_AMP_INP_DRV_CTL:
case CS35L34_AMP_DIG_VOL_CTL:
case CS35L34_AMP_DIG_VOL:
case CS35L34_AMP_ANLG_GAIN_CTL:
case CS35L34_PROTECT_CTL:
case CS35L34_AMP_KEEP_ALIVE_CTL:
case CS35L34_BST_CVTR_V_CTL:
case CS35L34_BST_PEAK_I:
case CS35L34_BST_RAMP_CTL:
case CS35L34_BST_CONV_COEF_1:
case CS35L34_BST_CONV_COEF_2:
case CS35L34_BST_CONV_SLOPE_COMP:
case CS35L34_BST_CONV_SW_FREQ:
case CS35L34_CLASS_H_CTL:
case CS35L34_CLASS_H_HEADRM_CTL:
case CS35L34_CLASS_H_RELEASE_RATE:
case CS35L34_CLASS_H_FET_DRIVE_CTL:
case CS35L34_CLASS_H_STATUS:
case CS35L34_VPBR_CTL:
case CS35L34_VPBR_VOL_CTL:
case CS35L34_VPBR_TIMING_CTL:
case CS35L34_PRED_MAX_ATTEN_SPK_LOAD:
case CS35L34_PRED_BROWNOUT_THRESH:
case CS35L34_PRED_BROWNOUT_VOL_CTL:
case CS35L34_PRED_BROWNOUT_RATE_CTL:
case CS35L34_PRED_WAIT_CTL:
case CS35L34_PRED_ZVP_INIT_IMP_CTL:
case CS35L34_PRED_MAN_SAFE_VPI_CTL:
case CS35L34_VPBR_ATTEN_STATUS:
case CS35L34_PRED_BRWNOUT_ATT_STATUS:
case CS35L34_SPKR_MON_CTL:
case CS35L34_ADSP_I2S_CTL:
case CS35L34_ADSP_TDM_CTL:
case CS35L34_TDM_TX_CTL_1_VMON:
case CS35L34_TDM_TX_CTL_2_IMON:
case CS35L34_TDM_TX_CTL_3_VPMON:
case CS35L34_TDM_TX_CTL_4_VBSTMON:
case CS35L34_TDM_TX_CTL_5_FLAG1:
case CS35L34_TDM_TX_CTL_6_FLAG2:
case CS35L34_TDM_TX_SLOT_EN_1:
case CS35L34_TDM_TX_SLOT_EN_2:
case CS35L34_TDM_TX_SLOT_EN_3:
case CS35L34_TDM_TX_SLOT_EN_4:
case CS35L34_TDM_RX_CTL_1_AUDIN:
case CS35L34_TDM_RX_CTL_3_ALIVE:
case CS35L34_MULT_DEV_SYNCH1:
case CS35L34_MULT_DEV_SYNCH2:
case CS35L34_PROT_RELEASE_CTL:
case CS35L34_DIAG_MODE_REG_LOCK:
case CS35L34_DIAG_MODE_CTL_1:
case CS35L34_DIAG_MODE_CTL_2:
case CS35L34_INT_MASK_1:
case CS35L34_INT_MASK_2:
case CS35L34_INT_MASK_3:
case CS35L34_INT_MASK_4:
case CS35L34_INT_STATUS_1:
case CS35L34_INT_STATUS_2:
case CS35L34_INT_STATUS_3:
case CS35L34_INT_STATUS_4:
case CS35L34_OTP_TRIM_STATUS:
return true;
default:
return false;
}
}
static bool cs35l34_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L34_INT_STATUS_1:
case CS35L34_INT_STATUS_2:
case CS35L34_INT_STATUS_3:
case CS35L34_INT_STATUS_4:
return true;
default:
return false;
}
}
static int cs35l34_sdin_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (priv->tdm_mode)
regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
CS35L34_PDN_TDM, 0x00);
ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
CS35L34_PDN_ALL, 0);
if (ret < 0) {
dev_err(component->dev, "Cannot set Power bits %d\n", ret);
return ret;
}
usleep_range(5000, 5100);
break;
case SND_SOC_DAPM_POST_PMD:
if (priv->tdm_mode) {
regmap_update_bits(priv->regmap, CS35L34_PWRCTL3,
CS35L34_PDN_TDM, CS35L34_PDN_TDM);
}
ret = regmap_update_bits(priv->regmap, CS35L34_PWRCTL1,
CS35L34_PDN_ALL, CS35L34_PDN_ALL);
break;
default:
pr_err("Invalid event = 0x%x\n", event);
}
return 0;
}
static int cs35l34_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
unsigned int reg, bit_pos;
int slot, slot_num;
if (slot_width != 8)
return -EINVAL;
priv->tdm_mode = true;
/* scan rx_mask for aud slot */
slot = ffs(rx_mask) - 1;
if (slot >= 0)
snd_soc_component_update_bits(component, CS35L34_TDM_RX_CTL_1_AUDIN,
CS35L34_X_LOC, slot);
/* scan tx_mask: vmon(2 slots); imon (2 slots); vpmon (1 slot)
* vbstmon (1 slot)
*/
slot = ffs(tx_mask) - 1;
slot_num = 0;
/* disable vpmon/vbstmon: enable later if set in tx_mask */
snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
CS35L34_X_STATE | CS35L34_X_LOC,
CS35L34_X_STATE | CS35L34_X_LOC);
snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_4_VBSTMON,
CS35L34_X_STATE | CS35L34_X_LOC,
CS35L34_X_STATE | CS35L34_X_LOC);
/* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
while (slot >= 0) {
/* configure VMON_TX_LOC */
if (slot_num == 0)
snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_1_VMON,
CS35L34_X_STATE | CS35L34_X_LOC, slot);
/* configure IMON_TX_LOC */
if (slot_num == 4) {
snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_2_IMON,
CS35L34_X_STATE | CS35L34_X_LOC, slot);
}
/* configure VPMON_TX_LOC */
if (slot_num == 3) {
snd_soc_component_update_bits(component, CS35L34_TDM_TX_CTL_3_VPMON,
CS35L34_X_STATE | CS35L34_X_LOC, slot);
}
/* configure VBSTMON_TX_LOC */
if (slot_num == 7) {
snd_soc_component_update_bits(component,
CS35L34_TDM_TX_CTL_4_VBSTMON,
CS35L34_X_STATE | CS35L34_X_LOC, slot);
}
/* Enable the relevant tx slot */
reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8);
bit_pos = slot - ((slot / 8) * (8));
snd_soc_component_update_bits(component, reg,
1 << bit_pos, 1 << bit_pos);
tx_mask &= ~(1 << slot);
slot = ffs(tx_mask) - 1;
slot_num++;
}
return 0;
}
static int cs35l34_main_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
CS35L34_BST_CVTL_MASK, priv->pdata.boost_vtge);
usleep_range(5000, 5100);
regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
CS35L34_MUTE, 0);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(priv->regmap, CS35L34_BST_CVTR_V_CTL,
CS35L34_BST_CVTL_MASK, 0);
regmap_update_bits(priv->regmap, CS35L34_PROTECT_CTL,
CS35L34_MUTE, CS35L34_MUTE);
usleep_range(5000, 5100);
break;
default:
pr_err("Invalid event = 0x%x\n", event);
}
return 0;
}
static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 300, 100, 0);
static const struct snd_kcontrol_new cs35l34_snd_controls[] = {
SOC_SINGLE_SX_TLV("Digital Volume", CS35L34_AMP_DIG_VOL,
0, 0x34, 0xE4, dig_vol_tlv),
SOC_SINGLE_TLV("Amp Gain Volume", CS35L34_AMP_ANLG_GAIN_CTL,
0, 0xF, 0, amp_gain_tlv),
};
static int cs35l34_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
int ret, i;
unsigned int reg;
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
ret = regmap_read(priv->regmap, CS35L34_AMP_DIG_VOL_CTL,
®);
if (ret != 0) {
pr_err("%s regmap read failure %d\n", __func__, ret);
return ret;
}
if (reg & CS35L34_AMP_DIGSFT)
msleep(40);
else
usleep_range(2000, 2100);
for (i = 0; i < PDN_DONE_ATTEMPTS; i++) {
ret = regmap_read(priv->regmap, CS35L34_INT_STATUS_2,
®);
if (ret != 0) {
pr_err("%s regmap read failure %d\n",
__func__, ret);
return ret;
}
if (reg & CS35L34_PDN_DONE)
break;
usleep_range(5000, 5100);
}
if (i == PDN_DONE_ATTEMPTS)
pr_err("%s Device did not power down properly\n",
__func__);
break;
default:
pr_err("Invalid event = 0x%x\n", event);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget cs35l34_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L34_PWRCTL3,
1, 1, cs35l34_sdin_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L34_PWRCTL3, 2, 1),
SND_SOC_DAPM_SUPPLY("EXTCLK", CS35L34_PWRCTL3, 7, 1,
cs35l34_mclk_event, SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_INPUT("VP"),
SND_SOC_DAPM_INPUT("VPST"),
SND_SOC_DAPM_INPUT("ISENSE"),
SND_SOC_DAPM_INPUT("VSENSE"),
SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L34_PWRCTL2, 7, 1),
SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L34_PWRCTL2, 6, 1),
SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L34_PWRCTL3, 3, 1),
SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L34_PWRCTL3, 4, 1),
SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L34_PWRCTL2, 5, 1),
SND_SOC_DAPM_ADC("BOOST", NULL, CS35L34_PWRCTL2, 2, 1),
SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L34_PWRCTL2, 0, 1, NULL, 0,
cs35l34_main_amp_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route cs35l34_audio_map[] = {
{"SDIN", NULL, "AMP Playback"},
{"BOOST", NULL, "SDIN"},
{"CLASS H", NULL, "BOOST"},
{"Main AMP", NULL, "CLASS H"},
{"SPK", NULL, "Main AMP"},
{"VPMON ADC", NULL, "CLASS H"},
{"VBSTMON ADC", NULL, "CLASS H"},
{"SPK", NULL, "VPMON ADC"},
{"SPK", NULL, "VBSTMON ADC"},
{"IMON ADC", NULL, "ISENSE"},
{"VMON ADC", NULL, "VSENSE"},
{"SDOUT", NULL, "IMON ADC"},
{"SDOUT", NULL, "VMON ADC"},
{"AMP Capture", NULL, "SDOUT"},
{"SDIN", NULL, "EXTCLK"},
{"SDOUT", NULL, "EXTCLK"},
};
struct cs35l34_mclk_div {
int mclk;
int srate;
u8 adsp_rate;
};
static struct cs35l34_mclk_div cs35l34_mclk_coeffs[] = {
/* MCLK, Sample Rate, adsp_rate */
{5644800, 11025, 0x1},
{5644800, 22050, 0x4},
{5644800, 44100, 0x7},
{6000000, 8000, 0x0},
{6000000, 11025, 0x1},
{6000000, 12000, 0x2},
{6000000, 16000, 0x3},
{6000000, 22050, 0x4},
{6000000, 24000, 0x5},
{6000000, 32000, 0x6},
{6000000, 44100, 0x7},
{6000000, 48000, 0x8},
{6144000, 8000, 0x0},
{6144000, 11025, 0x1},
{6144000, 12000, 0x2},
{6144000, 16000, 0x3},
{6144000, 22050, 0x4},
{6144000, 24000, 0x5},
{6144000, 32000, 0x6},
{6144000, 44100, 0x7},
{6144000, 48000, 0x8},
};
static int cs35l34_get_mclk_coeff(int mclk, int srate)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l34_mclk_coeffs); i++) {
if (cs35l34_mclk_coeffs[i].mclk == mclk &&
cs35l34_mclk_coeffs[i].srate == srate)
return i;
}
return -EINVAL;
}
static int cs35l34_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
0x80, 0x80);
break;
case SND_SOC_DAIFMT_CBS_CFS:
regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
0x80, 0x00);
break;
default:
return -EINVAL;
}
return 0;
}
static int cs35l34_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs35l34_private *priv = snd_soc_component_get_drvdata(component);
int srate = params_rate(params);
int ret;
int coeff = cs35l34_get_mclk_coeff(priv->mclk_int, srate);
if (coeff < 0) {
dev_err(component->dev, "ERROR: Invalid mclk %d and/or srate %d\n",
priv->mclk_int, srate);
return coeff;
}
ret = regmap_update_bits(priv->regmap, CS35L34_ADSP_CLK_CTL,
CS35L34_ADSP_RATE, cs35l34_mclk_coeffs[coeff].adsp_rate);
if (ret != 0)
dev_err(component->dev, "Failed to set clock state %d\n", ret);
return ret;
}
static const unsigned int cs35l34_src_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
};
static const struct snd_pcm_hw_constraint_list cs35l34_constraints = {
.count = ARRAY_SIZE(cs35l34_src_rates),
.list = cs35l34_src_rates,
};
static int cs35l34_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cs35l34_constraints);
return 0;
}
static int cs35l34_set_tristate(struct snd_soc_dai *dai, int tristate)
{
struct snd_soc_component *component = dai->component;
if (tristate)
snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
CS35L34_PDN_SDOUT, CS35L34_PDN_SDOUT);
else
snd_soc_component_update_bits(component, CS35L34_PWRCTL3,
CS35L34_PDN_SDOUT, 0);
return 0;
}
static int cs35l34_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
unsigned int value;
switch (freq) {
case CS35L34_MCLK_5644:
value = CS35L34_MCLK_RATE_5P6448;
cs35l34->mclk_int = freq;
break;
case CS35L34_MCLK_6:
value = CS35L34_MCLK_RATE_6P0000;
cs35l34->mclk_int = freq;
break;
case CS35L34_MCLK_6144:
value = CS35L34_MCLK_RATE_6P1440;
cs35l34->mclk_int = freq;
break;
case CS35L34_MCLK_11289:
value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_5P6448;
cs35l34->mclk_int = freq / 2;
break;
case CS35L34_MCLK_12:
value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P0000;
cs35l34->mclk_int = freq / 2;
break;
case CS35L34_MCLK_12288:
value = CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_6P1440;
cs35l34->mclk_int = freq / 2;
break;
default:
dev_err(component->dev, "ERROR: Invalid Frequency %d\n", freq);
cs35l34->mclk_int = 0;
return -EINVAL;
}
regmap_update_bits(cs35l34->regmap, CS35L34_MCLK_CTL,
CS35L34_MCLK_DIV | CS35L34_MCLK_RATE_MASK, value);
return 0;
}
static const struct snd_soc_dai_ops cs35l34_ops = {
.startup = cs35l34_pcm_startup,
.set_tristate = cs35l34_set_tristate,
.set_fmt = cs35l34_set_dai_fmt,
.hw_params = cs35l34_pcm_hw_params,
.set_sysclk = cs35l34_dai_set_sysclk,
.set_tdm_slot = cs35l34_set_tdm_slot,
};
static struct snd_soc_dai_driver cs35l34_dai = {
.name = "cs35l34",
.id = 0,
.playback = {
.stream_name = "AMP Playback",
.channels_min = 1,
.channels_max = 8,
.rates = CS35L34_RATES,
.formats = CS35L34_FORMATS,
},
.capture = {
.stream_name = "AMP Capture",
.channels_min = 1,
.channels_max = 8,
.rates = CS35L34_RATES,
.formats = CS35L34_FORMATS,
},
.ops = &cs35l34_ops,
.symmetric_rate = 1,
};
static int cs35l34_boost_inductor(struct cs35l34_private *cs35l34,
unsigned int inductor)
{
struct snd_soc_component *component = cs35l34->component;
switch (inductor) {
case 1000: /* 1 uH */
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x24);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x24);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0x4E);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 0);
break;
case 1200: /* 1.2 uH */
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0x47);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 1);
break;
case 1500: /* 1.5uH */
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x20);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x20);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0x3C);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 2);
break;
case 2200: /* 2.2uH */
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_1, 0x19);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_COEF_2, 0x25);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SLOPE_COMP,
0x23);
regmap_write(cs35l34->regmap, CS35L34_BST_CONV_SW_FREQ, 3);
break;
default:
dev_err(component->dev, "%s Invalid Inductor Value %d uH\n",
__func__, inductor);
return -EINVAL;
}
return 0;
}
static int cs35l34_probe(struct snd_soc_component *component)
{
int ret = 0;
struct cs35l34_private *cs35l34 = snd_soc_component_get_drvdata(component);
pm_runtime_get_sync(component->dev);
/* Set over temperature warning attenuation to 6 dB */
regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
CS35L34_OTW_ATTN_MASK, 0x8);
/* Set Power control registers 2 and 3 to have everything
* powered down at initialization
*/
regmap_write(cs35l34->regmap, CS35L34_PWRCTL2, 0xFD);
regmap_write(cs35l34->regmap, CS35L34_PWRCTL3, 0x1F);
/* Set mute bit at startup */
regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
CS35L34_MUTE, CS35L34_MUTE);
/* Set Platform Data */
if (cs35l34->pdata.boost_peak)
regmap_update_bits(cs35l34->regmap, CS35L34_BST_PEAK_I,
CS35L34_BST_PEAK_MASK,
cs35l34->pdata.boost_peak);
if (cs35l34->pdata.gain_zc_disable)
regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
CS35L34_GAIN_ZC_MASK, 0);
else
regmap_update_bits(cs35l34->regmap, CS35L34_PROTECT_CTL,
CS35L34_GAIN_ZC_MASK, CS35L34_GAIN_ZC_MASK);
if (cs35l34->pdata.aif_half_drv)
regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_CLK_CTL,
CS35L34_ADSP_DRIVE, 0);
if (cs35l34->pdata.digsft_disable)
regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
CS35L34_AMP_DIGSFT, 0);
if (cs35l34->pdata.amp_inv)
regmap_update_bits(cs35l34->regmap, CS35L34_AMP_DIG_VOL_CTL,
CS35L34_INV, CS35L34_INV);
if (cs35l34->pdata.boost_ind)
ret = cs35l34_boost_inductor(cs35l34, cs35l34->pdata.boost_ind);
if (cs35l34->pdata.i2s_sdinloc)
regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_I2S_CTL,
CS35L34_I2S_LOC_MASK,
cs35l34->pdata.i2s_sdinloc << CS35L34_I2S_LOC_SHIFT);
if (cs35l34->pdata.tdm_rising_edge)
regmap_update_bits(cs35l34->regmap, CS35L34_ADSP_TDM_CTL,
1, 1);
pm_runtime_put_sync(component->dev);
return ret;
}
static const struct snd_soc_component_driver soc_component_dev_cs35l34 = {
.probe = cs35l34_probe,
.dapm_widgets = cs35l34_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l34_dapm_widgets),
.dapm_routes = cs35l34_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l34_audio_map),
.controls = cs35l34_snd_controls,
.num_controls = ARRAY_SIZE(cs35l34_snd_controls),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct regmap_config cs35l34_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS35L34_MAX_REGISTER,
.reg_defaults = cs35l34_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l34_reg),
.volatile_reg = cs35l34_volatile_register,
.readable_reg = cs35l34_readable_register,
.precious_reg = cs35l34_precious_register,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static int cs35l34_handle_of_data(struct i2c_client *i2c_client,
struct cs35l34_platform_data *pdata)
{
struct device_node *np = i2c_client->dev.of_node;
unsigned int val;
if (of_property_read_u32(np, "cirrus,boost-vtge-millivolt",
&val) >= 0) {
/* Boost Voltage has a maximum of 8V */
if (val > 8000 || (val < 3300 && val > 0)) {
dev_err(&i2c_client->dev,
"Invalid Boost Voltage %d mV\n", val);
return -EINVAL;
}
if (val == 0)
pdata->boost_vtge = 0; /* Use VP */
else
pdata->boost_vtge = ((val - 3300)/100) + 1;
} else {
dev_warn(&i2c_client->dev,
"Boost Voltage not specified. Using VP\n");
}
if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
pdata->boost_ind = val;
} else {
dev_err(&i2c_client->dev, "Inductor not specified.\n");
return -EINVAL;
}
if (of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val) >= 0) {
if (val > 3840 || val < 1200) {
dev_err(&i2c_client->dev,
"Invalid Boost Peak Current %d mA\n", val);
return -EINVAL;
}
pdata->boost_peak = ((val - 1200)/80) + 1;
}
pdata->aif_half_drv = of_property_read_bool(np,
"cirrus,aif-half-drv");
pdata->digsft_disable = of_property_read_bool(np,
"cirrus,digsft-disable");
pdata->gain_zc_disable = of_property_read_bool(np,
"cirrus,gain-zc-disable");
pdata->amp_inv = of_property_read_bool(np, "cirrus,amp-inv");
if (of_property_read_u32(np, "cirrus,i2s-sdinloc", &val) >= 0)
pdata->i2s_sdinloc = val;
if (of_property_read_u32(np, "cirrus,tdm-rising-edge", &val) >= 0)
pdata->tdm_rising_edge = val;
return 0;
}
static irqreturn_t cs35l34_irq_thread(int irq, void *data)
{
struct cs35l34_private *cs35l34 = data;
struct snd_soc_component *component = cs35l34->component;
unsigned int sticky1, sticky2, sticky3, sticky4;
unsigned int mask1, mask2, mask3, mask4, current1;
/* ack the irq by reading all status registers */
regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_4, &sticky4);
regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_3, &sticky3);
regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_2, &sticky2);
regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, &sticky1);
regmap_read(cs35l34->regmap, CS35L34_INT_MASK_4, &mask4);
regmap_read(cs35l34->regmap, CS35L34_INT_MASK_3, &mask3);
regmap_read(cs35l34->regmap, CS35L34_INT_MASK_2, &mask2);
regmap_read(cs35l34->regmap, CS35L34_INT_MASK_1, &mask1);
if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
&& !(sticky4 & ~mask4))
return IRQ_NONE;
regmap_read(cs35l34->regmap, CS35L34_INT_STATUS_1, ¤t1);
if (sticky1 & CS35L34_CAL_ERR) {
dev_err(component->dev, "Cal error\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L34_CAL_ERR)) {
dev_dbg(component->dev, "Cal error release\n");
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_CAL_ERR_RLS, 0);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_CAL_ERR_RLS,
CS35L34_CAL_ERR_RLS);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_CAL_ERR_RLS, 0);
/* note: amp will re-calibrate on next resume */
}
}
if (sticky1 & CS35L34_ALIVE_ERR)
dev_err(component->dev, "Alive error\n");
if (sticky1 & CS35L34_AMP_SHORT) {
dev_crit(component->dev, "Amp short error\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L34_AMP_SHORT)) {
dev_dbg(component->dev,
"Amp short error release\n");
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_SHORT_RLS, 0);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_SHORT_RLS,
CS35L34_SHORT_RLS);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_SHORT_RLS, 0);
}
}
if (sticky1 & CS35L34_OTW) {
dev_crit(component->dev, "Over temperature warning\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L34_OTW)) {
dev_dbg(component->dev,
"Over temperature warning release\n");
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_OTW_RLS, 0);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_OTW_RLS,
CS35L34_OTW_RLS);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_OTW_RLS, 0);
}
}
if (sticky1 & CS35L34_OTE) {
dev_crit(component->dev, "Over temperature error\n");
/* error is no longer asserted; safe to reset */
if (!(current1 & CS35L34_OTE)) {
dev_dbg(component->dev,
"Over temperature error release\n");
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_OTE_RLS, 0);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_OTE_RLS,
CS35L34_OTE_RLS);
regmap_update_bits(cs35l34->regmap,
CS35L34_PROT_RELEASE_CTL,
CS35L34_OTE_RLS, 0);
}
}
if (sticky3 & CS35L34_BST_HIGH) {
dev_crit(component->dev, "VBST too high error; powering off!\n");
regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
CS35L34_PDN_AMP, CS35L34_PDN_AMP);
regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
CS35L34_PDN_ALL, CS35L34_PDN_ALL);
}
if (sticky3 & CS35L34_LBST_SHORT) {
dev_crit(component->dev, "LBST short error; powering off!\n");
regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL2,
CS35L34_PDN_AMP, CS35L34_PDN_AMP);
regmap_update_bits(cs35l34->regmap, CS35L34_PWRCTL1,
CS35L34_PDN_ALL, CS35L34_PDN_ALL);
}
return IRQ_HANDLED;
}
static const char * const cs35l34_core_supplies[] = {
"VA",
"VP",
};
static int cs35l34_i2c_probe(struct i2c_client *i2c_client)
{
struct cs35l34_private *cs35l34;
struct cs35l34_platform_data *pdata =
dev_get_platdata(&i2c_client->dev);
int i, devid;
int ret;
unsigned int reg;
cs35l34 = devm_kzalloc(&i2c_client->dev, sizeof(*cs35l34), GFP_KERNEL);
if (!cs35l34)
return -ENOMEM;
i2c_set_clientdata(i2c_client, cs35l34);
cs35l34->regmap = devm_regmap_init_i2c(i2c_client, &cs35l34_regmap);
if (IS_ERR(cs35l34->regmap)) {
ret = PTR_ERR(cs35l34->regmap);
dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
cs35l34->num_core_supplies = ARRAY_SIZE(cs35l34_core_supplies);
for (i = 0; i < ARRAY_SIZE(cs35l34_core_supplies); i++)
cs35l34->core_supplies[i].supply = cs35l34_core_supplies[i];
ret = devm_regulator_bulk_get(&i2c_client->dev,
cs35l34->num_core_supplies,
cs35l34->core_supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to request core supplies %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(cs35l34->num_core_supplies,
cs35l34->core_supplies);
if (ret != 0) {
dev_err(&i2c_client->dev,
"Failed to enable core supplies: %d\n", ret);
return ret;
}
if (pdata) {
cs35l34->pdata = *pdata;
} else {
pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata) {
ret = -ENOMEM;
goto err_regulator;
}
if (i2c_client->dev.of_node) {
ret = cs35l34_handle_of_data(i2c_client, pdata);
if (ret != 0)
goto err_regulator;
}
cs35l34->pdata = *pdata;
}
ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
cs35l34_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
"cs35l34", cs35l34);
if (ret != 0)
dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
cs35l34->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
"reset-gpios", GPIOD_OUT_LOW);
if (IS_ERR(cs35l34->reset_gpio)) {
ret = PTR_ERR(cs35l34->reset_gpio);
goto err_regulator;
}
gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
msleep(CS35L34_START_DELAY);
devid = cirrus_read_device_id(cs35l34->regmap, CS35L34_DEVID_AB);
if (devid < 0) {
ret = devid;
dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
goto err_reset;
}
if (devid != CS35L34_CHIP_ID) {
dev_err(&i2c_client->dev,
"CS35l34 Device ID (%X). Expected ID %X\n",
devid, CS35L34_CHIP_ID);
ret = -ENODEV;
goto err_reset;
}
ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, ®);
if (ret < 0) {
dev_err(&i2c_client->dev, "Get Revision ID failed\n");
goto err_reset;
}
dev_info(&i2c_client->dev,
"Cirrus Logic CS35l34 (%x), Revision: %02X\n", devid,
reg & 0xFF);
/* Unmask critical interrupts */
regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_1,
CS35L34_M_CAL_ERR | CS35L34_M_ALIVE_ERR |
CS35L34_M_AMP_SHORT | CS35L34_M_OTW |
CS35L34_M_OTE, 0);
regmap_update_bits(cs35l34->regmap, CS35L34_INT_MASK_3,
CS35L34_M_BST_HIGH | CS35L34_M_LBST_SHORT, 0);
pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
pm_runtime_use_autosuspend(&i2c_client->dev);
pm_runtime_set_active(&i2c_client->dev);
pm_runtime_enable(&i2c_client->dev);
ret = devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_cs35l34, &cs35l34_dai, 1);
if (ret < 0) {
dev_err(&i2c_client->dev,
"%s: Register component failed\n", __func__);
goto err_reset;
}
return 0;
err_reset:
gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
err_regulator:
regulator_bulk_disable(cs35l34->num_core_supplies,
cs35l34->core_supplies);
return ret;
}
static void cs35l34_i2c_remove(struct i2c_client *client)
{
struct cs35l34_private *cs35l34 = i2c_get_clientdata(client);
gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
pm_runtime_disable(&client->dev);
regulator_bulk_disable(cs35l34->num_core_supplies,
cs35l34->core_supplies);
}
static int __maybe_unused cs35l34_runtime_resume(struct device *dev)
{
struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
int ret;
ret = regulator_bulk_enable(cs35l34->num_core_supplies,
cs35l34->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n",
ret);
return ret;
}
regcache_cache_only(cs35l34->regmap, false);
gpiod_set_value_cansleep(cs35l34->reset_gpio, 1);
msleep(CS35L34_START_DELAY);
ret = regcache_sync(cs35l34->regmap);
if (ret != 0) {
dev_err(dev, "Failed to restore register cache\n");
goto err;
}
return 0;
err:
regcache_cache_only(cs35l34->regmap, true);
regulator_bulk_disable(cs35l34->num_core_supplies,
cs35l34->core_supplies);
return ret;
}
static int __maybe_unused cs35l34_runtime_suspend(struct device *dev)
{
struct cs35l34_private *cs35l34 = dev_get_drvdata(dev);
regcache_cache_only(cs35l34->regmap, true);
regcache_mark_dirty(cs35l34->regmap);
gpiod_set_value_cansleep(cs35l34->reset_gpio, 0);
regulator_bulk_disable(cs35l34->num_core_supplies,
cs35l34->core_supplies);
return 0;
}
static const struct dev_pm_ops cs35l34_pm_ops = {
SET_RUNTIME_PM_OPS(cs35l34_runtime_suspend,
cs35l34_runtime_resume,
NULL)
};
static const struct of_device_id cs35l34_of_match[] = {
{.compatible = "cirrus,cs35l34"},
{},
};
MODULE_DEVICE_TABLE(of, cs35l34_of_match);
static const struct i2c_device_id cs35l34_id[] = {
{"cs35l34", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l34_id);
static struct i2c_driver cs35l34_i2c_driver = {
.driver = {
.name = "cs35l34",
.pm = &cs35l34_pm_ops,
.of_match_table = cs35l34_of_match,
},
.id_table = cs35l34_id,
.probe = cs35l34_i2c_probe,
.remove = cs35l34_i2c_remove,
};
static int __init cs35l34_modinit(void)
{
int ret;
ret = i2c_add_driver(&cs35l34_i2c_driver);
if (ret != 0) {
pr_err("Failed to register CS35l34 I2C driver: %d\n", ret);
return ret;
}
return 0;
}
module_init(cs35l34_modinit);
static void __exit cs35l34_exit(void)
{
i2c_del_driver(&cs35l34_i2c_driver);
}
module_exit(cs35l34_exit);
MODULE_DESCRIPTION("ASoC CS35l34 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l34.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max98926.c -- ALSA SoC MAX98926 driver
* Copyright 2013-15 Maxim Integrated Products
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98926.h"
static const char * const max98926_boost_voltage_txt[] = {
"8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
"6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
};
static const char *const max98926_pdm_ch_text[] = {
"Current", "Voltage",
};
static const char *const max98926_hpf_cutoff_txt[] = {
"Disable", "DC Block", "100Hz",
"200Hz", "400Hz", "800Hz",
};
static const struct reg_default max98926_reg[] = {
{ 0x0B, 0x00 }, /* IRQ Enable0 */
{ 0x0C, 0x00 }, /* IRQ Enable1 */
{ 0x0D, 0x00 }, /* IRQ Enable2 */
{ 0x0E, 0x00 }, /* IRQ Clear0 */
{ 0x0F, 0x00 }, /* IRQ Clear1 */
{ 0x10, 0x00 }, /* IRQ Clear2 */
{ 0x11, 0xC0 }, /* Map0 */
{ 0x12, 0x00 }, /* Map1 */
{ 0x13, 0x00 }, /* Map2 */
{ 0x14, 0xF0 }, /* Map3 */
{ 0x15, 0x00 }, /* Map4 */
{ 0x16, 0xAB }, /* Map5 */
{ 0x17, 0x89 }, /* Map6 */
{ 0x18, 0x00 }, /* Map7 */
{ 0x19, 0x00 }, /* Map8 */
{ 0x1A, 0x04 }, /* DAI Clock Mode 1 */
{ 0x1B, 0x00 }, /* DAI Clock Mode 2 */
{ 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
{ 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
{ 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
{ 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
{ 0x20, 0x50 }, /* Format */
{ 0x21, 0x00 }, /* TDM Slot Select */
{ 0x22, 0x00 }, /* DOUT Configuration VMON */
{ 0x23, 0x00 }, /* DOUT Configuration IMON */
{ 0x24, 0x00 }, /* DOUT Configuration VBAT */
{ 0x25, 0x00 }, /* DOUT Configuration VBST */
{ 0x26, 0x00 }, /* DOUT Configuration FLAG */
{ 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
{ 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
{ 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
{ 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
{ 0x2B, 0x02 }, /* DOUT Drive Strength */
{ 0x2C, 0x90 }, /* Filters */
{ 0x2D, 0x00 }, /* Gain */
{ 0x2E, 0x02 }, /* Gain Ramping */
{ 0x2F, 0x00 }, /* Speaker Amplifier */
{ 0x30, 0x0A }, /* Threshold */
{ 0x31, 0x00 }, /* ALC Attack */
{ 0x32, 0x80 }, /* ALC Atten and Release */
{ 0x33, 0x00 }, /* ALC Infinite Hold Release */
{ 0x34, 0x92 }, /* ALC Configuration */
{ 0x35, 0x01 }, /* Boost Converter */
{ 0x36, 0x00 }, /* Block Enable */
{ 0x37, 0x00 }, /* Configuration */
{ 0x38, 0x00 }, /* Global Enable */
{ 0x3A, 0x00 }, /* Boost Limiter */
};
static const struct soc_enum max98926_voltage_enum[] = {
SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS, 0,
ARRAY_SIZE(max98926_pdm_ch_text),
max98926_pdm_ch_text),
};
static const struct snd_kcontrol_new max98926_voltage_control =
SOC_DAPM_ENUM("Route", max98926_voltage_enum);
static const struct soc_enum max98926_current_enum[] = {
SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS,
MAX98926_PDM_SOURCE_1_SHIFT,
ARRAY_SIZE(max98926_pdm_ch_text),
max98926_pdm_ch_text),
};
static const struct snd_kcontrol_new max98926_current_control =
SOC_DAPM_ENUM("Route", max98926_current_enum);
static const struct snd_kcontrol_new max98926_mixer_controls[] = {
SOC_DAPM_SINGLE("PCM Single Switch", MAX98926_SPK_AMP,
MAX98926_INSELECT_MODE_SHIFT, 0, 0),
SOC_DAPM_SINGLE("PDM Single Switch", MAX98926_SPK_AMP,
MAX98926_INSELECT_MODE_SHIFT, 1, 0),
};
static const struct snd_kcontrol_new max98926_dai_controls[] = {
SOC_DAPM_SINGLE("Left", MAX98926_GAIN,
MAX98926_DAC_IN_SEL_SHIFT, 0, 0),
SOC_DAPM_SINGLE("Right", MAX98926_GAIN,
MAX98926_DAC_IN_SEL_SHIFT, 1, 0),
SOC_DAPM_SINGLE("LeftRight", MAX98926_GAIN,
MAX98926_DAC_IN_SEL_SHIFT, 2, 0),
SOC_DAPM_SINGLE("(Left+Right)/2 Switch", MAX98926_GAIN,
MAX98926_DAC_IN_SEL_SHIFT, 3, 0),
};
static const struct snd_soc_dapm_widget max98926_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("Amp Enable", NULL, MAX98926_BLOCK_ENABLE,
MAX98926_SPK_EN_SHIFT, 0),
SND_SOC_DAPM_SUPPLY("Global Enable", MAX98926_GLOBAL_ENABLE,
MAX98926_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VI Enable", MAX98926_BLOCK_ENABLE,
MAX98926_ADC_IMON_EN_WIDTH |
MAX98926_ADC_VMON_EN_SHIFT,
0, NULL, 0),
SND_SOC_DAPM_PGA("BST Enable", MAX98926_BLOCK_ENABLE,
MAX98926_BST_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_MIXER("PCM Sel", MAX98926_SPK_AMP,
MAX98926_INSELECT_MODE_SHIFT, 0,
&max98926_mixer_controls[0],
ARRAY_SIZE(max98926_mixer_controls)),
SND_SOC_DAPM_MIXER("DAI Sel",
MAX98926_GAIN, MAX98926_DAC_IN_SEL_SHIFT, 0,
&max98926_dai_controls[0],
ARRAY_SIZE(max98926_dai_controls)),
SND_SOC_DAPM_MUX("PDM CH1 Source",
MAX98926_DAI_CLK_DIV_N_LSBS,
MAX98926_PDM_CURRENT_SHIFT,
0, &max98926_current_control),
SND_SOC_DAPM_MUX("PDM CH0 Source",
MAX98926_DAI_CLK_DIV_N_LSBS,
MAX98926_PDM_VOLTAGE_SHIFT,
0, &max98926_voltage_control),
};
static const struct snd_soc_dapm_route max98926_audio_map[] = {
{"VI Enable", NULL, "DAI_OUT"},
{"DAI Sel", "Left", "VI Enable"},
{"DAI Sel", "Right", "VI Enable"},
{"DAI Sel", "LeftRight", "VI Enable"},
{"DAI Sel", "LeftRightDiv2", "VI Enable"},
{"PCM Sel", "PCM", "DAI Sel"},
{"PDM CH1 Source", "Current", "DAI_OUT"},
{"PDM CH1 Source", "Voltage", "DAI_OUT"},
{"PDM CH0 Source", "Current", "DAI_OUT"},
{"PDM CH0 Source", "Voltage", "DAI_OUT"},
{"PCM Sel", "Analog", "PDM CH1 Source"},
{"PCM Sel", "Analog", "PDM CH0 Source"},
{"Amp Enable", NULL, "PCM Sel"},
{"BST Enable", NULL, "Amp Enable"},
{"BE_OUT", NULL, "BST Enable"},
};
static bool max98926_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98926_VBAT_DATA:
case MAX98926_VBST_DATA:
case MAX98926_LIVE_STATUS0:
case MAX98926_LIVE_STATUS1:
case MAX98926_LIVE_STATUS2:
case MAX98926_STATE0:
case MAX98926_STATE1:
case MAX98926_STATE2:
case MAX98926_FLAG0:
case MAX98926_FLAG1:
case MAX98926_FLAG2:
case MAX98926_VERSION:
return true;
default:
return false;
}
}
static bool max98926_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98926_IRQ_CLEAR0:
case MAX98926_IRQ_CLEAR1:
case MAX98926_IRQ_CLEAR2:
case MAX98926_ALC_HOLD_RLS:
return false;
default:
return true;
}
};
static DECLARE_TLV_DB_SCALE(max98926_spk_tlv, -600, 100, 0);
static DECLARE_TLV_DB_RANGE(max98926_current_tlv,
0, 11, TLV_DB_SCALE_ITEM(20, 20, 0),
12, 15, TLV_DB_SCALE_ITEM(320, 40, 0),
);
static SOC_ENUM_SINGLE_DECL(max98926_dac_hpf_cutoff,
MAX98926_FILTERS, MAX98926_DAC_HPF_SHIFT,
max98926_hpf_cutoff_txt);
static SOC_ENUM_SINGLE_DECL(max98926_boost_voltage,
MAX98926_CONFIGURATION, MAX98926_BST_VOUT_SHIFT,
max98926_boost_voltage_txt);
static const struct snd_kcontrol_new max98926_snd_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", MAX98926_GAIN,
MAX98926_SPK_GAIN_SHIFT,
(1<<MAX98926_SPK_GAIN_WIDTH)-1, 0,
max98926_spk_tlv),
SOC_SINGLE("Ramp Switch", MAX98926_GAIN_RAMPING,
MAX98926_SPK_RMP_EN_SHIFT, 1, 0),
SOC_SINGLE("ZCD Switch", MAX98926_GAIN_RAMPING,
MAX98926_SPK_ZCD_EN_SHIFT, 1, 0),
SOC_SINGLE("ALC Switch", MAX98926_THRESHOLD,
MAX98926_ALC_EN_SHIFT, 1, 0),
SOC_SINGLE("ALC Threshold", MAX98926_THRESHOLD,
MAX98926_ALC_TH_SHIFT,
(1<<MAX98926_ALC_TH_WIDTH)-1, 0),
SOC_ENUM("Boost Output Voltage", max98926_boost_voltage),
SOC_SINGLE_TLV("Boost Current Limit", MAX98926_BOOST_LIMITER,
MAX98926_BST_ILIM_SHIFT,
(1<<MAX98926_BST_ILIM_SHIFT)-1, 0,
max98926_current_tlv),
SOC_ENUM("DAC HPF Cutoff", max98926_dac_hpf_cutoff),
SOC_DOUBLE("PDM Channel One", MAX98926_DAI_CLK_DIV_N_LSBS,
MAX98926_PDM_CHANNEL_1_SHIFT,
MAX98926_PDM_CHANNEL_1_HIZ, 1, 0),
SOC_DOUBLE("PDM Channel Zero", MAX98926_DAI_CLK_DIV_N_LSBS,
MAX98926_PDM_CHANNEL_0_SHIFT,
MAX98926_PDM_CHANNEL_0_HIZ, 1, 0),
};
static const struct {
int rate;
int sr;
} rate_table[] = {
{
.rate = 8000,
.sr = 0,
},
{
.rate = 11025,
.sr = 1,
},
{
.rate = 12000,
.sr = 2,
},
{
.rate = 16000,
.sr = 3,
},
{
.rate = 22050,
.sr = 4,
},
{
.rate = 24000,
.sr = 5,
},
{
.rate = 32000,
.sr = 6,
},
{
.rate = 44100,
.sr = 7,
},
{
.rate = 48000,
.sr = 8,
},
};
static void max98926_set_sense_data(struct max98926_priv *max98926)
{
regmap_update_bits(max98926->regmap,
MAX98926_DOUT_CFG_VMON,
MAX98926_DAI_VMON_EN_MASK,
MAX98926_DAI_VMON_EN_MASK);
regmap_update_bits(max98926->regmap,
MAX98926_DOUT_CFG_IMON,
MAX98926_DAI_IMON_EN_MASK,
MAX98926_DAI_IMON_EN_MASK);
if (!max98926->interleave_mode) {
/* set VMON slots */
regmap_update_bits(max98926->regmap,
MAX98926_DOUT_CFG_VMON,
MAX98926_DAI_VMON_SLOT_MASK,
max98926->v_slot);
/* set IMON slots */
regmap_update_bits(max98926->regmap,
MAX98926_DOUT_CFG_IMON,
MAX98926_DAI_IMON_SLOT_MASK,
max98926->i_slot);
} else {
/* enable interleave mode */
regmap_update_bits(max98926->regmap,
MAX98926_FORMAT,
MAX98926_DAI_INTERLEAVE_MASK,
MAX98926_DAI_INTERLEAVE_MASK);
/* set interleave slots */
regmap_update_bits(max98926->regmap,
MAX98926_DOUT_CFG_VBAT,
MAX98926_DAI_INTERLEAVE_SLOT_MASK,
max98926->v_slot);
}
}
static int max98926_dai_set_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98926_priv *max98926 = snd_soc_component_get_drvdata(component);
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
max98926_set_sense_data(max98926);
break;
default:
dev_err(component->dev, "DAI clock mode unsupported\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
invert = MAX98926_DAI_WCI_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98926_DAI_BCI_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
invert = MAX98926_DAI_BCI_MASK | MAX98926_DAI_WCI_MASK;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_write(max98926->regmap,
MAX98926_FORMAT, MAX98926_DAI_DLY_MASK);
regmap_update_bits(max98926->regmap, MAX98926_FORMAT,
MAX98926_DAI_BCI_MASK, invert);
return 0;
}
static int max98926_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int dai_sr = -EINVAL;
int rate = params_rate(params), i;
struct snd_soc_component *component = dai->component;
struct max98926_priv *max98926 = snd_soc_component_get_drvdata(component);
int blr_clk_ratio;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
regmap_update_bits(max98926->regmap,
MAX98926_FORMAT,
MAX98926_DAI_CHANSZ_MASK,
MAX98926_DAI_CHANSZ_16);
max98926->ch_size = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
regmap_update_bits(max98926->regmap,
MAX98926_FORMAT,
MAX98926_DAI_CHANSZ_MASK,
MAX98926_DAI_CHANSZ_24);
max98926->ch_size = 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
regmap_update_bits(max98926->regmap,
MAX98926_FORMAT,
MAX98926_DAI_CHANSZ_MASK,
MAX98926_DAI_CHANSZ_32);
max98926->ch_size = 32;
break;
default:
dev_dbg(component->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
/* BCLK/LRCLK ratio calculation */
blr_clk_ratio = params_channels(params) * max98926->ch_size;
switch (blr_clk_ratio) {
case 32:
regmap_update_bits(max98926->regmap,
MAX98926_DAI_CLK_MODE2,
MAX98926_DAI_BSEL_MASK,
MAX98926_DAI_BSEL_32);
break;
case 48:
regmap_update_bits(max98926->regmap,
MAX98926_DAI_CLK_MODE2,
MAX98926_DAI_BSEL_MASK,
MAX98926_DAI_BSEL_48);
break;
case 64:
regmap_update_bits(max98926->regmap,
MAX98926_DAI_CLK_MODE2,
MAX98926_DAI_BSEL_MASK,
MAX98926_DAI_BSEL_64);
break;
default:
return -EINVAL;
}
/* find the closest rate */
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i].rate >= rate) {
dai_sr = rate_table[i].sr;
break;
}
}
if (dai_sr < 0)
return -EINVAL;
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98926->regmap,
MAX98926_DAI_CLK_MODE2,
MAX98926_DAI_SR_MASK, dai_sr << MAX98926_DAI_SR_SHIFT);
return 0;
}
#define MAX98926_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98926_dai_ops = {
.set_fmt = max98926_dai_set_fmt,
.hw_params = max98926_dai_hw_params,
};
static struct snd_soc_dai_driver max98926_dai[] = {
{
.name = "max98926-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = MAX98926_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = MAX98926_FORMATS,
},
.ops = &max98926_dai_ops,
}
};
static int max98926_probe(struct snd_soc_component *component)
{
struct max98926_priv *max98926 = snd_soc_component_get_drvdata(component);
max98926->component = component;
/* Hi-Z all the slots */
regmap_write(max98926->regmap, MAX98926_DOUT_HIZ_CFG4, 0xF0);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_max98926 = {
.probe = max98926_probe,
.controls = max98926_snd_controls,
.num_controls = ARRAY_SIZE(max98926_snd_controls),
.dapm_routes = max98926_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98926_audio_map),
.dapm_widgets = max98926_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98926_dapm_widgets),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98926_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX98926_VERSION,
.reg_defaults = max98926_reg,
.num_reg_defaults = ARRAY_SIZE(max98926_reg),
.volatile_reg = max98926_volatile_register,
.readable_reg = max98926_readable_register,
.cache_type = REGCACHE_RBTREE,
};
static int max98926_i2c_probe(struct i2c_client *i2c)
{
int ret, reg;
u32 value;
struct max98926_priv *max98926;
max98926 = devm_kzalloc(&i2c->dev,
sizeof(*max98926), GFP_KERNEL);
if (!max98926)
return -ENOMEM;
i2c_set_clientdata(i2c, max98926);
max98926->regmap = devm_regmap_init_i2c(i2c, &max98926_regmap);
if (IS_ERR(max98926->regmap)) {
ret = PTR_ERR(max98926->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
goto err_out;
}
if (of_property_read_bool(i2c->dev.of_node, "maxim,interleave-mode") ||
of_property_read_bool(i2c->dev.of_node, "interleave-mode"))
max98926->interleave_mode = true;
if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
if (value > MAX98926_DAI_VMON_SLOT_1E_1F) {
dev_err(&i2c->dev, "vmon slot number is wrong:\n");
return -EINVAL;
}
max98926->v_slot = value;
}
if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
if (value > MAX98926_DAI_IMON_SLOT_1E_1F) {
dev_err(&i2c->dev, "imon slot number is wrong:\n");
return -EINVAL;
}
max98926->i_slot = value;
}
ret = regmap_read(max98926->regmap,
MAX98926_VERSION, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read: %x\n", reg);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_max98926,
max98926_dai, ARRAY_SIZE(max98926_dai));
if (ret < 0)
dev_err(&i2c->dev,
"Failed to register component: %d\n", ret);
dev_info(&i2c->dev, "device version: %x\n", reg);
err_out:
return ret;
}
static const struct i2c_device_id max98926_i2c_id[] = {
{ "max98926", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max98926_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id max98926_of_match[] = {
{ .compatible = "maxim,max98926", },
{ }
};
MODULE_DEVICE_TABLE(of, max98926_of_match);
#endif
static struct i2c_driver max98926_i2c_driver = {
.driver = {
.name = "max98926",
.of_match_table = of_match_ptr(max98926_of_match),
},
.probe = max98926_i2c_probe,
.id_table = max98926_i2c_id,
};
module_i2c_driver(max98926_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98926 driver");
MODULE_AUTHOR("Anish kumar <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98926.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// uda1334.c -- UDA1334 ALSA SoC Audio driver
//
// Based on WM8523 ALSA SoC Audio driver written by Mark Brown
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#define UDA1334_NUM_RATES 6
/* codec private data */
struct uda1334_priv {
struct gpio_desc *mute;
struct gpio_desc *deemph;
unsigned int sysclk;
unsigned int rate_constraint_list[UDA1334_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
};
static const struct snd_soc_dapm_widget uda1334_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
};
static const struct snd_soc_dapm_route uda1334_dapm_routes[] = {
{ "LINEVOUTL", NULL, "DAC" },
{ "LINEVOUTR", NULL, "DAC" },
};
static int uda1334_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
int deemph = ucontrol->value.integer.value[0];
if (deemph > 1)
return -EINVAL;
gpiod_set_value_cansleep(uda1334->deemph, deemph);
return 0;
};
static int uda1334_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
int ret;
ret = gpiod_get_value_cansleep(uda1334->deemph);
if (ret < 0)
return -EINVAL;
ucontrol->value.integer.value[0] = ret;
return 0;
};
static const struct snd_kcontrol_new uda1334_snd_controls[] = {
SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
uda1334_get_deemph, uda1334_put_deemph),
};
static const struct {
int value;
int ratio;
} lrclk_ratios[UDA1334_NUM_RATES] = {
{ 1, 128 },
{ 2, 192 },
{ 3, 256 },
{ 4, 384 },
{ 5, 512 },
{ 6, 768 },
};
static int uda1334_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
/*
* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!uda1334->sysclk) {
dev_err(component->dev,
"No MCLK configured, call set_sysclk() on init\n");
return -EINVAL;
}
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&uda1334->rate_constraint);
gpiod_set_value_cansleep(uda1334->mute, 1);
return 0;
}
static void uda1334_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
gpiod_set_value_cansleep(uda1334->mute, 0);
}
static int uda1334_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
unsigned int val;
int i, j = 0;
uda1334->sysclk = freq;
uda1334->rate_constraint.count = 0;
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
val = freq / lrclk_ratios[i].ratio;
/*
* Check that it's a standard rate since core can't
* cope with others and having the odd rates confuses
* constraint matching.
*/
switch (val) {
case 8000:
case 32000:
case 44100:
case 48000:
case 64000:
case 88200:
case 96000:
dev_dbg(component->dev, "Supported sample rate: %dHz\n",
val);
uda1334->rate_constraint_list[j++] = val;
uda1334->rate_constraint.count++;
break;
default:
dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
val);
}
}
/* Need at least one supported rate... */
if (uda1334->rate_constraint.count == 0)
return -EINVAL;
return 0;
}
static int uda1334_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
fmt &= (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK |
SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
if (fmt != (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC)) {
dev_err(codec_dai->dev, "Invalid DAI format\n");
return -EINVAL;
}
return 0;
}
static int uda1334_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(dai->component);
if (uda1334->mute)
gpiod_set_value_cansleep(uda1334->mute, mute);
return 0;
}
#define UDA1334_RATES SNDRV_PCM_RATE_8000_96000
#define UDA1334_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops uda1334_dai_ops = {
.startup = uda1334_startup,
.shutdown = uda1334_shutdown,
.set_sysclk = uda1334_set_dai_sysclk,
.set_fmt = uda1334_set_fmt,
.mute_stream = uda1334_mute_stream,
};
static struct snd_soc_dai_driver uda1334_dai = {
.name = "uda1334-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = UDA1334_RATES,
.formats = UDA1334_FORMATS,
},
.ops = &uda1334_dai_ops,
};
static int uda1334_probe(struct snd_soc_component *component)
{
struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
uda1334->rate_constraint.list = &uda1334->rate_constraint_list[0];
uda1334->rate_constraint.count =
ARRAY_SIZE(uda1334->rate_constraint_list);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_uda1334 = {
.probe = uda1334_probe,
.controls = uda1334_snd_controls,
.num_controls = ARRAY_SIZE(uda1334_snd_controls),
.dapm_widgets = uda1334_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(uda1334_dapm_widgets),
.dapm_routes = uda1334_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(uda1334_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct of_device_id uda1334_of_match[] = {
{ .compatible = "nxp,uda1334" },
{ /* sentinel*/ }
};
MODULE_DEVICE_TABLE(of, uda1334_of_match);
static int uda1334_codec_probe(struct platform_device *pdev)
{
struct uda1334_priv *uda1334;
int ret;
uda1334 = devm_kzalloc(&pdev->dev, sizeof(struct uda1334_priv),
GFP_KERNEL);
if (!uda1334)
return -ENOMEM;
platform_set_drvdata(pdev, uda1334);
uda1334->mute = devm_gpiod_get(&pdev->dev, "nxp,mute", GPIOD_OUT_LOW);
if (IS_ERR(uda1334->mute)) {
ret = PTR_ERR(uda1334->mute);
dev_err(&pdev->dev, "Failed to get mute line: %d\n", ret);
return ret;
}
uda1334->deemph = devm_gpiod_get(&pdev->dev, "nxp,deemph", GPIOD_OUT_LOW);
if (IS_ERR(uda1334->deemph)) {
ret = PTR_ERR(uda1334->deemph);
dev_err(&pdev->dev, "Failed to get deemph line: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_uda1334,
&uda1334_dai, 1);
if (ret < 0)
dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
return ret;
}
static struct platform_driver uda1334_codec_driver = {
.probe = uda1334_codec_probe,
.driver = {
.name = "uda1334-codec",
.of_match_table = uda1334_of_match,
},
};
module_platform_driver(uda1334_codec_driver);
MODULE_DESCRIPTION("ASoC UDA1334 driver");
MODULE_AUTHOR("Andra Danciu <[email protected]>");
MODULE_ALIAS("platform:uda1334-codec");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/uda1334.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8978.c -- WM8978 ALSA SoC Audio Codec driver
*
* Copyright (C) 2009-2010 Guennadi Liakhovetski <[email protected]>
* Copyright (C) 2007 Carlos Munoz <[email protected]>
* Copyright 2006-2009 Wolfson Microelectronics PLC.
* Based on wm8974 and wm8990 by Liam Girdwood <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "wm8978.h"
static const struct reg_default wm8978_reg_defaults[] = {
{ 1, 0x0000 },
{ 2, 0x0000 },
{ 3, 0x0000 },
{ 4, 0x0050 },
{ 5, 0x0000 },
{ 6, 0x0140 },
{ 7, 0x0000 },
{ 8, 0x0000 },
{ 9, 0x0000 },
{ 10, 0x0000 },
{ 11, 0x00ff },
{ 12, 0x00ff },
{ 13, 0x0000 },
{ 14, 0x0100 },
{ 15, 0x00ff },
{ 16, 0x00ff },
{ 17, 0x0000 },
{ 18, 0x012c },
{ 19, 0x002c },
{ 20, 0x002c },
{ 21, 0x002c },
{ 22, 0x002c },
{ 23, 0x0000 },
{ 24, 0x0032 },
{ 25, 0x0000 },
{ 26, 0x0000 },
{ 27, 0x0000 },
{ 28, 0x0000 },
{ 29, 0x0000 },
{ 30, 0x0000 },
{ 31, 0x0000 },
{ 32, 0x0038 },
{ 33, 0x000b },
{ 34, 0x0032 },
{ 35, 0x0000 },
{ 36, 0x0008 },
{ 37, 0x000c },
{ 38, 0x0093 },
{ 39, 0x00e9 },
{ 40, 0x0000 },
{ 41, 0x0000 },
{ 42, 0x0000 },
{ 43, 0x0000 },
{ 44, 0x0033 },
{ 45, 0x0010 },
{ 46, 0x0010 },
{ 47, 0x0100 },
{ 48, 0x0100 },
{ 49, 0x0002 },
{ 50, 0x0001 },
{ 51, 0x0001 },
{ 52, 0x0039 },
{ 53, 0x0039 },
{ 54, 0x0039 },
{ 55, 0x0039 },
{ 56, 0x0001 },
{ 57, 0x0001 },
};
static bool wm8978_volatile(struct device *dev, unsigned int reg)
{
return reg == WM8978_RESET;
}
/* codec private data */
struct wm8978_priv {
struct regmap *regmap;
unsigned int f_pllout;
unsigned int f_mclk;
unsigned int f_256fs;
unsigned int f_opclk;
int mclk_idx;
enum wm8978_sysclk_src sysclk;
};
static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
static const char *wm8978_eqmode[] = {"Capture", "Playback"};
static const char *wm8978_bw[] = {"Narrow", "Wide"};
static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
static const char *wm8978_alc3[] = {"ALC", "Limiter"};
static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
static SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
wm8978_companding);
static SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
wm8978_companding);
static SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
static SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
static SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
static SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
static SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
static SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
static SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
static SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
static SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
static SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
static SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
static const struct snd_kcontrol_new wm8978_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch",
WM8978_COMPANDING_CONTROL, 0, 1, 0),
SOC_ENUM("ADC Companding", adc_compand),
SOC_ENUM("DAC Companding", dac_compand),
SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
SOC_DOUBLE_R_TLV("PCM Volume",
WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
0, 255, 0, digital_tlv),
SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
SOC_DOUBLE_R_TLV("ADC Volume",
WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
0, 255, 0, digital_tlv),
SOC_ENUM("Equaliser Function", eqmode),
SOC_ENUM("EQ1 Cut Off", eq1),
SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ2 Bandwidth", eq2bw),
SOC_ENUM("EQ2 Cut Off", eq2),
SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ3 Bandwidth", eq3bw),
SOC_ENUM("EQ3 Cut Off", eq3),
SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ4 Bandwidth", eq4bw),
SOC_ENUM("EQ4 Cut Off", eq4),
SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ5 Cut Off", eq5),
SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
SOC_SINGLE("DAC Playback Limiter Switch",
WM8978_DAC_LIMITER_1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay",
WM8978_DAC_LIMITER_1, 4, 15, 0),
SOC_SINGLE("DAC Playback Limiter Attack",
WM8978_DAC_LIMITER_1, 0, 15, 0),
SOC_SINGLE("DAC Playback Limiter Threshold",
WM8978_DAC_LIMITER_2, 4, 7, 0),
SOC_SINGLE_TLV("DAC Playback Limiter Volume",
WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
SOC_ENUM("ALC Enable Switch", alc1),
SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
SOC_ENUM("ALC Capture Mode", alc3),
SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold",
WM8978_NOISE_GATE, 0, 7, 0),
SOC_DOUBLE_R("Capture PGA ZC Switch",
WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
7, 1, 0),
/* OUT1 - Headphones */
SOC_DOUBLE_R("Headphone Playback ZC Switch",
WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
SOC_DOUBLE_R_TLV("Headphone Playback Volume",
WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
0, 63, 0, spk_tlv),
/* OUT2 - Speakers */
SOC_DOUBLE_R("Speaker Playback ZC Switch",
WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Playback Volume",
WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
0, 63, 0, spk_tlv),
/* OUT3/4 - Line Output */
SOC_DOUBLE_R("Line Playback Switch",
WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
/* Mixer #3: Boost (Input) mixer */
SOC_DOUBLE_R("PGA Boost (+20dB)",
WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
8, 1, 0),
SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
4, 7, 0, boost_tlv),
SOC_DOUBLE_R_TLV("Aux Boost Volume",
WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
0, 7, 0, boost_tlv),
/* Input PGA volume */
SOC_DOUBLE_R_TLV("Input PGA Volume",
WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
0, 63, 0, inpga_tlv),
/* Headphone */
SOC_DOUBLE_R("Headphone Switch",
WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
/* Speaker */
SOC_DOUBLE_R("Speaker Switch",
WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
/* DAC / ADC oversampling */
SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
5, 1, 0),
SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
5, 1, 0),
};
/* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
};
/* OUT3/OUT4 Mixer not implemented */
/* Mixer #2: Input PGA Mute */
static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
};
static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
WM8978_POWER_MANAGEMENT_3, 0, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
WM8978_POWER_MANAGEMENT_3, 1, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
WM8978_POWER_MANAGEMENT_2, 0, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
WM8978_POWER_MANAGEMENT_2, 1, 0),
/* Mixer #1: OUT1,2 */
SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
2, 0, wm8978_left_out_mixer),
SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
3, 0, wm8978_right_out_mixer),
SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
2, 0, wm8978_left_input_mixer),
SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
3, 0, wm8978_right_input_mixer),
SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
8, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
5, 0, NULL, 0),
SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
8, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
SND_SOC_DAPM_INPUT("LMICN"),
SND_SOC_DAPM_INPUT("LMICP"),
SND_SOC_DAPM_INPUT("RMICN"),
SND_SOC_DAPM_INPUT("RMICP"),
SND_SOC_DAPM_INPUT("LAUX"),
SND_SOC_DAPM_INPUT("RAUX"),
SND_SOC_DAPM_INPUT("L2"),
SND_SOC_DAPM_INPUT("R2"),
SND_SOC_DAPM_OUTPUT("LHP"),
SND_SOC_DAPM_OUTPUT("RHP"),
SND_SOC_DAPM_OUTPUT("LSPK"),
SND_SOC_DAPM_OUTPUT("RSPK"),
};
static const struct snd_soc_dapm_route wm8978_dapm_routes[] = {
/* Output mixer */
{"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
{"Right Output Mixer", "Aux Playback Switch", "RAUX"},
{"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
{"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
{"Left Output Mixer", "Aux Playback Switch", "LAUX"},
{"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
/* Outputs */
{"Right Headphone Out", NULL, "Right Output Mixer"},
{"RHP", NULL, "Right Headphone Out"},
{"Left Headphone Out", NULL, "Left Output Mixer"},
{"LHP", NULL, "Left Headphone Out"},
{"Right Speaker Out", NULL, "Right Output Mixer"},
{"RSPK", NULL, "Right Speaker Out"},
{"Left Speaker Out", NULL, "Left Output Mixer"},
{"LSPK", NULL, "Left Speaker Out"},
/* Boost Mixer */
{"Right ADC", NULL, "Right Boost Mixer"},
{"Right Boost Mixer", NULL, "RAUX"},
{"Right Boost Mixer", NULL, "Right Capture PGA"},
{"Right Boost Mixer", NULL, "R2"},
{"Left ADC", NULL, "Left Boost Mixer"},
{"Left Boost Mixer", NULL, "LAUX"},
{"Left Boost Mixer", NULL, "Left Capture PGA"},
{"Left Boost Mixer", NULL, "L2"},
/* Input PGA */
{"Right Capture PGA", NULL, "Right Input Mixer"},
{"Left Capture PGA", NULL, "Left Input Mixer"},
{"Right Input Mixer", "R2 Switch", "R2"},
{"Right Input Mixer", "MicN Switch", "RMICN"},
{"Right Input Mixer", "MicP Switch", "RMICP"},
{"Left Input Mixer", "L2 Switch", "L2"},
{"Left Input Mixer", "MicN Switch", "LMICN"},
{"Left Input Mixer", "MicP Switch", "LMICP"},
};
/* PLL divisors */
struct wm8978_pll_div {
u32 k;
u8 n;
u8 div2;
};
#define FIXED_PLL_SIZE (1 << 24)
static void pll_factors(struct snd_soc_component *component,
struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
{
u64 k_part;
unsigned int k, n_div, n_mod;
n_div = target / source;
if (n_div < 6) {
source >>= 1;
pll_div->div2 = 1;
n_div = target / source;
} else {
pll_div->div2 = 0;
}
if (n_div < 6 || n_div > 12)
dev_warn(component->dev,
"WM8978 N value exceeds recommended range! N = %u\n",
n_div);
pll_div->n = n_div;
n_mod = target - source * n_div;
k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
do_div(k_part, source);
k = k_part & 0xFFFFFFFF;
pll_div->k = k;
}
/* MCLK dividers */
static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
/*
* find index >= idx, such that, for a given f_out,
* 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
* f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
* generalised for f_opclk with suitable coefficient arrays, but currently
* the OPCLK divisor is calculated directly, not iteratively.
*/
static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
unsigned int *f_pllout)
{
int i;
for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
mclk_denominator[i];
if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
*f_pllout = f_pllout_x4 / 4;
return i;
}
}
return -EINVAL;
}
/*
* Calculate internal frequencies and dividers, according to Figure 40
* "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
*/
static int wm8978_configure_pll(struct snd_soc_component *component)
{
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
struct wm8978_pll_div pll_div;
unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
f_256fs = wm8978->f_256fs;
unsigned int f2;
if (!f_mclk)
return -EINVAL;
if (f_opclk) {
unsigned int opclk_div;
/* Cannot set up MCLK divider now, do later */
wm8978->mclk_idx = -1;
/*
* The user needs OPCLK. Choose OPCLKDIV to put
* 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
* f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
* prescale = 1, or prescale = 2. Prescale is calculated inside
* pll_factors(). We have to select f_PLLOUT, such that
* f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
* f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
*/
if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
return -EINVAL;
if (4 * f_opclk < 3 * f_mclk)
/* Have to use OPCLKDIV */
opclk_div = DIV_ROUND_UP(3 * f_mclk / 4, f_opclk);
else
opclk_div = 1;
dev_dbg(component->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 0x30,
(opclk_div - 1) << 4);
wm8978->f_pllout = f_opclk * opclk_div;
} else if (f_256fs) {
/*
* Not using OPCLK, but PLL is used for the codec, choose R:
* 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
* f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
* prescale = 1, or prescale = 2. Prescale is calculated inside
* pll_factors(). We have to select f_PLLOUT, such that
* f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
* f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
* must be 3.781MHz <= f_MCLK <= 32.768MHz
*/
int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
if (idx < 0)
return idx;
wm8978->mclk_idx = idx;
} else {
return -EINVAL;
}
f2 = wm8978->f_pllout * 4;
dev_dbg(component->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
wm8978->f_mclk, wm8978->f_pllout);
pll_factors(component, &pll_div, f2, wm8978->f_mclk);
dev_dbg(component->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
__func__, pll_div.n, pll_div.k, pll_div.div2);
/* Turn PLL off for configuration... */
snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
snd_soc_component_write(component, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18);
snd_soc_component_write(component, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8978_PLL_K3, pll_div.k & 0x1ff);
/* ...and on again */
snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
if (f_opclk)
/* Output PLL (OPCLK) to GPIO1 */
snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 7, 4);
return 0;
}
/*
* Configure WM8978 clock dividers.
*/
static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (div_id) {
case WM8978_OPCLKRATE:
wm8978->f_opclk = div;
if (wm8978->f_mclk)
/*
* We know the MCLK frequency, the user has requested
* OPCLK, configure the PLL based on that and start it
* and OPCLK immediately. We will configure PLL to match
* user-requested OPCLK frquency as good as possible.
* In fact, it is likely, that matching the sampling
* rate, when it becomes known, is more important, and
* we will not be reconfiguring PLL then, because we
* must not interrupt OPCLK. But it should be fine,
* because typically the user will request OPCLK to run
* at 256fs or 512fs, and for these cases we will also
* find an exact MCLK divider configuration - it will
* be equal to or double the OPCLK divisor.
*/
ret = wm8978_configure_pll(component);
break;
case WM8978_BCLKDIV:
if (div & ~0x1c)
return -EINVAL;
snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, div);
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
return ret;
}
/*
* @freq: when .set_pll() us not used, freq is codec MCLK input frequency
*/
static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
int ret = 0;
dev_dbg(component->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
if (freq) {
wm8978->f_mclk = freq;
/* Even if MCLK is used for system clock, might have to drive OPCLK */
if (wm8978->f_opclk)
ret = wm8978_configure_pll(component);
/* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
if (!ret)
wm8978->sysclk = clk_id;
}
if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
/* Clock CODEC directly from MCLK */
snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0);
/* GPIO1 into default mode as input - before configuring PLL */
snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 7, 0);
/* Turn off PLL */
snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
wm8978->sysclk = WM8978_MCLK;
wm8978->f_pllout = 0;
wm8978->f_opclk = 0;
}
return ret;
}
/*
* Set ADC and Voice DAC format.
*/
static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
/*
* BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
* Data Format mask = 0x18: all will be calculated anew
*/
u16 iface = snd_soc_component_read(component, WM8978_AUDIO_INTERFACE) & ~0x198;
u16 clk = snd_soc_component_read(component, WM8978_CLOCKING);
dev_dbg(component->dev, "%s\n", __func__);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
clk &= ~1;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x10;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x8;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x18;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x180;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x100;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x80;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface);
snd_soc_component_write(component, WM8978_CLOCKING, clk);
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
*/
static int wm8978_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
/* Word length mask = 0x60 */
u16 iface_ctl = snd_soc_component_read(component, WM8978_AUDIO_INTERFACE) & ~0x60;
/* Sampling rate mask = 0xe (for filters) */
u16 add_ctl = snd_soc_component_read(component, WM8978_ADDITIONAL_CONTROL) & ~0xe;
u16 clking = snd_soc_component_read(component, WM8978_CLOCKING);
enum wm8978_sysclk_src current_clk_id = (clking & 0x100) ?
WM8978_PLL : WM8978_MCLK;
unsigned int f_sel, diff, diff_best = INT_MAX;
int i, best = 0;
if (!wm8978->f_mclk)
return -EINVAL;
/* bit size */
switch (params_width(params)) {
case 16:
break;
case 20:
iface_ctl |= 0x20;
break;
case 24:
iface_ctl |= 0x40;
break;
case 32:
iface_ctl |= 0x60;
break;
}
/* filter coefficient */
switch (params_rate(params)) {
case 8000:
add_ctl |= 0x5 << 1;
break;
case 11025:
add_ctl |= 0x4 << 1;
break;
case 16000:
add_ctl |= 0x3 << 1;
break;
case 22050:
add_ctl |= 0x2 << 1;
break;
case 32000:
add_ctl |= 0x1 << 1;
break;
case 44100:
case 48000:
break;
}
/* Sampling rate is known now, can configure the MCLK divider */
wm8978->f_256fs = params_rate(params) * 256;
if (wm8978->sysclk == WM8978_MCLK) {
wm8978->mclk_idx = -1;
f_sel = wm8978->f_mclk;
} else {
if (!wm8978->f_opclk) {
/* We only enter here, if OPCLK is not used */
int ret = wm8978_configure_pll(component);
if (ret < 0)
return ret;
}
f_sel = wm8978->f_pllout;
}
if (wm8978->mclk_idx < 0) {
/* Either MCLK is used directly, or OPCLK is used */
if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
diff = abs(wm8978->f_256fs * 3 -
f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
if (diff < diff_best) {
diff_best = diff;
best = i;
}
if (!diff)
break;
}
} else {
/* OPCLK not used, codec driven by PLL */
best = wm8978->mclk_idx;
diff = 0;
}
if (diff)
dev_warn(component->dev, "Imprecise sampling rate: %uHz%s\n",
f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
wm8978->sysclk == WM8978_MCLK ?
", consider using PLL" : "");
dev_dbg(component->dev, "%s: width %d, rate %u, MCLK divisor #%d\n", __func__,
params_width(params), params_rate(params), best);
/* MCLK divisor mask = 0xe0 */
snd_soc_component_update_bits(component, WM8978_CLOCKING, 0xe0, best << 5);
snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface_ctl);
snd_soc_component_write(component, WM8978_ADDITIONAL_CONTROL, add_ctl);
if (wm8978->sysclk != current_clk_id) {
if (wm8978->sysclk == WM8978_PLL)
/* Run CODEC from PLL instead of MCLK */
snd_soc_component_update_bits(component, WM8978_CLOCKING,
0x100, 0x100);
else
/* Clock CODEC directly from MCLK */
snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0);
}
return 0;
}
static int wm8978_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
dev_dbg(component->dev, "%s: %d\n", __func__, mute);
if (mute)
snd_soc_component_update_bits(component, WM8978_DAC_CONTROL, 0x40, 0x40);
else
snd_soc_component_update_bits(component, WM8978_DAC_CONTROL, 0x40, 0);
return 0;
}
static int wm8978_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
u16 power1 = snd_soc_component_read(component, WM8978_POWER_MANAGEMENT_1) & ~3;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
power1 |= 1; /* VMID 75k */
snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, power1);
break;
case SND_SOC_BIAS_STANDBY:
/* bit 3: enable bias, bit 2: enable I/O tie off buffer */
power1 |= 0xc;
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
/* Initial cap charge at VMID 5k */
snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1,
power1 | 0x3);
mdelay(100);
}
power1 |= 0x2; /* VMID 500k */
snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, power1);
break;
case SND_SOC_BIAS_OFF:
/* Preserve PLL - OPCLK may be used by someone */
snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_2, 0);
snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_3, 0);
break;
}
dev_dbg(component->dev, "%s: %d, %x\n", __func__, level, power1);
return 0;
}
#define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8978_dai_ops = {
.hw_params = wm8978_hw_params,
.mute_stream = wm8978_mute,
.set_fmt = wm8978_set_dai_fmt,
.set_clkdiv = wm8978_set_dai_clkdiv,
.set_sysclk = wm8978_set_dai_sysclk,
.no_capture_mute = 1,
};
/* Also supports 12kHz */
static struct snd_soc_dai_driver wm8978_dai = {
.name = "wm8978-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8978_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8978_FORMATS,
},
.ops = &wm8978_dai_ops,
.symmetric_rate = 1,
};
static int wm8978_suspend(struct snd_soc_component *component)
{
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
/* Also switch PLL off */
snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, 0);
regcache_mark_dirty(wm8978->regmap);
return 0;
}
static int wm8978_resume(struct snd_soc_component *component)
{
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
/* Sync reg_cache with the hardware */
regcache_sync(wm8978->regmap);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
if (wm8978->f_pllout)
/* Switch PLL on */
snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
return 0;
}
/*
* These registers contain an "update" bit - bit 8. This means, for example,
* that one can write new DAC digital volume for both channels, but only when
* the update bit is set, will also the volume be updated - simultaneously for
* both channels.
*/
static const int update_reg[] = {
WM8978_LEFT_DAC_DIGITAL_VOLUME,
WM8978_RIGHT_DAC_DIGITAL_VOLUME,
WM8978_LEFT_ADC_DIGITAL_VOLUME,
WM8978_RIGHT_ADC_DIGITAL_VOLUME,
WM8978_LEFT_INP_PGA_CONTROL,
WM8978_RIGHT_INP_PGA_CONTROL,
WM8978_LOUT1_HP_CONTROL,
WM8978_ROUT1_HP_CONTROL,
WM8978_LOUT2_SPK_CONTROL,
WM8978_ROUT2_SPK_CONTROL,
};
static int wm8978_probe(struct snd_soc_component *component)
{
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
int i;
/*
* Set default system clock to PLL, it is more precise, this is also the
* default hardware setting
*/
wm8978->sysclk = WM8978_PLL;
/*
* Set the update bit in all registers, that have one. This way all
* writes to those registers will also cause the update bit to be
* written.
*/
for (i = 0; i < ARRAY_SIZE(update_reg); i++)
snd_soc_component_update_bits(component, update_reg[i], 0x100, 0x100);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_wm8978 = {
.probe = wm8978_probe,
.suspend = wm8978_suspend,
.resume = wm8978_resume,
.set_bias_level = wm8978_set_bias_level,
.controls = wm8978_snd_controls,
.num_controls = ARRAY_SIZE(wm8978_snd_controls),
.dapm_widgets = wm8978_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8978_dapm_widgets),
.dapm_routes = wm8978_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8978_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8978_regmap_config = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8978_MAX_REGISTER,
.volatile_reg = wm8978_volatile,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8978_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8978_reg_defaults),
};
static int wm8978_i2c_probe(struct i2c_client *i2c)
{
struct wm8978_priv *wm8978;
int ret;
wm8978 = devm_kzalloc(&i2c->dev, sizeof(struct wm8978_priv),
GFP_KERNEL);
if (wm8978 == NULL)
return -ENOMEM;
wm8978->regmap = devm_regmap_init_i2c(i2c, &wm8978_regmap_config);
if (IS_ERR(wm8978->regmap)) {
ret = PTR_ERR(wm8978->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, wm8978);
/* Reset the codec */
ret = regmap_write(wm8978->regmap, WM8978_RESET, 0);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8978, &wm8978_dai, 1);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id wm8978_i2c_id[] = {
{ "wm8978", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
static const struct of_device_id wm8978_of_match[] = {
{ .compatible = "wlf,wm8978", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8978_of_match);
static struct i2c_driver wm8978_i2c_driver = {
.driver = {
.name = "wm8978",
.of_match_table = wm8978_of_match,
},
.probe = wm8978_i2c_probe,
.id_table = wm8978_i2c_id,
};
module_i2c_driver(wm8978_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8978 codec driver");
MODULE_AUTHOR("Guennadi Liakhovetski <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8978.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l51.c
*
* ASoC Driver for Cirrus Logic CS42L51 codecs
*
* Copyright (c) 2010 Arnaud Patard <[email protected]>
*
* Based on cs4270.c - Copyright (c) Freescale Semiconductor
*
* For now:
* - Only I2C is support. Not SPI
* - master mode *NOT* supported
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/pcm.h>
#include <linux/gpio/consumer.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include "cs42l51.h"
enum master_slave_mode {
MODE_SLAVE,
MODE_SLAVE_AUTO,
MODE_MASTER,
};
static const char * const cs42l51_supply_names[] = {
"VL",
"VD",
"VA",
"VAHP",
};
struct cs42l51_private {
unsigned int mclk;
struct clk *mclk_handle;
unsigned int audio_mode; /* The mode (I2S or left-justified) */
enum master_slave_mode func;
struct regulator_bulk_data supplies[ARRAY_SIZE(cs42l51_supply_names)];
struct gpio_desc *reset_gpio;
struct regmap *regmap;
};
#define CS42L51_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned long value = snd_soc_component_read(component, CS42L51_PCM_MIXER)&3;
switch (value) {
default:
case 0:
ucontrol->value.enumerated.item[0] = 0;
break;
/* same value : (L+R)/2 and (R+L)/2 */
case 1:
case 2:
ucontrol->value.enumerated.item[0] = 1;
break;
case 3:
ucontrol->value.enumerated.item[0] = 2;
break;
}
return 0;
}
#define CHAN_MIX_NORMAL 0x00
#define CHAN_MIX_BOTH 0x55
#define CHAN_MIX_SWAP 0xFF
static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned char val;
switch (ucontrol->value.enumerated.item[0]) {
default:
case 0:
val = CHAN_MIX_NORMAL;
break;
case 1:
val = CHAN_MIX_BOTH;
break;
case 2:
val = CHAN_MIX_SWAP;
break;
}
snd_soc_component_write(component, CS42L51_PCM_MIXER, val);
return 1;
}
static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0);
static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0);
static const DECLARE_TLV_DB_SCALE(adc_boost_tlv, 2000, 2000, 0);
static const char *chan_mix[] = {
"L R",
"L+R",
"R L",
};
static const DECLARE_TLV_DB_SCALE(pga_tlv, -300, 50, 0);
static const DECLARE_TLV_DB_SCALE(adc_att_tlv, -9600, 100, 0);
static SOC_ENUM_SINGLE_EXT_DECL(cs42l51_chan_mix, chan_mix);
static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
0, 0x19, 0x7F, adc_pcm_tlv),
SOC_DOUBLE_R("PCM Playback Switch",
CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
0, 0x34, 0xE4, aout_tlv),
SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
0, 0x19, 0x7F, adc_pcm_tlv),
SOC_DOUBLE_R("ADC Mixer Switch",
CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
SOC_DOUBLE_R_SX_TLV("ADC Attenuator Volume",
CS42L51_ADCA_ATT, CS42L51_ADCB_ATT,
0, 0xA0, 96, adc_att_tlv),
SOC_DOUBLE_R_SX_TLV("PGA Volume",
CS42L51_ALC_PGA_CTL, CS42L51_ALC_PGB_CTL,
0, 0x1A, 30, pga_tlv),
SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0),
SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),
SOC_SINGLE("Zero Cross Switch", CS42L51_DAC_CTL, 0, 0, 0),
SOC_DOUBLE_TLV("Mic Boost Volume",
CS42L51_MIC_CTL, 0, 1, 1, 0, boost_tlv),
SOC_DOUBLE_TLV("ADC Boost Volume",
CS42L51_MIC_CTL, 5, 6, 1, 0, adc_boost_tlv),
SOC_SINGLE_TLV("Bass Volume", CS42L51_TONE_CTL, 0, 0xf, 1, tone_tlv),
SOC_SINGLE_TLV("Treble Volume", CS42L51_TONE_CTL, 4, 0xf, 1, tone_tlv),
SOC_ENUM_EXT("PCM channel mixer",
cs42l51_chan_mix,
cs42l51_get_chan_mix, cs42l51_set_chan_mix),
};
/*
* to power down, one must:
* 1.) Enable the PDN bit
* 2.) enable power-down for the select channels
* 3.) disable the PDN bit.
*/
static int cs42l51_pdn_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
CS42L51_POWER_CTL1_PDN,
CS42L51_POWER_CTL1_PDN);
break;
default:
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, CS42L51_POWER_CTL1,
CS42L51_POWER_CTL1_PDN, 0);
break;
}
return 0;
}
static const char *cs42l51_dac_names[] = {"Direct PCM",
"DSP PCM", "ADC"};
static SOC_ENUM_SINGLE_DECL(cs42l51_dac_mux_enum,
CS42L51_DAC_CTL, 6, cs42l51_dac_names);
static const struct snd_kcontrol_new cs42l51_dac_mux_controls =
SOC_DAPM_ENUM("Route", cs42l51_dac_mux_enum);
static const char *cs42l51_adcl_names[] = {"AIN1 Left", "AIN2 Left",
"MIC Left", "MIC+preamp Left"};
static SOC_ENUM_SINGLE_DECL(cs42l51_adcl_mux_enum,
CS42L51_ADC_INPUT, 4, cs42l51_adcl_names);
static const struct snd_kcontrol_new cs42l51_adcl_mux_controls =
SOC_DAPM_ENUM("Route", cs42l51_adcl_mux_enum);
static const char *cs42l51_adcr_names[] = {"AIN1 Right", "AIN2 Right",
"MIC Right", "MIC+preamp Right"};
static SOC_ENUM_SINGLE_DECL(cs42l51_adcr_mux_enum,
CS42L51_ADC_INPUT, 6, cs42l51_adcr_names);
static const struct snd_kcontrol_new cs42l51_adcr_mux_controls =
SOC_DAPM_ENUM("Route", cs42l51_adcr_mux_enum);
static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L51_MIC_POWER_CTL, 1, 1, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("Left PGA", CS42L51_POWER_CTL1, 3, 1, NULL, 0,
cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_PGA_E("Right PGA", CS42L51_POWER_CTL1, 4, 1, NULL, 0,
cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_ADC_E("Left ADC", "Left HiFi Capture",
CS42L51_POWER_CTL1, 1, 1,
cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_ADC_E("Right ADC", "Right HiFi Capture",
CS42L51_POWER_CTL1, 2, 1,
cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_DAC_E("Left DAC", NULL, CS42L51_POWER_CTL1, 5, 1,
cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_DAC_E("Right DAC", NULL, CS42L51_POWER_CTL1, 6, 1,
cs42l51_pdn_event, SND_SOC_DAPM_PRE_POST_PMD),
/* analog/mic */
SND_SOC_DAPM_INPUT("AIN1L"),
SND_SOC_DAPM_INPUT("AIN1R"),
SND_SOC_DAPM_INPUT("AIN2L"),
SND_SOC_DAPM_INPUT("AIN2R"),
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_INPUT("MICR"),
SND_SOC_DAPM_MIXER("Mic Preamp Left",
CS42L51_MIC_POWER_CTL, 2, 1, NULL, 0),
SND_SOC_DAPM_MIXER("Mic Preamp Right",
CS42L51_MIC_POWER_CTL, 3, 1, NULL, 0),
/* HP */
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
/* mux */
SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
&cs42l51_dac_mux_controls),
SND_SOC_DAPM_MUX("PGA-ADC Mux Left", SND_SOC_NOPM, 0, 0,
&cs42l51_adcl_mux_controls),
SND_SOC_DAPM_MUX("PGA-ADC Mux Right", SND_SOC_NOPM, 0, 0,
&cs42l51_adcr_mux_controls),
};
static int mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(comp);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return clk_prepare_enable(cs42l51->mclk_handle);
case SND_SOC_DAPM_POST_PMD:
/* Delay mclk shutdown to fulfill power-down sequence requirements */
msleep(20);
clk_disable_unprepare(cs42l51->mclk_handle);
break;
}
return 0;
}
static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route cs42l51_routes[] = {
{"HPL", NULL, "Left DAC"},
{"HPR", NULL, "Right DAC"},
{"Right DAC", NULL, "DAC Mux"},
{"Left DAC", NULL, "DAC Mux"},
{"DAC Mux", "Direct PCM", "Playback"},
{"DAC Mux", "DSP PCM", "Playback"},
{"Left ADC", NULL, "Left PGA"},
{"Right ADC", NULL, "Right PGA"},
{"Mic Preamp Left", NULL, "MICL"},
{"Mic Preamp Right", NULL, "MICR"},
{"PGA-ADC Mux Left", "AIN1 Left", "AIN1L" },
{"PGA-ADC Mux Left", "AIN2 Left", "AIN2L" },
{"PGA-ADC Mux Left", "MIC Left", "MICL" },
{"PGA-ADC Mux Left", "MIC+preamp Left", "Mic Preamp Left" },
{"PGA-ADC Mux Right", "AIN1 Right", "AIN1R" },
{"PGA-ADC Mux Right", "AIN2 Right", "AIN2R" },
{"PGA-ADC Mux Right", "MIC Right", "MICR" },
{"PGA-ADC Mux Right", "MIC+preamp Right", "Mic Preamp Right" },
{"Left PGA", NULL, "PGA-ADC Mux Left"},
{"Right PGA", NULL, "PGA-ADC Mux Right"},
};
static int cs42l51_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
cs42l51->audio_mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
dev_err(component->dev, "invalid DAI format\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
cs42l51->func = MODE_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
cs42l51->func = MODE_SLAVE_AUTO;
break;
default:
dev_err(component->dev, "Unknown master/slave configuration\n");
return -EINVAL;
}
return 0;
}
struct cs42l51_ratios {
unsigned int ratio;
unsigned char speed_mode;
unsigned char mclk;
};
static struct cs42l51_ratios slave_ratios[] = {
{ 512, CS42L51_QSM_MODE, 0 }, { 768, CS42L51_QSM_MODE, 0 },
{ 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
{ 2048, CS42L51_QSM_MODE, 0 }, { 3072, CS42L51_QSM_MODE, 0 },
{ 256, CS42L51_HSM_MODE, 0 }, { 384, CS42L51_HSM_MODE, 0 },
{ 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
{ 1024, CS42L51_HSM_MODE, 0 }, { 1536, CS42L51_HSM_MODE, 0 },
{ 128, CS42L51_SSM_MODE, 0 }, { 192, CS42L51_SSM_MODE, 0 },
{ 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
{ 512, CS42L51_SSM_MODE, 0 }, { 768, CS42L51_SSM_MODE, 0 },
{ 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
{ 256, CS42L51_DSM_MODE, 0 }, { 384, CS42L51_DSM_MODE, 0 },
};
static struct cs42l51_ratios slave_auto_ratios[] = {
{ 1024, CS42L51_QSM_MODE, 0 }, { 1536, CS42L51_QSM_MODE, 0 },
{ 2048, CS42L51_QSM_MODE, 1 }, { 3072, CS42L51_QSM_MODE, 1 },
{ 512, CS42L51_HSM_MODE, 0 }, { 768, CS42L51_HSM_MODE, 0 },
{ 1024, CS42L51_HSM_MODE, 1 }, { 1536, CS42L51_HSM_MODE, 1 },
{ 256, CS42L51_SSM_MODE, 0 }, { 384, CS42L51_SSM_MODE, 0 },
{ 512, CS42L51_SSM_MODE, 1 }, { 768, CS42L51_SSM_MODE, 1 },
{ 128, CS42L51_DSM_MODE, 0 }, { 192, CS42L51_DSM_MODE, 0 },
{ 256, CS42L51_DSM_MODE, 1 }, { 384, CS42L51_DSM_MODE, 1 },
};
/*
* Master mode mclk/fs ratios.
* Recommended configurations are SSM for 4-50khz and DSM for 50-100kHz ranges
* The table below provides support of following ratios:
* 128: SSM (%128) with div2 disabled
* 256: SSM (%128) with div2 enabled
* In both cases, if sampling rate is above 50kHz, SSM is overridden
* with DSM (%128) configuration
*/
static struct cs42l51_ratios master_ratios[] = {
{ 128, CS42L51_SSM_MODE, 0 }, { 256, CS42L51_SSM_MODE, 1 },
};
static int cs42l51_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
cs42l51->mclk = freq;
return 0;
}
static int cs42l51_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(component);
int ret;
unsigned int i;
unsigned int rate;
unsigned int ratio;
struct cs42l51_ratios *ratios = NULL;
int nr_ratios = 0;
int intf_ctl, power_ctl, fmt, mode;
switch (cs42l51->func) {
case MODE_MASTER:
ratios = master_ratios;
nr_ratios = ARRAY_SIZE(master_ratios);
break;
case MODE_SLAVE:
ratios = slave_ratios;
nr_ratios = ARRAY_SIZE(slave_ratios);
break;
case MODE_SLAVE_AUTO:
ratios = slave_auto_ratios;
nr_ratios = ARRAY_SIZE(slave_auto_ratios);
break;
}
/* Figure out which MCLK/LRCK ratio to use */
rate = params_rate(params); /* Sampling rate, in Hz */
ratio = cs42l51->mclk / rate; /* MCLK/LRCK ratio */
for (i = 0; i < nr_ratios; i++) {
if (ratios[i].ratio == ratio)
break;
}
if (i == nr_ratios) {
/* We did not find a matching ratio */
dev_err(component->dev, "could not find matching ratio\n");
return -EINVAL;
}
intf_ctl = snd_soc_component_read(component, CS42L51_INTF_CTL);
power_ctl = snd_soc_component_read(component, CS42L51_MIC_POWER_CTL);
intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
| CS42L51_INTF_CTL_DAC_FORMAT(7));
power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
| CS42L51_MIC_POWER_CTL_MCLK_DIV2);
switch (cs42l51->func) {
case MODE_MASTER:
intf_ctl |= CS42L51_INTF_CTL_MASTER;
mode = ratios[i].speed_mode;
/* Force DSM mode if sampling rate is above 50kHz */
if (rate > 50000)
mode = CS42L51_DSM_MODE;
power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(mode);
/*
* Auto detect mode is not applicable for master mode and has to
* be disabled. Otherwise SPEED[1:0] bits will be ignored.
*/
power_ctl &= ~CS42L51_MIC_POWER_CTL_AUTO;
break;
case MODE_SLAVE:
power_ctl |= CS42L51_MIC_POWER_CTL_SPEED(ratios[i].speed_mode);
break;
case MODE_SLAVE_AUTO:
power_ctl |= CS42L51_MIC_POWER_CTL_AUTO;
break;
}
switch (cs42l51->audio_mode) {
case SND_SOC_DAIFMT_I2S:
intf_ctl |= CS42L51_INTF_CTL_ADC_I2S;
intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_I2S);
break;
case SND_SOC_DAIFMT_LEFT_J:
intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(CS42L51_DAC_DIF_LJ24);
break;
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_width(params)) {
case 16:
fmt = CS42L51_DAC_DIF_RJ16;
break;
case 18:
fmt = CS42L51_DAC_DIF_RJ18;
break;
case 20:
fmt = CS42L51_DAC_DIF_RJ20;
break;
case 24:
fmt = CS42L51_DAC_DIF_RJ24;
break;
default:
dev_err(component->dev, "unknown format\n");
return -EINVAL;
}
intf_ctl |= CS42L51_INTF_CTL_DAC_FORMAT(fmt);
break;
default:
dev_err(component->dev, "unknown format\n");
return -EINVAL;
}
if (ratios[i].mclk)
power_ctl |= CS42L51_MIC_POWER_CTL_MCLK_DIV2;
ret = snd_soc_component_write(component, CS42L51_INTF_CTL, intf_ctl);
if (ret < 0)
return ret;
ret = snd_soc_component_write(component, CS42L51_MIC_POWER_CTL, power_ctl);
if (ret < 0)
return ret;
return 0;
}
static int cs42l51_dai_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
int reg;
int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE;
reg = snd_soc_component_read(component, CS42L51_DAC_OUT_CTL);
if (mute)
reg |= mask;
else
reg &= ~mask;
return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg);
}
static int cs42l51_of_xlate_dai_id(struct snd_soc_component *component,
struct device_node *endpoint)
{
/* return dai id 0, whatever the endpoint index */
return 0;
}
static const struct snd_soc_dai_ops cs42l51_dai_ops = {
.hw_params = cs42l51_hw_params,
.set_sysclk = cs42l51_set_dai_sysclk,
.set_fmt = cs42l51_set_dai_fmt,
.mute_stream = cs42l51_dai_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs42l51_dai = {
.name = "cs42l51-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = CS42L51_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = CS42L51_FORMATS,
},
.ops = &cs42l51_dai_ops,
};
static int cs42l51_component_probe(struct snd_soc_component *component)
{
int ret, reg;
struct snd_soc_dapm_context *dapm;
struct cs42l51_private *cs42l51;
cs42l51 = snd_soc_component_get_drvdata(component);
dapm = snd_soc_component_get_dapm(component);
if (cs42l51->mclk_handle)
snd_soc_dapm_new_controls(dapm, cs42l51_dapm_mclk_widgets, 1);
/*
* DAC configuration
* - Use signal processor
* - auto mute
* - vol changes immediate
* - no de-emphasize
*/
reg = CS42L51_DAC_CTL_DATA_SEL(1)
| CS42L51_DAC_CTL_AMUTE | CS42L51_DAC_CTL_DACSZ(0);
ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_component_driver soc_component_device_cs42l51 = {
.probe = cs42l51_component_probe,
.controls = cs42l51_snd_controls,
.num_controls = ARRAY_SIZE(cs42l51_snd_controls),
.dapm_widgets = cs42l51_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l51_dapm_widgets),
.dapm_routes = cs42l51_routes,
.num_dapm_routes = ARRAY_SIZE(cs42l51_routes),
.of_xlate_dai_id = cs42l51_of_xlate_dai_id,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L51_POWER_CTL1:
case CS42L51_MIC_POWER_CTL:
case CS42L51_INTF_CTL:
case CS42L51_MIC_CTL:
case CS42L51_ADC_CTL:
case CS42L51_ADC_INPUT:
case CS42L51_DAC_OUT_CTL:
case CS42L51_DAC_CTL:
case CS42L51_ALC_PGA_CTL:
case CS42L51_ALC_PGB_CTL:
case CS42L51_ADCA_ATT:
case CS42L51_ADCB_ATT:
case CS42L51_ADCA_VOL:
case CS42L51_ADCB_VOL:
case CS42L51_PCMA_VOL:
case CS42L51_PCMB_VOL:
case CS42L51_BEEP_FREQ:
case CS42L51_BEEP_VOL:
case CS42L51_BEEP_CONF:
case CS42L51_TONE_CTL:
case CS42L51_AOUTA_VOL:
case CS42L51_AOUTB_VOL:
case CS42L51_PCM_MIXER:
case CS42L51_LIMIT_THRES_DIS:
case CS42L51_LIMIT_REL:
case CS42L51_LIMIT_ATT:
case CS42L51_ALC_EN:
case CS42L51_ALC_REL:
case CS42L51_ALC_THRES:
case CS42L51_NOISE_CONF:
case CS42L51_CHARGE_FREQ:
return true;
default:
return false;
}
}
static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L51_STATUS:
return true;
default:
return false;
}
}
static bool cs42l51_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L51_CHIP_REV_ID:
case CS42L51_POWER_CTL1:
case CS42L51_MIC_POWER_CTL:
case CS42L51_INTF_CTL:
case CS42L51_MIC_CTL:
case CS42L51_ADC_CTL:
case CS42L51_ADC_INPUT:
case CS42L51_DAC_OUT_CTL:
case CS42L51_DAC_CTL:
case CS42L51_ALC_PGA_CTL:
case CS42L51_ALC_PGB_CTL:
case CS42L51_ADCA_ATT:
case CS42L51_ADCB_ATT:
case CS42L51_ADCA_VOL:
case CS42L51_ADCB_VOL:
case CS42L51_PCMA_VOL:
case CS42L51_PCMB_VOL:
case CS42L51_BEEP_FREQ:
case CS42L51_BEEP_VOL:
case CS42L51_BEEP_CONF:
case CS42L51_TONE_CTL:
case CS42L51_AOUTA_VOL:
case CS42L51_AOUTB_VOL:
case CS42L51_PCM_MIXER:
case CS42L51_LIMIT_THRES_DIS:
case CS42L51_LIMIT_REL:
case CS42L51_LIMIT_ATT:
case CS42L51_ALC_EN:
case CS42L51_ALC_REL:
case CS42L51_ALC_THRES:
case CS42L51_NOISE_CONF:
case CS42L51_STATUS:
case CS42L51_CHARGE_FREQ:
return true;
default:
return false;
}
}
const struct regmap_config cs42l51_regmap = {
.reg_bits = 8,
.reg_stride = 1,
.val_bits = 8,
.use_single_write = true,
.readable_reg = cs42l51_readable_reg,
.volatile_reg = cs42l51_volatile_reg,
.writeable_reg = cs42l51_writeable_reg,
.max_register = CS42L51_CHARGE_FREQ,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs42l51_regmap);
int cs42l51_probe(struct device *dev, struct regmap *regmap)
{
struct cs42l51_private *cs42l51;
unsigned int val;
int ret, i;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
GFP_KERNEL);
if (!cs42l51)
return -ENOMEM;
dev_set_drvdata(dev, cs42l51);
cs42l51->regmap = regmap;
cs42l51->mclk_handle = devm_clk_get_optional(dev, "MCLK");
if (IS_ERR(cs42l51->mclk_handle))
return PTR_ERR(cs42l51->mclk_handle);
for (i = 0; i < ARRAY_SIZE(cs42l51->supplies); i++)
cs42l51->supplies[i].supply = cs42l51_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs42l51->supplies),
cs42l51->supplies);
if (ret != 0) {
dev_err(dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(cs42l51->supplies),
cs42l51->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
cs42l51->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs42l51->reset_gpio))
return PTR_ERR(cs42l51->reset_gpio);
if (cs42l51->reset_gpio) {
dev_dbg(dev, "Release reset gpio\n");
gpiod_set_value_cansleep(cs42l51->reset_gpio, 0);
mdelay(2);
}
/* Verify that we have a CS42L51 */
ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
if (ret < 0) {
dev_err(dev, "failed to read I2C\n");
goto error;
}
if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
(val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
dev_err(dev, "Invalid chip id: %x\n", val);
ret = -ENODEV;
goto error;
}
dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
val & CS42L51_CHIP_REV_MASK);
ret = devm_snd_soc_register_component(dev,
&soc_component_device_cs42l51, &cs42l51_dai, 1);
if (ret < 0)
goto error;
return 0;
error:
regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
cs42l51->supplies);
return ret;
}
EXPORT_SYMBOL_GPL(cs42l51_probe);
void cs42l51_remove(struct device *dev)
{
struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
int ret;
gpiod_set_value_cansleep(cs42l51->reset_gpio, 1);
ret = regulator_bulk_disable(ARRAY_SIZE(cs42l51->supplies),
cs42l51->supplies);
if (ret)
dev_warn(dev, "Failed to disable all regulators (%pe)\n",
ERR_PTR(ret));
}
EXPORT_SYMBOL_GPL(cs42l51_remove);
int __maybe_unused cs42l51_suspend(struct device *dev)
{
struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
regcache_cache_only(cs42l51->regmap, true);
regcache_mark_dirty(cs42l51->regmap);
return 0;
}
EXPORT_SYMBOL_GPL(cs42l51_suspend);
int __maybe_unused cs42l51_resume(struct device *dev)
{
struct cs42l51_private *cs42l51 = dev_get_drvdata(dev);
regcache_cache_only(cs42l51->regmap, false);
return regcache_sync(cs42l51->regmap);
}
EXPORT_SYMBOL_GPL(cs42l51_resume);
MODULE_AUTHOR("Arnaud Patard <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs42l51.c |
// SPDX-License-Identifier: GPL-2.0
//
// nau8822.c -- NAU8822 ALSA Soc Audio driver
//
// Copyright 2017 Nuvoton Technology Crop.
//
// Author: David Lin <[email protected]>
// Co-author: John Hsu <[email protected]>
// Co-author: Seven Li <[email protected]>
//
// Based on WM8974.c
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <asm/div64.h>
#include "nau8822.h"
#define NAU_PLL_FREQ_MAX 100000000
#define NAU_PLL_FREQ_MIN 90000000
#define NAU_PLL_REF_MAX 33000000
#define NAU_PLL_REF_MIN 8000000
#define NAU_PLL_OPTOP_MIN 6
static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
static const struct reg_default nau8822_reg_defaults[] = {
{ NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 },
{ NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 },
{ NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 },
{ NAU8822_REG_AUDIO_INTERFACE, 0x0050 },
{ NAU8822_REG_COMPANDING_CONTROL, 0x0000 },
{ NAU8822_REG_CLOCKING, 0x0140 },
{ NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 },
{ NAU8822_REG_GPIO_CONTROL, 0x0000 },
{ NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 },
{ NAU8822_REG_DAC_CONTROL, 0x0000 },
{ NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff },
{ NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff },
{ NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 },
{ NAU8822_REG_ADC_CONTROL, 0x0100 },
{ NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff },
{ NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff },
{ NAU8822_REG_EQ1, 0x012c },
{ NAU8822_REG_EQ2, 0x002c },
{ NAU8822_REG_EQ3, 0x002c },
{ NAU8822_REG_EQ4, 0x002c },
{ NAU8822_REG_EQ5, 0x002c },
{ NAU8822_REG_DAC_LIMITER_1, 0x0032 },
{ NAU8822_REG_DAC_LIMITER_2, 0x0000 },
{ NAU8822_REG_NOTCH_FILTER_1, 0x0000 },
{ NAU8822_REG_NOTCH_FILTER_2, 0x0000 },
{ NAU8822_REG_NOTCH_FILTER_3, 0x0000 },
{ NAU8822_REG_NOTCH_FILTER_4, 0x0000 },
{ NAU8822_REG_ALC_CONTROL_1, 0x0038 },
{ NAU8822_REG_ALC_CONTROL_2, 0x000b },
{ NAU8822_REG_ALC_CONTROL_3, 0x0032 },
{ NAU8822_REG_NOISE_GATE, 0x0010 },
{ NAU8822_REG_PLL_N, 0x0008 },
{ NAU8822_REG_PLL_K1, 0x000c },
{ NAU8822_REG_PLL_K2, 0x0093 },
{ NAU8822_REG_PLL_K3, 0x00e9 },
{ NAU8822_REG_3D_CONTROL, 0x0000 },
{ NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 },
{ NAU8822_REG_INPUT_CONTROL, 0x0033 },
{ NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 },
{ NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 },
{ NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 },
{ NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 },
{ NAU8822_REG_OUTPUT_CONTROL, 0x0002 },
{ NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 },
{ NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 },
{ NAU8822_REG_LHP_VOLUME, 0x0039 },
{ NAU8822_REG_RHP_VOLUME, 0x0039 },
{ NAU8822_REG_LSPKOUT_VOLUME, 0x0039 },
{ NAU8822_REG_RSPKOUT_VOLUME, 0x0039 },
{ NAU8822_REG_AUX2_MIXER, 0x0001 },
{ NAU8822_REG_AUX1_MIXER, 0x0001 },
{ NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 },
{ NAU8822_REG_LEFT_TIME_SLOT, 0x0000 },
{ NAU8822_REG_MISC, 0x0020 },
{ NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 },
{ NAU8822_REG_DEVICE_REVISION, 0x007f },
{ NAU8822_REG_DEVICE_ID, 0x001a },
{ NAU8822_REG_DAC_DITHER, 0x0114 },
{ NAU8822_REG_ALC_ENHANCE_1, 0x0000 },
{ NAU8822_REG_ALC_ENHANCE_2, 0x0000 },
{ NAU8822_REG_192KHZ_SAMPLING, 0x0008 },
{ NAU8822_REG_MISC_CONTROL, 0x0000 },
{ NAU8822_REG_INPUT_TIEOFF, 0x0000 },
{ NAU8822_REG_POWER_REDUCTION, 0x0000 },
{ NAU8822_REG_AGC_PEAK2PEAK, 0x0000 },
{ NAU8822_REG_AGC_PEAK_DETECT, 0x0000 },
{ NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 },
{ NAU8822_REG_OUTPUT_TIEOFF, 0x0000 },
};
static bool nau8822_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
case NAU8822_REG_3D_CONTROL:
case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
case NAU8822_REG_DAC_DITHER:
case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
return true;
default:
return false;
}
}
static bool nau8822_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
case NAU8822_REG_3D_CONTROL:
case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
case NAU8822_REG_DAC_DITHER:
case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
return true;
default:
return false;
}
}
static bool nau8822_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case NAU8822_REG_RESET:
case NAU8822_REG_DEVICE_REVISION:
case NAU8822_REG_DEVICE_ID:
case NAU8822_REG_AGC_PEAK2PEAK:
case NAU8822_REG_AGC_PEAK_DETECT:
case NAU8822_REG_AUTOMUTE_CONTROL:
return true;
default:
return false;
}
}
/* The EQ parameters get function is to get the 5 band equalizer control.
* The regmap raw read can't work here because regmap doesn't provide
* value format for value width of 9 bits. Therefore, the driver reads data
* from cache and makes value format according to the endianness of
* bytes type control element.
*/
static int nau8822_eq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
int i, reg;
u16 reg_val, *val;
val = (u16 *)ucontrol->value.bytes.data;
reg = NAU8822_REG_EQ1;
for (i = 0; i < params->max / sizeof(u16); i++) {
reg_val = snd_soc_component_read(component, reg + i);
/* conversion of 16-bit integers between native CPU format
* and big endian format
*/
reg_val = cpu_to_be16(reg_val);
memcpy(val + i, ®_val, sizeof(reg_val));
}
return 0;
}
/* The EQ parameters put function is to make configuration of 5 band equalizer
* control. These configuration includes central frequency, equalizer gain,
* cut-off frequency, bandwidth control, and equalizer path.
* The regmap raw write can't work here because regmap doesn't provide
* register and value format for register with address 7 bits and value 9 bits.
* Therefore, the driver makes value format according to the endianness of
* bytes type control element and writes data to codec.
*/
static int nau8822_eq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct soc_bytes_ext *params = (void *)kcontrol->private_value;
void *data;
u16 *val, value;
int i, reg, ret;
data = kmemdup(ucontrol->value.bytes.data,
params->max, GFP_KERNEL | GFP_DMA);
if (!data)
return -ENOMEM;
val = (u16 *)data;
reg = NAU8822_REG_EQ1;
for (i = 0; i < params->max / sizeof(u16); i++) {
/* conversion of 16-bit integers between native CPU format
* and big endian format
*/
value = be16_to_cpu(*(val + i));
ret = snd_soc_component_write(component, reg + i, value);
if (ret) {
dev_err(component->dev,
"EQ configuration fail, register: %x ret: %d\n",
reg + i, ret);
kfree(data);
return ret;
}
}
kfree(data);
return 0;
}
static const char * const nau8822_companding[] = {
"Off", "NC", "u-law", "A-law"};
static const struct soc_enum nau8822_companding_adc_enum =
SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT,
ARRAY_SIZE(nau8822_companding), nau8822_companding);
static const struct soc_enum nau8822_companding_dac_enum =
SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT,
ARRAY_SIZE(nau8822_companding), nau8822_companding);
static const char * const nau8822_eqmode[] = {"Capture", "Playback"};
static const struct soc_enum nau8822_eqmode_enum =
SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT,
ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode);
static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"};
static const char * const nau8822_alc3[] = {"Normal", "Limiter"};
static const struct soc_enum nau8822_alc_enable_enum =
SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT,
ARRAY_SIZE(nau8822_alc1), nau8822_alc1);
static const struct soc_enum nau8822_alc_mode_enum =
SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT,
ARRAY_SIZE(nau8822_alc3), nau8822_alc3);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
static const struct snd_kcontrol_new nau8822_snd_controls[] = {
SOC_ENUM("ADC Companding", nau8822_companding_adc_enum),
SOC_ENUM("DAC Companding", nau8822_companding_dac_enum),
SOC_ENUM("EQ Function", nau8822_eqmode_enum),
SND_SOC_BYTES_EXT("EQ Parameters", 10,
nau8822_eq_get, nau8822_eq_put),
SOC_DOUBLE("DAC Inversion Switch",
NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0),
SOC_DOUBLE_R_TLV("PCM Volume",
NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
SOC_SINGLE("High Pass Filter Switch",
NAU8822_REG_ADC_CONTROL, 8, 1, 0),
SOC_SINGLE("High Pass Cut Off",
NAU8822_REG_ADC_CONTROL, 4, 7, 0),
SOC_DOUBLE("ADC Inversion Switch",
NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0),
SOC_DOUBLE_R_TLV("ADC Volume",
NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
SOC_SINGLE("DAC Limiter Switch",
NAU8822_REG_DAC_LIMITER_1, 8, 1, 0),
SOC_SINGLE("DAC Limiter Decay",
NAU8822_REG_DAC_LIMITER_1, 4, 15, 0),
SOC_SINGLE("DAC Limiter Attack",
NAU8822_REG_DAC_LIMITER_1, 0, 15, 0),
SOC_SINGLE("DAC Limiter Threshold",
NAU8822_REG_DAC_LIMITER_2, 4, 7, 0),
SOC_SINGLE_TLV("DAC Limiter Volume",
NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
SOC_ENUM("ALC Mode", nau8822_alc_mode_enum),
SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum),
SOC_SINGLE("ALC Min Gain",
NAU8822_REG_ALC_CONTROL_1, 0, 7, 0),
SOC_SINGLE("ALC Max Gain",
NAU8822_REG_ALC_CONTROL_1, 3, 7, 0),
SOC_SINGLE("ALC Hold",
NAU8822_REG_ALC_CONTROL_2, 4, 10, 0),
SOC_SINGLE("ALC Target",
NAU8822_REG_ALC_CONTROL_2, 0, 15, 0),
SOC_SINGLE("ALC Decay",
NAU8822_REG_ALC_CONTROL_3, 4, 10, 0),
SOC_SINGLE("ALC Attack",
NAU8822_REG_ALC_CONTROL_3, 0, 10, 0),
SOC_SINGLE("ALC Noise Gate Switch",
NAU8822_REG_NOISE_GATE, 3, 1, 0),
SOC_SINGLE("ALC Noise Gate Threshold",
NAU8822_REG_NOISE_GATE, 0, 7, 0),
SOC_DOUBLE_R("PGA ZC Switch",
NAU8822_REG_LEFT_INP_PGA_CONTROL,
NAU8822_REG_RIGHT_INP_PGA_CONTROL,
7, 1, 0),
SOC_DOUBLE_R_TLV("PGA Volume",
NAU8822_REG_LEFT_INP_PGA_CONTROL,
NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv),
SOC_DOUBLE_R("Headphone ZC Switch",
NAU8822_REG_LHP_VOLUME,
NAU8822_REG_RHP_VOLUME, 7, 1, 0),
SOC_DOUBLE_R("Headphone Playback Switch",
NAU8822_REG_LHP_VOLUME,
NAU8822_REG_RHP_VOLUME, 6, 1, 1),
SOC_DOUBLE_R_TLV("Headphone Volume",
NAU8822_REG_LHP_VOLUME,
NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv),
SOC_DOUBLE_R("Speaker ZC Switch",
NAU8822_REG_LSPKOUT_VOLUME,
NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0),
SOC_DOUBLE_R("Speaker Playback Switch",
NAU8822_REG_LSPKOUT_VOLUME,
NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1),
SOC_DOUBLE_R_TLV("Speaker Volume",
NAU8822_REG_LSPKOUT_VOLUME,
NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv),
SOC_DOUBLE_R("AUXOUT Playback Switch",
NAU8822_REG_AUX2_MIXER,
NAU8822_REG_AUX1_MIXER, 6, 1, 1),
SOC_DOUBLE_R_TLV("PGA Boost Volume",
NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv),
SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv),
SOC_DOUBLE_R_TLV("Aux Boost Volume",
NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv),
SOC_SINGLE("DAC 128x Oversampling Switch",
NAU8822_REG_DAC_CONTROL, 5, 1, 0),
SOC_SINGLE("ADC 128x Oversampling Switch",
NAU8822_REG_ADC_CONTROL, 5, 1, 0),
};
/* LMAIN and RMAIN Mixer */
static const struct snd_kcontrol_new nau8822_left_out_mixer[] = {
SOC_DAPM_SINGLE("LINMIX Switch",
NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("LAUX Switch",
NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0),
SOC_DAPM_SINGLE("LDAC Switch",
NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0),
SOC_DAPM_SINGLE("RDAC Switch",
NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0),
};
static const struct snd_kcontrol_new nau8822_right_out_mixer[] = {
SOC_DAPM_SINGLE("RINMIX Switch",
NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("RAUX Switch",
NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0),
SOC_DAPM_SINGLE("RDAC Switch",
NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0),
SOC_DAPM_SINGLE("LDAC Switch",
NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0),
};
/* AUX1 and AUX2 Mixer */
static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = {
SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0),
SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0),
SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0),
};
static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = {
SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0),
SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0),
SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("AUX1MIX Output Switch",
NAU8822_REG_AUX2_MIXER, 3, 1, 0),
};
/* Input PGA */
static const struct snd_kcontrol_new nau8822_left_input_mixer[] = {
SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0),
};
static const struct snd_kcontrol_new nau8822_right_input_mixer[] = {
SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0),
};
/* Loopback Switch */
static const struct snd_kcontrol_new nau8822_loopback =
SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL,
NAU8822_ADDAP_SFT, 1, 0);
static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(source->dapm);
unsigned int value;
value = snd_soc_component_read(component, NAU8822_REG_CLOCKING);
return (value & NAU8822_CLKM_MASK);
}
static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = {
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
NAU8822_REG_POWER_MANAGEMENT_3, 0, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
NAU8822_REG_POWER_MANAGEMENT_3, 1, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
NAU8822_REG_POWER_MANAGEMENT_2, 0, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
NAU8822_REG_POWER_MANAGEMENT_2, 1, 0),
SOC_MIXER_ARRAY("Left Output Mixer",
NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer),
SOC_MIXER_ARRAY("Right Output Mixer",
NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer),
SOC_MIXER_ARRAY("AUX1 Output Mixer",
NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer),
SOC_MIXER_ARRAY("AUX2 Output Mixer",
NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer),
SOC_MIXER_ARRAY("Left Input Mixer",
NAU8822_REG_POWER_MANAGEMENT_2,
2, 0, nau8822_left_input_mixer),
SOC_MIXER_ARRAY("Right Input Mixer",
NAU8822_REG_POWER_MANAGEMENT_2,
3, 0, nau8822_right_input_mixer),
SND_SOC_DAPM_PGA("Left Boost Mixer",
NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Boost Mixer",
NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Capture PGA",
NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Capture PGA",
NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Headphone Out",
NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone Out",
NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker Out",
NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker Out",
NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX1 Out",
NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX2 Out",
NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias",
NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLL",
NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
&nau8822_loopback),
SND_SOC_DAPM_INPUT("LMICN"),
SND_SOC_DAPM_INPUT("LMICP"),
SND_SOC_DAPM_INPUT("RMICN"),
SND_SOC_DAPM_INPUT("RMICP"),
SND_SOC_DAPM_INPUT("LAUX"),
SND_SOC_DAPM_INPUT("RAUX"),
SND_SOC_DAPM_INPUT("L2"),
SND_SOC_DAPM_INPUT("R2"),
SND_SOC_DAPM_OUTPUT("LHP"),
SND_SOC_DAPM_OUTPUT("RHP"),
SND_SOC_DAPM_OUTPUT("LSPK"),
SND_SOC_DAPM_OUTPUT("RSPK"),
SND_SOC_DAPM_OUTPUT("AUXOUT1"),
SND_SOC_DAPM_OUTPUT("AUXOUT2"),
};
static const struct snd_soc_dapm_route nau8822_dapm_routes[] = {
{"Right DAC", NULL, "PLL", check_mclk_select_pll},
{"Left DAC", NULL, "PLL", check_mclk_select_pll},
/* LMAIN and RMAIN Mixer */
{"Right Output Mixer", "LDAC Switch", "Left DAC"},
{"Right Output Mixer", "RDAC Switch", "Right DAC"},
{"Right Output Mixer", "RAUX Switch", "RAUX"},
{"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
{"Left Output Mixer", "LDAC Switch", "Left DAC"},
{"Left Output Mixer", "RDAC Switch", "Right DAC"},
{"Left Output Mixer", "LAUX Switch", "LAUX"},
{"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
/* AUX1 and AUX2 Mixer */
{"AUX1 Output Mixer", "RDAC Switch", "Right DAC"},
{"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"},
{"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
{"AUX1 Output Mixer", "LDAC Switch", "Left DAC"},
{"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"},
{"AUX2 Output Mixer", "LDAC Switch", "Left DAC"},
{"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"},
{"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
{"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"},
/* Outputs */
{"Right Headphone Out", NULL, "Right Output Mixer"},
{"RHP", NULL, "Right Headphone Out"},
{"Left Headphone Out", NULL, "Left Output Mixer"},
{"LHP", NULL, "Left Headphone Out"},
{"Right Speaker Out", NULL, "Right Output Mixer"},
{"RSPK", NULL, "Right Speaker Out"},
{"Left Speaker Out", NULL, "Left Output Mixer"},
{"LSPK", NULL, "Left Speaker Out"},
{"AUX1 Out", NULL, "AUX1 Output Mixer"},
{"AUX2 Out", NULL, "AUX2 Output Mixer"},
{"AUXOUT1", NULL, "AUX1 Out"},
{"AUXOUT2", NULL, "AUX2 Out"},
/* Boost Mixer */
{"Right ADC", NULL, "PLL", check_mclk_select_pll},
{"Left ADC", NULL, "PLL", check_mclk_select_pll},
{"Right ADC", NULL, "Right Boost Mixer"},
{"Right Boost Mixer", NULL, "RAUX"},
{"Right Boost Mixer", NULL, "Right Capture PGA"},
{"Right Boost Mixer", NULL, "R2"},
{"Left ADC", NULL, "Left Boost Mixer"},
{"Left Boost Mixer", NULL, "LAUX"},
{"Left Boost Mixer", NULL, "Left Capture PGA"},
{"Left Boost Mixer", NULL, "L2"},
/* Input PGA */
{"Right Capture PGA", NULL, "Right Input Mixer"},
{"Left Capture PGA", NULL, "Left Input Mixer"},
/* Enable Microphone Power */
{"Right Capture PGA", NULL, "Mic Bias"},
{"Left Capture PGA", NULL, "Mic Bias"},
{"Right Input Mixer", "R2 Switch", "R2"},
{"Right Input Mixer", "MicN Switch", "RMICN"},
{"Right Input Mixer", "MicP Switch", "RMICP"},
{"Left Input Mixer", "L2 Switch", "L2"},
{"Left Input Mixer", "MicN Switch", "LMICN"},
{"Left Input Mixer", "MicP Switch", "LMICP"},
/* Digital Loopback */
{"Digital Loopback", "Switch", "Left ADC"},
{"Digital Loopback", "Switch", "Right ADC"},
{"Left DAC", NULL, "Digital Loopback"},
{"Right DAC", NULL, "Digital Loopback"},
};
static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
nau8822->div_id = clk_id;
nau8822->sysclk = freq;
dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
return 0;
}
static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs,
struct nau8822_pll *pll_param)
{
u64 f2, f2_max, pll_ratio;
int i, scal_sel;
if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
return -EINVAL;
f2_max = 0;
scal_sel = ARRAY_SIZE(nau8822_mclk_scaler);
for (i = 0; i < scal_sel; i++) {
f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10;
if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
f2_max < f2) {
f2_max = f2;
scal_sel = i;
}
}
if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel)
return -EINVAL;
pll_param->mclk_scaler = scal_sel;
f2 = f2_max;
/* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
* input; round up the 24+4bit.
*/
pll_ratio = div_u64(f2 << 28, pll_in);
pll_param->pre_factor = 0;
if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
pll_ratio <<= 1;
pll_param->pre_factor = 1;
}
pll_param->pll_int = (pll_ratio >> 28) & 0xF;
pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
return 0;
}
static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate)
{
struct snd_soc_component *component = dai->component;
struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
struct nau8822_pll *pll = &nau8822->pll;
int i, sclk, imclk;
switch (nau8822->div_id) {
case NAU8822_CLK_MCLK:
/* Configure the master clock prescaler div to make system
* clock to approximate the internal master clock (IMCLK);
* and large or equal to IMCLK.
*/
div = 0;
imclk = rate * 256;
for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) {
sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
if (sclk < imclk)
break;
div = i;
}
dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",
div, rate);
/* master clock from MCLK and disable PLL */
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
(div << NAU8822_MCLKSEL_SFT));
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
NAU8822_CLKM_MCLK);
break;
case NAU8822_CLK_PLL:
/* master clock from PLL and enable PLL */
if (pll->mclk_scaler != div) {
dev_err(component->dev,
"master clock prescaler not meet PLL parameters\n");
return -EINVAL;
}
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
(div << NAU8822_MCLKSEL_SFT));
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
NAU8822_CLKM_PLL);
break;
default:
return -EINVAL;
}
return 0;
}
static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_component *component = dai->component;
struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
struct nau8822_pll *pll_param = &nau8822->pll;
int ret, fs;
if (freq_in == pll_param->freq_in &&
freq_out == pll_param->freq_out)
return 0;
if (freq_out == 0) {
dev_dbg(component->dev, "PLL disabled\n");
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF);
return 0;
}
fs = freq_out / 256;
ret = nau8822_calc_pll(freq_in, fs, pll_param);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n",
freq_in);
return ret;
}
dev_info(component->dev,
"pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
pll_param->pll_int, pll_param->pll_frac,
pll_param->mclk_scaler, pll_param->pre_factor);
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF);
snd_soc_component_update_bits(component,
NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK,
(pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
pll_param->pll_int);
snd_soc_component_write(component,
NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &
NAU8822_PLLK1_MASK);
snd_soc_component_write(component,
NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &
NAU8822_PLLK2_MASK);
snd_soc_component_write(component,
NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL);
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_ON);
pll_param->freq_in = freq_in;
pll_param->freq_out = freq_out;
return 0;
}
static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
u16 ctrl1_val = 0, ctrl2_val = 0;
dev_dbg(component->dev, "%s\n", __func__);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl2_val |= 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
ctrl2_val &= ~1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl1_val |= 0x10;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl1_val |= 0x8;
break;
case SND_SOC_DAIFMT_DSP_A:
ctrl1_val |= 0x18;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
ctrl1_val |= 0x180;
break;
case SND_SOC_DAIFMT_IB_NF:
ctrl1_val |= 0x100;
break;
case SND_SOC_DAIFMT_NB_IF:
ctrl1_val |= 0x80;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component,
NAU8822_REG_AUDIO_INTERFACE,
NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK,
ctrl1_val);
snd_soc_component_update_bits(component,
NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val);
return 0;
}
static int nau8822_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
int val_len = 0, val_rate = 0;
unsigned int ctrl_val, bclk_fs, bclk_div;
/* make BCLK and LRC divide configuration if the codec as master. */
ctrl_val = snd_soc_component_read(component, NAU8822_REG_CLOCKING);
if (ctrl_val & NAU8822_CLK_MASTER) {
/* get the bclk and fs ratio */
bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
if (bclk_fs <= 32)
bclk_div = NAU8822_BCLKDIV_8;
else if (bclk_fs <= 64)
bclk_div = NAU8822_BCLKDIV_4;
else if (bclk_fs <= 128)
bclk_div = NAU8822_BCLKDIV_2;
else
return -EINVAL;
snd_soc_component_update_bits(component, NAU8822_REG_CLOCKING,
NAU8822_BCLKSEL_MASK, bclk_div);
}
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val_len |= NAU8822_WLEN_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val_len |= NAU8822_WLEN_24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
val_len |= NAU8822_WLEN_32;
break;
default:
return -EINVAL;
}
switch (params_rate(params)) {
case 8000:
val_rate |= NAU8822_SMPLR_8K;
break;
case 11025:
val_rate |= NAU8822_SMPLR_12K;
break;
case 16000:
val_rate |= NAU8822_SMPLR_16K;
break;
case 22050:
val_rate |= NAU8822_SMPLR_24K;
break;
case 32000:
val_rate |= NAU8822_SMPLR_32K;
break;
case 44100:
case 48000:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component,
NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len);
snd_soc_component_update_bits(component,
NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate);
/* If the master clock is from MCLK, provide the runtime FS for driver
* to get the master clock prescaler configuration.
*/
if (nau8822->div_id == NAU8822_CLK_MCLK)
nau8822_config_clkdiv(dai, 0, params_rate(params));
return 0;
}
static int nau8822_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
dev_dbg(component->dev, "%s: %d\n", __func__, mute);
if (mute)
snd_soc_component_update_bits(component,
NAU8822_REG_DAC_CONTROL, 0x40, 0x40);
else
snd_soc_component_update_bits(component,
NAU8822_REG_DAC_CONTROL, 0x40, 0);
return 0;
}
static int nau8822_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1,
NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1,
NAU8822_IOBUF_EN | NAU8822_ABIAS_EN,
NAU8822_IOBUF_EN | NAU8822_ABIAS_EN);
if (snd_soc_component_get_bias_level(component) ==
SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1,
NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K);
mdelay(100);
}
snd_soc_component_update_bits(component,
NAU8822_REG_POWER_MANAGEMENT_1,
NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_write(component,
NAU8822_REG_POWER_MANAGEMENT_1, 0);
snd_soc_component_write(component,
NAU8822_REG_POWER_MANAGEMENT_2, 0);
snd_soc_component_write(component,
NAU8822_REG_POWER_MANAGEMENT_3, 0);
break;
}
dev_dbg(component->dev, "%s: %d\n", __func__, level);
return 0;
}
#define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000)
#define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops nau8822_dai_ops = {
.hw_params = nau8822_hw_params,
.mute_stream = nau8822_mute,
.set_fmt = nau8822_set_dai_fmt,
.set_sysclk = nau8822_set_dai_sysclk,
.set_pll = nau8822_set_pll,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver nau8822_dai = {
.name = "nau8822-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8822_RATES,
.formats = NAU8822_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = NAU8822_RATES,
.formats = NAU8822_FORMATS,
},
.ops = &nau8822_dai_ops,
.symmetric_rate = 1,
};
static int nau8822_suspend(struct snd_soc_component *component)
{
struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
regcache_mark_dirty(nau8822->regmap);
return 0;
}
static int nau8822_resume(struct snd_soc_component *component)
{
struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
regcache_sync(nau8822->regmap);
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
return 0;
}
/*
* These registers contain an "update" bit - bit 8. This means, for example,
* that one can write new DAC digital volume for both channels, but only when
* the update bit is set, will also the volume be updated - simultaneously for
* both channels.
*/
static const int update_reg[] = {
NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
NAU8822_REG_LEFT_INP_PGA_CONTROL,
NAU8822_REG_RIGHT_INP_PGA_CONTROL,
NAU8822_REG_LHP_VOLUME,
NAU8822_REG_RHP_VOLUME,
NAU8822_REG_LSPKOUT_VOLUME,
NAU8822_REG_RSPKOUT_VOLUME,
};
static int nau8822_probe(struct snd_soc_component *component)
{
int i;
struct device_node *of_node = component->dev->of_node;
/*
* Set the update bit in all registers, that have one. This way all
* writes to those registers will also cause the update bit to be
* written.
*/
for (i = 0; i < ARRAY_SIZE(update_reg); i++)
snd_soc_component_update_bits(component,
update_reg[i], 0x100, 0x100);
/* Check property to configure the two loudspeaker outputs as
* a single Bridge Tied Load output
*/
if (of_property_read_bool(of_node, "nuvoton,spk-btl"))
snd_soc_component_update_bits(component,
NAU8822_REG_RIGHT_SPEAKER_CONTROL,
NAU8822_RSUBBYP, NAU8822_RSUBBYP);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_nau8822 = {
.probe = nau8822_probe,
.suspend = nau8822_suspend,
.resume = nau8822_resume,
.set_bias_level = nau8822_set_bias_level,
.controls = nau8822_snd_controls,
.num_controls = ARRAY_SIZE(nau8822_snd_controls),
.dapm_widgets = nau8822_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets),
.dapm_routes = nau8822_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config nau8822_regmap_config = {
.reg_bits = 7,
.val_bits = 9,
.max_register = NAU8822_REG_MAX_REGISTER,
.volatile_reg = nau8822_volatile,
.readable_reg = nau8822_readable_reg,
.writeable_reg = nau8822_writeable_reg,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = nau8822_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults),
};
static int nau8822_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct nau8822 *nau8822 = dev_get_platdata(dev);
int ret;
if (!nau8822) {
nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL);
if (nau8822 == NULL)
return -ENOMEM;
}
i2c_set_clientdata(i2c, nau8822);
nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
if (IS_ERR(nau8822->regmap)) {
ret = PTR_ERR(nau8822->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
nau8822->dev = dev;
/* Reset the codec */
ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822,
&nau8822_dai, 1);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id nau8822_i2c_id[] = {
{ "nau8822", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id nau8822_of_match[] = {
{ .compatible = "nuvoton,nau8822", },
{ }
};
MODULE_DEVICE_TABLE(of, nau8822_of_match);
#endif
static struct i2c_driver nau8822_i2c_driver = {
.driver = {
.name = "nau8822",
.of_match_table = of_match_ptr(nau8822_of_match),
},
.probe = nau8822_i2c_probe,
.id_table = nau8822_i2c_id,
};
module_i2c_driver(nau8822_i2c_driver);
MODULE_DESCRIPTION("ASoC NAU8822 codec driver");
MODULE_AUTHOR("David Lin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/nau8822.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* stac9766.c -- ALSA SoC STAC9766 codec support
*
* Copyright 2009 Jon Smirl, Digispeaker
* Author: Jon Smirl <[email protected]>
*
* Features:-
*
* o Support for AC97 Codec, S/PDIF
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define STAC9766_VENDOR_ID 0x83847666
#define STAC9766_VENDOR_ID_MASK 0xffffffff
#define AC97_STAC_DA_CONTROL 0x6A
#define AC97_STAC_ANALOG_SPECIAL 0x6E
#define AC97_STAC_STEREO_MIC 0x78
static const struct reg_default stac9766_reg_defaults[] = {
{ 0x02, 0x8000 },
{ 0x04, 0x8000 },
{ 0x06, 0x8000 },
{ 0x0a, 0x0000 },
{ 0x0c, 0x8008 },
{ 0x0e, 0x8008 },
{ 0x10, 0x8808 },
{ 0x12, 0x8808 },
{ 0x14, 0x8808 },
{ 0x16, 0x8808 },
{ 0x18, 0x8808 },
{ 0x1a, 0x0000 },
{ 0x1c, 0x8000 },
{ 0x20, 0x0000 },
{ 0x22, 0x0000 },
{ 0x28, 0x0a05 },
{ 0x2c, 0xbb80 },
{ 0x32, 0xbb80 },
{ 0x3a, 0x2000 },
{ 0x3e, 0x0100 },
{ 0x4c, 0x0300 },
{ 0x4e, 0xffff },
{ 0x50, 0x0000 },
{ 0x52, 0x0000 },
{ 0x54, 0x0000 },
{ 0x6a, 0x0000 },
{ 0x6e, 0x1000 },
{ 0x72, 0x0000 },
{ 0x78, 0x0000 },
};
static const struct regmap_config stac9766_regmap_config = {
.reg_bits = 16,
.reg_stride = 2,
.val_bits = 16,
.max_register = 0x78,
.cache_type = REGCACHE_MAPLE,
.volatile_reg = regmap_ac97_default_volatile,
.reg_defaults = stac9766_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(stac9766_reg_defaults),
};
static const char *stac9766_record_mux[] = {"Mic", "CD", "Video", "AUX",
"Line", "Stereo Mix", "Mono Mix", "Phone"};
static const char *stac9766_mono_mux[] = {"Mix", "Mic"};
static const char *stac9766_mic_mux[] = {"Mic1", "Mic2"};
static const char *stac9766_SPDIF_mux[] = {"PCM", "ADC Record"};
static const char *stac9766_popbypass_mux[] = {"Normal", "Bypass Mixer"};
static const char *stac9766_record_all_mux[] = {"All analog",
"Analog plus DAC"};
static const char *stac9766_boost1[] = {"0dB", "10dB"};
static const char *stac9766_boost2[] = {"0dB", "20dB"};
static const char *stac9766_stereo_mic[] = {"Off", "On"};
static SOC_ENUM_DOUBLE_DECL(stac9766_record_enum,
AC97_REC_SEL, 8, 0, stac9766_record_mux);
static SOC_ENUM_SINGLE_DECL(stac9766_mono_enum,
AC97_GENERAL_PURPOSE, 9, stac9766_mono_mux);
static SOC_ENUM_SINGLE_DECL(stac9766_mic_enum,
AC97_GENERAL_PURPOSE, 8, stac9766_mic_mux);
static SOC_ENUM_SINGLE_DECL(stac9766_SPDIF_enum,
AC97_STAC_DA_CONTROL, 1, stac9766_SPDIF_mux);
static SOC_ENUM_SINGLE_DECL(stac9766_popbypass_enum,
AC97_GENERAL_PURPOSE, 15, stac9766_popbypass_mux);
static SOC_ENUM_SINGLE_DECL(stac9766_record_all_enum,
AC97_STAC_ANALOG_SPECIAL, 12,
stac9766_record_all_mux);
static SOC_ENUM_SINGLE_DECL(stac9766_boost1_enum,
AC97_MIC, 6, stac9766_boost1); /* 0/10dB */
static SOC_ENUM_SINGLE_DECL(stac9766_boost2_enum,
AC97_STAC_ANALOG_SPECIAL, 2, stac9766_boost2); /* 0/20dB */
static SOC_ENUM_SINGLE_DECL(stac9766_stereo_mic_enum,
AC97_STAC_STEREO_MIC, 2, stac9766_stereo_mic);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(master_tlv, -4650, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(record_tlv, 0, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(beep_tlv, -4500, 300, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(mix_tlv, -3450, 150, 0);
static const struct snd_kcontrol_new stac9766_snd_ac97_controls[] = {
SOC_DOUBLE_TLV("Speaker Volume", AC97_MASTER, 8, 0, 31, 1, master_tlv),
SOC_SINGLE("Speaker Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE_TLV("Headphone Volume", AC97_HEADPHONE, 8, 0, 31, 1,
master_tlv),
SOC_SINGLE("Headphone Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_SINGLE_TLV("Mono Out Volume", AC97_MASTER_MONO, 0, 31, 1,
master_tlv),
SOC_SINGLE("Mono Out Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_DOUBLE_TLV("Record Volume", AC97_REC_GAIN, 8, 0, 15, 0, record_tlv),
SOC_SINGLE("Record Switch", AC97_REC_GAIN, 15, 1, 1),
SOC_SINGLE_TLV("Beep Volume", AC97_PC_BEEP, 1, 15, 1, beep_tlv),
SOC_SINGLE("Beep Switch", AC97_PC_BEEP, 15, 1, 1),
SOC_SINGLE("Beep Frequency", AC97_PC_BEEP, 5, 127, 1),
SOC_SINGLE_TLV("Phone Volume", AC97_PHONE, 0, 31, 1, mix_tlv),
SOC_SINGLE("Phone Switch", AC97_PHONE, 15, 1, 1),
SOC_ENUM("Mic Boost1", stac9766_boost1_enum),
SOC_ENUM("Mic Boost2", stac9766_boost2_enum),
SOC_SINGLE_TLV("Mic Volume", AC97_MIC, 0, 31, 1, mix_tlv),
SOC_SINGLE("Mic Switch", AC97_MIC, 15, 1, 1),
SOC_ENUM("Stereo Mic", stac9766_stereo_mic_enum),
SOC_DOUBLE_TLV("Line Volume", AC97_LINE, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("Line Switch", AC97_LINE, 15, 1, 1),
SOC_DOUBLE_TLV("CD Volume", AC97_CD, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("CD Switch", AC97_CD, 15, 1, 1),
SOC_DOUBLE_TLV("AUX Volume", AC97_AUX, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("AUX Switch", AC97_AUX, 15, 1, 1),
SOC_DOUBLE_TLV("Video Volume", AC97_VIDEO, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("Video Switch", AC97_VIDEO, 15, 1, 1),
SOC_DOUBLE_TLV("DAC Volume", AC97_PCM, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("DAC Switch", AC97_PCM, 15, 1, 1),
SOC_SINGLE("Loopback Test Switch", AC97_GENERAL_PURPOSE, 7, 1, 0),
SOC_SINGLE("3D Volume", AC97_3D_CONTROL, 3, 2, 1),
SOC_SINGLE("3D Switch", AC97_GENERAL_PURPOSE, 13, 1, 0),
SOC_ENUM("SPDIF Mux", stac9766_SPDIF_enum),
SOC_ENUM("Mic1/2 Mux", stac9766_mic_enum),
SOC_ENUM("Record All Mux", stac9766_record_all_enum),
SOC_ENUM("Record Mux", stac9766_record_enum),
SOC_ENUM("Mono Mux", stac9766_mono_enum),
SOC_ENUM("Pop Bypass Mux", stac9766_popbypass_enum),
};
static int ac97_analog_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned short reg;
/* enable variable rate audio, disable SPDIF output */
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x5, 0x1);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return snd_soc_component_write(component, reg, runtime->rate);
}
static int ac97_digital_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned short reg;
snd_soc_component_write(component, AC97_SPDIF, 0x2002);
/* Enable VRA and SPDIF out */
snd_soc_component_update_bits(component, AC97_EXTENDED_STATUS, 0x5, 0x5);
reg = AC97_PCM_FRONT_DAC_RATE;
return snd_soc_component_write(component, reg, runtime->rate);
}
static int stac9766_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON: /* full On */
case SND_SOC_BIAS_PREPARE: /* partial On */
case SND_SOC_BIAS_STANDBY: /* Off, with power */
snd_soc_component_write(component, AC97_POWERDOWN, 0x0000);
break;
case SND_SOC_BIAS_OFF: /* Off, without power */
/* disable everything including AC link */
snd_soc_component_write(component, AC97_POWERDOWN, 0xffff);
break;
}
return 0;
}
static int stac9766_component_resume(struct snd_soc_component *component)
{
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
return snd_ac97_reset(ac97, true, STAC9766_VENDOR_ID,
STAC9766_VENDOR_ID_MASK);
}
static const struct snd_soc_dai_ops stac9766_dai_ops_analog = {
.prepare = ac97_analog_prepare,
};
static const struct snd_soc_dai_ops stac9766_dai_ops_digital = {
.prepare = ac97_digital_prepare,
};
static struct snd_soc_dai_driver stac9766_dai[] = {
{
.name = "stac9766-hifi-analog",
/* stream cababilities */
.playback = {
.stream_name = "stac9766 analog",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SND_SOC_STD_AC97_FMTS,
},
.capture = {
.stream_name = "stac9766 analog",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SND_SOC_STD_AC97_FMTS,
},
/* alsa ops */
.ops = &stac9766_dai_ops_analog,
},
{
.name = "stac9766-hifi-IEC958",
/* stream cababilities */
.playback = {
.stream_name = "stac9766 IEC958",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
},
/* alsa ops */
.ops = &stac9766_dai_ops_digital,
}
};
static int stac9766_component_probe(struct snd_soc_component *component)
{
struct snd_ac97 *ac97;
struct regmap *regmap;
int ret;
ac97 = snd_soc_new_ac97_component(component, STAC9766_VENDOR_ID,
STAC9766_VENDOR_ID_MASK);
if (IS_ERR(ac97))
return PTR_ERR(ac97);
regmap = regmap_init_ac97(ac97, &stac9766_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto err_free_ac97;
}
snd_soc_component_init_regmap(component, regmap);
snd_soc_component_set_drvdata(component, ac97);
return 0;
err_free_ac97:
snd_soc_free_ac97_component(ac97);
return ret;
}
static void stac9766_component_remove(struct snd_soc_component *component)
{
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
snd_soc_component_exit_regmap(component);
snd_soc_free_ac97_component(ac97);
}
static const struct snd_soc_component_driver soc_component_dev_stac9766 = {
.controls = stac9766_snd_ac97_controls,
.num_controls = ARRAY_SIZE(stac9766_snd_ac97_controls),
.set_bias_level = stac9766_set_bias_level,
.probe = stac9766_component_probe,
.remove = stac9766_component_remove,
.resume = stac9766_component_resume,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int stac9766_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_stac9766, stac9766_dai, ARRAY_SIZE(stac9766_dai));
}
static struct platform_driver stac9766_codec_driver = {
.driver = {
.name = "stac9766-codec",
},
.probe = stac9766_probe,
};
module_platform_driver(stac9766_codec_driver);
MODULE_DESCRIPTION("ASoC stac9766 driver");
MODULE_AUTHOR("Jon Smirl <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/stac9766.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments PCM186x Universal Audio ADC - SPI
*
* Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
* Andreas Dannenberg <[email protected]>
* Andrew F. Davis <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include "pcm186x.h"
static const struct of_device_id pcm186x_of_match[] = {
{ .compatible = "ti,pcm1862", .data = (void *)PCM1862 },
{ .compatible = "ti,pcm1863", .data = (void *)PCM1863 },
{ .compatible = "ti,pcm1864", .data = (void *)PCM1864 },
{ .compatible = "ti,pcm1865", .data = (void *)PCM1865 },
{ }
};
MODULE_DEVICE_TABLE(of, pcm186x_of_match);
static int pcm186x_spi_probe(struct spi_device *spi)
{
const enum pcm186x_type type =
(enum pcm186x_type)spi_get_device_id(spi)->driver_data;
int irq = spi->irq;
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &pcm186x_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return pcm186x_probe(&spi->dev, type, irq, regmap);
}
static const struct spi_device_id pcm186x_spi_id[] = {
{ "pcm1862", PCM1862 },
{ "pcm1863", PCM1863 },
{ "pcm1864", PCM1864 },
{ "pcm1865", PCM1865 },
{ }
};
MODULE_DEVICE_TABLE(spi, pcm186x_spi_id);
static struct spi_driver pcm186x_spi_driver = {
.probe = pcm186x_spi_probe,
.id_table = pcm186x_spi_id,
.driver = {
.name = "pcm186x",
.of_match_table = pcm186x_of_match,
},
};
module_spi_driver(pcm186x_spi_driver);
MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("PCM186x Universal Audio ADC SPI Interface Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm186x-spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for ADAU1701 SigmaDSP processor
*
* Copyright 2011 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
* based on an inital version by Cliff Cai <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/unaligned.h>
#include "sigmadsp.h"
#include "adau1701.h"
#define ADAU1701_SAFELOAD_DATA(i) (0x0810 + (i))
#define ADAU1701_SAFELOAD_ADDR(i) (0x0815 + (i))
#define ADAU1701_DSPCTRL 0x081c
#define ADAU1701_SEROCTL 0x081e
#define ADAU1701_SERICTL 0x081f
#define ADAU1701_AUXNPOW 0x0822
#define ADAU1701_PINCONF_0 0x0820
#define ADAU1701_PINCONF_1 0x0821
#define ADAU1701_AUXNPOW 0x0822
#define ADAU1701_OSCIPOW 0x0826
#define ADAU1701_DACSET 0x0827
#define ADAU1701_MAX_REGISTER 0x0828
#define ADAU1701_DSPCTRL_CR (1 << 2)
#define ADAU1701_DSPCTRL_DAM (1 << 3)
#define ADAU1701_DSPCTRL_ADM (1 << 4)
#define ADAU1701_DSPCTRL_IST (1 << 5)
#define ADAU1701_DSPCTRL_SR_48 0x00
#define ADAU1701_DSPCTRL_SR_96 0x01
#define ADAU1701_DSPCTRL_SR_192 0x02
#define ADAU1701_DSPCTRL_SR_MASK 0x03
#define ADAU1701_SEROCTL_INV_LRCLK 0x2000
#define ADAU1701_SEROCTL_INV_BCLK 0x1000
#define ADAU1701_SEROCTL_MASTER 0x0800
#define ADAU1701_SEROCTL_OBF16 0x0000
#define ADAU1701_SEROCTL_OBF8 0x0200
#define ADAU1701_SEROCTL_OBF4 0x0400
#define ADAU1701_SEROCTL_OBF2 0x0600
#define ADAU1701_SEROCTL_OBF_MASK 0x0600
#define ADAU1701_SEROCTL_OLF1024 0x0000
#define ADAU1701_SEROCTL_OLF512 0x0080
#define ADAU1701_SEROCTL_OLF256 0x0100
#define ADAU1701_SEROCTL_OLF_MASK 0x0180
#define ADAU1701_SEROCTL_MSB_DEALY1 0x0000
#define ADAU1701_SEROCTL_MSB_DEALY0 0x0004
#define ADAU1701_SEROCTL_MSB_DEALY8 0x0008
#define ADAU1701_SEROCTL_MSB_DEALY12 0x000c
#define ADAU1701_SEROCTL_MSB_DEALY16 0x0010
#define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c
#define ADAU1701_SEROCTL_WORD_LEN_24 0x0000
#define ADAU1701_SEROCTL_WORD_LEN_20 0x0001
#define ADAU1701_SEROCTL_WORD_LEN_16 0x0002
#define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003
#define ADAU1701_AUXNPOW_VBPD 0x40
#define ADAU1701_AUXNPOW_VRPD 0x20
#define ADAU1701_SERICTL_I2S 0
#define ADAU1701_SERICTL_LEFTJ 1
#define ADAU1701_SERICTL_TDM 2
#define ADAU1701_SERICTL_RIGHTJ_24 3
#define ADAU1701_SERICTL_RIGHTJ_20 4
#define ADAU1701_SERICTL_RIGHTJ_18 5
#define ADAU1701_SERICTL_RIGHTJ_16 6
#define ADAU1701_SERICTL_MODE_MASK 7
#define ADAU1701_SERICTL_INV_BCLK BIT(3)
#define ADAU1701_SERICTL_INV_LRCLK BIT(4)
#define ADAU1701_OSCIPOW_OPD 0x04
#define ADAU1701_DACSET_DACINIT 1
#define ADAU1707_CLKDIV_UNSET (-1U)
#define ADAU1701_FIRMWARE "adau1701.bin"
static const char * const supply_names[] = {
"dvdd", "avdd"
};
struct adau1701 {
struct gpio_desc *gpio_nreset;
struct gpio_descs *gpio_pll_mode;
unsigned int dai_fmt;
unsigned int pll_clkdiv;
unsigned int sysclk;
struct regmap *regmap;
struct i2c_client *client;
u8 pin_config[12];
struct sigmadsp *sigmadsp;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static const struct snd_kcontrol_new adau1701_controls[] = {
SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0),
};
static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1),
SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1),
SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1),
SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1),
SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1),
SND_SOC_DAPM_OUTPUT("OUT0"),
SND_SOC_DAPM_OUTPUT("OUT1"),
SND_SOC_DAPM_OUTPUT("OUT2"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_INPUT("IN0"),
SND_SOC_DAPM_INPUT("IN1"),
};
static const struct snd_soc_dapm_route adau1701_dapm_routes[] = {
{ "OUT0", NULL, "DAC0" },
{ "OUT1", NULL, "DAC1" },
{ "OUT2", NULL, "DAC2" },
{ "OUT3", NULL, "DAC3" },
{ "ADC", NULL, "IN0" },
{ "ADC", NULL, "IN1" },
};
static unsigned int adau1701_register_size(struct device *dev,
unsigned int reg)
{
switch (reg) {
case ADAU1701_PINCONF_0:
case ADAU1701_PINCONF_1:
return 3;
case ADAU1701_DSPCTRL:
case ADAU1701_SEROCTL:
case ADAU1701_AUXNPOW:
case ADAU1701_OSCIPOW:
case ADAU1701_DACSET:
return 2;
case ADAU1701_SERICTL:
return 1;
}
dev_err(dev, "Unsupported register address: %d\n", reg);
return 0;
}
static bool adau1701_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADAU1701_DACSET:
case ADAU1701_DSPCTRL:
return true;
default:
return false;
}
}
static int adau1701_reg_write(void *context, unsigned int reg,
unsigned int value)
{
struct i2c_client *client = context;
unsigned int i;
unsigned int size;
uint8_t buf[5];
int ret;
size = adau1701_register_size(&client->dev, reg);
if (size == 0)
return -EINVAL;
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
for (i = size + 1; i >= 2; --i) {
buf[i] = value;
value >>= 8;
}
ret = i2c_master_send(client, buf, size + 2);
if (ret == size + 2)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int adau1701_reg_read(void *context, unsigned int reg,
unsigned int *value)
{
int ret;
unsigned int i;
unsigned int size;
uint8_t send_buf[2], recv_buf[3];
struct i2c_client *client = context;
struct i2c_msg msgs[2];
size = adau1701_register_size(&client->dev, reg);
if (size == 0)
return -EINVAL;
send_buf[0] = reg >> 8;
send_buf[1] = reg & 0xff;
msgs[0].addr = client->addr;
msgs[0].len = sizeof(send_buf);
msgs[0].buf = send_buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = size;
msgs[1].buf = recv_buf;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
return ret;
else if (ret != ARRAY_SIZE(msgs))
return -EIO;
*value = 0;
for (i = 0; i < size; i++) {
*value <<= 8;
*value |= recv_buf[i];
}
return 0;
}
static int adau1701_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
const uint8_t bytes[], size_t len)
{
struct i2c_client *client = to_i2c_client(sigmadsp->dev);
struct adau1701 *adau1701 = i2c_get_clientdata(client);
unsigned int val;
unsigned int i;
uint8_t buf[10];
int ret;
ret = regmap_read(adau1701->regmap, ADAU1701_DSPCTRL, &val);
if (ret)
return ret;
if (val & ADAU1701_DSPCTRL_IST)
msleep(50);
for (i = 0; i < len / 4; i++) {
put_unaligned_le16(ADAU1701_SAFELOAD_DATA(i), buf);
buf[2] = 0x00;
memcpy(buf + 3, bytes + i * 4, 4);
ret = i2c_master_send(client, buf, 7);
if (ret < 0)
return ret;
else if (ret != 7)
return -EIO;
put_unaligned_le16(ADAU1701_SAFELOAD_ADDR(i), buf);
put_unaligned_le16(addr + i, buf + 2);
ret = i2c_master_send(client, buf, 4);
if (ret < 0)
return ret;
else if (ret != 4)
return -EIO;
}
return regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
ADAU1701_DSPCTRL_IST, ADAU1701_DSPCTRL_IST);
}
static const struct sigmadsp_ops adau1701_sigmadsp_ops = {
.safeload = adau1701_safeload,
};
static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv,
unsigned int rate)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
int ret;
DECLARE_BITMAP(values, 2);
sigmadsp_reset(adau1701->sigmadsp);
if (clkdiv != ADAU1707_CLKDIV_UNSET && adau1701->gpio_pll_mode) {
switch (clkdiv) {
case 64:
__assign_bit(0, values, 0);
__assign_bit(1, values, 0);
break;
case 256:
__assign_bit(0, values, 0);
__assign_bit(1, values, 1);
break;
case 384:
__assign_bit(0, values, 1);
__assign_bit(1, values, 0);
break;
case 0: /* fallback */
case 512:
__assign_bit(0, values, 1);
__assign_bit(1, values, 1);
break;
}
gpiod_set_array_value_cansleep(adau1701->gpio_pll_mode->ndescs,
adau1701->gpio_pll_mode->desc, adau1701->gpio_pll_mode->info,
values);
}
adau1701->pll_clkdiv = clkdiv;
if (adau1701->gpio_nreset) {
gpiod_set_value_cansleep(adau1701->gpio_nreset, 0);
/* minimum reset time is 20ns */
udelay(1);
gpiod_set_value_cansleep(adau1701->gpio_nreset, 1);
/* power-up time may be as long as 85ms */
mdelay(85);
}
/*
* Postpone the firmware download to a point in time when we
* know the correct PLL setup
*/
if (clkdiv != ADAU1707_CLKDIV_UNSET) {
ret = sigmadsp_setup(adau1701->sigmadsp, rate);
if (ret) {
dev_warn(component->dev, "Failed to load firmware\n");
return ret;
}
}
regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT);
regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR);
regcache_mark_dirty(adau1701->regmap);
regcache_sync(adau1701->regmap);
return 0;
}
static int adau1701_set_capture_pcm_format(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK;
unsigned int val;
switch (params_width(params)) {
case 16:
val = ADAU1701_SEROCTL_WORD_LEN_16;
break;
case 20:
val = ADAU1701_SEROCTL_WORD_LEN_20;
break;
case 24:
val = ADAU1701_SEROCTL_WORD_LEN_24;
break;
default:
return -EINVAL;
}
if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) {
switch (params_width(params)) {
case 16:
val |= ADAU1701_SEROCTL_MSB_DEALY16;
break;
case 20:
val |= ADAU1701_SEROCTL_MSB_DEALY12;
break;
case 24:
val |= ADAU1701_SEROCTL_MSB_DEALY8;
break;
}
mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK;
}
regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val);
return 0;
}
static int adau1701_set_playback_pcm_format(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
unsigned int val;
if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
return 0;
switch (params_width(params)) {
case 16:
val = ADAU1701_SERICTL_RIGHTJ_16;
break;
case 20:
val = ADAU1701_SERICTL_RIGHTJ_20;
break;
case 24:
val = ADAU1701_SERICTL_RIGHTJ_24;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL,
ADAU1701_SERICTL_MODE_MASK, val);
return 0;
}
static int adau1701_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
unsigned int clkdiv = adau1701->sysclk / params_rate(params);
unsigned int val;
int ret;
/*
* If the mclk/lrclk ratio changes, the chip needs updated PLL
* mode GPIO settings, and a full reset cycle, including a new
* firmware upload.
*/
if (clkdiv != adau1701->pll_clkdiv) {
ret = adau1701_reset(component, clkdiv, params_rate(params));
if (ret < 0)
return ret;
}
switch (params_rate(params)) {
case 192000:
val = ADAU1701_DSPCTRL_SR_192;
break;
case 96000:
val = ADAU1701_DSPCTRL_SR_96;
break;
case 48000:
val = ADAU1701_DSPCTRL_SR_48;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
ADAU1701_DSPCTRL_SR_MASK, val);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return adau1701_set_playback_pcm_format(component, params);
else
return adau1701_set_capture_pcm_format(component, params);
}
static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
unsigned int serictl = 0x00, seroctl = 0x00;
bool invert_lrclk;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
/* master, 64-bits per sample, 1 frame per sample */
seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
| ADAU1701_SEROCTL_OLF1024;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
invert_lrclk = false;
break;
case SND_SOC_DAIFMT_NB_IF:
invert_lrclk = true;
break;
case SND_SOC_DAIFMT_IB_NF:
invert_lrclk = false;
serictl |= ADAU1701_SERICTL_INV_BCLK;
seroctl |= ADAU1701_SEROCTL_INV_BCLK;
break;
case SND_SOC_DAIFMT_IB_IF:
invert_lrclk = true;
serictl |= ADAU1701_SERICTL_INV_BCLK;
seroctl |= ADAU1701_SEROCTL_INV_BCLK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
serictl |= ADAU1701_SERICTL_LEFTJ;
seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
invert_lrclk = !invert_lrclk;
break;
case SND_SOC_DAIFMT_RIGHT_J:
serictl |= ADAU1701_SERICTL_RIGHTJ_24;
seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
invert_lrclk = !invert_lrclk;
break;
default:
return -EINVAL;
}
if (invert_lrclk) {
seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
serictl |= ADAU1701_SERICTL_INV_LRCLK;
}
adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
return 0;
}
static int adau1701_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD;
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* Enable VREF and VREF buffer */
regmap_update_bits(adau1701->regmap,
ADAU1701_AUXNPOW, mask, 0x00);
break;
case SND_SOC_BIAS_OFF:
/* Disable VREF and VREF buffer */
regmap_update_bits(adau1701->regmap,
ADAU1701_AUXNPOW, mask, mask);
break;
}
return 0;
}
static int adau1701_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
unsigned int mask = ADAU1701_DSPCTRL_DAM;
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
unsigned int val;
if (mute)
val = 0;
else
val = mask;
regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val);
return 0;
}
static int adau1701_set_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
unsigned int val;
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case ADAU1701_CLK_SRC_OSC:
val = 0x0;
break;
case ADAU1701_CLK_SRC_MCLK:
val = ADAU1701_OSCIPOW_OPD;
break;
default:
return -EINVAL;
}
regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW,
ADAU1701_OSCIPOW_OPD, val);
adau1701->sysclk = freq;
return 0;
}
static int adau1701_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(dai->component);
return sigmadsp_restrict_params(adau1701->sigmadsp, substream);
}
#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000)
#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops adau1701_dai_ops = {
.set_fmt = adau1701_set_dai_fmt,
.hw_params = adau1701_hw_params,
.mute_stream = adau1701_mute_stream,
.startup = adau1701_startup,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver adau1701_dai = {
.name = "adau1701",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = ADAU1701_RATES,
.formats = ADAU1701_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = ADAU1701_RATES,
.formats = ADAU1701_FORMATS,
},
.ops = &adau1701_dai_ops,
.symmetric_rate = 1,
};
#ifdef CONFIG_OF
static const struct of_device_id adau1701_dt_ids[] = {
{ .compatible = "adi,adau1701", },
{ }
};
MODULE_DEVICE_TABLE(of, adau1701_dt_ids);
#endif
static int adau1701_probe(struct snd_soc_component *component)
{
int i, ret;
unsigned int val;
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
ret = sigmadsp_attach(adau1701->sigmadsp, component);
if (ret)
return ret;
ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
adau1701->supplies);
if (ret < 0) {
dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
/*
* Let the pll_clkdiv variable default to something that won't happen
* at runtime. That way, we can postpone the firmware download from
* adau1701_reset() to a point in time when we know the correct PLL
* mode parameters.
*/
adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET;
/* initalize with pre-configured pll mode settings */
ret = adau1701_reset(component, adau1701->pll_clkdiv, 0);
if (ret < 0)
goto exit_regulators_disable;
/* set up pin config */
val = 0;
for (i = 0; i < 6; i++)
val |= adau1701->pin_config[i] << (i * 4);
regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val);
val = 0;
for (i = 0; i < 6; i++)
val |= adau1701->pin_config[i + 6] << (i * 4);
regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val);
return 0;
exit_regulators_disable:
regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
return ret;
}
static void adau1701_remove(struct snd_soc_component *component)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
if (adau1701->gpio_nreset)
gpiod_set_value_cansleep(adau1701->gpio_nreset, 0);
regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
}
#ifdef CONFIG_PM
static int adau1701_suspend(struct snd_soc_component *component)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies),
adau1701->supplies);
return 0;
}
static int adau1701_resume(struct snd_soc_component *component)
{
struct adau1701 *adau1701 = snd_soc_component_get_drvdata(component);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
adau1701->supplies);
if (ret < 0) {
dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
return adau1701_reset(component, adau1701->pll_clkdiv, 0);
}
#else
#define adau1701_resume NULL
#define adau1701_suspend NULL
#endif /* CONFIG_PM */
static const struct snd_soc_component_driver adau1701_component_drv = {
.probe = adau1701_probe,
.remove = adau1701_remove,
.resume = adau1701_resume,
.suspend = adau1701_suspend,
.set_bias_level = adau1701_set_bias_level,
.controls = adau1701_controls,
.num_controls = ARRAY_SIZE(adau1701_controls),
.dapm_widgets = adau1701_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets),
.dapm_routes = adau1701_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes),
.set_sysclk = adau1701_set_sysclk,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config adau1701_regmap = {
.reg_bits = 16,
.val_bits = 32,
.max_register = ADAU1701_MAX_REGISTER,
.cache_type = REGCACHE_MAPLE,
.volatile_reg = adau1701_volatile_reg,
.reg_write = adau1701_reg_write,
.reg_read = adau1701_reg_read,
};
static int adau1701_i2c_probe(struct i2c_client *client)
{
struct adau1701 *adau1701;
struct device *dev = &client->dev;
int ret, i;
adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL);
if (!adau1701)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
adau1701->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(adau1701->supplies),
adau1701->supplies);
if (ret < 0) {
dev_err(dev, "Failed to get regulators: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
adau1701->supplies);
if (ret < 0) {
dev_err(dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
adau1701->client = client;
adau1701->regmap = devm_regmap_init(dev, NULL, client,
&adau1701_regmap);
if (IS_ERR(adau1701->regmap)) {
ret = PTR_ERR(adau1701->regmap);
goto exit_regulators_disable;
}
if (dev->of_node) {
of_property_read_u32(dev->of_node, "adi,pll-clkdiv",
&adau1701->pll_clkdiv);
of_property_read_u8_array(dev->of_node, "adi,pin-config",
adau1701->pin_config,
ARRAY_SIZE(adau1701->pin_config));
}
adau1701->gpio_nreset = devm_gpiod_get_optional(dev, "reset", GPIOD_IN);
if (IS_ERR(adau1701->gpio_nreset)) {
ret = PTR_ERR(adau1701->gpio_nreset);
goto exit_regulators_disable;
}
adau1701->gpio_pll_mode = devm_gpiod_get_array_optional(dev, "adi,pll-mode", GPIOD_OUT_LOW);
if (IS_ERR(adau1701->gpio_pll_mode)) {
ret = PTR_ERR(adau1701->gpio_pll_mode);
goto exit_regulators_disable;
}
i2c_set_clientdata(client, adau1701);
adau1701->sigmadsp = devm_sigmadsp_init_i2c(client,
&adau1701_sigmadsp_ops, ADAU1701_FIRMWARE);
if (IS_ERR(adau1701->sigmadsp)) {
ret = PTR_ERR(adau1701->sigmadsp);
goto exit_regulators_disable;
}
ret = devm_snd_soc_register_component(&client->dev,
&adau1701_component_drv,
&adau1701_dai, 1);
exit_regulators_disable:
regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
return ret;
}
static const struct i2c_device_id adau1701_i2c_id[] = {
{ "adau1401", 0 },
{ "adau1401a", 0 },
{ "adau1701", 0 },
{ "adau1702", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id);
static struct i2c_driver adau1701_i2c_driver = {
.driver = {
.name = "adau1701",
.of_match_table = of_match_ptr(adau1701_dt_ids),
},
.probe = adau1701_i2c_probe,
.id_table = adau1701_i2c_id,
};
module_i2c_driver(adau1701_i2c_driver);
MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver");
MODULE_AUTHOR("Cliff Cai <[email protected]>");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1701.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* CS4271 SPI audio driver
*
* Copyright (c) 2010 Alexander Sverdlin <[email protected]>
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "cs4271.h"
static int cs4271_spi_probe(struct spi_device *spi)
{
struct regmap_config config;
config = cs4271_regmap_config;
config.reg_bits = 16;
config.read_flag_mask = 0x21;
config.write_flag_mask = 0x20;
return cs4271_probe(&spi->dev, devm_regmap_init_spi(spi, &config));
}
static struct spi_driver cs4271_spi_driver = {
.driver = {
.name = "cs4271",
.of_match_table = of_match_ptr(cs4271_dt_ids),
},
.probe = cs4271_spi_probe,
};
module_spi_driver(cs4271_spi_driver);
MODULE_DESCRIPTION("ASoC CS4271 SPI Driver");
MODULE_AUTHOR("Alexander Sverdlin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs4271-spi.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt6359.c -- mt6359 ALSA SoC audio codec driver
//
// Copyright (c) 2020 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/sched.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "mt6359.h"
static void mt6359_set_gpio_smt(struct mt6359_priv *priv)
{
/* set gpio SMT mode */
regmap_update_bits(priv->regmap, MT6359_SMT_CON1, 0x3ff0, 0x3ff0);
}
static void mt6359_set_gpio_driving(struct mt6359_priv *priv)
{
/* 8:4mA(default), a:8mA, c:12mA, e:16mA */
regmap_update_bits(priv->regmap, MT6359_DRV_CON2, 0xffff, 0x8888);
regmap_update_bits(priv->regmap, MT6359_DRV_CON3, 0xffff, 0x8888);
regmap_update_bits(priv->regmap, MT6359_DRV_CON4, 0x00ff, 0x88);
}
static void mt6359_set_playback_gpio(struct mt6359_priv *priv)
{
/* set gpio mosi mode, clk / data mosi */
regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe);
regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249);
/* sync mosi */
regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6);
regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1);
}
static void mt6359_reset_playback_gpio(struct mt6359_priv *priv)
{
/* set pad_aud_*_mosi to GPIO mode and dir input
* reason:
* pad_aud_dat_mosi*, because the pin is used as boot strap
* don't clean clk/sync, for mtkaif protocol 2
*/
regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8);
regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0);
}
static void mt6359_set_capture_gpio(struct mt6359_priv *priv)
{
/* set gpio miso mode */
regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200);
regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009);
}
static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)
{
/* set pad_aud_*_miso to GPIO mode and dir input
* reason:
* pad_aud_clk_miso, because when playback only the miso_clk
* will also have 26m, so will have power leak
* pad_aud_dat_miso*, because the pin is used as boot strap
*/
regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
0x7 << 13, 0x0);
regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
0x3 << 0, 0x0);
}
/* use only when doing mtkaif calibraiton at the boot time */
static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
0x1 << RG_XO_AUDIO_EN_M_SFT,
(enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
}
/* use only when doing mtkaif calibraiton at the boot time */
static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
{
/* Enable/disable CLKSQ 26MHz */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
RG_CLKSQ_EN_MASK_SFT,
(enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
}
/* use only when doing mtkaif calibraiton at the boot time */
static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
RG_AUDGLB_PWRDN_VA32_MASK_SFT,
(enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
}
/* use only when doing mtkaif calibraiton at the boot time */
static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
0x0066, enable ? 0x0 : 0x66);
}
static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
RG_RSTB_DECODER_VA32_MASK_SFT,
(enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
}
static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)
{
switch (priv->mtkaif_protocol) {
case MT6359_MTKAIF_PROTOCOL_2_CLK_P2:
/* MTKAIF TX format setting */
regmap_update_bits(priv->regmap,
MT6359_AFE_ADDA_MTKAIF_CFG0,
0xffff, 0x0210);
/* enable aud_pad TX fifos */
regmap_update_bits(priv->regmap,
MT6359_AFE_AUD_PAD_TOP,
0xff00, 0x3800);
regmap_update_bits(priv->regmap,
MT6359_AFE_AUD_PAD_TOP,
0xff00, 0x3900);
break;
case MT6359_MTKAIF_PROTOCOL_2:
/* MTKAIF TX format setting */
regmap_update_bits(priv->regmap,
MT6359_AFE_ADDA_MTKAIF_CFG0,
0xffff, 0x0210);
/* enable aud_pad TX fifos */
regmap_update_bits(priv->regmap,
MT6359_AFE_AUD_PAD_TOP,
0xff00, 0x3100);
break;
case MT6359_MTKAIF_PROTOCOL_1:
default:
/* MTKAIF TX format setting */
regmap_update_bits(priv->regmap,
MT6359_AFE_ADDA_MTKAIF_CFG0,
0xffff, 0x0000);
/* enable aud_pad TX fifos */
regmap_update_bits(priv->regmap,
MT6359_AFE_AUD_PAD_TOP,
0xff00, 0x3100);
break;
}
}
static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
{
/* disable aud_pad TX fifos */
regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
0xff00, 0x3000);
}
void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
int mtkaif_protocol)
{
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
priv->mtkaif_protocol = mtkaif_protocol;
}
EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol);
void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
{
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
mt6359_set_playback_gpio(priv);
mt6359_set_capture_gpio(priv);
mt6359_mtkaif_tx_enable(priv);
mt6359_set_dcxo(priv, true);
mt6359_set_aud_global_bias(priv, true);
mt6359_set_clksq(priv, true);
mt6359_set_topck(priv, true);
/* set dat_miso_loopback on */
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
}
EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable);
void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
{
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
/* set dat_miso_loopback off */
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
mt6359_set_topck(priv, false);
mt6359_set_clksq(priv, false);
mt6359_set_aud_global_bias(priv, false);
mt6359_set_dcxo(priv, false);
mt6359_mtkaif_tx_disable(priv);
mt6359_reset_playback_gpio(priv);
mt6359_reset_capture_gpio(priv);
}
EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable);
void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
int phase_1, int phase_2, int phase_3)
{
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT,
phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT);
}
EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase);
static void zcd_disable(struct mt6359_priv *priv)
{
regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
}
static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
{
int i, stage;
int target = 7;
/* Enable/Reduce HPL/R main output stage step by step */
for (i = 0; i <= target; i++) {
stage = up ? i : target - i;
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT,
stage << RG_HPLOUTSTGCTRL_VAUDP32_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT,
stage << RG_HPROUTSTGCTRL_VAUDP32_SFT);
usleep_range(600, 650);
}
}
static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up)
{
int i, stage;
int target = 0xf;
/* Enable/Reduce HP aux feedback loop gain step by step */
for (i = 0; i <= target; i++) {
stage = up ? i : target - i;
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
0xf << 12, stage << 12);
usleep_range(600, 650);
}
}
static void hp_in_pair_current(struct mt6359_priv *priv, bool increase)
{
int i, stage;
int target = 0x3;
/* Set input diff pair bias select (Hi-Fi mode) */
if (priv->hp_hifi_mode) {
/* Reduce HP aux feedback loop gain step by step */
for (i = 0; i <= target; i++) {
stage = increase ? i : target - i;
regmap_update_bits(priv->regmap,
MT6359_AUDDEC_ANA_CON10,
0x3 << 3, stage << 3);
usleep_range(100, 150);
}
}
}
static void hp_pull_down(struct mt6359_priv *priv, bool enable)
{
int i;
if (enable) {
for (i = 0x0; i <= 0x7; i++) {
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
i << RG_HPPSHORT2VCM_VAUDP32_SFT);
usleep_range(100, 150);
}
} else {
for (i = 0x7; i >= 0x0; i--) {
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
RG_HPPSHORT2VCM_VAUDP32_MASK_SFT,
i << RG_HPPSHORT2VCM_VAUDP32_SFT);
usleep_range(100, 150);
}
}
}
static bool is_valid_hp_pga_idx(int reg_idx)
{
return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) ||
reg_idx == DL_GAIN_N_40DB;
}
static void headset_volume_ramp(struct mt6359_priv *priv,
int from, int to)
{
int offset = 0, count = 1, reg_idx;
if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) {
dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
__func__, from, to);
return;
}
dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to);
if (to > from)
offset = to - from;
else
offset = from - to;
while (offset > 0) {
if (to > from)
reg_idx = from + count;
else
reg_idx = from - count;
if (is_valid_hp_pga_idx(reg_idx)) {
regmap_update_bits(priv->regmap,
MT6359_ZCD_CON2,
DL_GAIN_REG_MASK,
(reg_idx << 7) | reg_idx);
usleep_range(600, 650);
}
offset--;
count++;
}
}
static int mt6359_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = 0;
int index = ucontrol->value.integer.value[0];
int orig_gain[2], new_gain[2];
int ret;
switch (mc->reg) {
case MT6359_ZCD_CON2:
orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
break;
case MT6359_ZCD_CON1:
orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
break;
case MT6359_ZCD_CON3:
orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
break;
case MT6359_AUDENC_ANA_CON0:
orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
break;
case MT6359_AUDENC_ANA_CON1:
orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
break;
case MT6359_AUDENC_ANA_CON2:
orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
break;
default:
return -EINVAL;
}
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret < 0)
return ret;
switch (mc->reg) {
case MT6359_ZCD_CON2:
regmap_read(priv->regmap, MT6359_ZCD_CON2, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
(reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
(reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
break;
case MT6359_ZCD_CON1:
regmap_read(priv->regmap, MT6359_ZCD_CON1, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
(reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
(reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
break;
case MT6359_ZCD_CON3:
regmap_read(priv->regmap, MT6359_ZCD_CON3, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
(reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
break;
case MT6359_AUDENC_ANA_CON0:
regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
(reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
break;
case MT6359_AUDENC_ANA_CON1:
regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
(reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
break;
case MT6359_AUDENC_ANA_CON2:
regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, ®);
priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] =
(reg >> RG_AUDPREAMP3GAIN_SFT) & RG_AUDPREAMP3GAIN_MASK;
new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
break;
}
ret = 0;
if (orig_gain[0] != new_gain[0]) {
ret = 1;
} else if (snd_soc_volsw_is_stereo(mc)) {
if (orig_gain[1] != new_gain[1])
ret = 1;
}
dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n",
__func__, kcontrol->id.name, mc->reg, reg, index);
return ret;
}
static int mt6359_get_playback_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
switch (mc->reg) {
case MT6359_ZCD_CON2:
ucontrol->value.integer.value[0] =
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
ucontrol->value.integer.value[1] =
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
break;
case MT6359_ZCD_CON1:
ucontrol->value.integer.value[0] =
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
ucontrol->value.integer.value[1] =
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
break;
case MT6359_ZCD_CON3:
ucontrol->value.integer.value[0] =
priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
break;
default:
return -EINVAL;
}
return 0;
}
/* MUX */
/* LOL MUX */
static const char * const lo_in_mux_map[] = {
"Open", "Playback_L_DAC", "Playback", "Test Mode"
};
static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map);
static const struct snd_kcontrol_new lo_in_mux_control =
SOC_DAPM_ENUM("LO Select", lo_in_mux_map_enum);
/*HP MUX */
static const char * const hp_in_mux_map[] = {
"Open",
"LoudSPK Playback",
"Audio Playback",
"Test Mode",
"HP Impedance",
};
static SOC_ENUM_SINGLE_DECL(hp_in_mux_map_enum,
SND_SOC_NOPM,
0,
hp_in_mux_map);
static const struct snd_kcontrol_new hp_in_mux_control =
SOC_DAPM_ENUM("HP Select", hp_in_mux_map_enum);
/* RCV MUX */
static const char * const rcv_in_mux_map[] = {
"Open", "Mute", "Voice Playback", "Test Mode"
};
static SOC_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
SND_SOC_NOPM,
0,
rcv_in_mux_map);
static const struct snd_kcontrol_new rcv_in_mux_control =
SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
/* DAC In MUX */
static const char * const dac_in_mux_map[] = {
"Normal Path", "Sgen"
};
static int dac_in_mux_map_value[] = {
0x0, 0x1,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
MT6359_AFE_TOP_CON0,
DL_SINE_ON_SFT,
DL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new dac_in_mux_control =
SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
/* AIF Out MUX */
static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
MT6359_AFE_TOP_CON0,
UL_SINE_ON_SFT,
UL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new aif_out_mux_control =
SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum,
MT6359_AFE_TOP_CON0,
ADDA6_UL_SINE_ON_SFT,
ADDA6_UL_SINE_ON_MASK,
dac_in_mux_map,
dac_in_mux_map_value);
static const struct snd_kcontrol_new aif2_out_mux_control =
SOC_DAPM_ENUM("AIF Out Select", aif2_out_mux_map_enum);
static const char * const ul_src_mux_map[] = {
"AMIC",
"DMIC",
};
static int ul_src_mux_map_value[] = {
UL_SRC_MUX_AMIC,
UL_SRC_MUX_DMIC,
};
static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum,
MT6359_AFE_UL_SRC_CON0_L,
UL_SDM_3_LEVEL_CTL_SFT,
UL_SDM_3_LEVEL_CTL_MASK,
ul_src_mux_map,
ul_src_mux_map_value);
static const struct snd_kcontrol_new ul_src_mux_control =
SOC_DAPM_ENUM("UL_SRC_MUX Select", ul_src_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum,
MT6359_AFE_ADDA6_UL_SRC_CON0_L,
ADDA6_UL_SDM_3_LEVEL_CTL_SFT,
ADDA6_UL_SDM_3_LEVEL_CTL_MASK,
ul_src_mux_map,
ul_src_mux_map_value);
static const struct snd_kcontrol_new ul2_src_mux_control =
SOC_DAPM_ENUM("UL_SRC_MUX Select", ul2_src_mux_map_enum);
static const char * const miso_mux_map[] = {
"UL1_CH1",
"UL1_CH2",
"UL2_CH1",
"UL2_CH2",
};
static int miso_mux_map_value[] = {
MISO_MUX_UL1_CH1,
MISO_MUX_UL1_CH2,
MISO_MUX_UL2_CH1,
MISO_MUX_UL2_CH2,
};
static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum,
MT6359_AFE_MTKAIF_MUX_CFG,
RG_ADDA_CH1_SEL_SFT,
RG_ADDA_CH1_SEL_MASK,
miso_mux_map,
miso_mux_map_value);
static const struct snd_kcontrol_new miso0_mux_control =
SOC_DAPM_ENUM("MISO_MUX Select", miso0_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum,
MT6359_AFE_MTKAIF_MUX_CFG,
RG_ADDA_CH2_SEL_SFT,
RG_ADDA_CH2_SEL_MASK,
miso_mux_map,
miso_mux_map_value);
static const struct snd_kcontrol_new miso1_mux_control =
SOC_DAPM_ENUM("MISO_MUX Select", miso1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum,
MT6359_AFE_MTKAIF_MUX_CFG,
RG_ADDA6_CH1_SEL_SFT,
RG_ADDA6_CH1_SEL_MASK,
miso_mux_map,
miso_mux_map_value);
static const struct snd_kcontrol_new miso2_mux_control =
SOC_DAPM_ENUM("MISO_MUX Select", miso2_mux_map_enum);
static const char * const dmic_mux_map[] = {
"DMIC_DATA0",
"DMIC_DATA1_L",
"DMIC_DATA1_L_1",
"DMIC_DATA1_R",
};
static int dmic_mux_map_value[] = {
DMIC_MUX_DMIC_DATA0,
DMIC_MUX_DMIC_DATA1_L,
DMIC_MUX_DMIC_DATA1_L_1,
DMIC_MUX_DMIC_DATA1_R,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum,
MT6359_AFE_MIC_ARRAY_CFG,
RG_DMIC_ADC1_SOURCE_SEL_SFT,
RG_DMIC_ADC1_SOURCE_SEL_MASK,
dmic_mux_map,
dmic_mux_map_value);
static const struct snd_kcontrol_new dmic0_mux_control =
SOC_DAPM_ENUM("DMIC_MUX Select", dmic0_mux_map_enum);
/* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */
static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum,
MT6359_AFE_MIC_ARRAY_CFG,
RG_DMIC_ADC3_SOURCE_SEL_SFT,
RG_DMIC_ADC3_SOURCE_SEL_MASK,
dmic_mux_map,
dmic_mux_map_value);
static const struct snd_kcontrol_new dmic1_mux_control =
SOC_DAPM_ENUM("DMIC_MUX Select", dmic1_mux_map_enum);
/* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */
static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum,
MT6359_AFE_MIC_ARRAY_CFG,
RG_DMIC_ADC2_SOURCE_SEL_SFT,
RG_DMIC_ADC2_SOURCE_SEL_MASK,
dmic_mux_map,
dmic_mux_map_value);
static const struct snd_kcontrol_new dmic2_mux_control =
SOC_DAPM_ENUM("DMIC_MUX Select", dmic2_mux_map_enum);
/* ADC L MUX */
static const char * const adc_left_mux_map[] = {
"Idle", "AIN0", "Left Preamplifier", "Idle_1"
};
static int adc_mux_map_value[] = {
ADC_MUX_IDLE,
ADC_MUX_AIN0,
ADC_MUX_PREAMPLIFIER,
ADC_MUX_IDLE1,
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
MT6359_AUDENC_ANA_CON0,
RG_AUDADCLINPUTSEL_SFT,
RG_AUDADCLINPUTSEL_MASK,
adc_left_mux_map,
adc_mux_map_value);
static const struct snd_kcontrol_new adc_left_mux_control =
SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
/* ADC R MUX */
static const char * const adc_right_mux_map[] = {
"Idle", "AIN0", "Right Preamplifier", "Idle_1"
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
MT6359_AUDENC_ANA_CON1,
RG_AUDADCRINPUTSEL_SFT,
RG_AUDADCRINPUTSEL_MASK,
adc_right_mux_map,
adc_mux_map_value);
static const struct snd_kcontrol_new adc_right_mux_control =
SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
/* ADC 3 MUX */
static const char * const adc_3_mux_map[] = {
"Idle", "AIN0", "Preamplifier", "Idle_1"
};
static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum,
MT6359_AUDENC_ANA_CON2,
RG_AUDADC3INPUTSEL_SFT,
RG_AUDADC3INPUTSEL_MASK,
adc_3_mux_map,
adc_mux_map_value);
static const struct snd_kcontrol_new adc_3_mux_control =
SOC_DAPM_ENUM("ADC 3 Select", adc_3_mux_map_enum);
static const char * const pga_l_mux_map[] = {
"None", "AIN0", "AIN1"
};
static int pga_l_mux_map_value[] = {
PGA_L_MUX_NONE,
PGA_L_MUX_AIN0,
PGA_L_MUX_AIN1
};
static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLINPUTSEL_SFT,
RG_AUDPREAMPLINPUTSEL_MASK,
pga_l_mux_map,
pga_l_mux_map_value);
static const struct snd_kcontrol_new pga_left_mux_control =
SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
static const char * const pga_r_mux_map[] = {
"None", "AIN2", "AIN3", "AIN0"
};
static int pga_r_mux_map_value[] = {
PGA_R_MUX_NONE,
PGA_R_MUX_AIN2,
PGA_R_MUX_AIN3,
PGA_R_MUX_AIN0
};
static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRINPUTSEL_SFT,
RG_AUDPREAMPRINPUTSEL_MASK,
pga_r_mux_map,
pga_r_mux_map_value);
static const struct snd_kcontrol_new pga_right_mux_control =
SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
static const char * const pga_3_mux_map[] = {
"None", "AIN3", "AIN2"
};
static int pga_3_mux_map_value[] = {
PGA_3_MUX_NONE,
PGA_3_MUX_AIN3,
PGA_3_MUX_AIN2
};
static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum,
MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3INPUTSEL_SFT,
RG_AUDPREAMP3INPUTSEL_MASK,
pga_3_mux_map,
pga_3_mux_map_value);
static const struct snd_kcontrol_new pga_3_mux_control =
SOC_DAPM_ENUM("PGA 3 Select", pga_3_mux_map_enum);
static int mt_sgen_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* sdm audio fifo clock power on */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
/* scrambler clock on enable */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
/* sdm power on */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
/* sdm fifo enable */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b);
regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0,
0xff3f,
0x0000);
regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1,
0xffff,
0x0001);
break;
case SND_SOC_DAPM_POST_PMD:
/* DL scrambler disabling sequence */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000);
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
break;
default:
break;
}
return 0;
}
static void mtk_hp_enable(struct mt6359_priv *priv)
{
if (priv->hp_hifi_mode) {
/* Set HP DR bias current optimization, 010: 6uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
DRBIAS_HP_MASK_SFT,
DRBIAS_6UA << DRBIAS_HP_SFT);
/* Set HP & ZCD bias current optimization */
/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_ZCD_MASK_SFT,
IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_HP_MASK_SFT,
IBIAS_5UA << IBIAS_HP_SFT);
} else {
/* Set HP DR bias current optimization, 001: 5uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
DRBIAS_HP_MASK_SFT,
DRBIAS_5UA << DRBIAS_HP_SFT);
/* Set HP & ZCD bias current optimization */
/* 00: ZCD: 3uA, HP/HS/LO: 4uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_ZCD_MASK_SFT,
IBIAS_ZCD_3UA << IBIAS_ZCD_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_HP_MASK_SFT,
IBIAS_4UA << IBIAS_HP_SFT);
}
/* HP damp circuit enable */
/* Enable HPRN/HPLN output 4K to VCM */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087);
/* HP Feedback Cap select 2'b00: 15pF */
/* for >= 96KHz sampling rate: 2'b01: 10.5pF */
if (priv->dl_rate[MT6359_AIF_1] >= 96000)
regmap_update_bits(priv->regmap,
MT6359_AUDDEC_ANA_CON4,
RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT,
0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT);
else
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000);
/* Set HPP/N STB enhance circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133);
/* Enable HP aux output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c);
/* Enable HP aux feedback loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c);
/* Enable HP aux CMFB loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00);
/* Enable HP driver bias circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0);
/* Enable HP driver core circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0);
/* Short HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc);
/* Increase HP input pair current to HPM step by step */
hp_in_pair_current(priv, true);
/* Enable HP main CMFB loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00);
/* Disable HP aux CMFB loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200);
/* Enable HP main output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff);
/* Enable HPR/L main output stage step by step */
hp_main_output_ramp(priv, true);
/* Reduce HP aux feedback loop gain */
hp_aux_feedback_loop_gain_ramp(priv, true);
/* Disable HP aux feedback loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
/* apply volume setting */
headset_volume_ramp(priv,
DL_GAIN_N_22DB,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
/* Disable HP aux output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
/* Unshort HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703);
usleep_range(100, 120);
/* Enable AUD_CLK */
mt6359_set_decoder_clk(priv, true);
/* Enable Audio DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff);
if (priv->hp_hifi_mode) {
/* Enable low-noise mode of DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201);
} else {
/* Disable low-noise mode of DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
}
usleep_range(100, 120);
/* Switch HPL MUX to audio DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff);
/* Switch HPR MUX to audio DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff);
/* Disable Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, false);
}
static void mtk_hp_disable(struct mt6359_priv *priv)
{
/* Pull-down HPL/R to AVSS28_AUD */
hp_pull_down(priv, true);
/* HPR/HPL mux to open */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x0f00, 0x0000);
/* Disable low-noise mode of DAC */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
0x0001, 0x0000);
/* Disable Audio DAC */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x000f, 0x0000);
/* Disable AUD_CLK */
mt6359_set_decoder_clk(priv, false);
/* Short HP main output to HP aux output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
/* Enable HP aux output stage */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
/* decrease HPL/R gain to normal gain step by step */
headset_volume_ramp(priv,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
DL_GAIN_N_22DB);
/* Enable HP aux feedback loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff);
/* Reduce HP aux feedback loop gain */
hp_aux_feedback_loop_gain_ramp(priv, false);
/* decrease HPR/L main output stage step by step */
hp_main_output_ramp(priv, false);
/* Disable HP main output stage */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0);
/* Enable HP aux CMFB loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01);
/* Disable HP main CMFB loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01);
/* Decrease HP input pair current to 2'b00 step by step */
hp_in_pair_current(priv, false);
/* Unshort HP main output to HP aux output stage */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
0x3 << 6, 0x0);
/* Disable HP driver core circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x3 << 4, 0x0);
/* Disable HP driver bias circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x3 << 6, 0x0);
/* Disable HP aux CMFB loop */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201);
/* Disable HP aux feedback loop */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
0x3 << 4, 0x0);
/* Disable HP aux output stage */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
0x3 << 2, 0x0);
}
static int mt_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
int device = DEVICE_HP;
dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
__func__, event, priv->dev_counter[device], mux);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
priv->dev_counter[device]++;
if (mux == HP_MUX_HP)
mtk_hp_enable(priv);
break;
case SND_SOC_DAPM_PRE_PMD:
priv->dev_counter[device]--;
if (mux == HP_MUX_HP)
mtk_hp_disable(priv);
break;
default:
break;
}
return 0;
}
static int mt_rcv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
__func__, event, dapm_kcontrol_get_value(w->kcontrols[0]));
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disable handset short-circuit protection */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
/* Set RCV DR bias current optimization, 010: 6uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
DRBIAS_HS_MASK_SFT,
DRBIAS_6UA << DRBIAS_HS_SFT);
/* Set RCV & ZCD bias current optimization */
/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_ZCD_MASK_SFT,
IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_HS_MASK_SFT,
IBIAS_5UA << IBIAS_HS_SFT);
/* Set HS STB enhance circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
/* Set HS output stage (3'b111 = 8x) */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
/* Enable HS driver bias circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
/* Enable HS driver core circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
/* Set HS gain to normal gain step by step */
regmap_write(priv->regmap, MT6359_ZCD_CON3,
priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]);
/* Enable AUD_CLK */
mt6359_set_decoder_clk(priv, true);
/* Enable Audio DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
/* Enable low-noise mode of DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
/* Switch HS MUX to audio DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
break;
case SND_SOC_DAPM_PRE_PMD:
/* HS mux to open */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT,
RCV_MUX_OPEN);
/* Disable Audio DAC */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x000f, 0x0000);
/* Disable AUD_CLK */
mt6359_set_decoder_clk(priv, false);
/* decrease HS gain to minimum gain step by step */
regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
/* Disable HS driver core circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0);
/* Disable HS driver bias circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
break;
default:
break;
}
return 0;
}
static int mt_lo_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
__func__, event, mux);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Disable handset short-circuit protection */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010);
/* Set LO DR bias current optimization, 010: 6uA */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
DRBIAS_LO_MASK_SFT,
DRBIAS_6UA << DRBIAS_LO_SFT);
/* Set LO & ZCD bias current optimization */
/* 01: ZCD: 4uA, HP/HS/LO: 5uA */
if (priv->dev_counter[DEVICE_HP] == 0)
regmap_update_bits(priv->regmap,
MT6359_AUDDEC_ANA_CON12,
IBIAS_ZCD_MASK_SFT,
IBIAS_ZCD_4UA << IBIAS_ZCD_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
IBIAS_LO_MASK_SFT,
IBIAS_5UA << IBIAS_LO_SFT);
/* Set LO STB enhance circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110);
/* Enable LO driver bias circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112);
/* Enable LO driver core circuits */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113);
/* Set LO gain to normal gain step by step */
regmap_write(priv->regmap, MT6359_ZCD_CON1,
priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
/* Enable AUD_CLK */
mt6359_set_decoder_clk(priv, true);
/* Switch LOL MUX to audio DAC */
if (mux == LO_MUX_L_DAC) {
if (priv->dev_counter[DEVICE_HP] > 0) {
dev_info(priv->dev, "%s(), can not enable DAC, hp count %d\n",
__func__, priv->dev_counter[DEVICE_HP]);
break;
}
/* Enable DACL and switch HP MUX to open*/
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3009);
/* Disable low-noise mode of DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
usleep_range(100, 120);
/* Switch LOL MUX to DACL */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0117);
} else if (mux == LO_MUX_3RD_DAC) {
/* Enable Audio DAC (3rd DAC) */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113);
/* Enable low-noise mode of DAC */
if (priv->dev_counter[DEVICE_HP] == 0)
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
/* Switch LOL MUX to audio 3rd DAC */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b);
}
break;
case SND_SOC_DAPM_PRE_PMD:
/* Switch LOL MUX to open */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT,
LO_MUX_OPEN);
/* Disable Audio DAC */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x000f, 0x0000);
if (mux == LO_MUX_L_DAC) {
/* Disable HP driver core circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x3 << 4, 0x0);
/* Disable HP driver bias circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
0x3 << 6, 0x0);
}
/* Disable AUD_CLK */
mt6359_set_decoder_clk(priv, false);
/* decrease LO gain to minimum gain step by step */
regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
/* Disable LO driver core circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0);
/* Disable LO driver bias circuits */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0);
break;
default:
break;
}
return 0;
}
static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* ADC CLK from CLKGEN (6.5MHz) */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKRSTB_MASK_SFT,
0x1 << RG_AUDADCCLKRSTB_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKSEL_MASK_SFT, 0x0);
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKGENMODE_MASK_SFT,
0x1 << RG_AUDADCCLKGENMODE_SFT);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKSOURCE_MASK_SFT, 0x0);
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKSEL_MASK_SFT, 0x0);
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKGENMODE_MASK_SFT, 0x0);
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
RG_AUDADCCLKRSTB_MASK_SFT, 0x0);
break;
default:
break;
}
return 0;
}
static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* DCC 50k CLK (from 26M) */
/* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */
regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
0xfff7, 0x2062);
regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
0xfff7, 0x2060);
regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
0xfff7, 0x2061);
regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
0xfff7, 0x2060);
regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
0xfff7, 0x2062);
break;
default:
break;
}
return 0;
}
static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];
dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
__func__, event, mic_type);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (mic_type) {
case MIC_TYPE_MUX_DCC_ECM_DIFF:
regmap_update_bits(priv->regmap,
MT6359_AUDENC_ANA_CON15,
0xff00, 0x7700);
break;
case MIC_TYPE_MUX_DCC_ECM_SINGLE:
regmap_update_bits(priv->regmap,
MT6359_AUDENC_ANA_CON15,
0xff00, 0x1100);
break;
default:
regmap_update_bits(priv->regmap,
MT6359_AUDENC_ANA_CON15,
0xff00, 0x0000);
break;
}
/* DMIC enable */
regmap_write(priv->regmap,
MT6359_AUDENC_ANA_CON14, 0x0004);
/* MISBIAS0 = 1P9V */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
RG_AUDMICBIAS0VREF_MASK_SFT,
MIC_BIAS_1P9 << RG_AUDMICBIAS0VREF_SFT);
/* normal power select */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
RG_AUDMICBIAS0LOWPEN_MASK_SFT,
0 << RG_AUDMICBIAS0LOWPEN_SFT);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable MICBIAS0, MISBIAS0 = 1P7V */
regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000);
break;
default:
break;
}
return 0;
}
static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];
dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
__func__, event, mic_type);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* MISBIAS1 = 2P6V */
if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
regmap_write(priv->regmap,
MT6359_AUDENC_ANA_CON16, 0x0160);
else
regmap_write(priv->regmap,
MT6359_AUDENC_ANA_CON16, 0x0060);
/* normal power select */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16,
RG_AUDMICBIAS1LOWPEN_MASK_SFT,
0 << RG_AUDMICBIAS1LOWPEN_SFT);
break;
default:
break;
}
return 0;
}
static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];
dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
__func__, event, mic_type);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
switch (mic_type) {
case MIC_TYPE_MUX_DCC_ECM_DIFF:
regmap_update_bits(priv->regmap,
MT6359_AUDENC_ANA_CON17,
0xff00, 0x7700);
break;
case MIC_TYPE_MUX_DCC_ECM_SINGLE:
regmap_update_bits(priv->regmap,
MT6359_AUDENC_ANA_CON17,
0xff00, 0x1100);
break;
default:
regmap_update_bits(priv->regmap,
MT6359_AUDENC_ANA_CON17,
0xff00, 0x0000);
break;
}
/* MISBIAS2 = 1P9V */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
RG_AUDMICBIAS2VREF_MASK_SFT,
MIC_BIAS_1P9 << RG_AUDMICBIAS2VREF_SFT);
/* normal power select */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
RG_AUDMICBIAS2LOWPEN_MASK_SFT,
0 << RG_AUDMICBIAS2LOWPEN_SFT);
break;
case SND_SOC_DAPM_POST_PMD:
/* Disable MICBIAS2, MISBIAS0 = 1P7V */
regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000);
break;
default:
break;
}
return 0;
}
static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt6359_mtkaif_tx_enable(priv);
break;
case SND_SOC_DAPM_POST_PMD:
mt6359_mtkaif_tx_disable(priv);
break;
default:
break;
}
return 0;
}
static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* UL dmic setting */
if (priv->dmic_one_wire_mode)
regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
0x0400);
else
regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
0x0080);
/* default one wire, 3.25M */
regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L,
0xfffc, 0x0000);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_write(priv->regmap,
MT6359_AFE_UL_SRC_CON0_H, 0x0000);
break;
default:
break;
}
return 0;
}
static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* default two wire, 3.25M */
regmap_write(priv->regmap,
MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080);
regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L,
0xfffc, 0x0000);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_write(priv->regmap,
MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000);
break;
default:
break;
}
return 0;
}
static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
usleep_range(100, 120);
/* Audio L preamplifier DCC precharge off */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
0x0);
break;
default:
break;
}
return 0;
}
static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
usleep_range(100, 120);
/* Audio R preamplifier DCC precharge off */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
0x0);
break;
default:
break;
}
return 0;
}
static int mt_adc_3_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
usleep_range(100, 120);
/* Audio R preamplifier DCC precharge off */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
0x0);
break;
default:
break;
}
return 0;
}
static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT;
return 0;
}
static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT;
return 0;
}
static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT;
return 0;
}
static int mt_pga_l_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
unsigned int mux_pga = priv->mux_select[MUX_PGA_L];
unsigned int mic_type;
switch (mux_pga) {
case PGA_L_MUX_AIN0:
mic_type = priv->mux_select[MUX_MIC_TYPE_0];
break;
case PGA_L_MUX_AIN1:
mic_type = priv->mux_select[MUX_MIC_TYPE_1];
break;
default:
dev_err(priv->dev, "%s(), invalid pga mux %d\n",
__func__, mux_pga);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (IS_DCC_BASE(mic_type)) {
/* Audio L preamplifier DCC precharge */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLDCPRECHARGE_MASK_SFT,
0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT);
}
break;
case SND_SOC_DAPM_POST_PMU:
/* set mic pga gain */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLGAIN_MASK_SFT,
mic_gain_l << RG_AUDPREAMPLGAIN_SFT);
if (IS_DCC_BASE(mic_type)) {
/* L preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLDCCEN_MASK_SFT,
0x1 << RG_AUDPREAMPLDCCEN_SFT);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* L preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLDCCEN_MASK_SFT,
0x0 << RG_AUDPREAMPLDCCEN_SFT);
break;
default:
break;
}
return 0;
}
static int mt_pga_r_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
unsigned int mux_pga = priv->mux_select[MUX_PGA_R];
unsigned int mic_type;
switch (mux_pga) {
case PGA_R_MUX_AIN0:
mic_type = priv->mux_select[MUX_MIC_TYPE_0];
break;
case PGA_R_MUX_AIN2:
case PGA_R_MUX_AIN3:
mic_type = priv->mux_select[MUX_MIC_TYPE_2];
break;
default:
dev_err(priv->dev, "%s(), invalid pga mux %d\n",
__func__, mux_pga);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (IS_DCC_BASE(mic_type)) {
/* Audio R preamplifier DCC precharge */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRDCPRECHARGE_MASK_SFT,
0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT);
}
break;
case SND_SOC_DAPM_POST_PMU:
/* set mic pga gain */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRGAIN_MASK_SFT,
mic_gain_r << RG_AUDPREAMPRGAIN_SFT);
if (IS_DCC_BASE(mic_type)) {
/* R preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRDCCEN_MASK_SFT,
0x1 << RG_AUDPREAMPRDCCEN_SFT);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* R preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRDCCEN_MASK_SFT,
0x0 << RG_AUDPREAMPRDCCEN_SFT);
break;
default:
break;
}
return 0;
}
static int mt_pga_3_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
unsigned int mux_pga = priv->mux_select[MUX_PGA_3];
unsigned int mic_type;
switch (mux_pga) {
case PGA_3_MUX_AIN2:
case PGA_3_MUX_AIN3:
mic_type = priv->mux_select[MUX_MIC_TYPE_2];
break;
default:
dev_err(priv->dev, "%s(), invalid pga mux %d\n",
__func__, mux_pga);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (IS_DCC_BASE(mic_type)) {
/* Audio 3 preamplifier DCC precharge */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3DCPRECHARGE_MASK_SFT,
0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT);
}
break;
case SND_SOC_DAPM_POST_PMU:
/* set mic pga gain */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3GAIN_MASK_SFT,
mic_gain_3 << RG_AUDPREAMP3GAIN_SFT);
if (IS_DCC_BASE(mic_type)) {
/* 3 preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3DCCEN_MASK_SFT,
0x1 << RG_AUDPREAMP3DCCEN_SFT);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* 3 preamplifier DCCEN */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3DCCEN_MASK_SFT,
0x0 << RG_AUDPREAMP3DCCEN_SFT);
break;
default:
break;
}
return 0;
}
/* It is based on hw's control sequenece to add some delay when PMU/PMD */
static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_PRE_PMD:
usleep_range(250, 270);
break;
default:
break;
}
return 0;
}
static int mt_delay_100_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
case SND_SOC_DAPM_PRE_PMD:
usleep_range(100, 120);
break;
default:
break;
}
return 0;
}
static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
hp_pull_down(priv, true);
break;
case SND_SOC_DAPM_POST_PMD:
hp_pull_down(priv, false);
break;
default:
break;
}
return 0;
}
static int mt_hp_mute_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Set HPR/HPL gain to -22dB */
regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG);
break;
case SND_SOC_DAPM_POST_PMD:
/* Set HPL/HPR gain to mute */
regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG);
break;
default:
break;
}
return 0;
}
static int mt_hp_damp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* Disable HP damping circuit & HPN 4K load */
/* reset CMFB PW level */
regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000);
break;
default:
break;
}
return 0;
}
static int mt_esd_resist_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Reduce ESD resistance of AU_REFN */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT,
0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT);
usleep_range(250, 270);
break;
case SND_SOC_DAPM_POST_PMD:
/* Increase ESD resistance of AU_REFN */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0);
break;
default:
break;
}
return 0;
}
static int mt_sdm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* sdm audio fifo clock power on */
regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
0xfffd, 0x0006);
/* scrambler clock on enable */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
/* sdm power on */
regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
0xfffd, 0x0003);
/* sdm fifo enable */
regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
0xfffd, 0x000B);
break;
case SND_SOC_DAPM_POST_PMD:
/* DL scrambler disabling sequence */
regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
0xfffd, 0x0000);
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
break;
default:
break;
}
return 0;
}
static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* sdm audio fifo clock power on */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006);
/* scrambler clock on enable */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1);
/* sdm power on */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003);
/* sdm fifo enable */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b);
break;
case SND_SOC_DAPM_POST_PMD:
/* DL scrambler disabling sequence */
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000);
regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0);
break;
default:
break;
}
return 0;
}
static int mt_ncp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
break;
default:
break;
}
return 0;
}
/* DAPM Widgets */
static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = {
/* Global Supply*/
SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
MT6359_DCXO_CW12,
RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
MT6359_AUDDEC_ANA_CON13,
RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
MT6359_AUDENC_ANA_CON23,
RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
MT6359_AUD_TOP_CKPDN_CON0,
RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
MT6359_AUD_TOP_CKPDN_CON0,
RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
MT6359_AUD_TOP_CKPDN_CON0,
RG_AUD_CK_PDN_SFT, 1, mt_delay_250_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
MT6359_AUD_TOP_CKPDN_CON0,
RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
SND_SOC_DAPM_REGULATOR_SUPPLY("vaud18", 0, 0),
/* Digital Clock */
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
MT6359_AUDIO_TOP_CON0,
PDN_AFE_CTL_SFT, 1,
mt_delay_250_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PDN_DAC_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PDN_ADC_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADDA6_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
MT6359_AUDIO_TOP_CON0,
PDN_RESERVED_SFT, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("SDM", SUPPLY_SEQ_DL_SDM,
SND_SOC_NOPM, 0, 0,
mt_sdm_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("SDM_3RD", SUPPLY_SEQ_DL_SDM,
SND_SOC_NOPM, 0, 0,
mt_sdm_3rd_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* ch123 share SDM FIFO CLK */
SND_SOC_DAPM_SUPPLY_S("SDM_FIFO_CLK", SUPPLY_SEQ_DL_SDM_FIFO_CLK,
MT6359_AFUNC_AUD_CON2,
CCI_AFIFO_CLK_PWDB_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("NCP", SUPPLY_SEQ_DL_NCP,
MT6359_AFE_NCP_CFG0,
RG_NCP_ON_SFT, 0,
mt_ncp_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_1_2", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DL Digital Clock CH_3", SND_SOC_NOPM,
0, 0, NULL, 0),
/* AFE ON */
SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
NULL, 0),
/* AIF Rx*/
SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY_S("AFE_DL_SRC", SUPPLY_SEQ_DL_SRC,
MT6359_AFE_DL_SRC2_CON0_L,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
NULL, 0),
/* DL Supply */
SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ESD_RESIST", SUPPLY_SEQ_DL_ESD_RESIST,
SND_SOC_NOPM,
0, 0,
mt_esd_resist_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("LDO", SUPPLY_SEQ_DL_LDO,
MT6359_AUDDEC_ANA_CON14,
RG_LCLDO_DEC_EN_VA32_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("LDO_REMOTE", SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
MT6359_AUDDEC_ANA_CON14,
RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("NV_REGULATOR", SUPPLY_SEQ_DL_NV,
MT6359_AUDDEC_ANA_CON14,
RG_NVREG_EN_VAUDP32_SFT, 0,
mt_delay_100_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY_S("IBIST", SUPPLY_SEQ_DL_IBIST,
MT6359_AUDDEC_ANA_CON12,
RG_AUDIBIASPWRDN_VAUDP32_SFT, 1,
NULL, 0),
/* DAC */
SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0),
/* Headphone */
SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0,
&hp_in_mux_control,
mt_hp_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("HP_Supply", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("HP_PULL_DOWN", SUPPLY_SEQ_HP_PULL_DOWN,
SND_SOC_NOPM,
0, 0,
mt_hp_pull_down_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("HP_MUTE", SUPPLY_SEQ_HP_MUTE,
SND_SOC_NOPM,
0, 0,
mt_hp_mute_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("HP_DAMP", SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
SND_SOC_NOPM,
0, 0,
mt_hp_damp_event,
SND_SOC_DAPM_POST_PMD),
/* Receiver */
SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
&rcv_in_mux_control,
mt_rcv_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
/* LOL */
SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
&lo_in_mux_control,
mt_lo_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
/* Outputs */
SND_SOC_DAPM_OUTPUT("Receiver"),
SND_SOC_DAPM_OUTPUT("Headphone L"),
SND_SOC_DAPM_OUTPUT("Headphone R"),
SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
SND_SOC_DAPM_OUTPUT("LINEOUT L"),
/* SGEN */
SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0,
SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6359_AFE_SGEN_CFG0,
SGEN_MUTE_SW_CTL_SFT, 1,
mt_sgen_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6359_AFE_DL_SRC2_CON0_L,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("SGEN DL"),
/* Uplinks */
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY_S("ADC_CLKGEN", SUPPLY_SEQ_ADC_CLKGEN,
SND_SOC_NOPM, 0, 0,
mt_adc_clk_gen_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY_S("DCC_CLK", SUPPLY_SEQ_DCC_CLK,
SND_SOC_NOPM, 0, 0,
mt_dcc_clk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Uplinks MUX */
SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
&aif_out_mux_control),
SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0,
&aif2_out_mux_control),
SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("MTKAIF_TX", SUPPLY_SEQ_UL_MTKAIF,
SND_SOC_NOPM, 0, 0,
mt_mtkaif_tx_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("UL_SRC", SUPPLY_SEQ_UL_SRC,
MT6359_AFE_UL_SRC_CON0_L,
UL_SRC_ON_TMP_CTL_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("UL_SRC_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
SND_SOC_NOPM, 0, 0,
mt_ul_src_dmic_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("UL_SRC_34", SUPPLY_SEQ_UL_SRC,
MT6359_AFE_ADDA6_UL_SRC_CON0_L,
ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("UL_SRC_34_DMIC", SUPPLY_SEQ_UL_SRC_DMIC,
SND_SOC_NOPM, 0, 0,
mt_ul_src_34_dmic_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control),
SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control),
SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control),
SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
&ul_src_mux_control),
SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0,
&ul2_src_mux_control),
SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control),
SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control),
SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control),
SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0,
&adc_left_mux_control, NULL, 0),
SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0,
&adc_right_mux_control, NULL, 0),
SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0,
&adc_3_mux_control, NULL, 0),
SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY_S("ADC_L_EN", SUPPLY_SEQ_UL_ADC,
MT6359_AUDENC_ANA_CON0,
RG_AUDADCLPWRUP_SFT, 0,
mt_adc_l_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY_S("ADC_R_EN", SUPPLY_SEQ_UL_ADC,
MT6359_AUDENC_ANA_CON1,
RG_AUDADCRPWRUP_SFT, 0,
mt_adc_r_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY_S("ADC_3_EN", SUPPLY_SEQ_UL_ADC,
MT6359_AUDENC_ANA_CON2,
RG_AUDADC3PWRUP_SFT, 0,
mt_adc_3_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0,
&pga_left_mux_control,
mt_pga_l_mux_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0,
&pga_right_mux_control,
mt_pga_r_mux_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0,
&pga_3_mux_control,
mt_pga_3_mux_event,
SND_SOC_DAPM_WILL_PMU),
SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("PGA_L_EN", SUPPLY_SEQ_UL_PGA,
MT6359_AUDENC_ANA_CON0,
RG_AUDPREAMPLON_SFT, 0,
mt_pga_l_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("PGA_R_EN", SUPPLY_SEQ_UL_PGA,
MT6359_AUDENC_ANA_CON1,
RG_AUDPREAMPRON_SFT, 0,
mt_pga_r_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("PGA_3_EN", SUPPLY_SEQ_UL_PGA,
MT6359_AUDENC_ANA_CON2,
RG_AUDPREAMP3ON_SFT, 0,
mt_pga_3_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
/* UL input */
SND_SOC_DAPM_INPUT("AIN0"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN0_DMIC"),
SND_SOC_DAPM_INPUT("AIN2_DMIC"),
SND_SOC_DAPM_INPUT("AIN3_DMIC"),
/* mic bias */
SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_0", SUPPLY_SEQ_MIC_BIAS,
MT6359_AUDENC_ANA_CON15,
RG_AUDPWDBMICBIAS0_SFT, 0,
mt_mic_bias_0_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_1", SUPPLY_SEQ_MIC_BIAS,
MT6359_AUDENC_ANA_CON16,
RG_AUDPWDBMICBIAS1_SFT, 0,
mt_mic_bias_1_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("MIC_BIAS_2", SUPPLY_SEQ_MIC_BIAS,
MT6359_AUDENC_ANA_CON17,
RG_AUDPWDBMICBIAS2_SFT, 0,
mt_mic_bias_2_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* dmic */
SND_SOC_DAPM_SUPPLY_S("DMIC_0", SUPPLY_SEQ_DMIC,
MT6359_AUDENC_ANA_CON13,
RG_AUDDIGMICEN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC_1", SUPPLY_SEQ_DMIC,
MT6359_AUDENC_ANA_CON14,
RG_AUDDIGMIC1EN_SFT, 0,
NULL, 0),
};
static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
return 1;
else
return 0;
}
static const struct snd_soc_dapm_route mt6359_dapm_routes[] = {
/* Capture */
{"AIFTX_Supply", NULL, "CLK_BUF"},
{"AIFTX_Supply", NULL, "vaud18"},
{"AIFTX_Supply", NULL, "AUDGLB"},
{"AIFTX_Supply", NULL, "CLKSQ Audio"},
{"AIFTX_Supply", NULL, "AUD_CK"},
{"AIFTX_Supply", NULL, "AUDIF_CK"},
{"AIFTX_Supply", NULL, "AUDIO_TOP_AFE_CTL"},
{"AIFTX_Supply", NULL, "AUDIO_TOP_PWR_CLK"},
{"AIFTX_Supply", NULL, "AUDIO_TOP_PDN_RESERVED"},
{"AIFTX_Supply", NULL, "AUDIO_TOP_I2S_DL"},
/*
* *_ADC_CTL should enable only if UL_SRC in use,
* but dm ck may be needed even UL_SRC_x not in use
*/
{"AIFTX_Supply", NULL, "AUDIO_TOP_ADC_CTL"},
{"AIFTX_Supply", NULL, "AUDIO_TOP_ADDA6_ADC_CTL"},
{"AIFTX_Supply", NULL, "AFE_ON"},
/* ul ch 12 */
{"AIF1TX", NULL, "AIF Out Mux"},
{"AIF1TX", NULL, "AIFTX_Supply"},
{"AIF1TX", NULL, "MTKAIF_TX"},
{"AIF2TX", NULL, "AIF2 Out Mux"},
{"AIF2TX", NULL, "AIFTX_Supply"},
{"AIF2TX", NULL, "MTKAIF_TX"},
{"AIF Out Mux", "Normal Path", "MISO0_MUX"},
{"AIF Out Mux", "Normal Path", "MISO1_MUX"},
{"AIF2 Out Mux", "Normal Path", "MISO2_MUX"},
{"MISO0_MUX", "UL1_CH1", "UL_SRC_MUX"},
{"MISO0_MUX", "UL1_CH2", "UL_SRC_MUX"},
{"MISO0_MUX", "UL2_CH1", "UL2_SRC_MUX"},
{"MISO0_MUX", "UL2_CH2", "UL2_SRC_MUX"},
{"MISO1_MUX", "UL1_CH1", "UL_SRC_MUX"},
{"MISO1_MUX", "UL1_CH2", "UL_SRC_MUX"},
{"MISO1_MUX", "UL2_CH1", "UL2_SRC_MUX"},
{"MISO1_MUX", "UL2_CH2", "UL2_SRC_MUX"},
{"MISO2_MUX", "UL1_CH1", "UL_SRC_MUX"},
{"MISO2_MUX", "UL1_CH2", "UL_SRC_MUX"},
{"MISO2_MUX", "UL2_CH1", "UL2_SRC_MUX"},
{"MISO2_MUX", "UL2_CH2", "UL2_SRC_MUX"},
{"MISO0_MUX", NULL, "UL_SRC"},
{"MISO1_MUX", NULL, "UL_SRC"},
{"MISO2_MUX", NULL, "UL_SRC_34"},
{"UL_SRC_MUX", "AMIC", "ADC_L"},
{"UL_SRC_MUX", "AMIC", "ADC_R"},
{"UL_SRC_MUX", "DMIC", "DMIC0_MUX"},
{"UL_SRC_MUX", "DMIC", "DMIC1_MUX"},
{"UL_SRC_MUX", NULL, "UL_SRC"},
{"UL2_SRC_MUX", "AMIC", "ADC_3"},
{"UL2_SRC_MUX", "DMIC", "DMIC2_MUX"},
{"UL2_SRC_MUX", NULL, "UL_SRC_34"},
{"DMIC0_MUX", "DMIC_DATA0", "AIN0_DMIC"},
{"DMIC0_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
{"DMIC0_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
{"DMIC0_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
{"DMIC1_MUX", "DMIC_DATA0", "AIN0_DMIC"},
{"DMIC1_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
{"DMIC1_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
{"DMIC1_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
{"DMIC2_MUX", "DMIC_DATA0", "AIN0_DMIC"},
{"DMIC2_MUX", "DMIC_DATA1_L", "AIN2_DMIC"},
{"DMIC2_MUX", "DMIC_DATA1_L_1", "AIN2_DMIC"},
{"DMIC2_MUX", "DMIC_DATA1_R", "AIN3_DMIC"},
{"DMIC0_MUX", NULL, "UL_SRC_DMIC"},
{"DMIC1_MUX", NULL, "UL_SRC_DMIC"},
{"DMIC2_MUX", NULL, "UL_SRC_34_DMIC"},
{"AIN0_DMIC", NULL, "DMIC_0"},
{"AIN2_DMIC", NULL, "DMIC_1"},
{"AIN3_DMIC", NULL, "DMIC_1"},
{"AIN0_DMIC", NULL, "MIC_BIAS_0"},
{"AIN2_DMIC", NULL, "MIC_BIAS_2"},
{"AIN3_DMIC", NULL, "MIC_BIAS_2"},
/* adc */
{"ADC_L", NULL, "ADC_L_Mux"},
{"ADC_L", NULL, "ADC_CLKGEN"},
{"ADC_L", NULL, "ADC_L_EN"},
{"ADC_R", NULL, "ADC_R_Mux"},
{"ADC_R", NULL, "ADC_CLKGEN"},
{"ADC_R", NULL, "ADC_R_EN"},
/*
* amic fifo ch1/2 clk from ADC_L,
* enable ADC_L even use ADC_R only
*/
{"ADC_R", NULL, "ADC_L_EN"},
{"ADC_3", NULL, "ADC_3_Mux"},
{"ADC_3", NULL, "ADC_CLKGEN"},
{"ADC_3", NULL, "ADC_3_EN"},
{"ADC_L_Mux", "Left Preamplifier", "PGA_L"},
{"ADC_R_Mux", "Right Preamplifier", "PGA_R"},
{"ADC_3_Mux", "Preamplifier", "PGA_3"},
{"PGA_L", NULL, "PGA_L_Mux"},
{"PGA_L", NULL, "PGA_L_EN"},
{"PGA_R", NULL, "PGA_R_Mux"},
{"PGA_R", NULL, "PGA_R_EN"},
{"PGA_3", NULL, "PGA_3_Mux"},
{"PGA_3", NULL, "PGA_3_EN"},
{"PGA_L", NULL, "DCC_CLK", mt_dcc_clk_connect},
{"PGA_R", NULL, "DCC_CLK", mt_dcc_clk_connect},
{"PGA_3", NULL, "DCC_CLK", mt_dcc_clk_connect},
{"PGA_L_Mux", "AIN0", "AIN0"},
{"PGA_L_Mux", "AIN1", "AIN1"},
{"PGA_R_Mux", "AIN0", "AIN0"},
{"PGA_R_Mux", "AIN2", "AIN2"},
{"PGA_R_Mux", "AIN3", "AIN3"},
{"PGA_3_Mux", "AIN2", "AIN2"},
{"PGA_3_Mux", "AIN3", "AIN3"},
{"AIN0", NULL, "MIC_BIAS_0"},
{"AIN1", NULL, "MIC_BIAS_1"},
{"AIN2", NULL, "MIC_BIAS_0"},
{"AIN2", NULL, "MIC_BIAS_2"},
{"AIN3", NULL, "MIC_BIAS_2"},
/* DL Supply */
{"DL Power Supply", NULL, "CLK_BUF"},
{"DL Power Supply", NULL, "vaud18"},
{"DL Power Supply", NULL, "AUDGLB"},
{"DL Power Supply", NULL, "CLKSQ Audio"},
{"DL Power Supply", NULL, "AUDNCP_CK"},
{"DL Power Supply", NULL, "ZCD13M_CK"},
{"DL Power Supply", NULL, "AUD_CK"},
{"DL Power Supply", NULL, "AUDIF_CK"},
{"DL Power Supply", NULL, "ESD_RESIST"},
{"DL Power Supply", NULL, "LDO"},
{"DL Power Supply", NULL, "LDO_REMOTE"},
{"DL Power Supply", NULL, "NV_REGULATOR"},
{"DL Power Supply", NULL, "IBIST"},
/* DL Digital Supply */
{"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
{"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
{"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
{"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
{"DL Digital Clock", NULL, "SDM_FIFO_CLK"},
{"DL Digital Clock", NULL, "NCP"},
{"DL Digital Clock", NULL, "AFE_ON"},
{"DL Digital Clock", NULL, "AFE_DL_SRC"},
{"DL Digital Clock CH_1_2", NULL, "DL Digital Clock"},
{"DL Digital Clock CH_1_2", NULL, "SDM"},
{"DL Digital Clock CH_3", NULL, "DL Digital Clock"},
{"DL Digital Clock CH_3", NULL, "SDM_3RD"},
{"AIF_RX", NULL, "DL Digital Clock CH_1_2"},
{"AIF2_RX", NULL, "DL Digital Clock CH_3"},
/* DL Path */
{"DAC In Mux", "Normal Path", "AIF_RX"},
{"DAC In Mux", "Sgen", "SGEN DL"},
{"SGEN DL", NULL, "SGEN DL SRC"},
{"SGEN DL", NULL, "SGEN MUTE"},
{"SGEN DL", NULL, "SGEN DL Enable"},
{"SGEN DL", NULL, "DL Digital Clock CH_1_2"},
{"SGEN DL", NULL, "DL Digital Clock CH_3"},
{"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
{"DACL", NULL, "DAC In Mux"},
{"DACL", NULL, "DL Power Supply"},
{"DACR", NULL, "DAC In Mux"},
{"DACR", NULL, "DL Power Supply"},
/* DAC 3RD */
{"DAC In Mux", "Normal Path", "AIF2_RX"},
{"DAC_3RD", NULL, "DAC In Mux"},
{"DAC_3RD", NULL, "DL Power Supply"},
/* Lineout Path */
{"LOL Mux", "Playback", "DAC_3RD"},
{"LOL Mux", "Playback_L_DAC", "DACL"},
{"LINEOUT L", NULL, "LOL Mux"},
/* Headphone Path */
{"HP_Supply", NULL, "HP_PULL_DOWN"},
{"HP_Supply", NULL, "HP_MUTE"},
{"HP_Supply", NULL, "HP_DAMP"},
{"HP Mux", NULL, "HP_Supply"},
{"HP Mux", "Audio Playback", "DACL"},
{"HP Mux", "Audio Playback", "DACR"},
{"HP Mux", "HP Impedance", "DACL"},
{"HP Mux", "HP Impedance", "DACR"},
{"HP Mux", "LoudSPK Playback", "DACL"},
{"HP Mux", "LoudSPK Playback", "DACR"},
{"Headphone L", NULL, "HP Mux"},
{"Headphone R", NULL, "HP Mux"},
{"Headphone L Ext Spk Amp", NULL, "HP Mux"},
{"Headphone R Ext Spk Amp", NULL, "HP Mux"},
/* Receiver Path */
{"RCV Mux", "Voice Playback", "DACL"},
{"Receiver", NULL, "RCV Mux"},
};
static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *cmpnt = dai->component;
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
unsigned int rate = params_rate(params);
int id = dai->id;
dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n",
__func__, id, substream->stream, rate, substream->number);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
priv->dl_rate[id] = rate;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
priv->ul_rate[id] = rate;
return 0;
}
static int mt6359_codec_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *cmpnt = dai->component;
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mt6359_set_playback_gpio(priv);
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mt6359_set_capture_gpio(priv);
return 0;
}
static void mt6359_codec_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *cmpnt = dai->component;
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mt6359_reset_playback_gpio(priv);
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mt6359_reset_capture_gpio(priv);
}
static const struct snd_soc_dai_ops mt6359_codec_dai_ops = {
.hw_params = mt6359_codec_dai_hw_params,
.startup = mt6359_codec_dai_startup,
.shutdown = mt6359_codec_dai_shutdown,
};
#define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
static struct snd_soc_dai_driver mt6359_dai_driver[] = {
{
.id = MT6359_AIF_1,
.name = "mt6359-snd-codec-aif1",
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = MT6359_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = MT6359_FORMATS,
},
.ops = &mt6359_codec_dai_ops,
},
{
.id = MT6359_AIF_2,
.name = "mt6359-snd-codec-aif2",
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = MT6359_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000,
.formats = MT6359_FORMATS,
},
.ops = &mt6359_codec_dai_ops,
},
};
static int mt6359_codec_init_reg(struct snd_soc_component *cmpnt)
{
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
/* enable clk buf */
regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
0x1 << RG_XO_AUDIO_EN_M_SFT,
0x1 << RG_XO_AUDIO_EN_M_SFT);
/* set those not controlled by dapm widget */
/* audio clk source from internal dcxo */
regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
0x0);
/* Disable HeadphoneL/HeadphoneR short circuit protection */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT,
0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT);
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT,
0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT);
/* Disable voice short circuit protection */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT,
0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT);
/* disable LO buffer left short circuit protection */
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT,
0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT);
/* set gpio */
mt6359_set_gpio_smt(priv);
mt6359_set_gpio_driving(priv);
mt6359_reset_playback_gpio(priv);
mt6359_reset_capture_gpio(priv);
/* hp hifi mode, default normal mode */
priv->hp_hifi_mode = 0;
/* Disable AUD_ZCD */
zcd_disable(priv);
/* disable clk buf */
regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
0x1 << RG_XO_AUDIO_EN_M_SFT,
0x0 << RG_XO_AUDIO_EN_M_SFT);
return 0;
}
static int mt6359_codec_probe(struct snd_soc_component *cmpnt)
{
struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
snd_soc_component_init_regmap(cmpnt, priv->regmap);
return mt6359_codec_init_reg(cmpnt);
}
static void mt6359_codec_remove(struct snd_soc_component *cmpnt)
{
cmpnt->regmap = NULL;
}
static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
static const struct snd_kcontrol_new mt6359_snd_controls[] = {
/* dl pga gain */
SOC_DOUBLE_EXT_TLV("Headset Volume",
MT6359_ZCD_CON2, 0, 7, 0x12, 0,
mt6359_get_playback_volsw, mt6359_put_volsw,
playback_tlv),
SOC_DOUBLE_EXT_TLV("Lineout Volume",
MT6359_ZCD_CON1, 0, 7, 0x12, 0,
mt6359_get_playback_volsw, mt6359_put_volsw,
playback_tlv),
SOC_SINGLE_EXT_TLV("Handset Volume",
MT6359_ZCD_CON3, 0, 0x12, 0,
mt6359_get_playback_volsw, mt6359_put_volsw,
playback_tlv),
/* ul pga gain */
SOC_SINGLE_EXT_TLV("PGA1 Volume",
MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0,
snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
SOC_SINGLE_EXT_TLV("PGA2 Volume",
MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0,
snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
SOC_SINGLE_EXT_TLV("PGA3 Volume",
MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0,
snd_soc_get_volsw, mt6359_put_volsw, capture_tlv),
};
static const struct snd_soc_component_driver mt6359_soc_component_driver = {
.name = CODEC_MT6359_NAME,
.probe = mt6359_codec_probe,
.remove = mt6359_codec_remove,
.controls = mt6359_snd_controls,
.num_controls = ARRAY_SIZE(mt6359_snd_controls),
.dapm_widgets = mt6359_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt6359_dapm_widgets),
.dapm_routes = mt6359_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt6359_dapm_routes),
.endianness = 1,
};
static int mt6359_parse_dt(struct mt6359_priv *priv)
{
int ret;
struct device *dev = priv->dev;
struct device_node *np;
np = of_get_child_by_name(dev->parent->of_node, "mt6359codec");
if (!np)
return -EINVAL;
ret = of_property_read_u32(np, "mediatek,dmic-mode",
&priv->dmic_one_wire_mode);
if (ret) {
dev_info(priv->dev,
"%s() failed to read dmic-mode, use default (0)\n",
__func__);
priv->dmic_one_wire_mode = 0;
}
ret = of_property_read_u32(np, "mediatek,mic-type-0",
&priv->mux_select[MUX_MIC_TYPE_0]);
if (ret) {
dev_info(priv->dev,
"%s() failed to read mic-type-0, use default (%d)\n",
__func__, MIC_TYPE_MUX_IDLE);
priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE;
}
ret = of_property_read_u32(np, "mediatek,mic-type-1",
&priv->mux_select[MUX_MIC_TYPE_1]);
if (ret) {
dev_info(priv->dev,
"%s() failed to read mic-type-1, use default (%d)\n",
__func__, MIC_TYPE_MUX_IDLE);
priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE;
}
ret = of_property_read_u32(np, "mediatek,mic-type-2",
&priv->mux_select[MUX_MIC_TYPE_2]);
of_node_put(np);
if (ret) {
dev_info(priv->dev,
"%s() failed to read mic-type-2, use default (%d)\n",
__func__, MIC_TYPE_MUX_IDLE);
priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE;
}
return 0;
}
static int mt6359_platform_driver_probe(struct platform_device *pdev)
{
struct mt6359_priv *priv;
int ret;
struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
dev_dbg(&pdev->dev, "%s(), dev name %s\n",
__func__, dev_name(&pdev->dev));
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->regmap = mt6397->regmap;
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
dev_set_drvdata(&pdev->dev, priv);
priv->dev = &pdev->dev;
ret = mt6359_parse_dt(priv);
if (ret) {
dev_warn(&pdev->dev, "%s() failed to parse dts\n", __func__);
return ret;
}
return devm_snd_soc_register_component(&pdev->dev,
&mt6359_soc_component_driver,
mt6359_dai_driver,
ARRAY_SIZE(mt6359_dai_driver));
}
static struct platform_driver mt6359_platform_driver = {
.driver = {
.name = "mt6359-sound",
},
.probe = mt6359_platform_driver_probe,
};
module_platform_driver(mt6359_platform_driver)
/* Module information */
MODULE_DESCRIPTION("MT6359 ALSA SoC codec driver");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_AUTHOR("Eason Yen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/mt6359.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ALSA SoC CQ0093 Voice Codec Driver for DaVinci platforms
*
* Copyright (C) 2010 Texas Instruments, Inc
*
* Author: Miguel Aguilar <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/mfd/davinci_voicecodec.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
static const struct snd_kcontrol_new cq93vc_snd_controls[] = {
SOC_SINGLE("PGA Capture Volume", DAVINCI_VC_REG05, 0, 0x03, 0),
SOC_SINGLE("Mono DAC Playback Volume", DAVINCI_VC_REG09, 0, 0x3f, 0),
};
static int cq93vc_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u8 reg;
if (mute)
reg = DAVINCI_VC_REG09_MUTE;
else
reg = 0;
snd_soc_component_update_bits(component, DAVINCI_VC_REG09, DAVINCI_VC_REG09_MUTE,
reg);
return 0;
}
static int cq93vc_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
switch (freq) {
case 22579200:
case 27000000:
case 33868800:
return 0;
}
return -EINVAL;
}
static int cq93vc_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_write(component, DAVINCI_VC_REG12,
DAVINCI_VC_REG12_POWER_ALL_ON);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_component_write(component, DAVINCI_VC_REG12,
DAVINCI_VC_REG12_POWER_ALL_OFF);
break;
case SND_SOC_BIAS_OFF:
/* force all power off */
snd_soc_component_write(component, DAVINCI_VC_REG12,
DAVINCI_VC_REG12_POWER_ALL_OFF);
break;
}
return 0;
}
#define CQ93VC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
#define CQ93VC_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE)
static const struct snd_soc_dai_ops cq93vc_dai_ops = {
.mute_stream = cq93vc_mute,
.set_sysclk = cq93vc_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cq93vc_dai = {
.name = "cq93vc-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CQ93VC_RATES,
.formats = CQ93VC_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = CQ93VC_RATES,
.formats = CQ93VC_FORMATS,},
.ops = &cq93vc_dai_ops,
};
static int cq93vc_probe(struct snd_soc_component *component)
{
struct davinci_vc *davinci_vc = component->dev->platform_data;
snd_soc_component_init_regmap(component, davinci_vc->regmap);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cq93vc = {
.set_bias_level = cq93vc_set_bias_level,
.probe = cq93vc_probe,
.controls = cq93vc_snd_controls,
.num_controls = ARRAY_SIZE(cq93vc_snd_controls),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int cq93vc_platform_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&soc_component_dev_cq93vc, &cq93vc_dai, 1);
}
static struct platform_driver cq93vc_codec_driver = {
.driver = {
.name = "cq93vc-codec",
},
.probe = cq93vc_platform_probe,
};
module_platform_driver(cq93vc_codec_driver);
MODULE_DESCRIPTION("Texas Instruments DaVinci ASoC CQ0093 Voice Codec Driver");
MODULE_AUTHOR("Miguel Aguilar");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cq93vc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max9877.c -- amp driver for max9877
*
* Copyright (C) 2009 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max9877.h"
static const struct reg_default max9877_regs[] = {
{ 0, 0x40 },
{ 1, 0x00 },
{ 2, 0x00 },
{ 3, 0x00 },
{ 4, 0x49 },
};
static const DECLARE_TLV_DB_RANGE(max9877_pgain_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 900, 0),
2, 2, TLV_DB_SCALE_ITEM(2000, 0, 0)
);
static const DECLARE_TLV_DB_RANGE(max9877_output_tlv,
0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
);
static const char *max9877_out_mode[] = {
"INA -> SPK",
"INA -> HP",
"INA -> SPK and HP",
"INB -> SPK",
"INB -> HP",
"INB -> SPK and HP",
"INA + INB -> SPK",
"INA + INB -> HP",
"INA + INB -> SPK and HP",
};
static const char *max9877_osc_mode[] = {
"1176KHz",
"1100KHz",
"700KHz",
};
static const struct soc_enum max9877_enum[] = {
SOC_ENUM_SINGLE(MAX9877_OUTPUT_MODE, 0, ARRAY_SIZE(max9877_out_mode),
max9877_out_mode),
SOC_ENUM_SINGLE(MAX9877_OUTPUT_MODE, MAX9877_OSC_OFFSET,
ARRAY_SIZE(max9877_osc_mode), max9877_osc_mode),
};
static const struct snd_kcontrol_new max9877_controls[] = {
SOC_SINGLE_TLV("MAX9877 PGAINA Playback Volume",
MAX9877_INPUT_MODE, 0, 2, 0, max9877_pgain_tlv),
SOC_SINGLE_TLV("MAX9877 PGAINB Playback Volume",
MAX9877_INPUT_MODE, 2, 2, 0, max9877_pgain_tlv),
SOC_SINGLE_TLV("MAX9877 Amp Speaker Playback Volume",
MAX9877_SPK_VOLUME, 0, 31, 0, max9877_output_tlv),
SOC_DOUBLE_R_TLV("MAX9877 Amp HP Playback Volume",
MAX9877_HPL_VOLUME, MAX9877_HPR_VOLUME, 0, 31, 0,
max9877_output_tlv),
SOC_SINGLE("MAX9877 INB Stereo Switch",
MAX9877_INPUT_MODE, 4, 1, 1),
SOC_SINGLE("MAX9877 INA Stereo Switch",
MAX9877_INPUT_MODE, 5, 1, 1),
SOC_SINGLE("MAX9877 Zero-crossing detection Switch",
MAX9877_INPUT_MODE, 6, 1, 0),
SOC_SINGLE("MAX9877 Bypass Mode Switch",
MAX9877_OUTPUT_MODE, 6, 1, 0),
SOC_ENUM("MAX9877 Output Mode", max9877_enum[0]),
SOC_ENUM("MAX9877 Oscillator Mode", max9877_enum[1]),
};
static const struct snd_soc_dapm_widget max9877_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("INA1"),
SND_SOC_DAPM_INPUT("INA2"),
SND_SOC_DAPM_INPUT("INB1"),
SND_SOC_DAPM_INPUT("INB2"),
SND_SOC_DAPM_INPUT("RXIN+"),
SND_SOC_DAPM_INPUT("RXIN-"),
SND_SOC_DAPM_PGA("SHDN", MAX9877_OUTPUT_MODE, 7, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("OUT+"),
SND_SOC_DAPM_OUTPUT("OUT-"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
};
static const struct snd_soc_dapm_route max9877_dapm_routes[] = {
{ "SHDN", NULL, "INA1" },
{ "SHDN", NULL, "INA2" },
{ "SHDN", NULL, "INB1" },
{ "SHDN", NULL, "INB2" },
{ "OUT+", NULL, "RXIN+" },
{ "OUT+", NULL, "SHDN" },
{ "OUT-", NULL, "SHDN" },
{ "OUT-", NULL, "RXIN-" },
{ "HPL", NULL, "SHDN" },
{ "HPR", NULL, "SHDN" },
};
static const struct snd_soc_component_driver max9877_component_driver = {
.controls = max9877_controls,
.num_controls = ARRAY_SIZE(max9877_controls),
.dapm_widgets = max9877_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max9877_dapm_widgets),
.dapm_routes = max9877_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max9877_dapm_routes),
};
static const struct regmap_config max9877_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = max9877_regs,
.num_reg_defaults = ARRAY_SIZE(max9877_regs),
.cache_type = REGCACHE_RBTREE,
};
static int max9877_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
int i;
regmap = devm_regmap_init_i2c(client, &max9877_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Ensure the device is in reset state */
for (i = 0; i < ARRAY_SIZE(max9877_regs); i++)
regmap_write(regmap, max9877_regs[i].reg, max9877_regs[i].def);
return devm_snd_soc_register_component(&client->dev,
&max9877_component_driver, NULL, 0);
}
static const struct i2c_device_id max9877_i2c_id[] = {
{ "max9877", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9877_i2c_id);
static struct i2c_driver max9877_i2c_driver = {
.driver = {
.name = "max9877",
},
.probe = max9877_i2c_probe,
.id_table = max9877_i2c_id,
};
module_i2c_driver(max9877_i2c_driver);
MODULE_DESCRIPTION("ASoC MAX9877 amp driver");
MODULE_AUTHOR("Joonyoung Shim <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max9877.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/pm_runtime.h>
#include <linux/component.h>
#include <sound/tlv.h>
#include <linux/of_gpio.h>
#include <linux/of.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/regulator/consumer.h>
#include "wcd-clsh-v2.h"
#include "wcd-mbhc-v2.h"
#include "wcd938x.h"
#define WCD938X_MAX_MICBIAS (4)
#define WCD938X_MAX_SUPPLY (4)
#define WCD938X_MBHC_MAX_BUTTONS (8)
#define TX_ADC_MAX (4)
#define WCD938X_TX_MAX_SWR_PORTS (5)
#define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
/* Fractional Rates */
#define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_176400)
#define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* Convert from vout ctl to micbias voltage in mV */
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
#define SWR_CLK_RATE_0P6MHZ (600000)
#define SWR_CLK_RATE_1P2MHZ (1200000)
#define SWR_CLK_RATE_2P4MHZ (2400000)
#define SWR_CLK_RATE_4P8MHZ (4800000)
#define SWR_CLK_RATE_9P6MHZ (9600000)
#define SWR_CLK_RATE_11P2896MHZ (1128960)
#define WCD938X_DRV_NAME "wcd938x_codec"
#define WCD938X_VERSION_1_0 (1)
#define EAR_RX_PATH_AUX (1)
#define ADC_MODE_VAL_HIFI 0x01
#define ADC_MODE_VAL_LO_HIF 0x02
#define ADC_MODE_VAL_NORMAL 0x03
#define ADC_MODE_VAL_LP 0x05
#define ADC_MODE_VAL_ULP1 0x09
#define ADC_MODE_VAL_ULP2 0x0B
/* Z value defined in milliohm */
#define WCD938X_ZDET_VAL_32 (32000)
#define WCD938X_ZDET_VAL_400 (400000)
#define WCD938X_ZDET_VAL_1200 (1200000)
#define WCD938X_ZDET_VAL_100K (100000000)
/* Z floating defined in ohms */
#define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
#define WCD938X_ZDET_NUM_MEASUREMENTS (900)
#define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
#define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF)
/* Z value compared in milliOhm */
#define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
#define WCD938X_MBHC_ZDET_CONST (86 * 16384)
#define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM
#define WCD_MBHC_HS_V_MAX 1600
#define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.tlv.p = (tlv_array), \
.info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
.put = wcd938x_ear_pa_put_gain, \
.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
enum {
WCD9380 = 0,
WCD9385 = 5,
};
enum {
TX_HDR12 = 0,
TX_HDR34,
TX_HDR_MAX,
};
enum {
WCD_RX1,
WCD_RX2,
WCD_RX3
};
enum {
/* INTR_CTRL_INT_MASK_0 */
WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
WCD938X_IRQ_MBHC_SW_DET,
WCD938X_IRQ_HPHR_OCP_INT,
WCD938X_IRQ_HPHR_CNP_INT,
WCD938X_IRQ_HPHL_OCP_INT,
/* INTR_CTRL_INT_MASK_1 */
WCD938X_IRQ_HPHL_CNP_INT,
WCD938X_IRQ_EAR_CNP_INT,
WCD938X_IRQ_EAR_SCD_INT,
WCD938X_IRQ_AUX_CNP_INT,
WCD938X_IRQ_AUX_SCD_INT,
WCD938X_IRQ_HPHL_PDM_WD_INT,
WCD938X_IRQ_HPHR_PDM_WD_INT,
WCD938X_IRQ_AUX_PDM_WD_INT,
/* INTR_CTRL_INT_MASK_2 */
WCD938X_IRQ_LDORT_SCD_INT,
WCD938X_IRQ_MBHC_MOISTURE_INT,
WCD938X_IRQ_HPHL_SURGE_DET_INT,
WCD938X_IRQ_HPHR_SURGE_DET_INT,
WCD938X_NUM_IRQS,
};
enum {
WCD_ADC1 = 0,
WCD_ADC2,
WCD_ADC3,
WCD_ADC4,
ALLOW_BUCK_DISABLE,
HPH_COMP_DELAY,
HPH_PA_DELAY,
AMIC2_BCS_ENABLE,
WCD_SUPPLIES_LPM_MODE,
};
enum {
ADC_MODE_INVALID = 0,
ADC_MODE_HIFI,
ADC_MODE_LO_HIF,
ADC_MODE_NORMAL,
ADC_MODE_LP,
ADC_MODE_ULP1,
ADC_MODE_ULP2,
};
enum {
AIF1_PB = 0,
AIF1_CAP,
NUM_CODEC_DAIS,
};
static u8 tx_mode_bit[] = {
[ADC_MODE_INVALID] = 0x00,
[ADC_MODE_HIFI] = 0x01,
[ADC_MODE_LO_HIF] = 0x02,
[ADC_MODE_NORMAL] = 0x04,
[ADC_MODE_LP] = 0x08,
[ADC_MODE_ULP1] = 0x10,
[ADC_MODE_ULP2] = 0x20,
};
struct wcd938x_priv {
struct sdw_slave *tx_sdw_dev;
struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
struct device *txdev;
struct device *rxdev;
struct device_node *rxnode, *txnode;
struct regmap *regmap;
struct mutex micb_lock;
/* mbhc module */
struct wcd_mbhc *wcd_mbhc;
struct wcd_mbhc_config mbhc_cfg;
struct wcd_mbhc_intr intr_ids;
struct wcd_clsh_ctrl *clsh_info;
struct irq_domain *virq;
struct regmap_irq_chip *wcd_regmap_irq_chip;
struct regmap_irq_chip_data *irq_chip;
struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
struct snd_soc_jack *jack;
unsigned long status_mask;
s32 micb_ref[WCD938X_MAX_MICBIAS];
s32 pullup_ref[WCD938X_MAX_MICBIAS];
u32 hph_mode;
u32 tx_mode[TX_ADC_MAX];
int flyback_cur_det_disable;
int ear_rx_path;
int variant;
int reset_gpio;
struct gpio_desc *us_euro_gpio;
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb4_mv;
int hphr_pdm_wd_int;
int hphl_pdm_wd_int;
int aux_pdm_wd_int;
bool comp1_enable;
bool comp2_enable;
bool ldoh;
bool bcs_dis;
};
static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, -3000);
static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
struct wcd938x_mbhc_zdet_param {
u16 ldo_ctl;
u16 noff;
u16 nshift;
u16 btn5;
u16 btn6;
u16 btn7;
};
static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06),
WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03),
WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03),
WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07),
WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF),
WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0),
WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0),
WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02),
WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70),
WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01),
WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20),
WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08),
WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40),
WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80),
WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF),
WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F),
WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10),
WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04),
WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
};
static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
};
static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
.name = "wcd938x",
.irqs = wcd938x_irqs,
.num_irqs = ARRAY_SIZE(wcd938x_irqs),
.num_regs = 3,
.status_base = WCD938X_DIGITAL_INTR_STATUS_0,
.mask_base = WCD938X_DIGITAL_INTR_MASK_0,
.ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
.use_ack = 1,
.runtime_pm = true,
.irq_drv_data = NULL,
};
static int wcd938x_get_clk_rate(int mode)
{
int rate;
switch (mode) {
case ADC_MODE_ULP2:
rate = SWR_CLK_RATE_0P6MHZ;
break;
case ADC_MODE_ULP1:
rate = SWR_CLK_RATE_1P2MHZ;
break;
case ADC_MODE_LP:
rate = SWR_CLK_RATE_4P8MHZ;
break;
case ADC_MODE_NORMAL:
case ADC_MODE_LO_HIF:
case ADC_MODE_HIFI:
case ADC_MODE_INVALID:
default:
rate = SWR_CLK_RATE_9P6MHZ;
break;
}
return rate;
}
static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
{
u8 mask = (bank ? 0xF0 : 0x0F);
u8 val = 0;
switch (rate) {
case SWR_CLK_RATE_0P6MHZ:
val = (bank ? 0x60 : 0x06);
break;
case SWR_CLK_RATE_1P2MHZ:
val = (bank ? 0x50 : 0x05);
break;
case SWR_CLK_RATE_2P4MHZ:
val = (bank ? 0x30 : 0x03);
break;
case SWR_CLK_RATE_4P8MHZ:
val = (bank ? 0x10 : 0x01);
break;
case SWR_CLK_RATE_9P6MHZ:
default:
val = 0x00;
break;
}
snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
mask, val);
return 0;
}
static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
{
struct regmap *rm = wcd938x->regmap;
regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1010);
regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1010);
regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
0xF0, 0x80);
regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
/* 10 msec delay as per HW requirement */
usleep_range(10000, 10010);
regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
0xF0, 0x00);
regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
0x1F, 0x15);
regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
0x1F, 0x15);
regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
0xC0, 0x80);
regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
0x02, 0x02);
regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
0xFF, 0x14);
regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
0x1F, 0x08);
regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
/* Set Noise Filter Resistor value */
regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
return 0;
}
static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
struct sdw_port_config *port_config,
u8 enable)
{
u8 ch_mask, port_num;
port_num = ch_info->port_num;
ch_mask = ch_info->ch_mask;
port_config->num = port_num;
if (enable)
port_config->ch_mask |= ch_mask;
else
port_config->ch_mask &= ~ch_mask;
return 0;
}
static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
{
return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
&wcd->port_config[port_num - 1],
enable);
}
static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_RX_CLK_EN_MASK, 1);
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_RX_BIAS_EN_MASK, 1);
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
WCD938X_DEM_DITHER_ENABLE_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
WCD938X_DEM_DITHER_ENABLE_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
WCD938X_DEM_DITHER_ENABLE_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
WCD938X_AUXPA_CLK_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_VNEG_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_VPOS_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_RX_BIAS_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_RX_CLK_EN_MASK, 0);
break;
}
return 0;
}
static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD0_CLK_EN_MASK, 0x01);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
WCD938X_HPHL_RX_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_HPH_RDAC_CLK_CTL1,
WCD938X_CHOP_CLK_EN_MASK, 0);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write_field(component,
WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
WCD938X_HPH_RES_DIV_MASK, 0x02);
if (wcd938x->comp1_enable) {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0,
WCD938X_HPHL_COMP_EN_MASK, 1);
/* 5msec compander delay as per HW requirement */
if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
usleep_range(5000, 5010);
snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
WCD938X_AUTOCHOP_TIMER_EN, 0);
} else {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0,
WCD938X_HPHL_COMP_EN_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_HPH_L_EN,
WCD938X_GAIN_SRC_SEL_MASK,
WCD938X_GAIN_SRC_SEL_REGISTER);
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component,
WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
WCD938X_HPH_RES_DIV_MASK, 0x1);
break;
}
return 0;
}
static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD1_CLK_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
WCD938X_HPHR_RX_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_HPH_RDAC_CLK_CTL1,
WCD938X_CHOP_CLK_EN_MASK, 0);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write_field(component,
WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
WCD938X_HPH_RES_DIV_MASK, 0x02);
if (wcd938x->comp2_enable) {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0,
WCD938X_HPHR_COMP_EN_MASK, 1);
/* 5msec compander delay as per HW requirement */
if (!wcd938x->comp1_enable ||
(snd_soc_component_read(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
usleep_range(5000, 5010);
snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
WCD938X_AUTOCHOP_TIMER_EN, 0);
} else {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0,
WCD938X_HPHR_COMP_EN_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_HPH_R_EN,
WCD938X_GAIN_SRC_SEL_MASK,
WCD938X_GAIN_SRC_SEL_REGISTER);
}
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component,
WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
WCD938X_HPH_RES_DIV_MASK, 0x01);
break;
}
return 0;
}
static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd938x->ear_rx_path =
snd_soc_component_read(
component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
snd_soc_component_write_field(component,
WCD938X_EAR_EAR_DAC_CON,
WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
WCD938X_AUX_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD2_CLK_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_ANA_EAR_COMPANDER_CTL,
WCD938X_GAIN_OVRD_REG_MASK, 1);
} else {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
WCD938X_HPHL_RX_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD0_CLK_EN_MASK, 1);
if (wcd938x->comp1_enable)
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0,
WCD938X_HPHL_COMP_EN_MASK, 1);
}
/* 5 msec delay as per HW requirement */
usleep_range(5000, 5010);
if (wcd938x->flyback_cur_det_disable == 0)
snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
WCD938X_EN_CUR_DET_MASK, 0);
wcd938x->flyback_cur_det_disable++;
wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_EAR,
wcd938x->hph_mode);
break;
case SND_SOC_DAPM_POST_PMD:
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
WCD938X_AUX_EN_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD2_CLK_EN_MASK, 0);
} else {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
WCD938X_HPHL_RX_EN_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD0_CLK_EN_MASK, 0);
if (wcd938x->comp1_enable)
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_COMP_CTL_0,
WCD938X_HPHL_COMP_EN_MASK, 0);
}
snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
WCD938X_GAIN_OVRD_REG_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_EAR_EAR_DAC_CON,
WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
break;
}
return 0;
}
static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_RXD2_CLK_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
WCD938X_AUX_EN_MASK, 1);
if (wcd938x->flyback_cur_det_disable == 0)
snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
WCD938X_EN_CUR_DET_MASK, 0);
wcd938x->flyback_cur_det_disable++;
wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_AUX,
wcd938x->hph_mode);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
break;
}
return 0;
}
static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int hph_mode = wcd938x->hph_mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (wcd938x->ldoh)
snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
WCD938X_LDOH_EN_MASK, 1);
wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_HPHR, hph_mode);
wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
hph_mode == CLS_H_ULP) {
snd_soc_component_write_field(component,
WCD938X_HPH_REFBUFF_LP_CTL,
WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
}
snd_soc_component_write_field(component, WCD938X_ANA_HPH,
WCD938X_HPHR_REF_EN_MASK, 1);
wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
/* 100 usec delay as per HW requirement */
usleep_range(100, 110);
set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_PDM_WD_CTL1,
WCD938X_PDM_WD_EN_MASK, 0x3);
break;
case SND_SOC_DAPM_POST_PMU:
/*
* 7ms sleep is required if compander is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is required.
*/
if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
if (!wcd938x->comp2_enable)
usleep_range(20000, 20100);
else
usleep_range(7000, 7100);
if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
hph_mode == CLS_H_ULP)
snd_soc_component_write_field(component,
WCD938X_HPH_REFBUFF_LP_CTL,
WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
}
snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
WCD938X_AUTOCHOP_TIMER_EN, 1);
if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_REGULATOR_MODE_MASK,
WCD938X_REGULATOR_MODE_CLASS_AB);
enable_irq(wcd938x->hphr_pdm_wd_int);
break;
case SND_SOC_DAPM_PRE_PMD:
disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
/*
* 7ms sleep is required if compander is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is required.
*/
if (!wcd938x->comp2_enable)
usleep_range(20000, 20100);
else
usleep_range(7000, 7100);
snd_soc_component_write_field(component, WCD938X_ANA_HPH,
WCD938X_HPHR_EN_MASK, 0);
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_PRE_HPHR_PA_OFF);
set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
break;
case SND_SOC_DAPM_POST_PMD:
/*
* 7ms sleep is required if compander is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is required.
*/
if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
if (!wcd938x->comp2_enable)
usleep_range(20000, 20100);
else
usleep_range(7000, 7100);
clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
}
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_POST_HPHR_PA_OFF);
snd_soc_component_write_field(component, WCD938X_ANA_HPH,
WCD938X_HPHR_REF_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
WCD938X_PDM_WD_EN_MASK, 0);
wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHR, hph_mode);
if (wcd938x->ldoh)
snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
WCD938X_LDOH_EN_MASK, 0);
break;
}
return 0;
}
static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int hph_mode = wcd938x->hph_mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (wcd938x->ldoh)
snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
WCD938X_LDOH_EN_MASK, 1);
wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
WCD_CLSH_STATE_HPHL, hph_mode);
wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
hph_mode == CLS_H_ULP) {
snd_soc_component_write_field(component,
WCD938X_HPH_REFBUFF_LP_CTL,
WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
}
snd_soc_component_write_field(component, WCD938X_ANA_HPH,
WCD938X_HPHL_REF_EN_MASK, 1);
wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
/* 100 usec delay as per HW requirement */
usleep_range(100, 110);
set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_PDM_WD_CTL0,
WCD938X_PDM_WD_EN_MASK, 0x3);
break;
case SND_SOC_DAPM_POST_PMU:
/*
* 7ms sleep is required if compander is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is required.
*/
if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
if (!wcd938x->comp1_enable)
usleep_range(20000, 20100);
else
usleep_range(7000, 7100);
if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
hph_mode == CLS_H_ULP)
snd_soc_component_write_field(component,
WCD938X_HPH_REFBUFF_LP_CTL,
WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
}
snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
WCD938X_AUTOCHOP_TIMER_EN, 1);
if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_REGULATOR_MODE_MASK,
WCD938X_REGULATOR_MODE_CLASS_AB);
enable_irq(wcd938x->hphl_pdm_wd_int);
break;
case SND_SOC_DAPM_PRE_PMD:
disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
/*
* 7ms sleep is required if compander is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is required.
*/
if (!wcd938x->comp1_enable)
usleep_range(20000, 20100);
else
usleep_range(7000, 7100);
snd_soc_component_write_field(component, WCD938X_ANA_HPH,
WCD938X_HPHL_EN_MASK, 0);
wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
break;
case SND_SOC_DAPM_POST_PMD:
/*
* 7ms sleep is required if compander is enabled as per
* HW requirement. If compander is disabled, then
* 20ms delay is required.
*/
if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
if (!wcd938x->comp1_enable)
usleep_range(21000, 21100);
else
usleep_range(7000, 7100);
clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
}
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_POST_HPHL_PA_OFF);
snd_soc_component_write_field(component, WCD938X_ANA_HPH,
WCD938X_HPHL_REF_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
WCD938X_PDM_WD_EN_MASK, 0);
wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_HPHL, hph_mode);
if (wcd938x->ldoh)
snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
WCD938X_LDOH_EN_MASK, 0);
break;
}
return 0;
}
static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int hph_mode = wcd938x->hph_mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
WCD938X_AUX_PDM_WD_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMU:
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1010);
if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_REGULATOR_MODE_MASK,
WCD938X_REGULATOR_MODE_CLASS_AB);
enable_irq(wcd938x->aux_pdm_wd_int);
break;
case SND_SOC_DAPM_PRE_PMD:
disable_irq_nosync(wcd938x->aux_pdm_wd_int);
break;
case SND_SOC_DAPM_POST_PMD:
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1010);
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
WCD938X_AUX_PDM_WD_EN_MASK, 0);
wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_AUX,
hph_mode);
wcd938x->flyback_cur_det_disable--;
if (wcd938x->flyback_cur_det_disable == 0)
snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
WCD938X_EN_CUR_DET_MASK, 1);
break;
}
return 0;
}
static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int hph_mode = wcd938x->hph_mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/*
* Enable watchdog interrupt for HPHL or AUX
* depending on mux value
*/
wcd938x->ear_rx_path = snd_soc_component_read(component,
WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
WCD938X_AUX_PDM_WD_EN_MASK, 1);
else
snd_soc_component_write_field(component,
WCD938X_DIGITAL_PDM_WD_CTL0,
WCD938X_PDM_WD_EN_MASK, 0x3);
if (!wcd938x->comp1_enable)
snd_soc_component_write_field(component,
WCD938X_ANA_EAR_COMPANDER_CTL,
WCD938X_GAIN_OVRD_REG_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMU:
/* 6 msec delay as per HW requirement */
usleep_range(6000, 6010);
if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
WCD938X_REGULATOR_MODE_MASK,
WCD938X_REGULATOR_MODE_CLASS_AB);
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
enable_irq(wcd938x->aux_pdm_wd_int);
else
enable_irq(wcd938x->hphl_pdm_wd_int);
break;
case SND_SOC_DAPM_PRE_PMD:
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
disable_irq_nosync(wcd938x->aux_pdm_wd_int);
else
disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
break;
case SND_SOC_DAPM_POST_PMD:
if (!wcd938x->comp1_enable)
snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
WCD938X_GAIN_OVRD_REG_MASK, 0);
/* 7 msec delay as per HW requirement */
usleep_range(7000, 7010);
if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
WCD938X_AUX_PDM_WD_EN_MASK, 0);
else
snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
WCD938X_PDM_WD_EN_MASK, 0);
wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
WCD_CLSH_STATE_EAR, hph_mode);
wcd938x->flyback_cur_det_disable--;
if (wcd938x->flyback_cur_det_disable == 0)
snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
WCD938X_EN_CUR_DET_MASK, 1);
break;
}
return 0;
}
static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 dmic_clk_reg, dmic_clk_en_reg;
u8 dmic_sel_mask, dmic_clk_mask;
switch (w->shift) {
case 0:
case 1:
dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
break;
case 2:
case 3:
dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
break;
case 4:
case 5:
dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
break;
case 6:
case 7:
dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
break;
default:
dev_err(component->dev, "%s: Invalid DMIC Selection\n",
__func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_AMIC_CTL,
dmic_sel_mask,
WCD938X_AMIC1_IN_SEL_DMIC);
/* 250us sleep as per HW requirement */
usleep_range(250, 260);
/* Setting DMIC clock rate to 2.4MHz */
snd_soc_component_write_field(component, dmic_clk_reg,
dmic_clk_mask,
WCD938X_DMIC4_RATE_2P4MHZ);
snd_soc_component_write_field(component, dmic_clk_en_reg,
WCD938X_DMIC_CLK_EN_MASK, 1);
/* enable clock scaling */
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_AMIC_CTL,
dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
snd_soc_component_write_field(component, dmic_clk_en_reg,
WCD938X_DMIC_CLK_EN_MASK, 0);
break;
}
return 0;
}
static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int bank;
int rate;
bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
bank = bank ? 0 : 1;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (strnstr(w->name, "ADC", sizeof("ADC"))) {
int i = 0, mode = 0;
if (test_bit(WCD_ADC1, &wcd938x->status_mask))
mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
if (test_bit(WCD_ADC2, &wcd938x->status_mask))
mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
if (test_bit(WCD_ADC3, &wcd938x->status_mask))
mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
if (test_bit(WCD_ADC4, &wcd938x->status_mask))
mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
if (mode != 0) {
for (i = 0; i < ADC_MODE_ULP2; i++) {
if (mode & (1 << i)) {
i++;
break;
}
}
}
rate = wcd938x_get_clk_rate(i);
wcd938x_set_swr_clk_rate(component, rate, bank);
/* Copy clk settings to active bank */
wcd938x_set_swr_clk_rate(component, rate, !bank);
}
break;
case SND_SOC_DAPM_POST_PMD:
if (strnstr(w->name, "ADC", sizeof("ADC"))) {
rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
wcd938x_set_swr_clk_rate(component, rate, !bank);
wcd938x_set_swr_clk_rate(component, rate, bank);
}
break;
}
return 0;
}
static int wcd938x_get_adc_mode(int val)
{
int ret = 0;
switch (val) {
case ADC_MODE_INVALID:
ret = ADC_MODE_VAL_NORMAL;
break;
case ADC_MODE_HIFI:
ret = ADC_MODE_VAL_HIFI;
break;
case ADC_MODE_LO_HIF:
ret = ADC_MODE_VAL_LO_HIF;
break;
case ADC_MODE_NORMAL:
ret = ADC_MODE_VAL_NORMAL;
break;
case ADC_MODE_LP:
ret = ADC_MODE_VAL_LP;
break;
case ADC_MODE_ULP1:
ret = ADC_MODE_VAL_ULP1;
break;
case ADC_MODE_ULP2:
ret = ADC_MODE_VAL_ULP2;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_TX_CLK_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
set_bit(w->shift, &wcd938x->status_mask);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_TX_CLK_EN_MASK, 0);
clear_bit(w->shift, &wcd938x->status_mask);
break;
}
return 0;
}
static void wcd938x_tx_channel_config(struct snd_soc_component *component,
int channel, int mode)
{
int reg, mask;
switch (channel) {
case 0:
reg = WCD938X_ANA_TX_CH2;
mask = WCD938X_HPF1_INIT_MASK;
break;
case 1:
reg = WCD938X_ANA_TX_CH2;
mask = WCD938X_HPF2_INIT_MASK;
break;
case 2:
reg = WCD938X_ANA_TX_CH4;
mask = WCD938X_HPF3_INIT_MASK;
break;
case 3:
reg = WCD938X_ANA_TX_CH4;
mask = WCD938X_HPF4_INIT_MASK;
break;
default:
return;
}
snd_soc_component_write_field(component, reg, mask, mode);
}
static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int mode;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_REQ_CTL,
WCD938X_FS_RATE_4P8_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_REQ_CTL,
WCD938X_NO_NOTCH_MASK, 0);
wcd938x_tx_channel_config(component, w->shift, 1);
mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
if (mode < 0) {
dev_info(component->dev, "Invalid ADC mode\n");
return -EINVAL;
}
switch (w->shift) {
case 0:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
WCD938X_TXD0_MODE_MASK, mode);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD0_CLK_EN_MASK, 1);
break;
case 1:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
WCD938X_TXD1_MODE_MASK, mode);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD1_CLK_EN_MASK, 1);
break;
case 2:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
WCD938X_TXD2_MODE_MASK, mode);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD2_CLK_EN_MASK, 1);
break;
case 3:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
WCD938X_TXD3_MODE_MASK, mode);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD3_CLK_EN_MASK, 1);
break;
default:
break;
}
wcd938x_tx_channel_config(component, w->shift, 0);
break;
case SND_SOC_DAPM_POST_PMD:
switch (w->shift) {
case 0:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
WCD938X_TXD0_MODE_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD0_CLK_EN_MASK, 0);
break;
case 1:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
WCD938X_TXD1_MODE_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD1_CLK_EN_MASK, 0);
break;
case 2:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
WCD938X_TXD2_MODE_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD2_CLK_EN_MASK, 0);
break;
case 3:
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
WCD938X_TXD3_MODE_MASK, 0);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TXD3_CLK_EN_MASK, 0);
break;
default:
break;
}
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
break;
}
return 0;
}
static int wcd938x_micbias_control(struct snd_soc_component *component,
int micb_num, int req, bool is_dapm)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int micb_index = micb_num - 1;
u16 micb_reg;
switch (micb_num) {
case MIC_BIAS_1:
micb_reg = WCD938X_ANA_MICB1;
break;
case MIC_BIAS_2:
micb_reg = WCD938X_ANA_MICB2;
break;
case MIC_BIAS_3:
micb_reg = WCD938X_ANA_MICB3;
break;
case MIC_BIAS_4:
micb_reg = WCD938X_ANA_MICB4;
break;
default:
dev_err(component->dev, "%s: Invalid micbias number: %d\n",
__func__, micb_num);
return -EINVAL;
}
switch (req) {
case MICB_PULLUP_ENABLE:
wcd938x->pullup_ref[micb_index]++;
if ((wcd938x->pullup_ref[micb_index] == 1) &&
(wcd938x->micb_ref[micb_index] == 0))
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK,
WCD938X_MICB_PULL_UP);
break;
case MICB_PULLUP_DISABLE:
if (wcd938x->pullup_ref[micb_index] > 0)
wcd938x->pullup_ref[micb_index]--;
if ((wcd938x->pullup_ref[micb_index] == 0) &&
(wcd938x->micb_ref[micb_index] == 0))
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK, 0);
break;
case MICB_ENABLE:
wcd938x->micb_ref[micb_index]++;
if (wcd938x->micb_ref[micb_index] == 1) {
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
WCD938X_TX_CLK_EN_MASK, 0xF);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
snd_soc_component_write_field(component,
WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
WCD938X_TX_SC_CLK_EN_MASK, 1);
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK,
WCD938X_MICB_ENABLE);
if (micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_POST_MICBIAS_2_ON);
}
if (micb_num == MIC_BIAS_2 && is_dapm)
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
break;
case MICB_DISABLE:
if (wcd938x->micb_ref[micb_index] > 0)
wcd938x->micb_ref[micb_index]--;
if ((wcd938x->micb_ref[micb_index] == 0) &&
(wcd938x->pullup_ref[micb_index] > 0))
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK,
WCD938X_MICB_PULL_UP);
else if ((wcd938x->micb_ref[micb_index] == 0) &&
(wcd938x->pullup_ref[micb_index] == 0)) {
if (micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_PRE_MICBIAS_2_OFF);
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK, 0);
if (micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_POST_MICBIAS_2_OFF);
}
if (is_dapm && micb_num == MIC_BIAS_2)
wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
break;
}
return 0;
}
static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int micb_num = w->shift;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
break;
case SND_SOC_DAPM_POST_PMU:
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1100);
break;
case SND_SOC_DAPM_POST_PMD:
wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
break;
}
return 0;
}
static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int micb_num = w->shift;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
wcd938x_micbias_control(component, micb_num,
MICB_PULLUP_ENABLE, true);
break;
case SND_SOC_DAPM_POST_PMU:
/* 1 msec delay as per HW requirement */
usleep_range(1000, 1100);
break;
case SND_SOC_DAPM_POST_PMD:
wcd938x_micbias_control(component, micb_num,
MICB_PULLUP_DISABLE, true);
break;
}
return 0;
}
static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int path = e->shift_l;
ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path];
return 0;
}
static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int path = e->shift_l;
if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0])
return 0;
wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
return 1;
}
static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = wcd938x->hph_mode;
return 0;
}
static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0])
return 0;
wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
return 1;
}
static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
if (wcd938x->comp1_enable) {
dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
return -EINVAL;
}
snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
WCD938X_EAR_GAIN_MASK,
ucontrol->value.integer.value[0]);
return 1;
}
static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc;
bool hphr;
mc = (struct soc_mixer_control *)(kcontrol->private_value);
hphr = mc->shift;
if (hphr)
ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
else
ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
return 0;
}
static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
struct wcd938x_sdw_priv *wcd;
int value = ucontrol->value.integer.value[0];
int portidx;
struct soc_mixer_control *mc;
bool hphr;
mc = (struct soc_mixer_control *)(kcontrol->private_value);
hphr = mc->shift;
wcd = wcd938x->sdw_priv[AIF1_PB];
if (hphr)
wcd938x->comp2_enable = value;
else
wcd938x->comp1_enable = value;
portidx = wcd->ch_info[mc->reg].port_num;
if (value)
wcd938x_connect_port(wcd, portidx, mc->reg, true);
else
wcd938x_connect_port(wcd, portidx, mc->reg, false);
return 1;
}
static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wcd938x->ldoh;
return 0;
}
static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
if (wcd938x->ldoh == ucontrol->value.integer.value[0])
return 0;
wcd938x->ldoh = ucontrol->value.integer.value[0];
return 1;
}
static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
return 0;
}
static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
if (wcd938x->bcs_dis == ucontrol->value.integer.value[0])
return 0;
wcd938x->bcs_dis = ucontrol->value.integer.value[0];
return 1;
}
static const char * const tx_mode_mux_text_wcd9380[] = {
"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
};
static const char * const tx_mode_mux_text[] = {
"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
"ADC_ULP1", "ADC_ULP2",
};
static const char * const rx_hph_mode_mux_text_wcd9380[] = {
"CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
"CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
"CLS_AB_LOHIFI",
};
static const char * const rx_hph_mode_mux_text[] = {
"CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
"CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
};
static const char * const adc2_mux_text[] = {
"INP2", "INP3"
};
static const char * const adc3_mux_text[] = {
"INP4", "INP6"
};
static const char * const adc4_mux_text[] = {
"INP5", "INP7"
};
static const char * const rdac3_mux_text[] = {
"RX1", "RX3"
};
static const char * const hdr12_mux_text[] = {
"NO_HDR12", "HDR12"
};
static const char * const hdr34_mux_text[] = {
"NO_HDR34", "HDR34"
};
static const struct soc_enum tx0_mode_enum_wcd9380 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
tx_mode_mux_text_wcd9380);
static const struct soc_enum tx1_mode_enum_wcd9380 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
tx_mode_mux_text_wcd9380);
static const struct soc_enum tx2_mode_enum_wcd9380 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
tx_mode_mux_text_wcd9380);
static const struct soc_enum tx3_mode_enum_wcd9380 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
tx_mode_mux_text_wcd9380);
static const struct soc_enum tx0_mode_enum_wcd9385 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
tx_mode_mux_text);
static const struct soc_enum tx1_mode_enum_wcd9385 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
tx_mode_mux_text);
static const struct soc_enum tx2_mode_enum_wcd9385 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
tx_mode_mux_text);
static const struct soc_enum tx3_mode_enum_wcd9385 =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
tx_mode_mux_text);
static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
rx_hph_mode_mux_text_wcd9380);
static const struct soc_enum rx_hph_mode_mux_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
rx_hph_mode_mux_text);
static const struct soc_enum adc2_enum =
SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
static const struct soc_enum adc3_enum =
SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
static const struct soc_enum adc4_enum =
SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
static const struct soc_enum hdr12_enum =
SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
static const struct soc_enum hdr34_enum =
SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
static const struct soc_enum rdac3_enum =
SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
static const struct snd_kcontrol_new adc1_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new adc2_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new adc3_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new adc4_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic1_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic2_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic3_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic4_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic5_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic6_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic7_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new dmic8_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new ear_rdac_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new aux_rdac_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new hphl_rdac_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new hphr_rdac_switch[] = {
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
};
static const struct snd_kcontrol_new tx_adc2_mux =
SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
static const struct snd_kcontrol_new tx_adc3_mux =
SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
static const struct snd_kcontrol_new tx_adc4_mux =
SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
static const struct snd_kcontrol_new tx_hdr12_mux =
SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
static const struct snd_kcontrol_new tx_hdr34_mux =
SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
static const struct snd_kcontrol_new rx_rdac3_mux =
SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
};
static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
wcd938x_tx_mode_get, wcd938x_tx_mode_put),
};
static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
struct wcd938x_sdw_priv *wcd;
struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
int dai_id = mixer->shift;
int portidx, ch_idx = mixer->reg;
wcd = wcd938x->sdw_priv[dai_id];
portidx = wcd->ch_info[ch_idx].port_num;
ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
return 0;
}
static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
struct wcd938x_sdw_priv *wcd;
struct soc_mixer_control *mixer =
(struct soc_mixer_control *)kcontrol->private_value;
int ch_idx = mixer->reg;
int portidx;
int dai_id = mixer->shift;
bool enable;
wcd = wcd938x->sdw_priv[dai_id];
portidx = wcd->ch_info[ch_idx].port_num;
if (ucontrol->value.integer.value[0])
enable = true;
else
enable = false;
wcd->port_enable[portidx] = enable;
wcd938x_connect_port(wcd, portidx, ch_idx, enable);
return 1;
}
/* MBHC related */
static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1,
WCD938X_MBHC_CTL_RCO_EN_MASK, enable);
}
static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT,
WCD938X_ANA_MBHC_BIAS_EN, enable);
}
static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component,
int *btn_low, int *btn_high,
int num_btn, bool is_micbias)
{
int i, vth;
if (num_btn > WCD_MBHC_DEF_BUTTONS) {
dev_err(component->dev, "%s: invalid number of buttons: %d\n",
__func__, num_btn);
return;
}
for (i = 0; i < num_btn; i++) {
vth = ((btn_high[i] * 2) / 25) & 0x3F;
snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i,
WCD938X_MBHC_BTN_VTH_MASK, vth);
dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
__func__, i, btn_high[i], vth);
}
}
static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
{
u8 val;
if (micb_num == MIC_BIAS_2) {
val = snd_soc_component_read_field(component,
WCD938X_ANA_MICB2,
WCD938X_ANA_MICB2_ENABLE_MASK);
if (val == WCD938X_MICB_ENABLE)
return true;
}
return false;
}
static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
int pull_up_cur)
{
/* Default pull up current to 2uA */
if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
pull_up_cur = HS_PULLUP_I_2P0_UA;
snd_soc_component_write_field(component,
WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,
WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur);
}
static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component,
int micb_num, int req)
{
return wcd938x_micbias_control(component, micb_num, req, false);
}
static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component,
bool enable)
{
if (enable) {
snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C);
snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
WCD938X_RAMP_EN_MASK, 1);
} else {
snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
WCD938X_RAMP_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
WCD938X_RAMP_SHIFT_CTRL_MASK, 0);
}
}
static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
{
/* min micbias voltage is 1V and maximum is 2.85V */
if (micb_mv < 1000 || micb_mv > 2850)
return -EINVAL;
return (micb_mv - 1000) / 50;
}
static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
int req_volt, int micb_num)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
switch (micb_num) {
case MIC_BIAS_1:
micb_reg = WCD938X_ANA_MICB1;
break;
case MIC_BIAS_2:
micb_reg = WCD938X_ANA_MICB2;
break;
case MIC_BIAS_3:
micb_reg = WCD938X_ANA_MICB3;
break;
case MIC_BIAS_4:
micb_reg = WCD938X_ANA_MICB4;
break;
default:
return -EINVAL;
}
mutex_lock(&wcd938x->micb_lock);
/*
* If requested micbias voltage is same as current micbias
* voltage, then just return. Otherwise, adjust voltage as
* per requested value. If micbias is already enabled, then
* to avoid slow micbias ramp-up or down enable pull-up
* momentarily, change the micbias value and then re-enable
* micbias.
*/
micb_en = snd_soc_component_read_field(component, micb_reg,
WCD938X_MICB_EN_MASK);
cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
WCD938X_MICB_VOUT_MASK);
req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
if (req_vout_ctl < 0) {
ret = -EINVAL;
goto exit;
}
if (cur_vout_ctl == req_vout_ctl) {
ret = 0;
goto exit;
}
if (micb_en == WCD938X_MICB_ENABLE)
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK,
WCD938X_MICB_PULL_UP);
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_VOUT_MASK,
req_vout_ctl);
if (micb_en == WCD938X_MICB_ENABLE) {
snd_soc_component_write_field(component, micb_reg,
WCD938X_MICB_EN_MASK,
WCD938X_MICB_ENABLE);
/*
* Add 2ms delay as per HW requirement after enabling
* micbias
*/
usleep_range(2000, 2100);
}
exit:
mutex_unlock(&wcd938x->micb_lock);
return ret;
}
static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
int micb_num, bool req_en)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int micb_mv;
if (micb_num != MIC_BIAS_2)
return -EINVAL;
/*
* If device tree micbias level is already above the minimum
* voltage needed to detect threshold microphone, then do
* not change the micbias, just return.
*/
if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
return 0;
micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv;
return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
}
static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component,
s16 *d1_a, u16 noff,
int32_t *zdet)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int i;
int val, val1;
s16 c1;
s32 x1, d1;
int32_t denom;
static const int minCode_param[] = {
3277, 1639, 820, 410, 205, 103, 52, 26
};
regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20);
for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) {
regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val);
if (val & 0x80)
break;
}
val = val << 0x8;
regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1);
val |= val1;
regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00);
x1 = WCD938X_MBHC_GET_X1(val);
c1 = WCD938X_MBHC_GET_C1(val);
/* If ramp is not complete, give additional 5ms */
if ((c1 < 2) && x1)
usleep_range(5000, 5050);
if (!c1 || !x1) {
dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n",
c1, x1);
goto ramp_down;
}
d1 = d1_a[c1];
denom = (x1 * d1) - (1 << (14 - noff));
if (denom > 0)
*zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom;
else if (x1 < minCode_param[noff])
*zdet = WCD938X_ZDET_FLOATING_IMPEDANCE;
dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n",
__func__, d1, c1, x1, *zdet);
ramp_down:
i = 0;
while (x1) {
regmap_read(wcd938x->regmap,
WCD938X_ANA_MBHC_RESULT_1, &val);
regmap_read(wcd938x->regmap,
WCD938X_ANA_MBHC_RESULT_2, &val1);
val = val << 0x08;
val |= val1;
x1 = WCD938X_MBHC_GET_X1(val);
i++;
if (i == WCD938X_ZDET_NUM_MEASUREMENTS)
break;
}
}
static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component,
struct wcd938x_mbhc_zdet_param *zdet_param,
int32_t *zl, int32_t *zr, s16 *d1_a)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
int32_t zdet = 0;
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5,
WCD938X_VTH_MASK, zdet_param->btn5);
snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6,
WCD938X_VTH_MASK, zdet_param->btn6);
snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7,
WCD938X_VTH_MASK, zdet_param->btn7);
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL,
0x0F, zdet_param->nshift);
if (!zl)
goto z_right;
/* Start impedance measurement for HPH_L */
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_ZDET, 0x80, 0x80);
dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
__func__, zdet_param->noff);
wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_ZDET, 0x80, 0x00);
*zl = zdet;
z_right:
if (!zr)
return;
/* Start impedance measurement for HPH_R */
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_ZDET, 0x40, 0x40);
dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
__func__, zdet_param->noff);
wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_ZDET, 0x40, 0x00);
*zr = zdet;
}
static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
int32_t *z_val, int flag_l_r)
{
s16 q1;
int q1_cal;
if (*z_val < (WCD938X_ZDET_VAL_400/1000))
q1 = snd_soc_component_read(component,
WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
else
q1 = snd_soc_component_read(component,
WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
if (q1 & 0x80)
q1_cal = (10000 - ((q1 & 0x7F) * 25));
else
q1_cal = (10000 + (q1 * 25));
if (q1_cal > 0)
*z_val = ((*z_val) * 10000) / q1_cal;
}
static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
uint32_t *zl, uint32_t *zr)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
s16 reg0, reg1, reg2, reg3, reg4;
int32_t z1L, z1R, z1Ls;
int zMono, z_diff1, z_diff2;
bool is_fsm_disable = false;
struct wcd938x_mbhc_zdet_param zdet_param[] = {
{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
};
struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL;
s16 d1_a[][4] = {
{0, 30, 90, 30},
{0, 30, 30, 5},
{0, 30, 30, 5},
{0, 30, 30, 5},
};
s16 *d1 = NULL;
reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5);
reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7);
reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK);
reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL);
if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) {
is_fsm_disable = true;
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_ELECT, 0x80, 0x00);
}
/* For NO-jack, disable L_DET_EN before Z-det measurements */
if (wcd938x->mbhc_cfg.hphl_swh)
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_MECH, 0x80, 0x00);
/* Turn off 100k pull down on HPHL */
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_MECH, 0x01, 0x00);
/* Disable surge protection before impedance detection.
* This is done to give correct value for high impedance.
*/
regmap_update_bits(wcd938x->regmap,
WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
/* 1ms delay needed after disable surge protection */
usleep_range(1000, 1010);
/* First get impedance on Left */
d1 = d1_a[1];
zdet_param_ptr = &zdet_param[1];
wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
goto left_ch_impedance;
/* Second ramp for left ch */
if (z1L < WCD938X_ZDET_VAL_32) {
zdet_param_ptr = &zdet_param[0];
d1 = d1_a[0];
} else if ((z1L > WCD938X_ZDET_VAL_400) &&
(z1L <= WCD938X_ZDET_VAL_1200)) {
zdet_param_ptr = &zdet_param[2];
d1 = d1_a[2];
} else if (z1L > WCD938X_ZDET_VAL_1200) {
zdet_param_ptr = &zdet_param[3];
d1 = d1_a[3];
}
wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
left_ch_impedance:
if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
(z1L > WCD938X_ZDET_VAL_100K)) {
*zl = WCD938X_ZDET_FLOATING_IMPEDANCE;
zdet_param_ptr = &zdet_param[1];
d1 = d1_a[1];
} else {
*zl = z1L/1000;
wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0);
}
dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
__func__, *zl);
/* Start of right impedance ramp and calculation */
wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
if (((z1R > WCD938X_ZDET_VAL_1200) &&
(zdet_param_ptr->noff == 0x6)) ||
((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE))
goto right_ch_impedance;
/* Second ramp for right ch */
if (z1R < WCD938X_ZDET_VAL_32) {
zdet_param_ptr = &zdet_param[0];
d1 = d1_a[0];
} else if ((z1R > WCD938X_ZDET_VAL_400) &&
(z1R <= WCD938X_ZDET_VAL_1200)) {
zdet_param_ptr = &zdet_param[2];
d1 = d1_a[2];
} else if (z1R > WCD938X_ZDET_VAL_1200) {
zdet_param_ptr = &zdet_param[3];
d1 = d1_a[3];
}
wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
}
right_ch_impedance:
if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
(z1R > WCD938X_ZDET_VAL_100K)) {
*zr = WCD938X_ZDET_FLOATING_IMPEDANCE;
} else {
*zr = z1R/1000;
wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1);
}
dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
__func__, *zr);
/* Mono/stereo detection */
if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) &&
(*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) {
dev_dbg(component->dev,
"%s: plug type is invalid or extension cable\n",
__func__);
goto zdet_complete;
}
if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
(*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
dev_dbg(component->dev,
"%s: Mono plug type with one ch floating or shorted to GND\n",
__func__);
wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
goto zdet_complete;
}
snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
WCD938X_HPHPA_GND_OVR_MASK, 1);
snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
WCD938X_HPHPA_GND_R_MASK, 1);
if (*zl < (WCD938X_ZDET_VAL_32/1000))
wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
else
wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
WCD938X_HPHPA_GND_R_MASK, 0);
snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
WCD938X_HPHPA_GND_OVR_MASK, 0);
z1Ls /= 1000;
wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
/* Parallel of left Z and 9 ohm pull down resistor */
zMono = ((*zl) * 9) / ((*zl) + 9);
z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
dev_dbg(component->dev, "%s: stereo plug type detected\n",
__func__);
wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
} else {
dev_dbg(component->dev, "%s: MONO plug type detected\n",
__func__);
wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
}
/* Enable surge protection again after impedance detection */
regmap_update_bits(wcd938x->regmap,
WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
zdet_complete:
snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0);
snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2);
/* Turn on 100k pull down on HPHL */
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_MECH, 0x01, 0x01);
/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
if (wcd938x->mbhc_cfg.hphl_swh)
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_MECH, 0x80, 0x80);
snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4);
snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3);
if (is_fsm_disable)
regmap_update_bits(wcd938x->regmap,
WCD938X_ANA_MBHC_ELECT, 0x80, 0x80);
}
static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
bool enable)
{
if (enable) {
snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1);
snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
WCD938X_MBHC_GND_DET_EN_MASK, 1);
} else {
snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
WCD938X_MBHC_GND_DET_EN_MASK, 0);
snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0);
}
}
static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
WCD938X_HPHPA_GND_R_MASK, enable);
snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
WCD938X_HPHPA_GND_L_MASK, enable);
}
static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, R_OFF);
return;
}
/* Do not enable moisture detection if jack type is NC */
if (!wcd938x->mbhc_cfg.hphl_swh) {
dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
__func__);
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, R_OFF);
return;
}
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
}
static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
if (enable)
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
else
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, R_OFF);
}
static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
bool ret = false;
if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, R_OFF);
goto done;
}
/* Do not enable moisture detection if jack type is NC */
if (!wcd938x->mbhc_cfg.hphl_swh) {
dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
__func__);
snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
WCD938X_M_RTH_CTL_MASK, R_OFF);
goto done;
}
/*
* If moisture_en is already enabled, then skip to plug type
* detection.
*/
if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK))
goto done;
wcd938x_mbhc_moisture_detect_en(component, true);
/* Read moisture comparator status */
ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS)
& 0x20) ? 0 : 1);
done:
return ret;
}
static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_write_field(component,
WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
WCD938X_MOISTURE_EN_POLLING_MASK, enable);
}
static const struct wcd_mbhc_cb mbhc_cb = {
.clk_setup = wcd938x_mbhc_clk_setup,
.mbhc_bias = wcd938x_mbhc_mbhc_bias_control,
.set_btn_thr = wcd938x_mbhc_program_btn_thr,
.micbias_enable_status = wcd938x_mbhc_micb_en_status,
.hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control,
.mbhc_micbias_control = wcd938x_mbhc_request_micbias,
.mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control,
.mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic,
.compute_impedance = wcd938x_wcd_mbhc_calc_impedance,
.mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl,
.hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl,
.mbhc_moisture_config = wcd938x_mbhc_moisture_config,
.mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status,
.mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl,
.mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en,
};
static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc);
return 0;
}
static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
uint32_t zl, zr;
bool hphr;
struct soc_mixer_control *mc;
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
mc = (struct soc_mixer_control *)(kcontrol->private_value);
hphr = mc->shift;
wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr);
dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
ucontrol->value.integer.value[0] = hphr ? zr : zl;
return 0;
}
static const struct snd_kcontrol_new hph_type_detect_controls[] = {
SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
wcd938x_get_hph_type, NULL),
};
static const struct snd_kcontrol_new impedance_detect_controls[] = {
SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
wcd938x_hph_impedance_get, NULL),
SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
wcd938x_hph_impedance_get, NULL),
};
static int wcd938x_mbhc_init(struct snd_soc_component *component)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids;
intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_MBHC_SW_DET);
intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_MBHC_BUTTON_PRESS_DET);
intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET);
intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_MBHC_ELECT_INS_REM_DET);
intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_HPHL_OCP_INT);
intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_HPHR_OCP_INT);
wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
if (IS_ERR(wcd938x->wcd_mbhc))
return PTR_ERR(wcd938x->wcd_mbhc);
snd_soc_add_component_controls(component, impedance_detect_controls,
ARRAY_SIZE(impedance_detect_controls));
snd_soc_add_component_controls(component, hph_type_detect_controls,
ARRAY_SIZE(hph_type_detect_controls));
return 0;
}
static void wcd938x_mbhc_deinit(struct snd_soc_component *component)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
wcd_mbhc_deinit(wcd938x->wcd_mbhc);
}
/* END MBHC */
static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
wcd938x_get_compander, wcd938x_set_compander),
SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
wcd938x_get_compander, wcd938x_set_compander),
SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain),
SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain),
WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
2, 0x10, 0, ear_pa_gain),
SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
wcd938x_get_swr_port, wcd938x_set_swr_port),
SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
wcd938x_ldoh_get, wcd938x_ldoh_put),
SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
wcd938x_bcs_get, wcd938x_bcs_put),
SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
};
static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
/*input widgets*/
SND_SOC_DAPM_INPUT("AMIC1"),
SND_SOC_DAPM_INPUT("AMIC2"),
SND_SOC_DAPM_INPUT("AMIC3"),
SND_SOC_DAPM_INPUT("AMIC4"),
SND_SOC_DAPM_INPUT("AMIC5"),
SND_SOC_DAPM_INPUT("AMIC6"),
SND_SOC_DAPM_INPUT("AMIC7"),
SND_SOC_DAPM_MIC("Analog Mic1", NULL),
SND_SOC_DAPM_MIC("Analog Mic2", NULL),
SND_SOC_DAPM_MIC("Analog Mic3", NULL),
SND_SOC_DAPM_MIC("Analog Mic4", NULL),
SND_SOC_DAPM_MIC("Analog Mic5", NULL),
/*tx widgets*/
SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
wcd938x_codec_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
wcd938x_codec_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
wcd938x_codec_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
wcd938x_codec_enable_adc,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
wcd938x_codec_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
NULL, 0, wcd938x_adc_enable_req,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
NULL, 0, wcd938x_adc_enable_req,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
NULL, 0, wcd938x_adc_enable_req,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
wcd938x_adc_enable_req,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
/*tx mixers*/
SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* micbias widgets*/
SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
wcd938x_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
wcd938x_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
wcd938x_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
wcd938x_codec_enable_micbias,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
/* micbias pull up widgets*/
SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
wcd938x_codec_enable_micbias_pullup,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
wcd938x_codec_enable_micbias_pullup,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
wcd938x_codec_enable_micbias_pullup,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
wcd938x_codec_enable_micbias_pullup,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
/*output widgets tx*/
SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
SND_SOC_DAPM_INPUT("IN1_HPHL"),
SND_SOC_DAPM_INPUT("IN2_HPHR"),
SND_SOC_DAPM_INPUT("IN3_AUX"),
/*rx widgets*/
SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
wcd938x_codec_enable_ear_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
wcd938x_codec_enable_aux_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
wcd938x_codec_enable_hphl_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
wcd938x_codec_enable_hphr_pa,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
wcd938x_codec_hphl_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
wcd938x_codec_hphr_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
wcd938x_codec_ear_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
wcd938x_codec_aux_dac_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
wcd938x_codec_enable_rxclk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
/* rx mixer widgets*/
SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
/*output widgets rx*/
SND_SOC_DAPM_OUTPUT("EAR"),
SND_SOC_DAPM_OUTPUT("AUX"),
SND_SOC_DAPM_OUTPUT("HPHL"),
SND_SOC_DAPM_OUTPUT("HPHR"),
};
static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
{"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
{"ADC1_MIXER", "Switch", "ADC1 REQ"},
{"ADC1 REQ", NULL, "ADC1"},
{"ADC1", NULL, "AMIC1"},
{"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
{"ADC2_MIXER", "Switch", "ADC2 REQ"},
{"ADC2 REQ", NULL, "ADC2"},
{"ADC2", NULL, "HDR12 MUX"},
{"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
{"HDR12 MUX", "HDR12", "AMIC1"},
{"ADC2 MUX", "INP3", "AMIC3"},
{"ADC2 MUX", "INP2", "AMIC2"},
{"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
{"ADC3_MIXER", "Switch", "ADC3 REQ"},
{"ADC3 REQ", NULL, "ADC3"},
{"ADC3", NULL, "HDR34 MUX"},
{"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
{"HDR34 MUX", "HDR34", "AMIC5"},
{"ADC3 MUX", "INP4", "AMIC4"},
{"ADC3 MUX", "INP6", "AMIC6"},
{"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
{"ADC4_MIXER", "Switch", "ADC4 REQ"},
{"ADC4 REQ", NULL, "ADC4"},
{"ADC4", NULL, "ADC4 MUX"},
{"ADC4 MUX", "INP5", "AMIC5"},
{"ADC4 MUX", "INP7", "AMIC7"},
{"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
{"DMIC1_MIXER", "Switch", "DMIC1"},
{"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
{"DMIC2_MIXER", "Switch", "DMIC2"},
{"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
{"DMIC3_MIXER", "Switch", "DMIC3"},
{"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
{"DMIC4_MIXER", "Switch", "DMIC4"},
{"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
{"DMIC5_MIXER", "Switch", "DMIC5"},
{"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
{"DMIC6_MIXER", "Switch", "DMIC6"},
{"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
{"DMIC7_MIXER", "Switch", "DMIC7"},
{"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
{"DMIC8_MIXER", "Switch", "DMIC8"},
{"IN1_HPHL", NULL, "VDD_BUCK"},
{"IN1_HPHL", NULL, "CLS_H_PORT"},
{"RX1", NULL, "IN1_HPHL"},
{"RX1", NULL, "RXCLK"},
{"RDAC1", NULL, "RX1"},
{"HPHL_RDAC", "Switch", "RDAC1"},
{"HPHL PGA", NULL, "HPHL_RDAC"},
{"HPHL", NULL, "HPHL PGA"},
{"IN2_HPHR", NULL, "VDD_BUCK"},
{"IN2_HPHR", NULL, "CLS_H_PORT"},
{"RX2", NULL, "IN2_HPHR"},
{"RDAC2", NULL, "RX2"},
{"RX2", NULL, "RXCLK"},
{"HPHR_RDAC", "Switch", "RDAC2"},
{"HPHR PGA", NULL, "HPHR_RDAC"},
{"HPHR", NULL, "HPHR PGA"},
{"IN3_AUX", NULL, "VDD_BUCK"},
{"IN3_AUX", NULL, "CLS_H_PORT"},
{"RX3", NULL, "IN3_AUX"},
{"RDAC4", NULL, "RX3"},
{"RX3", NULL, "RXCLK"},
{"AUX_RDAC", "Switch", "RDAC4"},
{"AUX PGA", NULL, "AUX_RDAC"},
{"AUX", NULL, "AUX PGA"},
{"RDAC3_MUX", "RX3", "RX3"},
{"RDAC3_MUX", "RX1", "RX1"},
{"RDAC3", NULL, "RDAC3_MUX"},
{"EAR_RDAC", "Switch", "RDAC3"},
{"EAR PGA", NULL, "EAR_RDAC"},
{"EAR", NULL, "EAR PGA"},
};
static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
{
int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
/* set micbias voltage */
vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
return -EINVAL;
regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
WCD938X_MICB_VOUT_MASK, vout_ctl_1);
regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
WCD938X_MICB_VOUT_MASK, vout_ctl_2);
regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
WCD938X_MICB_VOUT_MASK, vout_ctl_3);
regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
WCD938X_MICB_VOUT_MASK, vout_ctl_4);
return 0;
}
static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
{
return IRQ_HANDLED;
}
static struct irq_chip wcd_irq_chip = {
.name = "WCD938x",
};
static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops wcd_domain_ops = {
.map = wcd_irq_chip_map,
};
static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
{
wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
if (!(wcd->virq)) {
dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
return -EINVAL;
}
return devm_regmap_add_irq_chip(dev, wcd->regmap,
irq_create_mapping(wcd->virq, 0),
IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
&wcd->irq_chip);
}
static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev;
struct device *dev = component->dev;
unsigned long time_left;
int ret, i;
time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
msecs_to_jiffies(2000));
if (!time_left) {
dev_err(dev, "soundwire device init timeout\n");
return -ETIMEDOUT;
}
snd_soc_component_init_regmap(component, wcd938x->regmap);
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
wcd938x->variant = snd_soc_component_read_field(component,
WCD938X_DIGITAL_EFUSE_REG_0,
WCD938X_ID_MASK);
wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
if (IS_ERR(wcd938x->clsh_info)) {
pm_runtime_put(dev);
return PTR_ERR(wcd938x->clsh_info);
}
wcd938x_io_init(wcd938x);
/* Set all interrupts as edge triggered */
for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
regmap_write(wcd938x->regmap,
(WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
}
pm_runtime_put(dev);
wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_HPHR_PDM_WD_INT);
wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_HPHL_PDM_WD_INT);
wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
WCD938X_IRQ_AUX_PDM_WD_INT);
/* Request for watchdog interrupt */
ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"HPHR PDM WD INT", wcd938x);
if (ret) {
dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
goto err_free_clsh_ctrl;
}
ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"HPHL PDM WD INT", wcd938x);
if (ret) {
dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
goto err_free_hphr_pdm_wd_int;
}
ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
IRQF_ONESHOT | IRQF_TRIGGER_RISING,
"AUX PDM WD INT", wcd938x);
if (ret) {
dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
goto err_free_hphl_pdm_wd_int;
}
/* Disable watchdog interrupt for HPH and AUX */
disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
disable_irq_nosync(wcd938x->aux_pdm_wd_int);
switch (wcd938x->variant) {
case WCD9380:
ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
ARRAY_SIZE(wcd9380_snd_controls));
if (ret < 0) {
dev_err(component->dev,
"%s: Failed to add snd ctrls for variant: %d\n",
__func__, wcd938x->variant);
goto err_free_aux_pdm_wd_int;
}
break;
case WCD9385:
ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
ARRAY_SIZE(wcd9385_snd_controls));
if (ret < 0) {
dev_err(component->dev,
"%s: Failed to add snd ctrls for variant: %d\n",
__func__, wcd938x->variant);
goto err_free_aux_pdm_wd_int;
}
break;
default:
break;
}
ret = wcd938x_mbhc_init(component);
if (ret) {
dev_err(component->dev, "mbhc initialization failed\n");
goto err_free_aux_pdm_wd_int;
}
return 0;
err_free_aux_pdm_wd_int:
free_irq(wcd938x->aux_pdm_wd_int, wcd938x);
err_free_hphl_pdm_wd_int:
free_irq(wcd938x->hphl_pdm_wd_int, wcd938x);
err_free_hphr_pdm_wd_int:
free_irq(wcd938x->hphr_pdm_wd_int, wcd938x);
err_free_clsh_ctrl:
wcd_clsh_ctrl_free(wcd938x->clsh_info);
return ret;
}
static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
{
struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
wcd938x_mbhc_deinit(component);
free_irq(wcd938x->aux_pdm_wd_int, wcd938x);
free_irq(wcd938x->hphl_pdm_wd_int, wcd938x);
free_irq(wcd938x->hphr_pdm_wd_int, wcd938x);
wcd_clsh_ctrl_free(wcd938x->clsh_info);
}
static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
struct snd_soc_jack *jack, void *data)
{
struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
if (jack)
return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
else
wcd_mbhc_stop(wcd->wcd_mbhc);
return 0;
}
static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
.name = "wcd938x_codec",
.probe = wcd938x_soc_codec_probe,
.remove = wcd938x_soc_codec_remove,
.controls = wcd938x_snd_controls,
.num_controls = ARRAY_SIZE(wcd938x_snd_controls),
.dapm_widgets = wcd938x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
.dapm_routes = wcd938x_audio_map,
.num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
.set_jack = wcd938x_codec_set_jack,
.endianness = 1,
};
static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
{
struct device_node *np = dev->of_node;
u32 prop_val = 0;
int rc = 0;
rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
if (!rc)
wcd->micb1_mv = prop_val/1000;
else
dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
if (!rc)
wcd->micb2_mv = prop_val/1000;
else
dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
if (!rc)
wcd->micb3_mv = prop_val/1000;
else
dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val);
if (!rc)
wcd->micb4_mv = prop_val/1000;
else
dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
}
static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component, bool active)
{
int value;
struct wcd938x_priv *wcd938x;
wcd938x = snd_soc_component_get_drvdata(component);
value = gpiod_get_value(wcd938x->us_euro_gpio);
gpiod_set_value(wcd938x->us_euro_gpio, !value);
return true;
}
static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
{
struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg;
int ret;
wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
if (wcd938x->reset_gpio < 0)
return dev_err_probe(dev, wcd938x->reset_gpio,
"Failed to get reset gpio\n");
wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro",
GPIOD_OUT_LOW);
if (IS_ERR(wcd938x->us_euro_gpio))
return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio),
"us-euro swap Control GPIO not found\n");
cfg->swap_gnd_mic = wcd938x_swap_gnd_mic;
wcd938x->supplies[0].supply = "vdd-rxtx";
wcd938x->supplies[1].supply = "vdd-io";
wcd938x->supplies[2].supply = "vdd-buck";
wcd938x->supplies[3].supply = "vdd-mic-bias";
ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
if (ret)
return dev_err_probe(dev, ret, "Failed to get supplies\n");
ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable supplies\n");
wcd938x_dt_parse_micbias_info(dev, wcd938x);
cfg->mbhc_micbias = MIC_BIAS_2;
cfg->anc_micbias = MIC_BIAS_2;
cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS;
cfg->micb_mv = wcd938x->micb2_mv;
cfg->linein_th = 5000;
cfg->hs_thr = 1700;
cfg->hph_thr = 50;
wcd_dt_parse_mbhc_data(dev, cfg);
return 0;
}
static int wcd938x_reset(struct wcd938x_priv *wcd938x)
{
gpio_direction_output(wcd938x->reset_gpio, 0);
/* 20us sleep required after pulling the reset gpio to LOW */
usleep_range(20, 30);
gpio_set_value(wcd938x->reset_gpio, 1);
/* 20us sleep required after pulling the reset gpio to HIGH */
usleep_range(20, 30);
return 0;
}
static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
return wcd938x_sdw_hw_params(wcd, substream, params, dai);
}
static int wcd938x_codec_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
return wcd938x_sdw_free(wcd, substream, dai);
}
static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
void *stream, int direction)
{
struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
}
static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
.hw_params = wcd938x_codec_hw_params,
.hw_free = wcd938x_codec_free,
.set_stream = wcd938x_codec_set_sdw_stream,
};
static struct snd_soc_dai_driver wcd938x_dais[] = {
[0] = {
.name = "wcd938x-sdw-rx",
.playback = {
.stream_name = "WCD AIF1 Playback",
.rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
.formats = WCD938X_FORMATS_S16_S24_LE,
.rate_max = 192000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &wcd938x_sdw_dai_ops,
},
[1] = {
.name = "wcd938x-sdw-tx",
.capture = {
.stream_name = "WCD AIF1 Capture",
.rates = WCD938X_RATES_MASK,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 4,
},
.ops = &wcd938x_sdw_dai_ops,
},
};
static int wcd938x_bind(struct device *dev)
{
struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
int ret;
ret = component_bind_all(dev, wcd938x);
if (ret) {
dev_err(dev, "%s: Slave bind failed, ret = %d\n",
__func__, ret);
return ret;
}
wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
if (!wcd938x->rxdev) {
dev_err(dev, "could not find slave with matching of node\n");
return -EINVAL;
}
wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
if (!wcd938x->txdev) {
dev_err(dev, "could not find txslave with matching of node\n");
return -EINVAL;
}
wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
if (!wcd938x->tx_sdw_dev) {
dev_err(dev, "could not get txslave with matching of dev\n");
return -EINVAL;
}
/* As TX is main CSR reg interface, which should not be suspended first.
* expicilty add the dependency link */
if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME)) {
dev_err(dev, "could not devlink tx and rx\n");
return -EINVAL;
}
if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME)) {
dev_err(dev, "could not devlink wcd and tx\n");
return -EINVAL;
}
if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME)) {
dev_err(dev, "could not devlink wcd and rx\n");
return -EINVAL;
}
wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL);
if (!wcd938x->regmap) {
dev_err(dev, "could not get TX device regmap\n");
return -EINVAL;
}
ret = wcd938x_irq_init(wcd938x, dev);
if (ret) {
dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
return ret;
}
wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
ret = wcd938x_set_micbias_data(wcd938x);
if (ret < 0) {
dev_err(dev, "%s: bad micbias pdata\n", __func__);
return ret;
}
ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
if (ret)
dev_err(dev, "%s: Codec registration failed\n",
__func__);
return ret;
}
static void wcd938x_unbind(struct device *dev)
{
struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
device_link_remove(dev, wcd938x->txdev);
device_link_remove(dev, wcd938x->rxdev);
device_link_remove(wcd938x->rxdev, wcd938x->txdev);
snd_soc_unregister_component(dev);
component_unbind_all(dev, wcd938x);
}
static const struct component_master_ops wcd938x_comp_ops = {
.bind = wcd938x_bind,
.unbind = wcd938x_unbind,
};
static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
struct device *dev,
struct component_match **matchptr)
{
struct device_node *np;
np = dev->of_node;
wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
if (!wcd938x->rxnode) {
dev_err(dev, "%s: Rx-device node not defined\n", __func__);
return -ENODEV;
}
of_node_get(wcd938x->rxnode);
component_match_add_release(dev, matchptr, component_release_of,
component_compare_of, wcd938x->rxnode);
wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
if (!wcd938x->txnode) {
dev_err(dev, "%s: Tx-device node not defined\n", __func__);
return -ENODEV;
}
of_node_get(wcd938x->txnode);
component_match_add_release(dev, matchptr, component_release_of,
component_compare_of, wcd938x->txnode);
return 0;
}
static int wcd938x_probe(struct platform_device *pdev)
{
struct component_match *match = NULL;
struct wcd938x_priv *wcd938x = NULL;
struct device *dev = &pdev->dev;
int ret;
wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
GFP_KERNEL);
if (!wcd938x)
return -ENOMEM;
dev_set_drvdata(dev, wcd938x);
mutex_init(&wcd938x->micb_lock);
ret = wcd938x_populate_dt_data(wcd938x, dev);
if (ret) {
dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
return -EINVAL;
}
ret = wcd938x_add_slave_components(wcd938x, dev, &match);
if (ret)
return ret;
wcd938x_reset(wcd938x);
ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
if (ret)
return ret;
pm_runtime_set_autosuspend_delay(dev, 1000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
return 0;
}
static void wcd938x_remove(struct platform_device *pdev)
{
component_master_del(&pdev->dev, &wcd938x_comp_ops);
}
#if defined(CONFIG_OF)
static const struct of_device_id wcd938x_dt_match[] = {
{ .compatible = "qcom,wcd9380-codec" },
{ .compatible = "qcom,wcd9385-codec" },
{}
};
MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
#endif
static struct platform_driver wcd938x_codec_driver = {
.probe = wcd938x_probe,
.remove_new = wcd938x_remove,
.driver = {
.name = "wcd938x_codec",
.of_match_table = of_match_ptr(wcd938x_dt_match),
.suppress_bind_attrs = true,
},
};
module_platform_driver(wcd938x_codec_driver);
MODULE_DESCRIPTION("WCD938X Codec driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wcd938x.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt5682s.c -- RT5682I-VS ALSA SoC audio component driver
//
// Copyright 2021 Realtek Semiconductor Corp.
// Author: Derek Fang <[email protected]>
//
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5682s.h>
#include "rt5682s.h"
#define DEVICE_ID 0x6749
static const struct rt5682s_platform_data i2s_default_platform_data = {
.dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
.dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
.jd_src = RT5682S_JD1,
.dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
.dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
};
static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
[RT5682S_SUPPLY_AVDD] = "AVDD",
[RT5682S_SUPPLY_MICVDD] = "MICVDD",
[RT5682S_SUPPLY_DBVDD] = "DBVDD",
[RT5682S_SUPPLY_LDO1_IN] = "LDO1-IN",
};
static const struct reg_sequence patch_list[] = {
{RT5682S_I2C_CTRL, 0x0007},
{RT5682S_DIG_IN_CTRL_1, 0x0000},
{RT5682S_CHOP_DAC_2, 0x2020},
{RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
{RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
{RT5682S_HP_CALIB_CTRL_9, 0x0002},
{RT5682S_DEPOP_1, 0x0000},
{RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
{RT5682S_DAC1_DIG_VOL, 0xfefe},
{RT5682S_SAR_IL_CMD_2, 0xac00},
{RT5682S_SAR_IL_CMD_3, 0x024c},
{RT5682S_CBJ_CTRL_6, 0x0804},
};
static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
struct device *dev)
{
int ret;
ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
if (ret)
dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
}
static const struct reg_default rt5682s_reg[] = {
{0x0002, 0x8080},
{0x0003, 0x0001},
{0x0005, 0x0000},
{0x0006, 0x0000},
{0x0008, 0x8007},
{0x000b, 0x0000},
{0x000f, 0x4000},
{0x0010, 0x4040},
{0x0011, 0x0000},
{0x0012, 0x0000},
{0x0013, 0x1200},
{0x0014, 0x200a},
{0x0015, 0x0404},
{0x0016, 0x0404},
{0x0017, 0x05a4},
{0x0019, 0xffff},
{0x001c, 0x2f2f},
{0x001f, 0x0000},
{0x0022, 0x5757},
{0x0023, 0x0039},
{0x0024, 0x000b},
{0x0026, 0xc0c4},
{0x0029, 0x8080},
{0x002a, 0xa0a0},
{0x002b, 0x0300},
{0x0030, 0x0000},
{0x003c, 0x08c0},
{0x0044, 0x1818},
{0x004b, 0x00c0},
{0x004c, 0x0000},
{0x004d, 0x0000},
{0x0061, 0x00c0},
{0x0062, 0x008a},
{0x0063, 0x0800},
{0x0064, 0x0000},
{0x0065, 0x0000},
{0x0066, 0x0030},
{0x0067, 0x000c},
{0x0068, 0x0000},
{0x0069, 0x0000},
{0x006a, 0x0000},
{0x006b, 0x0000},
{0x006c, 0x0000},
{0x006d, 0x2200},
{0x006e, 0x0810},
{0x006f, 0xe4de},
{0x0070, 0x3320},
{0x0071, 0x0000},
{0x0073, 0x0000},
{0x0074, 0x0000},
{0x0075, 0x0002},
{0x0076, 0x0001},
{0x0079, 0x0000},
{0x007a, 0x0000},
{0x007b, 0x0000},
{0x007c, 0x0100},
{0x007e, 0x0000},
{0x007f, 0x0000},
{0x0080, 0x0000},
{0x0083, 0x0000},
{0x0084, 0x0000},
{0x0085, 0x0000},
{0x0086, 0x0005},
{0x0087, 0x0000},
{0x0088, 0x0000},
{0x008c, 0x0003},
{0x008e, 0x0060},
{0x008f, 0x4da1},
{0x0091, 0x1c15},
{0x0092, 0x0425},
{0x0093, 0x0000},
{0x0094, 0x0080},
{0x0095, 0x008f},
{0x0096, 0x0000},
{0x0097, 0x0000},
{0x0098, 0x0000},
{0x0099, 0x0000},
{0x009a, 0x0000},
{0x009b, 0x0000},
{0x009c, 0x0000},
{0x009d, 0x0000},
{0x009e, 0x0000},
{0x009f, 0x0009},
{0x00a0, 0x0000},
{0x00a3, 0x0002},
{0x00a4, 0x0001},
{0x00b6, 0x0000},
{0x00b7, 0x0000},
{0x00b8, 0x0000},
{0x00b9, 0x0002},
{0x00be, 0x0000},
{0x00c0, 0x0160},
{0x00c1, 0x82a0},
{0x00c2, 0x0000},
{0x00d0, 0x0000},
{0x00d2, 0x3300},
{0x00d3, 0x2200},
{0x00d4, 0x0000},
{0x00d9, 0x0000},
{0x00da, 0x0000},
{0x00db, 0x0000},
{0x00dc, 0x00c0},
{0x00dd, 0x2220},
{0x00de, 0x3131},
{0x00df, 0x3131},
{0x00e0, 0x3131},
{0x00e2, 0x0000},
{0x00e3, 0x4000},
{0x00e4, 0x0aa0},
{0x00e5, 0x3131},
{0x00e6, 0x3131},
{0x00e7, 0x3131},
{0x00e8, 0x3131},
{0x00ea, 0xb320},
{0x00eb, 0x0000},
{0x00f0, 0x0000},
{0x00f6, 0x0000},
{0x00fa, 0x0000},
{0x00fb, 0x0000},
{0x00fc, 0x0000},
{0x00fd, 0x0000},
{0x00fe, 0x10ec},
{0x00ff, 0x6749},
{0x0100, 0xa000},
{0x010b, 0x0066},
{0x010c, 0x6666},
{0x010d, 0x2202},
{0x010e, 0x6666},
{0x010f, 0xa800},
{0x0110, 0x0006},
{0x0111, 0x0460},
{0x0112, 0x2000},
{0x0113, 0x0200},
{0x0117, 0x8000},
{0x0118, 0x0303},
{0x0125, 0x0020},
{0x0132, 0x5026},
{0x0136, 0x8000},
{0x0139, 0x0005},
{0x013a, 0x3030},
{0x013b, 0xa000},
{0x013c, 0x4110},
{0x013f, 0x0000},
{0x0145, 0x0022},
{0x0146, 0x0000},
{0x0147, 0x0000},
{0x0148, 0x0000},
{0x0156, 0x0022},
{0x0157, 0x0303},
{0x0158, 0x2222},
{0x0159, 0x0000},
{0x0160, 0x4ec0},
{0x0161, 0x0080},
{0x0162, 0x0200},
{0x0163, 0x0800},
{0x0164, 0x0000},
{0x0165, 0x0000},
{0x0166, 0x0000},
{0x0167, 0x000f},
{0x0168, 0x000f},
{0x0169, 0x0001},
{0x0190, 0x4131},
{0x0194, 0x0000},
{0x0195, 0x0000},
{0x0197, 0x0022},
{0x0198, 0x0000},
{0x0199, 0x0000},
{0x01ac, 0x0000},
{0x01ad, 0x0000},
{0x01ae, 0x0000},
{0x01af, 0x2000},
{0x01b0, 0x0000},
{0x01b1, 0x0000},
{0x01b2, 0x0000},
{0x01b3, 0x0017},
{0x01b4, 0x004b},
{0x01b5, 0x0000},
{0x01b6, 0x03e8},
{0x01b7, 0x0000},
{0x01b8, 0x0000},
{0x01b9, 0x0400},
{0x01ba, 0xb5b6},
{0x01bb, 0x9124},
{0x01bc, 0x4924},
{0x01bd, 0x0009},
{0x01be, 0x0018},
{0x01bf, 0x002a},
{0x01c0, 0x004c},
{0x01c1, 0x0097},
{0x01c2, 0x01c3},
{0x01c3, 0x03e9},
{0x01c4, 0x1389},
{0x01c5, 0xc351},
{0x01c6, 0x02a0},
{0x01c7, 0x0b0f},
{0x01c8, 0x402f},
{0x01c9, 0x0702},
{0x01ca, 0x0000},
{0x01cb, 0x0000},
{0x01cc, 0x5757},
{0x01cd, 0x5757},
{0x01ce, 0x5757},
{0x01cf, 0x5757},
{0x01d0, 0x5757},
{0x01d1, 0x5757},
{0x01d2, 0x5757},
{0x01d3, 0x5757},
{0x01d4, 0x5757},
{0x01d5, 0x5757},
{0x01d6, 0x0000},
{0x01d7, 0x0000},
{0x01d8, 0x0162},
{0x01d9, 0x0007},
{0x01da, 0x0000},
{0x01db, 0x0004},
{0x01dc, 0x0000},
{0x01de, 0x7c00},
{0x01df, 0x0020},
{0x01e0, 0x04c1},
{0x01e1, 0x0000},
{0x01e2, 0x0000},
{0x01e3, 0x0000},
{0x01e4, 0x0000},
{0x01e5, 0x0000},
{0x01e6, 0x0001},
{0x01e7, 0x0000},
{0x01e8, 0x0000},
{0x01eb, 0x0000},
{0x01ec, 0x0000},
{0x01ed, 0x0000},
{0x01ee, 0x0000},
{0x01ef, 0x0000},
{0x01f0, 0x0000},
{0x01f1, 0x0000},
{0x01f2, 0x0000},
{0x01f3, 0x0000},
{0x01f4, 0x0000},
{0x0210, 0x6297},
{0x0211, 0xa004},
{0x0212, 0x0365},
{0x0213, 0xf7ff},
{0x0214, 0xf24c},
{0x0215, 0x0102},
{0x0216, 0x00a3},
{0x0217, 0x0048},
{0x0218, 0xa2c0},
{0x0219, 0x0400},
{0x021a, 0x00c8},
{0x021b, 0x00c0},
{0x021c, 0x0000},
{0x021d, 0x024c},
{0x02fa, 0x0000},
{0x02fb, 0x0000},
{0x02fc, 0x0000},
{0x03fe, 0x0000},
{0x03ff, 0x0000},
{0x0500, 0x0000},
{0x0600, 0x0000},
{0x0610, 0x6666},
{0x0611, 0xa9aa},
{0x0620, 0x6666},
{0x0621, 0xa9aa},
{0x0630, 0x6666},
{0x0631, 0xa9aa},
{0x0640, 0x6666},
{0x0641, 0xa9aa},
{0x07fa, 0x0000},
{0x08fa, 0x0000},
{0x08fb, 0x0000},
{0x0d00, 0x0000},
{0x1100, 0x0000},
{0x1101, 0x0000},
{0x1102, 0x0000},
{0x1103, 0x0000},
{0x1104, 0x0000},
{0x1105, 0x0000},
{0x1106, 0x0000},
{0x1107, 0x0000},
{0x1108, 0x0000},
{0x1109, 0x0000},
{0x110a, 0x0000},
{0x110b, 0x0000},
{0x110c, 0x0000},
{0x1111, 0x0000},
{0x1112, 0x0000},
{0x1113, 0x0000},
{0x1114, 0x0000},
{0x1115, 0x0000},
{0x1116, 0x0000},
{0x1117, 0x0000},
{0x1118, 0x0000},
{0x1119, 0x0000},
{0x111a, 0x0000},
{0x111b, 0x0000},
{0x111c, 0x0000},
{0x1401, 0x0404},
{0x1402, 0x0007},
{0x1403, 0x0365},
{0x1404, 0x0210},
{0x1405, 0x0365},
{0x1406, 0x0210},
{0x1407, 0x0000},
{0x1408, 0x0000},
{0x1409, 0x0000},
{0x140a, 0x0000},
{0x140b, 0x0000},
{0x140c, 0x0000},
{0x140d, 0x0000},
{0x140e, 0x0000},
{0x140f, 0x0000},
{0x1410, 0x0000},
{0x1411, 0x0000},
{0x1801, 0x0004},
{0x1802, 0x0000},
{0x1803, 0x0000},
{0x1804, 0x0000},
{0x1805, 0x00ff},
{0x2c00, 0x0000},
{0x3400, 0x0200},
{0x3404, 0x0000},
{0x3405, 0x0000},
{0x3406, 0x0000},
{0x3407, 0x0000},
{0x3408, 0x0000},
{0x3409, 0x0000},
{0x340a, 0x0000},
{0x340b, 0x0000},
{0x340c, 0x0000},
{0x340d, 0x0000},
{0x340e, 0x0000},
{0x340f, 0x0000},
{0x3410, 0x0000},
{0x3411, 0x0000},
{0x3412, 0x0000},
{0x3413, 0x0000},
{0x3414, 0x0000},
{0x3415, 0x0000},
{0x3424, 0x0000},
{0x3425, 0x0000},
{0x3426, 0x0000},
{0x3427, 0x0000},
{0x3428, 0x0000},
{0x3429, 0x0000},
{0x342a, 0x0000},
{0x342b, 0x0000},
{0x342c, 0x0000},
{0x342d, 0x0000},
{0x342e, 0x0000},
{0x342f, 0x0000},
{0x3430, 0x0000},
{0x3431, 0x0000},
{0x3432, 0x0000},
{0x3433, 0x0000},
{0x3434, 0x0000},
{0x3435, 0x0000},
{0x3440, 0x6319},
{0x3441, 0x3771},
{0x3500, 0x0002},
{0x3501, 0x5728},
{0x3b00, 0x3010},
{0x3b01, 0x3300},
{0x3b02, 0x2200},
{0x3b03, 0x0100},
};
static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5682S_RESET:
case RT5682S_CBJ_CTRL_2:
case RT5682S_I2S1_F_DIV_CTRL_2:
case RT5682S_I2S2_F_DIV_CTRL_2:
case RT5682S_INT_ST_1:
case RT5682S_GPIO_ST:
case RT5682S_IL_CMD_1:
case RT5682S_4BTN_IL_CMD_1:
case RT5682S_AJD1_CTRL:
case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
case RT5682S_STO_NG2_CTRL_1:
case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
case RT5682S_STO1_DAC_SIL_DET:
case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
case RT5682S_HP_IMP_SENS_CTRL_13:
case RT5682S_HP_IMP_SENS_CTRL_14:
case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
case RT5682S_HP_CALIB_CTRL_1:
case RT5682S_HP_CALIB_CTRL_10:
case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
case RT5682S_SAR_IL_CMD_10:
case RT5682S_SAR_IL_CMD_11:
case RT5682S_VERSION_ID_HIDE:
case RT5682S_VERSION_ID_CUS:
case RT5682S_I2C_TRANS_CTRL:
case RT5682S_DMIC_FLOAT_DET:
case RT5682S_HA_CMP_OP_1:
case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
case RT5682S_CLK_SW_TEST_1:
case RT5682S_CLK_SW_TEST_2:
case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
case RT5682S_PILOT_DIG_CTL_1:
return true;
default:
return false;
}
}
static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5682S_RESET:
case RT5682S_VERSION_ID:
case RT5682S_VENDOR_ID:
case RT5682S_DEVICE_ID:
case RT5682S_HP_CTRL_1:
case RT5682S_HP_CTRL_2:
case RT5682S_HPL_GAIN:
case RT5682S_HPR_GAIN:
case RT5682S_I2C_CTRL:
case RT5682S_CBJ_BST_CTRL:
case RT5682S_CBJ_DET_CTRL:
case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
case RT5682S_DAC1_DIG_VOL:
case RT5682S_STO1_ADC_DIG_VOL:
case RT5682S_STO1_ADC_BOOST:
case RT5682S_HP_IMP_GAIN_1:
case RT5682S_HP_IMP_GAIN_2:
case RT5682S_SIDETONE_CTRL:
case RT5682S_STO1_ADC_MIXER:
case RT5682S_AD_DA_MIXER:
case RT5682S_STO1_DAC_MIXER:
case RT5682S_A_DAC1_MUX:
case RT5682S_DIG_INF2_DATA:
case RT5682S_REC_MIXER:
case RT5682S_CAL_REC:
case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
case RT5682S_MB_CTRL:
case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
case RT5682S_I2S1_SDP:
case RT5682S_I2S2_SDP:
case RT5682S_ADDA_CLK_1:
case RT5682S_ADDA_CLK_2:
case RT5682S_I2S1_F_DIV_CTRL_1:
case RT5682S_I2S1_F_DIV_CTRL_2:
case RT5682S_TDM_CTRL:
case RT5682S_TDM_ADDA_CTRL_1:
case RT5682S_TDM_ADDA_CTRL_2:
case RT5682S_DATA_SEL_CTRL_1:
case RT5682S_TDM_TCON_CTRL_1:
case RT5682S_TDM_TCON_CTRL_2:
case RT5682S_GLB_CLK:
case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
case RT5682S_PLL_TRACK_11:
case RT5682S_DEPOP_1:
case RT5682S_HP_CHARGE_PUMP_1:
case RT5682S_HP_CHARGE_PUMP_2:
case RT5682S_HP_CHARGE_PUMP_3:
case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
case RT5682S_RC_CLK_CTRL:
case RT5682S_I2S2_M_CLK_CTRL_1:
case RT5682S_I2S2_F_DIV_CTRL_1:
case RT5682S_I2S2_F_DIV_CTRL_2:
case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
case RT5682S_INT_ST_1:
case RT5682S_GPIO_CTRL_1:
case RT5682S_GPIO_CTRL_2:
case RT5682S_GPIO_ST:
case RT5682S_HP_AMP_DET_CTRL_1:
case RT5682S_MID_HP_AMP_DET:
case RT5682S_LOW_HP_AMP_DET:
case RT5682S_DELAY_BUF_CTRL:
case RT5682S_SV_ZCD_1:
case RT5682S_SV_ZCD_2:
case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
case RT5682S_ADC_STO1_HP_CTRL_1:
case RT5682S_ADC_STO1_HP_CTRL_2:
case RT5682S_AJD1_CTRL:
case RT5682S_JD_CTRL_1:
case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
case RT5682S_DAC_ADC_DIG_VOL1:
case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
case RT5682S_CHARGE_PUMP_1:
case RT5682S_DIG_IN_CTRL_1:
case RT5682S_PAD_DRIVING_CTRL:
case RT5682S_CHOP_DAC_1:
case RT5682S_CHOP_DAC_2:
case RT5682S_CHOP_ADC:
case RT5682S_CALIB_ADC_CTRL:
case RT5682S_VOL_TEST:
case RT5682S_SPKVDD_DET_ST:
case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
case RT5682S_STO1_DAC_SIL_DET:
case RT5682S_SIL_PSV_CTRL1:
case RT5682S_SIL_PSV_CTRL2:
case RT5682S_SIL_PSV_CTRL3:
case RT5682S_SIL_PSV_CTRL4:
case RT5682S_SIL_PSV_CTRL5:
case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
case RT5682S_VERSION_ID_HIDE:
case RT5682S_VERSION_ID_CUS:
case RT5682S_SCAN_CTL:
case RT5682S_HP_AMP_DET:
case RT5682S_BIAS_CUR_CTRL_11:
case RT5682S_BIAS_CUR_CTRL_12:
case RT5682S_BIAS_CUR_CTRL_13:
case RT5682S_BIAS_CUR_CTRL_14:
case RT5682S_BIAS_CUR_CTRL_15:
case RT5682S_BIAS_CUR_CTRL_16:
case RT5682S_BIAS_CUR_CTRL_17:
case RT5682S_BIAS_CUR_CTRL_18:
case RT5682S_I2C_TRANS_CTRL:
case RT5682S_DUMMY_7:
case RT5682S_DUMMY_8:
case RT5682S_DMIC_FLOAT_DET:
case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
case RT5682S_CLK_SW_TEST_1:
case RT5682S_CLK_SW_TEST_2:
case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
case RT5682S_EFUSE_TIMING_CTL_1:
case RT5682S_EFUSE_TIMING_CTL_2:
case RT5682S_PILOT_DIG_CTL_1:
case RT5682S_PILOT_DIG_CTL_2:
case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
return true;
default:
return false;
}
}
static void rt5682s_reset(struct rt5682s_priv *rt5682s)
{
regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
}
static int rt5682s_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
return btn_type;
}
enum {
SAR_PWR_OFF,
SAR_PWR_NORMAL,
SAR_PWR_SAVING,
};
static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
mutex_lock(&rt5682s->sar_mutex);
switch (mode) {
case SAR_PWR_SAVING:
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
usleep_range(5000, 5500);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
usleep_range(5000, 5500);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
break;
case SAR_PWR_NORMAL:
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
usleep_range(5000, 5500);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
break;
case SAR_PWR_OFF:
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
break;
default:
dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
break;
}
mutex_unlock(&rt5682s->sar_mutex);
}
static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040);
snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
}
static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
{
snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
}
/**
* rt5682s_headset_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
unsigned int val, count;
int jack_type = 0;
if (jack_insert) {
rt5682s_disable_push_button_irq(component);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0);
usleep_range(15000, 20000);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365);
snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
usleep_range(45000, 50000);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
count = 0;
do {
usleep_range(10000, 15000);
val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
& RT5682S_JACK_TYPE_MASK;
count++;
} while (val == 0 && count < 50);
dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
switch (val) {
case 0x1:
case 0x2:
jack_type = SND_JACK_HEADSET;
snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN);
snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT);
rt5682s_enable_push_button_irq(component);
rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
break;
default:
jack_type = SND_JACK_HEADPHONE;
break;
}
snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
usleep_range(35000, 40000);
} else {
rt5682s_sar_power_mode(component, SAR_PWR_OFF);
rt5682s_disable_push_button_irq(component);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
if (!rt5682s->wclk_enabled) {
snd_soc_component_update_bits(component,
RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
}
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
RT5682S_PWR_CBJ, 0);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
jack_type = 0;
}
dev_dbg(component->dev, "jack_type = %d\n", jack_type);
return jack_type;
}
static void rt5682s_jack_detect_handler(struct work_struct *work)
{
struct rt5682s_priv *rt5682s =
container_of(work, struct rt5682s_priv, jack_detect_work.work);
struct snd_soc_dapm_context *dapm;
int val, btn_type;
if (!rt5682s->component ||
!snd_soc_card_is_instantiated(rt5682s->component->card)) {
/* card not yet ready, try later */
mod_delayed_work(system_power_efficient_wq,
&rt5682s->jack_detect_work, msecs_to_jiffies(15));
return;
}
dapm = snd_soc_component_get_dapm(rt5682s->component);
snd_soc_dapm_mutex_lock(dapm);
mutex_lock(&rt5682s->calibrate_mutex);
mutex_lock(&rt5682s->wclk_mutex);
val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
& RT5682S_JDH_RS_MASK;
if (!val) {
/* jack in */
if (rt5682s->jack_type == 0) {
/* jack was out, report jack type */
rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
rt5682s->irq_work_delay_time = 0;
} else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
/* jack is already in, report button event */
rt5682s->jack_type = SND_JACK_HEADSET;
btn_type = rt5682s_button_detect(rt5682s->component);
/**
* rt5682s can report three kinds of button behavior,
* one click, double click and hold. However,
* currently we will report button pressed/released
* event. So all the three button behaviors are
* treated as button pressed.
*/
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
rt5682s->jack_type |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
rt5682s->jack_type |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
rt5682s->jack_type |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
rt5682s->jack_type |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
dev_err(rt5682s->component->dev,
"Unexpected button code 0x%04x\n", btn_type);
break;
}
}
} else {
/* jack out */
rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
rt5682s->irq_work_delay_time = 50;
}
mutex_unlock(&rt5682s->wclk_mutex);
mutex_unlock(&rt5682s->calibrate_mutex);
snd_soc_dapm_mutex_unlock(dapm);
snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3))
schedule_delayed_work(&rt5682s->jd_check_work, 0);
else
cancel_delayed_work_sync(&rt5682s->jd_check_work);
}
static void rt5682s_jd_check_handler(struct work_struct *work)
{
struct rt5682s_priv *rt5682s =
container_of(work, struct rt5682s_priv, jd_check_work.work);
if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
/* jack out */
schedule_delayed_work(&rt5682s->jack_detect_work, 0);
} else {
schedule_delayed_work(&rt5682s->jd_check_work, 500);
}
}
static irqreturn_t rt5682s_irq(int irq, void *data)
{
struct rt5682s_priv *rt5682s = data;
mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
msecs_to_jiffies(rt5682s->irq_work_delay_time));
return IRQ_HANDLED;
}
static int rt5682s_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
int btndet_delay = 16;
rt5682s->hs_jack = hs_jack;
if (!hs_jack) {
regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
RT5682S_POW_JDH, 0);
cancel_delayed_work_sync(&rt5682s->jack_detect_work);
return 0;
}
switch (rt5682s->pdata.jd_src) {
case RT5682S_JD1:
regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS);
regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
mod_delayed_work(system_power_efficient_wq,
&rt5682s->jack_detect_work, msecs_to_jiffies(250));
break;
case RT5682S_JD_NULL:
regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
RT5682S_POW_JDH, 0);
break;
default:
dev_warn(component->dev, "Wrong JD source\n");
break;
}
return 0;
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
/* CBJ Boost Volume */
SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
RT5682S_BST_CBJ_SFT, 35, 0, cbj_bst_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
};
/**
* rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the component driver will turn on
* ASRC for these filters if ASRC is selected as their clock source.
*/
int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
switch (clk_src) {
case RT5682S_CLK_SEL_SYS:
case RT5682S_CLK_SEL_I2S1_ASRC:
case RT5682S_CLK_SEL_I2S2_ASRC:
break;
default:
return -EINVAL;
}
if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
}
if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
}
snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
return 0;
}
EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
int target, const int div[], int size)
{
int i;
if (rt5682s->sysclk < target) {
dev_err(rt5682s->component->dev,
"sysclk rate %d is too low\n", rt5682s->sysclk);
return 0;
}
for (i = 0; i < size - 1; i++) {
dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
if (target * div[i] == rt5682s->sysclk)
return i;
if (target * div[i + 1] > rt5682s->sysclk) {
dev_dbg(rt5682s->component->dev,
"can't find div for sysclk %d\n", rt5682s->sysclk);
return i;
}
}
if (target * div[i] < rt5682s->sysclk)
dev_err(rt5682s->component->dev,
"sysclk rate %d is too high\n", rt5682s->sysclk);
return size - 1;
}
static int get_clk_info(int sclk, int rate)
{
int i;
static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
if (sclk <= 0 || rate <= 0)
return -EINVAL;
rate = rate << 8;
for (i = 0; i < ARRAY_SIZE(pd); i++)
if (sclk == rate * pd[i])
return i;
return -EINVAL;
}
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
int idx, dmic_clk_rate = 3072000;
static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
if (rt5682s->pdata.dmic_clk_rate)
dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div));
snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT);
return 0;
}
static int rt5682s_set_pllb_power(struct rt5682s_priv *rt5682s, int on)
{
struct snd_soc_component *component = rt5682s->component;
if (on) {
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB,
RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
RT5682S_RSTB_PLLB, RT5682S_RSTB_PLLB);
} else {
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB |
RT5682S_RSTB_PLLB | RT5682S_PWR_PLLB, 0);
}
return 0;
}
static int set_pllb_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
int on = 0;
if (rt5682s->wclk_enabled)
return 0;
if (SND_SOC_DAPM_EVENT_ON(event))
on = 1;
rt5682s_set_pllb_power(rt5682s, on);
return 0;
}
static void rt5682s_set_filter_clk(struct rt5682s_priv *rt5682s, int reg, int ref)
{
struct snd_soc_component *component = rt5682s->component;
int idx;
static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
snd_soc_component_update_bits(component, reg,
RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT);
/* select over sample rate */
for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
if (rt5682s->sysclk <= 12288000 * div_o[idx])
break;
}
snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
(idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
}
static int set_filter_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
int ref, reg, val;
val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
& RT5682S_GP4_PIN_MASK;
if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
ref = 256 * rt5682s->lrck[RT5682S_AIF2];
else
ref = 256 * rt5682s->lrck[RT5682S_AIF1];
if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
reg = RT5682S_PLL_TRACK_3;
else
reg = RT5682S_PLL_TRACK_2;
rt5682s_set_filter_clk(rt5682s, reg, ref);
return 0;
}
static int set_dmic_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
unsigned int delay = 50, val;
if (rt5682s->pdata.dmic_delay)
delay = rt5682s->pdata.dmic_delay;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
& RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
/*Add delay to avoid pop noise*/
msleep(delay);
break;
case SND_SOC_DAPM_POST_PMD:
if (!rt5682s->jack_type && !rt5682s->wclk_enabled) {
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
}
break;
}
return 0;
}
static void rt5682s_set_i2s(struct rt5682s_priv *rt5682s, int id, int on)
{
struct snd_soc_component *component = rt5682s->component;
int pre_div;
unsigned int p_reg, p_mask, p_sft;
unsigned int c_reg, c_mask, c_sft;
if (id == RT5682S_AIF1) {
c_reg = RT5682S_ADDA_CLK_1;
c_mask = RT5682S_I2S_M_D_MASK;
c_sft = RT5682S_I2S_M_D_SFT;
p_reg = RT5682S_PWR_DIG_1;
p_mask = RT5682S_PWR_I2S1;
p_sft = RT5682S_PWR_I2S1_BIT;
} else {
c_reg = RT5682S_I2S2_M_CLK_CTRL_1;
c_mask = RT5682S_I2S2_M_D_MASK;
c_sft = RT5682S_I2S2_M_D_SFT;
p_reg = RT5682S_PWR_DIG_1;
p_mask = RT5682S_PWR_I2S2;
p_sft = RT5682S_PWR_I2S2_BIT;
}
if (on && rt5682s->master[id]) {
pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
if (pre_div < 0) {
dev_err(component->dev, "get pre_div failed\n");
return;
}
dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
rt5682s->lrck[id], pre_div, id);
snd_soc_component_update_bits(component, c_reg, c_mask, pre_div << c_sft);
}
snd_soc_component_update_bits(component, p_reg, p_mask, on << p_sft);
}
static int set_i2s_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
int on = 0;
if (SND_SOC_DAPM_EVENT_ON(event))
on = 1;
if (!strcmp(w->name, "I2S1") && !rt5682s->wclk_enabled)
rt5682s_set_i2s(rt5682s, RT5682S_AIF1, on);
else if (!strcmp(w->name, "I2S2"))
rt5682s_set_i2s(rt5682s, RT5682S_AIF2, on);
return 0;
}
static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
(rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
return 1;
return 0;
}
static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
return 1;
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, sft, val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case RT5682S_ADC_STO1_ASRC_SFT:
reg = RT5682S_PLL_TRACK_3;
sft = RT5682S_FILTER_CLK_SEL_SFT;
break;
case RT5682S_DAC_STO1_ASRC_SFT:
reg = RT5682S_PLL_TRACK_2;
sft = RT5682S_FILTER_CLK_SEL_SFT;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
switch (val) {
case RT5682S_CLK_SEL_I2S1_ASRC:
case RT5682S_CLK_SEL_I2S2_ASRC:
return 1;
default:
return 0;
}
}
static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
usleep_range(15000, 20000);
snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666);
snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a);
snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
usleep_range(5000, 10000);
snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
RT5682S_HPO_SEL_IP_EN_SW, 0);
snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0);
snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0);
break;
}
return 0;
}
static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
unsigned int delay = 0;
if (rt5682s->pdata.amic_delay)
delay = rt5682s->pdata.amic_delay;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(delay);
snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
RT5682S_L_MUTE, 0);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
RT5682S_L_MUTE, RT5682S_L_MUTE);
break;
}
return 0;
}
static int sar_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
return 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rt5682s_sar_power_mode(component, SAR_PWR_NORMAL);
break;
case SND_SOC_DAPM_POST_PMD:
rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
break;
}
return 0;
}
/* Interface data select */
static const char * const rt5682s_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
/* Digital Mixer */
static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
RT5682S_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
RT5682S_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
RT5682S_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
RT5682S_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
};
/* STO1 ADC1 Source */
/* MX-26 [13] [5] */
static const char * const rt5682s_sto1_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
/* STO1 ADC Source */
/* MX-26 [11:10] [3:2] */
static const char * const rt5682s_sto1_adc_src[] = {
"ADC1 L", "ADC1 R"
};
static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
/* STO1 ADC2 Source */
/* MX-26 [12] [4] */
static const char * const rt5682s_sto1_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
/* MX-79 [6:4] I2S1 ADC data location */
static const unsigned int rt5682s_if1_adc_slot_values[] = {
0, 2, 4, 6,
};
static const char * const rt5682s_if1_adc_slot_src[] = {
"Slot 0", "Slot 2", "Slot 4", "Slot 6"
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
/* Analog DAC L1 Source, Analog DAC R1 Source*/
/* MX-2B [4], MX-2B [0]*/
static const char * const rt5682s_alg_dac1_src[] = {
"Stereo1 DAC Mixer", "DAC1"
};
static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
static const unsigned int rt5682s_adcdat_pin_values[] = {
1, 3,
};
static const char * const rt5682s_adcdat_pin_select[] = {
"ADCDAT1", "ADCDAT2",
};
static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
RT5682S_PWR_LDO_BIT, 0, NULL, 0),
/* PLL Powers */
SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PLLB", SND_SOC_NOPM, 0, 0,
set_pllb_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
RT5682S_AD_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
RT5682S_DA_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
/* Input Side */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
RT5682S_PWR_MB1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
RT5682S_PWR_MB2_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
ARRAY_SIZE(rt5682s_rec1_l_mix)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
ARRAY_SIZE(rt5682s_rec1_r_mix)),
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_sto1_adc1l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_sto1_adc1r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_sto1_adc2l_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_sto1_adc2r_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_sto1_adcl_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_sto1_adcr_mux),
SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_if1_adc_slot_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
rt5682s_stereo1_adc_mixl_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", SND_SOC_NOPM, 0, 0,
set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("I2S2", SND_SOC_NOPM, 0, 0,
set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_if1_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_if1_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_if1_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_if1_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5682s_if2_adc_swap_mux),
SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
/* Audio Interface */
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
RT5682S_SEL_ADCDAT_SFT, 1),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
RT5682S_I2S2_PIN_CFG_SFT, 1),
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
/* DAC channel Mux */
SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
/* HPO */
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
/* CLK DET */
SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
/* SAR */
SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
/*PLL*/
{"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
{"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
{"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
{"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
{"PLLA", NULL, "PLLA_LDO"},
{"PLLA", NULL, "PLLA_BIAS"},
{"PLLA", NULL, "PLLA_RST"},
/*ASRC*/
{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
{"ADC STO1 ASRC", NULL, "AD ASRC"},
{"ADC STO1 ASRC", NULL, "DA ASRC"},
{"DAC STO1 ASRC", NULL, "AD ASRC"},
{"DAC STO1 ASRC", NULL, "DA ASRC"},
{"CLKDET SYS", NULL, "MCLK0 DET PWR"},
{"BST1 CBJ", NULL, "IN1P"},
{"BST1 CBJ", NULL, "SAR"},
{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
{"RECMIX1L", NULL, "RECMIX1L Power"},
{"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
{"RECMIX1R", NULL, "RECMIX1R Power"},
{"ADC1 L", NULL, "RECMIX1L"},
{"ADC1 L", NULL, "ADC1 L Power"},
{"ADC1 L", NULL, "ADC1 clock"},
{"ADC1 R", NULL, "RECMIX1R"},
{"ADC1 R", NULL, "ADC1 R Power"},
{"ADC1 R", NULL, "ADC1 clock"},
{"DMIC L1", NULL, "DMIC CLK"},
{"DMIC L1", NULL, "DMIC1 Power"},
{"DMIC R1", NULL, "DMIC CLK"},
{"DMIC R1", NULL, "DMIC1 Power"},
{"DMIC CLK", NULL, "DMIC ASRC"},
{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
{"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
{"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
{"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
{"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
{"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
{"AIF1TX", NULL, "I2S1"},
{"AIF1TX", NULL, "ADCDAT Mux"},
{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
{"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
{"AIF2TX", NULL, "ADCDAT Mux"},
{"IF1 DAC1 L", NULL, "AIF1RX"},
{"IF1 DAC1 L", NULL, "I2S1"},
{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
{"IF1 DAC1 R", NULL, "AIF1RX"},
{"IF1 DAC1 R", NULL, "I2S1"},
{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
{"DAC L1 Source", "DAC1", "DAC1 MIXL"},
{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
{"DAC R1 Source", "DAC1", "DAC1 MIXR"},
{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
{"DAC L1", NULL, "DAC L1 Source"},
{"DAC R1", NULL, "DAC R1 Source"},
{"HP Amp", NULL, "DAC L1"},
{"HP Amp", NULL, "DAC R1"},
{"HP Amp", NULL, "CLKDET SYS"},
{"HP Amp", NULL, "SAR"},
{"HPOL", NULL, "HP Amp"},
{"HPOR", NULL, "HP Amp"},
};
static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int cl, val = 0, tx_slotnum;
if (tx_mask || rx_mask)
snd_soc_component_update_bits(component,
RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
else
snd_soc_component_update_bits(component,
RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0);
/* Tx slot configuration */
tx_slotnum = hweight_long(tx_mask);
if (tx_slotnum) {
if (tx_slotnum > slots) {
dev_err(component->dev, "Invalid or oversized Tx slots.\n");
return -EINVAL;
}
val |= (tx_slotnum - 1) << RT5682S_TDM_ADC_DL_SFT;
}
switch (slots) {
case 4:
val |= RT5682S_TDM_TX_CH_4;
val |= RT5682S_TDM_RX_CH_4;
break;
case 6:
val |= RT5682S_TDM_TX_CH_6;
val |= RT5682S_TDM_RX_CH_6;
break;
case 8:
val |= RT5682S_TDM_TX_CH_8;
val |= RT5682S_TDM_RX_CH_8;
break;
case 2:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK |
RT5682S_TDM_ADC_DL_MASK, val);
switch (slot_width) {
case 8:
if (tx_mask || rx_mask)
return -EINVAL;
cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
break;
case 16:
val = RT5682S_TDM_CL_16;
cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
break;
case 20:
val = RT5682S_TDM_CL_20;
cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
break;
case 24:
val = RT5682S_TDM_CL_24;
cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
break;
case 32:
val = RT5682S_TDM_CL_32;
cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
RT5682S_TDM_CL_MASK, val);
snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl);
return 0;
}
static int rt5682s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
unsigned int len_1 = 0, len_2 = 0;
int frame_size;
rt5682s->lrck[dai->id] = params_rate(params);
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
switch (params_width(params)) {
case 16:
break;
case 20:
len_1 |= RT5682S_I2S1_DL_20;
len_2 |= RT5682S_I2S2_DL_20;
break;
case 24:
len_1 |= RT5682S_I2S1_DL_24;
len_2 |= RT5682S_I2S2_DL_24;
break;
case 32:
len_1 |= RT5682S_I2S1_DL_32;
len_2 |= RT5682S_I2S2_DL_24;
break;
case 8:
len_1 |= RT5682S_I2S2_DL_8;
len_2 |= RT5682S_I2S2_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5682S_AIF1:
snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
RT5682S_I2S1_DL_MASK, len_1);
if (params_channels(params) == 1) /* mono mode */
snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
else
snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
break;
case RT5682S_AIF2:
snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
RT5682S_I2S2_DL_MASK, len_2);
if (params_channels(params) == 1) /* mono mode */
snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
else
snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0, tdm_ctrl = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5682s->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
rt5682s->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5682S_I2S_BP_INV;
tdm_ctrl |= RT5682S_TDM_S_BP_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
if (dai->id == RT5682S_AIF1)
tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
else
return -EINVAL;
break;
case SND_SOC_DAIFMT_IB_IF:
if (dai->id == RT5682S_AIF1)
tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
else
return -EINVAL;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5682S_I2S_DF_LEFT;
tdm_ctrl |= RT5682S_TDM_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5682S_I2S_DF_PCM_A;
tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5682S_I2S_DF_PCM_B;
tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5682S_AIF1:
snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
RT5682S_I2S_DF_MASK, reg_val);
snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
tdm_ctrl | rt5682s->master[dai->id]);
break;
case RT5682S_AIF2:
if (rt5682s->master[dai->id] == 0)
reg_val |= RT5682S_I2S2_MS_S;
snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
RT5682S_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
unsigned int src = 0;
if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
return 0;
switch (clk_id) {
case RT5682S_SCLK_S_MCLK:
src = RT5682S_CLK_SRC_MCLK;
break;
case RT5682S_SCLK_S_PLL1:
src = RT5682S_CLK_SRC_PLL1;
break;
case RT5682S_SCLK_S_PLL2:
src = RT5682S_CLK_SRC_PLL2;
break;
case RT5682S_SCLK_S_RCCLK:
src = RT5682S_CLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT);
snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT);
snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT);
rt5682s->sysclk = freq;
rt5682s->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static const struct pll_calc_map plla_table[] = {
{2048000, 24576000, 0, 46, 2, true, false, false, false},
{256000, 24576000, 0, 382, 2, true, false, false, false},
{512000, 24576000, 0, 190, 2, true, false, false, false},
{4096000, 24576000, 0, 22, 2, true, false, false, false},
{1024000, 24576000, 0, 94, 2, true, false, false, false},
{11289600, 22579200, 1, 22, 2, false, false, false, false},
{1411200, 22579200, 0, 62, 2, true, false, false, false},
{2822400, 22579200, 0, 30, 2, true, false, false, false},
{12288000, 24576000, 1, 22, 2, false, false, false, false},
{1536000, 24576000, 0, 62, 2, true, false, false, false},
{3072000, 24576000, 0, 30, 2, true, false, false, false},
{24576000, 49152000, 4, 22, 0, false, false, false, false},
{3072000, 49152000, 0, 30, 0, true, false, false, false},
{6144000, 49152000, 0, 30, 0, false, false, false, false},
{49152000, 98304000, 10, 22, 0, false, true, false, false},
{6144000, 98304000, 0, 30, 0, false, true, false, false},
{12288000, 98304000, 1, 22, 0, false, true, false, false},
{48000000, 3840000, 10, 22, 23, false, false, false, false},
{24000000, 3840000, 4, 22, 23, false, false, false, false},
{19200000, 3840000, 3, 23, 23, false, false, false, false},
{38400000, 3840000, 8, 23, 23, false, false, false, false},
};
static const struct pll_calc_map pllb_table[] = {
{48000000, 24576000, 8, 6, 3, false, false, false, false},
{48000000, 22579200, 23, 12, 3, false, false, false, true},
{24000000, 24576000, 3, 6, 3, false, false, false, false},
{24000000, 22579200, 23, 26, 3, false, false, false, true},
{19200000, 24576000, 2, 6, 3, false, false, false, false},
{19200000, 22579200, 3, 5, 3, false, false, false, true},
{38400000, 24576000, 6, 6, 3, false, false, false, false},
{38400000, 22579200, 8, 5, 3, false, false, false, true},
{3840000, 49152000, 0, 6, 0, true, false, false, false},
};
static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
struct pll_calc_map *a, struct pll_calc_map *b)
{
int i, j;
/* Look at PLLA table */
for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
memcpy(a, plla_table + i, sizeof(*a));
return USE_PLLA;
}
}
/* Look at PLLB table */
for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
memcpy(b, pllb_table + i, sizeof(*b));
return USE_PLLB;
}
}
/* Find a combination of PLLA & PLLB */
for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
if (pllb_table[j].freq_in == 3840000 &&
pllb_table[j].freq_out == f_out) {
memcpy(a, plla_table + i, sizeof(*a));
memcpy(b, pllb_table + j, sizeof(*b));
return USE_PLLAB;
}
}
}
}
return -EINVAL;
}
static int rt5682s_set_component_pll(struct snd_soc_component *component,
int pll_id, int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
struct pll_calc_map a_map, b_map;
if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
freq_out == rt5682s->pll_out[pll_id])
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5682s->pll_in[pll_id] = 0;
rt5682s->pll_out[pll_id] = 0;
snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
return 0;
}
switch (source) {
case RT5682S_PLL_S_MCLK:
snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
break;
case RT5682S_PLL_S_BCLK1:
snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
break;
default:
dev_err(component->dev, "Unknown PLL Source %d\n", source);
return -EINVAL;
}
rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
&a_map, &b_map);
if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
(pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
rt5682s->pll_comb == USE_PLLAB))) {
dev_dbg(component->dev,
"Supported freq conversion for PLL%d:(%d->%d): %d\n",
pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
} else {
dev_err(component->dev,
"Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
return -EINVAL;
}
if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
dev_dbg(component->dev,
"PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
(a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
RT5682S_PLLA_N_MASK, a_map.n);
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
}
if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
dev_dbg(component->dev,
"PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
(b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
b_map.byp_ps, b_map.sel_ps);
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
RT5682S_PLLB_N_MASK, b_map.n);
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
}
if (rt5682s->pll_comb == USE_PLLB)
snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
rt5682s->pll_in[pll_id] = freq_in;
rt5682s->pll_out[pll_id] = freq_out;
rt5682s->pll_src[pll_id] = source;
return 0;
}
static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
rt5682s->bclk[dai->id] = ratio;
switch (ratio) {
case 256:
snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
break;
case 128:
snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
break;
case 64:
snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
break;
case 32:
snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
break;
default:
dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
return -EINVAL;
}
return 0;
}
static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
rt5682s->bclk[dai->id] = ratio;
switch (ratio) {
case 64:
snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
break;
case 32:
snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
break;
default:
dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
return -EINVAL;
}
return 0;
}
static int rt5682s_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
RT5682S_PWR_LDO, RT5682S_PWR_LDO);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, RT5682S_PWR_LDO, 0);
if (!rt5682s->wclk_enabled)
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
RT5682S_DIG_GATE_CTRL, 0);
break;
case SND_SOC_BIAS_ON:
break;
}
return 0;
}
#ifdef CONFIG_COMMON_CLK
#define CLK_PLL2_FIN 48000000
#define CLK_48 48000
#define CLK_44 44100
static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
{
if (!rt5682s->master[RT5682S_AIF1]) {
dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
return false;
}
return true;
}
static int rt5682s_wclk_prepare(struct clk_hw *hw)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
int ref, reg;
if (!rt5682s_clk_check(rt5682s))
return -EINVAL;
mutex_lock(&rt5682s->wclk_mutex);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB,
RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
usleep_range(15000, 20000);
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_FV2, RT5682S_PWR_FV2);
/* Set and power on I2S1 */
snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
rt5682s_set_i2s(rt5682s, RT5682S_AIF1, 1);
/* Only need to power on PLLB due to the rate set restriction */
reg = RT5682S_PLL_TRACK_2;
ref = 256 * rt5682s->lrck[RT5682S_AIF1];
rt5682s_set_filter_clk(rt5682s, reg, ref);
rt5682s_set_pllb_power(rt5682s, 1);
rt5682s->wclk_enabled = 1;
mutex_unlock(&rt5682s->wclk_mutex);
return 0;
}
static void rt5682s_wclk_unprepare(struct clk_hw *hw)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
if (!rt5682s_clk_check(rt5682s))
return;
mutex_lock(&rt5682s->wclk_mutex);
if (!rt5682s->jack_type)
snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0);
/* Power down I2S1 */
rt5682s_set_i2s(rt5682s, RT5682S_AIF1, 0);
snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
RT5682S_DIG_GATE_CTRL, 0);
/* Power down PLLB */
rt5682s_set_pllb_power(rt5682s, 0);
rt5682s->wclk_enabled = 0;
mutex_unlock(&rt5682s->wclk_mutex);
}
static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
const char * const clk_name = clk_hw_get_name(hw);
if (!rt5682s_clk_check(rt5682s))
return 0;
/*
* Only accept to set wclk rate to 44.1k or 48kHz.
*/
if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
__func__, clk_name, CLK_44, CLK_48);
return 0;
}
return rt5682s->lrck[RT5682S_AIF1];
}
static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
const char * const clk_name = clk_hw_get_name(hw);
if (!rt5682s_clk_check(rt5682s))
return -EINVAL;
/*
* Only accept to set wclk rate to 44.1k or 48kHz.
* It will force to 48kHz if not both.
*/
if (rate != CLK_48 && rate != CLK_44) {
dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
__func__, clk_name, CLK_44, CLK_48);
rate = CLK_48;
}
return rate;
}
static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
struct clk *parent_clk;
const char * const clk_name = clk_hw_get_name(hw);
unsigned int clk_pll2_fout;
if (!rt5682s_clk_check(rt5682s))
return -EINVAL;
/*
* Whether the wclk's parent clk (mclk) exists or not, please ensure
* it is fixed or set to 48MHz before setting wclk rate. It's a
* temporary limitation. Only accept 48MHz clk as the clk provider.
*
* It will set the codec anyway by assuming mclk is 48MHz.
*/
parent_clk = clk_get_parent(hw->clk);
if (!parent_clk)
dev_warn(component->dev,
"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
CLK_PLL2_FIN);
if (parent_rate != CLK_PLL2_FIN)
dev_warn(component->dev, "clk %s only support %d Hz input\n",
clk_name, CLK_PLL2_FIN);
/*
* To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
* PLL2 is needed.
*/
clk_pll2_fout = rate * 512;
rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
CLK_PLL2_FIN, clk_pll2_fout);
rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0,
clk_pll2_fout, SND_SOC_CLOCK_IN);
rt5682s->lrck[RT5682S_AIF1] = rate;
return 0;
}
static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
unsigned int bclks_per_wclk;
bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
case RT5682S_TDM_BCLK_MS1_256:
return parent_rate * 256;
case RT5682S_TDM_BCLK_MS1_128:
return parent_rate * 128;
case RT5682S_TDM_BCLK_MS1_64:
return parent_rate * 64;
case RT5682S_TDM_BCLK_MS1_32:
return parent_rate * 32;
default:
return 0;
}
}
static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
unsigned long parent_rate)
{
unsigned long factor;
factor = rate / parent_rate;
if (factor < 64)
return 32;
else if (factor < 128)
return 64;
else if (factor < 256)
return 128;
else
return 256;
}
static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
unsigned long factor;
if (!*parent_rate || !rt5682s_clk_check(rt5682s))
return -EINVAL;
/*
* BCLK rates are set as a multiplier of WCLK in HW.
* We don't allow changing the parent WCLK. We just do
* some rounding down based on the parent WCLK rate
* and find the appropriate multiplier of BCLK to
* get the rounded down BCLK value.
*/
factor = rt5682s_bclk_get_factor(rate, *parent_rate);
return *parent_rate * factor;
}
static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct rt5682s_priv *rt5682s =
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
struct snd_soc_component *component = rt5682s->component;
struct snd_soc_dai *dai;
unsigned long factor;
if (!rt5682s_clk_check(rt5682s))
return -EINVAL;
factor = rt5682s_bclk_get_factor(rate, parent_rate);
for_each_component_dais(component, dai)
if (dai->id == RT5682S_AIF1)
return rt5682s_set_bclk1_ratio(dai, factor);
dev_err(component->dev, "dai %d not found in component\n",
RT5682S_AIF1);
return -ENODEV;
}
static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
[RT5682S_DAI_WCLK_IDX] = {
.prepare = rt5682s_wclk_prepare,
.unprepare = rt5682s_wclk_unprepare,
.recalc_rate = rt5682s_wclk_recalc_rate,
.round_rate = rt5682s_wclk_round_rate,
.set_rate = rt5682s_wclk_set_rate,
},
[RT5682S_DAI_BCLK_IDX] = {
.recalc_rate = rt5682s_bclk_recalc_rate,
.round_rate = rt5682s_bclk_round_rate,
.set_rate = rt5682s_bclk_set_rate,
},
};
static int rt5682s_register_dai_clks(struct snd_soc_component *component)
{
struct device *dev = component->dev;
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
struct rt5682s_platform_data *pdata = &rt5682s->pdata;
struct clk_hw *dai_clk_hw;
int i, ret;
for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
struct clk_init_data init = { };
struct clk_parent_data parent_data;
const struct clk_hw *parent;
dai_clk_hw = &rt5682s->dai_clks_hw[i];
switch (i) {
case RT5682S_DAI_WCLK_IDX:
/* Make MCLK the parent of WCLK */
if (rt5682s->mclk) {
parent_data = (struct clk_parent_data){
.fw_name = "mclk",
};
init.parent_data = &parent_data;
init.num_parents = 1;
}
break;
case RT5682S_DAI_BCLK_IDX:
/* Make WCLK the parent of BCLK */
parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
init.parent_hws = &parent;
init.num_parents = 1;
break;
default:
dev_err(dev, "Invalid clock index\n");
return -EINVAL;
}
init.name = pdata->dai_clk_names[i];
init.ops = &rt5682s_dai_clk_ops[i];
init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
dai_clk_hw->init = &init;
ret = devm_clk_hw_register(dev, dai_clk_hw);
if (ret) {
dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
return ret;
}
if (dev->of_node) {
devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw);
} else {
ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
init.name, dev_name(dev));
if (ret)
return ret;
}
}
return 0;
}
static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
int ret;
/* Check if MCLK provided */
rt5682s->mclk = devm_clk_get_optional(component->dev, "mclk");
if (IS_ERR(rt5682s->mclk))
return PTR_ERR(rt5682s->mclk);
/* Register CCF DAI clock control */
ret = rt5682s_register_dai_clks(component);
if (ret)
return ret;
/* Initial setup for CCF */
rt5682s->lrck[RT5682S_AIF1] = CLK_48;
return 0;
}
#else
static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
{
return 0;
}
#endif /* CONFIG_COMMON_CLK */
static int rt5682s_probe(struct snd_soc_component *component)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
rt5682s->component = component;
return rt5682s_dai_probe_clks(component);
}
static void rt5682s_remove(struct snd_soc_component *component)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
rt5682s_reset(rt5682s);
}
#ifdef CONFIG_PM
static int rt5682s_suspend(struct snd_soc_component *component)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
if (rt5682s->irq)
disable_irq(rt5682s->irq);
cancel_delayed_work_sync(&rt5682s->jack_detect_work);
cancel_delayed_work_sync(&rt5682s->jd_check_work);
if (rt5682s->hs_jack)
rt5682s->jack_type = rt5682s_headset_detect(component, 0);
regcache_cache_only(rt5682s->regmap, true);
regcache_mark_dirty(rt5682s->regmap);
return 0;
}
static int rt5682s_resume(struct snd_soc_component *component)
{
struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5682s->regmap, false);
regcache_sync(rt5682s->regmap);
if (rt5682s->hs_jack) {
mod_delayed_work(system_power_efficient_wq,
&rt5682s->jack_detect_work, msecs_to_jiffies(0));
}
if (rt5682s->irq)
enable_irq(rt5682s->irq);
return 0;
}
#else
#define rt5682s_suspend NULL
#define rt5682s_resume NULL
#endif
static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
.hw_params = rt5682s_hw_params,
.set_fmt = rt5682s_set_dai_fmt,
.set_tdm_slot = rt5682s_set_tdm_slot,
.set_bclk_ratio = rt5682s_set_bclk1_ratio,
};
static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
.hw_params = rt5682s_hw_params,
.set_fmt = rt5682s_set_dai_fmt,
.set_bclk_ratio = rt5682s_set_bclk2_ratio,
};
static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
.probe = rt5682s_probe,
.remove = rt5682s_remove,
.suspend = rt5682s_suspend,
.resume = rt5682s_resume,
.set_bias_level = rt5682s_set_bias_level,
.controls = rt5682s_snd_controls,
.num_controls = ARRAY_SIZE(rt5682s_snd_controls),
.dapm_widgets = rt5682s_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
.dapm_routes = rt5682s_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
.set_sysclk = rt5682s_set_component_sysclk,
.set_pll = rt5682s_set_component_pll,
.set_jack = rt5682s_set_jack_detect,
.use_pmdown_time = 1,
.endianness = 1,
};
static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
{
device_property_read_u32(dev, "realtek,dmic1-data-pin",
&rt5682s->pdata.dmic1_data_pin);
device_property_read_u32(dev, "realtek,dmic1-clk-pin",
&rt5682s->pdata.dmic1_clk_pin);
device_property_read_u32(dev, "realtek,jd-src",
&rt5682s->pdata.jd_src);
device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
&rt5682s->pdata.dmic_clk_rate);
device_property_read_u32(dev, "realtek,dmic-delay-ms",
&rt5682s->pdata.dmic_delay);
device_property_read_u32(dev, "realtek,amic-delay-ms",
&rt5682s->pdata.amic_delay);
if (device_property_read_string_array(dev, "clock-output-names",
rt5682s->pdata.dai_clk_names,
RT5682S_DAI_NUM_CLKS) < 0)
dev_warn(dev, "Using default DAI clk names: %s, %s\n",
rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
"realtek,dmic-clk-driving-high");
return 0;
}
static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
{
unsigned int count, value;
mutex_lock(&rt5682s->calibrate_mutex);
regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
usleep_range(15000, 20000);
regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
for (count = 0; count < 60; count++) {
regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
if (!(value & 0x8000))
break;
usleep_range(10000, 10005);
}
if (count >= 60)
dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
/* restore settings */
regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
mutex_unlock(&rt5682s->calibrate_mutex);
}
static const struct regmap_config rt5682s_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = RT5682S_MAX_REG,
.volatile_reg = rt5682s_volatile_register,
.readable_reg = rt5682s_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = rt5682s_reg,
.num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
.use_single_read = true,
.use_single_write = true,
};
static struct snd_soc_dai_driver rt5682s_dai[] = {
{
.name = "rt5682s-aif1",
.id = RT5682S_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682S_STEREO_RATES,
.formats = RT5682S_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682S_STEREO_RATES,
.formats = RT5682S_FORMATS,
},
.ops = &rt5682s_aif1_dai_ops,
},
{
.name = "rt5682s-aif2",
.id = RT5682S_AIF2,
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5682S_STEREO_RATES,
.formats = RT5682S_FORMATS,
},
.ops = &rt5682s_aif2_dai_ops,
},
};
static void rt5682s_i2c_disable_regulators(void *data)
{
struct rt5682s_priv *rt5682s = data;
struct device *dev = regmap_get_device(rt5682s->regmap);
int ret;
ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
if (ret)
dev_err(dev, "Failed to disable supply AVDD: %d\n", ret);
ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
if (ret)
dev_err(dev, "Failed to disable supply DBVDD: %d\n", ret);
ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
if (ret)
dev_err(dev, "Failed to disable supply LDO1-IN: %d\n", ret);
usleep_range(1000, 1500);
ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
if (ret)
dev_err(dev, "Failed to disable supply MICVDD: %d\n", ret);
}
static int rt5682s_i2c_probe(struct i2c_client *i2c)
{
struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5682s_priv *rt5682s;
int i, ret;
unsigned int val;
rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
if (!rt5682s)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5682s);
rt5682s->pdata = i2s_default_platform_data;
if (pdata)
rt5682s->pdata = *pdata;
else
rt5682s_parse_dt(rt5682s, &i2c->dev);
rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
if (IS_ERR(rt5682s->regmap)) {
ret = PTR_ERR(rt5682s->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
rt5682s->supplies[i].supply = rt5682s_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev,
ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
if (ret) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
if (ret)
return ret;
ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
return ret;
}
usleep_range(1000, 1500);
ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
return ret;
}
ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supply DBVDD: %d\n", ret);
return ret;
}
ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
if (ret) {
dev_err(&i2c->dev, "Failed to enable supply LDO1-IN: %d\n", ret);
return ret;
}
rt5682s->ldo1_en = devm_gpiod_get_optional(&i2c->dev,
"realtek,ldo1-en",
GPIOD_OUT_HIGH);
if (IS_ERR(rt5682s->ldo1_en)) {
dev_err(&i2c->dev, "Fail gpio request ldo1_en\n");
return PTR_ERR(rt5682s->ldo1_en);
}
/* Sleep for 50 ms minimum */
usleep_range(50000, 55000);
regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
if (val != DEVICE_ID) {
dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
return -ENODEV;
}
rt5682s_reset(rt5682s);
rt5682s_apply_patch_list(rt5682s, &i2c->dev);
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
usleep_range(20000, 25000);
mutex_init(&rt5682s->calibrate_mutex);
mutex_init(&rt5682s->sar_mutex);
mutex_init(&rt5682s->wclk_mutex);
rt5682s_calibrate(rt5682s);
regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
RT5682S_PWR_BG, RT5682S_PWR_BG);
regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
/* DMIC data pin */
switch (rt5682s->pdata.dmic1_data_pin) {
case RT5682S_DMIC1_DATA_NULL:
break;
case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
break;
case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
break;
default:
dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
break;
}
/* DMIC clk pin */
switch (rt5682s->pdata.dmic1_clk_pin) {
case RT5682S_DMIC1_CLK_NULL:
break;
case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
break;
case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
if (rt5682s->pdata.dmic_clk_driving_high)
regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
break;
default:
dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
break;
}
INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
if (i2c->irq) {
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"rt5682s", rt5682s);
if (!ret)
rt5682s->irq = i2c->irq;
else
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
}
return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
}
static void rt5682s_i2c_shutdown(struct i2c_client *client)
{
struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
disable_irq(client->irq);
cancel_delayed_work_sync(&rt5682s->jack_detect_work);
cancel_delayed_work_sync(&rt5682s->jd_check_work);
rt5682s_reset(rt5682s);
}
static void rt5682s_i2c_remove(struct i2c_client *client)
{
rt5682s_i2c_shutdown(client);
}
static const struct of_device_id rt5682s_of_match[] = {
{.compatible = "realtek,rt5682s"},
{},
};
MODULE_DEVICE_TABLE(of, rt5682s_of_match);
static const struct acpi_device_id rt5682s_acpi_match[] = {
{"RTL5682", 0,},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
static const struct i2c_device_id rt5682s_i2c_id[] = {
{"rt5682s", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
static struct i2c_driver rt5682s_i2c_driver = {
.driver = {
.name = "rt5682s",
.of_match_table = rt5682s_of_match,
.acpi_match_table = rt5682s_acpi_match,
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = rt5682s_i2c_probe,
.remove = rt5682s_i2c_remove,
.shutdown = rt5682s_i2c_shutdown,
.id_table = rt5682s_i2c_id,
};
module_i2c_driver(rt5682s_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
MODULE_AUTHOR("Derek Fang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5682s.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// CS35L56 ALSA SoC audio driver SPI binding
//
// Copyright (C) 2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/types.h>
#include "cs35l56.h"
static int cs35l56_spi_probe(struct spi_device *spi)
{
const struct regmap_config *regmap_config = &cs35l56_regmap_spi;
struct cs35l56_private *cs35l56;
int ret;
cs35l56 = devm_kzalloc(&spi->dev, sizeof(struct cs35l56_private), GFP_KERNEL);
if (!cs35l56)
return -ENOMEM;
spi_set_drvdata(spi, cs35l56);
cs35l56->base.regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l56->base.regmap)) {
ret = PTR_ERR(cs35l56->base.regmap);
return dev_err_probe(&spi->dev, ret, "Failed to allocate register map\n");
}
cs35l56->base.dev = &spi->dev;
ret = cs35l56_common_probe(cs35l56);
if (ret != 0)
return ret;
ret = cs35l56_init(cs35l56);
if (ret == 0)
ret = cs35l56_irq_request(&cs35l56->base, spi->irq);
if (ret < 0)
cs35l56_remove(cs35l56);
return ret;
}
static void cs35l56_spi_remove(struct spi_device *spi)
{
struct cs35l56_private *cs35l56 = spi_get_drvdata(spi);
cs35l56_remove(cs35l56);
}
static const struct spi_device_id cs35l56_id_spi[] = {
{ "cs35l56", 0 },
{}
};
MODULE_DEVICE_TABLE(spi, cs35l56_id_spi);
#ifdef CONFIG_ACPI
static const struct acpi_device_id cs35l56_asoc_acpi_match[] = {
{ "CSC355C", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, cs35l56_asoc_acpi_match);
#endif
static struct spi_driver cs35l56_spi_driver = {
.driver = {
.name = "cs35l56",
.pm = &cs35l56_pm_ops_i2c_spi,
.acpi_match_table = ACPI_PTR(cs35l56_asoc_acpi_match),
},
.id_table = cs35l56_id_spi,
.probe = cs35l56_spi_probe,
.remove = cs35l56_spi_remove,
};
module_spi_driver(cs35l56_spi_driver);
MODULE_DESCRIPTION("ASoC CS35L56 SPI driver");
MODULE_IMPORT_NS(SND_SOC_CS35L56_CORE);
MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED);
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_AUTHOR("Simon Trimmer <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l56-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8962.c -- WM8962 ALSA SoC Audio driver
*
* Copyright 2010-2 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gcd.h>
#include <linux/gpio/driver.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/wm8962.h>
#include <trace/events/asoc.h>
#include "wm8962.h"
#define WM8962_NUM_SUPPLIES 8
static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD",
"CPVDD",
"MICVDD",
"PLLVDD",
"SPKVDD1",
"SPKVDD2",
};
/* codec private data */
struct wm8962_priv {
struct wm8962_pdata pdata;
struct regmap *regmap;
struct snd_soc_component *component;
int sysclk;
int sysclk_rate;
int bclk; /* Desired BCLK */
int lrclk;
struct completion fll_lock;
int fll_src;
int fll_fref;
int fll_fout;
struct mutex dsp2_ena_lock;
u16 dsp2_ena;
struct delayed_work mic_work;
struct snd_soc_jack *jack;
struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
struct input_dev *beep;
struct work_struct beep_work;
int beep_rate;
#ifdef CONFIG_GPIOLIB
struct gpio_chip gpio_chip;
#endif
int irq;
};
/* We can't use the same notifier block for more than one supply and
* there's no way I can see to get from a callback to the caller
* except container_of().
*/
#define WM8962_REGULATOR_EVENT(n) \
static int wm8962_regulator_event_##n(struct notifier_block *nb, \
unsigned long event, void *data) \
{ \
struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
disable_nb[n]); \
if (event & REGULATOR_EVENT_DISABLE) { \
regcache_mark_dirty(wm8962->regmap); \
} \
return 0; \
}
WM8962_REGULATOR_EVENT(0)
WM8962_REGULATOR_EVENT(1)
WM8962_REGULATOR_EVENT(2)
WM8962_REGULATOR_EVENT(3)
WM8962_REGULATOR_EVENT(4)
WM8962_REGULATOR_EVENT(5)
WM8962_REGULATOR_EVENT(6)
WM8962_REGULATOR_EVENT(7)
static const struct reg_default wm8962_reg[] = {
{ 0, 0x009F }, /* R0 - Left Input volume */
{ 1, 0x049F }, /* R1 - Right Input volume */
{ 2, 0x0000 }, /* R2 - HPOUTL volume */
{ 3, 0x0000 }, /* R3 - HPOUTR volume */
{ 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
{ 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
{ 7, 0x000A }, /* R7 - Audio Interface 0 */
{ 8, 0x01E4 }, /* R8 - Clocking2 */
{ 9, 0x0300 }, /* R9 - Audio Interface 1 */
{ 10, 0x00C0 }, /* R10 - Left DAC volume */
{ 11, 0x00C0 }, /* R11 - Right DAC volume */
{ 14, 0x0040 }, /* R14 - Audio Interface 2 */
{ 15, 0x6243 }, /* R15 - Software Reset */
{ 17, 0x007B }, /* R17 - ALC1 */
{ 18, 0x0000 }, /* R18 - ALC2 */
{ 19, 0x1C32 }, /* R19 - ALC3 */
{ 20, 0x3200 }, /* R20 - Noise Gate */
{ 21, 0x00C0 }, /* R21 - Left ADC volume */
{ 22, 0x00C0 }, /* R22 - Right ADC volume */
{ 23, 0x0160 }, /* R23 - Additional control(1) */
{ 24, 0x0000 }, /* R24 - Additional control(2) */
{ 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
{ 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
{ 27, 0x0010 }, /* R27 - Additional Control (3) */
{ 28, 0x0000 }, /* R28 - Anti-pop */
{ 30, 0x005E }, /* R30 - Clocking 3 */
{ 31, 0x0000 }, /* R31 - Input mixer control (1) */
{ 32, 0x0145 }, /* R32 - Left input mixer volume */
{ 33, 0x0145 }, /* R33 - Right input mixer volume */
{ 34, 0x0009 }, /* R34 - Input mixer control (2) */
{ 35, 0x0003 }, /* R35 - Input bias control */
{ 37, 0x0008 }, /* R37 - Left input PGA control */
{ 38, 0x0008 }, /* R38 - Right input PGA control */
{ 40, 0x0000 }, /* R40 - SPKOUTL volume */
{ 41, 0x0000 }, /* R41 - SPKOUTR volume */
{ 49, 0x0010 }, /* R49 - Class D Control 1 */
{ 51, 0x0003 }, /* R51 - Class D Control 2 */
{ 56, 0x0506 }, /* R56 - Clocking 4 */
{ 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
{ 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
{ 60, 0x0300 }, /* R60 - DC Servo 0 */
{ 61, 0x0300 }, /* R61 - DC Servo 1 */
{ 64, 0x0810 }, /* R64 - DC Servo 4 */
{ 68, 0x001B }, /* R68 - Analogue PGA Bias */
{ 69, 0x0000 }, /* R69 - Analogue HP 0 */
{ 71, 0x01FB }, /* R71 - Analogue HP 2 */
{ 72, 0x0000 }, /* R72 - Charge Pump 1 */
{ 82, 0x0004 }, /* R82 - Charge Pump B */
{ 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
{ 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
{ 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
{ 94, 0x0000 }, /* R94 - Control Interface */
{ 99, 0x0000 }, /* R99 - Mixer Enables */
{ 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
{ 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
{ 102, 0x013F }, /* R102 - Headphone Mixer (3) */
{ 103, 0x013F }, /* R103 - Headphone Mixer (4) */
{ 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
{ 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
{ 107, 0x013F }, /* R107 - Speaker Mixer (3) */
{ 108, 0x013F }, /* R108 - Speaker Mixer (4) */
{ 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
{ 110, 0x0002 }, /* R110 - Beep Generator (1) */
{ 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
{ 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
{ 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
{ 124, 0x0011 }, /* R124 - Analogue Clocking1 */
{ 125, 0x004B }, /* R125 - Analogue Clocking2 */
{ 126, 0x000D }, /* R126 - Analogue Clocking3 */
{ 127, 0x0000 }, /* R127 - PLL Software Reset */
{ 131, 0x0000 }, /* R131 - PLL 4 */
{ 136, 0x0067 }, /* R136 - PLL 9 */
{ 137, 0x001C }, /* R137 - PLL 10 */
{ 138, 0x0071 }, /* R138 - PLL 11 */
{ 139, 0x00C7 }, /* R139 - PLL 12 */
{ 140, 0x0067 }, /* R140 - PLL 13 */
{ 141, 0x0048 }, /* R141 - PLL 14 */
{ 142, 0x0022 }, /* R142 - PLL 15 */
{ 143, 0x0097 }, /* R143 - PLL 16 */
{ 155, 0x000C }, /* R155 - FLL Control (1) */
{ 156, 0x0039 }, /* R156 - FLL Control (2) */
{ 157, 0x0180 }, /* R157 - FLL Control (3) */
{ 159, 0x0032 }, /* R159 - FLL Control (5) */
{ 160, 0x0018 }, /* R160 - FLL Control (6) */
{ 161, 0x007D }, /* R161 - FLL Control (7) */
{ 162, 0x0008 }, /* R162 - FLL Control (8) */
{ 252, 0x0005 }, /* R252 - General test 1 */
{ 256, 0x0000 }, /* R256 - DF1 */
{ 257, 0x0000 }, /* R257 - DF2 */
{ 258, 0x0000 }, /* R258 - DF3 */
{ 259, 0x0000 }, /* R259 - DF4 */
{ 260, 0x0000 }, /* R260 - DF5 */
{ 261, 0x0000 }, /* R261 - DF6 */
{ 262, 0x0000 }, /* R262 - DF7 */
{ 264, 0x0000 }, /* R264 - LHPF1 */
{ 265, 0x0000 }, /* R265 - LHPF2 */
{ 268, 0x0000 }, /* R268 - THREED1 */
{ 269, 0x0000 }, /* R269 - THREED2 */
{ 270, 0x0000 }, /* R270 - THREED3 */
{ 271, 0x0000 }, /* R271 - THREED4 */
{ 276, 0x000C }, /* R276 - DRC 1 */
{ 277, 0x0925 }, /* R277 - DRC 2 */
{ 278, 0x0000 }, /* R278 - DRC 3 */
{ 279, 0x0000 }, /* R279 - DRC 4 */
{ 280, 0x0000 }, /* R280 - DRC 5 */
{ 285, 0x0000 }, /* R285 - Tloopback */
{ 335, 0x0004 }, /* R335 - EQ1 */
{ 336, 0x6318 }, /* R336 - EQ2 */
{ 337, 0x6300 }, /* R337 - EQ3 */
{ 338, 0x0FCA }, /* R338 - EQ4 */
{ 339, 0x0400 }, /* R339 - EQ5 */
{ 340, 0x00D8 }, /* R340 - EQ6 */
{ 341, 0x1EB5 }, /* R341 - EQ7 */
{ 342, 0xF145 }, /* R342 - EQ8 */
{ 343, 0x0B75 }, /* R343 - EQ9 */
{ 344, 0x01C5 }, /* R344 - EQ10 */
{ 345, 0x1C58 }, /* R345 - EQ11 */
{ 346, 0xF373 }, /* R346 - EQ12 */
{ 347, 0x0A54 }, /* R347 - EQ13 */
{ 348, 0x0558 }, /* R348 - EQ14 */
{ 349, 0x168E }, /* R349 - EQ15 */
{ 350, 0xF829 }, /* R350 - EQ16 */
{ 351, 0x07AD }, /* R351 - EQ17 */
{ 352, 0x1103 }, /* R352 - EQ18 */
{ 353, 0x0564 }, /* R353 - EQ19 */
{ 354, 0x0559 }, /* R354 - EQ20 */
{ 355, 0x4000 }, /* R355 - EQ21 */
{ 356, 0x6318 }, /* R356 - EQ22 */
{ 357, 0x6300 }, /* R357 - EQ23 */
{ 358, 0x0FCA }, /* R358 - EQ24 */
{ 359, 0x0400 }, /* R359 - EQ25 */
{ 360, 0x00D8 }, /* R360 - EQ26 */
{ 361, 0x1EB5 }, /* R361 - EQ27 */
{ 362, 0xF145 }, /* R362 - EQ28 */
{ 363, 0x0B75 }, /* R363 - EQ29 */
{ 364, 0x01C5 }, /* R364 - EQ30 */
{ 365, 0x1C58 }, /* R365 - EQ31 */
{ 366, 0xF373 }, /* R366 - EQ32 */
{ 367, 0x0A54 }, /* R367 - EQ33 */
{ 368, 0x0558 }, /* R368 - EQ34 */
{ 369, 0x168E }, /* R369 - EQ35 */
{ 370, 0xF829 }, /* R370 - EQ36 */
{ 371, 0x07AD }, /* R371 - EQ37 */
{ 372, 0x1103 }, /* R372 - EQ38 */
{ 373, 0x0564 }, /* R373 - EQ39 */
{ 374, 0x0559 }, /* R374 - EQ40 */
{ 375, 0x4000 }, /* R375 - EQ41 */
{ 513, 0x0000 }, /* R513 - GPIO 2 */
{ 514, 0x0000 }, /* R514 - GPIO 3 */
{ 516, 0x8100 }, /* R516 - GPIO 5 */
{ 517, 0x8100 }, /* R517 - GPIO 6 */
{ 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
{ 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
{ 576, 0x0000 }, /* R576 - Interrupt Control */
{ 584, 0x002D }, /* R584 - IRQ Debounce */
{ 586, 0x0000 }, /* R586 - MICINT Source Pol */
{ 768, 0x1C00 }, /* R768 - DSP2 Power Management */
{ 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
{ 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
{ 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
{ 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
{ 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
{ 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
{ 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
{ 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
{ 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
{ 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
{ 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
{ 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
{ 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
{ 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
{ 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
{ 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
{ 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
{ 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
{ 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
{ 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
{ 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
{ 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
{ 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
{ 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
{ 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
{ 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
{ 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
{ 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
{ 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
{ 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
{ 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
{ 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
{ 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
{ 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
{ 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
{ 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
{ 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
{ 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
{ 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
{ 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
{ 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
{ 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
{ 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
{ 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
{ 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
{ 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
{ 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
{ 17408, 0x0083 }, /* R17408 - HPF_C_1 */
{ 17409, 0x98AD }, /* R17409 - HPF_C_0 */
{ 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
{ 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
{ 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
{ 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
{ 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
{ 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
{ 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
{ 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
{ 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
{ 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
{ 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
{ 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
{ 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
{ 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
{ 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
{ 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
{ 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
{ 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
{ 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
{ 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
{ 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
{ 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
{ 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
{ 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
{ 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
{ 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
{ 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
{ 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
{ 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
{ 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
{ 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
{ 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
{ 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
{ 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
{ 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
{ 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
{ 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
{ 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
{ 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
{ 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
{ 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
{ 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
{ 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
{ 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
{ 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
{ 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
{ 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
{ 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
{ 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
{ 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
{ 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
{ 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
{ 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
{ 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
{ 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
{ 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
{ 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
{ 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
{ 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
{ 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
{ 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
{ 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
{ 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
{ 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
{ 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
{ 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
{ 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
{ 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
{ 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
{ 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
{ 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
{ 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
{ 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
{ 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
{ 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
{ 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
{ 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
{ 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
{ 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
{ 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
{ 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
{ 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
{ 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
{ 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
{ 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
{ 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
{ 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
{ 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
{ 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
{ 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
{ 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
{ 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
{ 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
{ 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
{ 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
{ 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
{ 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
{ 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
{ 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
{ 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
{ 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
{ 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
{ 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
{ 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
{ 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
{ 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
{ 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
{ 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
{ 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
{ 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
{ 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
{ 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
{ 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
{ 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
{ 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
{ 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
{ 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
{ 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
{ 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
{ 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
{ 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
{ 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
{ 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
{ 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
{ 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
{ 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
{ 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
{ 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
{ 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
{ 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
{ 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
{ 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
{ 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
{ 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
{ 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
{ 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
{ 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
{ 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
{ 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
{ 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
{ 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
{ 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
{ 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
{ 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
{ 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
{ 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
{ 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
{ 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
{ 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
{ 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
{ 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
{ 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
{ 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
{ 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
{ 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
{ 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
{ 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
{ 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
{ 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
{ 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
{ 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
{ 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
{ 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
{ 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
{ 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
{ 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
{ 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
{ 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
{ 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
{ 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
{ 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
{ 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
{ 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
{ 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
{ 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
{ 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
{ 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
{ 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
{ 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
{ 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
{ 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
{ 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
{ 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
{ 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
{ 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
{ 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
{ 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
{ 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
{ 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
{ 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
{ 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
{ 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
{ 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
{ 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
{ 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
{ 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
{ 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
{ 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
{ 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
{ 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
{ 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
{ 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
{ 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
{ 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
{ 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
{ 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
{ 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
{ 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
{ 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
{ 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
{ 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
{ 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
{ 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
{ 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
{ 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
{ 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
{ 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
{ 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
{ 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
{ 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
{ 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
{ 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
{ 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
{ 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
{ 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
{ 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
{ 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
{ 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
{ 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
{ 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
{ 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
{ 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
{ 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
{ 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
{ 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
{ 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
{ 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
{ 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
{ 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
{ 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
{ 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
{ 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
{ 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
{ 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
{ 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
{ 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
{ 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
{ 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
{ 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
{ 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
{ 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
{ 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
{ 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
{ 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
{ 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
{ 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
{ 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
{ 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
{ 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
{ 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
{ 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
{ 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
{ 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
{ 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
{ 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
{ 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
{ 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
{ 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
{ 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
{ 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
{ 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
{ 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
{ 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
{ 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
{ 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
{ 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
{ 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
{ 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
{ 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
{ 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
{ 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
{ 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
{ 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
{ 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
{ 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
{ 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
{ 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
{ 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
{ 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
{ 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
{ 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
{ 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
{ 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
{ 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
{ 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
{ 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
{ 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
{ 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
{ 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
{ 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
{ 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
{ 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
{ 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
{ 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
{ 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
{ 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
{ 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
{ 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
{ 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
{ 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
{ 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
{ 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
{ 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
{ 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
{ 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
{ 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
{ 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
{ 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
{ 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
{ 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
{ 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
{ 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
{ 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
{ 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
{ 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
{ 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
{ 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
{ 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
{ 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
{ 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
{ 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
{ 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
{ 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
{ 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
{ 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
{ 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
{ 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
{ 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
{ 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
{ 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
{ 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
{ 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
{ 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
{ 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
{ 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
{ 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
{ 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
{ 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
{ 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
{ 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
{ 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
{ 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
{ 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
{ 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
{ 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
{ 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
{ 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
{ 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
{ 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
{ 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
{ 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
{ 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
{ 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
{ 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
{ 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
{ 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
{ 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
{ 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
{ 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
{ 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
{ 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
{ 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
{ 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
{ 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
{ 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
{ 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
{ 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
{ 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
{ 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
{ 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
{ 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
{ 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
{ 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
{ 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
{ 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
{ 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
{ 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
{ 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
{ 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
{ 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
{ 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
{ 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
{ 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
{ 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
{ 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
{ 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
{ 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
{ 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
{ 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
{ 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
{ 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
{ 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
{ 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
{ 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
{ 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
{ 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
{ 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
{ 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
{ 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
{ 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
{ 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
{ 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
};
static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8962_CLOCKING1:
case WM8962_SOFTWARE_RESET:
case WM8962_THERMAL_SHUTDOWN_STATUS:
case WM8962_ADDITIONAL_CONTROL_4:
case WM8962_DC_SERVO_6:
case WM8962_INTERRUPT_STATUS_1:
case WM8962_INTERRUPT_STATUS_2:
case WM8962_DSP2_EXECCONTROL:
return true;
default:
return false;
}
}
static bool wm8962_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8962_LEFT_INPUT_VOLUME:
case WM8962_RIGHT_INPUT_VOLUME:
case WM8962_HPOUTL_VOLUME:
case WM8962_HPOUTR_VOLUME:
case WM8962_CLOCKING1:
case WM8962_ADC_DAC_CONTROL_1:
case WM8962_ADC_DAC_CONTROL_2:
case WM8962_AUDIO_INTERFACE_0:
case WM8962_CLOCKING2:
case WM8962_AUDIO_INTERFACE_1:
case WM8962_LEFT_DAC_VOLUME:
case WM8962_RIGHT_DAC_VOLUME:
case WM8962_AUDIO_INTERFACE_2:
case WM8962_SOFTWARE_RESET:
case WM8962_ALC1:
case WM8962_ALC2:
case WM8962_ALC3:
case WM8962_NOISE_GATE:
case WM8962_LEFT_ADC_VOLUME:
case WM8962_RIGHT_ADC_VOLUME:
case WM8962_ADDITIONAL_CONTROL_1:
case WM8962_ADDITIONAL_CONTROL_2:
case WM8962_PWR_MGMT_1:
case WM8962_PWR_MGMT_2:
case WM8962_ADDITIONAL_CONTROL_3:
case WM8962_ANTI_POP:
case WM8962_CLOCKING_3:
case WM8962_INPUT_MIXER_CONTROL_1:
case WM8962_LEFT_INPUT_MIXER_VOLUME:
case WM8962_RIGHT_INPUT_MIXER_VOLUME:
case WM8962_INPUT_MIXER_CONTROL_2:
case WM8962_INPUT_BIAS_CONTROL:
case WM8962_LEFT_INPUT_PGA_CONTROL:
case WM8962_RIGHT_INPUT_PGA_CONTROL:
case WM8962_SPKOUTL_VOLUME:
case WM8962_SPKOUTR_VOLUME:
case WM8962_THERMAL_SHUTDOWN_STATUS:
case WM8962_ADDITIONAL_CONTROL_4:
case WM8962_CLASS_D_CONTROL_1:
case WM8962_CLASS_D_CONTROL_2:
case WM8962_CLOCKING_4:
case WM8962_DAC_DSP_MIXING_1:
case WM8962_DAC_DSP_MIXING_2:
case WM8962_DC_SERVO_0:
case WM8962_DC_SERVO_1:
case WM8962_DC_SERVO_4:
case WM8962_DC_SERVO_6:
case WM8962_ANALOGUE_PGA_BIAS:
case WM8962_ANALOGUE_HP_0:
case WM8962_ANALOGUE_HP_2:
case WM8962_CHARGE_PUMP_1:
case WM8962_CHARGE_PUMP_B:
case WM8962_WRITE_SEQUENCER_CONTROL_1:
case WM8962_WRITE_SEQUENCER_CONTROL_2:
case WM8962_WRITE_SEQUENCER_CONTROL_3:
case WM8962_CONTROL_INTERFACE:
case WM8962_MIXER_ENABLES:
case WM8962_HEADPHONE_MIXER_1:
case WM8962_HEADPHONE_MIXER_2:
case WM8962_HEADPHONE_MIXER_3:
case WM8962_HEADPHONE_MIXER_4:
case WM8962_SPEAKER_MIXER_1:
case WM8962_SPEAKER_MIXER_2:
case WM8962_SPEAKER_MIXER_3:
case WM8962_SPEAKER_MIXER_4:
case WM8962_SPEAKER_MIXER_5:
case WM8962_BEEP_GENERATOR_1:
case WM8962_OSCILLATOR_TRIM_3:
case WM8962_OSCILLATOR_TRIM_4:
case WM8962_OSCILLATOR_TRIM_7:
case WM8962_ANALOGUE_CLOCKING1:
case WM8962_ANALOGUE_CLOCKING2:
case WM8962_ANALOGUE_CLOCKING3:
case WM8962_PLL_SOFTWARE_RESET:
case WM8962_PLL2:
case WM8962_PLL_4:
case WM8962_PLL_9:
case WM8962_PLL_10:
case WM8962_PLL_11:
case WM8962_PLL_12:
case WM8962_PLL_13:
case WM8962_PLL_14:
case WM8962_PLL_15:
case WM8962_PLL_16:
case WM8962_FLL_CONTROL_1:
case WM8962_FLL_CONTROL_2:
case WM8962_FLL_CONTROL_3:
case WM8962_FLL_CONTROL_5:
case WM8962_FLL_CONTROL_6:
case WM8962_FLL_CONTROL_7:
case WM8962_FLL_CONTROL_8:
case WM8962_GENERAL_TEST_1:
case WM8962_DF1:
case WM8962_DF2:
case WM8962_DF3:
case WM8962_DF4:
case WM8962_DF5:
case WM8962_DF6:
case WM8962_DF7:
case WM8962_LHPF1:
case WM8962_LHPF2:
case WM8962_THREED1:
case WM8962_THREED2:
case WM8962_THREED3:
case WM8962_THREED4:
case WM8962_DRC_1:
case WM8962_DRC_2:
case WM8962_DRC_3:
case WM8962_DRC_4:
case WM8962_DRC_5:
case WM8962_TLOOPBACK:
case WM8962_EQ1:
case WM8962_EQ2:
case WM8962_EQ3:
case WM8962_EQ4:
case WM8962_EQ5:
case WM8962_EQ6:
case WM8962_EQ7:
case WM8962_EQ8:
case WM8962_EQ9:
case WM8962_EQ10:
case WM8962_EQ11:
case WM8962_EQ12:
case WM8962_EQ13:
case WM8962_EQ14:
case WM8962_EQ15:
case WM8962_EQ16:
case WM8962_EQ17:
case WM8962_EQ18:
case WM8962_EQ19:
case WM8962_EQ20:
case WM8962_EQ21:
case WM8962_EQ22:
case WM8962_EQ23:
case WM8962_EQ24:
case WM8962_EQ25:
case WM8962_EQ26:
case WM8962_EQ27:
case WM8962_EQ28:
case WM8962_EQ29:
case WM8962_EQ30:
case WM8962_EQ31:
case WM8962_EQ32:
case WM8962_EQ33:
case WM8962_EQ34:
case WM8962_EQ35:
case WM8962_EQ36:
case WM8962_EQ37:
case WM8962_EQ38:
case WM8962_EQ39:
case WM8962_EQ40:
case WM8962_EQ41:
case WM8962_GPIO_2:
case WM8962_GPIO_3:
case WM8962_GPIO_5:
case WM8962_GPIO_6:
case WM8962_INTERRUPT_STATUS_1:
case WM8962_INTERRUPT_STATUS_2:
case WM8962_INTERRUPT_STATUS_1_MASK:
case WM8962_INTERRUPT_STATUS_2_MASK:
case WM8962_INTERRUPT_CONTROL:
case WM8962_IRQ_DEBOUNCE:
case WM8962_MICINT_SOURCE_POL:
case WM8962_DSP2_POWER_MANAGEMENT:
case WM8962_DSP2_EXECCONTROL:
case WM8962_DSP2_INSTRUCTION_RAM_0:
case WM8962_DSP2_ADDRESS_RAM_2:
case WM8962_DSP2_ADDRESS_RAM_1:
case WM8962_DSP2_ADDRESS_RAM_0:
case WM8962_DSP2_DATA1_RAM_1:
case WM8962_DSP2_DATA1_RAM_0:
case WM8962_DSP2_DATA2_RAM_1:
case WM8962_DSP2_DATA2_RAM_0:
case WM8962_DSP2_DATA3_RAM_1:
case WM8962_DSP2_DATA3_RAM_0:
case WM8962_DSP2_COEFF_RAM_0:
case WM8962_RETUNEADC_SHARED_COEFF_1:
case WM8962_RETUNEADC_SHARED_COEFF_0:
case WM8962_RETUNEDAC_SHARED_COEFF_1:
case WM8962_RETUNEDAC_SHARED_COEFF_0:
case WM8962_SOUNDSTAGE_ENABLES_1:
case WM8962_SOUNDSTAGE_ENABLES_0:
case WM8962_HDBASS_AI_1:
case WM8962_HDBASS_AI_0:
case WM8962_HDBASS_AR_1:
case WM8962_HDBASS_AR_0:
case WM8962_HDBASS_B_1:
case WM8962_HDBASS_B_0:
case WM8962_HDBASS_K_1:
case WM8962_HDBASS_K_0:
case WM8962_HDBASS_N1_1:
case WM8962_HDBASS_N1_0:
case WM8962_HDBASS_N2_1:
case WM8962_HDBASS_N2_0:
case WM8962_HDBASS_N3_1:
case WM8962_HDBASS_N3_0:
case WM8962_HDBASS_N4_1:
case WM8962_HDBASS_N4_0:
case WM8962_HDBASS_N5_1:
case WM8962_HDBASS_N5_0:
case WM8962_HDBASS_X1_1:
case WM8962_HDBASS_X1_0:
case WM8962_HDBASS_X2_1:
case WM8962_HDBASS_X2_0:
case WM8962_HDBASS_X3_1:
case WM8962_HDBASS_X3_0:
case WM8962_HDBASS_ATK_1:
case WM8962_HDBASS_ATK_0:
case WM8962_HDBASS_DCY_1:
case WM8962_HDBASS_DCY_0:
case WM8962_HDBASS_PG_1:
case WM8962_HDBASS_PG_0:
case WM8962_HPF_C_1:
case WM8962_HPF_C_0:
case WM8962_ADCL_RETUNE_C1_1:
case WM8962_ADCL_RETUNE_C1_0:
case WM8962_ADCL_RETUNE_C2_1:
case WM8962_ADCL_RETUNE_C2_0:
case WM8962_ADCL_RETUNE_C3_1:
case WM8962_ADCL_RETUNE_C3_0:
case WM8962_ADCL_RETUNE_C4_1:
case WM8962_ADCL_RETUNE_C4_0:
case WM8962_ADCL_RETUNE_C5_1:
case WM8962_ADCL_RETUNE_C5_0:
case WM8962_ADCL_RETUNE_C6_1:
case WM8962_ADCL_RETUNE_C6_0:
case WM8962_ADCL_RETUNE_C7_1:
case WM8962_ADCL_RETUNE_C7_0:
case WM8962_ADCL_RETUNE_C8_1:
case WM8962_ADCL_RETUNE_C8_0:
case WM8962_ADCL_RETUNE_C9_1:
case WM8962_ADCL_RETUNE_C9_0:
case WM8962_ADCL_RETUNE_C10_1:
case WM8962_ADCL_RETUNE_C10_0:
case WM8962_ADCL_RETUNE_C11_1:
case WM8962_ADCL_RETUNE_C11_0:
case WM8962_ADCL_RETUNE_C12_1:
case WM8962_ADCL_RETUNE_C12_0:
case WM8962_ADCL_RETUNE_C13_1:
case WM8962_ADCL_RETUNE_C13_0:
case WM8962_ADCL_RETUNE_C14_1:
case WM8962_ADCL_RETUNE_C14_0:
case WM8962_ADCL_RETUNE_C15_1:
case WM8962_ADCL_RETUNE_C15_0:
case WM8962_ADCL_RETUNE_C16_1:
case WM8962_ADCL_RETUNE_C16_0:
case WM8962_ADCL_RETUNE_C17_1:
case WM8962_ADCL_RETUNE_C17_0:
case WM8962_ADCL_RETUNE_C18_1:
case WM8962_ADCL_RETUNE_C18_0:
case WM8962_ADCL_RETUNE_C19_1:
case WM8962_ADCL_RETUNE_C19_0:
case WM8962_ADCL_RETUNE_C20_1:
case WM8962_ADCL_RETUNE_C20_0:
case WM8962_ADCL_RETUNE_C21_1:
case WM8962_ADCL_RETUNE_C21_0:
case WM8962_ADCL_RETUNE_C22_1:
case WM8962_ADCL_RETUNE_C22_0:
case WM8962_ADCL_RETUNE_C23_1:
case WM8962_ADCL_RETUNE_C23_0:
case WM8962_ADCL_RETUNE_C24_1:
case WM8962_ADCL_RETUNE_C24_0:
case WM8962_ADCL_RETUNE_C25_1:
case WM8962_ADCL_RETUNE_C25_0:
case WM8962_ADCL_RETUNE_C26_1:
case WM8962_ADCL_RETUNE_C26_0:
case WM8962_ADCL_RETUNE_C27_1:
case WM8962_ADCL_RETUNE_C27_0:
case WM8962_ADCL_RETUNE_C28_1:
case WM8962_ADCL_RETUNE_C28_0:
case WM8962_ADCL_RETUNE_C29_1:
case WM8962_ADCL_RETUNE_C29_0:
case WM8962_ADCL_RETUNE_C30_1:
case WM8962_ADCL_RETUNE_C30_0:
case WM8962_ADCL_RETUNE_C31_1:
case WM8962_ADCL_RETUNE_C31_0:
case WM8962_ADCL_RETUNE_C32_1:
case WM8962_ADCL_RETUNE_C32_0:
case WM8962_RETUNEADC_PG2_1:
case WM8962_RETUNEADC_PG2_0:
case WM8962_RETUNEADC_PG_1:
case WM8962_RETUNEADC_PG_0:
case WM8962_ADCR_RETUNE_C1_1:
case WM8962_ADCR_RETUNE_C1_0:
case WM8962_ADCR_RETUNE_C2_1:
case WM8962_ADCR_RETUNE_C2_0:
case WM8962_ADCR_RETUNE_C3_1:
case WM8962_ADCR_RETUNE_C3_0:
case WM8962_ADCR_RETUNE_C4_1:
case WM8962_ADCR_RETUNE_C4_0:
case WM8962_ADCR_RETUNE_C5_1:
case WM8962_ADCR_RETUNE_C5_0:
case WM8962_ADCR_RETUNE_C6_1:
case WM8962_ADCR_RETUNE_C6_0:
case WM8962_ADCR_RETUNE_C7_1:
case WM8962_ADCR_RETUNE_C7_0:
case WM8962_ADCR_RETUNE_C8_1:
case WM8962_ADCR_RETUNE_C8_0:
case WM8962_ADCR_RETUNE_C9_1:
case WM8962_ADCR_RETUNE_C9_0:
case WM8962_ADCR_RETUNE_C10_1:
case WM8962_ADCR_RETUNE_C10_0:
case WM8962_ADCR_RETUNE_C11_1:
case WM8962_ADCR_RETUNE_C11_0:
case WM8962_ADCR_RETUNE_C12_1:
case WM8962_ADCR_RETUNE_C12_0:
case WM8962_ADCR_RETUNE_C13_1:
case WM8962_ADCR_RETUNE_C13_0:
case WM8962_ADCR_RETUNE_C14_1:
case WM8962_ADCR_RETUNE_C14_0:
case WM8962_ADCR_RETUNE_C15_1:
case WM8962_ADCR_RETUNE_C15_0:
case WM8962_ADCR_RETUNE_C16_1:
case WM8962_ADCR_RETUNE_C16_0:
case WM8962_ADCR_RETUNE_C17_1:
case WM8962_ADCR_RETUNE_C17_0:
case WM8962_ADCR_RETUNE_C18_1:
case WM8962_ADCR_RETUNE_C18_0:
case WM8962_ADCR_RETUNE_C19_1:
case WM8962_ADCR_RETUNE_C19_0:
case WM8962_ADCR_RETUNE_C20_1:
case WM8962_ADCR_RETUNE_C20_0:
case WM8962_ADCR_RETUNE_C21_1:
case WM8962_ADCR_RETUNE_C21_0:
case WM8962_ADCR_RETUNE_C22_1:
case WM8962_ADCR_RETUNE_C22_0:
case WM8962_ADCR_RETUNE_C23_1:
case WM8962_ADCR_RETUNE_C23_0:
case WM8962_ADCR_RETUNE_C24_1:
case WM8962_ADCR_RETUNE_C24_0:
case WM8962_ADCR_RETUNE_C25_1:
case WM8962_ADCR_RETUNE_C25_0:
case WM8962_ADCR_RETUNE_C26_1:
case WM8962_ADCR_RETUNE_C26_0:
case WM8962_ADCR_RETUNE_C27_1:
case WM8962_ADCR_RETUNE_C27_0:
case WM8962_ADCR_RETUNE_C28_1:
case WM8962_ADCR_RETUNE_C28_0:
case WM8962_ADCR_RETUNE_C29_1:
case WM8962_ADCR_RETUNE_C29_0:
case WM8962_ADCR_RETUNE_C30_1:
case WM8962_ADCR_RETUNE_C30_0:
case WM8962_ADCR_RETUNE_C31_1:
case WM8962_ADCR_RETUNE_C31_0:
case WM8962_ADCR_RETUNE_C32_1:
case WM8962_ADCR_RETUNE_C32_0:
case WM8962_DACL_RETUNE_C1_1:
case WM8962_DACL_RETUNE_C1_0:
case WM8962_DACL_RETUNE_C2_1:
case WM8962_DACL_RETUNE_C2_0:
case WM8962_DACL_RETUNE_C3_1:
case WM8962_DACL_RETUNE_C3_0:
case WM8962_DACL_RETUNE_C4_1:
case WM8962_DACL_RETUNE_C4_0:
case WM8962_DACL_RETUNE_C5_1:
case WM8962_DACL_RETUNE_C5_0:
case WM8962_DACL_RETUNE_C6_1:
case WM8962_DACL_RETUNE_C6_0:
case WM8962_DACL_RETUNE_C7_1:
case WM8962_DACL_RETUNE_C7_0:
case WM8962_DACL_RETUNE_C8_1:
case WM8962_DACL_RETUNE_C8_0:
case WM8962_DACL_RETUNE_C9_1:
case WM8962_DACL_RETUNE_C9_0:
case WM8962_DACL_RETUNE_C10_1:
case WM8962_DACL_RETUNE_C10_0:
case WM8962_DACL_RETUNE_C11_1:
case WM8962_DACL_RETUNE_C11_0:
case WM8962_DACL_RETUNE_C12_1:
case WM8962_DACL_RETUNE_C12_0:
case WM8962_DACL_RETUNE_C13_1:
case WM8962_DACL_RETUNE_C13_0:
case WM8962_DACL_RETUNE_C14_1:
case WM8962_DACL_RETUNE_C14_0:
case WM8962_DACL_RETUNE_C15_1:
case WM8962_DACL_RETUNE_C15_0:
case WM8962_DACL_RETUNE_C16_1:
case WM8962_DACL_RETUNE_C16_0:
case WM8962_DACL_RETUNE_C17_1:
case WM8962_DACL_RETUNE_C17_0:
case WM8962_DACL_RETUNE_C18_1:
case WM8962_DACL_RETUNE_C18_0:
case WM8962_DACL_RETUNE_C19_1:
case WM8962_DACL_RETUNE_C19_0:
case WM8962_DACL_RETUNE_C20_1:
case WM8962_DACL_RETUNE_C20_0:
case WM8962_DACL_RETUNE_C21_1:
case WM8962_DACL_RETUNE_C21_0:
case WM8962_DACL_RETUNE_C22_1:
case WM8962_DACL_RETUNE_C22_0:
case WM8962_DACL_RETUNE_C23_1:
case WM8962_DACL_RETUNE_C23_0:
case WM8962_DACL_RETUNE_C24_1:
case WM8962_DACL_RETUNE_C24_0:
case WM8962_DACL_RETUNE_C25_1:
case WM8962_DACL_RETUNE_C25_0:
case WM8962_DACL_RETUNE_C26_1:
case WM8962_DACL_RETUNE_C26_0:
case WM8962_DACL_RETUNE_C27_1:
case WM8962_DACL_RETUNE_C27_0:
case WM8962_DACL_RETUNE_C28_1:
case WM8962_DACL_RETUNE_C28_0:
case WM8962_DACL_RETUNE_C29_1:
case WM8962_DACL_RETUNE_C29_0:
case WM8962_DACL_RETUNE_C30_1:
case WM8962_DACL_RETUNE_C30_0:
case WM8962_DACL_RETUNE_C31_1:
case WM8962_DACL_RETUNE_C31_0:
case WM8962_DACL_RETUNE_C32_1:
case WM8962_DACL_RETUNE_C32_0:
case WM8962_RETUNEDAC_PG2_1:
case WM8962_RETUNEDAC_PG2_0:
case WM8962_RETUNEDAC_PG_1:
case WM8962_RETUNEDAC_PG_0:
case WM8962_DACR_RETUNE_C1_1:
case WM8962_DACR_RETUNE_C1_0:
case WM8962_DACR_RETUNE_C2_1:
case WM8962_DACR_RETUNE_C2_0:
case WM8962_DACR_RETUNE_C3_1:
case WM8962_DACR_RETUNE_C3_0:
case WM8962_DACR_RETUNE_C4_1:
case WM8962_DACR_RETUNE_C4_0:
case WM8962_DACR_RETUNE_C5_1:
case WM8962_DACR_RETUNE_C5_0:
case WM8962_DACR_RETUNE_C6_1:
case WM8962_DACR_RETUNE_C6_0:
case WM8962_DACR_RETUNE_C7_1:
case WM8962_DACR_RETUNE_C7_0:
case WM8962_DACR_RETUNE_C8_1:
case WM8962_DACR_RETUNE_C8_0:
case WM8962_DACR_RETUNE_C9_1:
case WM8962_DACR_RETUNE_C9_0:
case WM8962_DACR_RETUNE_C10_1:
case WM8962_DACR_RETUNE_C10_0:
case WM8962_DACR_RETUNE_C11_1:
case WM8962_DACR_RETUNE_C11_0:
case WM8962_DACR_RETUNE_C12_1:
case WM8962_DACR_RETUNE_C12_0:
case WM8962_DACR_RETUNE_C13_1:
case WM8962_DACR_RETUNE_C13_0:
case WM8962_DACR_RETUNE_C14_1:
case WM8962_DACR_RETUNE_C14_0:
case WM8962_DACR_RETUNE_C15_1:
case WM8962_DACR_RETUNE_C15_0:
case WM8962_DACR_RETUNE_C16_1:
case WM8962_DACR_RETUNE_C16_0:
case WM8962_DACR_RETUNE_C17_1:
case WM8962_DACR_RETUNE_C17_0:
case WM8962_DACR_RETUNE_C18_1:
case WM8962_DACR_RETUNE_C18_0:
case WM8962_DACR_RETUNE_C19_1:
case WM8962_DACR_RETUNE_C19_0:
case WM8962_DACR_RETUNE_C20_1:
case WM8962_DACR_RETUNE_C20_0:
case WM8962_DACR_RETUNE_C21_1:
case WM8962_DACR_RETUNE_C21_0:
case WM8962_DACR_RETUNE_C22_1:
case WM8962_DACR_RETUNE_C22_0:
case WM8962_DACR_RETUNE_C23_1:
case WM8962_DACR_RETUNE_C23_0:
case WM8962_DACR_RETUNE_C24_1:
case WM8962_DACR_RETUNE_C24_0:
case WM8962_DACR_RETUNE_C25_1:
case WM8962_DACR_RETUNE_C25_0:
case WM8962_DACR_RETUNE_C26_1:
case WM8962_DACR_RETUNE_C26_0:
case WM8962_DACR_RETUNE_C27_1:
case WM8962_DACR_RETUNE_C27_0:
case WM8962_DACR_RETUNE_C28_1:
case WM8962_DACR_RETUNE_C28_0:
case WM8962_DACR_RETUNE_C29_1:
case WM8962_DACR_RETUNE_C29_0:
case WM8962_DACR_RETUNE_C30_1:
case WM8962_DACR_RETUNE_C30_0:
case WM8962_DACR_RETUNE_C31_1:
case WM8962_DACR_RETUNE_C31_0:
case WM8962_DACR_RETUNE_C32_1:
case WM8962_DACR_RETUNE_C32_0:
case WM8962_VSS_XHD2_1:
case WM8962_VSS_XHD2_0:
case WM8962_VSS_XHD3_1:
case WM8962_VSS_XHD3_0:
case WM8962_VSS_XHN1_1:
case WM8962_VSS_XHN1_0:
case WM8962_VSS_XHN2_1:
case WM8962_VSS_XHN2_0:
case WM8962_VSS_XHN3_1:
case WM8962_VSS_XHN3_0:
case WM8962_VSS_XLA_1:
case WM8962_VSS_XLA_0:
case WM8962_VSS_XLB_1:
case WM8962_VSS_XLB_0:
case WM8962_VSS_XLG_1:
case WM8962_VSS_XLG_0:
case WM8962_VSS_PG2_1:
case WM8962_VSS_PG2_0:
case WM8962_VSS_PG_1:
case WM8962_VSS_PG_0:
case WM8962_VSS_XTD1_1:
case WM8962_VSS_XTD1_0:
case WM8962_VSS_XTD2_1:
case WM8962_VSS_XTD2_0:
case WM8962_VSS_XTD3_1:
case WM8962_VSS_XTD3_0:
case WM8962_VSS_XTD4_1:
case WM8962_VSS_XTD4_0:
case WM8962_VSS_XTD5_1:
case WM8962_VSS_XTD5_0:
case WM8962_VSS_XTD6_1:
case WM8962_VSS_XTD6_0:
case WM8962_VSS_XTD7_1:
case WM8962_VSS_XTD7_0:
case WM8962_VSS_XTD8_1:
case WM8962_VSS_XTD8_0:
case WM8962_VSS_XTD9_1:
case WM8962_VSS_XTD9_0:
case WM8962_VSS_XTD10_1:
case WM8962_VSS_XTD10_0:
case WM8962_VSS_XTD11_1:
case WM8962_VSS_XTD11_0:
case WM8962_VSS_XTD12_1:
case WM8962_VSS_XTD12_0:
case WM8962_VSS_XTD13_1:
case WM8962_VSS_XTD13_0:
case WM8962_VSS_XTD14_1:
case WM8962_VSS_XTD14_0:
case WM8962_VSS_XTD15_1:
case WM8962_VSS_XTD15_0:
case WM8962_VSS_XTD16_1:
case WM8962_VSS_XTD16_0:
case WM8962_VSS_XTD17_1:
case WM8962_VSS_XTD17_0:
case WM8962_VSS_XTD18_1:
case WM8962_VSS_XTD18_0:
case WM8962_VSS_XTD19_1:
case WM8962_VSS_XTD19_0:
case WM8962_VSS_XTD20_1:
case WM8962_VSS_XTD20_0:
case WM8962_VSS_XTD21_1:
case WM8962_VSS_XTD21_0:
case WM8962_VSS_XTD22_1:
case WM8962_VSS_XTD22_0:
case WM8962_VSS_XTD23_1:
case WM8962_VSS_XTD23_0:
case WM8962_VSS_XTD24_1:
case WM8962_VSS_XTD24_0:
case WM8962_VSS_XTD25_1:
case WM8962_VSS_XTD25_0:
case WM8962_VSS_XTD26_1:
case WM8962_VSS_XTD26_0:
case WM8962_VSS_XTD27_1:
case WM8962_VSS_XTD27_0:
case WM8962_VSS_XTD28_1:
case WM8962_VSS_XTD28_0:
case WM8962_VSS_XTD29_1:
case WM8962_VSS_XTD29_0:
case WM8962_VSS_XTD30_1:
case WM8962_VSS_XTD30_0:
case WM8962_VSS_XTD31_1:
case WM8962_VSS_XTD31_0:
case WM8962_VSS_XTD32_1:
case WM8962_VSS_XTD32_0:
case WM8962_VSS_XTS1_1:
case WM8962_VSS_XTS1_0:
case WM8962_VSS_XTS2_1:
case WM8962_VSS_XTS2_0:
case WM8962_VSS_XTS3_1:
case WM8962_VSS_XTS3_0:
case WM8962_VSS_XTS4_1:
case WM8962_VSS_XTS4_0:
case WM8962_VSS_XTS5_1:
case WM8962_VSS_XTS5_0:
case WM8962_VSS_XTS6_1:
case WM8962_VSS_XTS6_0:
case WM8962_VSS_XTS7_1:
case WM8962_VSS_XTS7_0:
case WM8962_VSS_XTS8_1:
case WM8962_VSS_XTS8_0:
case WM8962_VSS_XTS9_1:
case WM8962_VSS_XTS9_0:
case WM8962_VSS_XTS10_1:
case WM8962_VSS_XTS10_0:
case WM8962_VSS_XTS11_1:
case WM8962_VSS_XTS11_0:
case WM8962_VSS_XTS12_1:
case WM8962_VSS_XTS12_0:
case WM8962_VSS_XTS13_1:
case WM8962_VSS_XTS13_0:
case WM8962_VSS_XTS14_1:
case WM8962_VSS_XTS14_0:
case WM8962_VSS_XTS15_1:
case WM8962_VSS_XTS15_0:
case WM8962_VSS_XTS16_1:
case WM8962_VSS_XTS16_0:
case WM8962_VSS_XTS17_1:
case WM8962_VSS_XTS17_0:
case WM8962_VSS_XTS18_1:
case WM8962_VSS_XTS18_0:
case WM8962_VSS_XTS19_1:
case WM8962_VSS_XTS19_0:
case WM8962_VSS_XTS20_1:
case WM8962_VSS_XTS20_0:
case WM8962_VSS_XTS21_1:
case WM8962_VSS_XTS21_0:
case WM8962_VSS_XTS22_1:
case WM8962_VSS_XTS22_0:
case WM8962_VSS_XTS23_1:
case WM8962_VSS_XTS23_0:
case WM8962_VSS_XTS24_1:
case WM8962_VSS_XTS24_0:
case WM8962_VSS_XTS25_1:
case WM8962_VSS_XTS25_0:
case WM8962_VSS_XTS26_1:
case WM8962_VSS_XTS26_0:
case WM8962_VSS_XTS27_1:
case WM8962_VSS_XTS27_0:
case WM8962_VSS_XTS28_1:
case WM8962_VSS_XTS28_0:
case WM8962_VSS_XTS29_1:
case WM8962_VSS_XTS29_0:
case WM8962_VSS_XTS30_1:
case WM8962_VSS_XTS30_0:
case WM8962_VSS_XTS31_1:
case WM8962_VSS_XTS31_0:
case WM8962_VSS_XTS32_1:
case WM8962_VSS_XTS32_0:
return true;
default:
return false;
}
}
static int wm8962_reset(struct wm8962_priv *wm8962)
{
int ret;
ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
if (ret != 0)
return ret;
return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
}
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_RANGE(mixinpga_tlv,
0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0)
);
static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
static const DECLARE_TLV_DB_RANGE(classd_tlv,
0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static int wm8962_dsp2_write_config(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
return regcache_sync_region(wm8962->regmap,
WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
}
static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
{
u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME);
u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME);
u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1);
/* Mute the ADCs and DACs */
snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
WM8962_DAC_MUTE, WM8962_DAC_MUTE);
snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val);
/* Restore the ADCs and DACs */
snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl);
snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr);
snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
WM8962_DAC_MUTE, dac);
return 0;
}
static int wm8962_dsp2_start(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
wm8962_dsp2_write_config(component);
snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
return 0;
}
static int wm8962_dsp2_stop(struct snd_soc_component *component)
{
wm8962_dsp2_set_enable(component, 0);
snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
return 0;
}
#define WM8962_DSP2_ENABLE(xname, xshift) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = wm8962_dsp2_ena_info, \
.get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
.private_value = xshift }
static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int shift = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
return 0;
}
static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int shift = kcontrol->private_value;
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
int old = wm8962->dsp2_ena;
int ret = 0;
int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) &
WM8962_DSP2_ENA;
mutex_lock(&wm8962->dsp2_ena_lock);
if (ucontrol->value.integer.value[0])
wm8962->dsp2_ena |= 1 << shift;
else
wm8962->dsp2_ena &= ~(1 << shift);
if (wm8962->dsp2_ena == old)
goto out;
ret = 1;
if (dsp2_running) {
if (wm8962->dsp2_ena)
wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
else
wm8962_dsp2_stop(component);
}
out:
mutex_unlock(&wm8962->dsp2_ena_lock);
return ret;
}
/* The VU bits for the headphones are in a different register to the mute
* bits and only take effect on the PGA if it is actually powered.
*/
static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ret;
/* Apply the update (if any) */
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret == 0)
return 0;
/* If the left PGA is enabled hit that VU bit... */
ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
if (ret & WM8962_HPOUTL_PGA_ENA) {
snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
snd_soc_component_read(component, WM8962_HPOUTL_VOLUME));
return 1;
}
/* ...otherwise the right. The VU is stereo. */
if (ret & WM8962_HPOUTR_PGA_ENA)
snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
snd_soc_component_read(component, WM8962_HPOUTR_VOLUME));
return 1;
}
/* The VU bits for the speakers are in a different register to the mute
* bits and only take effect on the PGA if it is actually powered.
*/
static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ret;
/* Apply the update (if any) */
ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (ret == 0)
return 0;
/* If the left PGA is enabled hit that VU bit... */
ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
if (ret & WM8962_SPKOUTL_PGA_ENA) {
snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME));
return 1;
}
/* ...otherwise the right. The VU is stereo. */
if (ret & WM8962_SPKOUTR_PGA_ENA)
snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME));
return 1;
}
static const char *cap_hpf_mode_text[] = {
"Hi-fi", "Application"
};
static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
static const char *cap_lhpf_mode_text[] = {
"LPF", "HPF"
};
static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
WM8962_LHPF1, 1, cap_lhpf_mode_text);
static const struct snd_kcontrol_new wm8962_snd_controls[] = {
SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
mixin_tlv),
SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
mixinpga_tlv),
SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
mixin_tlv),
SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
mixin_tlv),
SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
mixinpga_tlv),
SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
mixin_tlv),
SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0),
SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0),
SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
5, 1, 0),
SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
snd_soc_get_volsw, wm8962_put_hp_sw),
SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
7, 1, 0),
SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
hp_tlv),
SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
3, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
0, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
7, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
6, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
3, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
0, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
7, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
6, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
classd_tlv),
SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
WM8962_ALCR_ENA_SHIFT, 1, 0),
SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
};
static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
snd_soc_get_volsw, wm8962_put_spk_sw),
SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
3, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
0, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
7, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
6, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
7, 1, 0, inmix_tlv),
SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
6, 1, 0, inmix_tlv),
};
static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
snd_soc_get_volsw, wm8962_put_spk_sw),
SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
7, 1, 0),
SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
WM8962_SPEAKER_MIXER_4, 8, 1, 1),
SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
3, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
0, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
7, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
6, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
7, 1, 0, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
6, 1, 0, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
3, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
0, 7, 0, bypass_tlv),
SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
7, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
6, 1, 1, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
5, 1, 0, inmix_tlv),
SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
4, 1, 0, inmix_tlv),
};
static int tp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
int ret, reg, val, mask;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
dev_err(component->dev, "Failed to resume device: %d\n", ret);
return ret;
}
reg = WM8962_ADDITIONAL_CONTROL_4;
if (!strcmp(w->name, "TEMP_HP")) {
mask = WM8962_TEMP_ENA_HP_MASK;
val = WM8962_TEMP_ENA_HP;
} else if (!strcmp(w->name, "TEMP_SPK")) {
mask = WM8962_TEMP_ENA_SPK_MASK;
val = WM8962_TEMP_ENA_SPK;
} else {
pm_runtime_put(component->dev);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMD:
val = 0;
fallthrough;
case SND_SOC_DAPM_POST_PMU:
ret = snd_soc_component_update_bits(component, reg, mask, val);
break;
default:
WARN(1, "Invalid event %d\n", event);
pm_runtime_put(component->dev);
return -EINVAL;
}
pm_runtime_put(component->dev);
return 0;
}
static int cp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(5);
break;
default:
WARN(1, "Invalid event %d\n", event);
return -EINVAL;
}
return 0;
}
static int hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int timeout;
int reg;
int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
WM8962_DCS_STARTUP_DONE_HP1R);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
WM8962_HP1L_ENA | WM8962_HP1R_ENA,
WM8962_HP1L_ENA | WM8962_HP1R_ENA);
udelay(20);
snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
/* Start the DC servo */
snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
WM8962_HP1L_DCS_STARTUP |
WM8962_HP1R_DCS_STARTUP,
WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
WM8962_HP1L_DCS_STARTUP |
WM8962_HP1R_DCS_STARTUP);
/* Wait for it to complete, should be well under 100ms */
timeout = 0;
do {
msleep(1);
reg = snd_soc_component_read(component, WM8962_DC_SERVO_6);
if (reg < 0) {
dev_err(component->dev,
"Failed to read DCS status: %d\n",
reg);
continue;
}
dev_dbg(component->dev, "DCS status: %x\n", reg);
} while (++timeout < 200 && (reg & expected) != expected);
if ((reg & expected) != expected)
dev_err(component->dev, "DC servo timed out\n");
else
dev_dbg(component->dev, "DC servo complete after %dms\n",
timeout);
snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
WM8962_HP1L_ENA_OUTP |
WM8962_HP1R_ENA_OUTP,
WM8962_HP1L_ENA_OUTP |
WM8962_HP1R_ENA_OUTP);
udelay(20);
snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
WM8962_HP1L_RMV_SHORT |
WM8962_HP1R_RMV_SHORT,
WM8962_HP1L_RMV_SHORT |
WM8962_HP1R_RMV_SHORT);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
WM8962_HP1L_RMV_SHORT |
WM8962_HP1R_RMV_SHORT, 0);
udelay(20);
snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
WM8962_HP1L_DCS_STARTUP |
WM8962_HP1R_DCS_STARTUP,
0);
snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
WM8962_HP1L_ENA | WM8962_HP1R_ENA |
WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
WM8962_HP1L_ENA_OUTP |
WM8962_HP1R_ENA_OUTP, 0);
break;
default:
WARN(1, "Invalid event %d\n", event);
return -EINVAL;
}
return 0;
}
/* VU bits for the output PGAs only take effect while the PGA is powered */
static int out_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
int reg;
switch (w->shift) {
case WM8962_HPOUTR_PGA_ENA_SHIFT:
reg = WM8962_HPOUTR_VOLUME;
break;
case WM8962_HPOUTL_PGA_ENA_SHIFT:
reg = WM8962_HPOUTL_VOLUME;
break;
case WM8962_SPKOUTR_PGA_ENA_SHIFT:
reg = WM8962_SPKOUTR_VOLUME;
break;
case WM8962_SPKOUTL_PGA_ENA_SHIFT:
reg = WM8962_SPKOUTL_VOLUME;
break;
default:
WARN(1, "Invalid shift %d\n", w->shift);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_POST_PMU:
return snd_soc_component_write(component, reg,
snd_soc_component_read(component, reg));
default:
WARN(1, "Invalid event %d\n", event);
return -EINVAL;
}
}
static int dsp2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (wm8962->dsp2_ena)
wm8962_dsp2_start(component);
break;
case SND_SOC_DAPM_PRE_PMD:
if (wm8962->dsp2_ena)
wm8962_dsp2_stop(component);
break;
default:
WARN(1, "Invalid event %d\n", event);
return -EINVAL;
}
return 0;
}
static const char *st_text[] = { "None", "Left", "Right" };
static SOC_ENUM_SINGLE_DECL(str_enum,
WM8962_DAC_DSP_MIXING_1, 2, st_text);
static const struct snd_kcontrol_new str_mux =
SOC_DAPM_ENUM("Right Sidetone", str_enum);
static SOC_ENUM_SINGLE_DECL(stl_enum,
WM8962_DAC_DSP_MIXING_2, 2, st_text);
static const struct snd_kcontrol_new stl_mux =
SOC_DAPM_ENUM("Left Sidetone", stl_enum);
static const char *outmux_text[] = { "DAC", "Mixer" };
static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
WM8962_SPEAKER_MIXER_2, 7, outmux_text);
static const struct snd_kcontrol_new spkoutr_mux =
SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
WM8962_SPEAKER_MIXER_1, 7, outmux_text);
static const struct snd_kcontrol_new spkoutl_mux =
SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
static const struct snd_kcontrol_new hpoutr_mux =
SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
static const struct snd_kcontrol_new hpoutl_mux =
SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
static const char * const input_mode_text[] = { "Analog", "Digital" };
static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text);
static const struct snd_kcontrol_new input_mode_mux =
SOC_DAPM_ENUM("Input Mode", input_mode_enum);
static const struct snd_kcontrol_new inpgal[] = {
SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
};
static const struct snd_kcontrol_new inpgar[] = {
SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
};
static const struct snd_kcontrol_new mixinl[] = {
SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
};
static const struct snd_kcontrol_new mixinr[] = {
SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
};
static const struct snd_kcontrol_new hpmixl[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
};
static const struct snd_kcontrol_new hpmixr[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
};
static const struct snd_kcontrol_new spkmixl[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
};
static const struct snd_kcontrol_new spkmixr[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
};
static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_INPUT("IN4L"),
SND_SOC_DAPM_INPUT("IN4R"),
SND_SOC_DAPM_SIGGEN("Beep"),
SND_SOC_DAPM_INPUT("DMICDAT"),
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event,
SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
inpgal, ARRAY_SIZE(inpgal)),
SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
inpgar, ARRAY_SIZE(inpgar)),
SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
mixinl, ARRAY_SIZE(mixinl)),
SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
mixinr, ARRAY_SIZE(mixinr)),
SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux),
SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux),
SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
hpmixl, ARRAY_SIZE(hpmixl)),
SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
hpmixr, ARRAY_SIZE(hpmixr)),
SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
out_pga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
out_pga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
};
static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
spkmixl, ARRAY_SIZE(spkmixl)),
SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
out_pga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
};
static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
spkmixl, ARRAY_SIZE(spkmixl)),
SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
spkmixr, ARRAY_SIZE(spkmixr)),
SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
out_pga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
out_pga_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKOUTL"),
SND_SOC_DAPM_OUTPUT("SPKOUTR"),
};
static const struct snd_soc_dapm_route wm8962_intercon[] = {
{ "INPGAL", "IN1L Switch", "IN1L" },
{ "INPGAL", "IN2L Switch", "IN2L" },
{ "INPGAL", "IN3L Switch", "IN3L" },
{ "INPGAL", "IN4L Switch", "IN4L" },
{ "INPGAR", "IN1R Switch", "IN1R" },
{ "INPGAR", "IN2R Switch", "IN2R" },
{ "INPGAR", "IN3R Switch", "IN3R" },
{ "INPGAR", "IN4R Switch", "IN4R" },
{ "MIXINL", "IN2L Switch", "IN2L" },
{ "MIXINL", "IN3L Switch", "IN3L" },
{ "MIXINL", "PGA Switch", "INPGAL" },
{ "MIXINR", "IN2R Switch", "IN2R" },
{ "MIXINR", "IN3R Switch", "IN3R" },
{ "MIXINR", "PGA Switch", "INPGAR" },
{ "MICBIAS", NULL, "SYSCLK" },
{ "DMIC_ENA", NULL, "DMICDAT" },
{ "Input Mode L", "Analog", "MIXINL" },
{ "Input Mode L", "Digital", "DMIC_ENA" },
{ "Input Mode R", "Analog", "MIXINR" },
{ "Input Mode R", "Digital", "DMIC_ENA" },
{ "ADCL", NULL, "SYSCLK" },
{ "ADCL", NULL, "TOCLK" },
{ "ADCL", NULL, "Input Mode L" },
{ "ADCL", NULL, "DSP2" },
{ "ADCR", NULL, "SYSCLK" },
{ "ADCR", NULL, "TOCLK" },
{ "ADCR", NULL, "Input Mode R" },
{ "ADCR", NULL, "DSP2" },
{ "STL", "Left", "ADCL" },
{ "STL", "Right", "ADCR" },
{ "STL", NULL, "Class G" },
{ "STR", "Left", "ADCL" },
{ "STR", "Right", "ADCR" },
{ "STR", NULL, "Class G" },
{ "DACL", NULL, "SYSCLK" },
{ "DACL", NULL, "TOCLK" },
{ "DACL", NULL, "Beep" },
{ "DACL", NULL, "STL" },
{ "DACL", NULL, "DSP2" },
{ "DACR", NULL, "SYSCLK" },
{ "DACR", NULL, "TOCLK" },
{ "DACR", NULL, "Beep" },
{ "DACR", NULL, "STR" },
{ "DACR", NULL, "DSP2" },
{ "HPMIXL", "IN4L Switch", "IN4L" },
{ "HPMIXL", "IN4R Switch", "IN4R" },
{ "HPMIXL", "DACL Switch", "DACL" },
{ "HPMIXL", "DACR Switch", "DACR" },
{ "HPMIXL", "MIXINL Switch", "MIXINL" },
{ "HPMIXL", "MIXINR Switch", "MIXINR" },
{ "HPMIXR", "IN4L Switch", "IN4L" },
{ "HPMIXR", "IN4R Switch", "IN4R" },
{ "HPMIXR", "DACL Switch", "DACL" },
{ "HPMIXR", "DACR Switch", "DACR" },
{ "HPMIXR", "MIXINL Switch", "MIXINL" },
{ "HPMIXR", "MIXINR Switch", "MIXINR" },
{ "Left Bypass", NULL, "HPMIXL" },
{ "Left Bypass", NULL, "Class G" },
{ "Right Bypass", NULL, "HPMIXR" },
{ "Right Bypass", NULL, "Class G" },
{ "HPOUTL PGA", "Mixer", "Left Bypass" },
{ "HPOUTL PGA", "DAC", "DACL" },
{ "HPOUTR PGA", "Mixer", "Right Bypass" },
{ "HPOUTR PGA", "DAC", "DACR" },
{ "HPOUT", NULL, "HPOUTL PGA" },
{ "HPOUT", NULL, "HPOUTR PGA" },
{ "HPOUT", NULL, "Charge Pump" },
{ "HPOUT", NULL, "SYSCLK" },
{ "HPOUT", NULL, "TOCLK" },
{ "HPOUTL", NULL, "HPOUT" },
{ "HPOUTR", NULL, "HPOUT" },
{ "HPOUTL", NULL, "TEMP_HP" },
{ "HPOUTR", NULL, "TEMP_HP" },
};
static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
{ "Speaker Mixer", "IN4L Switch", "IN4L" },
{ "Speaker Mixer", "IN4R Switch", "IN4R" },
{ "Speaker Mixer", "DACL Switch", "DACL" },
{ "Speaker Mixer", "DACR Switch", "DACR" },
{ "Speaker Mixer", "MIXINL Switch", "MIXINL" },
{ "Speaker Mixer", "MIXINR Switch", "MIXINR" },
{ "Speaker PGA", "Mixer", "Speaker Mixer" },
{ "Speaker PGA", "DAC", "DACL" },
{ "Speaker Output", NULL, "Speaker PGA" },
{ "Speaker Output", NULL, "SYSCLK" },
{ "Speaker Output", NULL, "TOCLK" },
{ "Speaker Output", NULL, "TEMP_SPK" },
{ "SPKOUT", NULL, "Speaker Output" },
};
static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
{ "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
{ "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
{ "SPKOUTL Mixer", "DACL Switch", "DACL" },
{ "SPKOUTL Mixer", "DACR Switch", "DACR" },
{ "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
{ "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
{ "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
{ "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
{ "SPKOUTR Mixer", "DACL Switch", "DACL" },
{ "SPKOUTR Mixer", "DACR Switch", "DACR" },
{ "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
{ "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
{ "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
{ "SPKOUTL PGA", "DAC", "DACL" },
{ "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
{ "SPKOUTR PGA", "DAC", "DACR" },
{ "SPKOUTL Output", NULL, "SPKOUTL PGA" },
{ "SPKOUTL Output", NULL, "SYSCLK" },
{ "SPKOUTL Output", NULL, "TOCLK" },
{ "SPKOUTL Output", NULL, "TEMP_SPK" },
{ "SPKOUTR Output", NULL, "SPKOUTR PGA" },
{ "SPKOUTR Output", NULL, "SYSCLK" },
{ "SPKOUTR Output", NULL, "TOCLK" },
{ "SPKOUTR Output", NULL, "TEMP_SPK" },
{ "SPKOUTL", NULL, "SPKOUTL Output" },
{ "SPKOUTR", NULL, "SPKOUTR Output" },
};
static int wm8962_add_widgets(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
struct wm8962_pdata *pdata = &wm8962->pdata;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_add_component_controls(component, wm8962_snd_controls,
ARRAY_SIZE(wm8962_snd_controls));
if (pdata->spk_mono)
snd_soc_add_component_controls(component, wm8962_spk_mono_controls,
ARRAY_SIZE(wm8962_spk_mono_controls));
else
snd_soc_add_component_controls(component, wm8962_spk_stereo_controls,
ARRAY_SIZE(wm8962_spk_stereo_controls));
snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
ARRAY_SIZE(wm8962_dapm_widgets));
if (pdata->spk_mono)
snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
else
snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
snd_soc_dapm_add_routes(dapm, wm8962_intercon,
ARRAY_SIZE(wm8962_intercon));
if (pdata->spk_mono)
snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
ARRAY_SIZE(wm8962_spk_mono_intercon));
else
snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
ARRAY_SIZE(wm8962_spk_stereo_intercon));
snd_soc_dapm_disable_pin(dapm, "Beep");
return 0;
}
/* -1 for reserved values */
static const int bclk_divs[] = {
1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
};
static const int sysclk_rates[] = {
64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
};
static void wm8962_configure_bclk(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
int best, min_diff, diff;
int dspclk, i;
int clocking2 = 0;
int clocking4 = 0;
int aif2 = 0;
if (!wm8962->sysclk_rate) {
dev_dbg(component->dev, "No SYSCLK configured\n");
return;
}
if (!wm8962->bclk || !wm8962->lrclk) {
dev_dbg(component->dev, "No audio clocks configured\n");
return;
}
for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
break;
}
}
if (i == ARRAY_SIZE(sysclk_rates)) {
dev_err(component->dev, "Unsupported sysclk ratio %d\n",
wm8962->sysclk_rate / wm8962->lrclk);
return;
}
dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
snd_soc_component_update_bits(component, WM8962_CLOCKING_4,
WM8962_SYSCLK_RATE_MASK, clocking4);
/* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
* So we here provisionally enable it and then disable it afterward
* if current bias_level hasn't reached SND_SOC_BIAS_ON.
*/
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
snd_soc_component_update_bits(component, WM8962_CLOCKING2,
WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
/* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
* correct frequency of LRCLK and BCLK. Sometimes the read-only value
* can't be updated timely after enabling SYSCLK. This results in wrong
* calculation values. Delay is introduced here to wait for newest
* value from register. The time of the delay should be at least
* 500~1000us according to test.
*/
usleep_range(500, 1000);
dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
snd_soc_component_update_bits(component, WM8962_CLOCKING2,
WM8962_SYSCLK_ENA_MASK, 0);
if (dspclk < 0) {
dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk);
return;
}
dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
switch (dspclk) {
case 0:
dspclk = wm8962->sysclk_rate;
break;
case 1:
dspclk = wm8962->sysclk_rate / 2;
break;
case 2:
dspclk = wm8962->sysclk_rate / 4;
break;
default:
dev_warn(component->dev, "Unknown DSPCLK divisor read back\n");
dspclk = wm8962->sysclk_rate;
}
dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
/* Search a proper bclk, not exact match. */
best = 0;
min_diff = INT_MAX;
for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
if (bclk_divs[i] < 0)
continue;
diff = (dspclk / bclk_divs[i]) - wm8962->bclk;
if (diff < 0) /* Table is sorted */
break;
if (diff < min_diff) {
best = i;
min_diff = diff;
}
}
wm8962->bclk = dspclk / bclk_divs[best];
clocking2 |= best;
dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",
bclk_divs[best], wm8962->bclk);
aif2 |= wm8962->bclk / wm8962->lrclk;
dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
snd_soc_component_update_bits(component, WM8962_CLOCKING2,
WM8962_BCLK_DIV_MASK, clocking2);
snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2,
WM8962_AIF_RATE_MASK, aif2);
}
static int wm8962_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* VMID 2*50k */
snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
WM8962_VMID_SEL_MASK, 0x80);
wm8962_configure_bclk(component);
break;
case SND_SOC_BIAS_STANDBY:
/* VMID 2*250k */
snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
WM8962_VMID_SEL_MASK, 0x100);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
msleep(100);
break;
case SND_SOC_BIAS_OFF:
break;
}
return 0;
}
static const struct {
int rate;
int reg;
} sr_vals[] = {
{ 48000, 0 },
{ 44100, 0 },
{ 32000, 1 },
{ 22050, 2 },
{ 24000, 2 },
{ 16000, 3 },
{ 11025, 4 },
{ 12000, 4 },
{ 8000, 5 },
{ 88200, 6 },
{ 96000, 6 },
};
static int wm8962_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
int i;
int aif0 = 0;
int adctl3 = 0;
wm8962->bclk = snd_soc_params_to_bclk(params);
if (params_channels(params) == 1)
wm8962->bclk *= 2;
wm8962->lrclk = params_rate(params);
for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
if (sr_vals[i].rate == wm8962->lrclk) {
adctl3 |= sr_vals[i].reg;
break;
}
}
if (i == ARRAY_SIZE(sr_vals)) {
dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
return -EINVAL;
}
if (wm8962->lrclk % 8000 == 0)
adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
switch (params_width(params)) {
case 16:
break;
case 20:
aif0 |= 0x4;
break;
case 24:
aif0 |= 0x8;
break;
case 32:
aif0 |= 0xc;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
WM8962_WL_MASK, aif0);
snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3,
WM8962_SAMPLE_RATE_INT_MODE |
WM8962_SAMPLE_RATE_MASK, adctl3);
dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
wm8962->bclk, wm8962->lrclk);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON)
wm8962_configure_bclk(component);
return 0;
}
static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
int src;
switch (clk_id) {
case WM8962_SYSCLK_MCLK:
wm8962->sysclk = WM8962_SYSCLK_MCLK;
src = 0;
break;
case WM8962_SYSCLK_FLL:
wm8962->sysclk = WM8962_SYSCLK_FLL;
src = 1 << WM8962_SYSCLK_SRC_SHIFT;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
src);
wm8962->sysclk_rate = freq;
return 0;
}
static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
int aif0 = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_B:
aif0 |= WM8962_LRCLK_INV | 3;
fallthrough;
case SND_SOC_DAIFMT_DSP_A:
aif0 |= 3;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
case SND_SOC_DAIFMT_IB_NF:
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aif0 |= 1;
break;
case SND_SOC_DAIFMT_I2S:
aif0 |= 2;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif0 |= WM8962_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif0 |= WM8962_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aif0 |= WM8962_MSTR;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
WM8962_LRCLK_INV, aif0);
return 0;
}
struct _fll_div {
u16 fll_fratio;
u16 fll_outdiv;
u16 fll_refclk_div;
u16 n;
u16 theta;
u16 lambda;
};
/* The size in bits of the FLL divide multiplied by 10
* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 16) * 10)
static struct {
unsigned int min;
unsigned int max;
u16 fll_fratio;
int ratio;
} fll_fratios[] = {
{ 0, 64000, 4, 16 },
{ 64000, 128000, 3, 8 },
{ 128000, 256000, 2, 4 },
{ 256000, 1000000, 1, 2 },
{ 1000000, 13500000, 0, 1 },
};
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
unsigned int Fout)
{
unsigned int target;
unsigned int div;
unsigned int fratio, gcd_fll;
int i;
/* Fref must be <=13.5MHz */
div = 1;
fll_div->fll_refclk_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
fll_div->fll_refclk_div++;
if (div > 4) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
Fref);
return -EINVAL;
}
}
pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
/* Apply the division for our remaining calculations */
Fref /= div;
/* Fvco should be 90-100MHz; don't check the upper bound */
div = 2;
while (Fout * div < 90000000) {
div++;
if (div > 64) {
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
Fout);
return -EINVAL;
}
}
target = Fout * div;
fll_div->fll_outdiv = div - 1;
pr_debug("FLL Fvco=%dHz\n", target);
/* Find an appropriate FLL_FRATIO and factor it out of the target */
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
fratio = fll_fratios[i].ratio;
break;
}
}
if (i == ARRAY_SIZE(fll_fratios)) {
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
return -EINVAL;
}
fll_div->n = target / (fratio * Fref);
if (target % Fref == 0) {
fll_div->theta = 0;
fll_div->lambda = 1;
} else {
gcd_fll = gcd(target, fratio * Fref);
fll_div->theta = (target - (fll_div->n * fratio * Fref))
/ gcd_fll;
fll_div->lambda = (fratio * Fref) / gcd_fll;
}
pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
fll_div->n, fll_div->theta, fll_div->lambda);
pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
fll_div->fll_fratio, fll_div->fll_outdiv,
fll_div->fll_refclk_div);
return 0;
}
static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source,
unsigned int Fref, unsigned int Fout)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
struct _fll_div fll_div;
unsigned long timeout;
int ret;
int fll1 = 0;
/* Any change? */
if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
Fout == wm8962->fll_fout)
return 0;
if (Fout == 0) {
dev_dbg(component->dev, "FLL disabled\n");
wm8962->fll_fref = 0;
wm8962->fll_fout = 0;
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
WM8962_FLL_ENA, 0);
pm_runtime_put(component->dev);
return 0;
}
ret = fll_factors(&fll_div, Fref, Fout);
if (ret != 0)
return ret;
/* Parameters good, disable so we can reprogram */
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
switch (fll_id) {
case WM8962_FLL_MCLK:
case WM8962_FLL_BCLK:
case WM8962_FLL_OSC:
fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
break;
case WM8962_FLL_INT:
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5,
WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
break;
default:
dev_err(component->dev, "Unknown FLL source %d\n", ret);
return -EINVAL;
}
if (fll_div.theta)
fll1 |= WM8962_FLL_FRAC;
/* Stop the FLL while we reconfigure */
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2,
WM8962_FLL_OUTDIV_MASK |
WM8962_FLL_REFCLK_DIV_MASK,
(fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
(fll_div.fll_refclk_div));
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3,
WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta);
snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda);
snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n);
reinit_completion(&wm8962->fll_lock);
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
dev_err(component->dev, "Failed to resume device: %d\n", ret);
return ret;
}
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
/* This should be a massive overestimate but go even
* higher if we'll error out
*/
if (wm8962->irq)
timeout = msecs_to_jiffies(5);
else
timeout = msecs_to_jiffies(1);
timeout = wait_for_completion_timeout(&wm8962->fll_lock,
timeout);
if (timeout == 0 && wm8962->irq) {
dev_err(component->dev, "FLL lock timed out");
snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
WM8962_FLL_ENA, 0);
pm_runtime_put(component->dev);
return -ETIMEDOUT;
}
wm8962->fll_fref = Fref;
wm8962->fll_fout = Fout;
wm8962->fll_src = source;
return 0;
}
static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
int val, ret;
if (mute)
val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
else
val = 0;
/**
* The DAC mute bit is mirrored in two registers, update both to keep
* the register cache consistent.
*/
ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1,
WM8962_DAC_MUTE_ALT, val);
if (ret < 0)
return ret;
return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
WM8962_DAC_MUTE, val);
}
#define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8962_dai_ops = {
.hw_params = wm8962_hw_params,
.set_sysclk = wm8962_set_dai_sysclk,
.set_fmt = wm8962_set_dai_fmt,
.mute_stream = wm8962_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8962_dai = {
.name = "wm8962",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8962_RATES,
.formats = WM8962_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8962_RATES,
.formats = WM8962_FORMATS,
},
.ops = &wm8962_dai_ops,
.symmetric_rate = 1,
};
static void wm8962_mic_work(struct work_struct *work)
{
struct wm8962_priv *wm8962 = container_of(work,
struct wm8962_priv,
mic_work.work);
struct snd_soc_component *component = wm8962->component;
int status = 0;
int irq_pol = 0;
int reg;
reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4);
if (reg & WM8962_MICDET_STS) {
status |= SND_JACK_MICROPHONE;
irq_pol |= WM8962_MICD_IRQ_POL;
}
if (reg & WM8962_MICSHORT_STS) {
status |= SND_JACK_BTN_0;
irq_pol |= WM8962_MICSCD_IRQ_POL;
}
snd_soc_jack_report(wm8962->jack, status,
SND_JACK_MICROPHONE | SND_JACK_BTN_0);
snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL,
WM8962_MICSCD_IRQ_POL |
WM8962_MICD_IRQ_POL, irq_pol);
}
static irqreturn_t wm8962_irq(int irq, void *data)
{
struct device *dev = data;
struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
unsigned int mask;
unsigned int active;
int reg, ret;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
dev_err(dev, "Failed to resume: %d\n", ret);
return IRQ_NONE;
}
ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
&mask);
if (ret != 0) {
pm_runtime_put(dev);
dev_err(dev, "Failed to read interrupt mask: %d\n",
ret);
return IRQ_NONE;
}
ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
if (ret != 0) {
pm_runtime_put(dev);
dev_err(dev, "Failed to read interrupt: %d\n", ret);
return IRQ_NONE;
}
active &= ~mask;
if (!active) {
pm_runtime_put(dev);
return IRQ_NONE;
}
/* Acknowledge the interrupts */
ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
if (ret != 0)
dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
if (active & WM8962_FLL_LOCK_EINT) {
dev_dbg(dev, "FLL locked\n");
complete(&wm8962->fll_lock);
}
if (active & WM8962_FIFOS_ERR_EINT)
dev_err(dev, "FIFO error\n");
if (active & WM8962_TEMP_SHUT_EINT) {
dev_crit(dev, "Thermal shutdown\n");
ret = regmap_read(wm8962->regmap,
WM8962_THERMAL_SHUTDOWN_STATUS, ®);
if (ret != 0) {
dev_warn(dev, "Failed to read thermal status: %d\n",
ret);
reg = 0;
}
if (reg & WM8962_TEMP_ERR_HP)
dev_crit(dev, "Headphone thermal error\n");
if (reg & WM8962_TEMP_WARN_HP)
dev_crit(dev, "Headphone thermal warning\n");
if (reg & WM8962_TEMP_ERR_SPK)
dev_crit(dev, "Speaker thermal error\n");
if (reg & WM8962_TEMP_WARN_SPK)
dev_crit(dev, "Speaker thermal warning\n");
}
if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
dev_dbg(dev, "Microphone event detected\n");
#ifndef CONFIG_SND_SOC_WM8962_MODULE
trace_snd_soc_jack_irq(dev_name(dev));
#endif
pm_wakeup_event(dev, 300);
queue_delayed_work(system_power_efficient_wq,
&wm8962->mic_work,
msecs_to_jiffies(250));
}
pm_runtime_put(dev);
return IRQ_HANDLED;
}
/**
* wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
*
* @component: WM8962 component
* @jack: jack to report detection events on
*
* Enable microphone detection via IRQ on the WM8962. If GPIOs are
* being used to bring out signals to the processor then only platform
* data configuration is needed for WM8962 and processor GPIOs should
* be configured using snd_soc_jack_add_gpios() instead.
*
* If no jack is supplied detection will be disabled.
*/
int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int irq_mask, enable;
wm8962->jack = jack;
if (jack) {
irq_mask = 0;
enable = WM8962_MICDET_ENA;
} else {
irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
enable = 0;
}
snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK,
WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4,
WM8962_MICDET_ENA, enable);
/* Send an initial empty report */
snd_soc_jack_report(wm8962->jack, 0,
SND_JACK_MICROPHONE | SND_JACK_BTN_0);
snd_soc_dapm_mutex_lock(dapm);
if (jack) {
snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
} else {
snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
}
snd_soc_dapm_mutex_unlock(dapm);
return 0;
}
EXPORT_SYMBOL_GPL(wm8962_mic_detect);
static int beep_rates[] = {
500, 1000, 2000, 4000,
};
static void wm8962_beep_work(struct work_struct *work)
{
struct wm8962_priv *wm8962 =
container_of(work, struct wm8962_priv, beep_work);
struct snd_soc_component *component = wm8962->component;
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int i;
int reg = 0;
int best = 0;
if (wm8962->beep_rate) {
for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
if (abs(wm8962->beep_rate - beep_rates[i]) <
abs(wm8962->beep_rate - beep_rates[best]))
best = i;
}
dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
beep_rates[best], wm8962->beep_rate);
reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
snd_soc_dapm_enable_pin(dapm, "Beep");
} else {
dev_dbg(component->dev, "Disabling beep\n");
snd_soc_dapm_disable_pin(dapm, "Beep");
}
snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1,
WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
snd_soc_dapm_sync(dapm);
}
/* For usability define a way of injecting beep events for the device -
* many systems will not have a keyboard.
*/
static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
unsigned int code, int hz)
{
struct snd_soc_component *component = input_get_drvdata(dev);
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
switch (code) {
case SND_BELL:
if (hz)
hz = 1000;
fallthrough;
case SND_TONE:
break;
default:
return -1;
}
/* Kick the beep from a workqueue */
wm8962->beep_rate = hz;
schedule_work(&wm8962->beep_work);
return 0;
}
static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
long int time;
int ret;
ret = kstrtol(buf, 10, &time);
if (ret != 0)
return ret;
input_event(wm8962->beep, EV_SND, SND_TONE, time);
return count;
}
static DEVICE_ATTR_WO(beep);
static void wm8962_init_beep(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
int ret;
wm8962->beep = devm_input_allocate_device(component->dev);
if (!wm8962->beep) {
dev_err(component->dev, "Failed to allocate beep device\n");
return;
}
INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
wm8962->beep_rate = 0;
wm8962->beep->name = "WM8962 Beep Generator";
wm8962->beep->phys = dev_name(component->dev);
wm8962->beep->id.bustype = BUS_I2C;
wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
wm8962->beep->event = wm8962_beep_event;
wm8962->beep->dev.parent = component->dev;
input_set_drvdata(wm8962->beep, component);
ret = input_register_device(wm8962->beep);
if (ret != 0) {
wm8962->beep = NULL;
dev_err(component->dev, "Failed to register beep device\n");
}
ret = device_create_file(component->dev, &dev_attr_beep);
if (ret != 0) {
dev_err(component->dev, "Failed to create keyclick file: %d\n",
ret);
}
}
static void wm8962_free_beep(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
device_remove_file(component->dev, &dev_attr_beep);
cancel_work_sync(&wm8962->beep_work);
wm8962->beep = NULL;
snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
}
static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
{
int mask = 0;
int val = 0;
/* Some of the GPIOs are behind MFP configuration and need to
* be put into GPIO mode. */
switch (gpio) {
case 2:
mask = WM8962_CLKOUT2_SEL_MASK;
val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
break;
case 3:
mask = WM8962_CLKOUT3_SEL_MASK;
val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
break;
default:
break;
}
if (mask)
regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
mask, val);
}
#ifdef CONFIG_GPIOLIB
static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
/* The WM8962 GPIOs aren't linearly numbered. For simplicity
* we export linear numbers and error out if the unsupported
* ones are requsted.
*/
switch (offset + 1) {
case 2:
case 3:
case 5:
case 6:
break;
default:
return -EINVAL;
}
wm8962_set_gpio_mode(wm8962, offset + 1);
return 0;
}
static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
struct snd_soc_component *component = wm8962->component;
snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
}
static int wm8962_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
struct snd_soc_component *component = wm8962->component;
int ret, val;
/* Force function 1 (logic output) */
val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
if (ret < 0)
return ret;
return 0;
}
static const struct gpio_chip wm8962_template_chip = {
.label = "wm8962",
.owner = THIS_MODULE,
.request = wm8962_gpio_request,
.direction_output = wm8962_gpio_direction_out,
.set = wm8962_gpio_set,
.can_sleep = 1,
};
static void wm8962_init_gpio(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
struct wm8962_pdata *pdata = &wm8962->pdata;
int ret;
wm8962->gpio_chip = wm8962_template_chip;
wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
wm8962->gpio_chip.parent = component->dev;
if (pdata->gpio_base)
wm8962->gpio_chip.base = pdata->gpio_base;
else
wm8962->gpio_chip.base = -1;
ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962);
if (ret != 0)
dev_err(component->dev, "Failed to add GPIOs: %d\n", ret);
}
static void wm8962_free_gpio(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
gpiochip_remove(&wm8962->gpio_chip);
}
#else
static void wm8962_init_gpio(struct snd_soc_component *component)
{
}
static void wm8962_free_gpio(struct snd_soc_component *component)
{
}
#endif
static int wm8962_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
int i;
bool dmicclk, dmicdat;
wm8962->component = component;
wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
/* This should really be moved into the regulator core */
for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
ret = devm_regulator_register_notifier(
wm8962->supplies[i].consumer,
&wm8962->disable_nb[i]);
if (ret != 0) {
dev_err(component->dev,
"Failed to register regulator notifier: %d\n",
ret);
}
}
wm8962_add_widgets(component);
/* Save boards having to disable DMIC when not in use */
dmicclk = false;
dmicdat = false;
for (i = 1; i < WM8962_MAX_GPIO; i++) {
/*
* Register 515 (WM8962_GPIO_BASE + 3) does not exist,
* so skip its access
*/
if (i == 3)
continue;
switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i)
& WM8962_GP2_FN_MASK) {
case WM8962_GPIO_FN_DMICCLK:
dmicclk = true;
break;
case WM8962_GPIO_FN_DMICDAT:
dmicdat = true;
break;
default:
break;
}
}
if (!dmicclk || !dmicdat) {
dev_dbg(component->dev, "DMIC not in use, disabling\n");
snd_soc_dapm_nc_pin(dapm, "DMICDAT");
}
if (dmicclk != dmicdat)
dev_warn(component->dev, "DMIC GPIOs partially configured\n");
wm8962_init_beep(component);
wm8962_init_gpio(component);
return 0;
}
static void wm8962_remove(struct snd_soc_component *component)
{
struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&wm8962->mic_work);
wm8962_free_gpio(component);
wm8962_free_beep(component);
}
static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
.probe = wm8962_probe,
.remove = wm8962_remove,
.set_bias_level = wm8962_set_bias_level,
.set_pll = wm8962_set_fll,
.use_pmdown_time = 1,
.endianness = 1,
};
/* Improve power consumption for IN4 DC measurement mode */
static const struct reg_sequence wm8962_dc_measure[] = {
{ 0xfd, 0x1 },
{ 0xcc, 0x40 },
{ 0xfd, 0 },
};
static const struct regmap_config wm8962_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = WM8962_MAX_REGISTER,
.reg_defaults = wm8962_reg,
.num_reg_defaults = ARRAY_SIZE(wm8962_reg),
.volatile_reg = wm8962_volatile_register,
.readable_reg = wm8962_readable_register,
.cache_type = REGCACHE_MAPLE,
};
static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
struct wm8962_pdata *pdata)
{
const struct device_node *np = i2c->dev.of_node;
u32 val32;
int i;
if (of_property_read_bool(np, "spk-mono"))
pdata->spk_mono = true;
if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
pdata->mic_cfg = val32;
if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
ARRAY_SIZE(pdata->gpio_init)) >= 0)
for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
/*
* The range of GPIO register value is [0x0, 0xffff]
* While the default value of each register is 0x0
* Any other value will be regarded as default value
*/
if (pdata->gpio_init[i] > 0xffff)
pdata->gpio_init[i] = 0x0;
}
pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL);
return PTR_ERR_OR_ZERO(pdata->mclk);
}
static int wm8962_i2c_probe(struct i2c_client *i2c)
{
struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
struct wm8962_priv *wm8962;
unsigned int reg;
int ret, i, irq_pol, trigger;
wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
if (wm8962 == NULL)
return -ENOMEM;
mutex_init(&wm8962->dsp2_ena_lock);
i2c_set_clientdata(i2c, wm8962);
INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
init_completion(&wm8962->fll_lock);
wm8962->irq = i2c->irq;
/* If platform data was supplied, update the default data in priv */
if (pdata) {
memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
} else if (i2c->dev.of_node) {
ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
if (ret != 0)
return ret;
}
for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
wm8962->supplies[i].supply = wm8962_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
wm8962->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
goto err;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
wm8962->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
if (IS_ERR(wm8962->regmap)) {
ret = PTR_ERR(wm8962->regmap);
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
goto err_enable;
}
/*
* We haven't marked the chip revision as volatile due to
* sharing a register with the right input volume; explicitly
* bypass the cache to read it.
*/
regcache_cache_bypass(wm8962->regmap, true);
ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID register\n");
goto err_enable;
}
if (reg != 0x6243) {
dev_err(&i2c->dev,
"Device is not a WM8962, ID %x != 0x6243\n", reg);
ret = -EINVAL;
goto err_enable;
}
ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read device revision: %d\n",
ret);
goto err_enable;
}
dev_info(&i2c->dev, "customer id %x revision %c\n",
(reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
+ 'A');
regcache_cache_bypass(wm8962->regmap, false);
ret = wm8962_reset(wm8962);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to issue reset\n");
goto err_enable;
}
/* SYSCLK defaults to on; make sure it is off so we can safely
* write to registers if the device is declocked.
*/
regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
WM8962_SYSCLK_ENA, 0);
/* Ensure we have soft control over all registers */
regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
/* Ensure that the oscillator and PLLs are disabled */
regmap_update_bits(wm8962->regmap, WM8962_PLL2,
WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
0);
/* Apply static configuration for GPIOs */
for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
if (wm8962->pdata.gpio_init[i]) {
wm8962_set_gpio_mode(wm8962, i + 1);
regmap_write(wm8962->regmap, 0x200 + i,
wm8962->pdata.gpio_init[i] & 0xffff);
}
/* Put the speakers into mono mode? */
if (wm8962->pdata.spk_mono)
regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
/* Micbias setup, detection enable and detection
* threasholds. */
if (wm8962->pdata.mic_cfg)
regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
WM8962_MICDET_ENA |
WM8962_MICDET_THR_MASK |
WM8962_MICSHORT_THR_MASK |
WM8962_MICBIAS_LVL,
wm8962->pdata.mic_cfg);
/* Latch volume update bits */
regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
WM8962_IN_VU, WM8962_IN_VU);
regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
WM8962_IN_VU, WM8962_IN_VU);
regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
WM8962_ADC_VU, WM8962_ADC_VU);
regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
WM8962_ADC_VU, WM8962_ADC_VU);
regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
WM8962_DAC_VU, WM8962_DAC_VU);
regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
WM8962_DAC_VU, WM8962_DAC_VU);
regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
WM8962_HPOUT_VU, WM8962_HPOUT_VU);
regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
WM8962_HPOUT_VU, WM8962_HPOUT_VU);
/* Stereo control for EQ */
regmap_update_bits(wm8962->regmap, WM8962_EQ1,
WM8962_EQ_SHARED_COEFF, 0);
/* Don't debouce interrupts so we don't need SYSCLK */
regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
0);
if (wm8962->pdata.in4_dc_measure) {
ret = regmap_register_patch(wm8962->regmap,
wm8962_dc_measure,
ARRAY_SIZE(wm8962_dc_measure));
if (ret != 0)
dev_err(&i2c->dev,
"Failed to configure for DC measurement: %d\n",
ret);
}
if (wm8962->irq) {
if (wm8962->pdata.irq_active_low) {
trigger = IRQF_TRIGGER_LOW;
irq_pol = WM8962_IRQ_POL;
} else {
trigger = IRQF_TRIGGER_HIGH;
irq_pol = 0;
}
regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
WM8962_IRQ_POL, irq_pol);
ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
wm8962_irq,
trigger | IRQF_ONESHOT,
"wm8962", &i2c->dev);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
wm8962->irq, ret);
wm8962->irq = 0;
/* Non-fatal */
} else {
/* Enable some IRQs by default */
regmap_update_bits(wm8962->regmap,
WM8962_INTERRUPT_STATUS_2_MASK,
WM8962_FLL_LOCK_EINT |
WM8962_TEMP_SHUT_EINT |
WM8962_FIFOS_ERR_EINT, 0);
}
}
pm_runtime_enable(&i2c->dev);
pm_request_idle(&i2c->dev);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8962, &wm8962_dai, 1);
if (ret < 0)
goto err_pm_runtime;
regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
WM8962_TEMP_ENA_HP_MASK, 0);
regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
WM8962_TEMP_ENA_SPK_MASK, 0);
regcache_cache_only(wm8962->regmap, true);
/* The drivers should power up as needed */
regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
return 0;
err_pm_runtime:
pm_runtime_disable(&i2c->dev);
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
err:
return ret;
}
static void wm8962_i2c_remove(struct i2c_client *client)
{
pm_runtime_disable(&client->dev);
}
#ifdef CONFIG_PM
static int wm8962_runtime_resume(struct device *dev)
{
struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(wm8962->pdata.mclk);
if (ret) {
dev_err(dev, "Failed to enable MCLK: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
wm8962->supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
goto disable_clock;
}
regcache_cache_only(wm8962->regmap, false);
wm8962_reset(wm8962);
regcache_mark_dirty(wm8962->regmap);
/* SYSCLK defaults to on; make sure it is off so we can safely
* write to registers if the device is declocked.
*/
regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2,
WM8962_SYSCLK_ENA, 0);
/* Ensure we have soft control over all registers */
regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
/* Ensure that the oscillator and PLLs are disabled */
regmap_update_bits(wm8962->regmap, WM8962_PLL2,
WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
0);
regcache_sync(wm8962->regmap);
regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
/* Bias enable at 2*5k (fast start-up) */
regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
WM8962_BIAS_ENA | 0x180);
msleep(5);
return 0;
disable_clock:
clk_disable_unprepare(wm8962->pdata.mclk);
return ret;
}
static int wm8962_runtime_suspend(struct device *dev)
{
struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
WM8962_STARTUP_BIAS_ENA |
WM8962_VMID_BUF_ENA, 0);
regcache_cache_only(wm8962->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
wm8962->supplies);
clk_disable_unprepare(wm8962->pdata.mclk);
return 0;
}
#endif
static const struct dev_pm_ops wm8962_pm = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
};
static const struct i2c_device_id wm8962_i2c_id[] = {
{ "wm8962", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
static const struct of_device_id wm8962_of_match[] = {
{ .compatible = "wlf,wm8962", },
{ }
};
MODULE_DEVICE_TABLE(of, wm8962_of_match);
static struct i2c_driver wm8962_i2c_driver = {
.driver = {
.name = "wm8962",
.of_match_table = wm8962_of_match,
.pm = &wm8962_pm,
},
.probe = wm8962_i2c_probe,
.remove = wm8962_i2c_remove,
.id_table = wm8962_i2c_id,
};
module_i2c_driver(wm8962_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8962 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8962.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADAU7002 Stereo PDM-to-I2S/TDM converter driver
*
* Copyright 2014-2016 Analog Devices
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
struct adau7002_priv {
int wakeup_delay;
};
static int adau7002_aif_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct adau7002_priv *adau7002 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (adau7002->wakeup_delay)
msleep(adau7002->wakeup_delay);
break;
}
return 0;
}
static int adau7002_component_probe(struct snd_soc_component *component)
{
struct adau7002_priv *adau7002;
adau7002 = devm_kzalloc(component->dev, sizeof(*adau7002),
GFP_KERNEL);
if (!adau7002)
return -ENOMEM;
device_property_read_u32(component->dev, "wakeup-delay-ms",
&adau7002->wakeup_delay);
snd_soc_component_set_drvdata(component, adau7002);
return 0;
}
static const struct snd_soc_dapm_widget adau7002_widgets[] = {
SND_SOC_DAPM_AIF_OUT_E("ADAU AIF", "Capture", 0,
SND_SOC_NOPM, 0, 0, adau7002_aif_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("PDM_DAT"),
SND_SOC_DAPM_REGULATOR_SUPPLY("IOVDD", 0, 0),
};
static const struct snd_soc_dapm_route adau7002_routes[] = {
{ "ADAU AIF", NULL, "PDM_DAT"},
{ "Capture", NULL, "PDM_DAT" },
{ "Capture", NULL, "IOVDD" },
};
static struct snd_soc_dai_driver adau7002_dai = {
.name = "adau7002-hifi",
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE,
.sig_bits = 20,
},
};
static const struct snd_soc_component_driver adau7002_component_driver = {
.probe = adau7002_component_probe,
.dapm_widgets = adau7002_widgets,
.num_dapm_widgets = ARRAY_SIZE(adau7002_widgets),
.dapm_routes = adau7002_routes,
.num_dapm_routes = ARRAY_SIZE(adau7002_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static int adau7002_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev,
&adau7002_component_driver,
&adau7002_dai, 1);
}
#ifdef CONFIG_OF
static const struct of_device_id adau7002_dt_ids[] = {
{ .compatible = "adi,adau7002", },
{ }
};
MODULE_DEVICE_TABLE(of, adau7002_dt_ids);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id adau7002_acpi_match[] = {
{ "ADAU7002", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, adau7002_acpi_match);
#endif
static struct platform_driver adau7002_driver = {
.driver = {
.name = "adau7002",
.of_match_table = of_match_ptr(adau7002_dt_ids),
.acpi_match_table = ACPI_PTR(adau7002_acpi_match),
},
.probe = adau7002_probe,
};
module_platform_driver(adau7002_driver);
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("ADAU7002 Stereo PDM-to-I2S/TDM Converter driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/adau7002.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <linux/of_clk.h>
#include <linux/clk-provider.h>
#include "lpass-macro-common.h"
#define CDC_RX_TOP_TOP_CFG0 (0x0000)
#define CDC_RX_TOP_SWR_CTRL (0x0008)
#define CDC_RX_TOP_DEBUG (0x000C)
#define CDC_RX_TOP_DEBUG_BUS (0x0010)
#define CDC_RX_TOP_DEBUG_EN0 (0x0014)
#define CDC_RX_TOP_DEBUG_EN1 (0x0018)
#define CDC_RX_TOP_DEBUG_EN2 (0x001C)
#define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
#define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
#define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
#define CDC_RX_TOP_HPH_LUT_BYPASS_MASK BIT(7)
#define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C)
#define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030)
#define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034)
#define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038)
#define CDC_RX_TOP_HPHR_COMP_LUT (0x003C)
#define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040)
#define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044)
#define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070)
#define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074)
#define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078)
#define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C)
#define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080)
#define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084)
#define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088)
#define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C)
#define CDC_RX_TOP_RX_I2S_CTL (0x0090)
#define CDC_RX_TOP_TX_I2S2_CTL (0x0094)
#define CDC_RX_TOP_I2S_CLK (0x0098)
#define CDC_RX_TOP_I2S_RESET (0x009C)
#define CDC_RX_TOP_I2S_MUX (0x00A0)
#define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100)
#define CDC_RX_CLK_MCLK_EN_MASK BIT(0)
#define CDC_RX_CLK_MCLK_ENABLE BIT(0)
#define CDC_RX_CLK_MCLK2_EN_MASK BIT(1)
#define CDC_RX_CLK_MCLK2_ENABLE BIT(1)
#define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104)
#define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0)
#define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0)
#define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1)
#define CDC_RX_FS_MCLK_CNT_CLR BIT(1)
#define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)
#define CDC_RX_SWR_CLK_EN_MASK BIT(0)
#define CDC_RX_SWR_RESET_MASK BIT(1)
#define CDC_RX_SWR_RESET BIT(1)
#define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)
#define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110)
#define CDC_RX_SOFTCLIP_CRC (0x0140)
#define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0)
#define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144)
#define CDC_RX_SOFTCLIP_EN_MASK BIT(0)
#define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180)
#define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)
#define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)
#define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184)
#define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0)
#define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)
#define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188)
#define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C)
#define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190)
#define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194)
#define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198)
#define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C)
#define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0)
#define CDC_RX_CLSH_CRC (0x0200)
#define CDC_RX_CLSH_CLK_EN_MASK BIT(0)
#define CDC_RX_CLSH_DLY_CTRL (0x0204)
#define CDC_RX_CLSH_DECAY_CTRL (0x0208)
#define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0)
#define CDC_RX_CLSH_HPH_V_PA (0x020C)
#define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0)
#define CDC_RX_CLSH_EAR_V_PA (0x0210)
#define CDC_RX_CLSH_HPH_V_HD (0x0214)
#define CDC_RX_CLSH_EAR_V_HD (0x0218)
#define CDC_RX_CLSH_K1_MSB (0x021C)
#define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0)
#define CDC_RX_CLSH_K1_LSB (0x0220)
#define CDC_RX_CLSH_K2_MSB (0x0224)
#define CDC_RX_CLSH_K2_LSB (0x0228)
#define CDC_RX_CLSH_IDLE_CTRL (0x022C)
#define CDC_RX_CLSH_IDLE_HPH (0x0230)
#define CDC_RX_CLSH_IDLE_EAR (0x0234)
#define CDC_RX_CLSH_TEST0 (0x0238)
#define CDC_RX_CLSH_TEST1 (0x023C)
#define CDC_RX_CLSH_OVR_VREF (0x0240)
#define CDC_RX_CLSH_CLSG_CTL (0x0244)
#define CDC_RX_CLSH_CLSG_CFG1 (0x0248)
#define CDC_RX_CLSH_CLSG_CFG2 (0x024C)
#define CDC_RX_BCL_VBAT_PATH_CTL (0x0280)
#define CDC_RX_BCL_VBAT_CFG (0x0284)
#define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288)
#define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C)
#define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290)
#define CDC_RX_BCL_VBAT_PK_EST1 (0x0294)
#define CDC_RX_BCL_VBAT_PK_EST2 (0x0298)
#define CDC_RX_BCL_VBAT_PK_EST3 (0x029C)
#define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0)
#define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4)
#define CDC_RX_BCL_VBAT_TAC1 (0x02A8)
#define CDC_RX_BCL_VBAT_TAC2 (0x02AC)
#define CDC_RX_BCL_VBAT_TAC3 (0x02B0)
#define CDC_RX_BCL_VBAT_TAC4 (0x02B4)
#define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8)
#define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC)
#define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0)
#define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4)
#define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8)
#define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC)
#define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0)
#define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4)
#define CDC_RX_BCL_VBAT_BAN (0x02D8)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8)
#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC)
#define CDC_RX_BCL_VBAT_ATTN1 (0x0300)
#define CDC_RX_BCL_VBAT_ATTN2 (0x0304)
#define CDC_RX_BCL_VBAT_ATTN3 (0x0308)
#define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C)
#define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310)
#define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314)
#define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318)
#define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C)
#define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320)
#define CDC_RX_BCL_VBAT_DECODE_ST (0x0324)
#define CDC_RX_INTR_CTRL_CFG (0x0340)
#define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344)
#define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360)
#define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368)
#define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370)
#define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380)
#define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388)
#define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390)
#define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0)
#define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8)
#define CDC_RX_INTR_CTRL_SET0 (0x03D0)
#define CDC_RX_RXn_RX_PATH_CTL(n) (0x0400 + 0x80 * n)
#define CDC_RX_RX0_RX_PATH_CTL (0x0400)
#define CDC_RX_PATH_RESET_EN_MASK BIT(6)
#define CDC_RX_PATH_CLK_EN_MASK BIT(5)
#define CDC_RX_PATH_CLK_ENABLE BIT(5)
#define CDC_RX_PATH_PGA_MUTE_MASK BIT(4)
#define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4)
#define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0)
#define CDC_RX_RXn_RX_PATH_CFG0(n) (0x0404 + 0x80 * n)
#define CDC_RX_RXn_COMP_EN_MASK BIT(1)
#define CDC_RX_RX0_RX_PATH_CFG0 (0x0404)
#define CDC_RX_RXn_CLSH_EN_MASK BIT(6)
#define CDC_RX_DLY_ZN_EN_MASK BIT(3)
#define CDC_RX_DLY_ZN_ENABLE BIT(3)
#define CDC_RX_RXn_HD2_EN_MASK BIT(2)
#define CDC_RX_RXn_RX_PATH_CFG1(n) (0x0408 + 0x80 * n)
#define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4)
#define CDC_RX_RX0_RX_PATH_CFG1 (0x0408)
#define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1)
#define CDC_RX_RXn_RX_PATH_CFG2(n) (0x040C + 0x80 * n)
#define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0)
#define CDC_RX_RX0_RX_PATH_CFG2 (0x040C)
#define CDC_RX_RXn_RX_PATH_CFG3(n) (0x0410 + 0x80 * n)
#define CDC_RX_RX0_RX_PATH_CFG3 (0x0410)
#define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0)
#define CDC_RX_DC_COEFF_SEL_TWO 0x2
#define CDC_RX_RXn_RX_VOL_CTL(n) (0x0414 + 0x80 * n)
#define CDC_RX_RX0_RX_VOL_CTL (0x0414)
#define CDC_RX_RXn_RX_PATH_MIX_CTL(n) (0x0418 + 0x80 * n)
#define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0)
#define CDC_RX_RXn_MIX_RESET_MASK BIT(6)
#define CDC_RX_RXn_MIX_RESET BIT(6)
#define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5)
#define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418)
#define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C)
#define CDC_RX_RXn_RX_VOL_MIX_CTL(n) (0x0420 + 0x80 * n)
#define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420)
#define CDC_RX_RX0_RX_PATH_SEC1 (0x0424)
#define CDC_RX_RX0_RX_PATH_SEC2 (0x0428)
#define CDC_RX_RX0_RX_PATH_SEC3 (0x042C)
#define CDC_RX_RX0_RX_PATH_SEC4 (0x0430)
#define CDC_RX_RX0_RX_PATH_SEC7 (0x0434)
#define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0)
#define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
#define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438)
#define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C)
#define CDC_RX_RXn_RX_PATH_DSM_CTL(n) (0x0440 + 0x80 * n)
#define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0)
#define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440)
#define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444)
#define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448)
#define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C)
#define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450)
#define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454)
#define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458)
#define CDC_RX_RX1_RX_PATH_CTL (0x0480)
#define CDC_RX_RX1_RX_PATH_CFG0 (0x0484)
#define CDC_RX_RX1_RX_PATH_CFG1 (0x0488)
#define CDC_RX_RX1_RX_PATH_CFG2 (0x048C)
#define CDC_RX_RX1_RX_PATH_CFG3 (0x0490)
#define CDC_RX_RX1_RX_VOL_CTL (0x0494)
#define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498)
#define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C)
#define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0)
#define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4)
#define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8)
#define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC)
#define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2)
#define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0)
#define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4)
#define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8)
#define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC)
#define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0)
#define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4)
#define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8)
#define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC)
#define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0)
#define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4)
#define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8)
#define CDC_RX_RX2_RX_PATH_CTL (0x0500)
#define CDC_RX_RX2_RX_PATH_CFG0 (0x0504)
#define CDC_RX_RX2_CLSH_EN_MASK BIT(4)
#define CDC_RX_RX2_DLY_Z_EN_MASK BIT(3)
#define CDC_RX_RX2_RX_PATH_CFG1 (0x0508)
#define CDC_RX_RX2_RX_PATH_CFG2 (0x050C)
#define CDC_RX_RX2_RX_PATH_CFG3 (0x0510)
#define CDC_RX_RX2_RX_VOL_CTL (0x0514)
#define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518)
#define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C)
#define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520)
#define CDC_RX_RX2_RX_PATH_SEC0 (0x0524)
#define CDC_RX_RX2_RX_PATH_SEC1 (0x0528)
#define CDC_RX_RX2_RX_PATH_SEC2 (0x052C)
#define CDC_RX_RX2_RX_PATH_SEC3 (0x0530)
#define CDC_RX_RX2_RX_PATH_SEC4 (0x0534)
#define CDC_RX_RX2_RX_PATH_SEC5 (0x0538)
#define CDC_RX_RX2_RX_PATH_SEC6 (0x053C)
#define CDC_RX_RX2_RX_PATH_SEC7 (0x0540)
#define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544)
#define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548)
#define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C)
#define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780)
#define CDC_RX_IDLE_DETECT_CFG0 (0x0784)
#define CDC_RX_IDLE_DETECT_CFG1 (0x0788)
#define CDC_RX_IDLE_DETECT_CFG2 (0x078C)
#define CDC_RX_IDLE_DETECT_CFG3 (0x0790)
#define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n)
#define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0)
#define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1)
#define CDC_RX_COMPANDERn_HALT_MASK BIT(2)
#define CDC_RX_COMPANDER0_CTL0 (0x0800)
#define CDC_RX_COMPANDER0_CTL1 (0x0804)
#define CDC_RX_COMPANDER0_CTL2 (0x0808)
#define CDC_RX_COMPANDER0_CTL3 (0x080C)
#define CDC_RX_COMPANDER0_CTL4 (0x0810)
#define CDC_RX_COMPANDER0_CTL5 (0x0814)
#define CDC_RX_COMPANDER0_CTL6 (0x0818)
#define CDC_RX_COMPANDER0_CTL7 (0x081C)
#define CDC_RX_COMPANDER1_CTL0 (0x0840)
#define CDC_RX_COMPANDER1_CTL1 (0x0844)
#define CDC_RX_COMPANDER1_CTL2 (0x0848)
#define CDC_RX_COMPANDER1_CTL3 (0x084C)
#define CDC_RX_COMPANDER1_CTL4 (0x0850)
#define CDC_RX_COMPANDER1_CTL5 (0x0854)
#define CDC_RX_COMPANDER1_CTL6 (0x0858)
#define CDC_RX_COMPANDER1_CTL7 (0x085C)
#define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5)
#define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20)
#define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24)
#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)
#define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C)
#define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30)
#define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0)
#define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4)
#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)
#define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC)
#define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0)
#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00)
#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04)
#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08)
#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C)
#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10)
#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14)
#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18)
#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C)
#define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40)
#define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44)
#define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50)
#define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54)
#define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00)
#define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04)
#define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40)
#define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44)
#define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80)
#define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84)
#define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00)
#define CDC_RX_EC_ASRC0_CTL0 (0x0D04)
#define CDC_RX_EC_ASRC0_CTL1 (0x0D08)
#define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C)
#define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10)
#define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14)
#define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18)
#define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C)
#define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20)
#define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40)
#define CDC_RX_EC_ASRC1_CTL0 (0x0D44)
#define CDC_RX_EC_ASRC1_CTL1 (0x0D48)
#define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C)
#define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50)
#define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54)
#define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58)
#define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C)
#define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60)
#define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80)
#define CDC_RX_EC_ASRC2_CTL0 (0x0D84)
#define CDC_RX_EC_ASRC2_CTL1 (0x0D88)
#define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C)
#define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90)
#define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94)
#define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98)
#define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C)
#define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0)
#define CDC_RX_DSD0_PATH_CTL (0x0F00)
#define CDC_RX_DSD0_CFG0 (0x0F04)
#define CDC_RX_DSD0_CFG1 (0x0F08)
#define CDC_RX_DSD0_CFG2 (0x0F0C)
#define CDC_RX_DSD1_PATH_CTL (0x0F80)
#define CDC_RX_DSD1_CFG0 (0x0F84)
#define CDC_RX_DSD1_CFG1 (0x0F88)
#define CDC_RX_DSD1_CFG2 (0x0F8C)
#define RX_MAX_OFFSET (0x0F8C)
#define MCLK_FREQ 19200000
#define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
SNDRV_PCM_RATE_384000)
/* Fractional Rates */
#define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
#define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
#define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_48000)
#define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S24_3LE)
#define RX_MACRO_MAX_DMA_CH_PER_PORT 2
#define RX_MACRO_EC_MIX_TX0_MASK 0xf0
#define RX_MACRO_EC_MIX_TX1_MASK 0x0f
#define RX_MACRO_EC_MIX_TX2_MASK 0x0f
#define COMP_MAX_COEFF 25
#define RX_NUM_CLKS_MAX 5
struct comp_coeff_val {
u8 lsb;
u8 msb;
};
enum {
HPH_ULP,
HPH_LOHIFI,
HPH_MODE_MAX,
};
static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {
{
{0x40, 0x00},
{0x4C, 0x00},
{0x5A, 0x00},
{0x6B, 0x00},
{0x7F, 0x00},
{0x97, 0x00},
{0xB3, 0x00},
{0xD5, 0x00},
{0xFD, 0x00},
{0x2D, 0x01},
{0x66, 0x01},
{0xA7, 0x01},
{0xF8, 0x01},
{0x57, 0x02},
{0xC7, 0x02},
{0x4B, 0x03},
{0xE9, 0x03},
{0xA3, 0x04},
{0x7D, 0x05},
{0x90, 0x06},
{0xD1, 0x07},
{0x49, 0x09},
{0x00, 0x0B},
{0x01, 0x0D},
{0x59, 0x0F},
},
{
{0x40, 0x00},
{0x4C, 0x00},
{0x5A, 0x00},
{0x6B, 0x00},
{0x80, 0x00},
{0x98, 0x00},
{0xB4, 0x00},
{0xD5, 0x00},
{0xFE, 0x00},
{0x2E, 0x01},
{0x66, 0x01},
{0xA9, 0x01},
{0xF8, 0x01},
{0x56, 0x02},
{0xC4, 0x02},
{0x4F, 0x03},
{0xF0, 0x03},
{0xAE, 0x04},
{0x8B, 0x05},
{0x8E, 0x06},
{0xBC, 0x07},
{0x56, 0x09},
{0x0F, 0x0B},
{0x13, 0x0D},
{0x6F, 0x0F},
},
};
struct rx_macro_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
enum {
INTERP_HPHL,
INTERP_HPHR,
INTERP_AUX,
INTERP_MAX
};
enum {
RX_MACRO_RX0,
RX_MACRO_RX1,
RX_MACRO_RX2,
RX_MACRO_RX3,
RX_MACRO_RX4,
RX_MACRO_RX5,
RX_MACRO_PORTS_MAX
};
enum {
RX_MACRO_COMP1, /* HPH_L */
RX_MACRO_COMP2, /* HPH_R */
RX_MACRO_COMP_MAX
};
enum {
RX_MACRO_EC0_MUX = 0,
RX_MACRO_EC1_MUX,
RX_MACRO_EC2_MUX,
RX_MACRO_EC_MUX_MAX,
};
enum {
INTn_1_INP_SEL_ZERO = 0,
INTn_1_INP_SEL_DEC0,
INTn_1_INP_SEL_DEC1,
INTn_1_INP_SEL_IIR0,
INTn_1_INP_SEL_IIR1,
INTn_1_INP_SEL_RX0,
INTn_1_INP_SEL_RX1,
INTn_1_INP_SEL_RX2,
INTn_1_INP_SEL_RX3,
INTn_1_INP_SEL_RX4,
INTn_1_INP_SEL_RX5,
};
enum {
INTn_2_INP_SEL_ZERO = 0,
INTn_2_INP_SEL_RX0,
INTn_2_INP_SEL_RX1,
INTn_2_INP_SEL_RX2,
INTn_2_INP_SEL_RX3,
INTn_2_INP_SEL_RX4,
INTn_2_INP_SEL_RX5,
};
enum {
INTERP_MAIN_PATH,
INTERP_MIX_PATH,
};
/* Codec supports 2 IIR filters */
enum {
IIR0 = 0,
IIR1,
IIR_MAX,
};
/* Each IIR has 5 Filter Stages */
enum {
BAND1 = 0,
BAND2,
BAND3,
BAND4,
BAND5,
BAND_MAX,
};
#define RX_MACRO_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
#define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = rx_macro_iir_filter_info, \
.get = rx_macro_get_iir_band_audio_mixer, \
.put = rx_macro_put_iir_band_audio_mixer, \
.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
.iir_idx = iidx, \
.band_idx = bidx, \
.bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
} \
}
struct interp_sample_rate {
int sample_rate;
int rate_val;
};
static struct interp_sample_rate sr_val_tbl[] = {
{8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
{192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
{176400, 0xB}, {352800, 0xC},
};
enum {
RX_MACRO_AIF_INVALID = 0,
RX_MACRO_AIF1_PB,
RX_MACRO_AIF2_PB,
RX_MACRO_AIF3_PB,
RX_MACRO_AIF4_PB,
RX_MACRO_AIF_ECHO,
RX_MACRO_MAX_DAIS,
};
enum {
RX_MACRO_AIF1_CAP = 0,
RX_MACRO_AIF2_CAP,
RX_MACRO_AIF3_CAP,
RX_MACRO_MAX_AIF_CAP_DAIS
};
struct rx_macro {
struct device *dev;
int comp_enabled[RX_MACRO_COMP_MAX];
/* Main path clock users count */
int main_clk_users[INTERP_MAX];
int rx_port_value[RX_MACRO_PORTS_MAX];
u16 prim_int_users[INTERP_MAX];
int rx_mclk_users;
int clsh_users;
int rx_mclk_cnt;
bool is_ear_mode_on;
bool hph_pwr_mode;
bool hph_hd2_mode;
struct snd_soc_component *component;
unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];
unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];
u16 bit_width[RX_MACRO_MAX_DAIS];
int is_softclip_on;
int is_aux_hpf_on;
int softclip_clk_users;
struct lpass_macro *pds;
struct regmap *regmap;
struct clk *mclk;
struct clk *npl;
struct clk *macro;
struct clk *dcodec;
struct clk *fsgen;
struct clk_hw hw;
};
#define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
struct wcd_iir_filter_ctl {
unsigned int iir_idx;
unsigned int band_idx;
struct soc_bytes_ext bytes_ext;
};
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
static const char * const rx_int_mix_mux_text[] = {
"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
};
static const char * const rx_prim_mix_text[] = {
"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
"RX3", "RX4", "RX5"
};
static const char * const rx_sidetone_mix_text[] = {
"ZERO", "SRC0", "SRC1", "SRC_SUM"
};
static const char * const iir_inp_mux_text[] = {
"ZERO", "DEC0", "DEC1", "DEC2", "DEC3",
"RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
};
static const char * const rx_int_dem_inp_mux_text[] = {
"NORMAL_DSM_OUT", "CLSH_DSM_OUT",
};
static const char * const rx_int0_1_interp_mux_text[] = {
"ZERO", "RX INT0_1 MIX1",
};
static const char * const rx_int1_1_interp_mux_text[] = {
"ZERO", "RX INT1_1 MIX1",
};
static const char * const rx_int2_1_interp_mux_text[] = {
"ZERO", "RX INT2_1 MIX1",
};
static const char * const rx_int0_2_interp_mux_text[] = {
"ZERO", "RX INT0_2 MUX",
};
static const char * const rx_int1_2_interp_mux_text[] = {
"ZERO", "RX INT1_2 MUX",
};
static const char * const rx_int2_2_interp_mux_text[] = {
"ZERO", "RX INT2_2 MUX",
};
static const char *const rx_macro_mux_text[] = {
"ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB"
};
static const char *const rx_macro_hph_pwr_mode_text[] = {
"ULP", "LOHIFI"
};
static const char * const rx_echo_mux_text[] = {
"ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2"
};
static const struct soc_enum rx_macro_hph_pwr_mode_enum =
SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text);
static const struct soc_enum rx_mix_tx2_mux_enum =
SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
static const struct soc_enum rx_mix_tx1_mux_enum =
SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
static const struct soc_enum rx_mix_tx0_mux_enum =
SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
rx_int_mix_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
rx_int_mix_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
rx_int_mix_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,
rx_prim_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,
rx_sidetone_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,
rx_sidetone_mix_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,
rx_sidetone_mix_text);
static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
iir_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
rx_int0_1_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
rx_int1_1_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
rx_int2_1_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
rx_int0_2_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
rx_int1_2_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
rx_int2_2_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
rx_int_dem_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
rx_int_dem_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static const struct snd_kcontrol_new rx_mix_tx1_mux =
SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
static const struct snd_kcontrol_new rx_mix_tx2_mux =
SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
static const struct snd_kcontrol_new rx_int0_2_mux =
SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum);
static const struct snd_kcontrol_new rx_int1_2_mux =
SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum);
static const struct snd_kcontrol_new rx_int2_2_mux =
SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum);
static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum);
static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum);
static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum);
static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum);
static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum);
static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum);
static const struct snd_kcontrol_new iir0_inp0_mux =
SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum);
static const struct snd_kcontrol_new iir0_inp1_mux =
SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum);
static const struct snd_kcontrol_new iir0_inp2_mux =
SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum);
static const struct snd_kcontrol_new iir0_inp3_mux =
SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum);
static const struct snd_kcontrol_new iir1_inp0_mux =
SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum);
static const struct snd_kcontrol_new iir1_inp1_mux =
SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum);
static const struct snd_kcontrol_new iir1_inp2_mux =
SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum);
static const struct snd_kcontrol_new iir1_inp3_mux =
SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum);
static const struct snd_kcontrol_new rx_int0_1_interp_mux =
SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum);
static const struct snd_kcontrol_new rx_int1_1_interp_mux =
SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum);
static const struct snd_kcontrol_new rx_int2_1_interp_mux =
SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum);
static const struct snd_kcontrol_new rx_int0_2_interp_mux =
SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum);
static const struct snd_kcontrol_new rx_int1_2_interp_mux =
SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum);
static const struct snd_kcontrol_new rx_int2_2_interp_mux =
SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum);
static const struct snd_kcontrol_new rx_mix_tx0_mux =
SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
static const struct reg_default rx_defaults[] = {
/* RX Macro */
{ CDC_RX_TOP_TOP_CFG0, 0x00 },
{ CDC_RX_TOP_SWR_CTRL, 0x00 },
{ CDC_RX_TOP_DEBUG, 0x00 },
{ CDC_RX_TOP_DEBUG_BUS, 0x00 },
{ CDC_RX_TOP_DEBUG_EN0, 0x00 },
{ CDC_RX_TOP_DEBUG_EN1, 0x00 },
{ CDC_RX_TOP_DEBUG_EN2, 0x00 },
{ CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
{ CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
{ CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
{ CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
{ CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
{ CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
{ CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
{ CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
{ CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
{ CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
{ CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
{ CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
{ CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
{ CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
{ CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
{ CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
{ CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
{ CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
{ CDC_RX_TOP_RX_I2S_CTL, 0x0C },
{ CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
{ CDC_RX_TOP_I2S_CLK, 0x0C },
{ CDC_RX_TOP_I2S_RESET, 0x00 },
{ CDC_RX_TOP_I2S_MUX, 0x00 },
{ CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
{ CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
{ CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
{ CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
{ CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
{ CDC_RX_SOFTCLIP_CRC, 0x00 },
{ CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
{ CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
{ CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
{ CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
{ CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
{ CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
{ CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
{ CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
{ CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
{ CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
{ CDC_RX_CLSH_CRC, 0x00 },
{ CDC_RX_CLSH_DLY_CTRL, 0x03 },
{ CDC_RX_CLSH_DECAY_CTRL, 0x02 },
{ CDC_RX_CLSH_HPH_V_PA, 0x1C },
{ CDC_RX_CLSH_EAR_V_PA, 0x39 },
{ CDC_RX_CLSH_HPH_V_HD, 0x0C },
{ CDC_RX_CLSH_EAR_V_HD, 0x0C },
{ CDC_RX_CLSH_K1_MSB, 0x01 },
{ CDC_RX_CLSH_K1_LSB, 0x00 },
{ CDC_RX_CLSH_K2_MSB, 0x00 },
{ CDC_RX_CLSH_K2_LSB, 0x80 },
{ CDC_RX_CLSH_IDLE_CTRL, 0x00 },
{ CDC_RX_CLSH_IDLE_HPH, 0x00 },
{ CDC_RX_CLSH_IDLE_EAR, 0x00 },
{ CDC_RX_CLSH_TEST0, 0x07 },
{ CDC_RX_CLSH_TEST1, 0x00 },
{ CDC_RX_CLSH_OVR_VREF, 0x00 },
{ CDC_RX_CLSH_CLSG_CTL, 0x02 },
{ CDC_RX_CLSH_CLSG_CFG1, 0x9A },
{ CDC_RX_CLSH_CLSG_CFG2, 0x10 },
{ CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
{ CDC_RX_BCL_VBAT_CFG, 0x10 },
{ CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
{ CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
{ CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
{ CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
{ CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
{ CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
{ CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
{ CDC_RX_BCL_VBAT_RF_PROC1, 0x00 },
{ CDC_RX_BCL_VBAT_TAC1, 0x00 },
{ CDC_RX_BCL_VBAT_TAC2, 0x18 },
{ CDC_RX_BCL_VBAT_TAC3, 0x18 },
{ CDC_RX_BCL_VBAT_TAC4, 0x03 },
{ CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
{ CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
{ CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
{ CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
{ CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
{ CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
{ CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
{ CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
{ CDC_RX_BCL_VBAT_BAN, 0x0C },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
{ CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
{ CDC_RX_BCL_VBAT_ATTN1, 0x04 },
{ CDC_RX_BCL_VBAT_ATTN2, 0x08 },
{ CDC_RX_BCL_VBAT_ATTN3, 0x0C },
{ CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
{ CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
{ CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
{ CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
{ CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
{ CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
{ CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
{ CDC_RX_INTR_CTRL_CFG, 0x00 },
{ CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
{ CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
{ CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
{ CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
{ CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
{ CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
{ CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
{ CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
{ CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
{ CDC_RX_INTR_CTRL_SET0, 0x00 },
{ CDC_RX_RX0_RX_PATH_CTL, 0x04 },
{ CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
{ CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
{ CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
{ CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
{ CDC_RX_RX0_RX_VOL_CTL, 0x00 },
{ CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
{ CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
{ CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
{ CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
{ CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
{ CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
{ CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
{ CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
{ CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
{ CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
{ CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
{ CDC_RX_RX1_RX_PATH_CTL, 0x04 },
{ CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
{ CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
{ CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
{ CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
{ CDC_RX_RX1_RX_VOL_CTL, 0x00 },
{ CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
{ CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
{ CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
{ CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
{ CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
{ CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
{ CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
{ CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
{ CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
{ CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
{ CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
{ CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
{ CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
{ CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
{ CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
{ CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
{ CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
{ CDC_RX_RX2_RX_PATH_CTL, 0x04 },
{ CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
{ CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
{ CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
{ CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
{ CDC_RX_RX2_RX_VOL_CTL, 0x00 },
{ CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
{ CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
{ CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
{ CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
{ CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
{ CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
{ CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
{ CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
{ CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
{ CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
{ CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
{ CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
{ CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
{ CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
{ CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
{ CDC_RX_IDLE_DETECT_CFG0, 0x07 },
{ CDC_RX_IDLE_DETECT_CFG1, 0x3C },
{ CDC_RX_IDLE_DETECT_CFG2, 0x00 },
{ CDC_RX_IDLE_DETECT_CFG3, 0x00 },
{ CDC_RX_COMPANDER0_CTL0, 0x60 },
{ CDC_RX_COMPANDER0_CTL1, 0xDB },
{ CDC_RX_COMPANDER0_CTL2, 0xFF },
{ CDC_RX_COMPANDER0_CTL3, 0x35 },
{ CDC_RX_COMPANDER0_CTL4, 0xFF },
{ CDC_RX_COMPANDER0_CTL5, 0x00 },
{ CDC_RX_COMPANDER0_CTL6, 0x01 },
{ CDC_RX_COMPANDER0_CTL7, 0x28 },
{ CDC_RX_COMPANDER1_CTL0, 0x60 },
{ CDC_RX_COMPANDER1_CTL1, 0xDB },
{ CDC_RX_COMPANDER1_CTL2, 0xFF },
{ CDC_RX_COMPANDER1_CTL3, 0x35 },
{ CDC_RX_COMPANDER1_CTL4, 0xFF },
{ CDC_RX_COMPANDER1_CTL5, 0x00 },
{ CDC_RX_COMPANDER1_CTL6, 0x01 },
{ CDC_RX_COMPANDER1_CTL7, 0x28 },
{ CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
{ CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
{ CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
{ CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
{ CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
{ CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
{ CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
{ CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
{ CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
{ CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
{ CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
{ CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
{ CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
{ CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
{ CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
{ CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
{ CDC_RX_EC_ASRC0_CTL0, 0x00 },
{ CDC_RX_EC_ASRC0_CTL1, 0x00 },
{ CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
{ CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
{ CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
{ CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
{ CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
{ CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
{ CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
{ CDC_RX_EC_ASRC1_CTL0, 0x00 },
{ CDC_RX_EC_ASRC1_CTL1, 0x00 },
{ CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
{ CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
{ CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
{ CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
{ CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
{ CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
{ CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
{ CDC_RX_EC_ASRC2_CTL0, 0x00 },
{ CDC_RX_EC_ASRC2_CTL1, 0x00 },
{ CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
{ CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
{ CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
{ CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
{ CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
{ CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
{ CDC_RX_DSD0_PATH_CTL, 0x00 },
{ CDC_RX_DSD0_CFG0, 0x00 },
{ CDC_RX_DSD0_CFG1, 0x62 },
{ CDC_RX_DSD0_CFG2, 0x96 },
{ CDC_RX_DSD1_PATH_CTL, 0x00 },
{ CDC_RX_DSD1_CFG0, 0x00 },
{ CDC_RX_DSD1_CFG1, 0x62 },
{ CDC_RX_DSD1_CFG2, 0x96 },
};
static bool rx_is_wronly_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case CDC_RX_BCL_VBAT_GAIN_UPD_MON:
case CDC_RX_INTR_CTRL_CLR_COMMIT:
case CDC_RX_INTR_CTRL_PIN1_CLEAR0:
case CDC_RX_INTR_CTRL_PIN2_CLEAR0:
return true;
}
return false;
}
static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
{
/* Update volatile list for rx/tx macros */
switch (reg) {
case CDC_RX_TOP_HPHL_COMP_RD_LSB:
case CDC_RX_TOP_HPHL_COMP_WR_LSB:
case CDC_RX_TOP_HPHL_COMP_RD_MSB:
case CDC_RX_TOP_HPHL_COMP_WR_MSB:
case CDC_RX_TOP_HPHR_COMP_RD_LSB:
case CDC_RX_TOP_HPHR_COMP_WR_LSB:
case CDC_RX_TOP_HPHR_COMP_RD_MSB:
case CDC_RX_TOP_HPHR_COMP_WR_MSB:
case CDC_RX_TOP_DSD0_DEBUG_CFG2:
case CDC_RX_TOP_DSD1_DEBUG_CFG2:
case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
case CDC_RX_BCL_VBAT_DECODE_ST:
case CDC_RX_INTR_CTRL_PIN1_STATUS0:
case CDC_RX_INTR_CTRL_PIN2_STATUS0:
case CDC_RX_COMPANDER0_CTL6:
case CDC_RX_COMPANDER1_CTL6:
case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
case CDC_RX_EC_ASRC0_STATUS_FIFO:
case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
case CDC_RX_EC_ASRC1_STATUS_FIFO:
case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
case CDC_RX_EC_ASRC2_STATUS_FIFO:
return true;
}
return false;
}
static bool rx_is_rw_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_RX_TOP_TOP_CFG0:
case CDC_RX_TOP_SWR_CTRL:
case CDC_RX_TOP_DEBUG:
case CDC_RX_TOP_DEBUG_BUS:
case CDC_RX_TOP_DEBUG_EN0:
case CDC_RX_TOP_DEBUG_EN1:
case CDC_RX_TOP_DEBUG_EN2:
case CDC_RX_TOP_HPHL_COMP_WR_LSB:
case CDC_RX_TOP_HPHL_COMP_WR_MSB:
case CDC_RX_TOP_HPHL_COMP_LUT:
case CDC_RX_TOP_HPHR_COMP_WR_LSB:
case CDC_RX_TOP_HPHR_COMP_WR_MSB:
case CDC_RX_TOP_HPHR_COMP_LUT:
case CDC_RX_TOP_DSD0_DEBUG_CFG0:
case CDC_RX_TOP_DSD0_DEBUG_CFG1:
case CDC_RX_TOP_DSD0_DEBUG_CFG3:
case CDC_RX_TOP_DSD1_DEBUG_CFG0:
case CDC_RX_TOP_DSD1_DEBUG_CFG1:
case CDC_RX_TOP_DSD1_DEBUG_CFG3:
case CDC_RX_TOP_RX_I2S_CTL:
case CDC_RX_TOP_TX_I2S2_CTL:
case CDC_RX_TOP_I2S_CLK:
case CDC_RX_TOP_I2S_RESET:
case CDC_RX_TOP_I2S_MUX:
case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:
case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:
case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:
case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:
case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:
case CDC_RX_SOFTCLIP_CRC:
case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:
case CDC_RX_INP_MUX_RX_INT0_CFG0:
case CDC_RX_INP_MUX_RX_INT0_CFG1:
case CDC_RX_INP_MUX_RX_INT1_CFG0:
case CDC_RX_INP_MUX_RX_INT1_CFG1:
case CDC_RX_INP_MUX_RX_INT2_CFG0:
case CDC_RX_INP_MUX_RX_INT2_CFG1:
case CDC_RX_INP_MUX_RX_MIX_CFG4:
case CDC_RX_INP_MUX_RX_MIX_CFG5:
case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:
case CDC_RX_CLSH_CRC:
case CDC_RX_CLSH_DLY_CTRL:
case CDC_RX_CLSH_DECAY_CTRL:
case CDC_RX_CLSH_HPH_V_PA:
case CDC_RX_CLSH_EAR_V_PA:
case CDC_RX_CLSH_HPH_V_HD:
case CDC_RX_CLSH_EAR_V_HD:
case CDC_RX_CLSH_K1_MSB:
case CDC_RX_CLSH_K1_LSB:
case CDC_RX_CLSH_K2_MSB:
case CDC_RX_CLSH_K2_LSB:
case CDC_RX_CLSH_IDLE_CTRL:
case CDC_RX_CLSH_IDLE_HPH:
case CDC_RX_CLSH_IDLE_EAR:
case CDC_RX_CLSH_TEST0:
case CDC_RX_CLSH_TEST1:
case CDC_RX_CLSH_OVR_VREF:
case CDC_RX_CLSH_CLSG_CTL:
case CDC_RX_CLSH_CLSG_CFG1:
case CDC_RX_CLSH_CLSG_CFG2:
case CDC_RX_BCL_VBAT_PATH_CTL:
case CDC_RX_BCL_VBAT_CFG:
case CDC_RX_BCL_VBAT_ADC_CAL1:
case CDC_RX_BCL_VBAT_ADC_CAL2:
case CDC_RX_BCL_VBAT_ADC_CAL3:
case CDC_RX_BCL_VBAT_PK_EST1:
case CDC_RX_BCL_VBAT_PK_EST2:
case CDC_RX_BCL_VBAT_PK_EST3:
case CDC_RX_BCL_VBAT_RF_PROC1:
case CDC_RX_BCL_VBAT_RF_PROC2:
case CDC_RX_BCL_VBAT_TAC1:
case CDC_RX_BCL_VBAT_TAC2:
case CDC_RX_BCL_VBAT_TAC3:
case CDC_RX_BCL_VBAT_TAC4:
case CDC_RX_BCL_VBAT_GAIN_UPD1:
case CDC_RX_BCL_VBAT_GAIN_UPD2:
case CDC_RX_BCL_VBAT_GAIN_UPD3:
case CDC_RX_BCL_VBAT_GAIN_UPD4:
case CDC_RX_BCL_VBAT_GAIN_UPD5:
case CDC_RX_BCL_VBAT_DEBUG1:
case CDC_RX_BCL_VBAT_BAN:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:
case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:
case CDC_RX_BCL_VBAT_ATTN1:
case CDC_RX_BCL_VBAT_ATTN2:
case CDC_RX_BCL_VBAT_ATTN3:
case CDC_RX_BCL_VBAT_DECODE_CTL1:
case CDC_RX_BCL_VBAT_DECODE_CTL2:
case CDC_RX_BCL_VBAT_DECODE_CFG1:
case CDC_RX_BCL_VBAT_DECODE_CFG2:
case CDC_RX_BCL_VBAT_DECODE_CFG3:
case CDC_RX_BCL_VBAT_DECODE_CFG4:
case CDC_RX_INTR_CTRL_CFG:
case CDC_RX_INTR_CTRL_PIN1_MASK0:
case CDC_RX_INTR_CTRL_PIN2_MASK0:
case CDC_RX_INTR_CTRL_LEVEL0:
case CDC_RX_INTR_CTRL_BYPASS0:
case CDC_RX_INTR_CTRL_SET0:
case CDC_RX_RX0_RX_PATH_CTL:
case CDC_RX_RX0_RX_PATH_CFG0:
case CDC_RX_RX0_RX_PATH_CFG1:
case CDC_RX_RX0_RX_PATH_CFG2:
case CDC_RX_RX0_RX_PATH_CFG3:
case CDC_RX_RX0_RX_VOL_CTL:
case CDC_RX_RX0_RX_PATH_MIX_CTL:
case CDC_RX_RX0_RX_PATH_MIX_CFG:
case CDC_RX_RX0_RX_VOL_MIX_CTL:
case CDC_RX_RX0_RX_PATH_SEC1:
case CDC_RX_RX0_RX_PATH_SEC2:
case CDC_RX_RX0_RX_PATH_SEC3:
case CDC_RX_RX0_RX_PATH_SEC4:
case CDC_RX_RX0_RX_PATH_SEC7:
case CDC_RX_RX0_RX_PATH_MIX_SEC0:
case CDC_RX_RX0_RX_PATH_MIX_SEC1:
case CDC_RX_RX0_RX_PATH_DSM_CTL:
case CDC_RX_RX0_RX_PATH_DSM_DATA1:
case CDC_RX_RX0_RX_PATH_DSM_DATA2:
case CDC_RX_RX0_RX_PATH_DSM_DATA3:
case CDC_RX_RX0_RX_PATH_DSM_DATA4:
case CDC_RX_RX0_RX_PATH_DSM_DATA5:
case CDC_RX_RX0_RX_PATH_DSM_DATA6:
case CDC_RX_RX1_RX_PATH_CTL:
case CDC_RX_RX1_RX_PATH_CFG0:
case CDC_RX_RX1_RX_PATH_CFG1:
case CDC_RX_RX1_RX_PATH_CFG2:
case CDC_RX_RX1_RX_PATH_CFG3:
case CDC_RX_RX1_RX_VOL_CTL:
case CDC_RX_RX1_RX_PATH_MIX_CTL:
case CDC_RX_RX1_RX_PATH_MIX_CFG:
case CDC_RX_RX1_RX_VOL_MIX_CTL:
case CDC_RX_RX1_RX_PATH_SEC1:
case CDC_RX_RX1_RX_PATH_SEC2:
case CDC_RX_RX1_RX_PATH_SEC3:
case CDC_RX_RX1_RX_PATH_SEC4:
case CDC_RX_RX1_RX_PATH_SEC7:
case CDC_RX_RX1_RX_PATH_MIX_SEC0:
case CDC_RX_RX1_RX_PATH_MIX_SEC1:
case CDC_RX_RX1_RX_PATH_DSM_CTL:
case CDC_RX_RX1_RX_PATH_DSM_DATA1:
case CDC_RX_RX1_RX_PATH_DSM_DATA2:
case CDC_RX_RX1_RX_PATH_DSM_DATA3:
case CDC_RX_RX1_RX_PATH_DSM_DATA4:
case CDC_RX_RX1_RX_PATH_DSM_DATA5:
case CDC_RX_RX1_RX_PATH_DSM_DATA6:
case CDC_RX_RX2_RX_PATH_CTL:
case CDC_RX_RX2_RX_PATH_CFG0:
case CDC_RX_RX2_RX_PATH_CFG1:
case CDC_RX_RX2_RX_PATH_CFG2:
case CDC_RX_RX2_RX_PATH_CFG3:
case CDC_RX_RX2_RX_VOL_CTL:
case CDC_RX_RX2_RX_PATH_MIX_CTL:
case CDC_RX_RX2_RX_PATH_MIX_CFG:
case CDC_RX_RX2_RX_VOL_MIX_CTL:
case CDC_RX_RX2_RX_PATH_SEC0:
case CDC_RX_RX2_RX_PATH_SEC1:
case CDC_RX_RX2_RX_PATH_SEC2:
case CDC_RX_RX2_RX_PATH_SEC3:
case CDC_RX_RX2_RX_PATH_SEC4:
case CDC_RX_RX2_RX_PATH_SEC5:
case CDC_RX_RX2_RX_PATH_SEC6:
case CDC_RX_RX2_RX_PATH_SEC7:
case CDC_RX_RX2_RX_PATH_MIX_SEC0:
case CDC_RX_RX2_RX_PATH_MIX_SEC1:
case CDC_RX_RX2_RX_PATH_DSM_CTL:
case CDC_RX_IDLE_DETECT_PATH_CTL:
case CDC_RX_IDLE_DETECT_CFG0:
case CDC_RX_IDLE_DETECT_CFG1:
case CDC_RX_IDLE_DETECT_CFG2:
case CDC_RX_IDLE_DETECT_CFG3:
case CDC_RX_COMPANDER0_CTL0:
case CDC_RX_COMPANDER0_CTL1:
case CDC_RX_COMPANDER0_CTL2:
case CDC_RX_COMPANDER0_CTL3:
case CDC_RX_COMPANDER0_CTL4:
case CDC_RX_COMPANDER0_CTL5:
case CDC_RX_COMPANDER0_CTL7:
case CDC_RX_COMPANDER1_CTL0:
case CDC_RX_COMPANDER1_CTL1:
case CDC_RX_COMPANDER1_CTL2:
case CDC_RX_COMPANDER1_CTL3:
case CDC_RX_COMPANDER1_CTL4:
case CDC_RX_COMPANDER1_CTL5:
case CDC_RX_COMPANDER1_CTL7:
case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:
case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:
case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:
case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:
case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:
case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:
case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:
case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:
case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:
case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:
case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:
case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:
case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:
case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:
case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:
case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:
case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:
case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:
case CDC_RX_EC_ASRC0_CLK_RST_CTL:
case CDC_RX_EC_ASRC0_CTL0:
case CDC_RX_EC_ASRC0_CTL1:
case CDC_RX_EC_ASRC0_FIFO_CTL:
case CDC_RX_EC_ASRC1_CLK_RST_CTL:
case CDC_RX_EC_ASRC1_CTL0:
case CDC_RX_EC_ASRC1_CTL1:
case CDC_RX_EC_ASRC1_FIFO_CTL:
case CDC_RX_EC_ASRC2_CLK_RST_CTL:
case CDC_RX_EC_ASRC2_CTL0:
case CDC_RX_EC_ASRC2_CTL1:
case CDC_RX_EC_ASRC2_FIFO_CTL:
case CDC_RX_DSD0_PATH_CTL:
case CDC_RX_DSD0_CFG0:
case CDC_RX_DSD0_CFG1:
case CDC_RX_DSD0_CFG2:
case CDC_RX_DSD1_PATH_CTL:
case CDC_RX_DSD1_CFG0:
case CDC_RX_DSD1_CFG1:
case CDC_RX_DSD1_CFG2:
return true;
}
return false;
}
static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
{
bool ret;
ret = rx_is_rw_register(dev, reg);
if (!ret)
return rx_is_wronly_register(dev, reg);
return ret;
}
static bool rx_is_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CDC_RX_TOP_HPHL_COMP_RD_LSB:
case CDC_RX_TOP_HPHL_COMP_RD_MSB:
case CDC_RX_TOP_HPHR_COMP_RD_LSB:
case CDC_RX_TOP_HPHR_COMP_RD_MSB:
case CDC_RX_TOP_DSD0_DEBUG_CFG2:
case CDC_RX_TOP_DSD1_DEBUG_CFG2:
case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
case CDC_RX_BCL_VBAT_DECODE_ST:
case CDC_RX_INTR_CTRL_PIN1_STATUS0:
case CDC_RX_INTR_CTRL_PIN2_STATUS0:
case CDC_RX_COMPANDER0_CTL6:
case CDC_RX_COMPANDER1_CTL6:
case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
case CDC_RX_EC_ASRC0_STATUS_FIFO:
case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
case CDC_RX_EC_ASRC1_STATUS_FIFO:
case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
case CDC_RX_EC_ASRC2_STATUS_FIFO:
return true;
}
return rx_is_rw_register(dev, reg);
}
static const struct regmap_config rx_regmap_config = {
.name = "rx_macro",
.reg_bits = 16,
.val_bits = 32, /* 8 but with 32 bit read/write */
.reg_stride = 4,
.cache_type = REGCACHE_FLAT,
.reg_defaults = rx_defaults,
.num_reg_defaults = ARRAY_SIZE(rx_defaults),
.max_register = RX_MAX_OFFSET,
.writeable_reg = rx_is_writeable_register,
.volatile_reg = rx_is_volatile_register,
.readable_reg = rx_is_readable_register,
};
static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned short look_ahead_dly_reg;
unsigned int val;
val = ucontrol->value.enumerated.item[0];
if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
/* Set Look Ahead Delay */
if (val)
snd_soc_component_update_bits(component, look_ahead_dly_reg,
CDC_RX_DLY_ZN_EN_MASK,
CDC_RX_DLY_ZN_ENABLE);
else
snd_soc_component_update_bits(component, look_ahead_dly_reg,
CDC_RX_DLY_ZN_EN_MASK, 0);
/* Set DEM INP Select */
return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
}
static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum,
snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
int rate_reg_val, u32 sample_rate)
{
u8 int_1_mix1_inp;
u32 j, port;
u16 int_mux_cfg0, int_mux_cfg1;
u16 int_fs_reg;
u8 inp0_sel, inp1_sel, inp2_sel;
struct snd_soc_component *component = dai->component;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
int_1_mix1_inp = port;
int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0;
/*
* Loop through all interpolator MUX inputs and find out
* to which interpolator input, the rx port
* is connected
*/
for (j = 0; j < INTERP_MAX; j++) {
int_mux_cfg1 = int_mux_cfg0 + 4;
inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
(inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
(inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
/* sample_rate is in Hz */
snd_soc_component_update_bits(component, int_fs_reg,
CDC_RX_PATH_PCM_RATE_MASK,
rate_reg_val);
}
int_mux_cfg0 += 8;
}
}
return 0;
}
static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
int rate_reg_val, u32 sample_rate)
{
u8 int_2_inp;
u32 j, port;
u16 int_mux_cfg1, int_fs_reg;
u8 int_mux_cfg1_val;
struct snd_soc_component *component = dai->component;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
int_2_inp = port;
int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1;
for (j = 0; j < INTERP_MAX; j++) {
int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
CDC_RX_INTX_2_SEL_MASK);
if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
snd_soc_component_update_bits(component, int_fs_reg,
CDC_RX_RXn_MIX_PCM_RATE_MASK,
rate_reg_val);
}
int_mux_cfg1 += 8;
}
}
return 0;
}
static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,
u32 sample_rate)
{
int rate_val = 0;
int i, ret;
for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)
if (sample_rate == sr_val_tbl[i].sample_rate)
rate_val = sr_val_tbl[i].rate_val;
ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate);
if (ret)
return ret;
ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate);
return ret;
}
static int rx_macro_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
int ret;
switch (substream->stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
ret = rx_macro_set_interpolator_rate(dai, params_rate(params));
if (ret) {
dev_err(component->dev, "%s: cannot set sample rate: %u\n",
__func__, params_rate(params));
return ret;
}
rx->bit_width[dai->id] = params_width(params);
break;
default:
break;
}
return 0;
}
static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
unsigned int *tx_num, unsigned int *tx_slot,
unsigned int *rx_num, unsigned int *rx_slot)
{
struct snd_soc_component *component = dai->component;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
u16 val, mask = 0, cnt = 0, temp;
switch (dai->id) {
case RX_MACRO_AIF1_PB:
case RX_MACRO_AIF2_PB:
case RX_MACRO_AIF3_PB:
case RX_MACRO_AIF4_PB:
for_each_set_bit(temp, &rx->active_ch_mask[dai->id],
RX_MACRO_PORTS_MAX) {
mask |= (1 << temp);
if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT)
break;
}
/*
* CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3
* CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3
* CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1
* CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1
* AIFn can pair to any CDC_DMA_RX_n port.
* In general, below convention is used::
* CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/
* CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4)
*/
if (mask & 0x0C)
mask = mask >> 2;
if ((mask & 0x10) || (mask & 0x20))
mask = 0x1;
*rx_slot = mask;
*rx_num = rx->active_ch_cnt[dai->id];
break;
case RX_MACRO_AIF_ECHO:
val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4);
if (val & RX_MACRO_EC_MIX_TX0_MASK) {
mask |= 0x1;
cnt++;
}
if (val & RX_MACRO_EC_MIX_TX1_MASK) {
mask |= 0x2;
cnt++;
}
val = snd_soc_component_read(component,
CDC_RX_INP_MUX_RX_MIX_CFG5);
if (val & RX_MACRO_EC_MIX_TX2_MASK) {
mask |= 0x4;
cnt++;
}
*tx_slot = mask;
*tx_num = cnt;
break;
default:
dev_err(component->dev, "%s: Invalid AIF\n", __func__);
break;
}
return 0;
}
static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
uint16_t j, reg, mix_reg, dsm_reg;
u16 int_mux_cfg0, int_mux_cfg1;
u8 int_mux_cfg0_val, int_mux_cfg1_val;
switch (dai->id) {
case RX_MACRO_AIF1_PB:
case RX_MACRO_AIF2_PB:
case RX_MACRO_AIF3_PB:
case RX_MACRO_AIF4_PB:
for (j = 0; j < INTERP_MAX; j++) {
reg = CDC_RX_RXn_RX_PATH_CTL(j);
mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
if (mute) {
snd_soc_component_update_bits(component, reg,
CDC_RX_PATH_PGA_MUTE_MASK,
CDC_RX_PATH_PGA_MUTE_ENABLE);
snd_soc_component_update_bits(component, mix_reg,
CDC_RX_PATH_PGA_MUTE_MASK,
CDC_RX_PATH_PGA_MUTE_ENABLE);
} else {
snd_soc_component_update_bits(component, reg,
CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
snd_soc_component_update_bits(component, mix_reg,
CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
}
if (j == INTERP_AUX)
dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
int_mux_cfg1 = int_mux_cfg0 + 4;
int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
if (snd_soc_component_read(component, dsm_reg) & 0x01) {
if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
snd_soc_component_update_bits(component, reg, 0x20, 0x20);
if (int_mux_cfg1_val & 0x0F) {
snd_soc_component_update_bits(component, reg, 0x20, 0x20);
snd_soc_component_update_bits(component, mix_reg, 0x20,
0x20);
}
}
}
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dai_ops rx_macro_dai_ops = {
.hw_params = rx_macro_hw_params,
.get_channel_map = rx_macro_get_channel_map,
.mute_stream = rx_macro_digital_mute,
};
static struct snd_soc_dai_driver rx_macro_dai[] = {
{
.name = "rx_macro_rx1",
.id = RX_MACRO_AIF1_PB,
.playback = {
.stream_name = "RX_MACRO_AIF1 Playback",
.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
.formats = RX_MACRO_FORMATS,
.rate_max = 384000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &rx_macro_dai_ops,
},
{
.name = "rx_macro_rx2",
.id = RX_MACRO_AIF2_PB,
.playback = {
.stream_name = "RX_MACRO_AIF2 Playback",
.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
.formats = RX_MACRO_FORMATS,
.rate_max = 384000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &rx_macro_dai_ops,
},
{
.name = "rx_macro_rx3",
.id = RX_MACRO_AIF3_PB,
.playback = {
.stream_name = "RX_MACRO_AIF3 Playback",
.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
.formats = RX_MACRO_FORMATS,
.rate_max = 384000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &rx_macro_dai_ops,
},
{
.name = "rx_macro_rx4",
.id = RX_MACRO_AIF4_PB,
.playback = {
.stream_name = "RX_MACRO_AIF4 Playback",
.rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
.formats = RX_MACRO_FORMATS,
.rate_max = 384000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 2,
},
.ops = &rx_macro_dai_ops,
},
{
.name = "rx_macro_echo",
.id = RX_MACRO_AIF_ECHO,
.capture = {
.stream_name = "RX_AIF_ECHO Capture",
.rates = RX_MACRO_ECHO_RATES,
.formats = RX_MACRO_ECHO_FORMATS,
.rate_max = 48000,
.rate_min = 8000,
.channels_min = 1,
.channels_max = 3,
},
.ops = &rx_macro_dai_ops,
},
};
static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
{
struct regmap *regmap = rx->regmap;
if (mclk_enable) {
if (rx->rx_mclk_users == 0) {
regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
CDC_RX_CLK_MCLK_EN_MASK |
CDC_RX_CLK_MCLK2_EN_MASK,
CDC_RX_CLK_MCLK_ENABLE |
CDC_RX_CLK_MCLK2_ENABLE);
regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00);
regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_RX_FS_MCLK_CNT_EN_MASK,
CDC_RX_FS_MCLK_CNT_ENABLE);
regcache_mark_dirty(regmap);
regcache_sync(regmap);
}
rx->rx_mclk_users++;
} else {
if (rx->rx_mclk_users <= 0) {
dev_err(rx->dev, "%s: clock already disabled\n", __func__);
rx->rx_mclk_users = 0;
return;
}
rx->rx_mclk_users--;
if (rx->rx_mclk_users == 0) {
regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0);
regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
CDC_RX_FS_MCLK_CNT_CLR_MASK,
CDC_RX_FS_MCLK_CNT_CLR);
regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
CDC_RX_CLK_MCLK_EN_MASK |
CDC_RX_CLK_MCLK2_EN_MASK, 0x0);
}
}
}
static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rx_macro_mclk_enable(rx, true);
break;
case SND_SOC_DAPM_POST_PMD:
rx_macro_mclk_enable(rx, false);
break;
default:
dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event);
ret = -EINVAL;
}
return ret;
}
static bool rx_macro_adie_lb(struct snd_soc_component *component,
int interp_idx)
{
u16 int_mux_cfg0, int_mux_cfg1;
u8 int_n_inp0, int_n_inp1, int_n_inp2;
int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
int_mux_cfg1 = int_mux_cfg0 + 4;
int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
int_n_inp0 == INTn_1_INP_SEL_DEC1 ||
int_n_inp0 == INTn_1_INP_SEL_IIR0 ||
int_n_inp0 == INTn_1_INP_SEL_IIR1)
return true;
if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
int_n_inp1 == INTn_1_INP_SEL_DEC1 ||
int_n_inp1 == INTn_1_INP_SEL_IIR0 ||
int_n_inp1 == INTn_1_INP_SEL_IIR1)
return true;
if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
int_n_inp2 == INTn_1_INP_SEL_DEC1 ||
int_n_inp2 == INTn_1_INP_SEL_IIR0 ||
int_n_inp2 == INTn_1_INP_SEL_IIR1)
return true;
return false;
}
static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
int event, int interp_idx);
static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 gain_reg, reg;
reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rx_macro_enable_interp_clk(component, event, w->shift);
if (rx_macro_adie_lb(component, w->shift))
snd_soc_component_update_bits(component, reg,
CDC_RX_PATH_CLK_EN_MASK,
CDC_RX_PATH_CLK_ENABLE);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, gain_reg,
snd_soc_component_read(component, gain_reg));
break;
case SND_SOC_DAPM_POST_PMD:
rx_macro_enable_interp_clk(component, event, w->shift);
break;
}
return 0;
}
static int rx_macro_config_compander(struct snd_soc_component *component,
struct rx_macro *rx,
int comp, int event)
{
u8 pcm_rate, val;
/* AUX does not have compander */
if (comp == INTERP_AUX)
return 0;
pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
if (pcm_rate < 0x06)
val = 0x03;
else if (pcm_rate < 0x08)
val = 0x01;
else if (pcm_rate < 0x0B)
val = 0x02;
else
val = 0x00;
if (SND_SOC_DAPM_EVENT_ON(event))
snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
CDC_RX_DC_COEFF_SEL_MASK, val);
if (SND_SOC_DAPM_EVENT_OFF(event))
snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
CDC_RX_DC_COEFF_SEL_MASK, 0x3);
if (!rx->comp_enabled[comp])
return 0;
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Enable Compander Clock */
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1);
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
CDC_RX_RXn_COMP_EN_MASK, 0x1);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_HALT_MASK, 0x1);
snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
CDC_RX_RXn_COMP_EN_MASK, 0x0);
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_HALT_MASK, 0x0);
}
return 0;
}
static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
struct rx_macro *rx,
int comp, int event)
{
u16 comp_coeff_lsb_reg, comp_coeff_msb_reg;
int i;
int hph_pwr_mode;
/* AUX does not have compander */
if (comp == INTERP_AUX)
return 0;
if (!rx->comp_enabled[comp])
return 0;
if (comp == INTERP_HPHL) {
comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB;
comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB;
} else if (comp == INTERP_HPHR) {
comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB;
comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB;
} else {
/* compander coefficients are loaded only for hph path */
return 0;
}
hph_pwr_mode = rx->hph_pwr_mode;
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Load Compander Coeff */
for (i = 0; i < COMP_MAX_COEFF; i++) {
snd_soc_component_write(component, comp_coeff_lsb_reg,
comp_coeff_table[hph_pwr_mode][i].lsb);
snd_soc_component_write(component, comp_coeff_msb_reg,
comp_coeff_table[hph_pwr_mode][i].msb);
}
}
return 0;
}
static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
struct rx_macro *rx, bool enable)
{
if (enable) {
if (rx->softclip_clk_users == 0)
snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
CDC_RX_SOFTCLIP_CLK_EN_MASK, 1);
rx->softclip_clk_users++;
} else {
rx->softclip_clk_users--;
if (rx->softclip_clk_users == 0)
snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
CDC_RX_SOFTCLIP_CLK_EN_MASK, 0);
}
}
static int rx_macro_config_softclip(struct snd_soc_component *component,
struct rx_macro *rx, int event)
{
if (!rx->is_softclip_on)
return 0;
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Enable Softclip clock */
rx_macro_enable_softclip_clk(component, rx, true);
/* Enable Softclip control */
snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
CDC_RX_SOFTCLIP_EN_MASK, 0x01);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
CDC_RX_SOFTCLIP_EN_MASK, 0x0);
rx_macro_enable_softclip_clk(component, rx, false);
}
return 0;
}
static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
struct rx_macro *rx, int event)
{
if (SND_SOC_DAPM_EVENT_ON(event)) {
/* Update Aux HPF control */
if (!rx->is_aux_hpf_on)
snd_soc_component_update_bits(component,
CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
/* Reset to default (HPF=ON) */
snd_soc_component_update_bits(component,
CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04);
}
return 0;
}
static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable)
{
if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0))
snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC,
CDC_RX_CLSH_CLK_EN_MASK, enable);
if (rx->clsh_users < 0)
rx->clsh_users = 0;
}
static int rx_macro_config_classh(struct snd_soc_component *component,
struct rx_macro *rx,
int interp_n, int event)
{
if (SND_SOC_DAPM_EVENT_OFF(event)) {
rx_macro_enable_clsh_block(rx, false);
return 0;
}
if (!SND_SOC_DAPM_EVENT_ON(event))
return 0;
rx_macro_enable_clsh_block(rx, true);
if (interp_n == INTERP_HPHL ||
interp_n == INTERP_HPHR) {
/*
* These K1 values depend on the Headphone Impedance
* For now it is assumed to be 16 ohm
*/
snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0);
snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB,
CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0);
}
switch (interp_n) {
case INTERP_HPHL:
if (rx->is_ear_mode_on)
snd_soc_component_update_bits(component,
CDC_RX_CLSH_HPH_V_PA,
CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
else
snd_soc_component_update_bits(component,
CDC_RX_CLSH_HPH_V_PA,
CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
snd_soc_component_update_bits(component,
CDC_RX_CLSH_DECAY_CTRL,
CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
snd_soc_component_write_field(component,
CDC_RX_RX0_RX_PATH_CFG0,
CDC_RX_RXn_CLSH_EN_MASK, 0x1);
break;
case INTERP_HPHR:
if (rx->is_ear_mode_on)
snd_soc_component_update_bits(component,
CDC_RX_CLSH_HPH_V_PA,
CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
else
snd_soc_component_update_bits(component,
CDC_RX_CLSH_HPH_V_PA,
CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
snd_soc_component_update_bits(component,
CDC_RX_CLSH_DECAY_CTRL,
CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
snd_soc_component_write_field(component,
CDC_RX_RX1_RX_PATH_CFG0,
CDC_RX_RXn_CLSH_EN_MASK, 0x1);
break;
case INTERP_AUX:
snd_soc_component_update_bits(component,
CDC_RX_RX2_RX_PATH_CFG0,
CDC_RX_RX2_DLY_Z_EN_MASK, 1);
snd_soc_component_write_field(component,
CDC_RX_RX2_RX_PATH_CFG0,
CDC_RX_RX2_CLSH_EN_MASK, 1);
break;
}
return 0;
}
static void rx_macro_hd2_control(struct snd_soc_component *component,
u16 interp_idx, int event)
{
u16 hd2_scale_reg, hd2_enable_reg;
switch (interp_idx) {
case INTERP_HPHL:
hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
break;
case INTERP_HPHR:
hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
break;
}
if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(component, hd2_scale_reg,
CDC_RX_RXn_HD2_ALPHA_MASK, 0x14);
snd_soc_component_write_field(component, hd2_enable_reg,
CDC_RX_RXn_HD2_EN_MASK, 1);
}
if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write_field(component, hd2_enable_reg,
CDC_RX_RXn_HD2_EN_MASK, 0);
snd_soc_component_update_bits(component, hd2_scale_reg,
CDC_RX_RXn_HD2_ALPHA_MASK, 0x0);
}
}
static int rx_macro_get_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rx->comp_enabled[comp];
return 0;
}
static int rx_macro_set_compander(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
int value = ucontrol->value.integer.value[0];
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
rx->comp_enabled[comp] = value;
return 0;
}
static int rx_macro_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] =
rx->rx_port_value[widget->shift];
return 0;
}
static int rx_macro_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct snd_soc_dapm_update *update = NULL;
u32 rx_port_value = ucontrol->value.enumerated.item[0];
u32 aif_rst;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
aif_rst = rx->rx_port_value[widget->shift];
if (!rx_port_value) {
if (aif_rst == 0)
return 0;
if (aif_rst > RX_MACRO_AIF4_PB) {
dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
return 0;
}
}
rx->rx_port_value[widget->shift] = rx_port_value;
switch (rx_port_value) {
case 0:
if (rx->active_ch_cnt[aif_rst]) {
clear_bit(widget->shift,
&rx->active_ch_mask[aif_rst]);
rx->active_ch_cnt[aif_rst]--;
}
break;
case 1:
case 2:
case 3:
case 4:
set_bit(widget->shift,
&rx->active_ch_mask[rx_port_value]);
rx->active_ch_cnt[rx_port_value]++;
break;
default:
dev_err(component->dev,
"%s:Invalid AIF_ID for RX_MACRO MUX %d\n",
__func__, rx_port_value);
goto err;
}
snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
rx_port_value, e, update);
return 0;
err:
return -EINVAL;
}
static const struct snd_kcontrol_new rx_macro_rx0_mux =
SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum,
rx_macro_mux_get, rx_macro_mux_put);
static const struct snd_kcontrol_new rx_macro_rx1_mux =
SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum,
rx_macro_mux_get, rx_macro_mux_put);
static const struct snd_kcontrol_new rx_macro_rx2_mux =
SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum,
rx_macro_mux_get, rx_macro_mux_put);
static const struct snd_kcontrol_new rx_macro_rx3_mux =
SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum,
rx_macro_mux_get, rx_macro_mux_put);
static const struct snd_kcontrol_new rx_macro_rx4_mux =
SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum,
rx_macro_mux_get, rx_macro_mux_put);
static const struct snd_kcontrol_new rx_macro_rx5_mux =
SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum,
rx_macro_mux_get, rx_macro_mux_put);
static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rx->is_ear_mode_on;
return 0;
}
static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true);
return 0;
}
static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rx->hph_hd2_mode;
return 0;
}
static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
rx->hph_hd2_mode = ucontrol->value.integer.value[0];
return 0;
}
static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode;
return 0;
}
static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
rx->hph_pwr_mode = ucontrol->value.enumerated.item[0];
return 0;
}
static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rx->is_softclip_on;
return 0;
}
static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
rx->is_softclip_on = ucontrol->value.integer.value[0];
return 0;
}
static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rx->is_aux_hpf_on;
return 0;
}
static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
rx->is_aux_hpf_on = ucontrol->value.integer.value[0];
return 0;
}
static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
struct rx_macro *rx,
u16 interp_idx, int event)
{
u16 hph_lut_bypass_reg;
u16 hph_comp_ctrl7;
switch (interp_idx) {
case INTERP_HPHL:
hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT;
hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7;
break;
case INTERP_HPHR:
hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT;
hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7;
break;
default:
return -EINVAL;
}
if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
if (interp_idx == INTERP_HPHL) {
if (rx->is_ear_mode_on)
snd_soc_component_write_field(component,
CDC_RX_RX0_RX_PATH_CFG1,
CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
else
snd_soc_component_write_field(component,
hph_lut_bypass_reg,
CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
} else {
snd_soc_component_write_field(component, hph_lut_bypass_reg,
CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
}
if (rx->hph_pwr_mode)
snd_soc_component_write_field(component, hph_comp_ctrl7,
CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0);
}
if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write_field(component,
CDC_RX_RX0_RX_PATH_CFG1,
CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
snd_soc_component_update_bits(component, hph_lut_bypass_reg,
CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
snd_soc_component_write_field(component, hph_comp_ctrl7,
CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1);
}
return 0;
}
static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
int event, int interp_idx)
{
u16 main_reg, dsm_reg, rx_cfg2_reg;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
if (interp_idx == INTERP_AUX)
dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
if (SND_SOC_DAPM_EVENT_ON(event)) {
if (rx->main_clk_users[interp_idx] == 0) {
/* Main path PGA mute enable */
snd_soc_component_write_field(component, main_reg,
CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
snd_soc_component_write_field(component, dsm_reg,
CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1);
snd_soc_component_update_bits(component, rx_cfg2_reg,
CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03);
rx_macro_load_compander_coeff(component, rx, interp_idx, event);
if (rx->hph_hd2_mode)
rx_macro_hd2_control(component, interp_idx, event);
rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
rx_macro_config_compander(component, rx, interp_idx, event);
if (interp_idx == INTERP_AUX) {
rx_macro_config_softclip(component, rx, event);
rx_macro_config_aux_hpf(component, rx, event);
}
rx_macro_config_classh(component, rx, interp_idx, event);
}
rx->main_clk_users[interp_idx]++;
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
rx->main_clk_users[interp_idx]--;
if (rx->main_clk_users[interp_idx] <= 0) {
rx->main_clk_users[interp_idx] = 0;
/* Main path PGA mute enable */
snd_soc_component_write_field(component, main_reg,
CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
/* Clk Disable */
snd_soc_component_write_field(component, dsm_reg,
CDC_RX_RXn_DSM_CLK_EN_MASK, 0);
snd_soc_component_write_field(component, main_reg,
CDC_RX_PATH_CLK_EN_MASK, 0);
/* Reset enable and disable */
snd_soc_component_write_field(component, main_reg,
CDC_RX_PATH_RESET_EN_MASK, 1);
snd_soc_component_write_field(component, main_reg,
CDC_RX_PATH_RESET_EN_MASK, 0);
/* Reset rate to 48K*/
snd_soc_component_update_bits(component, main_reg,
CDC_RX_PATH_PCM_RATE_MASK,
0x04);
snd_soc_component_update_bits(component, rx_cfg2_reg,
CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00);
rx_macro_config_classh(component, rx, interp_idx, event);
rx_macro_config_compander(component, rx, interp_idx, event);
if (interp_idx == INTERP_AUX) {
rx_macro_config_softclip(component, rx, event);
rx_macro_config_aux_hpf(component, rx, event);
}
rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
if (rx->hph_hd2_mode)
rx_macro_hd2_control(component, interp_idx, event);
}
}
return rx->main_clk_users[interp_idx];
}
static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 gain_reg, mix_reg;
gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rx_macro_enable_interp_clk(component, event, w->shift);
break;
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, gain_reg,
snd_soc_component_read(component, gain_reg));
break;
case SND_SOC_DAPM_POST_PMD:
/* Clk Disable */
snd_soc_component_update_bits(component, mix_reg,
CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00);
rx_macro_enable_interp_clk(component, event, w->shift);
/* Reset enable and disable */
snd_soc_component_update_bits(component, mix_reg,
CDC_RX_RXn_MIX_RESET_MASK,
CDC_RX_RXn_MIX_RESET);
snd_soc_component_update_bits(component, mix_reg,
CDC_RX_RXn_MIX_RESET_MASK, 0x00);
break;
}
return 0;
}
static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rx_macro_enable_interp_clk(component, event, w->shift);
snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
CDC_RX_RXn_SIDETONE_EN_MASK, 1);
snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
CDC_RX_PATH_CLK_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
CDC_RX_RXn_SIDETONE_EN_MASK, 0);
rx_macro_enable_interp_clk(component, event, w->shift);
break;
default:
break;
}
return 0;
}
static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU: /* fall through */
case SND_SOC_DAPM_PRE_PMD:
if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
} else {
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
snd_soc_component_write(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
snd_soc_component_read(component,
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
}
break;
}
return 0;
}
static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
int iir_idx, int band_idx, int coeff_idx)
{
u32 value;
int reg, b2_reg;
/* Address does not automatically update if reading */
reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx) *
sizeof(uint32_t)) & 0x7F);
value = snd_soc_component_read(component, b2_reg);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 1) & 0x7F);
value |= (snd_soc_component_read(component, b2_reg) << 8);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 2) & 0x7F);
value |= (snd_soc_component_read(component, b2_reg) << 16);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 3) & 0x7F);
/* Mask bits top 2 bits since they are reserved */
value |= (snd_soc_component_read(component, b2_reg) << 24);
return value;
}
static void set_iir_band_coeff(struct snd_soc_component *component,
int iir_idx, int band_idx, uint32_t value)
{
int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
snd_soc_component_write(component, reg, (value & 0xFF));
snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
/* Mask top 2 bits, 7-8 are reserved */
snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
}
static int rx_macro_put_iir_band_audio_mixer(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
int iir_idx = ctl->iir_idx;
int band_idx = ctl->band_idx;
u32 coeff[BAND_MAX];
int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
/* Mask top bit it is reserved */
/* Updates addr automatically for each B2 write */
snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
sizeof(uint32_t)) & 0x7F);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
return 0;
}
static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
int iir_idx = ctl->iir_idx;
int band_idx = ctl->band_idx;
u32 coeff[BAND_MAX];
coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
return 0;
}
static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *ucontrol)
{
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ucontrol->count = params->max;
return 0;
}
static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
rx_macro_get_compander, rx_macro_set_compander),
SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
rx_macro_get_compander, rx_macro_set_compander),
SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
rx_macro_get_ear_mode, rx_macro_put_ear_mode),
SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode),
SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum,
rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode),
SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
rx_macro_soft_clip_enable_get,
rx_macro_soft_clip_enable_put),
SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
rx_macro_aux_hpf_mode_get,
rx_macro_aux_hpf_mode_put),
SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
digital_gain),
SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
0, 1, 0),
SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
1, 1, 0),
SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2, 1, 0),
SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
3, 1, 0),
SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
4, 1, 0),
SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
0, 1, 0),
SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
1, 1, 0),
SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2, 1, 0),
SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
3, 1, 0),
SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
4, 1, 0),
RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
};
static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
u16 val, ec_hq_reg;
int ec_tx = -1;
val = snd_soc_component_read(component,
CDC_RX_INP_MUX_RX_MIX_CFG4);
if (!(strcmp(w->name, "RX MIX TX0 MUX")))
ec_tx = ((val & 0xf0) >> 0x4) - 1;
else if (!(strcmp(w->name, "RX MIX TX1 MUX")))
ec_tx = (val & 0x0f) - 1;
val = snd_soc_component_read(component,
CDC_RX_INP_MUX_RX_MIX_CFG5);
if (!(strcmp(w->name, "RX MIX TX2 MUX")))
ec_tx = (val & 0x0f) - 1;
if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) {
dev_err(component->dev, "%s: EC mix control not set correctly\n",
__func__);
return -EINVAL;
}
ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL +
0x40 * ec_tx;
snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01);
ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 +
0x40 * ec_tx;
/* default set to 48k */
snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08);
return 0;
}
static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
&rx_macro_rx0_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
&rx_macro_rx1_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
&rx_macro_rx2_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
&rx_macro_rx3_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
&rx_macro_rx4_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
&rx_macro_rx5_mux),
SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
RX_MACRO_EC0_MUX, 0,
&rx_mix_tx0_mux, rx_macro_enable_echo,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
RX_MACRO_EC1_MUX, 0,
&rx_mix_tx1_mux, rx_macro_enable_echo,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
RX_MACRO_EC2_MUX, 0,
&rx_mix_tx2_mux, rx_macro_enable_echo,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
4, 0, NULL, 0, rx_macro_set_iir_gain,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
4, 0, NULL, 0, rx_macro_set_iir_gain,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4, 0, NULL, 0),
SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4, 0, NULL, 0),
SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int0_dem_inp_mux),
SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
&rx_int1_dem_inp_mux),
SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
&rx_int0_2_mux, rx_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
&rx_int1_2_mux, rx_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
&rx_int2_2_mux, rx_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
&rx_int0_1_interp_mux, rx_macro_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
&rx_int1_1_interp_mux, rx_macro_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
&rx_int2_1_interp_mux, rx_macro_enable_main_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int0_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int1_2_interp_mux),
SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
&rx_int2_2_interp_mux),
SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPHL_OUT"),
SND_SOC_DAPM_OUTPUT("HPHR_OUT"),
SND_SOC_DAPM_OUTPUT("AUX_OUT"),
SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"),
SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"),
SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"),
SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"),
SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route rx_audio_map[] = {
{"RX AIF1 PB", NULL, "RX_MCLK"},
{"RX AIF2 PB", NULL, "RX_MCLK"},
{"RX AIF3 PB", NULL, "RX_MCLK"},
{"RX AIF4 PB", NULL, "RX_MCLK"},
{"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
{"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
{"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
{"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
{"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
{"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
{"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
{"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
{"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
{"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
{"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
{"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
{"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
{"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
{"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
{"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
{"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
{"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
{"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
{"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
{"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
{"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
{"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
{"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
{"RX_RX0", NULL, "RX_MACRO RX0 MUX"},
{"RX_RX1", NULL, "RX_MACRO RX1 MUX"},
{"RX_RX2", NULL, "RX_MACRO RX2 MUX"},
{"RX_RX3", NULL, "RX_MACRO RX3 MUX"},
{"RX_RX4", NULL, "RX_MACRO RX4 MUX"},
{"RX_RX5", NULL, "RX_MACRO RX5 MUX"},
{"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
{"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
{"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
{"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
{"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
{"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
{"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
{"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
{"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
{"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
{"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
{"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
{"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
{"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
{"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
{"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
{"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
{"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
{"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
{"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
{"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
{"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
{"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
{"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
{"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
{"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
{"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
{"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
{"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
{"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
{"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
{"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
{"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
{"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
{"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
{"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
{"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
{"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
{"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
{"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
{"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
{"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
{"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
{"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
{"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
{"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
{"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
{"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
{"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
{"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
{"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
{"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
{"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
{"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
{"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
{"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
{"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
{"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
{"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
{"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
{"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
{"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
{"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
{"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
{"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
{"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
{"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
{"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
{"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
{"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
{"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
{"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
{"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
{"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
{"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
{"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
{"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
{"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
{"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
{"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
{"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
{"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
{"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
{"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
{"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
{"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
{"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
{"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
{"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
{"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
{"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
{"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
{"RX AIF_ECHO", NULL, "RX_MCLK"},
/* Mixing path INT0 */
{"RX INT0_2 MUX", "RX0", "RX_RX0"},
{"RX INT0_2 MUX", "RX1", "RX_RX1"},
{"RX INT0_2 MUX", "RX2", "RX_RX2"},
{"RX INT0_2 MUX", "RX3", "RX_RX3"},
{"RX INT0_2 MUX", "RX4", "RX_RX4"},
{"RX INT0_2 MUX", "RX5", "RX_RX5"},
{"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
{"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
/* Mixing path INT1 */
{"RX INT1_2 MUX", "RX0", "RX_RX0"},
{"RX INT1_2 MUX", "RX1", "RX_RX1"},
{"RX INT1_2 MUX", "RX2", "RX_RX2"},
{"RX INT1_2 MUX", "RX3", "RX_RX3"},
{"RX INT1_2 MUX", "RX4", "RX_RX4"},
{"RX INT1_2 MUX", "RX5", "RX_RX5"},
{"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
{"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
/* Mixing path INT2 */
{"RX INT2_2 MUX", "RX0", "RX_RX0"},
{"RX INT2_2 MUX", "RX1", "RX_RX1"},
{"RX INT2_2 MUX", "RX2", "RX_RX2"},
{"RX INT2_2 MUX", "RX3", "RX_RX3"},
{"RX INT2_2 MUX", "RX4", "RX_RX4"},
{"RX INT2_2 MUX", "RX5", "RX_RX5"},
{"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
{"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
{"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
{"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
{"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
{"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
{"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
{"HPHL_OUT", NULL, "RX_MCLK"},
{"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
{"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
{"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
{"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
{"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
{"HPHR_OUT", NULL, "RX_MCLK"},
{"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
{"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
{"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
{"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
{"AUX_OUT", NULL, "RX INT2 MIX2"},
{"AUX_OUT", NULL, "RX_MCLK"},
{"IIR0", NULL, "RX_MCLK"},
{"IIR0", NULL, "IIR0 INP0 MUX"},
{"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR0 INP0 MUX", "RX0", "RX_RX0"},
{"IIR0 INP0 MUX", "RX1", "RX_RX1"},
{"IIR0 INP0 MUX", "RX2", "RX_RX2"},
{"IIR0 INP0 MUX", "RX3", "RX_RX3"},
{"IIR0 INP0 MUX", "RX4", "RX_RX4"},
{"IIR0 INP0 MUX", "RX5", "RX_RX5"},
{"IIR0", NULL, "IIR0 INP1 MUX"},
{"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR0 INP1 MUX", "RX0", "RX_RX0"},
{"IIR0 INP1 MUX", "RX1", "RX_RX1"},
{"IIR0 INP1 MUX", "RX2", "RX_RX2"},
{"IIR0 INP1 MUX", "RX3", "RX_RX3"},
{"IIR0 INP1 MUX", "RX4", "RX_RX4"},
{"IIR0 INP1 MUX", "RX5", "RX_RX5"},
{"IIR0", NULL, "IIR0 INP2 MUX"},
{"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR0 INP2 MUX", "RX0", "RX_RX0"},
{"IIR0 INP2 MUX", "RX1", "RX_RX1"},
{"IIR0 INP2 MUX", "RX2", "RX_RX2"},
{"IIR0 INP2 MUX", "RX3", "RX_RX3"},
{"IIR0 INP2 MUX", "RX4", "RX_RX4"},
{"IIR0 INP2 MUX", "RX5", "RX_RX5"},
{"IIR0", NULL, "IIR0 INP3 MUX"},
{"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR0 INP3 MUX", "RX0", "RX_RX0"},
{"IIR0 INP3 MUX", "RX1", "RX_RX1"},
{"IIR0 INP3 MUX", "RX2", "RX_RX2"},
{"IIR0 INP3 MUX", "RX3", "RX_RX3"},
{"IIR0 INP3 MUX", "RX4", "RX_RX4"},
{"IIR0 INP3 MUX", "RX5", "RX_RX5"},
{"IIR1", NULL, "RX_MCLK"},
{"IIR1", NULL, "IIR1 INP0 MUX"},
{"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR1 INP0 MUX", "RX0", "RX_RX0"},
{"IIR1 INP0 MUX", "RX1", "RX_RX1"},
{"IIR1 INP0 MUX", "RX2", "RX_RX2"},
{"IIR1 INP0 MUX", "RX3", "RX_RX3"},
{"IIR1 INP0 MUX", "RX4", "RX_RX4"},
{"IIR1 INP0 MUX", "RX5", "RX_RX5"},
{"IIR1", NULL, "IIR1 INP1 MUX"},
{"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR1 INP1 MUX", "RX0", "RX_RX0"},
{"IIR1 INP1 MUX", "RX1", "RX_RX1"},
{"IIR1 INP1 MUX", "RX2", "RX_RX2"},
{"IIR1 INP1 MUX", "RX3", "RX_RX3"},
{"IIR1 INP1 MUX", "RX4", "RX_RX4"},
{"IIR1 INP1 MUX", "RX5", "RX_RX5"},
{"IIR1", NULL, "IIR1 INP2 MUX"},
{"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR1 INP2 MUX", "RX0", "RX_RX0"},
{"IIR1 INP2 MUX", "RX1", "RX_RX1"},
{"IIR1 INP2 MUX", "RX2", "RX_RX2"},
{"IIR1 INP2 MUX", "RX3", "RX_RX3"},
{"IIR1 INP2 MUX", "RX4", "RX_RX4"},
{"IIR1 INP2 MUX", "RX5", "RX_RX5"},
{"IIR1", NULL, "IIR1 INP3 MUX"},
{"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
{"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
{"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
{"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
{"IIR1 INP3 MUX", "RX0", "RX_RX0"},
{"IIR1 INP3 MUX", "RX1", "RX_RX1"},
{"IIR1 INP3 MUX", "RX2", "RX_RX2"},
{"IIR1 INP3 MUX", "RX3", "RX_RX3"},
{"IIR1 INP3 MUX", "RX4", "RX_RX4"},
{"IIR1 INP3 MUX", "RX5", "RX_RX5"},
{"SRC0", NULL, "IIR0"},
{"SRC1", NULL, "IIR1"},
{"RX INT0 MIX2 INP", "SRC0", "SRC0"},
{"RX INT0 MIX2 INP", "SRC1", "SRC1"},
{"RX INT1 MIX2 INP", "SRC0", "SRC0"},
{"RX INT1 MIX2 INP", "SRC1", "SRC1"},
{"RX INT2 MIX2 INP", "SRC0", "SRC0"},
{"RX INT2 MIX2 INP", "SRC1", "SRC1"},
};
static int rx_macro_component_probe(struct snd_soc_component *component)
{
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
snd_soc_component_init_regmap(component, rx->regmap);
snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
CDC_RX_DSM_OUT_DELAY_SEL_MASK,
CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
CDC_RX_DSM_OUT_DELAY_SEL_MASK,
CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
CDC_RX_DSM_OUT_DELAY_SEL_MASK,
CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
CDC_RX_DC_COEFF_SEL_MASK,
CDC_RX_DC_COEFF_SEL_TWO);
snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
CDC_RX_DC_COEFF_SEL_MASK,
CDC_RX_DC_COEFF_SEL_TWO);
snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
CDC_RX_DC_COEFF_SEL_MASK,
CDC_RX_DC_COEFF_SEL_TWO);
rx->component = component;
return 0;
}
static int swclk_gate_enable(struct clk_hw *hw)
{
struct rx_macro *rx = to_rx_macro(hw);
int ret;
ret = clk_prepare_enable(rx->mclk);
if (ret) {
dev_err(rx->dev, "unable to prepare mclk\n");
return ret;
}
rx_macro_mclk_enable(rx, true);
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_CLK_EN_MASK, 1);
return 0;
}
static void swclk_gate_disable(struct clk_hw *hw)
{
struct rx_macro *rx = to_rx_macro(hw);
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_CLK_EN_MASK, 0);
rx_macro_mclk_enable(rx, false);
clk_disable_unprepare(rx->mclk);
}
static int swclk_gate_is_enabled(struct clk_hw *hw)
{
struct rx_macro *rx = to_rx_macro(hw);
int ret, val;
regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val);
ret = val & BIT(0);
return ret;
}
static unsigned long swclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return parent_rate / 2;
}
static const struct clk_ops swclk_gate_ops = {
.prepare = swclk_gate_enable,
.unprepare = swclk_gate_disable,
.is_enabled = swclk_gate_is_enabled,
.recalc_rate = swclk_recalc_rate,
};
static int rx_macro_register_mclk_output(struct rx_macro *rx)
{
struct device *dev = rx->dev;
const char *parent_clk_name = NULL;
const char *clk_name = "lpass-rx-mclk";
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (rx->npl)
parent_clk_name = __clk_get_name(rx->npl);
else
parent_clk_name = __clk_get_name(rx->mclk);
init.name = clk_name;
init.ops = &swclk_gate_ops;
init.flags = 0;
init.parent_names = &parent_clk_name;
init.num_parents = 1;
rx->hw.init = &init;
hw = &rx->hw;
ret = devm_clk_hw_register(rx->dev, hw);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static const struct snd_soc_component_driver rx_macro_component_drv = {
.name = "RX-MACRO",
.probe = rx_macro_component_probe,
.controls = rx_macro_snd_controls,
.num_controls = ARRAY_SIZE(rx_macro_snd_controls),
.dapm_widgets = rx_macro_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets),
.dapm_routes = rx_audio_map,
.num_dapm_routes = ARRAY_SIZE(rx_audio_map),
};
static int rx_macro_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
kernel_ulong_t flags;
struct rx_macro *rx;
void __iomem *base;
int ret;
flags = (kernel_ulong_t)device_get_match_data(dev);
rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL);
if (!rx)
return -ENOMEM;
rx->macro = devm_clk_get_optional(dev, "macro");
if (IS_ERR(rx->macro))
return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n");
rx->dcodec = devm_clk_get_optional(dev, "dcodec");
if (IS_ERR(rx->dcodec))
return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n");
rx->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(rx->mclk))
return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n");
if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
rx->npl = devm_clk_get(dev, "npl");
if (IS_ERR(rx->npl))
return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n");
}
rx->fsgen = devm_clk_get(dev, "fsgen");
if (IS_ERR(rx->fsgen))
return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n");
rx->pds = lpass_macro_pds_init(dev);
if (IS_ERR(rx->pds))
return PTR_ERR(rx->pds);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
ret = PTR_ERR(base);
goto err;
}
rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
if (IS_ERR(rx->regmap)) {
ret = PTR_ERR(rx->regmap);
goto err;
}
dev_set_drvdata(dev, rx);
rx->dev = dev;
/* set MCLK and NPL rates */
clk_set_rate(rx->mclk, MCLK_FREQ);
clk_set_rate(rx->npl, MCLK_FREQ);
ret = clk_prepare_enable(rx->macro);
if (ret)
goto err;
ret = clk_prepare_enable(rx->dcodec);
if (ret)
goto err_dcodec;
ret = clk_prepare_enable(rx->mclk);
if (ret)
goto err_mclk;
ret = clk_prepare_enable(rx->npl);
if (ret)
goto err_npl;
ret = clk_prepare_enable(rx->fsgen);
if (ret)
goto err_fsgen;
/* reset swr block */
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_RESET_MASK,
CDC_RX_SWR_RESET);
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_CLK_EN_MASK, 1);
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_RESET_MASK, 0);
ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
rx_macro_dai,
ARRAY_SIZE(rx_macro_dai));
if (ret)
goto err_clkout;
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
ret = rx_macro_register_mclk_output(rx);
if (ret)
goto err_clkout;
return 0;
err_clkout:
clk_disable_unprepare(rx->fsgen);
err_fsgen:
clk_disable_unprepare(rx->npl);
err_npl:
clk_disable_unprepare(rx->mclk);
err_mclk:
clk_disable_unprepare(rx->dcodec);
err_dcodec:
clk_disable_unprepare(rx->macro);
err:
lpass_macro_pds_exit(rx->pds);
return ret;
}
static void rx_macro_remove(struct platform_device *pdev)
{
struct rx_macro *rx = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(rx->mclk);
clk_disable_unprepare(rx->npl);
clk_disable_unprepare(rx->fsgen);
clk_disable_unprepare(rx->macro);
clk_disable_unprepare(rx->dcodec);
lpass_macro_pds_exit(rx->pds);
}
static const struct of_device_id rx_macro_dt_match[] = {
{
.compatible = "qcom,sc7280-lpass-rx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8250-lpass-rx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8450-lpass-rx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
}, {
.compatible = "qcom,sm8550-lpass-rx-macro",
}, {
.compatible = "qcom,sc8280xp-lpass-rx-macro",
.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
},
{ }
};
MODULE_DEVICE_TABLE(of, rx_macro_dt_match);
static int __maybe_unused rx_macro_runtime_suspend(struct device *dev)
{
struct rx_macro *rx = dev_get_drvdata(dev);
regcache_cache_only(rx->regmap, true);
regcache_mark_dirty(rx->regmap);
clk_disable_unprepare(rx->fsgen);
clk_disable_unprepare(rx->npl);
clk_disable_unprepare(rx->mclk);
return 0;
}
static int __maybe_unused rx_macro_runtime_resume(struct device *dev)
{
struct rx_macro *rx = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(rx->mclk);
if (ret) {
dev_err(dev, "unable to prepare mclk\n");
return ret;
}
ret = clk_prepare_enable(rx->npl);
if (ret) {
dev_err(dev, "unable to prepare mclkx2\n");
goto err_npl;
}
ret = clk_prepare_enable(rx->fsgen);
if (ret) {
dev_err(dev, "unable to prepare fsgen\n");
goto err_fsgen;
}
regcache_cache_only(rx->regmap, false);
regcache_sync(rx->regmap);
return 0;
err_fsgen:
clk_disable_unprepare(rx->npl);
err_npl:
clk_disable_unprepare(rx->mclk);
return ret;
}
static const struct dev_pm_ops rx_macro_pm_ops = {
SET_RUNTIME_PM_OPS(rx_macro_runtime_suspend, rx_macro_runtime_resume, NULL)
};
static struct platform_driver rx_macro_driver = {
.driver = {
.name = "rx_macro",
.of_match_table = rx_macro_dt_match,
.suppress_bind_attrs = true,
.pm = &rx_macro_pm_ops,
},
.probe = rx_macro_probe,
.remove_new = rx_macro_remove,
};
module_platform_driver(rx_macro_driver);
MODULE_DESCRIPTION("RX macro driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/lpass-rx-macro.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* es8316.c -- es8316 ALSA SoC audio driver
* Copyright Everest Semiconductor Co.,Ltd
*
* Authors: David Yang <[email protected]>,
* Daniel Drake <[email protected]>
*/
#include <linux/module.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/regmap.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/jack.h>
#include "es8316.h"
/* In slave mode at single speed, the codec is documented as accepting 5
* MCLK/LRCK ratios, but we also add ratio 400, which is commonly used on
* Intel Cherry Trail platforms (19.2MHz MCLK, 48kHz LRCK).
*/
#define NR_SUPPORTED_MCLK_LRCK_RATIOS ARRAY_SIZE(supported_mclk_lrck_ratios)
static const unsigned int supported_mclk_lrck_ratios[] = {
256, 384, 400, 500, 512, 768, 1024
};
struct es8316_priv {
struct mutex lock;
struct clk *mclk;
struct regmap *regmap;
struct snd_soc_component *component;
struct snd_soc_jack *jack;
int irq;
unsigned int sysclk;
unsigned int allowed_rates[NR_SUPPORTED_MCLK_LRCK_RATIOS];
struct snd_pcm_hw_constraint_list sysclk_constraints;
bool jd_inverted;
};
/*
* ES8316 controls
*/
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9600, 50, 1);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9600, 50, 1);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_max_gain_tlv, -650, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_min_gain_tlv, -1200, 150, 0);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(alc_target_tlv,
0, 10, TLV_DB_SCALE_ITEM(-1650, 150, 0),
11, 11, TLV_DB_SCALE_ITEM(-150, 0, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(hpmixer_gain_tlv,
0, 4, TLV_DB_SCALE_ITEM(-1200, 150, 0),
8, 11, TLV_DB_SCALE_ITEM(-450, 150, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(adc_pga_gain_tlv,
0, 0, TLV_DB_SCALE_ITEM(-350, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(0, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(250, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
4, 7, TLV_DB_SCALE_ITEM(700, 300, 0),
8, 10, TLV_DB_SCALE_ITEM(1800, 300, 0),
);
static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(hpout_vol_tlv,
0, 0, TLV_DB_SCALE_ITEM(-4800, 0, 0),
1, 3, TLV_DB_SCALE_ITEM(-2400, 1200, 0),
);
static const char * const ng_type_txt[] =
{ "Constant PGA Gain", "Mute ADC Output" };
static const struct soc_enum ng_type =
SOC_ENUM_SINGLE(ES8316_ADC_ALC_NG, 6, 2, ng_type_txt);
static const char * const adcpol_txt[] = { "Normal", "Invert" };
static const struct soc_enum adcpol =
SOC_ENUM_SINGLE(ES8316_ADC_MUTE, 1, 2, adcpol_txt);
static const char *const dacpol_txt[] =
{ "Normal", "R Invert", "L Invert", "L + R Invert" };
static const struct soc_enum dacpol =
SOC_ENUM_SINGLE(ES8316_DAC_SET1, 0, 4, dacpol_txt);
static const struct snd_kcontrol_new es8316_snd_controls[] = {
SOC_DOUBLE_TLV("Headphone Playback Volume", ES8316_CPHP_ICAL_VOL,
4, 0, 3, 1, hpout_vol_tlv),
SOC_DOUBLE_TLV("Headphone Mixer Volume", ES8316_HPMIX_VOL,
4, 0, 11, 0, hpmixer_gain_tlv),
SOC_ENUM("Playback Polarity", dacpol),
SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8316_DAC_VOLL,
ES8316_DAC_VOLR, 0, 0xc0, 1, dac_vol_tlv),
SOC_SINGLE("DAC Soft Ramp Switch", ES8316_DAC_SET1, 4, 1, 1),
SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1, 2, 4, 0),
SOC_SINGLE("DAC Notch Filter Switch", ES8316_DAC_SET2, 6, 1, 0),
SOC_SINGLE("DAC Double Fs Switch", ES8316_DAC_SET2, 7, 1, 0),
SOC_SINGLE("DAC Stereo Enhancement", ES8316_DAC_SET3, 0, 7, 0),
SOC_SINGLE("DAC Mono Mix Switch", ES8316_DAC_SET3, 3, 1, 0),
SOC_ENUM("Capture Polarity", adcpol),
SOC_SINGLE("Mic Boost Switch", ES8316_ADC_D2SEPGA, 0, 1, 0),
SOC_SINGLE_TLV("ADC Capture Volume", ES8316_ADC_VOLUME,
0, 0xc0, 1, adc_vol_tlv),
SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8316_ADC_PGAGAIN,
4, 10, 0, adc_pga_gain_tlv),
SOC_SINGLE("ADC Soft Ramp Switch", ES8316_ADC_MUTE, 4, 1, 0),
SOC_SINGLE("ADC Double Fs Switch", ES8316_ADC_DMIC, 4, 1, 0),
SOC_SINGLE("ALC Capture Switch", ES8316_ADC_ALC1, 6, 1, 0),
SOC_SINGLE_TLV("ALC Capture Max Volume", ES8316_ADC_ALC1, 0, 28, 0,
alc_max_gain_tlv),
SOC_SINGLE_TLV("ALC Capture Min Volume", ES8316_ADC_ALC2, 0, 28, 0,
alc_min_gain_tlv),
SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 11, 0,
alc_target_tlv),
SOC_SINGLE("ALC Capture Hold Time", ES8316_ADC_ALC3, 0, 10, 0),
SOC_SINGLE("ALC Capture Decay Time", ES8316_ADC_ALC4, 4, 10, 0),
SOC_SINGLE("ALC Capture Attack Time", ES8316_ADC_ALC4, 0, 10, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", ES8316_ADC_ALC_NG,
5, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", ES8316_ADC_ALC_NG,
0, 31, 0),
SOC_ENUM("ALC Capture Noise Gate Type", ng_type),
};
/* Analog Input Mux */
static const char * const es8316_analog_in_txt[] = {
"lin1-rin1",
"lin2-rin2",
"lin1-rin1 with 20db Boost",
"lin2-rin2 with 20db Boost"
};
static const unsigned int es8316_analog_in_values[] = { 0, 1, 2, 3 };
static const struct soc_enum es8316_analog_input_enum =
SOC_VALUE_ENUM_SINGLE(ES8316_ADC_PDN_LINSEL, 4, 3,
ARRAY_SIZE(es8316_analog_in_txt),
es8316_analog_in_txt,
es8316_analog_in_values);
static const struct snd_kcontrol_new es8316_analog_in_mux_controls =
SOC_DAPM_ENUM("Route", es8316_analog_input_enum);
static const char * const es8316_dmic_txt[] = {
"dmic disable",
"dmic data at high level",
"dmic data at low level",
};
static const unsigned int es8316_dmic_values[] = { 0, 2, 3 };
static const struct soc_enum es8316_dmic_src_enum =
SOC_VALUE_ENUM_SINGLE(ES8316_ADC_DMIC, 0, 3,
ARRAY_SIZE(es8316_dmic_txt),
es8316_dmic_txt,
es8316_dmic_values);
static const struct snd_kcontrol_new es8316_dmic_src_controls =
SOC_DAPM_ENUM("Route", es8316_dmic_src_enum);
/* hp mixer mux */
static const char * const es8316_hpmux_texts[] = {
"lin1-rin1",
"lin2-rin2",
"lin-rin with Boost",
"lin-rin with Boost and PGA"
};
static SOC_ENUM_SINGLE_DECL(es8316_left_hpmux_enum, ES8316_HPMIX_SEL,
4, es8316_hpmux_texts);
static const struct snd_kcontrol_new es8316_left_hpmux_controls =
SOC_DAPM_ENUM("Route", es8316_left_hpmux_enum);
static SOC_ENUM_SINGLE_DECL(es8316_right_hpmux_enum, ES8316_HPMIX_SEL,
0, es8316_hpmux_texts);
static const struct snd_kcontrol_new es8316_right_hpmux_controls =
SOC_DAPM_ENUM("Route", es8316_right_hpmux_enum);
/* headphone Output Mixer */
static const struct snd_kcontrol_new es8316_out_left_mix[] = {
SOC_DAPM_SINGLE("LLIN Switch", ES8316_HPMIX_SWITCH, 6, 1, 0),
SOC_DAPM_SINGLE("Left DAC Switch", ES8316_HPMIX_SWITCH, 7, 1, 0),
};
static const struct snd_kcontrol_new es8316_out_right_mix[] = {
SOC_DAPM_SINGLE("RLIN Switch", ES8316_HPMIX_SWITCH, 2, 1, 0),
SOC_DAPM_SINGLE("Right DAC Switch", ES8316_HPMIX_SWITCH, 3, 1, 0),
};
/* DAC data source mux */
static const char * const es8316_dacsrc_texts[] = {
"LDATA TO LDAC, RDATA TO RDAC",
"LDATA TO LDAC, LDATA TO RDAC",
"RDATA TO LDAC, RDATA TO RDAC",
"RDATA TO LDAC, LDATA TO RDAC",
};
static SOC_ENUM_SINGLE_DECL(es8316_dacsrc_mux_enum, ES8316_DAC_SET1,
6, es8316_dacsrc_texts);
static const struct snd_kcontrol_new es8316_dacsrc_mux_controls =
SOC_DAPM_ENUM("Route", es8316_dacsrc_mux_enum);
static const struct snd_soc_dapm_widget es8316_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("Bias", ES8316_SYS_PDN, 3, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Analog power", ES8316_SYS_PDN, 4, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", ES8316_SYS_PDN, 5, 1, NULL, 0),
SND_SOC_DAPM_INPUT("DMIC"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
/* Input Mux */
SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
&es8316_analog_in_mux_controls),
SND_SOC_DAPM_SUPPLY("ADC Vref", ES8316_SYS_PDN, 1, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC bias", ES8316_SYS_PDN, 2, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Clock", ES8316_CLKMGR_CLKSW, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line input PGA", ES8316_ADC_PDN_LINSEL,
7, 1, NULL, 0),
SND_SOC_DAPM_ADC("Mono ADC", NULL, ES8316_ADC_PDN_LINSEL, 6, 1),
SND_SOC_DAPM_MUX("Digital Mic Mux", SND_SOC_NOPM, 0, 0,
&es8316_dmic_src_controls),
/* Digital Interface */
SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 1,
ES8316_SERDATA_ADC, 6, 1),
SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DAC Source Mux", SND_SOC_NOPM, 0, 0,
&es8316_dacsrc_mux_controls),
SND_SOC_DAPM_SUPPLY("DAC Vref", ES8316_SYS_PDN, 0, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Clock", ES8316_CLKMGR_CLKSW, 2, 0, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", NULL, ES8316_DAC_PDN, 0, 1),
SND_SOC_DAPM_DAC("Left DAC", NULL, ES8316_DAC_PDN, 4, 1),
/* Headphone Output Side */
SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0,
&es8316_left_hpmux_controls),
SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0,
&es8316_right_hpmux_controls),
SND_SOC_DAPM_MIXER("Left Headphone Mixer", ES8316_HPMIX_PDN,
5, 1, &es8316_out_left_mix[0],
ARRAY_SIZE(es8316_out_left_mix)),
SND_SOC_DAPM_MIXER("Right Headphone Mixer", ES8316_HPMIX_PDN,
1, 1, &es8316_out_right_mix[0],
ARRAY_SIZE(es8316_out_right_mix)),
SND_SOC_DAPM_PGA("Left Headphone Mixer Out", ES8316_HPMIX_PDN,
4, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone Mixer Out", ES8316_HPMIX_PDN,
0, 1, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Left Headphone Charge Pump", ES8316_CPHP_OUTEN,
6, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Right Headphone Charge Pump", ES8316_CPHP_OUTEN,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Charge Pump", ES8316_CPHP_PDN2,
5, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Charge Pump Clock", ES8316_CLKMGR_CLKSW,
4, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Left Headphone Driver", ES8316_CPHP_OUTEN,
5, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Right Headphone Driver", ES8316_CPHP_OUTEN,
1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Out", ES8316_CPHP_PDN1, 2, 1, NULL, 0),
/* pdn_Lical and pdn_Rical bits are documented as Reserved, but must
* be explicitly unset in order to enable HP output
*/
SND_SOC_DAPM_SUPPLY("Left Headphone ical", ES8316_CPHP_ICAL_VOL,
7, 1, NULL, 0),
SND_SOC_DAPM_SUPPLY("Right Headphone ical", ES8316_CPHP_ICAL_VOL,
3, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_route es8316_dapm_routes[] = {
/* Recording */
{"MIC1", NULL, "Mic Bias"},
{"MIC2", NULL, "Mic Bias"},
{"MIC1", NULL, "Bias"},
{"MIC2", NULL, "Bias"},
{"MIC1", NULL, "Analog power"},
{"MIC2", NULL, "Analog power"},
{"Differential Mux", "lin1-rin1", "MIC1"},
{"Differential Mux", "lin2-rin2", "MIC2"},
{"Line input PGA", NULL, "Differential Mux"},
{"Mono ADC", NULL, "ADC Clock"},
{"Mono ADC", NULL, "ADC Vref"},
{"Mono ADC", NULL, "ADC bias"},
{"Mono ADC", NULL, "Line input PGA"},
/* It's not clear why, but to avoid recording only silence,
* the DAC clock must be running for the ADC to work.
*/
{"Mono ADC", NULL, "DAC Clock"},
{"Digital Mic Mux", "dmic disable", "Mono ADC"},
{"I2S OUT", NULL, "Digital Mic Mux"},
/* Playback */
{"DAC Source Mux", "LDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
{"Left DAC", NULL, "DAC Clock"},
{"Right DAC", NULL, "DAC Clock"},
{"Left DAC", NULL, "DAC Vref"},
{"Right DAC", NULL, "DAC Vref"},
{"Left DAC", NULL, "DAC Source Mux"},
{"Right DAC", NULL, "DAC Source Mux"},
{"Left Headphone Mux", "lin-rin with Boost and PGA", "Line input PGA"},
{"Right Headphone Mux", "lin-rin with Boost and PGA", "Line input PGA"},
{"Left Headphone Mixer", "LLIN Switch", "Left Headphone Mux"},
{"Left Headphone Mixer", "Left DAC Switch", "Left DAC"},
{"Right Headphone Mixer", "RLIN Switch", "Right Headphone Mux"},
{"Right Headphone Mixer", "Right DAC Switch", "Right DAC"},
{"Left Headphone Mixer Out", NULL, "Left Headphone Mixer"},
{"Right Headphone Mixer Out", NULL, "Right Headphone Mixer"},
{"Left Headphone Charge Pump", NULL, "Left Headphone Mixer Out"},
{"Right Headphone Charge Pump", NULL, "Right Headphone Mixer Out"},
{"Left Headphone Charge Pump", NULL, "Headphone Charge Pump"},
{"Right Headphone Charge Pump", NULL, "Headphone Charge Pump"},
{"Left Headphone Charge Pump", NULL, "Headphone Charge Pump Clock"},
{"Right Headphone Charge Pump", NULL, "Headphone Charge Pump Clock"},
{"Left Headphone Driver", NULL, "Left Headphone Charge Pump"},
{"Right Headphone Driver", NULL, "Right Headphone Charge Pump"},
{"HPOL", NULL, "Left Headphone Driver"},
{"HPOR", NULL, "Right Headphone Driver"},
{"HPOL", NULL, "Left Headphone ical"},
{"HPOR", NULL, "Right Headphone ical"},
{"Headphone Out", NULL, "Bias"},
{"Headphone Out", NULL, "Analog power"},
{"HPOL", NULL, "Headphone Out"},
{"HPOR", NULL, "Headphone Out"},
};
static int es8316_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
int i, ret;
int count = 0;
es8316->sysclk = freq;
es8316->sysclk_constraints.list = NULL;
es8316->sysclk_constraints.count = 0;
if (freq == 0)
return 0;
ret = clk_set_rate(es8316->mclk, freq);
if (ret)
return ret;
/* Limit supported sample rates to ones that can be autodetected
* by the codec running in slave mode.
*/
for (i = 0; i < NR_SUPPORTED_MCLK_LRCK_RATIOS; i++) {
const unsigned int ratio = supported_mclk_lrck_ratios[i];
if (freq % ratio == 0)
es8316->allowed_rates[count++] = freq / ratio;
}
if (count) {
es8316->sysclk_constraints.list = es8316->allowed_rates;
es8316->sysclk_constraints.count = count;
}
return 0;
}
static int es8316_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u8 serdata1 = 0;
u8 serdata2 = 0;
u8 clksw;
u8 mask;
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBP_CFP)
serdata1 |= ES8316_SERDATA1_MASTER;
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S) {
dev_err(component->dev, "Codec driver only supports I2S format\n");
return -EINVAL;
}
/* Clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
serdata1 |= ES8316_SERDATA1_BCLK_INV;
serdata2 |= ES8316_SERDATA2_ADCLRP;
break;
case SND_SOC_DAIFMT_IB_NF:
serdata1 |= ES8316_SERDATA1_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
serdata2 |= ES8316_SERDATA2_ADCLRP;
break;
default:
return -EINVAL;
}
mask = ES8316_SERDATA1_MASTER | ES8316_SERDATA1_BCLK_INV;
snd_soc_component_update_bits(component, ES8316_SERDATA1, mask, serdata1);
mask = ES8316_SERDATA2_FMT_MASK | ES8316_SERDATA2_ADCLRP;
snd_soc_component_update_bits(component, ES8316_SERDATA_ADC, mask, serdata2);
snd_soc_component_update_bits(component, ES8316_SERDATA_DAC, mask, serdata2);
/* Enable BCLK and MCLK inputs in slave mode */
clksw = ES8316_CLKMGR_CLKSW_MCLK_ON | ES8316_CLKMGR_CLKSW_BCLK_ON;
snd_soc_component_update_bits(component, ES8316_CLKMGR_CLKSW, clksw, clksw);
return 0;
}
static int es8316_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
if (es8316->sysclk_constraints.list)
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&es8316->sysclk_constraints);
return 0;
}
static int es8316_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
u8 wordlen = 0;
u8 bclk_divider;
u16 lrck_divider;
int i;
/* Validate supported sample rates that are autodetected from MCLK */
for (i = 0; i < NR_SUPPORTED_MCLK_LRCK_RATIOS; i++) {
const unsigned int ratio = supported_mclk_lrck_ratios[i];
if (es8316->sysclk % ratio != 0)
continue;
if (es8316->sysclk / ratio == params_rate(params))
break;
}
if (i == NR_SUPPORTED_MCLK_LRCK_RATIOS)
return -EINVAL;
lrck_divider = es8316->sysclk / params_rate(params);
bclk_divider = lrck_divider / 4;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
wordlen = ES8316_SERDATA2_LEN_16;
bclk_divider /= 16;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
wordlen = ES8316_SERDATA2_LEN_20;
bclk_divider /= 20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_S24_3LE:
wordlen = ES8316_SERDATA2_LEN_24;
bclk_divider /= 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
wordlen = ES8316_SERDATA2_LEN_32;
bclk_divider /= 32;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, ES8316_SERDATA_DAC,
ES8316_SERDATA2_LEN_MASK, wordlen);
snd_soc_component_update_bits(component, ES8316_SERDATA_ADC,
ES8316_SERDATA2_LEN_MASK, wordlen);
snd_soc_component_update_bits(component, ES8316_SERDATA1, 0x1f, bclk_divider);
snd_soc_component_update_bits(component, ES8316_CLKMGR_ADCDIV1, 0x0f, lrck_divider >> 8);
snd_soc_component_update_bits(component, ES8316_CLKMGR_ADCDIV2, 0xff, lrck_divider & 0xff);
snd_soc_component_update_bits(component, ES8316_CLKMGR_DACDIV1, 0x0f, lrck_divider >> 8);
snd_soc_component_update_bits(component, ES8316_CLKMGR_DACDIV2, 0xff, lrck_divider & 0xff);
return 0;
}
static int es8316_mute(struct snd_soc_dai *dai, int mute, int direction)
{
snd_soc_component_update_bits(dai->component, ES8316_DAC_SET1, 0x20,
mute ? 0x20 : 0);
return 0;
}
#define ES8316_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops es8316_ops = {
.startup = es8316_pcm_startup,
.hw_params = es8316_pcm_hw_params,
.set_fmt = es8316_set_dai_fmt,
.set_sysclk = es8316_set_dai_sysclk,
.mute_stream = es8316_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver es8316_dai = {
.name = "ES8316 HiFi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ES8316_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ES8316_FORMATS,
},
.ops = &es8316_ops,
.symmetric_rate = 1,
};
static void es8316_enable_micbias_for_mic_gnd_short_detect(
struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Bias");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Analog power");
snd_soc_dapm_force_enable_pin_unlocked(dapm, "Mic Bias");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
msleep(20);
}
static void es8316_disable_micbias_for_mic_gnd_short_detect(
struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
snd_soc_dapm_mutex_lock(dapm);
snd_soc_dapm_disable_pin_unlocked(dapm, "Mic Bias");
snd_soc_dapm_disable_pin_unlocked(dapm, "Analog power");
snd_soc_dapm_disable_pin_unlocked(dapm, "Bias");
snd_soc_dapm_sync_unlocked(dapm);
snd_soc_dapm_mutex_unlock(dapm);
}
static irqreturn_t es8316_irq(int irq, void *data)
{
struct es8316_priv *es8316 = data;
struct snd_soc_component *comp = es8316->component;
unsigned int flags;
mutex_lock(&es8316->lock);
regmap_read(es8316->regmap, ES8316_GPIO_FLAG, &flags);
if (flags == 0x00)
goto out; /* Powered-down / reset */
/* Catch spurious IRQ before set_jack is called */
if (!es8316->jack)
goto out;
if (es8316->jd_inverted)
flags ^= ES8316_GPIO_FLAG_HP_NOT_INSERTED;
dev_dbg(comp->dev, "gpio flags %#04x\n", flags);
if (flags & ES8316_GPIO_FLAG_HP_NOT_INSERTED) {
/* Jack removed, or spurious IRQ? */
if (es8316->jack->status & SND_JACK_MICROPHONE)
es8316_disable_micbias_for_mic_gnd_short_detect(comp);
if (es8316->jack->status & SND_JACK_HEADPHONE) {
snd_soc_jack_report(es8316->jack, 0,
SND_JACK_HEADSET | SND_JACK_BTN_0);
dev_dbg(comp->dev, "jack unplugged\n");
}
} else if (!(es8316->jack->status & SND_JACK_HEADPHONE)) {
/* Jack inserted, determine type */
es8316_enable_micbias_for_mic_gnd_short_detect(comp);
regmap_read(es8316->regmap, ES8316_GPIO_FLAG, &flags);
if (es8316->jd_inverted)
flags ^= ES8316_GPIO_FLAG_HP_NOT_INSERTED;
dev_dbg(comp->dev, "gpio flags %#04x\n", flags);
if (flags & ES8316_GPIO_FLAG_HP_NOT_INSERTED) {
/* Jack unplugged underneath us */
es8316_disable_micbias_for_mic_gnd_short_detect(comp);
} else if (flags & ES8316_GPIO_FLAG_GM_NOT_SHORTED) {
/* Open, headset */
snd_soc_jack_report(es8316->jack,
SND_JACK_HEADSET,
SND_JACK_HEADSET);
/* Keep mic-gnd-short detection on for button press */
} else {
/* Shorted, headphones */
snd_soc_jack_report(es8316->jack,
SND_JACK_HEADPHONE,
SND_JACK_HEADSET);
/* No longer need mic-gnd-short detection */
es8316_disable_micbias_for_mic_gnd_short_detect(comp);
}
} else if (es8316->jack->status & SND_JACK_MICROPHONE) {
/* Interrupt while jack inserted, report button state */
if (flags & ES8316_GPIO_FLAG_GM_NOT_SHORTED) {
/* Open, button release */
snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0);
} else {
/* Short, button press */
snd_soc_jack_report(es8316->jack,
SND_JACK_BTN_0,
SND_JACK_BTN_0);
}
}
out:
mutex_unlock(&es8316->lock);
return IRQ_HANDLED;
}
static void es8316_enable_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *jack)
{
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
/*
* Init es8316->jd_inverted here and not in the probe, as we cannot
* guarantee that the bytchr-es8316 driver, which might set this
* property, will probe before us.
*/
es8316->jd_inverted = device_property_read_bool(component->dev,
"everest,jack-detect-inverted");
mutex_lock(&es8316->lock);
es8316->jack = jack;
if (es8316->jack->status & SND_JACK_MICROPHONE)
es8316_enable_micbias_for_mic_gnd_short_detect(component);
snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE,
ES8316_GPIO_ENABLE_INTERRUPT,
ES8316_GPIO_ENABLE_INTERRUPT);
mutex_unlock(&es8316->lock);
/* Enable irq and sync initial jack state */
enable_irq(es8316->irq);
es8316_irq(es8316->irq, es8316);
}
static void es8316_disable_jack_detect(struct snd_soc_component *component)
{
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
if (!es8316->jack)
return; /* Already disabled (or never enabled) */
disable_irq(es8316->irq);
mutex_lock(&es8316->lock);
snd_soc_component_update_bits(component, ES8316_GPIO_DEBOUNCE,
ES8316_GPIO_ENABLE_INTERRUPT, 0);
if (es8316->jack->status & SND_JACK_MICROPHONE) {
es8316_disable_micbias_for_mic_gnd_short_detect(component);
snd_soc_jack_report(es8316->jack, 0, SND_JACK_BTN_0);
}
es8316->jack = NULL;
mutex_unlock(&es8316->lock);
}
static int es8316_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
if (jack)
es8316_enable_jack_detect(component, jack);
else
es8316_disable_jack_detect(component);
return 0;
}
static int es8316_probe(struct snd_soc_component *component)
{
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
int ret;
es8316->component = component;
es8316->mclk = devm_clk_get_optional(component->dev, "mclk");
if (IS_ERR(es8316->mclk)) {
dev_err(component->dev, "unable to get mclk\n");
return PTR_ERR(es8316->mclk);
}
if (!es8316->mclk)
dev_warn(component->dev, "assuming static mclk\n");
ret = clk_prepare_enable(es8316->mclk);
if (ret) {
dev_err(component->dev, "unable to enable mclk\n");
return ret;
}
/* Reset codec and enable current state machine */
snd_soc_component_write(component, ES8316_RESET, 0x3f);
usleep_range(5000, 5500);
snd_soc_component_write(component, ES8316_RESET, ES8316_RESET_CSM_ON);
msleep(30);
/*
* Documentation is unclear, but this value from the vendor driver is
* needed otherwise audio output is silent.
*/
snd_soc_component_write(component, ES8316_SYS_VMIDSEL, 0xff);
/*
* Documentation for this register is unclear and incomplete,
* but here is a vendor-provided value that improves volume
* and quality for Intel CHT platforms.
*/
snd_soc_component_write(component, ES8316_CLKMGR_ADCOSR, 0x32);
return 0;
}
static void es8316_remove(struct snd_soc_component *component)
{
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
clk_disable_unprepare(es8316->mclk);
}
static int es8316_resume(struct snd_soc_component *component)
{
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
regcache_cache_only(es8316->regmap, false);
regcache_sync(es8316->regmap);
return 0;
}
static int es8316_suspend(struct snd_soc_component *component)
{
struct es8316_priv *es8316 = snd_soc_component_get_drvdata(component);
regcache_cache_only(es8316->regmap, true);
regcache_mark_dirty(es8316->regmap);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_es8316 = {
.probe = es8316_probe,
.remove = es8316_remove,
.resume = es8316_resume,
.suspend = es8316_suspend,
.set_jack = es8316_set_jack,
.controls = es8316_snd_controls,
.num_controls = ARRAY_SIZE(es8316_snd_controls),
.dapm_widgets = es8316_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(es8316_dapm_widgets),
.dapm_routes = es8316_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(es8316_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static bool es8316_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ES8316_GPIO_FLAG:
return true;
default:
return false;
}
}
static const struct regmap_config es8316_regmap = {
.reg_bits = 8,
.val_bits = 8,
.use_single_read = true,
.use_single_write = true,
.max_register = 0x53,
.volatile_reg = es8316_volatile_reg,
.cache_type = REGCACHE_MAPLE,
};
static int es8316_i2c_probe(struct i2c_client *i2c_client)
{
struct device *dev = &i2c_client->dev;
struct es8316_priv *es8316;
int ret;
es8316 = devm_kzalloc(&i2c_client->dev, sizeof(struct es8316_priv),
GFP_KERNEL);
if (es8316 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c_client, es8316);
es8316->regmap = devm_regmap_init_i2c(i2c_client, &es8316_regmap);
if (IS_ERR(es8316->regmap))
return PTR_ERR(es8316->regmap);
es8316->irq = i2c_client->irq;
mutex_init(&es8316->lock);
if (es8316->irq > 0) {
ret = devm_request_threaded_irq(dev, es8316->irq, NULL, es8316_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT | IRQF_NO_AUTOEN,
"es8316", es8316);
if (ret) {
dev_warn(dev, "Failed to get IRQ %d: %d\n", es8316->irq, ret);
es8316->irq = -ENXIO;
}
}
return devm_snd_soc_register_component(&i2c_client->dev,
&soc_component_dev_es8316,
&es8316_dai, 1);
}
static const struct i2c_device_id es8316_i2c_id[] = {
{"es8316", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, es8316_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id es8316_of_match[] = {
{ .compatible = "everest,es8316", },
{},
};
MODULE_DEVICE_TABLE(of, es8316_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id es8316_acpi_match[] = {
{"ESSX8316", 0},
{"ESSX8336", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, es8316_acpi_match);
#endif
static struct i2c_driver es8316_i2c_driver = {
.driver = {
.name = "es8316",
.acpi_match_table = ACPI_PTR(es8316_acpi_match),
.of_match_table = of_match_ptr(es8316_of_match),
},
.probe = es8316_i2c_probe,
.id_table = es8316_i2c_id,
};
module_i2c_driver(es8316_i2c_driver);
MODULE_DESCRIPTION("Everest Semi ES8316 ALSA SoC Codec Driver");
MODULE_AUTHOR("David Yang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/es8316.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* max98390.c -- MAX98390 ALSA Soc Audio driver
*
* Copyright (C) 2020 Maxim Integrated Products
*
*/
#include <linux/acpi.h>
#include <linux/cdev.h>
#include <linux/dmi.h>
#include <linux/firmware.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98390.h"
static struct reg_default max98390_reg_defaults[] = {
{MAX98390_INT_EN1, 0xf0},
{MAX98390_INT_EN2, 0x00},
{MAX98390_INT_EN3, 0x00},
{MAX98390_INT_FLAG_CLR1, 0x00},
{MAX98390_INT_FLAG_CLR2, 0x00},
{MAX98390_INT_FLAG_CLR3, 0x00},
{MAX98390_IRQ_CTRL, 0x01},
{MAX98390_CLK_MON, 0x6d},
{MAX98390_DAT_MON, 0x03},
{MAX98390_WDOG_CTRL, 0x00},
{MAX98390_WDOG_RST, 0x00},
{MAX98390_MEAS_ADC_THERM_WARN_THRESH, 0x75},
{MAX98390_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
{MAX98390_MEAS_ADC_THERM_HYSTERESIS, 0x08},
{MAX98390_PIN_CFG, 0x55},
{MAX98390_PCM_RX_EN_A, 0x00},
{MAX98390_PCM_RX_EN_B, 0x00},
{MAX98390_PCM_TX_EN_A, 0x00},
{MAX98390_PCM_TX_EN_B, 0x00},
{MAX98390_PCM_TX_HIZ_CTRL_A, 0xff},
{MAX98390_PCM_TX_HIZ_CTRL_B, 0xff},
{MAX98390_PCM_CH_SRC_1, 0x00},
{MAX98390_PCM_CH_SRC_2, 0x00},
{MAX98390_PCM_CH_SRC_3, 0x00},
{MAX98390_PCM_MODE_CFG, 0xc0},
{MAX98390_PCM_MASTER_MODE, 0x1c},
{MAX98390_PCM_CLK_SETUP, 0x44},
{MAX98390_PCM_SR_SETUP, 0x08},
{MAX98390_ICC_RX_EN_A, 0x00},
{MAX98390_ICC_RX_EN_B, 0x00},
{MAX98390_ICC_TX_EN_A, 0x00},
{MAX98390_ICC_TX_EN_B, 0x00},
{MAX98390_ICC_HIZ_MANUAL_MODE, 0x00},
{MAX98390_ICC_TX_HIZ_EN_A, 0x00},
{MAX98390_ICC_TX_HIZ_EN_B, 0x00},
{MAX98390_ICC_LNK_EN, 0x00},
{MAX98390_R2039_AMP_DSP_CFG, 0x0f},
{MAX98390_R203A_AMP_EN, 0x81},
{MAX98390_TONE_GEN_DC_CFG, 0x00},
{MAX98390_SPK_SRC_SEL, 0x00},
{MAX98390_SSM_CFG, 0x85},
{MAX98390_MEAS_EN, 0x03},
{MAX98390_MEAS_DSP_CFG, 0x0f},
{MAX98390_BOOST_CTRL0, 0x1c},
{MAX98390_BOOST_CTRL3, 0x01},
{MAX98390_BOOST_CTRL1, 0x40},
{MAX98390_MEAS_ADC_CFG, 0x07},
{MAX98390_MEAS_ADC_BASE_MSB, 0x00},
{MAX98390_MEAS_ADC_BASE_LSB, 0x23},
{MAX98390_ADC_CH0_DIVIDE, 0x00},
{MAX98390_ADC_CH1_DIVIDE, 0x00},
{MAX98390_ADC_CH2_DIVIDE, 0x00},
{MAX98390_ADC_CH0_FILT_CFG, 0x00},
{MAX98390_ADC_CH1_FILT_CFG, 0x00},
{MAX98390_ADC_CH2_FILT_CFG, 0x00},
{MAX98390_PWR_GATE_CTL, 0x2c},
{MAX98390_BROWNOUT_EN, 0x00},
{MAX98390_BROWNOUT_INFINITE_HOLD, 0x00},
{MAX98390_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
{MAX98390_BROWNOUT_LVL_HOLD, 0x00},
{MAX98390_BROWNOUT_LVL1_THRESH, 0x00},
{MAX98390_BROWNOUT_LVL2_THRESH, 0x00},
{MAX98390_BROWNOUT_LVL3_THRESH, 0x00},
{MAX98390_BROWNOUT_LVL4_THRESH, 0x00},
{MAX98390_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
{MAX98390_BROWNOUT_AMP_LIMITER_ATK_REL, 0x1f},
{MAX98390_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
{MAX98390_BROWNOUT_AMP1_CLIP_MODE, 0x00},
{MAX98390_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
{MAX98390_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
{MAX98390_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
{MAX98390_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
{MAX98390_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
{MAX98390_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
{MAX98390_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
{MAX98390_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
{MAX98390_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
{MAX98390_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
{MAX98390_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
{MAX98390_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
{MAX98390_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
{MAX98390_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
{MAX98390_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
{MAX98390_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
{MAX98390_BROWNOUT_ILIM_HLD, 0x00},
{MAX98390_BROWNOUT_LIM_HLD, 0x00},
{MAX98390_BROWNOUT_CLIP_HLD, 0x00},
{MAX98390_BROWNOUT_GAIN_HLD, 0x00},
{MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0f},
{MAX98390_ENV_TRACK_BOOST_VOUT_DELAY, 0x80},
{MAX98390_ENV_TRACK_REL_RATE, 0x07},
{MAX98390_ENV_TRACK_HOLD_RATE, 0x07},
{MAX98390_ENV_TRACK_CTRL, 0x01},
{MAX98390_BOOST_BYPASS1, 0x49},
{MAX98390_BOOST_BYPASS2, 0x2b},
{MAX98390_BOOST_BYPASS3, 0x08},
{MAX98390_FET_SCALING1, 0x00},
{MAX98390_FET_SCALING2, 0x03},
{MAX98390_FET_SCALING3, 0x00},
{MAX98390_FET_SCALING4, 0x07},
{MAX98390_SPK_SPEEDUP, 0x00},
{DSMIG_WB_DRC_RELEASE_TIME_1, 0x00},
{DSMIG_WB_DRC_RELEASE_TIME_2, 0x00},
{DSMIG_WB_DRC_ATTACK_TIME_1, 0x00},
{DSMIG_WB_DRC_ATTACK_TIME_2, 0x00},
{DSMIG_WB_DRC_COMPRESSION_RATIO, 0x00},
{DSMIG_WB_DRC_COMPRESSION_THRESHOLD, 0x00},
{DSMIG_WB_DRC_MAKEUPGAIN, 0x00},
{DSMIG_WB_DRC_NOISE_GATE_THRESHOLD, 0x00},
{DSMIG_WBDRC_HPF_ENABLE, 0x00},
{DSMIG_WB_DRC_TEST_SMOOTHER_OUT_EN, 0x00},
{DSMIG_PPR_THRESHOLD, 0x00},
{DSM_STEREO_BASS_CHANNEL_SELECT, 0x00},
{DSM_TPROT_THRESHOLD_BYTE0, 0x00},
{DSM_TPROT_THRESHOLD_BYTE1, 0x00},
{DSM_TPROT_ROOM_TEMPERATURE_BYTE0, 0x00},
{DSM_TPROT_ROOM_TEMPERATURE_BYTE1, 0x00},
{DSM_TPROT_RECIP_RDC_ROOM_BYTE0, 0x00},
{DSM_TPROT_RECIP_RDC_ROOM_BYTE1, 0x00},
{DSM_TPROT_RECIP_RDC_ROOM_BYTE2, 0x00},
{DSM_TPROT_RECIP_TCONST_BYTE0, 0x00},
{DSM_TPROT_RECIP_TCONST_BYTE1, 0x00},
{DSM_TPROT_RECIP_TCONST_BYTE2, 0x00},
{DSM_THERMAL_ATTENUATION_SETTINGS, 0x00},
{DSM_THERMAL_PILOT_TONE_ATTENUATION, 0x00},
{DSM_TPROT_PG_TEMP_THRESH_BYTE0, 0x00},
{DSM_TPROT_PG_TEMP_THRESH_BYTE1, 0x00},
{DSMIG_DEBUZZER_THRESHOLD, 0x00},
{DSMIG_DEBUZZER_ALPHA_COEF_TEST_ONLY, 0x08},
{DSM_VOL_ENA, 0x20},
{DSM_VOL_CTRL, 0xa0},
{DSMIG_EN, 0x00},
{MAX98390_R23E1_DSP_GLOBAL_EN, 0x00},
{MAX98390_R23FF_GLOBAL_EN, 0x00},
};
static int max98390_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
unsigned int mode;
unsigned int format;
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
mode = MAX98390_PCM_MASTER_MODE_SLAVE;
break;
case SND_SOC_DAIFMT_CBP_CFP:
max98390->provider = true;
mode = MAX98390_PCM_MASTER_MODE_MASTER;
break;
default:
dev_err(component->dev, "DAI clock mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_MASTER_MODE,
MAX98390_PCM_MASTER_MODE_MASK,
mode);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_MODE_CFG,
MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98390_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98390_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98390_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98390_PCM_FORMAT_TDM_MODE0;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_MODE_CFG,
MAX98390_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98390_PCM_MODE_CFG_FORMAT_SHIFT);
return 0;
}
static int max98390_get_bclk_sel(int bclk)
{
int i;
/* BCLKs per LRCLK */
static int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 320, 384, 512,
};
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98390_set_clock(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
/* codec MCLK rate in master mode */
static int rate_table[] = {
5644800, 6000000, 6144000, 6500000,
9600000, 11289600, 12000000, 12288000,
13000000, 19200000,
};
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params)
* snd_pcm_format_width(params_format(params));
int value;
if (max98390->provider) {
int i;
/* match rate to closest value */
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
if (rate_table[i] >= max98390->sysclk)
break;
}
if (i == ARRAY_SIZE(rate_table)) {
dev_err(component->dev, "failed to find proper clock rate.\n");
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_MASTER_MODE,
MAX98390_PCM_MASTER_MODE_MCLK_MASK,
i << MAX98390_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
}
if (!max98390->tdm_mode) {
/* BCLK configuration */
value = max98390_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_CLK_SETUP,
MAX98390_PCM_CLK_SETUP_BSEL_MASK,
value);
}
return 0;
}
static int max98390_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component =
dai->component;
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
unsigned int sampling_rate;
unsigned int chan_sz;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_MODE_CFG,
MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(component->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98390_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98390_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98390_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98390_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98390_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98390_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98390_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98390_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98390_PCM_SR_SET1_SR_48000;
break;
default:
dev_err(component->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98390->regmap,
MAX98390_PCM_SR_SETUP,
MAX98390_PCM_SR_SET1_SR_MASK,
sampling_rate);
return max98390_set_clock(component, params);
err:
return -EINVAL;
}
static int max98390_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
int bsel;
unsigned int chan_sz;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98390->tdm_mode = false;
else
max98390->tdm_mode = true;
dev_dbg(component->dev,
"Tdm mode : %d\n", max98390->tdm_mode);
/* BCLK configuration */
bsel = max98390_get_bclk_sel(slots * slot_width);
if (!bsel) {
dev_err(component->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_CLK_SETUP,
MAX98390_PCM_CLK_SETUP_BSEL_MASK,
bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98390->regmap,
MAX98390_PCM_MODE_CFG,
MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
regmap_write(max98390->regmap,
MAX98390_PCM_RX_EN_A,
rx_mask & 0xFF);
regmap_write(max98390->regmap,
MAX98390_PCM_RX_EN_B,
(rx_mask & 0xFF00) >> 8);
/* Tx slot Hi-Z configuration */
regmap_write(max98390->regmap,
MAX98390_PCM_TX_HIZ_CTRL_A,
~tx_mask & 0xFF);
regmap_write(max98390->regmap,
MAX98390_PCM_TX_HIZ_CTRL_B,
(~tx_mask & 0xFF00) >> 8);
return 0;
}
static int max98390_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
max98390->sysclk = freq;
return 0;
}
static const struct snd_soc_dai_ops max98390_dai_ops = {
.set_sysclk = max98390_dai_set_sysclk,
.set_fmt = max98390_dai_set_fmt,
.hw_params = max98390_dai_hw_params,
.set_tdm_slot = max98390_dai_tdm_slot,
};
static int max98390_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(max98390->regmap,
MAX98390_R203A_AMP_EN,
MAX98390_AMP_EN_MASK, 1);
regmap_update_bits(max98390->regmap,
MAX98390_R23FF_GLOBAL_EN,
MAX98390_GLOBAL_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(max98390->regmap,
MAX98390_R23FF_GLOBAL_EN,
MAX98390_GLOBAL_EN_MASK, 0);
regmap_update_bits(max98390->regmap,
MAX98390_R203A_AMP_EN,
MAX98390_AMP_EN_MASK, 0);
break;
}
return 0;
}
static const char * const max98390_switch_text[] = {
"Left", "Right", "LeftRight"};
static const char * const max98390_boost_voltage_text[] = {
"6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
"7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
"8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
"9.5V", "9.625V", "9.75V", "9.875V", "10V"
};
static SOC_ENUM_SINGLE_DECL(max98390_boost_voltage,
MAX98390_BOOST_CTRL0, 0,
max98390_boost_voltage_text);
static DECLARE_TLV_DB_SCALE(max98390_spk_tlv, 300, 300, 0);
static DECLARE_TLV_DB_SCALE(max98390_digital_tlv, -8000, 50, 0);
static const char * const max98390_current_limit_text[] = {
"0.00A", "0.50A", "1.00A", "1.05A", "1.10A", "1.15A", "1.20A", "1.25A",
"1.30A", "1.35A", "1.40A", "1.45A", "1.50A", "1.55A", "1.60A", "1.65A",
"1.70A", "1.75A", "1.80A", "1.85A", "1.90A", "1.95A", "2.00A", "2.05A",
"2.10A", "2.15A", "2.20A", "2.25A", "2.30A", "2.35A", "2.40A", "2.45A",
"2.50A", "2.55A", "2.60A", "2.65A", "2.70A", "2.75A", "2.80A", "2.85A",
"2.90A", "2.95A", "3.00A", "3.05A", "3.10A", "3.15A", "3.20A", "3.25A",
"3.30A", "3.35A", "3.40A", "3.45A", "3.50A", "3.55A", "3.60A", "3.65A",
"3.70A", "3.75A", "3.80A", "3.85A", "3.90A", "3.95A", "4.00A", "4.05A",
"4.10A"
};
static SOC_ENUM_SINGLE_DECL(max98390_current_limit,
MAX98390_BOOST_CTRL1, 0,
max98390_current_limit_text);
static int max98390_ref_rdc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
max98390->ref_rdc_value = ucontrol->value.integer.value[0];
regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
max98390->ref_rdc_value & 0x000000ff);
regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
(max98390->ref_rdc_value >> 8) & 0x000000ff);
regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
(max98390->ref_rdc_value >> 16) & 0x000000ff);
return 0;
}
static int max98390_ref_rdc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = max98390->ref_rdc_value;
return 0;
}
static int max98390_ambient_temp_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
max98390->ambient_temp_value = ucontrol->value.integer.value[0];
regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
(max98390->ambient_temp_value >> 8) & 0x000000ff);
regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
(max98390->ambient_temp_value) & 0x000000ff);
return 0;
}
static int max98390_ambient_temp_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = max98390->ambient_temp_value;
return 0;
}
static int max98390_adaptive_rdc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
dev_warn(component->dev, "Put adaptive rdc not supported\n");
return 0;
}
static int max98390_adaptive_rdc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int rdc, rdc0;
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE1, &rdc);
regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE0, &rdc0);
ucontrol->value.integer.value[0] = rdc0 | rdc << 8;
return 0;
}
static int max98390_dsm_calib_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
/* Do nothing */
return 0;
}
static int max98390_dsm_calib_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct max98390_priv *max98390 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
unsigned int rdc, rdc_cal_result, rdc_integer, rdc_factor, temp, val;
snd_soc_dapm_mutex_lock(dapm);
regmap_read(max98390->regmap, MAX98390_R23FF_GLOBAL_EN, &val);
if (!val) {
/* Enable the codec for the duration of calibration readout */
regmap_update_bits(max98390->regmap, MAX98390_R203A_AMP_EN,
MAX98390_AMP_EN_MASK, 1);
regmap_update_bits(max98390->regmap, MAX98390_R23FF_GLOBAL_EN,
MAX98390_GLOBAL_EN_MASK, 1);
}
regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE1, &rdc);
regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE0, &rdc_cal_result);
regmap_read(max98390->regmap, MAX98390_MEAS_ADC_CH2_READ, &temp);
if (!val) {
/* Disable the codec if it was disabled */
regmap_update_bits(max98390->regmap, MAX98390_R23FF_GLOBAL_EN,
MAX98390_GLOBAL_EN_MASK, 0);
regmap_update_bits(max98390->regmap, MAX98390_R203A_AMP_EN,
MAX98390_AMP_EN_MASK, 0);
}
snd_soc_dapm_mutex_unlock(dapm);
rdc_cal_result |= (rdc << 8) & 0x0000FFFF;
if (rdc_cal_result)
max98390->ref_rdc_value = 268435456U / rdc_cal_result;
max98390->ambient_temp_value = temp * 52 - 1188;
rdc_integer = rdc_cal_result * 937 / 65536;
rdc_factor = ((rdc_cal_result * 937 * 100) / 65536) - (rdc_integer * 100);
dev_info(component->dev,
"rdc resistance about %d.%02d ohm, reg=0x%X temp reg=0x%X\n",
rdc_integer, rdc_factor, rdc_cal_result, temp);
return 0;
}
static const struct snd_kcontrol_new max98390_snd_controls[] = {
SOC_SINGLE_TLV("Digital Volume", DSM_VOL_CTRL,
0, 184, 0,
max98390_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98390_R203D_SPK_GAIN,
0, 6, 0,
max98390_spk_tlv),
SOC_SINGLE("Ramp Up Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
MAX98390_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
MAX98390_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
SOC_SINGLE("Boost Clock Phase", MAX98390_BOOST_CTRL3,
MAX98390_BOOST_CLK_PHASE_CFG_SHIFT, 3, 0),
SOC_ENUM("Boost Output Voltage", max98390_boost_voltage),
SOC_ENUM("Current Limit", max98390_current_limit),
SOC_SINGLE_EXT("DSM Rdc", SND_SOC_NOPM, 0, 0xffffff, 0,
max98390_ref_rdc_get, max98390_ref_rdc_put),
SOC_SINGLE_EXT("DSM Ambient Temp", SND_SOC_NOPM, 0, 0xffff, 0,
max98390_ambient_temp_get, max98390_ambient_temp_put),
SOC_SINGLE_EXT("DSM Adaptive Rdc", SND_SOC_NOPM, 0, 0xffff, 0,
max98390_adaptive_rdc_get, max98390_adaptive_rdc_put),
SOC_SINGLE_EXT("DSM Calibration", SND_SOC_NOPM, 0, 1, 0,
max98390_dsm_calib_get, max98390_dsm_calib_put),
};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98390_PCM_CH_SRC_1,
MAX98390_PCM_RX_CH_SRC_SHIFT,
3, max98390_switch_text);
static const struct snd_kcontrol_new max98390_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_soc_dapm_widget max98390_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
SND_SOC_NOPM, 0, 0, max98390_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98390_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
};
static const struct snd_soc_dapm_route max98390_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
};
static bool max98390_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
case MAX98390_IRQ_CTRL ... MAX98390_WDOG_CTRL:
case MAX98390_MEAS_ADC_THERM_WARN_THRESH
... MAX98390_BROWNOUT_INFINITE_HOLD:
case MAX98390_BROWNOUT_LVL_HOLD ... DSMIG_DEBUZZER_THRESHOLD:
case DSM_VOL_ENA ... MAX98390_R24FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98390_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
case MAX98390_MEAS_ADC_CH0_READ ... MAX98390_MEAS_ADC_CH2_READ:
case MAX98390_PWR_GATE_STATUS ... MAX98390_BROWNOUT_STATUS:
case MAX98390_BROWNOUT_LOWEST_STATUS:
case MAX98390_ENV_TRACK_BOOST_VOUT_READ:
case DSM_STBASS_HPF_B0_BYTE0 ... DSM_DEBUZZER_ATTACK_TIME_BYTE2:
case THERMAL_RDC_RD_BACK_BYTE1 ... DSMIG_DEBUZZER_THRESHOLD:
case DSM_THERMAL_GAIN ... DSM_WBDRC_GAIN:
return true;
default:
return false;
}
}
#define MAX98390_RATES SNDRV_PCM_RATE_8000_48000
#define MAX98390_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver max98390_dai[] = {
{
.name = "max98390-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98390_RATES,
.formats = MAX98390_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98390_RATES,
.formats = MAX98390_FORMATS,
},
.ops = &max98390_dai_ops,
}
};
static int max98390_dsm_init(struct snd_soc_component *component)
{
int ret;
int param_size, param_start_addr;
char filename[128];
const char *vendor, *product;
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
const struct firmware *fw;
char *dsm_param;
vendor = dmi_get_system_info(DMI_SYS_VENDOR);
product = dmi_get_system_info(DMI_PRODUCT_NAME);
if (!strcmp(max98390->dsm_param_name, "default")) {
if (vendor && product) {
snprintf(filename, sizeof(filename),
"dsm_param_%s_%s.bin", vendor, product);
} else {
sprintf(filename, "dsm_param.bin");
}
} else {
snprintf(filename, sizeof(filename), "%s",
max98390->dsm_param_name);
}
ret = request_firmware(&fw, filename, component->dev);
if (ret) {
ret = request_firmware(&fw, "dsm_param.bin", component->dev);
if (ret) {
ret = request_firmware(&fw, "dsmparam.bin",
component->dev);
if (ret)
goto err;
}
}
dev_dbg(component->dev,
"max98390: param fw size %zd\n",
fw->size);
if (fw->size < MAX98390_DSM_PARAM_MIN_SIZE) {
dev_err(component->dev,
"param fw is invalid.\n");
ret = -EINVAL;
goto err_alloc;
}
dsm_param = (char *)fw->data;
param_start_addr = (dsm_param[0] & 0xff) | (dsm_param[1] & 0xff) << 8;
param_size = (dsm_param[2] & 0xff) | (dsm_param[3] & 0xff) << 8;
if (param_size > MAX98390_DSM_PARAM_MAX_SIZE ||
param_start_addr < MAX98390_IRQ_CTRL ||
fw->size < param_size + MAX98390_DSM_PAYLOAD_OFFSET) {
dev_err(component->dev,
"param fw is invalid.\n");
ret = -EINVAL;
goto err_alloc;
}
regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x80);
dsm_param += MAX98390_DSM_PAYLOAD_OFFSET;
regmap_bulk_write(max98390->regmap, param_start_addr,
dsm_param, param_size);
regmap_write(max98390->regmap, MAX98390_R23E1_DSP_GLOBAL_EN, 0x01);
err_alloc:
release_firmware(fw);
err:
return ret;
}
static void max98390_init_regs(struct snd_soc_component *component)
{
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
regmap_write(max98390->regmap, MAX98390_CLK_MON, 0x6f);
regmap_write(max98390->regmap, MAX98390_DAT_MON, 0x00);
regmap_write(max98390->regmap, MAX98390_PWR_GATE_CTL, 0x00);
regmap_write(max98390->regmap, MAX98390_PCM_RX_EN_A, 0x03);
regmap_write(max98390->regmap, MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0e);
regmap_write(max98390->regmap, MAX98390_BOOST_BYPASS1, 0x46);
regmap_write(max98390->regmap, MAX98390_FET_SCALING3, 0x03);
/* voltage, current slot configuration */
regmap_write(max98390->regmap,
MAX98390_PCM_CH_SRC_2,
(max98390->i_l_slot << 4 |
max98390->v_l_slot)&0xFF);
if (max98390->v_l_slot < 8) {
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_HIZ_CTRL_A,
1 << max98390->v_l_slot, 0);
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_EN_A,
1 << max98390->v_l_slot,
1 << max98390->v_l_slot);
} else {
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_HIZ_CTRL_B,
1 << (max98390->v_l_slot - 8), 0);
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_EN_B,
1 << (max98390->v_l_slot - 8),
1 << (max98390->v_l_slot - 8));
}
if (max98390->i_l_slot < 8) {
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_HIZ_CTRL_A,
1 << max98390->i_l_slot, 0);
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_EN_A,
1 << max98390->i_l_slot,
1 << max98390->i_l_slot);
} else {
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_HIZ_CTRL_B,
1 << (max98390->i_l_slot - 8), 0);
regmap_update_bits(max98390->regmap,
MAX98390_PCM_TX_EN_B,
1 << (max98390->i_l_slot - 8),
1 << (max98390->i_l_slot - 8));
}
}
static int max98390_probe(struct snd_soc_component *component)
{
struct max98390_priv *max98390 =
snd_soc_component_get_drvdata(component);
regmap_write(max98390->regmap, MAX98390_SOFTWARE_RESET, 0x01);
/* Sleep reset settle time */
msleep(20);
/* Amp init setting */
max98390_init_regs(component);
/* Update dsm bin param */
max98390_dsm_init(component);
/* Dsm Setting */
if (max98390->ref_rdc_value) {
regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
max98390->ref_rdc_value & 0x000000ff);
regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
(max98390->ref_rdc_value >> 8) & 0x000000ff);
regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
(max98390->ref_rdc_value >> 16) & 0x000000ff);
}
if (max98390->ambient_temp_value) {
regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
(max98390->ambient_temp_value >> 8) & 0x000000ff);
regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
(max98390->ambient_temp_value) & 0x000000ff);
}
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int max98390_suspend(struct device *dev)
{
struct max98390_priv *max98390 = dev_get_drvdata(dev);
dev_dbg(dev, "%s:Enter\n", __func__);
regcache_cache_only(max98390->regmap, true);
regcache_mark_dirty(max98390->regmap);
return 0;
}
static int max98390_resume(struct device *dev)
{
struct max98390_priv *max98390 = dev_get_drvdata(dev);
dev_dbg(dev, "%s:Enter\n", __func__);
regcache_cache_only(max98390->regmap, false);
regcache_sync(max98390->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98390_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98390_suspend, max98390_resume)
};
static const struct snd_soc_component_driver soc_codec_dev_max98390 = {
.probe = max98390_probe,
.controls = max98390_snd_controls,
.num_controls = ARRAY_SIZE(max98390_snd_controls),
.dapm_widgets = max98390_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98390_dapm_widgets),
.dapm_routes = max98390_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98390_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config max98390_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98390_R24FF_REV_ID,
.reg_defaults = max98390_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(max98390_reg_defaults),
.readable_reg = max98390_readable_register,
.volatile_reg = max98390_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98390_slot_config(struct i2c_client *i2c,
struct max98390_priv *max98390)
{
int value;
struct device *dev = &i2c->dev;
if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
max98390->v_l_slot = value & 0xF;
else
max98390->v_l_slot = 0;
if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
max98390->i_l_slot = value & 0xF;
else
max98390->i_l_slot = 1;
}
static int max98390_i2c_probe(struct i2c_client *i2c)
{
int ret = 0;
int reg = 0;
struct max98390_priv *max98390 = NULL;
struct i2c_adapter *adapter = i2c->adapter;
struct gpio_desc *reset_gpio;
ret = i2c_check_functionality(adapter,
I2C_FUNC_SMBUS_BYTE
| I2C_FUNC_SMBUS_BYTE_DATA);
if (!ret) {
dev_err(&i2c->dev, "I2C check functionality failed\n");
return -ENXIO;
}
max98390 = devm_kzalloc(&i2c->dev, sizeof(*max98390), GFP_KERNEL);
if (!max98390) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98390);
ret = device_property_read_u32(&i2c->dev, "maxim,temperature_calib",
&max98390->ambient_temp_value);
if (ret) {
dev_info(&i2c->dev,
"no optional property 'temperature_calib' found, default:\n");
}
ret = device_property_read_u32(&i2c->dev, "maxim,r0_calib",
&max98390->ref_rdc_value);
if (ret) {
dev_info(&i2c->dev,
"no optional property 'r0_calib' found, default:\n");
}
dev_info(&i2c->dev,
"%s: r0_calib: 0x%x,temperature_calib: 0x%x",
__func__, max98390->ref_rdc_value,
max98390->ambient_temp_value);
ret = device_property_read_string(&i2c->dev, "maxim,dsm_param_name",
&max98390->dsm_param_name);
if (ret)
max98390->dsm_param_name = "default";
/* voltage/current slot configuration */
max98390_slot_config(i2c, max98390);
/* regmap initialization */
max98390->regmap = devm_regmap_init_i2c(i2c, &max98390_regmap);
if (IS_ERR(max98390->regmap)) {
ret = PTR_ERR(max98390->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
reset_gpio = devm_gpiod_get_optional(&i2c->dev,
"reset", GPIOD_OUT_HIGH);
/* Power on device */
if (reset_gpio) {
usleep_range(1000, 2000);
/* bring out of reset */
gpiod_set_value_cansleep(reset_gpio, 0);
usleep_range(1000, 2000);
}
/* Check Revision ID */
ret = regmap_read(max98390->regmap,
MAX98390_R24FF_REV_ID, ®);
if (ret) {
dev_err(&i2c->dev,
"ret=%d, Failed to read: 0x%02X\n",
ret, MAX98390_R24FF_REV_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98390 revisionID: 0x%02X\n", reg);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_max98390,
max98390_dai, ARRAY_SIZE(max98390_dai));
return ret;
}
static const struct i2c_device_id max98390_i2c_id[] = {
{ "max98390", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, max98390_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98390_of_match[] = {
{ .compatible = "maxim,max98390", },
{}
};
MODULE_DEVICE_TABLE(of, max98390_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98390_acpi_match[] = {
{ "MX98390", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98390_acpi_match);
#endif
static struct i2c_driver max98390_i2c_driver = {
.driver = {
.name = "max98390",
.of_match_table = of_match_ptr(max98390_of_match),
.acpi_match_table = ACPI_PTR(max98390_acpi_match),
.pm = &max98390_pm,
},
.probe = max98390_i2c_probe,
.id_table = max98390_i2c_id,
};
module_i2c_driver(max98390_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98390 driver");
MODULE_AUTHOR("Steve Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98390.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8985.c -- WM8985 / WM8758 ALSA SoC Audio driver
*
* Copyright 2010 Wolfson Microelectronics plc
* Author: Dimitris Papastamos <[email protected]>
*
* WM8758 support:
* Copyright: 2016 Barix AG
* Author: Petr Kulhavy <[email protected]>
*
* TODO:
* o Add OUT3/OUT4 mixer controls.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8985.h"
#define WM8985_NUM_SUPPLIES 4
static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
"DCVDD",
"DBVDD",
"AVDD1",
"AVDD2"
};
enum wm8985_type {
WM8985,
WM8758,
};
static const struct reg_default wm8985_reg_defaults[] = {
{ 1, 0x0000 }, /* R1 - Power management 1 */
{ 2, 0x0000 }, /* R2 - Power management 2 */
{ 3, 0x0000 }, /* R3 - Power management 3 */
{ 4, 0x0050 }, /* R4 - Audio Interface */
{ 5, 0x0000 }, /* R5 - Companding control */
{ 6, 0x0140 }, /* R6 - Clock Gen control */
{ 7, 0x0000 }, /* R7 - Additional control */
{ 8, 0x0000 }, /* R8 - GPIO Control */
{ 9, 0x0000 }, /* R9 - Jack Detect Control 1 */
{ 10, 0x0000 }, /* R10 - DAC Control */
{ 11, 0x00FF }, /* R11 - Left DAC digital Vol */
{ 12, 0x00FF }, /* R12 - Right DAC digital vol */
{ 13, 0x0000 }, /* R13 - Jack Detect Control 2 */
{ 14, 0x0100 }, /* R14 - ADC Control */
{ 15, 0x00FF }, /* R15 - Left ADC Digital Vol */
{ 16, 0x00FF }, /* R16 - Right ADC Digital Vol */
{ 18, 0x012C }, /* R18 - EQ1 - low shelf */
{ 19, 0x002C }, /* R19 - EQ2 - peak 1 */
{ 20, 0x002C }, /* R20 - EQ3 - peak 2 */
{ 21, 0x002C }, /* R21 - EQ4 - peak 3 */
{ 22, 0x002C }, /* R22 - EQ5 - high shelf */
{ 24, 0x0032 }, /* R24 - DAC Limiter 1 */
{ 25, 0x0000 }, /* R25 - DAC Limiter 2 */
{ 27, 0x0000 }, /* R27 - Notch Filter 1 */
{ 28, 0x0000 }, /* R28 - Notch Filter 2 */
{ 29, 0x0000 }, /* R29 - Notch Filter 3 */
{ 30, 0x0000 }, /* R30 - Notch Filter 4 */
{ 32, 0x0038 }, /* R32 - ALC control 1 */
{ 33, 0x000B }, /* R33 - ALC control 2 */
{ 34, 0x0032 }, /* R34 - ALC control 3 */
{ 35, 0x0000 }, /* R35 - Noise Gate */
{ 36, 0x0008 }, /* R36 - PLL N */
{ 37, 0x000C }, /* R37 - PLL K 1 */
{ 38, 0x0093 }, /* R38 - PLL K 2 */
{ 39, 0x00E9 }, /* R39 - PLL K 3 */
{ 41, 0x0000 }, /* R41 - 3D control */
{ 42, 0x0000 }, /* R42 - OUT4 to ADC */
{ 43, 0x0000 }, /* R43 - Beep control */
{ 44, 0x0033 }, /* R44 - Input ctrl */
{ 45, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
{ 46, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
{ 47, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
{ 48, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
{ 49, 0x0002 }, /* R49 - Output ctrl */
{ 50, 0x0001 }, /* R50 - Left mixer ctrl */
{ 51, 0x0001 }, /* R51 - Right mixer ctrl */
{ 52, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
{ 53, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
{ 54, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
{ 55, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
{ 56, 0x0001 }, /* R56 - OUT3 mixer ctrl */
{ 57, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
{ 60, 0x0004 }, /* R60 - OUTPUT ctrl */
{ 61, 0x0000 }, /* R61 - BIAS CTRL */
};
static bool wm8985_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8985_SOFTWARE_RESET:
case WM8985_POWER_MANAGEMENT_1:
case WM8985_POWER_MANAGEMENT_2:
case WM8985_POWER_MANAGEMENT_3:
case WM8985_AUDIO_INTERFACE:
case WM8985_COMPANDING_CONTROL:
case WM8985_CLOCK_GEN_CONTROL:
case WM8985_ADDITIONAL_CONTROL:
case WM8985_GPIO_CONTROL:
case WM8985_JACK_DETECT_CONTROL_1:
case WM8985_DAC_CONTROL:
case WM8985_LEFT_DAC_DIGITAL_VOL:
case WM8985_RIGHT_DAC_DIGITAL_VOL:
case WM8985_JACK_DETECT_CONTROL_2:
case WM8985_ADC_CONTROL:
case WM8985_LEFT_ADC_DIGITAL_VOL:
case WM8985_RIGHT_ADC_DIGITAL_VOL:
case WM8985_EQ1_LOW_SHELF:
case WM8985_EQ2_PEAK_1:
case WM8985_EQ3_PEAK_2:
case WM8985_EQ4_PEAK_3:
case WM8985_EQ5_HIGH_SHELF:
case WM8985_DAC_LIMITER_1:
case WM8985_DAC_LIMITER_2:
case WM8985_NOTCH_FILTER_1:
case WM8985_NOTCH_FILTER_2:
case WM8985_NOTCH_FILTER_3:
case WM8985_NOTCH_FILTER_4:
case WM8985_ALC_CONTROL_1:
case WM8985_ALC_CONTROL_2:
case WM8985_ALC_CONTROL_3:
case WM8985_NOISE_GATE:
case WM8985_PLL_N:
case WM8985_PLL_K_1:
case WM8985_PLL_K_2:
case WM8985_PLL_K_3:
case WM8985_3D_CONTROL:
case WM8985_OUT4_TO_ADC:
case WM8985_BEEP_CONTROL:
case WM8985_INPUT_CTRL:
case WM8985_LEFT_INP_PGA_GAIN_CTRL:
case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
case WM8985_LEFT_ADC_BOOST_CTRL:
case WM8985_RIGHT_ADC_BOOST_CTRL:
case WM8985_OUTPUT_CTRL0:
case WM8985_LEFT_MIXER_CTRL:
case WM8985_RIGHT_MIXER_CTRL:
case WM8985_LOUT1_HP_VOLUME_CTRL:
case WM8985_ROUT1_HP_VOLUME_CTRL:
case WM8985_LOUT2_SPK_VOLUME_CTRL:
case WM8985_ROUT2_SPK_VOLUME_CTRL:
case WM8985_OUT3_MIXER_CTRL:
case WM8985_OUT4_MONO_MIX_CTRL:
case WM8985_OUTPUT_CTRL1:
case WM8985_BIAS_CTRL:
return true;
default:
return false;
}
}
/*
* latch bit 8 of these registers to ensure instant
* volume updates
*/
static const int volume_update_regs[] = {
WM8985_LEFT_DAC_DIGITAL_VOL,
WM8985_RIGHT_DAC_DIGITAL_VOL,
WM8985_LEFT_ADC_DIGITAL_VOL,
WM8985_RIGHT_ADC_DIGITAL_VOL,
WM8985_LOUT2_SPK_VOLUME_CTRL,
WM8985_ROUT2_SPK_VOLUME_CTRL,
WM8985_LOUT1_HP_VOLUME_CTRL,
WM8985_ROUT1_HP_VOLUME_CTRL,
WM8985_LEFT_INP_PGA_GAIN_CTRL,
WM8985_RIGHT_INP_PGA_GAIN_CTRL
};
struct wm8985_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
enum wm8985_type dev_type;
unsigned int sysclk;
unsigned int bclk;
};
static const struct {
int div;
int ratio;
} fs_ratios[] = {
{ 10, 128 },
{ 15, 192 },
{ 20, 256 },
{ 30, 384 },
{ 40, 512 },
{ 60, 768 },
{ 80, 1024 },
{ 120, 1536 }
};
static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
static const int bclk_divs[] = {
1, 2, 4, 8, 16, 32
};
static int eqmode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static int eqmode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
static const char *alc_mode_text[] = { "ALC", "Limiter" };
static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
static const char *filter_mode_text[] = { "Audio", "Application" };
static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
filter_mode_text);
static const char *eq_bw_text[] = { "Narrow", "Wide" };
static const char *eqmode_text[] = { "Capture", "Playback" };
static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
static const char *eq1_cutoff_text[] = {
"80Hz", "105Hz", "135Hz", "175Hz"
};
static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
eq1_cutoff_text);
static const char *eq2_cutoff_text[] = {
"230Hz", "300Hz", "385Hz", "500Hz"
};
static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
static const char *eq3_cutoff_text[] = {
"650Hz", "850Hz", "1.1kHz", "1.4kHz"
};
static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
eq3_cutoff_text);
static const char *eq4_cutoff_text[] = {
"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
};
static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
static const char *eq5_cutoff_text[] = {
"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
};
static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
eq5_cutoff_text);
static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
static const char *depth_3d_text[] = {
"Off",
"6.67%",
"13.3%",
"20%",
"26.7%",
"33.3%",
"40%",
"46.6%",
"53.3%",
"60%",
"66.7%",
"73.3%",
"80%",
"86.7%",
"93.3%",
"100%"
};
static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
static const struct snd_kcontrol_new wm8985_common_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
0, 1, 0),
SOC_ENUM("ALC Capture Function", alc_sel),
SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
3, 7, 0, alc_max_tlv),
SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
0, 7, 0, alc_min_tlv),
SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
0, 15, 0, alc_tar_tlv),
SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
SOC_ENUM("ALC Mode", alc_mode),
SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
3, 1, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
0, 7, 1),
SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
8, 1, 0, pga_boost_tlv),
SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
4, 7, 1, lim_thresh_tlv),
SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
0, 12, 0, lim_boost_tlv),
SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
SOC_ENUM("High Pass Filter Mode", filter_mode),
SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
bypass_tlv),
SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ2 Bandwidth", eq2_bw),
SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ3 Bandwidth", eq3_bw),
SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ4 Bandwidth", eq4_bw),
SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
SOC_ENUM("3D Depth", depth_3d),
};
static const struct snd_kcontrol_new wm8985_specific_snd_controls[] = {
SOC_DOUBLE_R_TLV("Aux Bypass Volume",
WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
aux_tlv),
SOC_ENUM("Speaker Mode", speaker_mode)
};
static const struct snd_kcontrol_new left_out_mixer[] = {
SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
/* --- WM8985 only --- */
SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
};
static const struct snd_kcontrol_new right_out_mixer[] = {
SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
/* --- WM8985 only --- */
SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
};
static const struct snd_kcontrol_new left_input_mixer[] = {
SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
};
static const struct snd_kcontrol_new right_input_mixer[] = {
SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
};
static const struct snd_kcontrol_new left_boost_mixer[] = {
SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
4, 7, 0, boost_tlv),
/* --- WM8985 only --- */
SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
0, 7, 0, boost_tlv)
};
static const struct snd_kcontrol_new right_boost_mixer[] = {
SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
4, 7, 0, boost_tlv),
/* --- WM8985 only --- */
SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
0, 7, 0, boost_tlv)
};
static const struct snd_soc_dapm_widget wm8985_common_dapm_widgets[] = {
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
0, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
1, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
0, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
1, 0),
SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
6, 1, NULL, 0),
SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
8, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
6, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
NULL, 0),
SND_SOC_DAPM_INPUT("LIN"),
SND_SOC_DAPM_INPUT("LIP"),
SND_SOC_DAPM_INPUT("RIN"),
SND_SOC_DAPM_INPUT("RIP"),
SND_SOC_DAPM_INPUT("L2"),
SND_SOC_DAPM_INPUT("R2"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR")
};
static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
SND_SOC_DAPM_INPUT("AUXL"),
SND_SOC_DAPM_INPUT("AUXR"),
};
static const struct snd_soc_dapm_widget wm8758_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
2, 0, left_out_mixer,
ARRAY_SIZE(left_out_mixer) - 1),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
3, 0, right_out_mixer,
ARRAY_SIZE(right_out_mixer) - 1),
SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
4, 0, left_boost_mixer,
ARRAY_SIZE(left_boost_mixer) - 1),
SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
5, 0, right_boost_mixer,
ARRAY_SIZE(right_boost_mixer) - 1),
};
static const struct snd_soc_dapm_route wm8985_common_dapm_routes[] = {
{ "Right Output Mixer", "PCM Switch", "Right DAC" },
{ "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
{ "Left Output Mixer", "PCM Switch", "Left DAC" },
{ "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
{ "Right Headphone Out", NULL, "Right Output Mixer" },
{ "HPR", NULL, "Right Headphone Out" },
{ "Left Headphone Out", NULL, "Left Output Mixer" },
{ "HPL", NULL, "Left Headphone Out" },
{ "Right Speaker Out", NULL, "Right Output Mixer" },
{ "SPKR", NULL, "Right Speaker Out" },
{ "Left Speaker Out", NULL, "Left Output Mixer" },
{ "SPKL", NULL, "Left Speaker Out" },
{ "Right ADC", NULL, "Right Boost Mixer" },
{ "Right Boost Mixer", NULL, "Right Capture PGA" },
{ "Right Boost Mixer", "R2 Volume", "R2" },
{ "Left ADC", NULL, "Left Boost Mixer" },
{ "Left Boost Mixer", NULL, "Left Capture PGA" },
{ "Left Boost Mixer", "L2 Volume", "L2" },
{ "Right Capture PGA", NULL, "Right Input Mixer" },
{ "Left Capture PGA", NULL, "Left Input Mixer" },
{ "Right Input Mixer", "R2 Switch", "R2" },
{ "Right Input Mixer", "MicN Switch", "RIN" },
{ "Right Input Mixer", "MicP Switch", "RIP" },
{ "Left Input Mixer", "L2 Switch", "L2" },
{ "Left Input Mixer", "MicN Switch", "LIN" },
{ "Left Input Mixer", "MicP Switch", "LIP" },
};
static const struct snd_soc_dapm_route wm8985_aux_dapm_routes[] = {
{ "Right Output Mixer", "Aux Switch", "AUXR" },
{ "Left Output Mixer", "Aux Switch", "AUXL" },
{ "Right Boost Mixer", "AUXR Volume", "AUXR" },
{ "Left Boost Mixer", "AUXL Volume", "AUXL" },
};
static int wm8985_add_widgets(struct snd_soc_component *component)
{
struct wm8985_priv *wm8985 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
switch (wm8985->dev_type) {
case WM8758:
snd_soc_dapm_new_controls(dapm, wm8758_dapm_widgets,
ARRAY_SIZE(wm8758_dapm_widgets));
break;
case WM8985:
snd_soc_add_component_controls(component, wm8985_specific_snd_controls,
ARRAY_SIZE(wm8985_specific_snd_controls));
snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
ARRAY_SIZE(wm8985_dapm_widgets));
snd_soc_dapm_add_routes(dapm, wm8985_aux_dapm_routes,
ARRAY_SIZE(wm8985_aux_dapm_routes));
break;
}
return 0;
}
static int eqmode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int reg;
reg = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
if (reg & WM8985_EQ3DMODE)
ucontrol->value.enumerated.item[0] = 1;
else
ucontrol->value.enumerated.item[0] = 0;
return 0;
}
static int eqmode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
unsigned int regpwr2, regpwr3;
unsigned int reg_eq;
if (ucontrol->value.enumerated.item[0] != 0
&& ucontrol->value.enumerated.item[0] != 1)
return -EINVAL;
reg_eq = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
case 0:
if (!ucontrol->value.enumerated.item[0])
return 0;
break;
case 1:
if (ucontrol->value.enumerated.item[0])
return 0;
break;
}
regpwr2 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_2);
regpwr3 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_3);
/* disable the DACs and ADCs */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_2,
WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_3,
WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
WM8985_M128ENB_MASK, WM8985_M128ENB);
/* set the desired eqmode */
snd_soc_component_update_bits(component, WM8985_EQ1_LOW_SHELF,
WM8985_EQ3DMODE_MASK,
ucontrol->value.enumerated.item[0]
<< WM8985_EQ3DMODE_SHIFT);
/* restore DAC/ADC configuration */
snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, regpwr2);
snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, regpwr3);
return 0;
}
static int wm8985_reset(struct snd_soc_component *component)
{
return snd_soc_component_write(component, WM8985_SOFTWARE_RESET, 0x0);
}
static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
return snd_soc_component_update_bits(component, WM8985_DAC_CONTROL,
WM8985_SOFTMUTE_MASK,
!!mute << WM8985_SOFTMUTE_SHIFT);
}
static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component;
u16 format, master, bcp, lrp;
component = dai->component;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format = 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = 0x1;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
format = 0x3;
break;
default:
dev_err(dai->dev, "Unknown dai format\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
master = 0;
break;
default:
dev_err(dai->dev, "Unknown master/slave configuration\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
WM8985_MS_MASK, master << WM8985_MS_SHIFT);
/* frame inversion is not valid for dsp modes */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
case SND_SOC_DAIFMT_NB_IF:
return -EINVAL;
default:
break;
}
break;
default:
break;
}
bcp = lrp = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
bcp = lrp = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
bcp = 1;
break;
case SND_SOC_DAIFMT_NB_IF:
lrp = 1;
break;
default:
dev_err(dai->dev, "Unknown polarity configuration\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
return 0;
}
static int wm8985_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int i;
struct snd_soc_component *component;
struct wm8985_priv *wm8985;
u16 blen, srate_idx;
unsigned int tmp;
int srate_best;
component = dai->component;
wm8985 = snd_soc_component_get_drvdata(component);
wm8985->bclk = snd_soc_params_to_bclk(params);
if ((int)wm8985->bclk < 0)
return wm8985->bclk;
switch (params_width(params)) {
case 16:
blen = 0x0;
break;
case 20:
blen = 0x1;
break;
case 24:
blen = 0x2;
break;
case 32:
blen = 0x3;
break;
default:
dev_err(dai->dev, "Unsupported word length %u\n",
params_width(params));
return -EINVAL;
}
snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
/*
* match to the nearest possible sample rate and rely
* on the array index to configure the SR register
*/
srate_idx = 0;
srate_best = abs(srates[0] - params_rate(params));
for (i = 1; i < ARRAY_SIZE(srates); ++i) {
if (abs(srates[i] - params_rate(params)) >= srate_best)
continue;
srate_idx = i;
srate_best = abs(srates[i] - params_rate(params));
}
dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
if (wm8985->sysclk / params_rate(params)
== fs_ratios[i].ratio)
break;
}
if (i == ARRAY_SIZE(fs_ratios)) {
dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
wm8985->sysclk, params_rate(params));
return -EINVAL;
}
dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
/* select the appropriate bclk divider */
tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
if (wm8985->bclk == tmp / bclk_divs[i])
break;
}
if (i == ARRAY_SIZE(bclk_divs)) {
dev_err(dai->dev, "No matching BCLK divider found\n");
return -EINVAL;
}
dev_dbg(dai->dev, "BCLK div = %d\n", i);
snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
return 0;
}
struct pll_div {
u32 div2:1;
u32 n:4;
u32 k:24;
};
#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
static int pll_factors(struct pll_div *pll_div, unsigned int target,
unsigned int source)
{
u64 Kpart;
unsigned long int K, Ndiv, Nmod;
pll_div->div2 = 0;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->div2 = 1;
Ndiv = target / source;
}
if (Ndiv < 6 || Ndiv > 12) {
printk(KERN_ERR "%s: WM8985 N value is not within"
" the recommended range: %lu\n", __func__, Ndiv);
return -EINVAL;
}
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (u64)Nmod;
do_div(Kpart, source);
K = Kpart & 0xffffffff;
if ((K % 10) >= 5)
K += 5;
K /= 10;
pll_div->k = K;
return 0;
}
static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
int ret;
struct snd_soc_component *component;
struct pll_div pll_div;
component = dai->component;
if (!freq_in || !freq_out) {
/* disable the PLL */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_PLLEN_MASK, 0);
} else {
ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
if (ret)
return ret;
/* set PLLN and PRESCALE */
snd_soc_component_write(component, WM8985_PLL_N,
(pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
| pll_div.n);
/* set PLLK */
snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff);
snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18));
/* set the source of the clock to be the PLL */
snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
WM8985_CLKSEL_MASK, WM8985_CLKSEL);
/* enable the PLL */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_PLLEN_MASK, WM8985_PLLEN);
}
return 0;
}
static int wm8985_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component;
struct wm8985_priv *wm8985;
component = dai->component;
wm8985 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case WM8985_CLKSRC_MCLK:
snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
WM8985_CLKSEL_MASK, 0);
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_PLLEN_MASK, 0);
break;
case WM8985_CLKSRC_PLL:
snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
WM8985_CLKSEL_MASK, WM8985_CLKSEL);
break;
default:
dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
return -EINVAL;
}
wm8985->sysclk = freq;
return 0;
}
static int wm8985_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
int ret;
struct wm8985_priv *wm8985;
wm8985 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
/* VMID at 75k */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_VMIDSEL_MASK,
1 << WM8985_VMIDSEL_SHIFT);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
wm8985->supplies);
if (ret) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
regcache_sync(wm8985->regmap);
/* enable anti-pop features */
snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
WM8985_POBCTRL_MASK,
WM8985_POBCTRL);
/* enable thermal shutdown */
snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
WM8985_TSDEN_MASK, WM8985_TSDEN);
snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
WM8985_TSOPCTRL_MASK,
WM8985_TSOPCTRL);
/* enable BIASEN */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_BIASEN_MASK, WM8985_BIASEN);
/* VMID at 75k */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_VMIDSEL_MASK,
1 << WM8985_VMIDSEL_SHIFT);
msleep(500);
/* disable anti-pop features */
snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
WM8985_POBCTRL_MASK, 0);
}
/* VMID at 300k */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_VMIDSEL_MASK,
2 << WM8985_VMIDSEL_SHIFT);
break;
case SND_SOC_BIAS_OFF:
/* disable thermal shutdown */
snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
WM8985_TSOPCTRL_MASK, 0);
snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
WM8985_TSDEN_MASK, 0);
/* disable VMIDSEL and BIASEN */
snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
0);
snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_1, 0);
snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, 0);
snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, 0);
regcache_mark_dirty(wm8985->regmap);
regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
wm8985->supplies);
break;
}
return 0;
}
static int wm8985_probe(struct snd_soc_component *component)
{
size_t i;
struct wm8985_priv *wm8985;
int ret;
wm8985 = snd_soc_component_get_drvdata(component);
for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
wm8985->supplies[i].supply = wm8985_supply_names[i];
ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8985->supplies),
wm8985->supplies);
if (ret) {
dev_err(component->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
wm8985->supplies);
if (ret) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = wm8985_reset(component);
if (ret < 0) {
dev_err(component->dev, "Failed to issue reset: %d\n", ret);
goto err_reg_enable;
}
/* latch volume update bits */
for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
snd_soc_component_update_bits(component, volume_update_regs[i],
0x100, 0x100);
/* enable BIASCUT */
snd_soc_component_update_bits(component, WM8985_BIAS_CTRL, WM8985_BIASCUT,
WM8985_BIASCUT);
wm8985_add_widgets(component);
return 0;
err_reg_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
return ret;
}
static const struct snd_soc_dai_ops wm8985_dai_ops = {
.mute_stream = wm8985_dac_mute,
.hw_params = wm8985_hw_params,
.set_fmt = wm8985_set_fmt,
.set_sysclk = wm8985_set_sysclk,
.set_pll = wm8985_set_pll,
.no_capture_mute = 1,
};
#define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver wm8985_dai = {
.name = "wm8985-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8985_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = WM8985_FORMATS,
},
.ops = &wm8985_dai_ops,
.symmetric_rate = 1
};
static const struct snd_soc_component_driver soc_component_dev_wm8985 = {
.probe = wm8985_probe,
.set_bias_level = wm8985_set_bias_level,
.controls = wm8985_common_snd_controls,
.num_controls = ARRAY_SIZE(wm8985_common_snd_controls),
.dapm_widgets = wm8985_common_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8985_common_dapm_widgets),
.dapm_routes = wm8985_common_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(wm8985_common_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8985_regmap = {
.reg_bits = 7,
.val_bits = 9,
.max_register = WM8985_MAX_REGISTER,
.writeable_reg = wm8985_writeable,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8985_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
};
#if defined(CONFIG_SPI_MASTER)
static int wm8985_spi_probe(struct spi_device *spi)
{
struct wm8985_priv *wm8985;
int ret;
wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
if (!wm8985)
return -ENOMEM;
spi_set_drvdata(spi, wm8985);
wm8985->dev_type = WM8985;
wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
if (IS_ERR(wm8985->regmap)) {
ret = PTR_ERR(wm8985->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = devm_snd_soc_register_component(&spi->dev,
&soc_component_dev_wm8985, &wm8985_dai, 1);
return ret;
}
static struct spi_driver wm8985_spi_driver = {
.driver = {
.name = "wm8985",
},
.probe = wm8985_spi_probe,
};
#endif
#if IS_ENABLED(CONFIG_I2C)
static const struct i2c_device_id wm8985_i2c_id[];
static int wm8985_i2c_probe(struct i2c_client *i2c)
{
struct wm8985_priv *wm8985;
const struct i2c_device_id *id = i2c_match_id(wm8985_i2c_id, i2c);
int ret;
wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
if (!wm8985)
return -ENOMEM;
i2c_set_clientdata(i2c, wm8985);
wm8985->dev_type = id->driver_data;
wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
if (IS_ERR(wm8985->regmap)) {
ret = PTR_ERR(wm8985->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8985, &wm8985_dai, 1);
return ret;
}
static const struct i2c_device_id wm8985_i2c_id[] = {
{ "wm8985", WM8985 },
{ "wm8758", WM8758 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
static struct i2c_driver wm8985_i2c_driver = {
.driver = {
.name = "wm8985",
},
.probe = wm8985_i2c_probe,
.id_table = wm8985_i2c_id
};
#endif
static int __init wm8985_modinit(void)
{
int ret = 0;
#if IS_ENABLED(CONFIG_I2C)
ret = i2c_add_driver(&wm8985_i2c_driver);
if (ret) {
printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8985_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
ret);
}
#endif
return ret;
}
module_init(wm8985_modinit);
static void __exit wm8985_exit(void)
{
#if IS_ENABLED(CONFIG_I2C)
i2c_del_driver(&wm8985_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8985_spi_driver);
#endif
}
module_exit(wm8985_exit);
MODULE_DESCRIPTION("ASoC WM8985 / WM8758 driver");
MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8985.c |
// SPDX-License-Identifier: GPL-2.0
//
// CS42L43 CODEC driver jack handling
//
// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/build_bug.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <linux/jiffies.h>
#include <linux/mfd/cs42l43.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <sound/control.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-component.h>
#include <sound/soc.h>
#include "cs42l43.h"
static const unsigned int cs42l43_accdet_us[] = {
20, 100, 1000, 10000, 50000, 75000, 100000, 200000
};
static const unsigned int cs42l43_accdet_db_ms[] = {
0, 125, 250, 500, 750, 1000, 1250, 1500
};
static const unsigned int cs42l43_accdet_ramp_ms[] = { 10, 40, 90, 170 };
static const unsigned int cs42l43_accdet_bias_sense[] = {
14, 23, 41, 50, 60, 68, 86, 95, 0,
};
static int cs42l43_find_index(struct cs42l43_codec *priv, const char * const prop,
unsigned int defval, unsigned int *val,
const unsigned int *values, const int nvalues)
{
struct cs42l43 *cs42l43 = priv->core;
int i, ret;
ret = device_property_read_u32(cs42l43->dev, prop, &defval);
if (ret != -EINVAL && ret < 0) {
dev_err(priv->dev, "Property %s malformed: %d\n", prop, ret);
return ret;
}
if (val)
*val = defval;
for (i = 0; i < nvalues; i++)
if (defval == values[i])
return i;
dev_err(priv->dev, "Invalid value for property %s: %d\n", prop, defval);
return -EINVAL;
}
int cs42l43_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *d)
{
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
/* This tip sense invert is always set, HW wants an inverted signal */
unsigned int tip_deb = CS42L43_TIPSENSE_INV_MASK;
unsigned int hs2 = 0x2 << CS42L43_HSDET_MODE_SHIFT;
unsigned int autocontrol = 0, pdncntl = 0;
int ret;
dev_dbg(priv->dev, "Configure accessory detect\n");
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for jack config: %d\n", ret);
return ret;
}
mutex_lock(&priv->jack_lock);
priv->jack_hp = jack;
if (!jack)
goto done;
ret = device_property_count_u32(cs42l43->dev, "cirrus,buttons-ohms");
if (ret != -EINVAL) {
if (ret < 0) {
dev_err(priv->dev, "Property cirrus,buttons-ohms malformed: %d\n",
ret);
goto error;
}
if (ret > CS42L43_N_BUTTONS) {
ret = -EINVAL;
dev_err(priv->dev, "Property cirrus,buttons-ohms too many entries\n");
goto error;
}
device_property_read_u32_array(cs42l43->dev, "cirrus,buttons-ohms",
priv->buttons, ret);
} else {
priv->buttons[0] = 70;
priv->buttons[1] = 185;
priv->buttons[2] = 355;
priv->buttons[3] = 735;
}
ret = cs42l43_find_index(priv, "cirrus,detect-us", 10000, &priv->detect_us,
cs42l43_accdet_us, ARRAY_SIZE(cs42l43_accdet_us));
if (ret < 0)
goto error;
hs2 |= ret << CS42L43_AUTO_HSDET_TIME_SHIFT;
priv->bias_low = device_property_read_bool(cs42l43->dev, "cirrus,bias-low");
ret = cs42l43_find_index(priv, "cirrus,bias-ramp-ms", 170,
&priv->bias_ramp_ms, cs42l43_accdet_ramp_ms,
ARRAY_SIZE(cs42l43_accdet_ramp_ms));
if (ret < 0)
goto error;
hs2 |= ret << CS42L43_HSBIAS_RAMP_SHIFT;
ret = cs42l43_find_index(priv, "cirrus,bias-sense-microamp", 0,
&priv->bias_sense_ua, cs42l43_accdet_bias_sense,
ARRAY_SIZE(cs42l43_accdet_bias_sense));
if (ret < 0)
goto error;
if (priv->bias_sense_ua)
autocontrol |= ret << CS42L43_HSBIAS_SENSE_TRIP_SHIFT;
if (!device_property_read_bool(cs42l43->dev, "cirrus,button-automute"))
autocontrol |= CS42L43_S0_AUTO_ADCMUTE_DISABLE_MASK;
ret = device_property_read_u32(cs42l43->dev, "cirrus,tip-debounce-ms",
&priv->tip_debounce_ms);
if (ret < 0 && ret != -EINVAL) {
dev_err(priv->dev, "Property cirrus,tip-debounce-ms malformed: %d\n", ret);
goto error;
}
/* This tip sense invert is set normally, as TIPSENSE_INV already inverted */
if (device_property_read_bool(cs42l43->dev, "cirrus,tip-invert"))
autocontrol |= 0x1 << CS42L43_JACKDET_INV_SHIFT;
if (device_property_read_bool(cs42l43->dev, "cirrus,tip-disable-pullup"))
autocontrol |= 0x1 << CS42L43_JACKDET_MODE_SHIFT;
else
autocontrol |= 0x3 << CS42L43_JACKDET_MODE_SHIFT;
ret = cs42l43_find_index(priv, "cirrus,tip-fall-db-ms", 500,
NULL, cs42l43_accdet_db_ms,
ARRAY_SIZE(cs42l43_accdet_db_ms));
if (ret < 0)
goto error;
tip_deb |= ret << CS42L43_TIPSENSE_FALLING_DB_TIME_SHIFT;
ret = cs42l43_find_index(priv, "cirrus,tip-rise-db-ms", 500,
NULL, cs42l43_accdet_db_ms,
ARRAY_SIZE(cs42l43_accdet_db_ms));
if (ret < 0)
goto error;
tip_deb |= ret << CS42L43_TIPSENSE_RISING_DB_TIME_SHIFT;
if (device_property_read_bool(cs42l43->dev, "cirrus,use-ring-sense")) {
unsigned int ring_deb = 0;
priv->use_ring_sense = true;
/* HW wants an inverted signal, so invert the invert */
if (!device_property_read_bool(cs42l43->dev, "cirrus,ring-invert"))
ring_deb |= CS42L43_RINGSENSE_INV_MASK;
if (!device_property_read_bool(cs42l43->dev,
"cirrus,ring-disable-pullup"))
ring_deb |= CS42L43_RINGSENSE_PULLUP_PDNB_MASK;
ret = cs42l43_find_index(priv, "cirrus,ring-fall-db-ms", 500,
NULL, cs42l43_accdet_db_ms,
ARRAY_SIZE(cs42l43_accdet_db_ms));
if (ret < 0)
goto error;
ring_deb |= ret << CS42L43_RINGSENSE_FALLING_DB_TIME_SHIFT;
ret = cs42l43_find_index(priv, "cirrus,ring-rise-db-ms", 500,
NULL, cs42l43_accdet_db_ms,
ARRAY_SIZE(cs42l43_accdet_db_ms));
if (ret < 0)
goto error;
ring_deb |= ret << CS42L43_RINGSENSE_RISING_DB_TIME_SHIFT;
pdncntl |= CS42L43_RING_SENSE_EN_MASK;
regmap_update_bits(cs42l43->regmap, CS42L43_RINGSENSE_DEB_CTRL,
CS42L43_RINGSENSE_INV_MASK |
CS42L43_RINGSENSE_PULLUP_PDNB_MASK |
CS42L43_RINGSENSE_FALLING_DB_TIME_MASK |
CS42L43_RINGSENSE_RISING_DB_TIME_MASK,
ring_deb);
}
regmap_update_bits(cs42l43->regmap, CS42L43_TIPSENSE_DEB_CTRL,
CS42L43_TIPSENSE_INV_MASK |
CS42L43_TIPSENSE_FALLING_DB_TIME_MASK |
CS42L43_TIPSENSE_RISING_DB_TIME_MASK, tip_deb);
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HSBIAS_RAMP_MASK | CS42L43_HSDET_MODE_MASK |
CS42L43_AUTO_HSDET_TIME_MASK, hs2);
done:
ret = 0;
regmap_update_bits(cs42l43->regmap, CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,
CS42L43_JACKDET_MODE_MASK | CS42L43_S0_AUTO_ADCMUTE_DISABLE_MASK |
CS42L43_HSBIAS_SENSE_TRIP_MASK, autocontrol);
regmap_update_bits(cs42l43->regmap, CS42L43_PDNCNTL,
CS42L43_RING_SENSE_EN_MASK, pdncntl);
dev_dbg(priv->dev, "Successfully configured accessory detect\n");
error:
mutex_unlock(&priv->jack_lock);
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
return ret;
}
static void cs42l43_start_hs_bias(struct cs42l43_codec *priv, bool force_high)
{
struct cs42l43 *cs42l43 = priv->core;
unsigned int val = 0x3 << CS42L43_HSBIAS_MODE_SHIFT;
dev_dbg(priv->dev, "Start headset bias\n");
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HS_CLAMP_DISABLE_MASK, CS42L43_HS_CLAMP_DISABLE_MASK);
if (!force_high && priv->bias_low)
val = 0x2 << CS42L43_HSBIAS_MODE_SHIFT;
regmap_update_bits(cs42l43->regmap, CS42L43_MIC_DETECT_CONTROL_1,
CS42L43_HSBIAS_MODE_MASK, val);
msleep(priv->bias_ramp_ms);
}
static void cs42l43_stop_hs_bias(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
dev_dbg(priv->dev, "Stop headset bias\n");
regmap_update_bits(cs42l43->regmap, CS42L43_MIC_DETECT_CONTROL_1,
CS42L43_HSBIAS_MODE_MASK, 0x1 << CS42L43_HSBIAS_MODE_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HS_CLAMP_DISABLE_MASK, 0);
}
irqreturn_t cs42l43_bias_detect_clamp(int irq, void *data)
{
struct cs42l43_codec *priv = data;
queue_delayed_work(system_wq, &priv->bias_sense_timeout,
msecs_to_jiffies(250));
return IRQ_HANDLED;
}
#define CS42L43_JACK_PRESENT 0x3
#define CS42L43_JACK_ABSENT 0x0
#define CS42L43_JACK_OPTICAL (SND_JACK_MECHANICAL | SND_JACK_AVOUT)
#define CS42L43_JACK_HEADPHONE (SND_JACK_MECHANICAL | SND_JACK_HEADPHONE)
#define CS42L43_JACK_HEADSET (SND_JACK_MECHANICAL | SND_JACK_HEADSET)
#define CS42L43_JACK_LINEOUT (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)
#define CS42L43_JACK_LINEIN (SND_JACK_MECHANICAL | SND_JACK_LINEIN)
#define CS42L43_JACK_EXTENSION (SND_JACK_MECHANICAL)
#define CS42L43_JACK_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 | \
SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5)
static inline bool cs42l43_jack_present(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
unsigned int sts = 0;
regmap_read(cs42l43->regmap, CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS, &sts);
sts = (sts >> CS42L43_TIPSENSE_PLUG_DB_STS_SHIFT) & CS42L43_JACK_PRESENT;
return sts == CS42L43_JACK_PRESENT;
}
static void cs42l43_start_button_detect(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
unsigned int val = 0x3 << CS42L43_BUTTON_DETECT_MODE_SHIFT;
dev_dbg(priv->dev, "Start button detect\n");
priv->button_detect_running = true;
if (priv->bias_low)
val = 0x1 << CS42L43_BUTTON_DETECT_MODE_SHIFT;
regmap_update_bits(cs42l43->regmap, CS42L43_MIC_DETECT_CONTROL_1,
CS42L43_BUTTON_DETECT_MODE_MASK |
CS42L43_MIC_LVL_DET_DISABLE_MASK, val);
if (priv->bias_sense_ua) {
regmap_update_bits(cs42l43->regmap,
CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,
CS42L43_HSBIAS_SENSE_EN_MASK |
CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK,
CS42L43_HSBIAS_SENSE_EN_MASK |
CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK);
}
}
static void cs42l43_stop_button_detect(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
dev_dbg(priv->dev, "Stop button detect\n");
if (priv->bias_sense_ua) {
regmap_update_bits(cs42l43->regmap,
CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,
CS42L43_HSBIAS_SENSE_EN_MASK |
CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK, 0);
}
regmap_update_bits(cs42l43->regmap, CS42L43_MIC_DETECT_CONTROL_1,
CS42L43_BUTTON_DETECT_MODE_MASK |
CS42L43_MIC_LVL_DET_DISABLE_MASK,
CS42L43_MIC_LVL_DET_DISABLE_MASK);
priv->button_detect_running = false;
}
#define CS42L43_BUTTON_COMB_MAX 512
#define CS42L43_BUTTON_ROUT 2210
void cs42l43_button_press_work(struct work_struct *work)
{
struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
button_press_work.work);
struct cs42l43 *cs42l43 = priv->core;
unsigned int buttons = 0;
unsigned int val = 0;
int i, ret;
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for button press: %d\n", ret);
return;
}
mutex_lock(&priv->jack_lock);
if (!priv->button_detect_running) {
dev_dbg(priv->dev, "Spurious button press IRQ\n");
goto error;
}
regmap_read(cs42l43->regmap, CS42L43_DETECT_STATUS_1, &val);
/* Bail if jack removed, the button is irrelevant and likely invalid */
if (!cs42l43_jack_present(priv)) {
dev_dbg(priv->dev, "Button ignored due to removal\n");
goto error;
}
if (val & CS42L43_HSBIAS_CLAMP_STS_MASK) {
dev_dbg(priv->dev, "Button ignored due to bias sense\n");
goto error;
}
val = (val & CS42L43_HSDET_DC_STS_MASK) >> CS42L43_HSDET_DC_STS_SHIFT;
val = ((CS42L43_BUTTON_COMB_MAX << 20) / (val + 1)) - (1 << 20);
if (val)
val = (CS42L43_BUTTON_ROUT << 20) / val;
else
val = UINT_MAX;
for (i = 0; i < CS42L43_N_BUTTONS; i++) {
if (val < priv->buttons[i]) {
buttons = SND_JACK_BTN_0 >> i;
dev_dbg(priv->dev, "Detected button %d at %d Ohms\n", i, val);
break;
}
}
if (!buttons)
dev_dbg(priv->dev, "Unrecognised button: %d Ohms\n", val);
snd_soc_jack_report(priv->jack_hp, buttons, CS42L43_JACK_BUTTONS);
error:
mutex_unlock(&priv->jack_lock);
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
}
irqreturn_t cs42l43_button_press(int irq, void *data)
{
struct cs42l43_codec *priv = data;
// Wait for 2 full cycles of comb filter to ensure good reading
queue_delayed_work(system_wq, &priv->button_press_work,
msecs_to_jiffies(10));
return IRQ_HANDLED;
}
void cs42l43_button_release_work(struct work_struct *work)
{
struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
button_release_work);
int ret;
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for button release: %d\n", ret);
return;
}
mutex_lock(&priv->jack_lock);
if (priv->button_detect_running) {
dev_dbg(priv->dev, "Button release IRQ\n");
snd_soc_jack_report(priv->jack_hp, 0, CS42L43_JACK_BUTTONS);
} else {
dev_dbg(priv->dev, "Spurious button release IRQ\n");
}
mutex_unlock(&priv->jack_lock);
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
}
irqreturn_t cs42l43_button_release(int irq, void *data)
{
struct cs42l43_codec *priv = data;
queue_work(system_wq, &priv->button_release_work);
return IRQ_HANDLED;
}
void cs42l43_bias_sense_timeout(struct work_struct *work)
{
struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
bias_sense_timeout.work);
struct cs42l43 *cs42l43 = priv->core;
int ret;
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for bias sense: %d\n", ret);
return;
}
mutex_lock(&priv->jack_lock);
if (cs42l43_jack_present(priv) && priv->button_detect_running) {
dev_dbg(priv->dev, "Bias sense timeout out, restore bias\n");
regmap_update_bits(cs42l43->regmap,
CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,
CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap,
CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL,
CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK,
CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK);
}
mutex_unlock(&priv->jack_lock);
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
}
static void cs42l43_start_load_detect(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
dev_dbg(priv->dev, "Start load detect\n");
snd_soc_dapm_mutex_lock(snd_soc_component_get_dapm(priv->component));
priv->load_detect_running = true;
if (priv->hp_ena) {
unsigned long time_left;
reinit_completion(&priv->hp_shutdown);
regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
CS42L43_HP_EN_MASK, 0);
time_left = wait_for_completion_timeout(&priv->hp_shutdown,
msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS));
if (!time_left)
dev_err(priv->dev, "Load detect HP power down timed out\n");
}
regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
CS42L43_ADC1_EN_MASK | CS42L43_ADC2_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_DACCNFG2, CS42L43_HP_HPF_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_MIC_DETECT_CONTROL_1,
CS42L43_HSBIAS_MODE_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_CTRL,
CS42L43_ADPTPWR_MODE_MASK, 0x4 << CS42L43_ADPTPWR_MODE_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_PGAVOL,
CS42L43_HP_DIG_VOL_RAMP_MASK | CS42L43_HP_ANA_VOL_RAMP_MASK, 0x6);
regmap_update_bits(cs42l43->regmap, CS42L43_DACCNFG1,
CS42L43_HP_MSTR_VOL_CTRL_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HS_CLAMP_DISABLE_MASK, CS42L43_HS_CLAMP_DISABLE_MASK);
regmap_update_bits(cs42l43->regmap, CS42L43_LOADDETENA,
CS42L43_HPLOAD_DET_EN_MASK,
CS42L43_HPLOAD_DET_EN_MASK);
snd_soc_dapm_mutex_unlock(snd_soc_component_get_dapm(priv->component));
}
static void cs42l43_stop_load_detect(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
dev_dbg(priv->dev, "Stop load detect\n");
snd_soc_dapm_mutex_lock(snd_soc_component_get_dapm(priv->component));
regmap_update_bits(cs42l43->regmap, CS42L43_LOADDETENA,
CS42L43_HPLOAD_DET_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HS_CLAMP_DISABLE_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_DACCNFG1,
CS42L43_HP_MSTR_VOL_CTRL_EN_MASK,
CS42L43_HP_MSTR_VOL_CTRL_EN_MASK);
regmap_update_bits(cs42l43->regmap, CS42L43_PGAVOL,
CS42L43_HP_DIG_VOL_RAMP_MASK | CS42L43_HP_ANA_VOL_RAMP_MASK,
0x4 << CS42L43_HP_DIG_VOL_RAMP_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_CTRL,
CS42L43_ADPTPWR_MODE_MASK, 0x7 << CS42L43_ADPTPWR_MODE_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_MIC_DETECT_CONTROL_1,
CS42L43_HSBIAS_MODE_MASK, 0x1 << CS42L43_HSBIAS_MODE_SHIFT);
regmap_update_bits(cs42l43->regmap, CS42L43_DACCNFG2,
CS42L43_HP_HPF_EN_MASK, CS42L43_HP_HPF_EN_MASK);
regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
CS42L43_ADC1_EN_MASK | CS42L43_ADC2_EN_MASK,
priv->adc_ena);
if (priv->hp_ena) {
unsigned long time_left;
reinit_completion(&priv->hp_startup);
regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
CS42L43_HP_EN_MASK, priv->hp_ena);
time_left = wait_for_completion_timeout(&priv->hp_startup,
msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS));
if (!time_left)
dev_err(priv->dev, "Load detect HP restore timed out\n");
}
priv->load_detect_running = false;
snd_soc_dapm_mutex_unlock(snd_soc_component_get_dapm(priv->component));
}
static int cs42l43_run_load_detect(struct cs42l43_codec *priv, bool mic)
{
struct cs42l43 *cs42l43 = priv->core;
unsigned int val = 0;
unsigned long time_left;
reinit_completion(&priv->load_detect);
cs42l43_start_load_detect(priv);
time_left = wait_for_completion_timeout(&priv->load_detect,
msecs_to_jiffies(CS42L43_LOAD_TIMEOUT_MS));
cs42l43_stop_load_detect(priv);
if (!time_left)
return -ETIMEDOUT;
regmap_read(cs42l43->regmap, CS42L43_LOADDETRESULTS, &val);
dev_dbg(priv->dev, "Headphone load detect: 0x%x\n", val);
/* Bail if jack removed, the load is irrelevant and likely invalid */
if (!cs42l43_jack_present(priv))
return -ENODEV;
if (mic) {
cs42l43_start_hs_bias(priv, false);
cs42l43_start_button_detect(priv);
return CS42L43_JACK_HEADSET;
}
switch (val & CS42L43_AMP3_RES_DET_MASK) {
case 0x0: // low impedance
case 0x1: // high impedance
return CS42L43_JACK_HEADPHONE;
case 0x2: // lineout
case 0x3: // Open circuit
return CS42L43_JACK_LINEOUT;
default:
return -EINVAL;
}
}
static int cs42l43_run_type_detect(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
int timeout_ms = ((2 * priv->detect_us) / 1000) + 200;
unsigned int type = 0xff;
unsigned long time_left;
reinit_completion(&priv->type_detect);
cs42l43_start_hs_bias(priv, true);
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HSDET_MODE_MASK, 0x3 << CS42L43_HSDET_MODE_SHIFT);
time_left = wait_for_completion_timeout(&priv->type_detect,
msecs_to_jiffies(timeout_ms));
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HSDET_MODE_MASK, 0x2 << CS42L43_HSDET_MODE_SHIFT);
cs42l43_stop_hs_bias(priv);
if (!time_left)
return -ETIMEDOUT;
regmap_read(cs42l43->regmap, CS42L43_HS_STAT, &type);
dev_dbg(priv->dev, "Type detect: 0x%x\n", type);
/* Bail if jack removed, the type is irrelevant and likely invalid */
if (!cs42l43_jack_present(priv))
return -ENODEV;
switch (type & CS42L43_HSDET_TYPE_STS_MASK) {
case 0x0: // CTIA
case 0x1: // OMTP
return cs42l43_run_load_detect(priv, true);
case 0x2: // 3-pole
return cs42l43_run_load_detect(priv, false);
case 0x3: // Open-circuit
return CS42L43_JACK_EXTENSION;
default:
return -EINVAL;
}
}
static void cs42l43_clear_jack(struct cs42l43_codec *priv)
{
struct cs42l43 *cs42l43 = priv->core;
cs42l43_stop_button_detect(priv);
cs42l43_stop_hs_bias(priv);
regmap_update_bits(cs42l43->regmap, CS42L43_ADC_B_CTRL1,
CS42L43_PGA_WIDESWING_MODE_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_ADC_B_CTRL2,
CS42L43_PGA_WIDESWING_MODE_EN_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_STEREO_MIC_CTRL,
CS42L43_JACK_STEREO_CONFIG_MASK, 0);
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HSDET_MODE_MASK | CS42L43_HSDET_MANUAL_MODE_MASK,
0x2 << CS42L43_HSDET_MODE_SHIFT);
snd_soc_jack_report(priv->jack_hp, 0, 0xFFFF);
}
void cs42l43_tip_sense_work(struct work_struct *work)
{
struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
tip_sense_work.work);
struct cs42l43 *cs42l43 = priv->core;
unsigned int sts = 0;
unsigned int tip, ring;
int ret, report;
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for tip work: %d\n", ret);
return;
}
mutex_lock(&priv->jack_lock);
regmap_read(cs42l43->regmap, CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS, &sts);
dev_dbg(priv->dev, "Tip sense: 0x%x\n", sts);
tip = (sts >> CS42L43_TIPSENSE_PLUG_DB_STS_SHIFT) & CS42L43_JACK_PRESENT;
ring = (sts >> CS42L43_RINGSENSE_PLUG_DB_STS_SHIFT) & CS42L43_JACK_PRESENT;
if (tip == CS42L43_JACK_PRESENT) {
if (cs42l43->sdw && !priv->jack_present) {
priv->jack_present = true;
pm_runtime_get(priv->dev);
}
if (priv->use_ring_sense && ring == CS42L43_JACK_ABSENT) {
report = CS42L43_JACK_OPTICAL;
} else {
report = cs42l43_run_type_detect(priv);
if (report < 0) {
dev_err(priv->dev, "Jack detect failed: %d\n", report);
goto error;
}
}
snd_soc_jack_report(priv->jack_hp, report, report);
} else {
priv->jack_override = 0;
cs42l43_clear_jack(priv);
if (cs42l43->sdw && priv->jack_present) {
pm_runtime_put(priv->dev);
priv->jack_present = false;
}
}
error:
mutex_unlock(&priv->jack_lock);
pm_runtime_mark_last_busy(priv->dev);
pm_runtime_put_autosuspend(priv->dev);
}
irqreturn_t cs42l43_tip_sense(int irq, void *data)
{
struct cs42l43_codec *priv = data;
cancel_delayed_work(&priv->bias_sense_timeout);
cancel_delayed_work(&priv->tip_sense_work);
cancel_delayed_work(&priv->button_press_work);
cancel_work(&priv->button_release_work);
queue_delayed_work(system_long_wq, &priv->tip_sense_work,
msecs_to_jiffies(priv->tip_debounce_ms));
return IRQ_HANDLED;
}
enum cs42l43_raw_jack {
CS42L43_JACK_RAW_CTIA = 0,
CS42L43_JACK_RAW_OMTP,
CS42L43_JACK_RAW_HEADPHONE,
CS42L43_JACK_RAW_LINE_OUT,
CS42L43_JACK_RAW_LINE_IN,
CS42L43_JACK_RAW_MICROPHONE,
CS42L43_JACK_RAW_OPTICAL,
};
#define CS42L43_JACK_3_POLE_SWITCHES ((0x2 << CS42L43_HSDET_MANUAL_MODE_SHIFT) | \
CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK | \
CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK | \
CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK | \
CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK | \
CS42L43_HSGND_HS3_SEL_MASK | \
CS42L43_HSGND_HS4_SEL_MASK)
static const struct cs42l43_jack_override_mode {
unsigned int hsdet_mode;
unsigned int mic_ctrl;
unsigned int clamp_ctrl;
int report;
} cs42l43_jack_override_modes[] = {
[CS42L43_JACK_RAW_CTIA] = {
.hsdet_mode = CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK |
CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK |
CS42L43_HSBIAS_OUT_HS4_SEL_MASK |
CS42L43_HSGND_HS3_SEL_MASK,
.clamp_ctrl = CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK,
.report = CS42L43_JACK_HEADSET,
},
[CS42L43_JACK_RAW_OMTP] = {
.hsdet_mode = (0x1 << CS42L43_HSDET_MANUAL_MODE_SHIFT) |
CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK |
CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK |
CS42L43_HSBIAS_OUT_HS3_SEL_MASK |
CS42L43_HSGND_HS4_SEL_MASK,
.clamp_ctrl = CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK,
.report = CS42L43_JACK_HEADSET,
},
[CS42L43_JACK_RAW_HEADPHONE] = {
.hsdet_mode = CS42L43_JACK_3_POLE_SWITCHES,
.clamp_ctrl = CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK,
.report = CS42L43_JACK_HEADPHONE,
},
[CS42L43_JACK_RAW_LINE_OUT] = {
.hsdet_mode = CS42L43_JACK_3_POLE_SWITCHES,
.clamp_ctrl = CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK,
.report = CS42L43_JACK_LINEOUT,
},
[CS42L43_JACK_RAW_LINE_IN] = {
.hsdet_mode = CS42L43_JACK_3_POLE_SWITCHES,
.mic_ctrl = 0x2 << CS42L43_JACK_STEREO_CONFIG_SHIFT,
.report = CS42L43_JACK_LINEIN,
},
[CS42L43_JACK_RAW_MICROPHONE] = {
.hsdet_mode = CS42L43_JACK_3_POLE_SWITCHES,
.mic_ctrl = (0x3 << CS42L43_JACK_STEREO_CONFIG_SHIFT) |
CS42L43_HS1_BIAS_EN_MASK | CS42L43_HS2_BIAS_EN_MASK,
.report = CS42L43_JACK_LINEIN,
},
[CS42L43_JACK_RAW_OPTICAL] = {
.hsdet_mode = CS42L43_JACK_3_POLE_SWITCHES,
.clamp_ctrl = CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK,
.report = CS42L43_JACK_OPTICAL,
},
};
static const char * const cs42l43_jack_text[] = {
"None", "CTIA", "OMTP", "Headphone", "Line-Out",
"Line-In", "Microphone", "Optical",
};
SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_jack_enum, cs42l43_jack_text);
int cs42l43_jack_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
mutex_lock(&priv->jack_lock);
ucontrol->value.integer.value[0] = priv->jack_override;
mutex_unlock(&priv->jack_lock);
return 0;
}
int cs42l43_jack_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
struct cs42l43 *cs42l43 = priv->core;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int override = ucontrol->value.integer.value[0];
BUILD_BUG_ON(ARRAY_SIZE(cs42l43_jack_override_modes) !=
ARRAY_SIZE(cs42l43_jack_text) - 1);
if (override >= e->items)
return -EINVAL;
mutex_lock(&priv->jack_lock);
if (!cs42l43_jack_present(priv)) {
mutex_unlock(&priv->jack_lock);
return -EBUSY;
}
if (override == priv->jack_override) {
mutex_unlock(&priv->jack_lock);
return 0;
}
priv->jack_override = override;
cs42l43_clear_jack(priv);
if (!override) {
queue_delayed_work(system_long_wq, &priv->tip_sense_work, 0);
} else {
override--;
regmap_update_bits(cs42l43->regmap, CS42L43_HS2,
CS42L43_HSDET_MODE_MASK |
CS42L43_HSDET_MANUAL_MODE_MASK |
CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK |
CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK |
CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK |
CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK |
CS42L43_HSBIAS_OUT_HS3_SEL_MASK |
CS42L43_HSBIAS_OUT_HS4_SEL_MASK |
CS42L43_HSGND_HS3_SEL_MASK |
CS42L43_HSGND_HS4_SEL_MASK,
cs42l43_jack_override_modes[override].hsdet_mode);
regmap_update_bits(cs42l43->regmap, CS42L43_STEREO_MIC_CTRL,
CS42L43_HS2_BIAS_EN_MASK | CS42L43_HS1_BIAS_EN_MASK |
CS42L43_JACK_STEREO_CONFIG_MASK,
cs42l43_jack_override_modes[override].mic_ctrl);
regmap_update_bits(cs42l43->regmap, CS42L43_STEREO_MIC_CLAMP_CTRL,
CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK,
cs42l43_jack_override_modes[override].clamp_ctrl);
switch (override) {
case CS42L43_JACK_RAW_CTIA:
case CS42L43_JACK_RAW_OMTP:
cs42l43_start_hs_bias(priv, false);
cs42l43_start_button_detect(priv);
break;
case CS42L43_JACK_RAW_LINE_IN:
regmap_update_bits(cs42l43->regmap, CS42L43_ADC_B_CTRL1,
CS42L43_PGA_WIDESWING_MODE_EN_MASK,
CS42L43_PGA_WIDESWING_MODE_EN_MASK);
regmap_update_bits(cs42l43->regmap, CS42L43_ADC_B_CTRL2,
CS42L43_PGA_WIDESWING_MODE_EN_MASK,
CS42L43_PGA_WIDESWING_MODE_EN_MASK);
break;
case CS42L43_JACK_RAW_MICROPHONE:
cs42l43_start_hs_bias(priv, false);
break;
default:
break;
}
snd_soc_jack_report(priv->jack_hp,
cs42l43_jack_override_modes[override].report,
cs42l43_jack_override_modes[override].report);
}
mutex_unlock(&priv->jack_lock);
return 1;
}
| linux-master | sound/soc/codecs/cs42l43-jack.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for the Texas Instruments TAS2562 CODEC
// Copyright (C) 2019 Texas Instruments Inc.
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "tas2562.h"
#define TAS2562_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FORMAT_S32_LE)
/* DVC equation involves floating point math
* round(10^(volume in dB/20)*2^30)
* so create a lookup table for 2dB step
*/
static const unsigned int float_vol_db_lookup[] = {
0x00000d43, 0x000010b2, 0x00001505, 0x00001a67, 0x00002151,
0x000029f1, 0x000034cd, 0x00004279, 0x000053af, 0x0000695b,
0x0000695b, 0x0000a6fa, 0x0000d236, 0x000108a4, 0x00014d2a,
0x0001a36e, 0x00021008, 0x000298c0, 0x000344df, 0x00041d8f,
0x00052e5a, 0x000685c8, 0x00083621, 0x000a566d, 0x000d03a7,
0x0010624d, 0x0014a050, 0x0019f786, 0x0020b0bc, 0x0029279d,
0x0033cf8d, 0x004139d3, 0x00521d50, 0x00676044, 0x0082248a,
0x00a3d70a, 0x00ce4328, 0x0103ab3d, 0x0146e75d, 0x019b8c27,
0x02061b89, 0x028c423f, 0x03352529, 0x0409c2b0, 0x05156d68,
0x080e9f96, 0x0a24b062, 0x0cc509ab, 0x10137987, 0x143d1362,
0x197a967f, 0x2013739e, 0x28619ae9, 0x32d64617, 0x40000000
};
struct tas2562_data {
struct snd_soc_component *component;
struct gpio_desc *sdz_gpio;
struct regmap *regmap;
struct device *dev;
struct i2c_client *client;
int v_sense_slot;
int i_sense_slot;
int volume_lvl;
int model_id;
bool dac_powered;
bool unmuted;
};
enum tas256x_model {
TAS2562,
TAS2563,
TAS2564,
TAS2110,
};
static int tas2562_set_samplerate(struct tas2562_data *tas2562, int samplerate)
{
int samp_rate;
int ramp_rate;
switch (samplerate) {
case 7350:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_7305_8KHZ;
break;
case 8000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_7305_8KHZ;
break;
case 14700:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_14_7_16KHZ;
break;
case 16000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_14_7_16KHZ;
break;
case 22050:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_22_05_24KHZ;
break;
case 24000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_22_05_24KHZ;
break;
case 29400:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_29_4_32KHZ;
break;
case 32000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_29_4_32KHZ;
break;
case 44100:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_44_1_48KHZ;
break;
case 48000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_44_1_48KHZ;
break;
case 88200:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_88_2_96KHZ;
break;
case 96000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_88_2_96KHZ;
break;
case 176400:
ramp_rate = TAS2562_TDM_CFG0_RAMPRATE_44_1;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_176_4_192KHZ;
break;
case 192000:
ramp_rate = 0;
samp_rate = TAS2562_TDM_CFG0_SAMPRATE_176_4_192KHZ;
break;
default:
dev_info(tas2562->dev, "%s, unsupported sample rate, %d\n",
__func__, samplerate);
return -EINVAL;
}
snd_soc_component_update_bits(tas2562->component, TAS2562_TDM_CFG0,
TAS2562_TDM_CFG0_RAMPRATE_MASK, ramp_rate);
snd_soc_component_update_bits(tas2562->component, TAS2562_TDM_CFG0,
TAS2562_TDM_CFG0_SAMPRATE_MASK, samp_rate);
return 0;
}
static int tas2562_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
int left_slot, right_slot;
int slots_cfg;
int ret;
if (!tx_mask) {
dev_err(component->dev, "tx masks must not be 0\n");
return -EINVAL;
}
if (slots == 1) {
if (tx_mask != 1)
return -EINVAL;
left_slot = 0;
right_slot = 0;
} else {
left_slot = __ffs(tx_mask);
tx_mask &= ~(1 << left_slot);
if (tx_mask == 0) {
right_slot = left_slot;
} else {
right_slot = __ffs(tx_mask);
}
}
slots_cfg = (right_slot << TAS2562_RIGHT_SLOT_SHIFT) | left_slot;
ret = snd_soc_component_write(component, TAS2562_TDM_CFG3, slots_cfg);
if (ret < 0)
return ret;
switch (slot_width) {
case 16:
ret = snd_soc_component_update_bits(component,
TAS2562_TDM_CFG2,
TAS2562_TDM_CFG2_RXLEN_MASK,
TAS2562_TDM_CFG2_RXLEN_16B);
break;
case 24:
ret = snd_soc_component_update_bits(component,
TAS2562_TDM_CFG2,
TAS2562_TDM_CFG2_RXLEN_MASK,
TAS2562_TDM_CFG2_RXLEN_24B);
break;
case 32:
ret = snd_soc_component_update_bits(component,
TAS2562_TDM_CFG2,
TAS2562_TDM_CFG2_RXLEN_MASK,
TAS2562_TDM_CFG2_RXLEN_32B);
break;
case 0:
/* Do not change slot width */
break;
default:
dev_err(tas2562->dev, "slot width not supported");
ret = -EINVAL;
}
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2562_TDM_CFG5,
TAS2562_TDM_CFG5_VSNS_SLOT_MASK,
tas2562->v_sense_slot);
if (ret < 0)
return ret;
ret = snd_soc_component_update_bits(component, TAS2562_TDM_CFG6,
TAS2562_TDM_CFG6_ISNS_SLOT_MASK,
tas2562->i_sense_slot);
if (ret < 0)
return ret;
return 0;
}
static int tas2562_set_bitwidth(struct tas2562_data *tas2562, int bitwidth)
{
int ret;
int val;
int sense_en;
switch (bitwidth) {
case SNDRV_PCM_FORMAT_S16_LE:
snd_soc_component_update_bits(tas2562->component,
TAS2562_TDM_CFG2,
TAS2562_TDM_CFG2_RXWLEN_MASK,
TAS2562_TDM_CFG2_RXWLEN_16B);
break;
case SNDRV_PCM_FORMAT_S24_LE:
snd_soc_component_update_bits(tas2562->component,
TAS2562_TDM_CFG2,
TAS2562_TDM_CFG2_RXWLEN_MASK,
TAS2562_TDM_CFG2_RXWLEN_24B);
break;
case SNDRV_PCM_FORMAT_S32_LE:
snd_soc_component_update_bits(tas2562->component,
TAS2562_TDM_CFG2,
TAS2562_TDM_CFG2_RXWLEN_MASK,
TAS2562_TDM_CFG2_RXWLEN_32B);
break;
default:
dev_info(tas2562->dev, "Unsupported bitwidth format\n");
return -EINVAL;
}
val = snd_soc_component_read(tas2562->component, TAS2562_PWR_CTRL);
if (val < 0)
return val;
if (val & (1 << TAS2562_VSENSE_POWER_EN))
sense_en = 0;
else
sense_en = TAS2562_TDM_CFG5_VSNS_EN;
ret = snd_soc_component_update_bits(tas2562->component, TAS2562_TDM_CFG5,
TAS2562_TDM_CFG5_VSNS_EN, sense_en);
if (ret < 0)
return ret;
if (val & (1 << TAS2562_ISENSE_POWER_EN))
sense_en = 0;
else
sense_en = TAS2562_TDM_CFG6_ISNS_EN;
ret = snd_soc_component_update_bits(tas2562->component, TAS2562_TDM_CFG6,
TAS2562_TDM_CFG6_ISNS_EN, sense_en);
if (ret < 0)
return ret;
return 0;
}
static int tas2562_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
int ret;
ret = tas2562_set_bitwidth(tas2562, params_format(params));
if (ret) {
dev_err(tas2562->dev, "set bitwidth failed, %d\n", ret);
return ret;
}
ret = tas2562_set_samplerate(tas2562, params_rate(params));
if (ret)
dev_err(tas2562->dev, "set sample rate failed, %d\n", ret);
return ret;
}
static int tas2562_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
u8 asi_cfg_1 = 0;
u8 tdm_rx_start_slot = 0;
int ret;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
asi_cfg_1 = 0;
break;
case SND_SOC_DAIFMT_IB_NF:
asi_cfg_1 |= TAS2562_TDM_CFG1_RX_FALLING;
break;
default:
dev_err(tas2562->dev, "ASI format Inverse is not found\n");
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2562_TDM_CFG1,
TAS2562_TDM_CFG1_RX_EDGE_MASK,
asi_cfg_1);
if (ret < 0) {
dev_err(tas2562->dev, "Failed to set RX edge\n");
return ret;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_DSP_B:
tdm_rx_start_slot = 0;
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_DSP_A:
tdm_rx_start_slot = 1;
break;
default:
dev_err(tas2562->dev,
"DAI Format is not found, fmt=0x%x\n", fmt);
return -EINVAL;
}
ret = snd_soc_component_update_bits(component, TAS2562_TDM_CFG1,
TAS2562_RX_OFF_MASK, (tdm_rx_start_slot << 1));
if (ret < 0)
return ret;
return 0;
}
static int tas2562_update_pwr_ctrl(struct tas2562_data *tas2562)
{
struct snd_soc_component *component = tas2562->component;
unsigned int val;
int ret;
if (tas2562->dac_powered)
val = tas2562->unmuted ?
TAS2562_ACTIVE : TAS2562_MUTE;
else
val = TAS2562_SHUTDOWN;
ret = snd_soc_component_update_bits(component, TAS2562_PWR_CTRL,
TAS2562_MODE_MASK, val);
if (ret < 0)
return ret;
return 0;
}
static int tas2562_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(dai->component);
tas2562->unmuted = !mute;
return tas2562_update_pwr_ctrl(tas2562);
}
static int tas2562_codec_probe(struct snd_soc_component *component)
{
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
tas2562->component = component;
if (tas2562->sdz_gpio)
gpiod_set_value_cansleep(tas2562->sdz_gpio, 1);
return 0;
}
#ifdef CONFIG_PM
static int tas2562_suspend(struct snd_soc_component *component)
{
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
regcache_cache_only(tas2562->regmap, true);
regcache_mark_dirty(tas2562->regmap);
if (tas2562->sdz_gpio)
gpiod_set_value_cansleep(tas2562->sdz_gpio, 0);
return 0;
}
static int tas2562_resume(struct snd_soc_component *component)
{
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
if (tas2562->sdz_gpio)
gpiod_set_value_cansleep(tas2562->sdz_gpio, 1);
regcache_cache_only(tas2562->regmap, false);
return regcache_sync(tas2562->regmap);
}
#else
#define tas2562_suspend NULL
#define tas2562_resume NULL
#endif
static const char * const tas2562_ASI1_src[] = {
"I2C offset", "Left", "Right", "LeftRightDiv2",
};
static SOC_ENUM_SINGLE_DECL(tas2562_ASI1_src_enum, TAS2562_TDM_CFG2, 4,
tas2562_ASI1_src);
static const struct snd_kcontrol_new tas2562_asi1_mux =
SOC_DAPM_ENUM("ASI1 Source", tas2562_ASI1_src_enum);
static int tas2562_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
tas2562->dac_powered = true;
ret = tas2562_update_pwr_ctrl(tas2562);
break;
case SND_SOC_DAPM_PRE_PMD:
tas2562->dac_powered = false;
ret = tas2562_update_pwr_ctrl(tas2562);
break;
default:
dev_err(tas2562->dev, "Not supported evevt\n");
return -EINVAL;
}
return ret;
}
static int tas2562_volume_control_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = tas2562->volume_lvl;
return 0;
}
static int tas2562_volume_control_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct tas2562_data *tas2562 = snd_soc_component_get_drvdata(component);
int ret;
u32 reg_val;
reg_val = float_vol_db_lookup[ucontrol->value.integer.value[0]/2];
ret = snd_soc_component_write(component, TAS2562_DVC_CFG4,
(reg_val & 0xff));
if (ret)
return ret;
ret = snd_soc_component_write(component, TAS2562_DVC_CFG3,
((reg_val >> 8) & 0xff));
if (ret)
return ret;
ret = snd_soc_component_write(component, TAS2562_DVC_CFG2,
((reg_val >> 16) & 0xff));
if (ret)
return ret;
ret = snd_soc_component_write(component, TAS2562_DVC_CFG1,
((reg_val >> 24) & 0xff));
if (ret)
return ret;
tas2562->volume_lvl = ucontrol->value.integer.value[0];
return 0;
}
/* Digital Volume Control. From 0 dB to -110 dB in 1 dB steps */
static const DECLARE_TLV_DB_SCALE(dvc_tlv, -11000, 100, 0);
static DECLARE_TLV_DB_SCALE(tas2562_dac_tlv, 850, 50, 0);
static const struct snd_kcontrol_new isense_switch =
SOC_DAPM_SINGLE("Switch", TAS2562_PWR_CTRL, TAS2562_ISENSE_POWER_EN,
1, 1);
static const struct snd_kcontrol_new vsense_switch =
SOC_DAPM_SINGLE("Switch", TAS2562_PWR_CTRL, TAS2562_VSENSE_POWER_EN,
1, 1);
static const struct snd_kcontrol_new tas2562_snd_controls[] = {
SOC_SINGLE_TLV("Amp Gain Volume", TAS2562_PB_CFG1, 1, 0x1c, 0,
tas2562_dac_tlv),
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Digital Volume Control",
.index = 0,
.tlv.p = dvc_tlv,
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = snd_soc_info_volsw,
.get = tas2562_volume_control_get,
.put = tas2562_volume_control_put,
.private_value = SOC_SINGLE_VALUE(TAS2562_DVC_CFG1, 0, 110, 0, 0),
},
};
static const struct snd_soc_dapm_widget tas2110_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2562_asi1_mux),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas2562_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route tas2110_audio_map[] = {
{"ASI1 Sel", "I2C offset", "ASI1"},
{"ASI1 Sel", "Left", "ASI1"},
{"ASI1 Sel", "Right", "ASI1"},
{"ASI1 Sel", "LeftRightDiv2", "ASI1"},
{ "DAC", NULL, "ASI1 Sel" },
{ "OUT", NULL, "DAC" },
};
static const struct snd_soc_component_driver soc_component_dev_tas2110 = {
.probe = tas2562_codec_probe,
.suspend = tas2562_suspend,
.resume = tas2562_resume,
.controls = tas2562_snd_controls,
.num_controls = ARRAY_SIZE(tas2562_snd_controls),
.dapm_widgets = tas2110_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas2110_dapm_widgets),
.dapm_routes = tas2110_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas2110_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dapm_widget tas2562_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2562_asi1_mux),
SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas2562_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SWITCH("ISENSE", TAS2562_PWR_CTRL, 3, 1, &isense_switch),
SND_SOC_DAPM_SWITCH("VSENSE", TAS2562_PWR_CTRL, 2, 1, &vsense_switch),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static const struct snd_soc_dapm_route tas2562_audio_map[] = {
{"ASI1 Sel", "I2C offset", "ASI1"},
{"ASI1 Sel", "Left", "ASI1"},
{"ASI1 Sel", "Right", "ASI1"},
{"ASI1 Sel", "LeftRightDiv2", "ASI1"},
{ "DAC", NULL, "ASI1 Sel" },
{ "OUT", NULL, "DAC" },
{"ISENSE", "Switch", "IMON"},
{"VSENSE", "Switch", "VMON"},
};
static const struct snd_soc_component_driver soc_component_dev_tas2562 = {
.probe = tas2562_codec_probe,
.suspend = tas2562_suspend,
.resume = tas2562_resume,
.controls = tas2562_snd_controls,
.num_controls = ARRAY_SIZE(tas2562_snd_controls),
.dapm_widgets = tas2562_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas2562_dapm_widgets),
.dapm_routes = tas2562_audio_map,
.num_dapm_routes = ARRAY_SIZE(tas2562_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_dai_ops tas2562_speaker_dai_ops = {
.hw_params = tas2562_hw_params,
.set_fmt = tas2562_set_dai_fmt,
.set_tdm_slot = tas2562_set_dai_tdm_slot,
.mute_stream = tas2562_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver tas2562_dai[] = {
{
.name = "tas2562-amplifier",
.id = 0,
.playback = {
.stream_name = "ASI1 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = TAS2562_FORMATS,
},
.capture = {
.stream_name = "ASI1 Capture",
.channels_min = 0,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = TAS2562_FORMATS,
},
.ops = &tas2562_speaker_dai_ops,
},
};
static const struct regmap_range_cfg tas2562_ranges[] = {
{
.range_min = 0,
.range_max = 5 * 128,
.selector_reg = TAS2562_PAGE_CTRL,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 128,
},
};
static const struct reg_default tas2562_reg_defaults[] = {
{ TAS2562_PAGE_CTRL, 0x00 },
{ TAS2562_SW_RESET, 0x00 },
{ TAS2562_PWR_CTRL, 0x0e },
{ TAS2562_PB_CFG1, 0x20 },
{ TAS2562_TDM_CFG0, 0x09 },
{ TAS2562_TDM_CFG1, 0x02 },
{ TAS2562_DVC_CFG1, 0x40 },
{ TAS2562_DVC_CFG2, 0x40 },
{ TAS2562_DVC_CFG3, 0x00 },
{ TAS2562_DVC_CFG4, 0x00 },
};
static const struct regmap_config tas2562_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 5 * 128,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = tas2562_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas2562_reg_defaults),
.ranges = tas2562_ranges,
.num_ranges = ARRAY_SIZE(tas2562_ranges),
};
static int tas2562_parse_dt(struct tas2562_data *tas2562)
{
struct device *dev = tas2562->dev;
int ret = 0;
tas2562->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
if (IS_ERR(tas2562->sdz_gpio)) {
if (PTR_ERR(tas2562->sdz_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
tas2562->sdz_gpio = NULL;
}
/*
* The shut-down property is deprecated but needs to be checked for
* backwards compatibility.
*/
if (tas2562->sdz_gpio == NULL) {
tas2562->sdz_gpio = devm_gpiod_get_optional(dev, "shut-down",
GPIOD_OUT_HIGH);
if (IS_ERR(tas2562->sdz_gpio))
if (PTR_ERR(tas2562->sdz_gpio) == -EPROBE_DEFER)
return -EPROBE_DEFER;
tas2562->sdz_gpio = NULL;
}
if (tas2562->model_id == TAS2110)
return ret;
ret = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
&tas2562->i_sense_slot);
if (ret) {
dev_err(dev, "Property %s is missing setting default slot\n",
"ti,imon-slot-no");
tas2562->i_sense_slot = 0;
}
ret = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no",
&tas2562->v_sense_slot);
if (ret) {
dev_info(dev, "Property %s is missing setting default slot\n",
"ti,vmon-slot-no");
tas2562->v_sense_slot = 2;
}
if (tas2562->v_sense_slot < tas2562->i_sense_slot) {
dev_err(dev, "Vsense slot must be greater than Isense slot\n");
return -EINVAL;
}
return ret;
}
static const struct i2c_device_id tas2562_id[] = {
{ "tas2562", TAS2562 },
{ "tas2563", TAS2563 },
{ "tas2564", TAS2564 },
{ "tas2110", TAS2110 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas2562_id);
static int tas2562_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tas2562_data *data;
int ret;
const struct i2c_device_id *id;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
id = i2c_match_id(tas2562_id, client);
data->client = client;
data->dev = &client->dev;
data->model_id = id->driver_data;
tas2562_parse_dt(data);
data->regmap = devm_regmap_init_i2c(client, &tas2562_regmap_config);
if (IS_ERR(data->regmap)) {
ret = PTR_ERR(data->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
dev_set_drvdata(&client->dev, data);
if (data->model_id == TAS2110)
return devm_snd_soc_register_component(dev,
&soc_component_dev_tas2110,
tas2562_dai,
ARRAY_SIZE(tas2562_dai));
return devm_snd_soc_register_component(dev, &soc_component_dev_tas2562,
tas2562_dai,
ARRAY_SIZE(tas2562_dai));
}
#ifdef CONFIG_OF
static const struct of_device_id tas2562_of_match[] = {
{ .compatible = "ti,tas2562", },
{ .compatible = "ti,tas2563", },
{ .compatible = "ti,tas2564", },
{ .compatible = "ti,tas2110", },
{ },
};
MODULE_DEVICE_TABLE(of, tas2562_of_match);
#endif
static struct i2c_driver tas2562_i2c_driver = {
.driver = {
.name = "tas2562",
.of_match_table = of_match_ptr(tas2562_of_match),
},
.probe = tas2562_probe,
.id_table = tas2562_id,
};
module_i2c_driver(tas2562_i2c_driver);
MODULE_AUTHOR("Dan Murphy <[email protected]>");
MODULE_DESCRIPTION("TAS2562 Audio amplifier driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas2562.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2016, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#define LPASS_CDC_CLK_RX_RESET_CTL (0x000)
#define LPASS_CDC_CLK_TX_RESET_B1_CTL (0x004)
#define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
#define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
#define LPASS_CDC_CLK_DMIC_B1_CTL (0x008)
#define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1)
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 (0x0 << 1)
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 (0x1 << 1)
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 (0x2 << 1)
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 (0x3 << 1)
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 (0x4 << 1)
#define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
#define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
#define LPASS_CDC_CLK_RX_I2S_CTL (0x00C)
#define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
#define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
#define RX_I2S_CTL_RX_I2S_MODE_32 0
#define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0)
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ 0x0
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ 0x1
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ 0x2
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ 0x3
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ 0x4
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5
#define LPASS_CDC_CLK_TX_I2S_CTL (0x010)
#define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5)
#define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5)
#define TX_I2S_CTL_TX_I2S_MODE_32 0
#define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0)
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ 0x0
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ 0x1
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ 0x2
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ 0x3
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ 0x4
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5
#define LPASS_CDC_CLK_OTHR_RESET_B1_CTL (0x014)
#define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL (0x018)
#define LPASS_CDC_CLK_OTHR_CTL (0x01C)
#define LPASS_CDC_CLK_RX_B1_CTL (0x020)
#define LPASS_CDC_CLK_MCLK_CTL (0x024)
#define MCLK_CTL_MCLK_EN_MASK BIT(0)
#define MCLK_CTL_MCLK_EN_ENABLE BIT(0)
#define MCLK_CTL_MCLK_EN_DISABLE 0
#define LPASS_CDC_CLK_PDM_CTL (0x028)
#define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0)
#define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0)
#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1)
#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1)
#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK 0
#define LPASS_CDC_CLK_SD_CTL (0x02C)
#define LPASS_CDC_RX1_B1_CTL (0x040)
#define LPASS_CDC_RX2_B1_CTL (0x060)
#define LPASS_CDC_RX3_B1_CTL (0x080)
#define LPASS_CDC_RX1_B2_CTL (0x044)
#define LPASS_CDC_RX2_B2_CTL (0x064)
#define LPASS_CDC_RX3_B2_CTL (0x084)
#define LPASS_CDC_RX1_B3_CTL (0x048)
#define LPASS_CDC_RX2_B3_CTL (0x068)
#define LPASS_CDC_RX3_B3_CTL (0x088)
#define LPASS_CDC_RX1_B4_CTL (0x04C)
#define LPASS_CDC_RX2_B4_CTL (0x06C)
#define LPASS_CDC_RX3_B4_CTL (0x08C)
#define LPASS_CDC_RX1_B5_CTL (0x050)
#define LPASS_CDC_RX2_B5_CTL (0x070)
#define LPASS_CDC_RX3_B5_CTL (0x090)
#define LPASS_CDC_RX1_B6_CTL (0x054)
#define RXn_B6_CTL_MUTE_MASK BIT(0)
#define RXn_B6_CTL_MUTE_ENABLE BIT(0)
#define RXn_B6_CTL_MUTE_DISABLE 0
#define LPASS_CDC_RX2_B6_CTL (0x074)
#define LPASS_CDC_RX3_B6_CTL (0x094)
#define LPASS_CDC_RX1_VOL_CTL_B1_CTL (0x058)
#define LPASS_CDC_RX2_VOL_CTL_B1_CTL (0x078)
#define LPASS_CDC_RX3_VOL_CTL_B1_CTL (0x098)
#define LPASS_CDC_RX1_VOL_CTL_B2_CTL (0x05C)
#define LPASS_CDC_RX2_VOL_CTL_B2_CTL (0x07C)
#define LPASS_CDC_RX3_VOL_CTL_B2_CTL (0x09C)
#define LPASS_CDC_TOP_GAIN_UPDATE (0x0A0)
#define LPASS_CDC_TOP_CTL (0x0A4)
#define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0)
#define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ 0
#define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0)
#define LPASS_CDC_DEBUG_DESER1_CTL (0x0E0)
#define LPASS_CDC_DEBUG_DESER2_CTL (0x0E4)
#define LPASS_CDC_DEBUG_B1_CTL_CFG (0x0E8)
#define LPASS_CDC_DEBUG_B2_CTL_CFG (0x0EC)
#define LPASS_CDC_DEBUG_B3_CTL_CFG (0x0F0)
#define LPASS_CDC_IIR1_GAIN_B1_CTL (0x100)
#define LPASS_CDC_IIR2_GAIN_B1_CTL (0x140)
#define LPASS_CDC_IIR1_GAIN_B2_CTL (0x104)
#define LPASS_CDC_IIR2_GAIN_B2_CTL (0x144)
#define LPASS_CDC_IIR1_GAIN_B3_CTL (0x108)
#define LPASS_CDC_IIR2_GAIN_B3_CTL (0x148)
#define LPASS_CDC_IIR1_GAIN_B4_CTL (0x10C)
#define LPASS_CDC_IIR2_GAIN_B4_CTL (0x14C)
#define LPASS_CDC_IIR1_GAIN_B5_CTL (0x110)
#define LPASS_CDC_IIR2_GAIN_B5_CTL (0x150)
#define LPASS_CDC_IIR1_GAIN_B6_CTL (0x114)
#define LPASS_CDC_IIR2_GAIN_B6_CTL (0x154)
#define LPASS_CDC_IIR1_GAIN_B7_CTL (0x118)
#define LPASS_CDC_IIR2_GAIN_B7_CTL (0x158)
#define LPASS_CDC_IIR1_GAIN_B8_CTL (0x11C)
#define LPASS_CDC_IIR2_GAIN_B8_CTL (0x15C)
#define LPASS_CDC_IIR1_CTL (0x120)
#define LPASS_CDC_IIR2_CTL (0x160)
#define LPASS_CDC_IIR1_GAIN_TIMER_CTL (0x124)
#define LPASS_CDC_IIR2_GAIN_TIMER_CTL (0x164)
#define LPASS_CDC_IIR1_COEF_B1_CTL (0x128)
#define LPASS_CDC_IIR2_COEF_B1_CTL (0x168)
#define LPASS_CDC_IIR1_COEF_B2_CTL (0x12C)
#define LPASS_CDC_IIR2_COEF_B2_CTL (0x16C)
#define LPASS_CDC_CONN_RX1_B1_CTL (0x180)
#define LPASS_CDC_CONN_RX1_B2_CTL (0x184)
#define LPASS_CDC_CONN_RX1_B3_CTL (0x188)
#define LPASS_CDC_CONN_RX2_B1_CTL (0x18C)
#define LPASS_CDC_CONN_RX2_B2_CTL (0x190)
#define LPASS_CDC_CONN_RX2_B3_CTL (0x194)
#define LPASS_CDC_CONN_RX3_B1_CTL (0x198)
#define LPASS_CDC_CONN_RX3_B2_CTL (0x19C)
#define LPASS_CDC_CONN_TX_B1_CTL (0x1A0)
#define LPASS_CDC_CONN_EQ1_B1_CTL (0x1A8)
#define LPASS_CDC_CONN_EQ1_B2_CTL (0x1AC)
#define LPASS_CDC_CONN_EQ1_B3_CTL (0x1B0)
#define LPASS_CDC_CONN_EQ1_B4_CTL (0x1B4)
#define LPASS_CDC_CONN_EQ2_B1_CTL (0x1B8)
#define LPASS_CDC_CONN_EQ2_B2_CTL (0x1BC)
#define LPASS_CDC_CONN_EQ2_B3_CTL (0x1C0)
#define LPASS_CDC_CONN_EQ2_B4_CTL (0x1C4)
#define LPASS_CDC_CONN_TX_I2S_SD1_CTL (0x1C8)
#define LPASS_CDC_TX1_VOL_CTL_TIMER (0x280)
#define LPASS_CDC_TX2_VOL_CTL_TIMER (0x2A0)
#define LPASS_CDC_TX1_VOL_CTL_GAIN (0x284)
#define LPASS_CDC_TX2_VOL_CTL_GAIN (0x2A4)
#define LPASS_CDC_TX1_VOL_CTL_CFG (0x288)
#define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0)
#define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0)
#define LPASS_CDC_TX2_VOL_CTL_CFG (0x2A8)
#define LPASS_CDC_TX1_MUX_CTL (0x28C)
#define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4)
#define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT 4
#define TX_MUX_CTL_CF_NEG_3DB_4HZ (0x0 << 4)
#define TX_MUX_CTL_CF_NEG_3DB_75HZ (0x1 << 4)
#define TX_MUX_CTL_CF_NEG_3DB_150HZ (0x2 << 4)
#define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3)
#define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3)
#define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS 0
#define LPASS_CDC_TX2_MUX_CTL (0x2AC)
#define LPASS_CDC_TX1_CLK_FS_CTL (0x290)
#define LPASS_CDC_TX2_CLK_FS_CTL (0x2B0)
#define LPASS_CDC_TX1_DMIC_CTL (0x294)
#define LPASS_CDC_TX2_DMIC_CTL (0x2B4)
#define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0)
#define TXN_DMIC_CTL_CLK_SEL_DIV2 0x0
#define TXN_DMIC_CTL_CLK_SEL_DIV3 0x1
#define TXN_DMIC_CTL_CLK_SEL_DIV4 0x2
#define TXN_DMIC_CTL_CLK_SEL_DIV6 0x3
#define TXN_DMIC_CTL_CLK_SEL_DIV16 0x4
#define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_48000)
#define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
/* Codec supports 2 IIR filters */
enum {
IIR1 = 0,
IIR2,
IIR_MAX,
};
/* Codec supports 5 bands */
enum {
BAND1 = 0,
BAND2,
BAND3,
BAND4,
BAND5,
BAND_MAX,
};
#define WCD_IIR_FILTER_SIZE (sizeof(u32)*BAND_MAX)
#define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = wcd_iir_filter_info, \
.get = msm8x16_wcd_get_iir_band_audio_mixer, \
.put = msm8x16_wcd_put_iir_band_audio_mixer, \
.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
.iir_idx = iidx, \
.band_idx = bidx, \
.bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
} \
}
struct wcd_iir_filter_ctl {
unsigned int iir_idx;
unsigned int band_idx;
struct soc_bytes_ext bytes_ext;
};
struct msm8916_wcd_digital_priv {
struct clk *ahbclk, *mclk;
};
static const unsigned long rx_gain_reg[] = {
LPASS_CDC_RX1_VOL_CTL_B2_CTL,
LPASS_CDC_RX2_VOL_CTL_B2_CTL,
LPASS_CDC_RX3_VOL_CTL_B2_CTL,
};
static const unsigned long tx_gain_reg[] = {
LPASS_CDC_TX1_VOL_CTL_GAIN,
LPASS_CDC_TX2_VOL_CTL_GAIN,
};
static const char *const rx_mix1_text[] = {
"ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
};
static const char * const rx_mix2_text[] = {
"ZERO", "IIR1", "IIR2"
};
static const char *const dec_mux_text[] = {
"ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
};
static const char *const cic_mux_text[] = { "AMIC", "DMIC" };
/* RX1 MIX1 */
static const struct soc_enum rx_mix1_inp_enum[] = {
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
};
/* RX2 MIX1 */
static const struct soc_enum rx2_mix1_inp_enum[] = {
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text),
};
/* RX3 MIX1 */
static const struct soc_enum rx3_mix1_inp_enum[] = {
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text),
};
/* RX1 MIX2 */
static const struct soc_enum rx_mix2_inp1_chain_enum =
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B3_CTL,
0, 3, rx_mix2_text);
/* RX2 MIX2 */
static const struct soc_enum rx2_mix2_inp1_chain_enum =
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B3_CTL,
0, 3, rx_mix2_text);
/* DEC */
static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
/* CIC */
static const struct soc_enum cic1_mux_enum = SOC_ENUM_SINGLE(
LPASS_CDC_TX1_MUX_CTL, 0, 2, cic_mux_text);
static const struct soc_enum cic2_mux_enum = SOC_ENUM_SINGLE(
LPASS_CDC_TX2_MUX_CTL, 0, 2, cic_mux_text);
/* RDAC2 MUX */
static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
"DEC1 MUX Mux", dec1_mux_enum);
static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
"DEC2 MUX Mux", dec2_mux_enum);
static const struct snd_kcontrol_new cic1_mux = SOC_DAPM_ENUM(
"CIC1 MUX Mux", cic1_mux_enum);
static const struct snd_kcontrol_new cic2_mux = SOC_DAPM_ENUM(
"CIC2 MUX Mux", cic2_mux_enum);
static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
"RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
"RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
"RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
"RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
"RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
"RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
"RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
"RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
"RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
static const struct snd_kcontrol_new rx1_mix2_inp1_mux = SOC_DAPM_ENUM(
"RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
static const struct snd_kcontrol_new rx2_mix2_inp1_mux = SOC_DAPM_ENUM(
"RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
/* Digital Gain control -84 dB to +40 dB in 1 dB steps */
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
/* Cutoff Freq for High Pass Filter at -3dB */
static const char * const hpf_cutoff_text[] = {
"4Hz", "75Hz", "150Hz",
};
static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
hpf_cutoff_text);
static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
hpf_cutoff_text);
/* cut off for dc blocker inside rx chain */
static const char * const dc_blocker_cutoff_text[] = {
"4Hz", "75Hz", "150Hz",
};
static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
dc_blocker_cutoff_text);
static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
dc_blocker_cutoff_text);
static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
dc_blocker_cutoff_text);
static int msm8x16_wcd_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
int value = 0, reg = 0;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (w->shift == 0)
reg = LPASS_CDC_IIR1_GAIN_B1_CTL;
else if (w->shift == 1)
reg = LPASS_CDC_IIR2_GAIN_B1_CTL;
value = snd_soc_component_read(component, reg);
snd_soc_component_write(component, reg, value);
break;
default:
break;
}
return 0;
}
static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
int iir_idx, int band_idx,
int coeff_idx)
{
uint32_t value = 0;
/* Address does not automatically update if reading */
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t)) & 0x7F);
value |= snd_soc_component_read(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx));
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 1) & 0x7F);
value |= (snd_soc_component_read(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8);
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 2) & 0x7F);
value |= (snd_soc_component_read(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16);
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 3) & 0x7F);
/* Mask bits top 2 bits since they are reserved */
value |= ((snd_soc_component_read(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) << 24);
return value;
}
static int msm8x16_wcd_get_iir_band_audio_mixer(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
int iir_idx = ctl->iir_idx;
int band_idx = ctl->band_idx;
u32 coeff[BAND_MAX];
coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
return 0;
}
static void set_iir_band_coeff(struct snd_soc_component *component,
int iir_idx, int band_idx,
uint32_t value)
{
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
(value & 0xFF));
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
(value >> 8) & 0xFF);
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
(value >> 16) & 0xFF);
/* Mask top 2 bits, 7-8 are reserved */
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
(value >> 24) & 0x3F);
}
static int msm8x16_wcd_put_iir_band_audio_mixer(
struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
int iir_idx = ctl->iir_idx;
int band_idx = ctl->band_idx;
u32 coeff[BAND_MAX];
memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
/* Mask top bit it is reserved */
/* Updates addr automatically for each B2 write */
snd_soc_component_write(component,
(LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
(band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
return 0;
}
static int wcd_iir_filter_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *ucontrol)
{
struct wcd_iir_filter_ctl *ctl =
(struct wcd_iir_filter_ctl *)kcontrol->private_value;
struct soc_bytes_ext *params = &ctl->bytes_ext;
ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ucontrol->count = params->max;
return 0;
}
static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
-84, 40, digital_gain),
SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
SOC_SINGLE("IIR1 Band1 Switch", LPASS_CDC_IIR1_CTL, 0, 1, 0),
SOC_SINGLE("IIR1 Band2 Switch", LPASS_CDC_IIR1_CTL, 1, 1, 0),
SOC_SINGLE("IIR1 Band3 Switch", LPASS_CDC_IIR1_CTL, 2, 1, 0),
SOC_SINGLE("IIR1 Band4 Switch", LPASS_CDC_IIR1_CTL, 3, 1, 0),
SOC_SINGLE("IIR1 Band5 Switch", LPASS_CDC_IIR1_CTL, 4, 1, 0),
SOC_SINGLE("IIR2 Band1 Switch", LPASS_CDC_IIR2_CTL, 0, 1, 0),
SOC_SINGLE("IIR2 Band2 Switch", LPASS_CDC_IIR2_CTL, 1, 1, 0),
SOC_SINGLE("IIR2 Band3 Switch", LPASS_CDC_IIR2_CTL, 2, 1, 0),
SOC_SINGLE("IIR2 Band4 Switch", LPASS_CDC_IIR2_CTL, 3, 1, 0),
SOC_SINGLE("IIR2 Band5 Switch", LPASS_CDC_IIR2_CTL, 4, 1, 0),
WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
WCD_IIR_FILTER_CTL("IIR2 Band1", IIR2, BAND1),
WCD_IIR_FILTER_CTL("IIR2 Band2", IIR2, BAND2),
WCD_IIR_FILTER_CTL("IIR2 Band3", IIR2, BAND3),
WCD_IIR_FILTER_CTL("IIR2 Band4", IIR2, BAND4),
WCD_IIR_FILTER_CTL("IIR2 Band5", IIR2, BAND5),
SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", LPASS_CDC_IIR1_GAIN_B1_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", LPASS_CDC_IIR1_GAIN_B2_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", LPASS_CDC_IIR1_GAIN_B3_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR1 INP4 Volume", LPASS_CDC_IIR1_GAIN_B4_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR2 INP1 Volume", LPASS_CDC_IIR2_GAIN_B1_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR2 INP2 Volume", LPASS_CDC_IIR2_GAIN_B2_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR2 INP3 Volume", LPASS_CDC_IIR2_GAIN_B3_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("IIR2 INP4 Volume", LPASS_CDC_IIR2_GAIN_B4_CTL,
-84, 40, digital_gain),
};
static int msm8916_wcd_digital_enable_interpolator(
struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* apply the digital gain after the interpolator is enabled */
usleep_range(10000, 10100);
snd_soc_component_write(component, rx_gain_reg[w->shift],
snd_soc_component_read(component, rx_gain_reg[w->shift]));
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
1 << w->shift, 1 << w->shift);
snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
1 << w->shift, 0x0);
break;
}
return 0;
}
static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int decimator = w->shift + 1;
u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
u8 dec_hpf_cut_of_freq;
dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Enable TX digital mute */
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
TX_VOL_CTL_CFG_MUTE_EN_MASK,
TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
dec_hpf_cut_of_freq = snd_soc_component_read(component, tx_mux_ctl_reg) &
TX_MUX_CTL_CUT_OFF_FREQ_MASK;
dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
/* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
snd_soc_component_update_bits(component, tx_mux_ctl_reg,
TX_MUX_CTL_CUT_OFF_FREQ_MASK,
TX_MUX_CTL_CF_NEG_3DB_150HZ);
}
break;
case SND_SOC_DAPM_POST_PMU:
/* enable HPF */
snd_soc_component_update_bits(component, tx_mux_ctl_reg,
TX_MUX_CTL_HPF_BP_SEL_MASK,
TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
/* apply the digital gain after the decimator is enabled */
snd_soc_component_write(component, tx_gain_reg[w->shift],
snd_soc_component_read(component, tx_gain_reg[w->shift]));
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
TX_VOL_CTL_CFG_MUTE_EN_MASK,
TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
snd_soc_component_update_bits(component, tx_mux_ctl_reg,
TX_MUX_CTL_HPF_BP_SEL_MASK,
TX_MUX_CTL_HPF_BP_SEL_BYPASS);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift,
1 << w->shift);
snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift, 0x0);
snd_soc_component_update_bits(component, tx_mux_ctl_reg,
TX_MUX_CTL_HPF_BP_SEL_MASK,
TX_MUX_CTL_HPF_BP_SEL_BYPASS);
snd_soc_component_update_bits(component, tx_vol_ctl_reg,
TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
break;
}
return 0;
}
static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
unsigned int dmic;
int ret;
/* get dmic number out of widget name */
char *dmic_num = strpbrk(w->name, "12");
if (dmic_num == NULL) {
dev_err(component->dev, "Invalid DMIC\n");
return -EINVAL;
}
ret = kstrtouint(dmic_num, 10, &dmic);
if (ret < 0 || dmic > 2) {
dev_err(component->dev, "Invalid DMIC line on the component\n");
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, LPASS_CDC_CLK_DMIC_B1_CTL,
DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
switch (dmic) {
case 1:
snd_soc_component_update_bits(component, LPASS_CDC_TX1_DMIC_CTL,
TXN_DMIC_CTL_CLK_SEL_MASK,
TXN_DMIC_CTL_CLK_SEL_DIV3);
break;
case 2:
snd_soc_component_update_bits(component, LPASS_CDC_TX2_DMIC_CTL,
TXN_DMIC_CTL_CLK_SEL_MASK,
TXN_DMIC_CTL_CLK_SEL_DIV3);
break;
}
break;
}
return 0;
}
static const char * const iir_inp1_text[] = {
"ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
};
static const struct soc_enum iir1_inp1_mux_enum =
SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ1_B1_CTL,
0, 6, iir_inp1_text);
static const struct soc_enum iir2_inp1_mux_enum =
SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ2_B1_CTL,
0, 6, iir_inp1_text);
static const struct snd_kcontrol_new iir1_inp1_mux =
SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
static const struct snd_kcontrol_new iir2_inp1_mux =
SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
/*RX stuff */
SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("PDM_RX1"),
SND_SOC_DAPM_OUTPUT("PDM_RX2"),
SND_SOC_DAPM_OUTPUT("PDM_RX3"),
SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Interpolator */
SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
0, msm8916_wcd_digital_enable_interpolator,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
0, msm8916_wcd_digital_enable_interpolator,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
0, msm8916_wcd_digital_enable_interpolator,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx_mix1_inp1_mux),
SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx_mix1_inp2_mux),
SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
&rx_mix1_inp3_mux),
SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx2_mix1_inp1_mux),
SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx2_mix1_inp2_mux),
SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
&rx2_mix1_inp3_mux),
SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
&rx3_mix1_inp1_mux),
SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx3_mix1_inp2_mux),
SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
&rx3_mix1_inp3_mux),
SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
&rx1_mix2_inp1_mux),
SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
&rx2_mix2_inp1_mux),
SND_SOC_DAPM_MUX("CIC1 MUX", SND_SOC_NOPM, 0, 0, &cic1_mux),
SND_SOC_DAPM_MUX("CIC2 MUX", SND_SOC_NOPM, 0, 0, &cic2_mux),
/* TX */
SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
&dec1_mux, msm8916_wcd_digital_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
&dec2_mux, msm8916_wcd_digital_enable_dec,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
/* Digital Mic Inputs */
SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
msm8916_wcd_digital_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
msm8916_wcd_digital_enable_dmic,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
/* Connectivity Clock */
SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
NULL, 0),
SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("Digital Mic2", NULL),
/* Sidetone */
SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
SND_SOC_DAPM_PGA_E("IIR1", LPASS_CDC_CLK_SD_CTL, 0, 0, NULL, 0,
msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
SND_SOC_DAPM_PGA_E("IIR2", LPASS_CDC_CLK_SD_CTL, 1, 0, NULL, 0,
msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
};
static int msm8916_wcd_digital_get_clks(struct platform_device *pdev,
struct msm8916_wcd_digital_priv *priv)
{
struct device *dev = &pdev->dev;
priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
if (IS_ERR(priv->ahbclk)) {
dev_err(dev, "failed to get ahbix clk\n");
return PTR_ERR(priv->ahbclk);
}
priv->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(priv->mclk)) {
dev_err(dev, "failed to get mclk\n");
return PTR_ERR(priv->mclk);
}
return 0;
}
static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component)
{
struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(component->dev);
snd_soc_component_set_drvdata(component, priv);
return 0;
}
static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source,
unsigned int freq, int dir)
{
struct msm8916_wcd_digital_priv *p = dev_get_drvdata(component->dev);
return clk_set_rate(p->mclk, freq);
}
static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
u8 tx_fs_rate;
u8 rx_fs_rate;
switch (params_rate(params)) {
case 8000:
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
break;
case 16000:
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
break;
case 32000:
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
break;
case 48000:
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
break;
default:
dev_err(dai->component->dev, "Invalid sampling rate %d\n",
params_rate(params));
return -EINVAL;
}
switch (substream->stream) {
case SNDRV_PCM_STREAM_CAPTURE:
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
break;
case SNDRV_PCM_STREAM_PLAYBACK:
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
break;
default:
return -EINVAL;
}
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
TX_I2S_CTL_TX_I2S_MODE_MASK,
TX_I2S_CTL_TX_I2S_MODE_16);
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
RX_I2S_CTL_RX_I2S_MODE_MASK,
RX_I2S_CTL_RX_I2S_MODE_16);
break;
case SNDRV_PCM_FORMAT_S32_LE:
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
TX_I2S_CTL_TX_I2S_MODE_MASK,
TX_I2S_CTL_TX_I2S_MODE_32);
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
RX_I2S_CTL_RX_I2S_MODE_MASK,
RX_I2S_CTL_RX_I2S_MODE_32);
break;
default:
dev_err(dai->dev, "%s: wrong format selected\n", __func__);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
{"I2S RX1", NULL, "AIF1 Playback"},
{"I2S RX2", NULL, "AIF1 Playback"},
{"I2S RX3", NULL, "AIF1 Playback"},
{"AIF1 Capture", NULL, "I2S TX1"},
{"AIF1 Capture", NULL, "I2S TX2"},
{"AIF1 Capture", NULL, "I2S TX3"},
{"CIC1 MUX", "DMIC", "DEC1 MUX"},
{"CIC1 MUX", "AMIC", "DEC1 MUX"},
{"CIC2 MUX", "DMIC", "DEC2 MUX"},
{"CIC2 MUX", "AMIC", "DEC2 MUX"},
/* Decimator Inputs */
{"DEC1 MUX", "DMIC1", "DMIC1"},
{"DEC1 MUX", "DMIC2", "DMIC2"},
{"DEC1 MUX", "ADC1", "ADC1"},
{"DEC1 MUX", "ADC2", "ADC2"},
{"DEC1 MUX", "ADC3", "ADC3"},
{"DEC1 MUX", NULL, "CDC_CONN"},
{"DEC2 MUX", "DMIC1", "DMIC1"},
{"DEC2 MUX", "DMIC2", "DMIC2"},
{"DEC2 MUX", "ADC1", "ADC1"},
{"DEC2 MUX", "ADC2", "ADC2"},
{"DEC2 MUX", "ADC3", "ADC3"},
{"DEC2 MUX", NULL, "CDC_CONN"},
{"DMIC1", NULL, "DMIC_CLK"},
{"DMIC2", NULL, "DMIC_CLK"},
{"I2S TX1", NULL, "CIC1 MUX"},
{"I2S TX2", NULL, "CIC2 MUX"},
{"I2S TX1", NULL, "TX_I2S_CLK"},
{"I2S TX2", NULL, "TX_I2S_CLK"},
{"TX_I2S_CLK", NULL, "MCLK"},
{"TX_I2S_CLK", NULL, "PDM_CLK"},
{"ADC1", NULL, "LPASS_PDM_TX"},
{"ADC2", NULL, "LPASS_PDM_TX"},
{"ADC3", NULL, "LPASS_PDM_TX"},
{"I2S RX1", NULL, "RX_I2S_CLK"},
{"I2S RX2", NULL, "RX_I2S_CLK"},
{"I2S RX3", NULL, "RX_I2S_CLK"},
{"RX_I2S_CLK", NULL, "PDM_CLK"},
{"RX_I2S_CLK", NULL, "MCLK"},
{"RX_I2S_CLK", NULL, "CDC_CONN"},
/* RX1 PATH.. */
{"PDM_RX1", NULL, "RX1 INT"},
{"RX1 INT", NULL, "RX1 MIX1"},
{"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
{"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
{"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
{"RX1 MIX1 INP1", "RX1", "I2S RX1"},
{"RX1 MIX1 INP1", "RX2", "I2S RX2"},
{"RX1 MIX1 INP1", "RX3", "I2S RX3"},
{"RX1 MIX1 INP1", "IIR1", "IIR1"},
{"RX1 MIX1 INP1", "IIR2", "IIR2"},
{"RX1 MIX1 INP2", "RX1", "I2S RX1"},
{"RX1 MIX1 INP2", "RX2", "I2S RX2"},
{"RX1 MIX1 INP2", "RX3", "I2S RX3"},
{"RX1 MIX1 INP2", "IIR1", "IIR1"},
{"RX1 MIX1 INP2", "IIR2", "IIR2"},
{"RX1 MIX1 INP3", "RX1", "I2S RX1"},
{"RX1 MIX1 INP3", "RX2", "I2S RX2"},
{"RX1 MIX1 INP3", "RX3", "I2S RX3"},
/* RX2 PATH */
{"PDM_RX2", NULL, "RX2 INT"},
{"RX2 INT", NULL, "RX2 MIX1"},
{"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
{"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
{"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
{"RX2 MIX1 INP1", "RX1", "I2S RX1"},
{"RX2 MIX1 INP1", "RX2", "I2S RX2"},
{"RX2 MIX1 INP1", "RX3", "I2S RX3"},
{"RX2 MIX1 INP1", "IIR1", "IIR1"},
{"RX2 MIX1 INP1", "IIR2", "IIR2"},
{"RX2 MIX1 INP2", "RX1", "I2S RX1"},
{"RX2 MIX1 INP2", "RX2", "I2S RX2"},
{"RX2 MIX1 INP2", "RX3", "I2S RX3"},
{"RX2 MIX1 INP1", "IIR1", "IIR1"},
{"RX2 MIX1 INP1", "IIR2", "IIR2"},
{"RX2 MIX1 INP3", "RX1", "I2S RX1"},
{"RX2 MIX1 INP3", "RX2", "I2S RX2"},
{"RX2 MIX1 INP3", "RX3", "I2S RX3"},
/* RX3 PATH */
{"PDM_RX3", NULL, "RX3 INT"},
{"RX3 INT", NULL, "RX3 MIX1"},
{"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
{"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
{"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
{"RX3 MIX1 INP1", "RX1", "I2S RX1"},
{"RX3 MIX1 INP1", "RX2", "I2S RX2"},
{"RX3 MIX1 INP1", "RX3", "I2S RX3"},
{"RX3 MIX1 INP1", "IIR1", "IIR1"},
{"RX3 MIX1 INP1", "IIR2", "IIR2"},
{"RX3 MIX1 INP2", "RX1", "I2S RX1"},
{"RX3 MIX1 INP2", "RX2", "I2S RX2"},
{"RX3 MIX1 INP2", "RX3", "I2S RX3"},
{"RX3 MIX1 INP2", "IIR1", "IIR1"},
{"RX3 MIX1 INP2", "IIR2", "IIR2"},
{"RX1 MIX2 INP1", "IIR1", "IIR1"},
{"RX2 MIX2 INP1", "IIR1", "IIR1"},
{"RX1 MIX2 INP1", "IIR2", "IIR2"},
{"RX2 MIX2 INP1", "IIR2", "IIR2"},
{"IIR1", NULL, "IIR1 INP1 MUX"},
{"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
{"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
{"IIR2", NULL, "IIR2 INP1 MUX"},
{"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
{"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
{"RX3 MIX1 INP3", "RX1", "I2S RX1"},
{"RX3 MIX1 INP3", "RX2", "I2S RX2"},
{"RX3 MIX1 INP3", "RX3", "I2S RX3"},
};
static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct msm8916_wcd_digital_priv *msm8916_wcd;
unsigned long mclk_rate;
msm8916_wcd = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, LPASS_CDC_CLK_MCLK_CTL,
MCLK_CTL_MCLK_EN_MASK,
MCLK_CTL_MCLK_EN_ENABLE);
snd_soc_component_update_bits(component, LPASS_CDC_CLK_PDM_CTL,
LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
mclk_rate = clk_get_rate(msm8916_wcd->mclk);
switch (mclk_rate) {
case 12288000:
snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
TOP_CTL_DIG_MCLK_FREQ_MASK,
TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
break;
case 9600000:
snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
TOP_CTL_DIG_MCLK_FREQ_MASK,
TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
break;
default:
dev_err(component->dev, "Invalid mclk rate %ld\n", mclk_rate);
break;
}
return 0;
}
static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_PDM_CTL,
LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
}
static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
.startup = msm8916_wcd_digital_startup,
.shutdown = msm8916_wcd_digital_shutdown,
.hw_params = msm8916_wcd_digital_hw_params,
};
static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
[0] = {
.name = "msm8916_wcd_digital_i2s_rx1",
.id = 0,
.playback = {
.stream_name = "AIF1 Playback",
.rates = MSM8916_WCD_DIGITAL_RATES,
.formats = MSM8916_WCD_DIGITAL_FORMATS,
.channels_min = 1,
.channels_max = 3,
},
.ops = &msm8916_wcd_digital_dai_ops,
},
[1] = {
.name = "msm8916_wcd_digital_i2s_tx1",
.id = 1,
.capture = {
.stream_name = "AIF1 Capture",
.rates = MSM8916_WCD_DIGITAL_RATES,
.formats = MSM8916_WCD_DIGITAL_FORMATS,
.channels_min = 1,
.channels_max = 4,
},
.ops = &msm8916_wcd_digital_dai_ops,
},
};
static const struct snd_soc_component_driver msm8916_wcd_digital = {
.probe = msm8916_wcd_digital_component_probe,
.set_sysclk = msm8916_wcd_digital_component_set_sysclk,
.controls = msm8916_wcd_digital_snd_controls,
.num_controls = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
.dapm_widgets = msm8916_wcd_digital_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
.dapm_routes = msm8916_wcd_digital_audio_map,
.num_dapm_routes = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config msm8916_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = LPASS_CDC_TX2_DMIC_CTL,
.cache_type = REGCACHE_FLAT,
};
static int msm8916_wcd_digital_probe(struct platform_device *pdev)
{
struct msm8916_wcd_digital_priv *priv;
struct device *dev = &pdev->dev;
void __iomem *base;
struct regmap *digital_map;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
digital_map =
devm_regmap_init_mmio(&pdev->dev, base,
&msm8916_codec_regmap_config);
if (IS_ERR(digital_map))
return PTR_ERR(digital_map);
ret = msm8916_wcd_digital_get_clks(pdev, priv);
if (ret < 0)
return ret;
ret = clk_prepare_enable(priv->ahbclk);
if (ret < 0) {
dev_err(dev, "failed to enable ahbclk %d\n", ret);
return ret;
}
ret = clk_prepare_enable(priv->mclk);
if (ret < 0) {
dev_err(dev, "failed to enable mclk %d\n", ret);
goto err_clk;
}
dev_set_drvdata(dev, priv);
ret = devm_snd_soc_register_component(dev, &msm8916_wcd_digital,
msm8916_wcd_digital_dai,
ARRAY_SIZE(msm8916_wcd_digital_dai));
if (ret)
goto err_mclk;
return 0;
err_mclk:
clk_disable_unprepare(priv->mclk);
err_clk:
clk_disable_unprepare(priv->ahbclk);
return ret;
}
static void msm8916_wcd_digital_remove(struct platform_device *pdev)
{
struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(priv->mclk);
clk_disable_unprepare(priv->ahbclk);
}
static const struct of_device_id msm8916_wcd_digital_match_table[] = {
{ .compatible = "qcom,msm8916-wcd-digital-codec" },
{ }
};
MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
static struct platform_driver msm8916_wcd_digital_driver = {
.driver = {
.name = "msm8916-wcd-digital-codec",
.of_match_table = msm8916_wcd_digital_match_table,
},
.probe = msm8916_wcd_digital_probe,
.remove_new = msm8916_wcd_digital_remove,
};
module_platform_driver(msm8916_wcd_digital_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]>");
MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/msm8916-wcd-digital.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MAX9768 AMP driver
*
* Copyright (C) 2011, 2012 by Wolfram Sang, Pengutronix e.K.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/max9768.h>
/* "Registers" */
#define MAX9768_VOL 0
#define MAX9768_CTRL 3
/* Commands */
#define MAX9768_CTRL_PWM 0x15
#define MAX9768_CTRL_FILTERLESS 0x16
struct max9768 {
struct regmap *regmap;
int mute_gpio;
int shdn_gpio;
u32 flags;
};
static const struct reg_default max9768_default_regs[] = {
{ 0, 0 },
{ 3, MAX9768_CTRL_FILTERLESS},
};
static int max9768_get_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct max9768 *max9768 = snd_soc_component_get_drvdata(c);
int val = gpio_get_value_cansleep(max9768->mute_gpio);
ucontrol->value.integer.value[0] = !val;
return 0;
}
static int max9768_set_gpio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
struct max9768 *max9768 = snd_soc_component_get_drvdata(c);
gpio_set_value_cansleep(max9768->mute_gpio, !ucontrol->value.integer.value[0]);
return 0;
}
static const DECLARE_TLV_DB_RANGE(volume_tlv,
0, 0, TLV_DB_SCALE_ITEM(-16150, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(-9280, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(-9030, 0, 0),
3, 3, TLV_DB_SCALE_ITEM(-8680, 0, 0),
4, 4, TLV_DB_SCALE_ITEM(-8430, 0, 0),
5, 5, TLV_DB_SCALE_ITEM(-8080, 0, 0),
6, 6, TLV_DB_SCALE_ITEM(-7830, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(-7470, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(-7220, 0, 0),
9, 9, TLV_DB_SCALE_ITEM(-6870, 0, 0),
10, 10, TLV_DB_SCALE_ITEM(-6620, 0, 0),
11, 11, TLV_DB_SCALE_ITEM(-6270, 0, 0),
12, 12, TLV_DB_SCALE_ITEM(-6020, 0, 0),
13, 13, TLV_DB_SCALE_ITEM(-5670, 0, 0),
14, 14, TLV_DB_SCALE_ITEM(-5420, 0, 0),
15, 17, TLV_DB_SCALE_ITEM(-5060, 250, 0),
18, 18, TLV_DB_SCALE_ITEM(-4370, 0, 0),
19, 19, TLV_DB_SCALE_ITEM(-4210, 0, 0),
20, 20, TLV_DB_SCALE_ITEM(-3960, 0, 0),
21, 21, TLV_DB_SCALE_ITEM(-3760, 0, 0),
22, 22, TLV_DB_SCALE_ITEM(-3600, 0, 0),
23, 23, TLV_DB_SCALE_ITEM(-3340, 0, 0),
24, 24, TLV_DB_SCALE_ITEM(-3150, 0, 0),
25, 25, TLV_DB_SCALE_ITEM(-2980, 0, 0),
26, 26, TLV_DB_SCALE_ITEM(-2720, 0, 0),
27, 27, TLV_DB_SCALE_ITEM(-2520, 0, 0),
28, 30, TLV_DB_SCALE_ITEM(-2350, 190, 0),
31, 31, TLV_DB_SCALE_ITEM(-1750, 0, 0),
32, 34, TLV_DB_SCALE_ITEM(-1640, 100, 0),
35, 37, TLV_DB_SCALE_ITEM(-1310, 110, 0),
38, 39, TLV_DB_SCALE_ITEM(-990, 100, 0),
40, 40, TLV_DB_SCALE_ITEM(-710, 0, 0),
41, 41, TLV_DB_SCALE_ITEM(-600, 0, 0),
42, 42, TLV_DB_SCALE_ITEM(-500, 0, 0),
43, 43, TLV_DB_SCALE_ITEM(-340, 0, 0),
44, 44, TLV_DB_SCALE_ITEM(-190, 0, 0),
45, 45, TLV_DB_SCALE_ITEM(-50, 0, 0),
46, 46, TLV_DB_SCALE_ITEM(50, 0, 0),
47, 50, TLV_DB_SCALE_ITEM(120, 40, 0),
51, 57, TLV_DB_SCALE_ITEM(290, 50, 0),
58, 58, TLV_DB_SCALE_ITEM(650, 0, 0),
59, 62, TLV_DB_SCALE_ITEM(700, 60, 0),
63, 63, TLV_DB_SCALE_ITEM(950, 0, 0)
);
static const struct snd_kcontrol_new max9768_volume[] = {
SOC_SINGLE_TLV("Playback Volume", MAX9768_VOL, 0, 63, 0, volume_tlv),
};
static const struct snd_kcontrol_new max9768_mute[] = {
SOC_SINGLE_BOOL_EXT("Playback Switch", 0, max9768_get_gpio, max9768_set_gpio),
};
static const struct snd_soc_dapm_widget max9768_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_OUTPUT("OUT+"),
SND_SOC_DAPM_OUTPUT("OUT-"),
};
static const struct snd_soc_dapm_route max9768_dapm_routes[] = {
{ "OUT+", NULL, "IN" },
{ "OUT-", NULL, "IN" },
};
static int max9768_probe(struct snd_soc_component *component)
{
struct max9768 *max9768 = snd_soc_component_get_drvdata(component);
int ret;
if (max9768->flags & MAX9768_FLAG_CLASSIC_PWM) {
ret = regmap_write(max9768->regmap, MAX9768_CTRL,
MAX9768_CTRL_PWM);
if (ret)
return ret;
}
if (gpio_is_valid(max9768->mute_gpio)) {
ret = snd_soc_add_component_controls(component, max9768_mute,
ARRAY_SIZE(max9768_mute));
if (ret)
return ret;
}
return 0;
}
static const struct snd_soc_component_driver max9768_component_driver = {
.probe = max9768_probe,
.controls = max9768_volume,
.num_controls = ARRAY_SIZE(max9768_volume),
.dapm_widgets = max9768_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max9768_dapm_widgets),
.dapm_routes = max9768_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(max9768_dapm_routes),
};
static const struct regmap_config max9768_i2c_regmap_config = {
.reg_bits = 2,
.val_bits = 6,
.max_register = 3,
.reg_defaults = max9768_default_regs,
.num_reg_defaults = ARRAY_SIZE(max9768_default_regs),
.cache_type = REGCACHE_RBTREE,
};
static int max9768_i2c_probe(struct i2c_client *client)
{
struct max9768 *max9768;
struct max9768_pdata *pdata = client->dev.platform_data;
int err;
max9768 = devm_kzalloc(&client->dev, sizeof(*max9768), GFP_KERNEL);
if (!max9768)
return -ENOMEM;
if (pdata) {
/* Mute on powerup to avoid clicks */
err = devm_gpio_request_one(&client->dev, pdata->mute_gpio,
GPIOF_INIT_HIGH, "MAX9768 Mute");
max9768->mute_gpio = err ?: pdata->mute_gpio;
/* Activate chip by releasing shutdown, enables I2C */
err = devm_gpio_request_one(&client->dev, pdata->shdn_gpio,
GPIOF_INIT_HIGH, "MAX9768 Shutdown");
max9768->shdn_gpio = err ?: pdata->shdn_gpio;
max9768->flags = pdata->flags;
} else {
max9768->shdn_gpio = -EINVAL;
max9768->mute_gpio = -EINVAL;
}
i2c_set_clientdata(client, max9768);
max9768->regmap = devm_regmap_init_i2c(client, &max9768_i2c_regmap_config);
if (IS_ERR(max9768->regmap))
return PTR_ERR(max9768->regmap);
return devm_snd_soc_register_component(&client->dev,
&max9768_component_driver, NULL, 0);
}
static const struct i2c_device_id max9768_i2c_id[] = {
{ "max9768", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9768_i2c_id);
static struct i2c_driver max9768_i2c_driver = {
.driver = {
.name = "max9768",
},
.probe = max9768_i2c_probe,
.id_table = max9768_i2c_id,
};
module_i2c_driver(max9768_i2c_driver);
MODULE_AUTHOR("Wolfram Sang <[email protected]>");
MODULE_DESCRIPTION("ASoC MAX9768 amplifier driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/max9768.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADAU1372 codec
*
* Copyright 2016 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "adau1372.h"
static int adau1372_i2c_probe(struct i2c_client *client)
{
return adau1372_probe(&client->dev,
devm_regmap_init_i2c(client, &adau1372_regmap_config), NULL);
}
static const struct i2c_device_id adau1372_i2c_ids[] = {
{ "adau1372", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adau1372_i2c_ids);
static struct i2c_driver adau1372_i2c_driver = {
.driver = {
.name = "adau1372",
},
.probe = adau1372_i2c_probe,
.id_table = adau1372_i2c_ids,
};
module_i2c_driver(adau1372_i2c_driver);
MODULE_DESCRIPTION("ASoC ADAU1372 CODEC I2C driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/adau1372-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
*
* Copyright: 2014 Raumfeld GmbH
* Author: Sven Brandau <[email protected]>
*
* based on code from:
* Raumfeld GmbH
* Johannes Stezenbach <[email protected]>
* Wolfson Microelectronics PLC.
* Mark Brown <[email protected]>
* Freescale Semiconductor, Inc.
* Timur Tabi <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/sta350.h>
#include "sta350.h"
#define STA350_RATES (SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000)
#define STA350_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
/* Power-up register defaults */
static const struct reg_default sta350_regs[] = {
{ 0x0, 0x63 },
{ 0x1, 0x80 },
{ 0x2, 0xdf },
{ 0x3, 0x40 },
{ 0x4, 0xc2 },
{ 0x5, 0x5c },
{ 0x6, 0x00 },
{ 0x7, 0xff },
{ 0x8, 0x60 },
{ 0x9, 0x60 },
{ 0xa, 0x60 },
{ 0xb, 0x00 },
{ 0xc, 0x00 },
{ 0xd, 0x00 },
{ 0xe, 0x00 },
{ 0xf, 0x40 },
{ 0x10, 0x80 },
{ 0x11, 0x77 },
{ 0x12, 0x6a },
{ 0x13, 0x69 },
{ 0x14, 0x6a },
{ 0x15, 0x69 },
{ 0x16, 0x00 },
{ 0x17, 0x00 },
{ 0x18, 0x00 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x00 },
{ 0x1d, 0x00 },
{ 0x1e, 0x00 },
{ 0x1f, 0x00 },
{ 0x20, 0x00 },
{ 0x21, 0x00 },
{ 0x22, 0x00 },
{ 0x23, 0x00 },
{ 0x24, 0x00 },
{ 0x25, 0x00 },
{ 0x26, 0x00 },
{ 0x27, 0x2a },
{ 0x28, 0xc0 },
{ 0x29, 0xf3 },
{ 0x2a, 0x33 },
{ 0x2b, 0x00 },
{ 0x2c, 0x0c },
{ 0x31, 0x00 },
{ 0x36, 0x00 },
{ 0x37, 0x00 },
{ 0x38, 0x00 },
{ 0x39, 0x01 },
{ 0x3a, 0xee },
{ 0x3b, 0xff },
{ 0x3c, 0x7e },
{ 0x3d, 0xc0 },
{ 0x3e, 0x26 },
{ 0x3f, 0x00 },
{ 0x48, 0x00 },
{ 0x49, 0x00 },
{ 0x4a, 0x00 },
{ 0x4b, 0x04 },
{ 0x4c, 0x00 },
};
static const struct regmap_range sta350_write_regs_range[] = {
regmap_reg_range(STA350_CONFA, STA350_AUTO2),
regmap_reg_range(STA350_C1CFG, STA350_FDRC2),
regmap_reg_range(STA350_EQCFG, STA350_EVOLRES),
regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
};
static const struct regmap_range sta350_read_regs_range[] = {
regmap_reg_range(STA350_CONFA, STA350_AUTO2),
regmap_reg_range(STA350_C1CFG, STA350_STATUS),
regmap_reg_range(STA350_EQCFG, STA350_EVOLRES),
regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
};
static const struct regmap_range sta350_volatile_regs_range[] = {
regmap_reg_range(STA350_CFADDR2, STA350_CFUD),
regmap_reg_range(STA350_STATUS, STA350_STATUS),
};
static const struct regmap_access_table sta350_write_regs = {
.yes_ranges = sta350_write_regs_range,
.n_yes_ranges = ARRAY_SIZE(sta350_write_regs_range),
};
static const struct regmap_access_table sta350_read_regs = {
.yes_ranges = sta350_read_regs_range,
.n_yes_ranges = ARRAY_SIZE(sta350_read_regs_range),
};
static const struct regmap_access_table sta350_volatile_regs = {
.yes_ranges = sta350_volatile_regs_range,
.n_yes_ranges = ARRAY_SIZE(sta350_volatile_regs_range),
};
/* regulator power supply names */
static const char * const sta350_supply_names[] = {
"vdd-dig", /* digital supply, 3.3V */
"vdd-pll", /* pll supply, 3.3V */
"vcc" /* power amp supply, 5V - 26V */
};
/* codec private data */
struct sta350_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[ARRAY_SIZE(sta350_supply_names)];
struct sta350_platform_data *pdata;
unsigned int mclk;
unsigned int format;
u32 coef_shadow[STA350_COEF_COUNT];
int shutdown;
struct gpio_desc *gpiod_nreset;
struct gpio_desc *gpiod_power_down;
struct mutex coeff_lock;
};
static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
static const DECLARE_TLV_DB_SCALE(tone_tlv, -1200, 200, 0);
static const char * const sta350_drc_ac[] = {
"Anti-Clipping", "Dynamic Range Compression"
};
static const char * const sta350_auto_gc_mode[] = {
"User", "AC no clipping", "AC limited clipping (10%)",
"DRC nighttime listening mode"
};
static const char * const sta350_auto_xo_mode[] = {
"User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz",
"200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz",
"340Hz", "360Hz"
};
static const char * const sta350_binary_output[] = {
"FFX 3-state output - normal operation", "Binary output"
};
static const char * const sta350_limiter_select[] = {
"Limiter Disabled", "Limiter #1", "Limiter #2"
};
static const char * const sta350_limiter_attack_rate[] = {
"3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
"0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
"0.0645", "0.0564", "0.0501", "0.0451"
};
static const char * const sta350_limiter_release_rate[] = {
"0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
"0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
"0.0134", "0.0117", "0.0110", "0.0104"
};
static const char * const sta350_noise_shaper_type[] = {
"Third order", "Fourth order"
};
static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_attack_tlv,
0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
);
static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_release_tlv,
0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
);
static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_attack_tlv,
0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
);
static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_release_tlv,
0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
);
static SOC_ENUM_SINGLE_DECL(sta350_drc_ac_enum,
STA350_CONFD, STA350_CONFD_DRC_SHIFT,
sta350_drc_ac);
static SOC_ENUM_SINGLE_DECL(sta350_noise_shaper_enum,
STA350_CONFE, STA350_CONFE_NSBW_SHIFT,
sta350_noise_shaper_type);
static SOC_ENUM_SINGLE_DECL(sta350_auto_gc_enum,
STA350_AUTO1, STA350_AUTO1_AMGC_SHIFT,
sta350_auto_gc_mode);
static SOC_ENUM_SINGLE_DECL(sta350_auto_xo_enum,
STA350_AUTO2, STA350_AUTO2_XO_SHIFT,
sta350_auto_xo_mode);
static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch1_enum,
STA350_C1CFG, STA350_CxCFG_BO_SHIFT,
sta350_binary_output);
static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch2_enum,
STA350_C2CFG, STA350_CxCFG_BO_SHIFT,
sta350_binary_output);
static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch3_enum,
STA350_C3CFG, STA350_CxCFG_BO_SHIFT,
sta350_binary_output);
static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch1_enum,
STA350_C1CFG, STA350_CxCFG_LS_SHIFT,
sta350_limiter_select);
static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch2_enum,
STA350_C2CFG, STA350_CxCFG_LS_SHIFT,
sta350_limiter_select);
static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch3_enum,
STA350_C3CFG, STA350_CxCFG_LS_SHIFT,
sta350_limiter_select);
static SOC_ENUM_SINGLE_DECL(sta350_limiter1_attack_rate_enum,
STA350_L1AR, STA350_LxA_SHIFT,
sta350_limiter_attack_rate);
static SOC_ENUM_SINGLE_DECL(sta350_limiter2_attack_rate_enum,
STA350_L2AR, STA350_LxA_SHIFT,
sta350_limiter_attack_rate);
static SOC_ENUM_SINGLE_DECL(sta350_limiter1_release_rate_enum,
STA350_L1AR, STA350_LxR_SHIFT,
sta350_limiter_release_rate);
static SOC_ENUM_SINGLE_DECL(sta350_limiter2_release_rate_enum,
STA350_L2AR, STA350_LxR_SHIFT,
sta350_limiter_release_rate);
/*
* byte array controls for setting biquad, mixer, scaling coefficients;
* for biquads all five coefficients need to be set in one go,
* mixer and pre/postscale coefs can be set individually;
* each coef is 24bit, the bytes are ordered in the same way
* as given in the STA350 data sheet (big endian; b1, b2, a1, a2, b0)
*/
static int sta350_coefficient_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
int numcoef = kcontrol->private_value >> 16;
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = 3 * numcoef;
return 0;
}
static int sta350_coefficient_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
int numcoef = kcontrol->private_value >> 16;
int index = kcontrol->private_value & 0xffff;
unsigned int cfud, val;
int i, ret = 0;
mutex_lock(&sta350->coeff_lock);
/* preserve reserved bits in STA350_CFUD */
regmap_read(sta350->regmap, STA350_CFUD, &cfud);
cfud &= 0xf0;
/*
* chip documentation does not say if the bits are self clearing,
* so do it explicitly
*/
regmap_write(sta350->regmap, STA350_CFUD, cfud);
regmap_write(sta350->regmap, STA350_CFADDR2, index);
if (numcoef == 1) {
regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x04);
} else if (numcoef == 5) {
regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x08);
} else {
ret = -EINVAL;
goto exit_unlock;
}
for (i = 0; i < 3 * numcoef; i++) {
regmap_read(sta350->regmap, STA350_B1CF1 + i, &val);
ucontrol->value.bytes.data[i] = val;
}
exit_unlock:
mutex_unlock(&sta350->coeff_lock);
return ret;
}
static int sta350_coefficient_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
int numcoef = kcontrol->private_value >> 16;
int index = kcontrol->private_value & 0xffff;
unsigned int cfud;
int i;
/* preserve reserved bits in STA350_CFUD */
regmap_read(sta350->regmap, STA350_CFUD, &cfud);
cfud &= 0xf0;
/*
* chip documentation does not say if the bits are self clearing,
* so do it explicitly
*/
regmap_write(sta350->regmap, STA350_CFUD, cfud);
regmap_write(sta350->regmap, STA350_CFADDR2, index);
for (i = 0; i < numcoef && (index + i < STA350_COEF_COUNT); i++)
sta350->coef_shadow[index + i] =
(ucontrol->value.bytes.data[3 * i] << 16)
| (ucontrol->value.bytes.data[3 * i + 1] << 8)
| (ucontrol->value.bytes.data[3 * i + 2]);
for (i = 0; i < 3 * numcoef; i++)
regmap_write(sta350->regmap, STA350_B1CF1 + i,
ucontrol->value.bytes.data[i]);
if (numcoef == 1)
regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
else if (numcoef == 5)
regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x02);
else
return -EINVAL;
return 0;
}
static int sta350_sync_coef_shadow(struct snd_soc_component *component)
{
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
unsigned int cfud;
int i;
/* preserve reserved bits in STA350_CFUD */
regmap_read(sta350->regmap, STA350_CFUD, &cfud);
cfud &= 0xf0;
for (i = 0; i < STA350_COEF_COUNT; i++) {
regmap_write(sta350->regmap, STA350_CFADDR2, i);
regmap_write(sta350->regmap, STA350_B1CF1,
(sta350->coef_shadow[i] >> 16) & 0xff);
regmap_write(sta350->regmap, STA350_B1CF2,
(sta350->coef_shadow[i] >> 8) & 0xff);
regmap_write(sta350->regmap, STA350_B1CF3,
(sta350->coef_shadow[i]) & 0xff);
/*
* chip documentation does not say if the bits are
* self-clearing, so do it explicitly
*/
regmap_write(sta350->regmap, STA350_CFUD, cfud);
regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
}
return 0;
}
static int sta350_cache_sync(struct snd_soc_component *component)
{
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
unsigned int mute;
int rc;
/* mute during register sync */
regmap_read(sta350->regmap, STA350_CFUD, &mute);
regmap_write(sta350->regmap, STA350_MMUTE, mute | STA350_MMUTE_MMUTE);
sta350_sync_coef_shadow(component);
rc = regcache_sync(sta350->regmap);
regmap_write(sta350->regmap, STA350_MMUTE, mute);
return rc;
}
#define SINGLE_COEF(xname, index) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = sta350_coefficient_info, \
.get = sta350_coefficient_get,\
.put = sta350_coefficient_put, \
.private_value = index | (1 << 16) }
#define BIQUAD_COEFS(xname, index) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = sta350_coefficient_info, \
.get = sta350_coefficient_get,\
.put = sta350_coefficient_put, \
.private_value = index | (5 << 16) }
static const struct snd_kcontrol_new sta350_snd_controls[] = {
SOC_SINGLE_TLV("Master Volume", STA350_MVOL, 0, 0xff, 1, mvol_tlv),
/* VOL */
SOC_SINGLE_TLV("Ch1 Volume", STA350_C1VOL, 0, 0xff, 1, chvol_tlv),
SOC_SINGLE_TLV("Ch2 Volume", STA350_C2VOL, 0, 0xff, 1, chvol_tlv),
SOC_SINGLE_TLV("Ch3 Volume", STA350_C3VOL, 0, 0xff, 1, chvol_tlv),
/* CONFD */
SOC_SINGLE("High Pass Filter Bypass Switch",
STA350_CONFD, STA350_CONFD_HPB_SHIFT, 1, 1),
SOC_SINGLE("De-emphasis Filter Switch",
STA350_CONFD, STA350_CONFD_DEMP_SHIFT, 1, 0),
SOC_SINGLE("DSP Bypass Switch",
STA350_CONFD, STA350_CONFD_DSPB_SHIFT, 1, 0),
SOC_SINGLE("Post-scale Link Switch",
STA350_CONFD, STA350_CONFD_PSL_SHIFT, 1, 0),
SOC_SINGLE("Biquad Coefficient Link Switch",
STA350_CONFD, STA350_CONFD_BQL_SHIFT, 1, 0),
SOC_ENUM("Compressor/Limiter Switch", sta350_drc_ac_enum),
SOC_ENUM("Noise Shaper Bandwidth", sta350_noise_shaper_enum),
SOC_SINGLE("Zero-detect Mute Enable Switch",
STA350_CONFD, STA350_CONFD_ZDE_SHIFT, 1, 0),
SOC_SINGLE("Submix Mode Switch",
STA350_CONFD, STA350_CONFD_SME_SHIFT, 1, 0),
/* CONFE */
SOC_SINGLE("Zero Cross Switch", STA350_CONFE, STA350_CONFE_ZCE_SHIFT, 1, 0),
SOC_SINGLE("Soft Ramp Switch", STA350_CONFE, STA350_CONFE_SVE_SHIFT, 1, 0),
/* MUTE */
SOC_SINGLE("Master Switch", STA350_MMUTE, STA350_MMUTE_MMUTE_SHIFT, 1, 1),
SOC_SINGLE("Ch1 Switch", STA350_MMUTE, STA350_MMUTE_C1M_SHIFT, 1, 1),
SOC_SINGLE("Ch2 Switch", STA350_MMUTE, STA350_MMUTE_C2M_SHIFT, 1, 1),
SOC_SINGLE("Ch3 Switch", STA350_MMUTE, STA350_MMUTE_C3M_SHIFT, 1, 1),
/* AUTOx */
SOC_ENUM("Automode GC", sta350_auto_gc_enum),
SOC_ENUM("Automode XO", sta350_auto_xo_enum),
/* CxCFG */
SOC_SINGLE("Ch1 Tone Control Bypass Switch",
STA350_C1CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
SOC_SINGLE("Ch2 Tone Control Bypass Switch",
STA350_C2CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
SOC_SINGLE("Ch1 EQ Bypass Switch",
STA350_C1CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
SOC_SINGLE("Ch2 EQ Bypass Switch",
STA350_C2CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
SOC_SINGLE("Ch1 Master Volume Bypass Switch",
STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
SOC_SINGLE("Ch2 Master Volume Bypass Switch",
STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
SOC_SINGLE("Ch3 Master Volume Bypass Switch",
STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
SOC_ENUM("Ch1 Binary Output Select", sta350_binary_output_ch1_enum),
SOC_ENUM("Ch2 Binary Output Select", sta350_binary_output_ch2_enum),
SOC_ENUM("Ch3 Binary Output Select", sta350_binary_output_ch3_enum),
SOC_ENUM("Ch1 Limiter Select", sta350_limiter_ch1_enum),
SOC_ENUM("Ch2 Limiter Select", sta350_limiter_ch2_enum),
SOC_ENUM("Ch3 Limiter Select", sta350_limiter_ch3_enum),
/* TONE */
SOC_SINGLE_RANGE_TLV("Bass Tone Control Volume",
STA350_TONE, STA350_TONE_BTC_SHIFT, 1, 13, 0, tone_tlv),
SOC_SINGLE_RANGE_TLV("Treble Tone Control Volume",
STA350_TONE, STA350_TONE_TTC_SHIFT, 1, 13, 0, tone_tlv),
SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta350_limiter1_attack_rate_enum),
SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta350_limiter2_attack_rate_enum),
SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta350_limiter1_release_rate_enum),
SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta350_limiter2_release_rate_enum),
/*
* depending on mode, the attack/release thresholds have
* two different enum definitions; provide both
*/
SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)",
STA350_L1ATRT, STA350_LxA_SHIFT,
16, 0, sta350_limiter_ac_attack_tlv),
SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)",
STA350_L2ATRT, STA350_LxA_SHIFT,
16, 0, sta350_limiter_ac_attack_tlv),
SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)",
STA350_L1ATRT, STA350_LxR_SHIFT,
16, 0, sta350_limiter_ac_release_tlv),
SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)",
STA350_L2ATRT, STA350_LxR_SHIFT,
16, 0, sta350_limiter_ac_release_tlv),
SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)",
STA350_L1ATRT, STA350_LxA_SHIFT,
16, 0, sta350_limiter_drc_attack_tlv),
SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)",
STA350_L2ATRT, STA350_LxA_SHIFT,
16, 0, sta350_limiter_drc_attack_tlv),
SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)",
STA350_L1ATRT, STA350_LxR_SHIFT,
16, 0, sta350_limiter_drc_release_tlv),
SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)",
STA350_L2ATRT, STA350_LxR_SHIFT,
16, 0, sta350_limiter_drc_release_tlv),
BIQUAD_COEFS("Ch1 - Biquad 1", 0),
BIQUAD_COEFS("Ch1 - Biquad 2", 5),
BIQUAD_COEFS("Ch1 - Biquad 3", 10),
BIQUAD_COEFS("Ch1 - Biquad 4", 15),
BIQUAD_COEFS("Ch2 - Biquad 1", 20),
BIQUAD_COEFS("Ch2 - Biquad 2", 25),
BIQUAD_COEFS("Ch2 - Biquad 3", 30),
BIQUAD_COEFS("Ch2 - Biquad 4", 35),
BIQUAD_COEFS("High-pass", 40),
BIQUAD_COEFS("Low-pass", 45),
SINGLE_COEF("Ch1 - Prescale", 50),
SINGLE_COEF("Ch2 - Prescale", 51),
SINGLE_COEF("Ch1 - Postscale", 52),
SINGLE_COEF("Ch2 - Postscale", 53),
SINGLE_COEF("Ch3 - Postscale", 54),
SINGLE_COEF("Thermal warning - Postscale", 55),
SINGLE_COEF("Ch1 - Mix 1", 56),
SINGLE_COEF("Ch1 - Mix 2", 57),
SINGLE_COEF("Ch2 - Mix 1", 58),
SINGLE_COEF("Ch2 - Mix 2", 59),
SINGLE_COEF("Ch3 - Mix 1", 60),
SINGLE_COEF("Ch3 - Mix 2", 61),
};
static const struct snd_soc_dapm_widget sta350_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LEFT"),
SND_SOC_DAPM_OUTPUT("RIGHT"),
SND_SOC_DAPM_OUTPUT("SUB"),
};
static const struct snd_soc_dapm_route sta350_dapm_routes[] = {
{ "LEFT", NULL, "DAC" },
{ "RIGHT", NULL, "DAC" },
{ "SUB", NULL, "DAC" },
{ "DAC", NULL, "Playback" },
};
/* MCLK interpolation ratio per fs */
static struct {
int fs;
int ir;
} interpolation_ratios[] = {
{ 32000, 0 },
{ 44100, 0 },
{ 48000, 0 },
{ 88200, 1 },
{ 96000, 1 },
{ 176400, 2 },
{ 192000, 2 },
};
/* MCLK to fs clock ratios */
static int mcs_ratio_table[3][6] = {
{ 768, 512, 384, 256, 128, 576 },
{ 384, 256, 192, 128, 64, 0 },
{ 192, 128, 96, 64, 32, 0 },
};
/**
* sta350_set_dai_sysclk - configure MCLK
* @codec_dai: the codec DAI
* @clk_id: the clock ID (ignored)
* @freq: the MCLK input frequency
* @dir: the clock direction (ignored)
*
* The value of MCLK is used to determine which sample rates are supported
* by the STA350, based on the mcs_ratio_table.
*
* This function must be called by the machine driver's 'startup' function,
* otherwise the list of supported sample rates will not be available in
* time for ALSA.
*/
static int sta350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "mclk=%u\n", freq);
sta350->mclk = freq;
return 0;
}
/**
* sta350_set_dai_fmt - configure the codec for the selected audio format
* @codec_dai: the codec DAI
* @fmt: a SND_SOC_DAIFMT_x value indicating the data format
*
* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
* codec accordingly.
*/
static int sta350_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
unsigned int confb = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
sta350->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
confb |= STA350_CONFB_C2IM;
break;
case SND_SOC_DAIFMT_NB_IF:
confb |= STA350_CONFB_C1IM;
break;
default:
return -EINVAL;
}
return regmap_update_bits(sta350->regmap, STA350_CONFB,
STA350_CONFB_C1IM | STA350_CONFB_C2IM, confb);
}
/**
* sta350_hw_params - program the STA350 with the given hardware parameters.
* @substream: the audio stream
* @params: the hardware parameters to set
* @dai: the SOC DAI (ignored)
*
* This function programs the hardware with the values provided.
* Specifically, the sample rate and the data format.
*/
static int sta350_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
int i, mcs = -EINVAL, ir = -EINVAL;
unsigned int confa, confb;
unsigned int rate, ratio;
int ret;
if (!sta350->mclk) {
dev_err(component->dev,
"sta350->mclk is unset. Unable to determine ratio\n");
return -EIO;
}
rate = params_rate(params);
ratio = sta350->mclk / rate;
dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
if (interpolation_ratios[i].fs == rate) {
ir = interpolation_ratios[i].ir;
break;
}
}
if (ir < 0) {
dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
return -EINVAL;
}
for (i = 0; i < 6; i++) {
if (mcs_ratio_table[ir][i] == ratio) {
mcs = i;
break;
}
}
if (mcs < 0) {
dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
return -EINVAL;
}
confa = (ir << STA350_CONFA_IR_SHIFT) |
(mcs << STA350_CONFA_MCS_SHIFT);
confb = 0;
switch (params_width(params)) {
case 24:
dev_dbg(component->dev, "24bit\n");
fallthrough;
case 32:
dev_dbg(component->dev, "24bit or 32bit\n");
switch (sta350->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x1;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0x2;
break;
}
break;
case 20:
dev_dbg(component->dev, "20bit\n");
switch (sta350->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x4;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x5;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0x6;
break;
}
break;
case 18:
dev_dbg(component->dev, "18bit\n");
switch (sta350->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x8;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0x9;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0xa;
break;
}
break;
case 16:
dev_dbg(component->dev, "16bit\n");
switch (sta350->format) {
case SND_SOC_DAIFMT_I2S:
confb |= 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
confb |= 0xd;
break;
case SND_SOC_DAIFMT_RIGHT_J:
confb |= 0xe;
break;
}
break;
default:
return -EINVAL;
}
ret = regmap_update_bits(sta350->regmap, STA350_CONFA,
STA350_CONFA_MCS_MASK | STA350_CONFA_IR_MASK,
confa);
if (ret < 0)
return ret;
ret = regmap_update_bits(sta350->regmap, STA350_CONFB,
STA350_CONFB_SAI_MASK | STA350_CONFB_SAIFB,
confb);
if (ret < 0)
return ret;
return 0;
}
static int sta350_startup_sequence(struct sta350_priv *sta350)
{
if (sta350->gpiod_power_down)
gpiod_set_value(sta350->gpiod_power_down, 1);
if (sta350->gpiod_nreset) {
gpiod_set_value(sta350->gpiod_nreset, 0);
mdelay(1);
gpiod_set_value(sta350->gpiod_nreset, 1);
mdelay(1);
}
return 0;
}
/**
* sta350_set_bias_level - DAPM callback
* @component: the component device
* @level: DAPM power level
*
* This is called by ALSA to put the component into low power mode
* or to wake it up. If the component is powered off completely
* all registers must be restored after power on.
*/
static int sta350_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
int ret;
dev_dbg(component->dev, "level = %d\n", level);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Full power on */
regmap_update_bits(sta350->regmap, STA350_CONFF,
STA350_CONFF_PWDN | STA350_CONFF_EAPD,
STA350_CONFF_PWDN | STA350_CONFF_EAPD);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(
ARRAY_SIZE(sta350->supplies),
sta350->supplies);
if (ret < 0) {
dev_err(component->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
sta350_startup_sequence(sta350);
sta350_cache_sync(component);
}
/* Power down */
regmap_update_bits(sta350->regmap, STA350_CONFF,
STA350_CONFF_PWDN | STA350_CONFF_EAPD,
0);
break;
case SND_SOC_BIAS_OFF:
/* The chip runs through the power down sequence for us */
regmap_update_bits(sta350->regmap, STA350_CONFF,
STA350_CONFF_PWDN | STA350_CONFF_EAPD, 0);
/* power down: low */
if (sta350->gpiod_power_down)
gpiod_set_value(sta350->gpiod_power_down, 0);
if (sta350->gpiod_nreset)
gpiod_set_value(sta350->gpiod_nreset, 0);
regulator_bulk_disable(ARRAY_SIZE(sta350->supplies),
sta350->supplies);
break;
}
return 0;
}
static const struct snd_soc_dai_ops sta350_dai_ops = {
.hw_params = sta350_hw_params,
.set_sysclk = sta350_set_dai_sysclk,
.set_fmt = sta350_set_dai_fmt,
};
static struct snd_soc_dai_driver sta350_dai = {
.name = "sta350-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = STA350_RATES,
.formats = STA350_FORMATS,
},
.ops = &sta350_dai_ops,
};
static int sta350_probe(struct snd_soc_component *component)
{
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
struct sta350_platform_data *pdata = sta350->pdata;
int i, ret = 0, thermal = 0;
ret = regulator_bulk_enable(ARRAY_SIZE(sta350->supplies),
sta350->supplies);
if (ret < 0) {
dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = sta350_startup_sequence(sta350);
if (ret < 0) {
dev_err(component->dev, "Failed to startup device\n");
return ret;
}
/* CONFA */
if (!pdata->thermal_warning_recovery)
thermal |= STA350_CONFA_TWAB;
if (!pdata->thermal_warning_adjustment)
thermal |= STA350_CONFA_TWRB;
if (!pdata->fault_detect_recovery)
thermal |= STA350_CONFA_FDRB;
regmap_update_bits(sta350->regmap, STA350_CONFA,
STA350_CONFA_TWAB | STA350_CONFA_TWRB |
STA350_CONFA_FDRB,
thermal);
/* CONFC */
regmap_update_bits(sta350->regmap, STA350_CONFC,
STA350_CONFC_OM_MASK,
pdata->ffx_power_output_mode
<< STA350_CONFC_OM_SHIFT);
regmap_update_bits(sta350->regmap, STA350_CONFC,
STA350_CONFC_CSZ_MASK,
pdata->drop_compensation_ns
<< STA350_CONFC_CSZ_SHIFT);
regmap_update_bits(sta350->regmap,
STA350_CONFC,
STA350_CONFC_OCRB,
pdata->oc_warning_adjustment ?
STA350_CONFC_OCRB : 0);
/* CONFE */
regmap_update_bits(sta350->regmap, STA350_CONFE,
STA350_CONFE_MPCV,
pdata->max_power_use_mpcc ?
STA350_CONFE_MPCV : 0);
regmap_update_bits(sta350->regmap, STA350_CONFE,
STA350_CONFE_MPC,
pdata->max_power_correction ?
STA350_CONFE_MPC : 0);
regmap_update_bits(sta350->regmap, STA350_CONFE,
STA350_CONFE_AME,
pdata->am_reduction_mode ?
STA350_CONFE_AME : 0);
regmap_update_bits(sta350->regmap, STA350_CONFE,
STA350_CONFE_PWMS,
pdata->odd_pwm_speed_mode ?
STA350_CONFE_PWMS : 0);
regmap_update_bits(sta350->regmap, STA350_CONFE,
STA350_CONFE_DCCV,
pdata->distortion_compensation ?
STA350_CONFE_DCCV : 0);
/* CONFF */
regmap_update_bits(sta350->regmap, STA350_CONFF,
STA350_CONFF_IDE,
pdata->invalid_input_detect_mute ?
STA350_CONFF_IDE : 0);
regmap_update_bits(sta350->regmap, STA350_CONFF,
STA350_CONFF_OCFG_MASK,
pdata->output_conf
<< STA350_CONFF_OCFG_SHIFT);
/* channel to output mapping */
regmap_update_bits(sta350->regmap, STA350_C1CFG,
STA350_CxCFG_OM_MASK,
pdata->ch1_output_mapping
<< STA350_CxCFG_OM_SHIFT);
regmap_update_bits(sta350->regmap, STA350_C2CFG,
STA350_CxCFG_OM_MASK,
pdata->ch2_output_mapping
<< STA350_CxCFG_OM_SHIFT);
regmap_update_bits(sta350->regmap, STA350_C3CFG,
STA350_CxCFG_OM_MASK,
pdata->ch3_output_mapping
<< STA350_CxCFG_OM_SHIFT);
/* miscellaneous registers */
regmap_update_bits(sta350->regmap, STA350_MISC1,
STA350_MISC1_CPWMEN,
pdata->activate_mute_output ?
STA350_MISC1_CPWMEN : 0);
regmap_update_bits(sta350->regmap, STA350_MISC1,
STA350_MISC1_BRIDGOFF,
pdata->bridge_immediate_off ?
STA350_MISC1_BRIDGOFF : 0);
regmap_update_bits(sta350->regmap, STA350_MISC1,
STA350_MISC1_NSHHPEN,
pdata->noise_shape_dc_cut ?
STA350_MISC1_NSHHPEN : 0);
regmap_update_bits(sta350->regmap, STA350_MISC1,
STA350_MISC1_RPDNEN,
pdata->powerdown_master_vol ?
STA350_MISC1_RPDNEN: 0);
regmap_update_bits(sta350->regmap, STA350_MISC2,
STA350_MISC2_PNDLSL_MASK,
pdata->powerdown_delay_divider
<< STA350_MISC2_PNDLSL_SHIFT);
/* initialize coefficient shadow RAM with reset values */
for (i = 4; i <= 49; i += 5)
sta350->coef_shadow[i] = 0x400000;
for (i = 50; i <= 54; i++)
sta350->coef_shadow[i] = 0x7fffff;
sta350->coef_shadow[55] = 0x5a9df7;
sta350->coef_shadow[56] = 0x7fffff;
sta350->coef_shadow[59] = 0x7fffff;
sta350->coef_shadow[60] = 0x400000;
sta350->coef_shadow[61] = 0x400000;
snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
/* Bias level configuration will have done an extra enable */
regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
return 0;
}
static void sta350_remove(struct snd_soc_component *component)
{
struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
}
static const struct snd_soc_component_driver sta350_component = {
.probe = sta350_probe,
.remove = sta350_remove,
.set_bias_level = sta350_set_bias_level,
.controls = sta350_snd_controls,
.num_controls = ARRAY_SIZE(sta350_snd_controls),
.dapm_widgets = sta350_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sta350_dapm_widgets),
.dapm_routes = sta350_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sta350_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config sta350_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = STA350_MISC2,
.reg_defaults = sta350_regs,
.num_reg_defaults = ARRAY_SIZE(sta350_regs),
.cache_type = REGCACHE_MAPLE,
.wr_table = &sta350_write_regs,
.rd_table = &sta350_read_regs,
.volatile_table = &sta350_volatile_regs,
};
#ifdef CONFIG_OF
static const struct of_device_id st350_dt_ids[] = {
{ .compatible = "st,sta350", },
{ }
};
MODULE_DEVICE_TABLE(of, st350_dt_ids);
static const char * const sta350_ffx_modes[] = {
[STA350_FFX_PM_DROP_COMP] = "drop-compensation",
[STA350_FFX_PM_TAPERED_COMP] = "tapered-compensation",
[STA350_FFX_PM_FULL_POWER] = "full-power-mode",
[STA350_FFX_PM_VARIABLE_DROP_COMP] = "variable-drop-compensation",
};
static int sta350_probe_dt(struct device *dev, struct sta350_priv *sta350)
{
struct device_node *np = dev->of_node;
struct sta350_platform_data *pdata;
const char *ffx_power_mode;
u16 tmp;
u8 tmp8;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
of_property_read_u8(np, "st,output-conf",
&pdata->output_conf);
of_property_read_u8(np, "st,ch1-output-mapping",
&pdata->ch1_output_mapping);
of_property_read_u8(np, "st,ch2-output-mapping",
&pdata->ch2_output_mapping);
of_property_read_u8(np, "st,ch3-output-mapping",
&pdata->ch3_output_mapping);
pdata->thermal_warning_recovery =
of_property_read_bool(np, "st,thermal-warning-recovery");
pdata->thermal_warning_adjustment =
of_property_read_bool(np, "st,thermal-warning-adjustment");
pdata->fault_detect_recovery =
of_property_read_bool(np, "st,fault-detect-recovery");
pdata->ffx_power_output_mode = STA350_FFX_PM_VARIABLE_DROP_COMP;
if (!of_property_read_string(np, "st,ffx-power-output-mode",
&ffx_power_mode)) {
int i, mode = -EINVAL;
for (i = 0; i < ARRAY_SIZE(sta350_ffx_modes); i++)
if (!strcasecmp(ffx_power_mode, sta350_ffx_modes[i]))
mode = i;
if (mode < 0)
dev_warn(dev, "Unsupported ffx output mode: %s\n",
ffx_power_mode);
else
pdata->ffx_power_output_mode = mode;
}
tmp = 140;
of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
pdata->oc_warning_adjustment =
of_property_read_bool(np, "st,overcurrent-warning-adjustment");
/* CONFE */
pdata->max_power_use_mpcc =
of_property_read_bool(np, "st,max-power-use-mpcc");
pdata->max_power_correction =
of_property_read_bool(np, "st,max-power-correction");
pdata->am_reduction_mode =
of_property_read_bool(np, "st,am-reduction-mode");
pdata->odd_pwm_speed_mode =
of_property_read_bool(np, "st,odd-pwm-speed-mode");
pdata->distortion_compensation =
of_property_read_bool(np, "st,distortion-compensation");
/* CONFF */
pdata->invalid_input_detect_mute =
of_property_read_bool(np, "st,invalid-input-detect-mute");
/* MISC */
pdata->activate_mute_output =
of_property_read_bool(np, "st,activate-mute-output");
pdata->bridge_immediate_off =
of_property_read_bool(np, "st,bridge-immediate-off");
pdata->noise_shape_dc_cut =
of_property_read_bool(np, "st,noise-shape-dc-cut");
pdata->powerdown_master_vol =
of_property_read_bool(np, "st,powerdown-master-volume");
if (!of_property_read_u8(np, "st,powerdown-delay-divider", &tmp8)) {
if (is_power_of_2(tmp8) && tmp8 >= 1 && tmp8 <= 128)
pdata->powerdown_delay_divider = ilog2(tmp8);
else
dev_warn(dev, "Unsupported powerdown delay divider %d\n",
tmp8);
}
sta350->pdata = pdata;
return 0;
}
#endif
static int sta350_i2c_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct sta350_priv *sta350;
int ret, i;
sta350 = devm_kzalloc(dev, sizeof(struct sta350_priv), GFP_KERNEL);
if (!sta350)
return -ENOMEM;
mutex_init(&sta350->coeff_lock);
sta350->pdata = dev_get_platdata(dev);
#ifdef CONFIG_OF
if (dev->of_node) {
ret = sta350_probe_dt(dev, sta350);
if (ret < 0)
return ret;
}
#endif
/* GPIOs */
sta350->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(sta350->gpiod_nreset))
return PTR_ERR(sta350->gpiod_nreset);
sta350->gpiod_power_down = devm_gpiod_get_optional(dev, "power-down",
GPIOD_OUT_LOW);
if (IS_ERR(sta350->gpiod_power_down))
return PTR_ERR(sta350->gpiod_power_down);
/* regulators */
for (i = 0; i < ARRAY_SIZE(sta350->supplies); i++)
sta350->supplies[i].supply = sta350_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sta350->supplies),
sta350->supplies);
if (ret < 0) {
dev_err(dev, "Failed to request supplies: %d\n", ret);
return ret;
}
sta350->regmap = devm_regmap_init_i2c(i2c, &sta350_regmap);
if (IS_ERR(sta350->regmap)) {
ret = PTR_ERR(sta350->regmap);
dev_err(dev, "Failed to init regmap: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, sta350);
ret = devm_snd_soc_register_component(dev, &sta350_component, &sta350_dai, 1);
if (ret < 0)
dev_err(dev, "Failed to register component (%d)\n", ret);
return ret;
}
static void sta350_i2c_remove(struct i2c_client *client)
{}
static const struct i2c_device_id sta350_i2c_id[] = {
{ "sta350", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, sta350_i2c_id);
static struct i2c_driver sta350_i2c_driver = {
.driver = {
.name = "sta350",
.of_match_table = of_match_ptr(st350_dt_ids),
},
.probe = sta350_i2c_probe,
.remove = sta350_i2c_remove,
.id_table = sta350_i2c_id,
};
module_i2c_driver(sta350_i2c_driver);
MODULE_DESCRIPTION("ASoC STA350 driver");
MODULE_AUTHOR("Sven Brandau <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sta350.c |
// SPDX-License-Identifier: GPL-2.0-only
/* ALSA SoC TLV320AIC3X codec driver
*
* Author: Vladimir Barinov, <[email protected]>
* Copyright: (C) 2007 MontaVista Software, Inc., <[email protected]>
*
* Based on sound/soc/codecs/wm8753.c by Liam Girdwood
*
* Notes:
* The AIC3X is a driver for a low power stereo audio
* codecs aic31, aic32, aic33, aic3007.
*
* It supports full aic33 codec functionality.
* The compatibility with aic32, aic31 and aic3007 is as follows:
* aic32/aic3007 | aic31
* ---------------------------------------
* MONO_LOUT -> N/A | MONO_LOUT -> N/A
* | IN1L -> LINE1L
* | IN1R -> LINE1R
* | IN2L -> LINE2L
* | IN2R -> LINE2R
* | MIC3L/R -> N/A
* truncated internal functionality in
* accordance with documentation
* ---------------------------------------
*
* Hence the machine layer should disable unsupported inputs/outputs by
* snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "tlv320aic3x.h"
#define AIC3X_NUM_SUPPLIES 4
static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
"IOVDD", /* I/O Voltage */
"DVDD", /* Digital Core Voltage */
"AVDD", /* Analog DAC Voltage */
"DRVDD", /* ADC Analog and Output Driver Voltage */
};
struct aic3x_priv;
struct aic3x_disable_nb {
struct notifier_block nb;
struct aic3x_priv *aic3x;
};
struct aic3x_setup_data {
unsigned int gpio_func[2];
};
/* codec private data */
struct aic3x_priv {
struct snd_soc_component *component;
struct regmap *regmap;
struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
struct aic3x_setup_data *setup;
unsigned int sysclk;
unsigned int dai_fmt;
unsigned int tdm_delay;
unsigned int slot_width;
int master;
struct gpio_desc *gpio_reset;
bool shared_reset;
int power;
u16 model;
/* Selects the micbias voltage */
enum aic3x_micbias_voltage micbias_vg;
/* Output Common-Mode Voltage */
u8 ocmv;
};
static const struct reg_default aic3x_reg[] = {
{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
{ 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
{ 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
{ 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
{ 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
{ 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
{ 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
{ 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
{ 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
{ 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
{ 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
{ 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
{ 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
{ 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
{ 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
{ 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
{ 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
{ 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
{ 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
{ 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
{ 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
{ 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
{ 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
{ 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
{ 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
{ 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
{ 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
{ 108, 0x00 }, { 109, 0x00 },
};
static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AIC3X_RESET:
return true;
default:
return false;
}
}
const struct regmap_config aic3x_regmap = {
.max_register = DAC_ICC_ADJ,
.reg_defaults = aic3x_reg,
.num_reg_defaults = ARRAY_SIZE(aic3x_reg),
.volatile_reg = aic3x_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL_GPL(aic3x_regmap);
#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
/*
* All input lines are connected when !0xf and disconnected with 0xf bit field,
* so we have to use specific dapm_put call for input mixer
*/
static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
unsigned int shift = mc->shift;
int max = mc->max;
unsigned int mask = (1 << fls(max)) - 1;
unsigned int invert = mc->invert;
unsigned short val;
struct snd_soc_dapm_update update = {};
int connect, change;
val = (ucontrol->value.integer.value[0] & mask);
mask = 0xf;
if (val)
val = mask;
connect = !!val;
if (invert)
val = mask - val;
mask <<= shift;
val <<= shift;
change = snd_soc_component_test_bits(component, reg, mask, val);
if (change) {
update.kcontrol = kcontrol;
update.reg = reg;
update.mask = mask;
update.val = val;
snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
&update);
}
return change;
}
/*
* mic bias power on/off share the same register bits with
* output voltage of mic bias. when power on mic bias, we
* need reclaim it to voltage value.
* 0x0 = Powered off
* 0x1 = MICBIAS output is powered to 2.0V,
* 0x2 = MICBIAS output is powered to 2.5V
* 0x3 = MICBIAS output is connected to AVDD
*/
static int mic_bias_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* change mic bias voltage to user defined */
snd_soc_component_update_bits(component, MICBIAS_CTRL,
MICBIAS_LEVEL_MASK,
aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, MICBIAS_CTRL,
MICBIAS_LEVEL_MASK, 0);
break;
}
return 0;
}
static const char * const aic3x_left_dac_mux[] = {
"DAC_L1", "DAC_L3", "DAC_L2" };
static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
aic3x_left_dac_mux);
static const char * const aic3x_right_dac_mux[] = {
"DAC_R1", "DAC_R3", "DAC_R2" };
static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
aic3x_right_dac_mux);
static const char * const aic3x_left_hpcom_mux[] = {
"differential of HPLOUT", "constant VCM", "single-ended" };
static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
aic3x_left_hpcom_mux);
static const char * const aic3x_right_hpcom_mux[] = {
"differential of HPROUT", "constant VCM", "single-ended",
"differential of HPLCOM", "external feedback" };
static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
aic3x_right_hpcom_mux);
static const char * const aic3x_linein_mode_mux[] = {
"single-ended", "differential" };
static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
aic3x_linein_mode_mux);
static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
aic3x_linein_mode_mux);
static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
aic3x_linein_mode_mux);
static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
aic3x_linein_mode_mux);
static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
aic3x_linein_mode_mux);
static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
aic3x_linein_mode_mux);
static const char * const aic3x_adc_hpf[] = {
"Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
aic3x_adc_hpf);
static const char * const aic3x_agc_level[] = {
"-5.5dB", "-8dB", "-10dB", "-12dB",
"-14dB", "-17dB", "-20dB", "-24dB" };
static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
aic3x_agc_level);
static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
aic3x_agc_level);
static const char * const aic3x_agc_attack[] = {
"8ms", "11ms", "16ms", "20ms" };
static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
aic3x_agc_attack);
static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
aic3x_agc_attack);
static const char * const aic3x_agc_decay[] = {
"100ms", "200ms", "400ms", "500ms" };
static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
aic3x_agc_decay);
static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
aic3x_agc_decay);
static const char * const aic3x_poweron_time[] = {
"0us", "10us", "100us", "1ms", "10ms", "50ms",
"100ms", "200ms", "400ms", "800ms", "2s", "4s" };
static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
aic3x_poweron_time);
static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
aic3x_rampup_step);
/*
* DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
*/
static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
/*
* Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
* Step size is approximately 0.5 dB over most of the scale but increasing
* near the very low levels.
* Define dB scale so that it is mostly correct for range about -55 to 0 dB
* but having increasing dB difference below that (and where it doesn't count
* so much). This setting shows -50 dB (actual is -50.3 dB) for register
* value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
*/
static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
/* Output volumes. From 0 to 9 dB in 1 dB steps */
static const DECLARE_TLV_DB_SCALE(out_tlv, 0, 100, 0);
static const struct snd_kcontrol_new aic3x_snd_controls[] = {
/* Output */
SOC_DOUBLE_R_TLV("PCM Playback Volume",
LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
/*
* Output controls that map to output mixer switches. Note these are
* only for swapped L-to-R and R-to-L routes. See below stereo controls
* for direct L-to-L and R-to-R routes.
*/
SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
/* Stereo output controls for direct L-to-L and R-to-R routes */
SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
0, 118, 1, output_stage_tlv),
/* Output pin controls */
SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4,
9, 0, out_tlv),
SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
0x01, 0),
SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4,
9, 0, out_tlv),
SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
0x01, 0),
SOC_DOUBLE_R_TLV("HPCOM Playback Volume", HPLCOM_CTRL, HPRCOM_CTRL,
4, 9, 0, out_tlv),
SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
0x01, 0),
/*
* Note: enable Automatic input Gain Controller with care. It can
* adjust PGA to max value when ADC is on and will never go back.
*/
SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
/* De-emphasis */
SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
/* Input */
SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
0, 119, 0, adc_tlv),
SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
/* Pop reduction */
SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
};
/* For other than tlv320aic3104 */
static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
/*
* Output controls that map to output mixer switches. Note these are
* only for swapped L-to-R and R-to-L routes. See below stereo controls
* for direct L-to-L and R-to-R routes.
*/
SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
/* Stereo output controls for direct L-to-L and R-to-R routes */
SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
0, 118, 1, output_stage_tlv),
};
static const struct snd_kcontrol_new aic3x_mono_controls[] = {
SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
0, 118, 1, output_stage_tlv),
SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
0, 118, 1, output_stage_tlv),
SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0,
out_tlv),
};
/*
* Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
*/
static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
/* Left DAC Mux */
static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
/* Right DAC Mux */
static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
/* Left HPCOM Mux */
static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
/* Right HPCOM Mux */
static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
/* Left Line Mixer */
static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
/* Not on tlv320aic3104 */
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
};
/* Right Line Mixer */
static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
/* Not on tlv320aic3104 */
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
};
/* Mono Mixer */
static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
};
/* Left HP Mixer */
static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
/* Not on tlv320aic3104 */
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
};
/* Right HP Mixer */
static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
/* Not on tlv320aic3104 */
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
};
/* Left HPCOM Mixer */
static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
/* Not on tlv320aic3104 */
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
};
/* Right HPCOM Mixer */
static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
/* Not on tlv320aic3104 */
SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
};
/* Left PGA Mixer */
static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
};
/* Right PGA Mixer */
static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
};
/* Left PGA Mixer for tlv320aic3104 */
static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
};
/* Right PGA Mixer for tlv320aic3104 */
static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
};
/* Left Line1 Mux */
static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
/* Right Line1 Mux */
static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
/* Left Line2 Mux */
static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
/* Right Line2 Mux */
static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
/* Left DAC to Left Outputs */
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
&aic3x_left_dac_mux_controls),
SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
&aic3x_left_hpcom_mux_controls),
SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
/* Right DAC to Right Outputs */
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
&aic3x_right_dac_mux_controls),
SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
&aic3x_right_hpcom_mux_controls),
SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
/* Inputs to Left ADC */
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
&aic3x_left_line1l_mux_controls),
SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
&aic3x_left_line1r_mux_controls),
/* Inputs to Right ADC */
SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
LINE1R_2_RADC_CTRL, 2, 0),
SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
&aic3x_right_line1l_mux_controls),
SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
&aic3x_right_line1r_mux_controls),
/* Mic Bias */
SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
mic_bias_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("LLOUT"),
SND_SOC_DAPM_OUTPUT("RLOUT"),
SND_SOC_DAPM_OUTPUT("HPLOUT"),
SND_SOC_DAPM_OUTPUT("HPROUT"),
SND_SOC_DAPM_OUTPUT("HPLCOM"),
SND_SOC_DAPM_OUTPUT("HPRCOM"),
SND_SOC_DAPM_INPUT("LINE1L"),
SND_SOC_DAPM_INPUT("LINE1R"),
/*
* Virtual output pin to detection block inside codec. This can be
* used to keep codec bias on if gpio or detection features are needed.
* Force pin on or construct a path with an input jack and mic bias
* widgets.
*/
SND_SOC_DAPM_OUTPUT("Detection"),
};
/* For other than tlv320aic3104 */
static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
/* Inputs to Left ADC */
SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_pga_mixer_controls[0],
ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
&aic3x_left_line2_mux_controls),
/* Inputs to Right ADC */
SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_pga_mixer_controls[0],
ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
&aic3x_right_line2_mux_controls),
/*
* Not a real mic bias widget but similar function. This is for dynamic
* control of GPIO1 digital mic modulator clock output function when
* using digital mic.
*/
SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
AIC3X_GPIO1_REG, 4, 0xf,
AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
AIC3X_GPIO1_FUNC_DISABLED),
/*
* Also similar function like mic bias. Selects digital mic with
* configurable oversampling rate instead of ADC converter.
*/
SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
/* Output mixers */
SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_line_mixer_controls[0],
ARRAY_SIZE(aic3x_left_line_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_line_mixer_controls[0],
ARRAY_SIZE(aic3x_right_line_mixer_controls)),
SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_hp_mixer_controls[0],
ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_hp_mixer_controls[0],
ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_hpcom_mixer_controls[0],
ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_hpcom_mixer_controls[0],
ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
SND_SOC_DAPM_INPUT("MIC3L"),
SND_SOC_DAPM_INPUT("MIC3R"),
SND_SOC_DAPM_INPUT("LINE2L"),
SND_SOC_DAPM_INPUT("LINE2R"),
};
/* For tlv320aic3104 */
static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
/* Inputs to Left ADC */
SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
&aic3104_left_pga_mixer_controls[0],
ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
/* Inputs to Right ADC */
SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
&aic3104_right_pga_mixer_controls[0],
ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
/* Output mixers */
SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_line_mixer_controls[0],
ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_line_mixer_controls[0],
ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_hp_mixer_controls[0],
ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_hp_mixer_controls[0],
ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_left_hpcom_mixer_controls[0],
ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_right_hpcom_mixer_controls[0],
ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
SND_SOC_DAPM_INPUT("MIC2L"),
SND_SOC_DAPM_INPUT("MIC2R"),
};
static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
/* Mono Output */
SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
&aic3x_mono_mixer_controls[0],
ARRAY_SIZE(aic3x_mono_mixer_controls)),
SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
};
static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
/* Class-D outputs */
SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPOP"),
SND_SOC_DAPM_OUTPUT("SPOM"),
};
static const struct snd_soc_dapm_route intercon[] = {
/* Left Input */
{"Left Line1L Mux", "single-ended", "LINE1L"},
{"Left Line1L Mux", "differential", "LINE1L"},
{"Left Line1R Mux", "single-ended", "LINE1R"},
{"Left Line1R Mux", "differential", "LINE1R"},
{"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
{"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
{"Left ADC", NULL, "Left PGA Mixer"},
/* Right Input */
{"Right Line1R Mux", "single-ended", "LINE1R"},
{"Right Line1R Mux", "differential", "LINE1R"},
{"Right Line1L Mux", "single-ended", "LINE1L"},
{"Right Line1L Mux", "differential", "LINE1L"},
{"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
{"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
{"Right ADC", NULL, "Right PGA Mixer"},
/* Left DAC Output */
{"Left DAC Mux", "DAC_L1", "Left DAC"},
{"Left DAC Mux", "DAC_L2", "Left DAC"},
{"Left DAC Mux", "DAC_L3", "Left DAC"},
/* Right DAC Output */
{"Right DAC Mux", "DAC_R1", "Right DAC"},
{"Right DAC Mux", "DAC_R2", "Right DAC"},
{"Right DAC Mux", "DAC_R3", "Right DAC"},
/* Left Line Output */
{"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Left Line Out", NULL, "Left Line Mixer"},
{"Left Line Out", NULL, "Left DAC Mux"},
{"LLOUT", NULL, "Left Line Out"},
/* Right Line Output */
{"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Right Line Out", NULL, "Right Line Mixer"},
{"Right Line Out", NULL, "Right DAC Mux"},
{"RLOUT", NULL, "Right Line Out"},
/* Left HP Output */
{"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Left HP Out", NULL, "Left HP Mixer"},
{"Left HP Out", NULL, "Left DAC Mux"},
{"HPLOUT", NULL, "Left HP Out"},
/* Right HP Output */
{"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Right HP Out", NULL, "Right HP Mixer"},
{"Right HP Out", NULL, "Right DAC Mux"},
{"HPROUT", NULL, "Right HP Out"},
/* Left HPCOM Output */
{"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
{"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
{"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
{"Left HP Com", NULL, "Left HPCOM Mux"},
{"HPLCOM", NULL, "Left HP Com"},
/* Right HPCOM Output */
{"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
{"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
{"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
{"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
{"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
{"Right HP Com", NULL, "Right HPCOM Mux"},
{"HPRCOM", NULL, "Right HP Com"},
};
/* For other than tlv320aic3104 */
static const struct snd_soc_dapm_route intercon_extra[] = {
/* Left Input */
{"Left Line2L Mux", "single-ended", "LINE2L"},
{"Left Line2L Mux", "differential", "LINE2L"},
{"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
{"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
{"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
{"Left ADC", NULL, "GPIO1 dmic modclk"},
/* Right Input */
{"Right Line2R Mux", "single-ended", "LINE2R"},
{"Right Line2R Mux", "differential", "LINE2R"},
{"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
{"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
{"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
{"Right ADC", NULL, "GPIO1 dmic modclk"},
/*
* Logical path between digital mic enable and GPIO1 modulator clock
* output function
*/
{"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
{"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
{"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
/* Left Line Output */
{"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
/* Right Line Output */
{"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
/* Left HP Output */
{"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
/* Right HP Output */
{"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
/* Left HPCOM Output */
{"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
/* Right HPCOM Output */
{"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
};
/* For tlv320aic3104 */
static const struct snd_soc_dapm_route intercon_extra_3104[] = {
/* Left Input */
{"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
{"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
/* Right Input */
{"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
{"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
};
static const struct snd_soc_dapm_route intercon_mono[] = {
/* Mono Output */
{"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
{"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
{"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
{"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
{"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
{"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
{"Mono Out", NULL, "Mono Mixer"},
{"MONO_LOUT", NULL, "Mono Out"},
};
static const struct snd_soc_dapm_route intercon_3007[] = {
/* Class-D outputs */
{"Left Class-D Out", NULL, "Left Line Out"},
{"Right Class-D Out", NULL, "Left Line Out"},
{"SPOP", NULL, "Left Class-D Out"},
{"SPOM", NULL, "Right Class-D Out"},
};
static int aic3x_add_widgets(struct snd_soc_component *component)
{
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
switch (aic3x->model) {
case AIC3X_MODEL_3X:
case AIC3X_MODEL_33:
case AIC3X_MODEL_3106:
snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
ARRAY_SIZE(aic3x_extra_dapm_widgets));
snd_soc_dapm_add_routes(dapm, intercon_extra,
ARRAY_SIZE(intercon_extra));
snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
ARRAY_SIZE(aic3x_dapm_mono_widgets));
snd_soc_dapm_add_routes(dapm, intercon_mono,
ARRAY_SIZE(intercon_mono));
break;
case AIC3X_MODEL_3007:
snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
ARRAY_SIZE(aic3x_extra_dapm_widgets));
snd_soc_dapm_add_routes(dapm, intercon_extra,
ARRAY_SIZE(intercon_extra));
snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
ARRAY_SIZE(aic3007_dapm_widgets));
snd_soc_dapm_add_routes(dapm, intercon_3007,
ARRAY_SIZE(intercon_3007));
break;
case AIC3X_MODEL_3104:
snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
ARRAY_SIZE(aic3104_extra_dapm_widgets));
snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
ARRAY_SIZE(intercon_extra_3104));
break;
}
return 0;
}
static int aic3x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
u16 d, pll_d = 1;
int clk;
int width = aic3x->slot_width;
if (!width)
width = params_width(params);
/* select data word length */
data = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
switch (width) {
case 16:
break;
case 20:
data |= (0x01 << 4);
break;
case 24:
data |= (0x02 << 4);
break;
case 32:
data |= (0x03 << 4);
break;
}
snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
/* Fsref can be 44100 or 48000 */
fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
/* Try to find a value for Q which allows us to bypass the PLL and
* generate CODEC_CLK directly. */
for (pll_q = 2; pll_q < 18; pll_q++)
if (aic3x->sysclk / (128 * pll_q) == fsref) {
bypass_pll = 1;
break;
}
if (bypass_pll) {
pll_q &= 0xf;
snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
/* disable PLL if it is bypassed */
snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
} else {
snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
/* enable PLL when it is used */
snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
PLL_ENABLE, PLL_ENABLE);
}
/* Route Left DAC to left channel input and
* right DAC to right channel input */
data = (LDAC2LCH | RDAC2RCH);
data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
if (params_rate(params) >= 64000)
data |= DUAL_RATE_MODE;
snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data);
/* codec sample rate select */
data = (fsref * 20) / params_rate(params);
if (params_rate(params) < 64000)
data /= 2;
data /= 5;
data -= 2;
data |= (data << 4);
snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data);
if (bypass_pll)
return 0;
/* Use PLL, compute appropriate setup for j, d, r and p, the closest
* one wins the game. Try with d==0 first, next with d!=0.
* Constraints for j are according to the datasheet.
* The sysclk is divided by 1000 to prevent integer overflows.
*/
codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
for (r = 1; r <= 16; r++)
for (p = 1; p <= 8; p++) {
for (j = 4; j <= 55; j++) {
/* This is actually 1000*((j+(d/10000))*r)/p
* The term had to be converted to get
* rid of the division by 10000; d = 0 here
*/
int tmp_clk = (1000 * j * r) / p;
/* Check whether this values get closer than
* the best ones we had before
*/
if (abs(codec_clk - tmp_clk) <
abs(codec_clk - last_clk)) {
pll_j = j; pll_d = 0;
pll_r = r; pll_p = p;
last_clk = tmp_clk;
}
/* Early exit for exact matches */
if (tmp_clk == codec_clk)
goto found;
}
}
/* try with d != 0 */
for (p = 1; p <= 8; p++) {
j = codec_clk * p / 1000;
if (j < 4 || j > 11)
continue;
/* do not use codec_clk here since we'd loose precision */
d = ((2048 * p * fsref) - j * aic3x->sysclk)
* 100 / (aic3x->sysclk/100);
clk = (10000 * j + d) / (10 * p);
/* check whether this values get closer than the best
* ones we had before */
if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
last_clk = clk;
}
/* Early exit for exact matches */
if (clk == codec_clk)
goto found;
}
if (last_clk == 0) {
printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
return -EINVAL;
}
found:
snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG,
pll_r << PLLR_SHIFT);
snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
snd_soc_component_write(component, AIC3X_PLL_PROGC_REG,
(pll_d >> 6) << PLLD_MSB_SHIFT);
snd_soc_component_write(component, AIC3X_PLL_PROGD_REG,
(pll_d & 0x3F) << PLLD_LSB_SHIFT);
return 0;
}
static int aic3x_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
int delay = 0;
int width = aic3x->slot_width;
if (!width)
width = substream->runtime->sample_bits;
/* TDM slot selection only valid in DSP_A/_B mode */
if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
delay += (aic3x->tdm_delay*width + 1);
else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
delay += aic3x->tdm_delay*width;
/* Configure data delay */
snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay);
return 0;
}
static int aic3x_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u8 ldac_reg = snd_soc_component_read(component, LDAC_VOL) & ~MUTE_ON;
u8 rdac_reg = snd_soc_component_read(component, RDAC_VOL) & ~MUTE_ON;
if (mute) {
snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON);
snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON);
} else {
snd_soc_component_write(component, LDAC_VOL, ldac_reg);
snd_soc_component_write(component, RDAC_VOL, rdac_reg);
}
return 0;
}
static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
/* set clock on MCLK or GPIO2 or BCLK */
snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
clk_id << PLLCLK_IN_SHIFT);
snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
clk_id << CLKDIV_IN_SHIFT);
aic3x->sysclk = freq;
return 0;
}
static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
u8 iface_areg, iface_breg;
iface_areg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLA) & 0x3f;
iface_breg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & 0x3f;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
aic3x->master = 1;
iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFC:
aic3x->master = 0;
iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
break;
case SND_SOC_DAIFMT_CBP_CFC:
aic3x->master = 1;
iface_areg |= BIT_CLK_MASTER;
iface_areg &= ~WORD_CLK_MASTER;
break;
case SND_SOC_DAIFMT_CBC_CFP:
aic3x->master = 1;
iface_areg |= WORD_CLK_MASTER;
iface_areg &= ~BIT_CLK_MASTER;
break;
default:
return -EINVAL;
}
/*
* match both interface format and signal polarities since they
* are fixed
*/
switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
SND_SOC_DAIFMT_INV_MASK)) {
case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
break;
case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
iface_breg |= (0x01 << 6);
break;
case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
iface_breg |= (0x02 << 6);
break;
case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
iface_breg |= (0x03 << 6);
break;
default:
return -EINVAL;
}
aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
/* set iface */
snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg);
snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg);
return 0;
}
static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = codec_dai->component;
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
unsigned int lsb;
if (tx_mask != rx_mask) {
dev_err(component->dev, "tx and rx masks must be symmetric\n");
return -EINVAL;
}
if (unlikely(!tx_mask)) {
dev_err(component->dev, "tx and rx masks need to be non 0\n");
return -EINVAL;
}
/* TDM based on DSP mode requires slots to be adjacent */
lsb = __ffs(tx_mask);
if ((lsb + 1) != __fls(tx_mask)) {
dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
return -EINVAL;
}
switch (slot_width) {
case 16:
case 20:
case 24:
case 32:
break;
default:
dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
return -EINVAL;
}
aic3x->tdm_delay = lsb;
aic3x->slot_width = slot_width;
/* DOUT in high-impedance on inactive bit clocks */
snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA,
DOUT_TRISTATE, DOUT_TRISTATE);
return 0;
}
static int aic3x_regulator_event(struct notifier_block *nb,
unsigned long event, void *data)
{
struct aic3x_disable_nb *disable_nb =
container_of(nb, struct aic3x_disable_nb, nb);
struct aic3x_priv *aic3x = disable_nb->aic3x;
if (event & REGULATOR_EVENT_DISABLE) {
/*
* Put codec to reset and require cache sync as at least one
* of the supplies was disabled
*/
if (aic3x->gpio_reset)
gpiod_set_value(aic3x->gpio_reset, 1);
regcache_mark_dirty(aic3x->regmap);
}
return 0;
}
static int aic3x_set_power(struct snd_soc_component *component, int power)
{
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
unsigned int pll_c, pll_d;
int ret;
if (power) {
ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
aic3x->supplies);
if (ret)
goto out;
aic3x->power = 1;
if (aic3x->gpio_reset) {
udelay(1);
gpiod_set_value(aic3x->gpio_reset, 0);
}
/* Sync reg_cache with the hardware */
regcache_cache_only(aic3x->regmap, false);
regcache_sync(aic3x->regmap);
/* Rewrite paired PLL D registers in case cached sync skipped
* writing one of them and thus caused other one also not
* being written
*/
pll_c = snd_soc_component_read(component, AIC3X_PLL_PROGC_REG);
pll_d = snd_soc_component_read(component, AIC3X_PLL_PROGD_REG);
if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c);
snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d);
}
/*
* Delay is needed to reduce pop-noise after syncing back the
* registers
*/
mdelay(50);
} else {
/*
* Do soft reset to this codec instance in order to clear
* possible VDD leakage currents in case the supply regulators
* remain on
*/
snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
regcache_mark_dirty(aic3x->regmap);
aic3x->power = 0;
/* HW writes are needless when bias is off */
regcache_cache_only(aic3x->regmap, true);
ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
aic3x->supplies);
}
out:
return ret;
}
static int aic3x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY &&
aic3x->master) {
/* enable pll */
snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
PLL_ENABLE, PLL_ENABLE);
}
break;
case SND_SOC_BIAS_STANDBY:
if (!aic3x->power)
aic3x_set_power(component, 1);
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE &&
aic3x->master) {
/* disable pll */
snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
PLL_ENABLE, 0);
}
break;
case SND_SOC_BIAS_OFF:
if (aic3x->power)
aic3x_set_power(component, 0);
break;
}
return 0;
}
#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops aic3x_dai_ops = {
.hw_params = aic3x_hw_params,
.prepare = aic3x_prepare,
.mute_stream = aic3x_mute,
.set_sysclk = aic3x_set_dai_sysclk,
.set_fmt = aic3x_set_dai_fmt,
.set_tdm_slot = aic3x_set_dai_tdm_slot,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver aic3x_dai = {
.name = "tlv320aic3x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC3X_RATES,
.formats = AIC3X_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = AIC3X_RATES,
.formats = AIC3X_FORMATS,},
.ops = &aic3x_dai_ops,
.symmetric_rate = 1,
};
static void aic3x_mono_init(struct snd_soc_component *component)
{
/* DAC to Mono Line Out default volume and route to Output mixer */
snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
/* unmute all outputs */
snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE);
/* PGA to Mono Line Out default volume, disconnect from Output Mixer */
snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
/* Line2 to Mono Out default volume, disconnect from Output Mixer */
snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
}
/*
* initialise the AIC3X driver
* register the mixer and dsp interfaces with the kernel
*/
static int aic3x_init(struct snd_soc_component *component)
{
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT);
snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
/* DAC default volume and mute */
snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
/* DAC to HP default volume and route to Output mixer */
snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
/* DAC to Line Out default volume and route to Output mixer */
snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
/* unmute all outputs */
snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE);
snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE);
snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE);
snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE);
snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE);
snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE);
/* ADC default volume and unmute */
snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN);
snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN);
/* By default route Line1 to ADC PGA mixer */
snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0);
snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0);
/* PGA to HP Bypass default volume, disconnect from Output Mixer */
snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
/* PGA to Line Out default volume, disconnect from Output Mixer */
snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
/* On tlv320aic3104, these registers are reserved and must not be written */
if (aic3x->model != AIC3X_MODEL_3104) {
/* Line2 to HP Bypass default volume, disconnect from Output Mixer */
snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
/* Line2 Line Out default volume, disconnect from Output Mixer */
snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
}
switch (aic3x->model) {
case AIC3X_MODEL_3X:
case AIC3X_MODEL_33:
case AIC3X_MODEL_3106:
aic3x_mono_init(component);
break;
case AIC3X_MODEL_3007:
snd_soc_component_write(component, CLASSD_CTRL, 0);
break;
}
/* Output common-mode voltage = 1.5 V */
snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK,
aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
return 0;
}
static int aic3x_component_probe(struct snd_soc_component *component)
{
struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
int ret, i;
aic3x->component = component;
for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
aic3x->disable_nb[i].aic3x = aic3x;
ret = devm_regulator_register_notifier(
aic3x->supplies[i].consumer,
&aic3x->disable_nb[i].nb);
if (ret) {
dev_err(component->dev,
"Failed to request regulator notifier: %d\n",
ret);
return ret;
}
}
regcache_mark_dirty(aic3x->regmap);
aic3x_init(component);
if (aic3x->setup) {
if (aic3x->model != AIC3X_MODEL_3104) {
/* setup GPIO functions */
snd_soc_component_write(component, AIC3X_GPIO1_REG,
(aic3x->setup->gpio_func[0] & 0xf) << 4);
snd_soc_component_write(component, AIC3X_GPIO2_REG,
(aic3x->setup->gpio_func[1] & 0xf) << 4);
} else {
dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
}
}
switch (aic3x->model) {
case AIC3X_MODEL_3X:
case AIC3X_MODEL_33:
case AIC3X_MODEL_3106:
snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
ARRAY_SIZE(aic3x_extra_snd_controls));
snd_soc_add_component_controls(component, aic3x_mono_controls,
ARRAY_SIZE(aic3x_mono_controls));
break;
case AIC3X_MODEL_3007:
snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
ARRAY_SIZE(aic3x_extra_snd_controls));
snd_soc_add_component_controls(component,
&aic3x_classd_amp_gain_ctrl, 1);
break;
case AIC3X_MODEL_3104:
break;
}
/* set mic bias voltage */
switch (aic3x->micbias_vg) {
case AIC3X_MICBIAS_2_0V:
case AIC3X_MICBIAS_2_5V:
case AIC3X_MICBIAS_AVDDV:
snd_soc_component_update_bits(component, MICBIAS_CTRL,
MICBIAS_LEVEL_MASK,
(aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
break;
case AIC3X_MICBIAS_OFF:
/*
* noting to do. target won't enter here. This is just to avoid
* compile time warning "warning: enumeration value
* 'AIC3X_MICBIAS_OFF' not handled in switch"
*/
break;
}
aic3x_add_widgets(component);
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_aic3x = {
.set_bias_level = aic3x_set_bias_level,
.probe = aic3x_component_probe,
.controls = aic3x_snd_controls,
.num_controls = ARRAY_SIZE(aic3x_snd_controls),
.dapm_widgets = aic3x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.use_pmdown_time = 1,
.endianness = 1,
};
static void aic3x_configure_ocmv(struct device *dev, struct aic3x_priv *aic3x)
{
struct device_node *np = dev->of_node;
u32 value;
int dvdd, avdd;
if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
/* OCMV setting is forced by DT */
if (value <= 3) {
aic3x->ocmv = value;
return;
}
}
dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
if (avdd > 3600000 || dvdd > 1950000) {
dev_warn(dev,
"Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
avdd, dvdd);
} else if (avdd == 3600000 && dvdd == 1950000) {
aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
} else if (avdd > 3300000 && dvdd > 1800000) {
aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
} else if (avdd > 3000000 && dvdd > 1650000) {
aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
} else if (avdd >= 2700000 && dvdd >= 1525000) {
aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
} else {
dev_warn(dev,
"Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
avdd, dvdd);
}
}
static const struct reg_sequence aic3007_class_d[] = {
/* Class-D speaker driver init; datasheet p. 46 */
{ AIC3X_PAGE_SELECT, 0x0D },
{ 0xD, 0x0D },
{ 0x8, 0x5C },
{ 0x8, 0x5D },
{ 0x8, 0x5C },
{ AIC3X_PAGE_SELECT, 0x00 },
};
int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data)
{
struct aic3x_priv *aic3x;
struct aic3x_setup_data *ai3x_setup;
struct device_node *np = dev->of_node;
int ret, i;
u32 value;
aic3x = devm_kzalloc(dev, sizeof(struct aic3x_priv), GFP_KERNEL);
if (!aic3x)
return -ENOMEM;
aic3x->regmap = regmap;
if (IS_ERR(aic3x->regmap)) {
ret = PTR_ERR(aic3x->regmap);
return ret;
}
regcache_cache_only(aic3x->regmap, true);
dev_set_drvdata(dev, aic3x);
if (np) {
ai3x_setup = devm_kzalloc(dev, sizeof(*ai3x_setup), GFP_KERNEL);
if (!ai3x_setup)
return -ENOMEM;
if (of_property_read_u32_array(np, "ai3x-gpio-func",
ai3x_setup->gpio_func, 2) >= 0) {
aic3x->setup = ai3x_setup;
}
if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
switch (value) {
case 1 :
aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
break;
case 2 :
aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
break;
case 3 :
aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
break;
default :
aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
dev_err(dev, "Unsuitable MicBias voltage "
"found in DT\n");
}
} else {
aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
}
}
aic3x->model = driver_data;
aic3x->gpio_reset = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset);
if (ret) {
if (ret != -EBUSY)
return ret;
/*
* Apparently there are setups where the codec is sharing
* its reset line. Try to get it non-exclusively, although
* the utility of this is unclear: how do we make sure that
* resetting one chip will not disturb the others that share
* the same line?
*/
aic3x->gpio_reset = devm_gpiod_get(dev, "reset",
GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset);
if (ret)
return ret;
aic3x->shared_reset = true;
}
gpiod_set_consumer_name(aic3x->gpio_reset, "tlv320aic3x reset");
for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
aic3x->supplies[i].supply = aic3x_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(aic3x->supplies),
aic3x->supplies);
if (ret) {
dev_err(dev, "Failed to request supplies: %d\n", ret);
return ret;
}
aic3x_configure_ocmv(dev, aic3x);
if (aic3x->model == AIC3X_MODEL_3007) {
ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
ARRAY_SIZE(aic3007_class_d));
if (ret != 0)
dev_err(dev, "Failed to init class D: %d\n", ret);
}
ret = devm_snd_soc_register_component(dev, &soc_component_dev_aic3x, &aic3x_dai, 1);
if (ret)
return ret;
return 0;
}
EXPORT_SYMBOL(aic3x_probe);
void aic3x_remove(struct device *dev)
{
struct aic3x_priv *aic3x = dev_get_drvdata(dev);
/* Leave the codec in reset state */
if (aic3x->gpio_reset && !aic3x->shared_reset)
gpiod_set_value(aic3x->gpio_reset, 1);
}
EXPORT_SYMBOL(aic3x_remove);
MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
MODULE_AUTHOR("Vladimir Barinov");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tlv320aic3x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
*
* Copyright 2015 Realtek Semiconductor Corp.
* Author: Bard Liao <[email protected]>
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/acpi.h>
#include <linux/gpio/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5659.h>
#include "rl6231.h"
#include "rt5659.h"
static const struct reg_default rt5659_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0001, 0x4848 },
{ 0x0002, 0x8080 },
{ 0x0003, 0xc8c8 },
{ 0x0004, 0xc80a },
{ 0x0005, 0x0000 },
{ 0x0006, 0x0000 },
{ 0x0007, 0x0103 },
{ 0x0008, 0x0080 },
{ 0x0009, 0x0000 },
{ 0x000a, 0x0000 },
{ 0x000c, 0x0000 },
{ 0x000d, 0x0000 },
{ 0x000f, 0x0808 },
{ 0x0010, 0x3080 },
{ 0x0011, 0x4a00 },
{ 0x0012, 0x4e00 },
{ 0x0015, 0x42c1 },
{ 0x0016, 0x0000 },
{ 0x0018, 0x000b },
{ 0x0019, 0xafaf },
{ 0x001a, 0xafaf },
{ 0x001b, 0x0011 },
{ 0x001c, 0x2f2f },
{ 0x001d, 0x2f2f },
{ 0x001e, 0x2f2f },
{ 0x001f, 0x0000 },
{ 0x0020, 0x0000 },
{ 0x0021, 0x0000 },
{ 0x0022, 0x5757 },
{ 0x0023, 0x0039 },
{ 0x0026, 0xc060 },
{ 0x0027, 0xd8d8 },
{ 0x0029, 0x8080 },
{ 0x002a, 0xaaaa },
{ 0x002b, 0xaaaa },
{ 0x002c, 0x00af },
{ 0x002d, 0x0000 },
{ 0x002f, 0x1002 },
{ 0x0031, 0x5000 },
{ 0x0032, 0x0000 },
{ 0x0033, 0x0000 },
{ 0x0034, 0x0000 },
{ 0x0035, 0x0000 },
{ 0x0036, 0x0000 },
{ 0x003a, 0x0000 },
{ 0x003b, 0x0000 },
{ 0x003c, 0x007f },
{ 0x003d, 0x0000 },
{ 0x003e, 0x007f },
{ 0x0040, 0x0808 },
{ 0x0046, 0x001f },
{ 0x0047, 0x001f },
{ 0x0048, 0x0003 },
{ 0x0049, 0xe061 },
{ 0x004a, 0x0000 },
{ 0x004b, 0x031f },
{ 0x004d, 0x0000 },
{ 0x004e, 0x001f },
{ 0x004f, 0x0000 },
{ 0x0050, 0x001f },
{ 0x0052, 0xf000 },
{ 0x0053, 0x0111 },
{ 0x0054, 0x0064 },
{ 0x0055, 0x0080 },
{ 0x0056, 0xef0e },
{ 0x0057, 0xf0f0 },
{ 0x0058, 0xef0e },
{ 0x0059, 0xf0f0 },
{ 0x005a, 0xef0e },
{ 0x005b, 0xf0f0 },
{ 0x005c, 0xf000 },
{ 0x005d, 0x0000 },
{ 0x005e, 0x1f2c },
{ 0x005f, 0x1f2c },
{ 0x0060, 0x2717 },
{ 0x0061, 0x0000 },
{ 0x0062, 0x0000 },
{ 0x0063, 0x003e },
{ 0x0064, 0x0000 },
{ 0x0065, 0x0000 },
{ 0x0066, 0x0000 },
{ 0x0067, 0x0000 },
{ 0x006a, 0x0000 },
{ 0x006b, 0x0000 },
{ 0x006c, 0x0000 },
{ 0x006e, 0x0000 },
{ 0x006f, 0x0000 },
{ 0x0070, 0x8000 },
{ 0x0071, 0x8000 },
{ 0x0072, 0x8000 },
{ 0x0073, 0x1110 },
{ 0x0074, 0xfe00 },
{ 0x0075, 0x2409 },
{ 0x0076, 0x000a },
{ 0x0077, 0x00f0 },
{ 0x0078, 0x0000 },
{ 0x0079, 0x0000 },
{ 0x007a, 0x0123 },
{ 0x007b, 0x8003 },
{ 0x0080, 0x0000 },
{ 0x0081, 0x0000 },
{ 0x0082, 0x0000 },
{ 0x0083, 0x0000 },
{ 0x0084, 0x0000 },
{ 0x0085, 0x0000 },
{ 0x0086, 0x0008 },
{ 0x0087, 0x0000 },
{ 0x0088, 0x0000 },
{ 0x0089, 0x0000 },
{ 0x008a, 0x0000 },
{ 0x008b, 0x0000 },
{ 0x008c, 0x0003 },
{ 0x008e, 0x0000 },
{ 0x008f, 0x1000 },
{ 0x0090, 0x0646 },
{ 0x0091, 0x0c16 },
{ 0x0092, 0x0073 },
{ 0x0093, 0x0000 },
{ 0x0094, 0x0080 },
{ 0x0097, 0x0000 },
{ 0x0098, 0x0000 },
{ 0x0099, 0x0000 },
{ 0x009a, 0x0000 },
{ 0x009b, 0x0000 },
{ 0x009c, 0x007f },
{ 0x009d, 0x0000 },
{ 0x009e, 0x007f },
{ 0x009f, 0x0000 },
{ 0x00a0, 0x0060 },
{ 0x00a1, 0x90a1 },
{ 0x00ae, 0x2000 },
{ 0x00af, 0x0000 },
{ 0x00b0, 0x2000 },
{ 0x00b1, 0x0000 },
{ 0x00b2, 0x0000 },
{ 0x00b6, 0x0000 },
{ 0x00b7, 0x0000 },
{ 0x00b8, 0x0000 },
{ 0x00b9, 0x0000 },
{ 0x00ba, 0x0000 },
{ 0x00bb, 0x0000 },
{ 0x00be, 0x0000 },
{ 0x00bf, 0x0000 },
{ 0x00c0, 0x0000 },
{ 0x00c1, 0x0000 },
{ 0x00c2, 0x0000 },
{ 0x00c3, 0x0000 },
{ 0x00c4, 0x0003 },
{ 0x00c5, 0x0000 },
{ 0x00cb, 0xa02f },
{ 0x00cc, 0x0000 },
{ 0x00cd, 0x0e02 },
{ 0x00d6, 0x0000 },
{ 0x00d7, 0x2244 },
{ 0x00d9, 0x0809 },
{ 0x00da, 0x0000 },
{ 0x00db, 0x0008 },
{ 0x00dc, 0x00c0 },
{ 0x00dd, 0x6724 },
{ 0x00de, 0x3131 },
{ 0x00df, 0x0008 },
{ 0x00e0, 0x4000 },
{ 0x00e1, 0x3131 },
{ 0x00e4, 0x400c },
{ 0x00e5, 0x8031 },
{ 0x00ea, 0xb320 },
{ 0x00eb, 0x0000 },
{ 0x00ec, 0xb300 },
{ 0x00ed, 0x0000 },
{ 0x00f0, 0x0000 },
{ 0x00f1, 0x0202 },
{ 0x00f2, 0x0ddd },
{ 0x00f3, 0x0ddd },
{ 0x00f4, 0x0ddd },
{ 0x00f6, 0x0000 },
{ 0x00f7, 0x0000 },
{ 0x00f8, 0x0000 },
{ 0x00f9, 0x0000 },
{ 0x00fa, 0x8000 },
{ 0x00fb, 0x0000 },
{ 0x00fc, 0x0000 },
{ 0x00fd, 0x0001 },
{ 0x00fe, 0x10ec },
{ 0x00ff, 0x6311 },
{ 0x0100, 0xaaaa },
{ 0x010a, 0xaaaa },
{ 0x010b, 0x00a0 },
{ 0x010c, 0xaeae },
{ 0x010d, 0xaaaa },
{ 0x010e, 0xaaa8 },
{ 0x010f, 0xa0aa },
{ 0x0110, 0xe02a },
{ 0x0111, 0xa702 },
{ 0x0112, 0xaaaa },
{ 0x0113, 0x2800 },
{ 0x0116, 0x0000 },
{ 0x0117, 0x0f00 },
{ 0x011a, 0x0020 },
{ 0x011b, 0x0011 },
{ 0x011c, 0x0150 },
{ 0x011d, 0x0000 },
{ 0x011e, 0x0000 },
{ 0x011f, 0x0000 },
{ 0x0120, 0x0000 },
{ 0x0121, 0x009b },
{ 0x0122, 0x5014 },
{ 0x0123, 0x0421 },
{ 0x0124, 0x7cea },
{ 0x0125, 0x0420 },
{ 0x0126, 0x5550 },
{ 0x0132, 0x0000 },
{ 0x0133, 0x0000 },
{ 0x0137, 0x5055 },
{ 0x0138, 0x3700 },
{ 0x0139, 0x79a1 },
{ 0x013a, 0x2020 },
{ 0x013b, 0x2020 },
{ 0x013c, 0x2005 },
{ 0x013e, 0x1f00 },
{ 0x013f, 0x0000 },
{ 0x0145, 0x0002 },
{ 0x0146, 0x0000 },
{ 0x0147, 0x0000 },
{ 0x0148, 0x0000 },
{ 0x0150, 0x1813 },
{ 0x0151, 0x0690 },
{ 0x0152, 0x1c17 },
{ 0x0153, 0x6883 },
{ 0x0154, 0xd3ce },
{ 0x0155, 0x352d },
{ 0x0156, 0x00eb },
{ 0x0157, 0x3717 },
{ 0x0158, 0x4c6a },
{ 0x0159, 0xe41b },
{ 0x015a, 0x2a13 },
{ 0x015b, 0xb600 },
{ 0x015c, 0xc730 },
{ 0x015d, 0x35d4 },
{ 0x015e, 0x00bf },
{ 0x0160, 0x0ec0 },
{ 0x0161, 0x0020 },
{ 0x0162, 0x0080 },
{ 0x0163, 0x0800 },
{ 0x0164, 0x0000 },
{ 0x0165, 0x0000 },
{ 0x0166, 0x0000 },
{ 0x0167, 0x001f },
{ 0x0170, 0x4e80 },
{ 0x0171, 0x0020 },
{ 0x0172, 0x0080 },
{ 0x0173, 0x0800 },
{ 0x0174, 0x000c },
{ 0x0175, 0x0000 },
{ 0x0190, 0x3300 },
{ 0x0191, 0x2200 },
{ 0x0192, 0x0000 },
{ 0x01b0, 0x4b38 },
{ 0x01b1, 0x0000 },
{ 0x01b2, 0x0000 },
{ 0x01b3, 0x0000 },
{ 0x01c0, 0x0045 },
{ 0x01c1, 0x0540 },
{ 0x01c2, 0x0000 },
{ 0x01c3, 0x0030 },
{ 0x01c7, 0x0000 },
{ 0x01c8, 0x5757 },
{ 0x01c9, 0x5757 },
{ 0x01ca, 0x5757 },
{ 0x01cb, 0x5757 },
{ 0x01cc, 0x5757 },
{ 0x01cd, 0x5757 },
{ 0x01ce, 0x006f },
{ 0x01da, 0x0000 },
{ 0x01db, 0x0000 },
{ 0x01de, 0x7d00 },
{ 0x01df, 0x10c0 },
{ 0x01e0, 0x06a1 },
{ 0x01e1, 0x0000 },
{ 0x01e2, 0x0000 },
{ 0x01e3, 0x0000 },
{ 0x01e4, 0x0001 },
{ 0x01e6, 0x0000 },
{ 0x01e7, 0x0000 },
{ 0x01e8, 0x0000 },
{ 0x01ea, 0x0000 },
{ 0x01eb, 0x0000 },
{ 0x01ec, 0x0000 },
{ 0x01ed, 0x0000 },
{ 0x01ee, 0x0000 },
{ 0x01ef, 0x0000 },
{ 0x01f0, 0x0000 },
{ 0x01f1, 0x0000 },
{ 0x01f2, 0x0000 },
{ 0x01f6, 0x1e04 },
{ 0x01f7, 0x01a1 },
{ 0x01f8, 0x0000 },
{ 0x01f9, 0x0000 },
{ 0x01fa, 0x0002 },
{ 0x01fb, 0x0000 },
{ 0x01fc, 0x0000 },
{ 0x01fd, 0x0000 },
{ 0x01fe, 0x0000 },
{ 0x0200, 0x066c },
{ 0x0201, 0x7fff },
{ 0x0202, 0x7fff },
{ 0x0203, 0x0000 },
{ 0x0204, 0x0000 },
{ 0x0205, 0x0000 },
{ 0x0206, 0x0000 },
{ 0x0207, 0x0000 },
{ 0x0208, 0x0000 },
{ 0x0256, 0x0000 },
{ 0x0257, 0x0000 },
{ 0x0258, 0x0000 },
{ 0x0259, 0x0000 },
{ 0x025a, 0x0000 },
{ 0x025b, 0x3333 },
{ 0x025c, 0x3333 },
{ 0x025d, 0x3333 },
{ 0x025e, 0x0000 },
{ 0x025f, 0x0000 },
{ 0x0260, 0x0000 },
{ 0x0261, 0x0022 },
{ 0x0262, 0x0300 },
{ 0x0265, 0x1e80 },
{ 0x0266, 0x0131 },
{ 0x0267, 0x0003 },
{ 0x0268, 0x0000 },
{ 0x0269, 0x0000 },
{ 0x026a, 0x0000 },
{ 0x026b, 0x0000 },
{ 0x026c, 0x0000 },
{ 0x026d, 0x0000 },
{ 0x026e, 0x0000 },
{ 0x026f, 0x0000 },
{ 0x0270, 0x0000 },
{ 0x0271, 0x0000 },
{ 0x0272, 0x0000 },
{ 0x0273, 0x0000 },
{ 0x0280, 0x0000 },
{ 0x0281, 0x0000 },
{ 0x0282, 0x0418 },
{ 0x0283, 0x7fff },
{ 0x0284, 0x7000 },
{ 0x0290, 0x01d0 },
{ 0x0291, 0x0100 },
{ 0x02fa, 0x0000 },
{ 0x02fb, 0x0000 },
{ 0x02fc, 0x0000 },
{ 0x0300, 0x001f },
{ 0x0301, 0x032c },
{ 0x0302, 0x5f21 },
{ 0x0303, 0x4000 },
{ 0x0304, 0x4000 },
{ 0x0305, 0x0600 },
{ 0x0306, 0x8000 },
{ 0x0307, 0x0700 },
{ 0x0308, 0x001f },
{ 0x0309, 0x032c },
{ 0x030a, 0x5f21 },
{ 0x030b, 0x4000 },
{ 0x030c, 0x4000 },
{ 0x030d, 0x0600 },
{ 0x030e, 0x8000 },
{ 0x030f, 0x0700 },
{ 0x0310, 0x4560 },
{ 0x0311, 0xa4a8 },
{ 0x0312, 0x7418 },
{ 0x0313, 0x0000 },
{ 0x0314, 0x0006 },
{ 0x0315, 0x00ff },
{ 0x0316, 0xc400 },
{ 0x0317, 0x4560 },
{ 0x0318, 0xa4a8 },
{ 0x0319, 0x7418 },
{ 0x031a, 0x0000 },
{ 0x031b, 0x0006 },
{ 0x031c, 0x00ff },
{ 0x031d, 0xc400 },
{ 0x0320, 0x0f20 },
{ 0x0321, 0x8700 },
{ 0x0322, 0x7dc2 },
{ 0x0323, 0xa178 },
{ 0x0324, 0x5383 },
{ 0x0325, 0x7dc2 },
{ 0x0326, 0xa178 },
{ 0x0327, 0x5383 },
{ 0x0328, 0x003e },
{ 0x0329, 0x02c1 },
{ 0x032a, 0xd37d },
{ 0x0330, 0x00a6 },
{ 0x0331, 0x04c3 },
{ 0x0332, 0x27c8 },
{ 0x0333, 0xbf50 },
{ 0x0334, 0x0045 },
{ 0x0335, 0x2007 },
{ 0x0336, 0x7418 },
{ 0x0337, 0x0501 },
{ 0x0338, 0x0000 },
{ 0x0339, 0x0010 },
{ 0x033a, 0x1010 },
{ 0x0340, 0x0800 },
{ 0x0341, 0x0800 },
{ 0x0342, 0x0800 },
{ 0x0343, 0x0800 },
{ 0x0344, 0x0000 },
{ 0x0345, 0x0000 },
{ 0x0346, 0x0000 },
{ 0x0347, 0x0000 },
{ 0x0348, 0x0000 },
{ 0x0349, 0x0000 },
{ 0x034a, 0x0000 },
{ 0x034b, 0x0000 },
{ 0x034c, 0x0000 },
{ 0x034d, 0x0000 },
{ 0x034e, 0x0000 },
{ 0x034f, 0x0000 },
{ 0x0350, 0x0000 },
{ 0x0351, 0x0000 },
{ 0x0352, 0x0000 },
{ 0x0353, 0x0000 },
{ 0x0354, 0x0000 },
{ 0x0355, 0x0000 },
{ 0x0356, 0x0000 },
{ 0x0357, 0x0000 },
{ 0x0358, 0x0000 },
{ 0x0359, 0x0000 },
{ 0x035a, 0x0000 },
{ 0x035b, 0x0000 },
{ 0x035c, 0x0000 },
{ 0x035d, 0x0000 },
{ 0x035e, 0x2000 },
{ 0x035f, 0x0000 },
{ 0x0360, 0x2000 },
{ 0x0361, 0x2000 },
{ 0x0362, 0x0000 },
{ 0x0363, 0x2000 },
{ 0x0364, 0x0200 },
{ 0x0365, 0x0000 },
{ 0x0366, 0x0000 },
{ 0x0367, 0x0000 },
{ 0x0368, 0x0000 },
{ 0x0369, 0x0000 },
{ 0x036a, 0x0000 },
{ 0x036b, 0x0000 },
{ 0x036c, 0x0000 },
{ 0x036d, 0x0000 },
{ 0x036e, 0x0200 },
{ 0x036f, 0x0000 },
{ 0x0370, 0x0000 },
{ 0x0371, 0x0000 },
{ 0x0372, 0x0000 },
{ 0x0373, 0x0000 },
{ 0x0374, 0x0000 },
{ 0x0375, 0x0000 },
{ 0x0376, 0x0000 },
{ 0x0377, 0x0000 },
{ 0x03d0, 0x0000 },
{ 0x03d1, 0x0000 },
{ 0x03d2, 0x0000 },
{ 0x03d3, 0x0000 },
{ 0x03d4, 0x2000 },
{ 0x03d5, 0x2000 },
{ 0x03d6, 0x0000 },
{ 0x03d7, 0x0000 },
{ 0x03d8, 0x2000 },
{ 0x03d9, 0x2000 },
{ 0x03da, 0x2000 },
{ 0x03db, 0x2000 },
{ 0x03dc, 0x0000 },
{ 0x03dd, 0x0000 },
{ 0x03de, 0x0000 },
{ 0x03df, 0x2000 },
{ 0x03e0, 0x0000 },
{ 0x03e1, 0x0000 },
{ 0x03e2, 0x0000 },
{ 0x03e3, 0x0000 },
{ 0x03e4, 0x0000 },
{ 0x03e5, 0x0000 },
{ 0x03e6, 0x0000 },
{ 0x03e7, 0x0000 },
{ 0x03e8, 0x0000 },
{ 0x03e9, 0x0000 },
{ 0x03ea, 0x0000 },
{ 0x03eb, 0x0000 },
{ 0x03ec, 0x0000 },
{ 0x03ed, 0x0000 },
{ 0x03ee, 0x0000 },
{ 0x03ef, 0x0000 },
{ 0x03f0, 0x0800 },
{ 0x03f1, 0x0800 },
{ 0x03f2, 0x0800 },
{ 0x03f3, 0x0800 },
};
static bool rt5659_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5659_RESET:
case RT5659_EJD_CTRL_2:
case RT5659_SILENCE_CTRL:
case RT5659_DAC2_DIG_VOL:
case RT5659_HP_IMP_GAIN_2:
case RT5659_PDM_OUT_CTRL:
case RT5659_PDM_DATA_CTRL_1:
case RT5659_PDM_DATA_CTRL_4:
case RT5659_HAPTIC_GEN_CTRL_1:
case RT5659_HAPTIC_GEN_CTRL_3:
case RT5659_HAPTIC_LPF_CTRL_3:
case RT5659_CLK_DET:
case RT5659_MICBIAS_1:
case RT5659_ASRC_11:
case RT5659_ADC_EQ_CTRL_1:
case RT5659_DAC_EQ_CTRL_1:
case RT5659_INT_ST_1:
case RT5659_INT_ST_2:
case RT5659_GPIO_STA:
case RT5659_SINE_GEN_CTRL_1:
case RT5659_IL_CMD_1:
case RT5659_4BTN_IL_CMD_1:
case RT5659_PSV_IL_CMD_1:
case RT5659_AJD1_CTRL:
case RT5659_AJD2_AJD3_CTRL:
case RT5659_JD_CTRL_3:
case RT5659_VENDOR_ID:
case RT5659_VENDOR_ID_1:
case RT5659_DEVICE_ID:
case RT5659_MEMORY_TEST:
case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
case RT5659_VOL_TEST:
case RT5659_STO_NG2_CTRL_1:
case RT5659_STO_NG2_CTRL_5:
case RT5659_STO_NG2_CTRL_6:
case RT5659_STO_NG2_CTRL_7:
case RT5659_MONO_NG2_CTRL_1:
case RT5659_MONO_NG2_CTRL_5:
case RT5659_MONO_NG2_CTRL_6:
case RT5659_HP_IMP_SENS_CTRL_1:
case RT5659_HP_IMP_SENS_CTRL_3:
case RT5659_HP_IMP_SENS_CTRL_4:
case RT5659_HP_CALIB_CTRL_1:
case RT5659_HP_CALIB_CTRL_9:
case RT5659_HP_CALIB_STA_1:
case RT5659_HP_CALIB_STA_2:
case RT5659_HP_CALIB_STA_3:
case RT5659_HP_CALIB_STA_4:
case RT5659_HP_CALIB_STA_5:
case RT5659_HP_CALIB_STA_6:
case RT5659_HP_CALIB_STA_7:
case RT5659_HP_CALIB_STA_8:
case RT5659_HP_CALIB_STA_9:
case RT5659_MONO_AMP_CALIB_CTRL_1:
case RT5659_MONO_AMP_CALIB_CTRL_3:
case RT5659_MONO_AMP_CALIB_STA_1:
case RT5659_MONO_AMP_CALIB_STA_2:
case RT5659_MONO_AMP_CALIB_STA_3:
case RT5659_MONO_AMP_CALIB_STA_4:
case RT5659_SPK_PWR_LMT_STA_1:
case RT5659_SPK_PWR_LMT_STA_2:
case RT5659_SPK_PWR_LMT_STA_3:
case RT5659_SPK_PWR_LMT_STA_4:
case RT5659_SPK_PWR_LMT_STA_5:
case RT5659_SPK_PWR_LMT_STA_6:
case RT5659_SPK_DC_CAILB_CTRL_1:
case RT5659_SPK_DC_CAILB_STA_1:
case RT5659_SPK_DC_CAILB_STA_2:
case RT5659_SPK_DC_CAILB_STA_3:
case RT5659_SPK_DC_CAILB_STA_4:
case RT5659_SPK_DC_CAILB_STA_5:
case RT5659_SPK_DC_CAILB_STA_6:
case RT5659_SPK_DC_CAILB_STA_7:
case RT5659_SPK_DC_CAILB_STA_8:
case RT5659_SPK_DC_CAILB_STA_9:
case RT5659_SPK_DC_CAILB_STA_10:
case RT5659_SPK_VDD_STA_1:
case RT5659_SPK_VDD_STA_2:
case RT5659_SPK_DC_DET_CTRL_1:
case RT5659_PURE_DC_DET_CTRL_1:
case RT5659_PURE_DC_DET_CTRL_2:
case RT5659_DRC1_PRIV_1:
case RT5659_DRC1_PRIV_4:
case RT5659_DRC1_PRIV_5:
case RT5659_DRC1_PRIV_6:
case RT5659_DRC1_PRIV_7:
case RT5659_DRC2_PRIV_1:
case RT5659_DRC2_PRIV_4:
case RT5659_DRC2_PRIV_5:
case RT5659_DRC2_PRIV_6:
case RT5659_DRC2_PRIV_7:
case RT5659_ALC_PGA_STA_1:
case RT5659_ALC_PGA_STA_2:
case RT5659_ALC_PGA_STA_3:
return true;
default:
return false;
}
}
static bool rt5659_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5659_RESET:
case RT5659_SPO_VOL:
case RT5659_HP_VOL:
case RT5659_LOUT:
case RT5659_MONO_OUT:
case RT5659_HPL_GAIN:
case RT5659_HPR_GAIN:
case RT5659_MONO_GAIN:
case RT5659_SPDIF_CTRL_1:
case RT5659_SPDIF_CTRL_2:
case RT5659_CAL_BST_CTRL:
case RT5659_IN1_IN2:
case RT5659_IN3_IN4:
case RT5659_INL1_INR1_VOL:
case RT5659_EJD_CTRL_1:
case RT5659_EJD_CTRL_2:
case RT5659_EJD_CTRL_3:
case RT5659_SILENCE_CTRL:
case RT5659_PSV_CTRL:
case RT5659_SIDETONE_CTRL:
case RT5659_DAC1_DIG_VOL:
case RT5659_DAC2_DIG_VOL:
case RT5659_DAC_CTRL:
case RT5659_STO1_ADC_DIG_VOL:
case RT5659_MONO_ADC_DIG_VOL:
case RT5659_STO2_ADC_DIG_VOL:
case RT5659_STO1_BOOST:
case RT5659_MONO_BOOST:
case RT5659_STO2_BOOST:
case RT5659_HP_IMP_GAIN_1:
case RT5659_HP_IMP_GAIN_2:
case RT5659_STO1_ADC_MIXER:
case RT5659_MONO_ADC_MIXER:
case RT5659_AD_DA_MIXER:
case RT5659_STO_DAC_MIXER:
case RT5659_MONO_DAC_MIXER:
case RT5659_DIG_MIXER:
case RT5659_A_DAC_MUX:
case RT5659_DIG_INF23_DATA:
case RT5659_PDM_OUT_CTRL:
case RT5659_PDM_DATA_CTRL_1:
case RT5659_PDM_DATA_CTRL_2:
case RT5659_PDM_DATA_CTRL_3:
case RT5659_PDM_DATA_CTRL_4:
case RT5659_SPDIF_CTRL:
case RT5659_REC1_GAIN:
case RT5659_REC1_L1_MIXER:
case RT5659_REC1_L2_MIXER:
case RT5659_REC1_R1_MIXER:
case RT5659_REC1_R2_MIXER:
case RT5659_CAL_REC:
case RT5659_REC2_L1_MIXER:
case RT5659_REC2_L2_MIXER:
case RT5659_REC2_R1_MIXER:
case RT5659_REC2_R2_MIXER:
case RT5659_SPK_L_MIXER:
case RT5659_SPK_R_MIXER:
case RT5659_SPO_AMP_GAIN:
case RT5659_ALC_BACK_GAIN:
case RT5659_MONOMIX_GAIN:
case RT5659_MONOMIX_IN_GAIN:
case RT5659_OUT_L_GAIN:
case RT5659_OUT_L_MIXER:
case RT5659_OUT_R_GAIN:
case RT5659_OUT_R_MIXER:
case RT5659_LOUT_MIXER:
case RT5659_HAPTIC_GEN_CTRL_1:
case RT5659_HAPTIC_GEN_CTRL_2:
case RT5659_HAPTIC_GEN_CTRL_3:
case RT5659_HAPTIC_GEN_CTRL_4:
case RT5659_HAPTIC_GEN_CTRL_5:
case RT5659_HAPTIC_GEN_CTRL_6:
case RT5659_HAPTIC_GEN_CTRL_7:
case RT5659_HAPTIC_GEN_CTRL_8:
case RT5659_HAPTIC_GEN_CTRL_9:
case RT5659_HAPTIC_GEN_CTRL_10:
case RT5659_HAPTIC_GEN_CTRL_11:
case RT5659_HAPTIC_LPF_CTRL_1:
case RT5659_HAPTIC_LPF_CTRL_2:
case RT5659_HAPTIC_LPF_CTRL_3:
case RT5659_PWR_DIG_1:
case RT5659_PWR_DIG_2:
case RT5659_PWR_ANLG_1:
case RT5659_PWR_ANLG_2:
case RT5659_PWR_ANLG_3:
case RT5659_PWR_MIXER:
case RT5659_PWR_VOL:
case RT5659_PRIV_INDEX:
case RT5659_CLK_DET:
case RT5659_PRIV_DATA:
case RT5659_PRE_DIV_1:
case RT5659_PRE_DIV_2:
case RT5659_I2S1_SDP:
case RT5659_I2S2_SDP:
case RT5659_I2S3_SDP:
case RT5659_ADDA_CLK_1:
case RT5659_ADDA_CLK_2:
case RT5659_DMIC_CTRL_1:
case RT5659_DMIC_CTRL_2:
case RT5659_TDM_CTRL_1:
case RT5659_TDM_CTRL_2:
case RT5659_TDM_CTRL_3:
case RT5659_TDM_CTRL_4:
case RT5659_TDM_CTRL_5:
case RT5659_GLB_CLK:
case RT5659_PLL_CTRL_1:
case RT5659_PLL_CTRL_2:
case RT5659_ASRC_1:
case RT5659_ASRC_2:
case RT5659_ASRC_3:
case RT5659_ASRC_4:
case RT5659_ASRC_5:
case RT5659_ASRC_6:
case RT5659_ASRC_7:
case RT5659_ASRC_8:
case RT5659_ASRC_9:
case RT5659_ASRC_10:
case RT5659_DEPOP_1:
case RT5659_DEPOP_2:
case RT5659_DEPOP_3:
case RT5659_HP_CHARGE_PUMP_1:
case RT5659_HP_CHARGE_PUMP_2:
case RT5659_MICBIAS_1:
case RT5659_MICBIAS_2:
case RT5659_ASRC_11:
case RT5659_ASRC_12:
case RT5659_ASRC_13:
case RT5659_REC_M1_M2_GAIN_CTRL:
case RT5659_RC_CLK_CTRL:
case RT5659_CLASSD_CTRL_1:
case RT5659_CLASSD_CTRL_2:
case RT5659_ADC_EQ_CTRL_1:
case RT5659_ADC_EQ_CTRL_2:
case RT5659_DAC_EQ_CTRL_1:
case RT5659_DAC_EQ_CTRL_2:
case RT5659_DAC_EQ_CTRL_3:
case RT5659_IRQ_CTRL_1:
case RT5659_IRQ_CTRL_2:
case RT5659_IRQ_CTRL_3:
case RT5659_IRQ_CTRL_4:
case RT5659_IRQ_CTRL_5:
case RT5659_IRQ_CTRL_6:
case RT5659_INT_ST_1:
case RT5659_INT_ST_2:
case RT5659_GPIO_CTRL_1:
case RT5659_GPIO_CTRL_2:
case RT5659_GPIO_CTRL_3:
case RT5659_GPIO_CTRL_4:
case RT5659_GPIO_CTRL_5:
case RT5659_GPIO_STA:
case RT5659_SINE_GEN_CTRL_1:
case RT5659_SINE_GEN_CTRL_2:
case RT5659_SINE_GEN_CTRL_3:
case RT5659_HP_AMP_DET_CTRL_1:
case RT5659_HP_AMP_DET_CTRL_2:
case RT5659_SV_ZCD_1:
case RT5659_SV_ZCD_2:
case RT5659_IL_CMD_1:
case RT5659_IL_CMD_2:
case RT5659_IL_CMD_3:
case RT5659_IL_CMD_4:
case RT5659_4BTN_IL_CMD_1:
case RT5659_4BTN_IL_CMD_2:
case RT5659_4BTN_IL_CMD_3:
case RT5659_PSV_IL_CMD_1:
case RT5659_PSV_IL_CMD_2:
case RT5659_ADC_STO1_HP_CTRL_1:
case RT5659_ADC_STO1_HP_CTRL_2:
case RT5659_ADC_MONO_HP_CTRL_1:
case RT5659_ADC_MONO_HP_CTRL_2:
case RT5659_AJD1_CTRL:
case RT5659_AJD2_AJD3_CTRL:
case RT5659_JD1_THD:
case RT5659_JD2_THD:
case RT5659_JD3_THD:
case RT5659_JD_CTRL_1:
case RT5659_JD_CTRL_2:
case RT5659_JD_CTRL_3:
case RT5659_JD_CTRL_4:
case RT5659_DIG_MISC:
case RT5659_DUMMY_2:
case RT5659_DUMMY_3:
case RT5659_VENDOR_ID:
case RT5659_VENDOR_ID_1:
case RT5659_DEVICE_ID:
case RT5659_DAC_ADC_DIG_VOL:
case RT5659_BIAS_CUR_CTRL_1:
case RT5659_BIAS_CUR_CTRL_2:
case RT5659_BIAS_CUR_CTRL_3:
case RT5659_BIAS_CUR_CTRL_4:
case RT5659_BIAS_CUR_CTRL_5:
case RT5659_BIAS_CUR_CTRL_6:
case RT5659_BIAS_CUR_CTRL_7:
case RT5659_BIAS_CUR_CTRL_8:
case RT5659_BIAS_CUR_CTRL_9:
case RT5659_BIAS_CUR_CTRL_10:
case RT5659_MEMORY_TEST:
case RT5659_VREF_REC_OP_FB_CAP_CTRL:
case RT5659_CLASSD_0:
case RT5659_CLASSD_1:
case RT5659_CLASSD_2:
case RT5659_CLASSD_3:
case RT5659_CLASSD_4:
case RT5659_CLASSD_5:
case RT5659_CLASSD_6:
case RT5659_CLASSD_7:
case RT5659_CLASSD_8:
case RT5659_CLASSD_9:
case RT5659_CLASSD_10:
case RT5659_CHARGE_PUMP_1:
case RT5659_CHARGE_PUMP_2:
case RT5659_DIG_IN_CTRL_1:
case RT5659_DIG_IN_CTRL_2:
case RT5659_PAD_DRIVING_CTRL:
case RT5659_SOFT_RAMP_DEPOP:
case RT5659_PLL:
case RT5659_CHOP_DAC:
case RT5659_CHOP_ADC:
case RT5659_CALIB_ADC_CTRL:
case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
case RT5659_VOL_TEST:
case RT5659_TEST_MODE_CTRL_1:
case RT5659_TEST_MODE_CTRL_2:
case RT5659_TEST_MODE_CTRL_3:
case RT5659_TEST_MODE_CTRL_4:
case RT5659_BASSBACK_CTRL:
case RT5659_MP3_PLUS_CTRL_1:
case RT5659_MP3_PLUS_CTRL_2:
case RT5659_MP3_HPF_A1:
case RT5659_MP3_HPF_A2:
case RT5659_MP3_HPF_H0:
case RT5659_MP3_LPF_H0:
case RT5659_3D_SPK_CTRL:
case RT5659_3D_SPK_COEF_1:
case RT5659_3D_SPK_COEF_2:
case RT5659_3D_SPK_COEF_3:
case RT5659_3D_SPK_COEF_4:
case RT5659_3D_SPK_COEF_5:
case RT5659_3D_SPK_COEF_6:
case RT5659_3D_SPK_COEF_7:
case RT5659_STO_NG2_CTRL_1:
case RT5659_STO_NG2_CTRL_2:
case RT5659_STO_NG2_CTRL_3:
case RT5659_STO_NG2_CTRL_4:
case RT5659_STO_NG2_CTRL_5:
case RT5659_STO_NG2_CTRL_6:
case RT5659_STO_NG2_CTRL_7:
case RT5659_STO_NG2_CTRL_8:
case RT5659_MONO_NG2_CTRL_1:
case RT5659_MONO_NG2_CTRL_2:
case RT5659_MONO_NG2_CTRL_3:
case RT5659_MONO_NG2_CTRL_4:
case RT5659_MONO_NG2_CTRL_5:
case RT5659_MONO_NG2_CTRL_6:
case RT5659_MID_HP_AMP_DET:
case RT5659_LOW_HP_AMP_DET:
case RT5659_LDO_CTRL:
case RT5659_HP_DECROSS_CTRL_1:
case RT5659_HP_DECROSS_CTRL_2:
case RT5659_HP_DECROSS_CTRL_3:
case RT5659_HP_DECROSS_CTRL_4:
case RT5659_HP_IMP_SENS_CTRL_1:
case RT5659_HP_IMP_SENS_CTRL_2:
case RT5659_HP_IMP_SENS_CTRL_3:
case RT5659_HP_IMP_SENS_CTRL_4:
case RT5659_HP_IMP_SENS_MAP_1:
case RT5659_HP_IMP_SENS_MAP_2:
case RT5659_HP_IMP_SENS_MAP_3:
case RT5659_HP_IMP_SENS_MAP_4:
case RT5659_HP_IMP_SENS_MAP_5:
case RT5659_HP_IMP_SENS_MAP_6:
case RT5659_HP_IMP_SENS_MAP_7:
case RT5659_HP_IMP_SENS_MAP_8:
case RT5659_HP_LOGIC_CTRL_1:
case RT5659_HP_LOGIC_CTRL_2:
case RT5659_HP_CALIB_CTRL_1:
case RT5659_HP_CALIB_CTRL_2:
case RT5659_HP_CALIB_CTRL_3:
case RT5659_HP_CALIB_CTRL_4:
case RT5659_HP_CALIB_CTRL_5:
case RT5659_HP_CALIB_CTRL_6:
case RT5659_HP_CALIB_CTRL_7:
case RT5659_HP_CALIB_CTRL_9:
case RT5659_HP_CALIB_CTRL_10:
case RT5659_HP_CALIB_CTRL_11:
case RT5659_HP_CALIB_STA_1:
case RT5659_HP_CALIB_STA_2:
case RT5659_HP_CALIB_STA_3:
case RT5659_HP_CALIB_STA_4:
case RT5659_HP_CALIB_STA_5:
case RT5659_HP_CALIB_STA_6:
case RT5659_HP_CALIB_STA_7:
case RT5659_HP_CALIB_STA_8:
case RT5659_HP_CALIB_STA_9:
case RT5659_MONO_AMP_CALIB_CTRL_1:
case RT5659_MONO_AMP_CALIB_CTRL_2:
case RT5659_MONO_AMP_CALIB_CTRL_3:
case RT5659_MONO_AMP_CALIB_CTRL_4:
case RT5659_MONO_AMP_CALIB_CTRL_5:
case RT5659_MONO_AMP_CALIB_STA_1:
case RT5659_MONO_AMP_CALIB_STA_2:
case RT5659_MONO_AMP_CALIB_STA_3:
case RT5659_MONO_AMP_CALIB_STA_4:
case RT5659_SPK_PWR_LMT_CTRL_1:
case RT5659_SPK_PWR_LMT_CTRL_2:
case RT5659_SPK_PWR_LMT_CTRL_3:
case RT5659_SPK_PWR_LMT_STA_1:
case RT5659_SPK_PWR_LMT_STA_2:
case RT5659_SPK_PWR_LMT_STA_3:
case RT5659_SPK_PWR_LMT_STA_4:
case RT5659_SPK_PWR_LMT_STA_5:
case RT5659_SPK_PWR_LMT_STA_6:
case RT5659_FLEX_SPK_BST_CTRL_1:
case RT5659_FLEX_SPK_BST_CTRL_2:
case RT5659_FLEX_SPK_BST_CTRL_3:
case RT5659_FLEX_SPK_BST_CTRL_4:
case RT5659_SPK_EX_LMT_CTRL_1:
case RT5659_SPK_EX_LMT_CTRL_2:
case RT5659_SPK_EX_LMT_CTRL_3:
case RT5659_SPK_EX_LMT_CTRL_4:
case RT5659_SPK_EX_LMT_CTRL_5:
case RT5659_SPK_EX_LMT_CTRL_6:
case RT5659_SPK_EX_LMT_CTRL_7:
case RT5659_ADJ_HPF_CTRL_1:
case RT5659_ADJ_HPF_CTRL_2:
case RT5659_SPK_DC_CAILB_CTRL_1:
case RT5659_SPK_DC_CAILB_CTRL_2:
case RT5659_SPK_DC_CAILB_CTRL_3:
case RT5659_SPK_DC_CAILB_CTRL_4:
case RT5659_SPK_DC_CAILB_CTRL_5:
case RT5659_SPK_DC_CAILB_STA_1:
case RT5659_SPK_DC_CAILB_STA_2:
case RT5659_SPK_DC_CAILB_STA_3:
case RT5659_SPK_DC_CAILB_STA_4:
case RT5659_SPK_DC_CAILB_STA_5:
case RT5659_SPK_DC_CAILB_STA_6:
case RT5659_SPK_DC_CAILB_STA_7:
case RT5659_SPK_DC_CAILB_STA_8:
case RT5659_SPK_DC_CAILB_STA_9:
case RT5659_SPK_DC_CAILB_STA_10:
case RT5659_SPK_VDD_STA_1:
case RT5659_SPK_VDD_STA_2:
case RT5659_SPK_DC_DET_CTRL_1:
case RT5659_SPK_DC_DET_CTRL_2:
case RT5659_SPK_DC_DET_CTRL_3:
case RT5659_PURE_DC_DET_CTRL_1:
case RT5659_PURE_DC_DET_CTRL_2:
case RT5659_DUMMY_4:
case RT5659_DUMMY_5:
case RT5659_DUMMY_6:
case RT5659_DRC1_CTRL_1:
case RT5659_DRC1_CTRL_2:
case RT5659_DRC1_CTRL_3:
case RT5659_DRC1_CTRL_4:
case RT5659_DRC1_CTRL_5:
case RT5659_DRC1_CTRL_6:
case RT5659_DRC1_HARD_LMT_CTRL_1:
case RT5659_DRC1_HARD_LMT_CTRL_2:
case RT5659_DRC2_CTRL_1:
case RT5659_DRC2_CTRL_2:
case RT5659_DRC2_CTRL_3:
case RT5659_DRC2_CTRL_4:
case RT5659_DRC2_CTRL_5:
case RT5659_DRC2_CTRL_6:
case RT5659_DRC2_HARD_LMT_CTRL_1:
case RT5659_DRC2_HARD_LMT_CTRL_2:
case RT5659_DRC1_PRIV_1:
case RT5659_DRC1_PRIV_2:
case RT5659_DRC1_PRIV_3:
case RT5659_DRC1_PRIV_4:
case RT5659_DRC1_PRIV_5:
case RT5659_DRC1_PRIV_6:
case RT5659_DRC1_PRIV_7:
case RT5659_DRC2_PRIV_1:
case RT5659_DRC2_PRIV_2:
case RT5659_DRC2_PRIV_3:
case RT5659_DRC2_PRIV_4:
case RT5659_DRC2_PRIV_5:
case RT5659_DRC2_PRIV_6:
case RT5659_DRC2_PRIV_7:
case RT5659_MULTI_DRC_CTRL:
case RT5659_CROSS_OVER_1:
case RT5659_CROSS_OVER_2:
case RT5659_CROSS_OVER_3:
case RT5659_CROSS_OVER_4:
case RT5659_CROSS_OVER_5:
case RT5659_CROSS_OVER_6:
case RT5659_CROSS_OVER_7:
case RT5659_CROSS_OVER_8:
case RT5659_CROSS_OVER_9:
case RT5659_CROSS_OVER_10:
case RT5659_ALC_PGA_CTRL_1:
case RT5659_ALC_PGA_CTRL_2:
case RT5659_ALC_PGA_CTRL_3:
case RT5659_ALC_PGA_CTRL_4:
case RT5659_ALC_PGA_CTRL_5:
case RT5659_ALC_PGA_CTRL_6:
case RT5659_ALC_PGA_CTRL_7:
case RT5659_ALC_PGA_CTRL_8:
case RT5659_ALC_PGA_STA_1:
case RT5659_ALC_PGA_STA_2:
case RT5659_ALC_PGA_STA_3:
case RT5659_DAC_L_EQ_PRE_VOL:
case RT5659_DAC_R_EQ_PRE_VOL:
case RT5659_DAC_L_EQ_POST_VOL:
case RT5659_DAC_R_EQ_POST_VOL:
case RT5659_DAC_L_EQ_LPF1_A1:
case RT5659_DAC_L_EQ_LPF1_H0:
case RT5659_DAC_R_EQ_LPF1_A1:
case RT5659_DAC_R_EQ_LPF1_H0:
case RT5659_DAC_L_EQ_BPF2_A1:
case RT5659_DAC_L_EQ_BPF2_A2:
case RT5659_DAC_L_EQ_BPF2_H0:
case RT5659_DAC_R_EQ_BPF2_A1:
case RT5659_DAC_R_EQ_BPF2_A2:
case RT5659_DAC_R_EQ_BPF2_H0:
case RT5659_DAC_L_EQ_BPF3_A1:
case RT5659_DAC_L_EQ_BPF3_A2:
case RT5659_DAC_L_EQ_BPF3_H0:
case RT5659_DAC_R_EQ_BPF3_A1:
case RT5659_DAC_R_EQ_BPF3_A2:
case RT5659_DAC_R_EQ_BPF3_H0:
case RT5659_DAC_L_EQ_BPF4_A1:
case RT5659_DAC_L_EQ_BPF4_A2:
case RT5659_DAC_L_EQ_BPF4_H0:
case RT5659_DAC_R_EQ_BPF4_A1:
case RT5659_DAC_R_EQ_BPF4_A2:
case RT5659_DAC_R_EQ_BPF4_H0:
case RT5659_DAC_L_EQ_HPF1_A1:
case RT5659_DAC_L_EQ_HPF1_H0:
case RT5659_DAC_R_EQ_HPF1_A1:
case RT5659_DAC_R_EQ_HPF1_H0:
case RT5659_DAC_L_EQ_HPF2_A1:
case RT5659_DAC_L_EQ_HPF2_A2:
case RT5659_DAC_L_EQ_HPF2_H0:
case RT5659_DAC_R_EQ_HPF2_A1:
case RT5659_DAC_R_EQ_HPF2_A2:
case RT5659_DAC_R_EQ_HPF2_H0:
case RT5659_DAC_L_BI_EQ_BPF1_H0_1:
case RT5659_DAC_L_BI_EQ_BPF1_H0_2:
case RT5659_DAC_L_BI_EQ_BPF1_B1_1:
case RT5659_DAC_L_BI_EQ_BPF1_B1_2:
case RT5659_DAC_L_BI_EQ_BPF1_B2_1:
case RT5659_DAC_L_BI_EQ_BPF1_B2_2:
case RT5659_DAC_L_BI_EQ_BPF1_A1_1:
case RT5659_DAC_L_BI_EQ_BPF1_A1_2:
case RT5659_DAC_L_BI_EQ_BPF1_A2_1:
case RT5659_DAC_L_BI_EQ_BPF1_A2_2:
case RT5659_DAC_R_BI_EQ_BPF1_H0_1:
case RT5659_DAC_R_BI_EQ_BPF1_H0_2:
case RT5659_DAC_R_BI_EQ_BPF1_B1_1:
case RT5659_DAC_R_BI_EQ_BPF1_B1_2:
case RT5659_DAC_R_BI_EQ_BPF1_B2_1:
case RT5659_DAC_R_BI_EQ_BPF1_B2_2:
case RT5659_DAC_R_BI_EQ_BPF1_A1_1:
case RT5659_DAC_R_BI_EQ_BPF1_A1_2:
case RT5659_DAC_R_BI_EQ_BPF1_A2_1:
case RT5659_DAC_R_BI_EQ_BPF1_A2_2:
case RT5659_ADC_L_EQ_LPF1_A1:
case RT5659_ADC_R_EQ_LPF1_A1:
case RT5659_ADC_L_EQ_LPF1_H0:
case RT5659_ADC_R_EQ_LPF1_H0:
case RT5659_ADC_L_EQ_BPF1_A1:
case RT5659_ADC_R_EQ_BPF1_A1:
case RT5659_ADC_L_EQ_BPF1_A2:
case RT5659_ADC_R_EQ_BPF1_A2:
case RT5659_ADC_L_EQ_BPF1_H0:
case RT5659_ADC_R_EQ_BPF1_H0:
case RT5659_ADC_L_EQ_BPF2_A1:
case RT5659_ADC_R_EQ_BPF2_A1:
case RT5659_ADC_L_EQ_BPF2_A2:
case RT5659_ADC_R_EQ_BPF2_A2:
case RT5659_ADC_L_EQ_BPF2_H0:
case RT5659_ADC_R_EQ_BPF2_H0:
case RT5659_ADC_L_EQ_BPF3_A1:
case RT5659_ADC_R_EQ_BPF3_A1:
case RT5659_ADC_L_EQ_BPF3_A2:
case RT5659_ADC_R_EQ_BPF3_A2:
case RT5659_ADC_L_EQ_BPF3_H0:
case RT5659_ADC_R_EQ_BPF3_H0:
case RT5659_ADC_L_EQ_BPF4_A1:
case RT5659_ADC_R_EQ_BPF4_A1:
case RT5659_ADC_L_EQ_BPF4_A2:
case RT5659_ADC_R_EQ_BPF4_A2:
case RT5659_ADC_L_EQ_BPF4_H0:
case RT5659_ADC_R_EQ_BPF4_H0:
case RT5659_ADC_L_EQ_HPF1_A1:
case RT5659_ADC_R_EQ_HPF1_A1:
case RT5659_ADC_L_EQ_HPF1_H0:
case RT5659_ADC_R_EQ_HPF1_H0:
case RT5659_ADC_L_EQ_PRE_VOL:
case RT5659_ADC_R_EQ_PRE_VOL:
case RT5659_ADC_L_EQ_POST_VOL:
case RT5659_ADC_R_EQ_POST_VOL:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
/* Interface data select */
static const char * const rt5659_data_select[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(rt5659_if1_01_adc_enum,
RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT01_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if1_23_adc_enum,
RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT23_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if1_45_adc_enum,
RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT45_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if1_67_adc_enum,
RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT67_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if2_dac_enum,
RT5659_DIG_INF23_DATA, RT5659_IF2_DAC_SEL_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if2_adc_enum,
RT5659_DIG_INF23_DATA, RT5659_IF2_ADC_SEL_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if3_dac_enum,
RT5659_DIG_INF23_DATA, RT5659_IF3_DAC_SEL_SFT, rt5659_data_select);
static SOC_ENUM_SINGLE_DECL(rt5659_if3_adc_enum,
RT5659_DIG_INF23_DATA, RT5659_IF3_ADC_SEL_SFT, rt5659_data_select);
static const struct snd_kcontrol_new rt5659_if1_01_adc_swap_mux =
SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
static const struct snd_kcontrol_new rt5659_if1_23_adc_swap_mux =
SOC_DAPM_ENUM("IF1 23 ADC1 Swap Source", rt5659_if1_23_adc_enum);
static const struct snd_kcontrol_new rt5659_if1_45_adc_swap_mux =
SOC_DAPM_ENUM("IF1 45 ADC1 Swap Source", rt5659_if1_45_adc_enum);
static const struct snd_kcontrol_new rt5659_if1_67_adc_swap_mux =
SOC_DAPM_ENUM("IF1 67 ADC1 Swap Source", rt5659_if1_67_adc_enum);
static const struct snd_kcontrol_new rt5659_if2_dac_swap_mux =
SOC_DAPM_ENUM("IF2 DAC Swap Source", rt5659_if2_dac_enum);
static const struct snd_kcontrol_new rt5659_if2_adc_swap_mux =
SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
static const struct snd_kcontrol_new rt5659_if3_dac_swap_mux =
SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5659_if3_dac_enum);
static const struct snd_kcontrol_new rt5659_if3_adc_swap_mux =
SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
static int rt5659_hp_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int ret = snd_soc_put_volsw(kcontrol, ucontrol);
if (snd_soc_component_read(component, RT5659_STO_NG2_CTRL_1) & RT5659_NG2_EN) {
snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1,
RT5659_NG2_EN_MASK, RT5659_NG2_DIS);
snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1,
RT5659_NG2_EN_MASK, RT5659_NG2_EN);
}
return ret;
}
static void rt5659_enable_push_button_irq(struct snd_soc_component *component,
bool enable)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
if (enable) {
snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, 0x000b);
/* MICBIAS1 and Mic Det Power for button detect*/
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
snd_soc_dapm_force_enable_pin(dapm,
"Mic Det Power");
snd_soc_dapm_sync(dapm);
snd_soc_component_update_bits(component, RT5659_PWR_ANLG_2,
RT5659_PWR_MB1, RT5659_PWR_MB1);
snd_soc_component_update_bits(component, RT5659_PWR_VOL,
RT5659_PWR_MIC_DET, RT5659_PWR_MIC_DET);
snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2,
RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2,
RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
} else {
snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2,
RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_DIS);
snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2,
RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_DIS);
/* MICBIAS1 and Mic Det Power for button detect*/
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
}
}
/**
* rt5659_headset_detect - Detect headset.
* @component: SoC audio component device.
* @jack_insert: Jack insert or not.
*
* Detect whether is headset or not when jack inserted.
*
* Returns detect status.
*/
static int rt5659_headset_detect(struct snd_soc_component *component, int jack_insert)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
int reg_63;
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
if (jack_insert) {
snd_soc_dapm_force_enable_pin(dapm,
"Mic Det Power");
snd_soc_dapm_sync(dapm);
reg_63 = snd_soc_component_read(component, RT5659_PWR_ANLG_1);
snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1,
RT5659_PWR_VREF2 | RT5659_PWR_MB,
RT5659_PWR_VREF2 | RT5659_PWR_MB);
msleep(20);
snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1,
RT5659_PWR_FV2, RT5659_PWR_FV2);
snd_soc_component_write(component, RT5659_EJD_CTRL_2, 0x4160);
snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1,
0x20, 0x0);
msleep(20);
snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1,
0x20, 0x20);
while (i < 5) {
msleep(sleep_time[i]);
val = snd_soc_component_read(component, RT5659_EJD_CTRL_2) & 0x0003;
i++;
if (val == 0x1 || val == 0x2 || val == 0x3)
break;
}
switch (val) {
case 1:
rt5659->jack_type = SND_JACK_HEADSET;
rt5659_enable_push_button_irq(component, true);
break;
default:
snd_soc_component_write(component, RT5659_PWR_ANLG_1, reg_63);
rt5659->jack_type = SND_JACK_HEADPHONE;
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
break;
}
} else {
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_sync(dapm);
if (rt5659->jack_type == SND_JACK_HEADSET)
rt5659_enable_push_button_irq(component, false);
rt5659->jack_type = 0;
}
dev_dbg(component->dev, "jack_type = %d\n", rt5659->jack_type);
return rt5659->jack_type;
}
static int rt5659_button_detect(struct snd_soc_component *component)
{
int btn_type, val;
val = snd_soc_component_read(component, RT5659_4BTN_IL_CMD_1);
btn_type = val & 0xfff0;
snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, val);
return btn_type;
}
static irqreturn_t rt5659_irq(int irq, void *data)
{
struct rt5659_priv *rt5659 = data;
queue_delayed_work(system_power_efficient_wq,
&rt5659->jack_detect_work, msecs_to_jiffies(250));
return IRQ_HANDLED;
}
int rt5659_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack)
{
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
rt5659->hs_jack = hs_jack;
rt5659_irq(0, rt5659);
return 0;
}
EXPORT_SYMBOL_GPL(rt5659_set_jack_detect);
static void rt5659_jack_detect_work(struct work_struct *work)
{
struct rt5659_priv *rt5659 =
container_of(work, struct rt5659_priv, jack_detect_work.work);
int val, btn_type, report = 0;
if (!rt5659->component)
return;
val = snd_soc_component_read(rt5659->component, RT5659_INT_ST_1) & 0x0080;
if (!val) {
/* jack in */
if (rt5659->jack_type == 0) {
/* jack was out, report jack type */
report = rt5659_headset_detect(rt5659->component, 1);
} else {
/* jack is already in, report button event */
report = SND_JACK_HEADSET;
btn_type = rt5659_button_detect(rt5659->component);
/**
* rt5659 can report three kinds of button behavior,
* one click, double click and hold. However,
* currently we will report button pressed/released
* event. So all the three button behaviors are
* treated as button pressed.
*/
switch (btn_type) {
case 0x8000:
case 0x4000:
case 0x2000:
report |= SND_JACK_BTN_0;
break;
case 0x1000:
case 0x0800:
case 0x0400:
report |= SND_JACK_BTN_1;
break;
case 0x0200:
case 0x0100:
case 0x0080:
report |= SND_JACK_BTN_2;
break;
case 0x0040:
case 0x0020:
case 0x0010:
report |= SND_JACK_BTN_3;
break;
case 0x0000: /* unpressed */
break;
default:
btn_type = 0;
dev_err(rt5659->component->dev,
"Unexpected button code 0x%04x\n",
btn_type);
break;
}
/* button release or spurious interrput*/
if (btn_type == 0)
report = rt5659->jack_type;
}
} else {
/* jack out */
report = rt5659_headset_detect(rt5659->component, 0);
}
snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
}
static void rt5659_jack_detect_intel_hd_header(struct work_struct *work)
{
struct rt5659_priv *rt5659 =
container_of(work, struct rt5659_priv, jack_detect_work.work);
unsigned int value;
bool hp_flag, mic_flag;
if (!rt5659->hs_jack)
return;
/* headphone jack */
regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value);
hp_flag = (!(value & 0x8)) ? true : false;
if (hp_flag != rt5659->hda_hp_plugged) {
rt5659->hda_hp_plugged = hp_flag;
if (hp_flag) {
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
0x10, 0x0);
rt5659->jack_type |= SND_JACK_HEADPHONE;
} else {
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
0x10, 0x10);
rt5659->jack_type = rt5659->jack_type &
(~SND_JACK_HEADPHONE);
}
snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type,
SND_JACK_HEADPHONE);
}
/* mic jack */
regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value);
mic_flag = (value & 0x2000) ? true : false;
if (mic_flag != rt5659->hda_mic_plugged) {
rt5659->hda_mic_plugged = mic_flag;
if (mic_flag) {
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
0x2, 0x2);
rt5659->jack_type |= SND_JACK_MICROPHONE;
} else {
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
0x2, 0x0);
rt5659->jack_type = rt5659->jack_type
& (~SND_JACK_MICROPHONE);
}
snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type,
SND_JACK_MICROPHONE);
}
}
static const struct snd_kcontrol_new rt5659_snd_controls[] = {
/* Speaker Output Volume */
SOC_DOUBLE_TLV("Speaker Playback Volume", RT5659_SPO_VOL,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
/* Headphone Output Volume */
SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5659_HPL_GAIN,
RT5659_HPR_GAIN, RT5659_G_HP_SFT, 31, 1, snd_soc_get_volsw,
rt5659_hp_vol_put, hp_vol_tlv),
/* Mono Output Volume */
SOC_SINGLE_TLV("Mono Playback Volume", RT5659_MONO_OUT,
RT5659_L_VOL_SFT, 39, 1, out_vol_tlv),
/* Output Volume */
SOC_DOUBLE_TLV("OUT Playback Volume", RT5659_LOUT,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5659_DAC1_DIG_VOL,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
SOC_DOUBLE("DAC1 Playback Switch", RT5659_AD_DA_MIXER,
RT5659_M_DAC1_L_SFT, RT5659_M_DAC1_R_SFT, 1, 1),
SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5659_DAC2_DIG_VOL,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
SOC_DOUBLE("DAC2 Playback Switch", RT5659_DAC_CTRL,
RT5659_M_DAC2_L_VOL_SFT, RT5659_M_DAC2_R_VOL_SFT, 1, 1),
/* IN1/IN2/IN3/IN4 Volume */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5659_IN1_IN2,
RT5659_BST1_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5659_IN1_IN2,
RT5659_BST2_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN3 Boost Volume", RT5659_IN3_IN4,
RT5659_BST3_SFT, 69, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN4 Boost Volume", RT5659_IN3_IN4,
RT5659_BST4_SFT, 69, 0, in_bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5659_INL1_INR1_VOL,
RT5659_INL_VOL_SFT, RT5659_INR_VOL_SFT, 31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
RT5659_STO1_ADC_L_BST_SFT, RT5659_STO1_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
RT5659_MONO_ADC_L_BST_SFT, RT5659_MONO_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
RT5659_STO2_ADC_L_BST_SFT, RT5659_STO2_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_SINGLE("DAC IF1 DAC1 L Data Switch", RT5659_TDM_CTRL_4, 12, 7, 0),
SOC_SINGLE("DAC IF1 DAC1 R Data Switch", RT5659_TDM_CTRL_4, 8, 7, 0),
SOC_SINGLE("DAC IF1 DAC2 L Data Switch", RT5659_TDM_CTRL_4, 4, 7, 0),
SOC_SINGLE("DAC IF1 DAC2 R Data Switch", RT5659_TDM_CTRL_4, 0, 7, 0),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
int pd, idx;
pd = rl6231_get_pre_div(rt5659->regmap,
RT5659_ADDA_CLK_1, RT5659_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else {
snd_soc_component_update_bits(component, RT5659_DMIC_CTRL_1,
RT5659_DMIC_CLK_MASK, idx << RT5659_DMIC_CLK_SFT);
}
return idx;
}
static int set_adc1_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK,
RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, 0);
break;
default:
return 0;
}
return 0;
}
static int set_adc2_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK,
RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5659_charge_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Depop */
snd_soc_component_write(component, RT5659_DEPOP_1, 0x0009);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
break;
default:
return 0;
}
return 0;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
val = snd_soc_component_read(component, RT5659_GLB_CLK);
val &= RT5659_SCLK_SRC_MASK;
if (val == RT5659_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, shift, val;
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (w->shift) {
case RT5659_ADC_MONO_R_ASRC_SFT:
reg = RT5659_ASRC_3;
shift = RT5659_AD_MONO_R_T_SFT;
break;
case RT5659_ADC_MONO_L_ASRC_SFT:
reg = RT5659_ASRC_3;
shift = RT5659_AD_MONO_L_T_SFT;
break;
case RT5659_ADC_STO1_ASRC_SFT:
reg = RT5659_ASRC_2;
shift = RT5659_AD_STO1_T_SFT;
break;
case RT5659_DAC_MONO_R_ASRC_SFT:
reg = RT5659_ASRC_2;
shift = RT5659_DA_MONO_R_T_SFT;
break;
case RT5659_DAC_MONO_L_ASRC_SFT:
reg = RT5659_ASRC_2;
shift = RT5659_DA_MONO_L_T_SFT;
break;
case RT5659_DAC_STO_ASRC_SFT:
reg = RT5659_ASRC_2;
shift = RT5659_DA_STO_T_SFT;
break;
default:
return 0;
}
val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
switch (val) {
case 1:
case 2:
case 3:
/* I2S_Pre_Div1 should be 1 in asrc mode */
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
RT5659_I2S_PD1_MASK, RT5659_I2S_PD1_2);
return 1;
default:
return 0;
}
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5659_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
RT5659_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
RT5659_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
RT5659_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
RT5659_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
RT5659_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
RT5659_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
RT5659_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
RT5659_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
RT5659_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
RT5659_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
RT5659_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
RT5659_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_L1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_R1_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_L2_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_R2_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_L1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_R1_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_L2_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
RT5659_M_DAC_R2_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_L1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_R1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_L2_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_R2_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_L1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_R1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_L2_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
RT5659_M_DAC_R2_MONO_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5659_rec1_l_mix[] = {
SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC1_L2_MIXER,
RT5659_M_SPKVOLL_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5659_REC1_L2_MIXER,
RT5659_M_INL_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_L2_MIXER,
RT5659_M_BST4_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_L2_MIXER,
RT5659_M_BST3_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_L2_MIXER,
RT5659_M_BST2_RM1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_L2_MIXER,
RT5659_M_BST1_RM1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_rec1_r_mix[] = {
SOC_DAPM_SINGLE("HPOVOLR Switch", RT5659_REC1_L2_MIXER,
RT5659_M_HPOVOLR_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5659_REC1_R2_MIXER,
RT5659_M_INR_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_R2_MIXER,
RT5659_M_BST4_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_R2_MIXER,
RT5659_M_BST3_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_R2_MIXER,
RT5659_M_BST2_RM1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_R2_MIXER,
RT5659_M_BST1_RM1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_rec2_l_mix[] = {
SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC2_L2_MIXER,
RT5659_M_SPKVOL_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOLL Switch", RT5659_REC2_L2_MIXER,
RT5659_M_OUTVOLL_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_L2_MIXER,
RT5659_M_BST4_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_L2_MIXER,
RT5659_M_BST3_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_L2_MIXER,
RT5659_M_BST2_RM2_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_L2_MIXER,
RT5659_M_BST1_RM2_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_rec2_r_mix[] = {
SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_REC2_R2_MIXER,
RT5659_M_MONOVOL_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOLR Switch", RT5659_REC2_R2_MIXER,
RT5659_M_OUTVOLR_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_R2_MIXER,
RT5659_M_BST4_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_R2_MIXER,
RT5659_M_BST3_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_R2_MIXER,
RT5659_M_BST2_RM2_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_R2_MIXER,
RT5659_M_BST1_RM2_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_spk_l_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPK_L_MIXER,
RT5659_M_DAC_L2_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_SPK_L_MIXER,
RT5659_M_BST1_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_L_MIXER,
RT5659_M_IN_L_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_L_MIXER,
RT5659_M_IN_R_SM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_L_MIXER,
RT5659_M_BST3_SM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_spk_r_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPK_R_MIXER,
RT5659_M_DAC_R2_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5659_SPK_R_MIXER,
RT5659_M_BST4_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_R_MIXER,
RT5659_M_IN_L_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_R_MIXER,
RT5659_M_IN_R_SM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_R_MIXER,
RT5659_M_BST3_SM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_monovol_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_DAC_L2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_DAC_R2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_BST1_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_BST2_MM_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_BST3_MM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_out_l_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_OUT_L_MIXER,
RT5659_M_DAC_L2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5659_OUT_L_MIXER,
RT5659_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5659_OUT_L_MIXER,
RT5659_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_L_MIXER,
RT5659_M_BST2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_L_MIXER,
RT5659_M_BST3_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_out_r_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_OUT_R_MIXER,
RT5659_M_DAC_R2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5659_OUT_R_MIXER,
RT5659_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_R_MIXER,
RT5659_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_R_MIXER,
RT5659_M_BST3_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST4 Switch", RT5659_OUT_R_MIXER,
RT5659_M_BST4_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_spo_l_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPO_AMP_GAIN,
RT5659_M_DAC_L2_SPKOMIX_SFT, 1, 0),
SOC_DAPM_SINGLE("SPKVOL L Switch", RT5659_SPO_AMP_GAIN,
RT5659_M_SPKVOLL_SPKOMIX_SFT, 1, 0),
};
static const struct snd_kcontrol_new rt5659_spo_r_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPO_AMP_GAIN,
RT5659_M_DAC_R2_SPKOMIX_SFT, 1, 0),
SOC_DAPM_SINGLE("SPKVOL R Switch", RT5659_SPO_AMP_GAIN,
RT5659_M_SPKVOLR_SPKOMIX_SFT, 1, 0),
};
static const struct snd_kcontrol_new rt5659_mono_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_DAC_L2_MA_SFT, 1, 1),
SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_MONOMIX_IN_GAIN,
RT5659_M_MONOVOL_MA_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_lout_l_mix[] = {
SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_LOUT_MIXER,
RT5659_M_DAC_L2_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5659_LOUT_MIXER,
RT5659_M_OV_L_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5659_lout_r_mix[] = {
SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_LOUT_MIXER,
RT5659_M_DAC_R2_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5659_LOUT_MIXER,
RT5659_M_OV_R_LM_SFT, 1, 1),
};
/*DAC L2, DAC R2*/
/*MX-1B [6:4], MX-1B [2:0]*/
static const char * const rt5659_dac2_src[] = {
"IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_dac_l2_enum, RT5659_DAC_CTRL,
RT5659_DAC_L2_SEL_SFT, rt5659_dac2_src);
static const struct snd_kcontrol_new rt5659_dac_l2_mux =
SOC_DAPM_ENUM("DAC L2 Source", rt5659_dac_l2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_dac_r2_enum, RT5659_DAC_CTRL,
RT5659_DAC_R2_SEL_SFT, rt5659_dac2_src);
static const struct snd_kcontrol_new rt5659_dac_r2_mux =
SOC_DAPM_ENUM("DAC R2 Source", rt5659_dac_r2_enum);
/* STO1 ADC1 Source */
/* MX-26 [13] */
static const char * const rt5659_sto1_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_sto1_adc1_enum, RT5659_STO1_ADC_MIXER,
RT5659_STO1_ADC1_SRC_SFT, rt5659_sto1_adc1_src);
static const struct snd_kcontrol_new rt5659_sto1_adc1_mux =
SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5659_sto1_adc1_enum);
/* STO1 ADC Source */
/* MX-26 [12] */
static const char * const rt5659_sto1_adc_src[] = {
"ADC1", "ADC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_sto1_adc_enum, RT5659_STO1_ADC_MIXER,
RT5659_STO1_ADC_SRC_SFT, rt5659_sto1_adc_src);
static const struct snd_kcontrol_new rt5659_sto1_adc_mux =
SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
/* STO1 ADC2 Source */
/* MX-26 [11] */
static const char * const rt5659_sto1_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_sto1_adc2_enum, RT5659_STO1_ADC_MIXER,
RT5659_STO1_ADC2_SRC_SFT, rt5659_sto1_adc2_src);
static const struct snd_kcontrol_new rt5659_sto1_adc2_mux =
SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5659_sto1_adc2_enum);
/* STO1 DMIC Source */
/* MX-26 [8] */
static const char * const rt5659_sto1_dmic_src[] = {
"DMIC1", "DMIC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_sto1_dmic_enum, RT5659_STO1_ADC_MIXER,
RT5659_STO1_DMIC_SRC_SFT, rt5659_sto1_dmic_src);
static const struct snd_kcontrol_new rt5659_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5659_sto1_dmic_enum);
/* MONO ADC L2 Source */
/* MX-27 [12] */
static const char * const rt5659_mono_adc_l2_src[] = {
"Mono DAC MIXL", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_adc_l2_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_ADC_L2_SRC_SFT, rt5659_mono_adc_l2_src);
static const struct snd_kcontrol_new rt5659_mono_adc_l2_mux =
SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
/* MONO ADC L1 Source */
/* MX-27 [11] */
static const char * const rt5659_mono_adc_l1_src[] = {
"Mono DAC MIXL", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_adc_l1_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_ADC_L1_SRC_SFT, rt5659_mono_adc_l1_src);
static const struct snd_kcontrol_new rt5659_mono_adc_l1_mux =
SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
/* MONO ADC L Source, MONO ADC R Source*/
/* MX-27 [10:9], MX-27 [2:1] */
static const char * const rt5659_mono_adc_src[] = {
"ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_adc_l_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_ADC_L_SRC_SFT, rt5659_mono_adc_src);
static const struct snd_kcontrol_new rt5659_mono_adc_l_mux =
SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_adcr_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_ADC_R_SRC_SFT, rt5659_mono_adc_src);
static const struct snd_kcontrol_new rt5659_mono_adc_r_mux =
SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
/* MONO DMIC L Source */
/* MX-27 [8] */
static const char * const rt5659_mono_dmic_l_src[] = {
"DMIC1 L", "DMIC2 L"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_dmic_l_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_DMIC_L_SRC_SFT, rt5659_mono_dmic_l_src);
static const struct snd_kcontrol_new rt5659_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC L Source", rt5659_mono_dmic_l_enum);
/* MONO ADC R2 Source */
/* MX-27 [4] */
static const char * const rt5659_mono_adc_r2_src[] = {
"Mono DAC MIXR", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_adc_r2_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_ADC_R2_SRC_SFT, rt5659_mono_adc_r2_src);
static const struct snd_kcontrol_new rt5659_mono_adc_r2_mux =
SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
/* MONO ADC R1 Source */
/* MX-27 [3] */
static const char * const rt5659_mono_adc_r1_src[] = {
"Mono DAC MIXR", "ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_adc_r1_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_ADC_R1_SRC_SFT, rt5659_mono_adc_r1_src);
static const struct snd_kcontrol_new rt5659_mono_adc_r1_mux =
SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
/* MONO DMIC R Source */
/* MX-27 [0] */
static const char * const rt5659_mono_dmic_r_src[] = {
"DMIC1 R", "DMIC2 R"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_mono_dmic_r_enum, RT5659_MONO_ADC_MIXER,
RT5659_MONO_DMIC_R_SRC_SFT, rt5659_mono_dmic_r_src);
static const struct snd_kcontrol_new rt5659_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC R Source", rt5659_mono_dmic_r_enum);
/* DAC R1 Source, DAC L1 Source*/
/* MX-29 [11:10], MX-29 [9:8]*/
static const char * const rt5659_dac1_src[] = {
"IF1 DAC1", "IF2 DAC", "IF3 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_dac_r1_enum, RT5659_AD_DA_MIXER,
RT5659_DAC1_R_SEL_SFT, rt5659_dac1_src);
static const struct snd_kcontrol_new rt5659_dac_r1_mux =
SOC_DAPM_ENUM("DAC R1 Source", rt5659_dac_r1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_dac_l1_enum, RT5659_AD_DA_MIXER,
RT5659_DAC1_L_SEL_SFT, rt5659_dac1_src);
static const struct snd_kcontrol_new rt5659_dac_l1_mux =
SOC_DAPM_ENUM("DAC L1 Source", rt5659_dac_l1_enum);
/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
/* MX-2C [6], MX-2C [4]*/
static const char * const rt5659_dig_dac_mix_src[] = {
"Stereo DAC Mixer", "Mono DAC Mixer"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_dig_dac_mixl_enum, RT5659_DIG_MIXER,
RT5659_DAC_MIX_L_SFT, rt5659_dig_dac_mix_src);
static const struct snd_kcontrol_new rt5659_dig_dac_mixl_mux =
SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5659_dig_dac_mixl_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_dig_dac_mixr_enum, RT5659_DIG_MIXER,
RT5659_DAC_MIX_R_SFT, rt5659_dig_dac_mix_src);
static const struct snd_kcontrol_new rt5659_dig_dac_mixr_mux =
SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5659_dig_dac_mixr_enum);
/* Analog DAC L1 Source, Analog DAC R1 Source*/
/* MX-2D [3], MX-2D [2]*/
static const char * const rt5659_alg_dac1_src[] = {
"DAC", "Stereo DAC Mixer"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_alg_dac_l1_enum, RT5659_A_DAC_MUX,
RT5659_A_DACL1_SFT, rt5659_alg_dac1_src);
static const struct snd_kcontrol_new rt5659_alg_dac_l1_mux =
SOC_DAPM_ENUM("Analog DACL1 Source", rt5659_alg_dac_l1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_alg_dac_r1_enum, RT5659_A_DAC_MUX,
RT5659_A_DACR1_SFT, rt5659_alg_dac1_src);
static const struct snd_kcontrol_new rt5659_alg_dac_r1_mux =
SOC_DAPM_ENUM("Analog DACR1 Source", rt5659_alg_dac_r1_enum);
/* Analog DAC LR Source, Analog DAC R2 Source*/
/* MX-2D [1], MX-2D [0]*/
static const char * const rt5659_alg_dac2_src[] = {
"Stereo DAC Mixer", "Mono DAC Mixer"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_alg_dac_l2_enum, RT5659_A_DAC_MUX,
RT5659_A_DACL2_SFT, rt5659_alg_dac2_src);
static const struct snd_kcontrol_new rt5659_alg_dac_l2_mux =
SOC_DAPM_ENUM("Analog DAC L2 Source", rt5659_alg_dac_l2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_alg_dac_r2_enum, RT5659_A_DAC_MUX,
RT5659_A_DACR2_SFT, rt5659_alg_dac2_src);
static const struct snd_kcontrol_new rt5659_alg_dac_r2_mux =
SOC_DAPM_ENUM("Analog DAC R2 Source", rt5659_alg_dac_r2_enum);
/* Interface2 ADC Data Input*/
/* MX-2F [13:12] */
static const char * const rt5659_if2_adc_in_src[] = {
"IF_ADC1", "IF_ADC2", "DAC_REF", "IF_ADC3"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_if2_adc_in_enum, RT5659_DIG_INF23_DATA,
RT5659_IF2_ADC_IN_SFT, rt5659_if2_adc_in_src);
static const struct snd_kcontrol_new rt5659_if2_adc_in_mux =
SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
/* Interface3 ADC Data Input*/
/* MX-2F [1:0] */
static const char * const rt5659_if3_adc_in_src[] = {
"IF_ADC1", "IF_ADC2", "DAC_REF", "Stereo2_ADC_L/R"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_if3_adc_in_enum, RT5659_DIG_INF23_DATA,
RT5659_IF3_ADC_IN_SFT, rt5659_if3_adc_in_src);
static const struct snd_kcontrol_new rt5659_if3_adc_in_mux =
SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
/* PDM 1 L/R*/
/* MX-31 [15] [13] */
static const char * const rt5659_pdm_src[] = {
"Mono DAC", "Stereo DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_pdm_l_enum, RT5659_PDM_OUT_CTRL,
RT5659_PDM1_L_SFT, rt5659_pdm_src);
static const struct snd_kcontrol_new rt5659_pdm_l_mux =
SOC_DAPM_ENUM("PDM L Source", rt5659_pdm_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5659_pdm_r_enum, RT5659_PDM_OUT_CTRL,
RT5659_PDM1_R_SFT, rt5659_pdm_src);
static const struct snd_kcontrol_new rt5659_pdm_r_mux =
SOC_DAPM_ENUM("PDM R Source", rt5659_pdm_r_enum);
/* SPDIF Output source*/
/* MX-36 [1:0] */
static const char * const rt5659_spdif_src[] = {
"IF1_DAC1", "IF1_DAC2", "IF2_DAC", "IF3_DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_spdif_enum, RT5659_SPDIF_CTRL,
RT5659_SPDIF_SEL_SFT, rt5659_spdif_src);
static const struct snd_kcontrol_new rt5659_spdif_mux =
SOC_DAPM_ENUM("SPDIF Source", rt5659_spdif_enum);
/* I2S1 TDM ADCDAT Source */
/* MX-78[4:0] */
static const char * const rt5659_rx_adc_data_src[] = {
"AD1:AD2:DAC:NUL", "AD1:AD2:NUL:DAC", "AD1:DAC:AD2:NUL",
"AD1:DAC:NUL:AD2", "AD1:NUL:DAC:AD2", "AD1:NUL:AD2:DAC",
"AD2:AD1:DAC:NUL", "AD2:AD1:NUL:DAC", "AD2:DAC:AD1:NUL",
"AD2:DAC:NUL:AD1", "AD2:NUL:DAC:AD1", "AD1:NUL:AD1:DAC",
"DAC:AD1:AD2:NUL", "DAC:AD1:NUL:AD2", "DAC:AD2:AD1:NUL",
"DAC:AD2:NUL:AD1", "DAC:NUL:DAC:AD2", "DAC:NUL:AD2:DAC",
"NUL:AD1:AD2:DAC", "NUL:AD1:DAC:AD2", "NUL:AD2:AD1:DAC",
"NUL:AD2:DAC:AD1", "NUL:DAC:DAC:AD2", "NUL:DAC:AD2:DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5659_rx_adc_data_enum, RT5659_TDM_CTRL_2,
RT5659_ADCDAT_SRC_SFT, rt5659_rx_adc_data_src);
static const struct snd_kcontrol_new rt5659_rx_adc_dac_mux =
SOC_DAPM_ENUM("TDM ADCDAT Source", rt5659_rx_adc_data_enum);
/* Out Volume Switch */
static const struct snd_kcontrol_new spkvol_l_switch =
SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new spkvol_r_switch =
SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_R_SFT, 1, 1);
static const struct snd_kcontrol_new monovol_switch =
SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new outvol_l_switch =
SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_L_SFT, 1, 1);
static const struct snd_kcontrol_new outvol_r_switch =
SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_R_SFT, 1, 1);
/* Out Switch */
static const struct snd_kcontrol_new spo_switch =
SOC_DAPM_SINGLE("Switch", RT5659_CLASSD_2, RT5659_M_RF_DIG_SFT, 1, 1);
static const struct snd_kcontrol_new mono_switch =
SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpo_l_switch =
SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new hpo_r_switch =
SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new lout_l_switch =
SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new lout_r_switch =
SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_R_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new pdm_l_switch =
SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_L_SFT, 1,
1);
static const struct snd_kcontrol_new pdm_r_switch =
SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_R_SFT, 1,
1);
static int rt5659_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1,
RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_EN);
snd_soc_component_update_bits(component, RT5659_CLASSD_2,
RT5659_M_RI_DIG, RT5659_M_RI_DIG);
snd_soc_component_write(component, RT5659_CLASSD_1, 0x0803);
snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, RT5659_CLASSD_1, 0x0011);
snd_soc_component_update_bits(component, RT5659_CLASSD_2,
RT5659_M_RI_DIG, 0x0);
snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1,
RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_DIS);
break;
default:
return 0;
}
return 0;
}
static int rt5659_mono_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
break;
default:
return 0;
}
return 0;
}
static int rt5659_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0e1e);
snd_soc_component_update_bits(component, RT5659_DEPOP_1, 0x0010, 0x0010);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_write(component, RT5659_DEPOP_1, 0x0000);
break;
default:
return 0;
}
return 0;
}
static int set_dmic_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/*Add delay to avoid pop noise*/
msleep(450);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5659_particular_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5659_PWR_ANLG_3, RT5659_PWR_LDO2_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5659_PWR_ANLG_2, RT5659_PWR_MB1_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5659_PWR_VOL,
RT5659_PWR_MIC_DET_BIT, 0, NULL, 0),
};
static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL", RT5659_PWR_ANLG_3, RT5659_PWR_PLL_BIT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Mono Vref", RT5659_PWR_ANLG_1,
RT5659_PWR_VREF3_BIT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5659_ASRC_1,
RT5659_I2S1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5659_ASRC_1,
RT5659_I2S2_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5659_ASRC_1,
RT5659_I2S3_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5659_ASRC_1,
RT5659_DAC_STO_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5659_ASRC_1,
RT5659_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5659_ASRC_1,
RT5659_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
RT5659_ADC_STO1_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
RT5659_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
RT5659_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
/* Input Side */
SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5659_PWR_ANLG_2, RT5659_PWR_MB2_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5659_PWR_ANLG_2, RT5659_PWR_MB3_BIT,
0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("IN3P"),
SND_SOC_DAPM_INPUT("IN3N"),
SND_SOC_DAPM_INPUT("IN4P"),
SND_SOC_DAPM_INPUT("IN4N"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5659_DMIC_CTRL_1,
RT5659_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5659_DMIC_CTRL_1,
RT5659_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
/* Boost */
SND_SOC_DAPM_PGA("BST1", RT5659_PWR_ANLG_2,
RT5659_PWR_BST1_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", RT5659_PWR_ANLG_2,
RT5659_PWR_BST2_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST3", RT5659_PWR_ANLG_2,
RT5659_PWR_BST3_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST4", RT5659_PWR_ANLG_2,
RT5659_PWR_BST4_P_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST1 Power", RT5659_PWR_ANLG_2,
RT5659_PWR_BST1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2 Power", RT5659_PWR_ANLG_2,
RT5659_PWR_BST2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST3 Power", RT5659_PWR_ANLG_2,
RT5659_PWR_BST3_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST4 Power", RT5659_PWR_ANLG_2,
RT5659_PWR_BST4_BIT, 0, NULL, 0),
/* Input Volume */
SND_SOC_DAPM_PGA("INL VOL", RT5659_PWR_VOL, RT5659_PWR_IN_L_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA("INR VOL", RT5659_PWR_VOL, RT5659_PWR_IN_R_BIT,
0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", RT5659_PWR_MIXER, RT5659_PWR_RM1_L_BIT,
0, rt5659_rec1_l_mix, ARRAY_SIZE(rt5659_rec1_l_mix)),
SND_SOC_DAPM_MIXER("RECMIX1R", RT5659_PWR_MIXER, RT5659_PWR_RM1_R_BIT,
0, rt5659_rec1_r_mix, ARRAY_SIZE(rt5659_rec1_r_mix)),
SND_SOC_DAPM_MIXER("RECMIX2L", RT5659_PWR_MIXER, RT5659_PWR_RM2_L_BIT,
0, rt5659_rec2_l_mix, ARRAY_SIZE(rt5659_rec2_l_mix)),
SND_SOC_DAPM_MIXER("RECMIX2R", RT5659_PWR_MIXER, RT5659_PWR_RM2_R_BIT,
0, rt5659_rec2_r_mix, ARRAY_SIZE(rt5659_rec2_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5659_PWR_DIG_1,
RT5659_PWR_ADC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1,
RT5659_PWR_ADC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_1,
RT5659_PWR_ADC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_1,
RT5659_PWR_ADC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc1_clk,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc2_clk,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_adc1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_adc1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_adc2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_adc2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_adc_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5659_sto1_adc_mux),
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_adc_l2_mux),
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_adc_r2_mux),
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_adc_l1_mux),
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_adc_r1_mux),
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_dmic_l_mux),
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_dmic_r_mux),
SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_adc_l_mux),
SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5659_mono_adc_r_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
RT5659_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
RT5659_PWR_ADC_S2F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
0, 0, rt5659_sto1_adc_l_mix,
ARRAY_SIZE(rt5659_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
0, 0, rt5659_sto1_adc_r_mix,
ARRAY_SIZE(rt5659_sto1_adc_r_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
RT5659_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
RT5659_L_MUTE_SFT, 1, rt5659_mono_adc_l_mix,
ARRAY_SIZE(rt5659_mono_adc_l_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
RT5659_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
RT5659_R_MUTE_SFT, 1, rt5659_mono_adc_r_mix,
ARRAY_SIZE(rt5659_mono_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
RT5659_L_MUTE_SFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
RT5659_R_MUTE_SFT, 1, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5659_PWR_DIG_1, RT5659_PWR_I2S1_BIT,
0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5659_PWR_DIG_1, RT5659_PWR_I2S2_BIT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S3", RT5659_PWR_DIG_1, RT5659_PWR_I2S3_BIT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_PGA("TDM AD1:AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TDM AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
&rt5659_rx_adc_dac_mux),
SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if2_adc_in_mux),
SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if3_adc_in_mux),
SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if1_01_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if1_23_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if1_45_adc_swap_mux),
SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if1_67_adc_swap_mux),
SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if2_dac_swap_mux),
SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if2_adc_swap_mux),
SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if3_dac_swap_mux),
SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
&rt5659_if3_adc_swap_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5659_dac_l_mix, ARRAY_SIZE(rt5659_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5659_dac_r_mix, ARRAY_SIZE(rt5659_dac_r_mix)),
/* DAC channel Mux */
SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux),
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux),
SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
&rt5659_alg_dac_l1_mux),
SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
&rt5659_alg_dac_r1_mux),
SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
&rt5659_alg_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
&rt5659_alg_dac_r2_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5659_PWR_DIG_2,
RT5659_PWR_DAC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5659_PWR_DIG_2,
RT5659_PWR_DAC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5659_PWR_DIG_2,
RT5659_PWR_DAC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5659_sto_dac_l_mix, ARRAY_SIZE(rt5659_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5659_sto_dac_r_mix, ARRAY_SIZE(rt5659_sto_dac_r_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5659_mono_dac_l_mix, ARRAY_SIZE(rt5659_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5659_mono_dac_r_mix, ARRAY_SIZE(rt5659_mono_dac_r_mix)),
SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
&rt5659_dig_dac_mixl_mux),
SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
&rt5659_dig_dac_mixr_mux),
/* DACs */
SND_SOC_DAPM_SUPPLY_S("DAC L1 Power", 1, RT5659_PWR_DIG_1,
RT5659_PWR_DAC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC R1 Power", 1, RT5659_PWR_DIG_1,
RT5659_PWR_DAC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5659_PWR_DIG_1,
RT5659_PWR_DAC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5659_PWR_DIG_1,
RT5659_PWR_DAC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("DAC_REF", SND_SOC_NOPM, 0, 0, NULL, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("SPK MIXL", RT5659_PWR_MIXER, RT5659_PWR_SM_L_BIT,
0, rt5659_spk_l_mix, ARRAY_SIZE(rt5659_spk_l_mix)),
SND_SOC_DAPM_MIXER("SPK MIXR", RT5659_PWR_MIXER, RT5659_PWR_SM_R_BIT,
0, rt5659_spk_r_mix, ARRAY_SIZE(rt5659_spk_r_mix)),
SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5659_PWR_MIXER, RT5659_PWR_MM_BIT,
0, rt5659_monovol_mix, ARRAY_SIZE(rt5659_monovol_mix)),
SND_SOC_DAPM_MIXER("OUT MIXL", RT5659_PWR_MIXER, RT5659_PWR_OM_L_BIT,
0, rt5659_out_l_mix, ARRAY_SIZE(rt5659_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5659_PWR_MIXER, RT5659_PWR_OM_R_BIT,
0, rt5659_out_r_mix, ARRAY_SIZE(rt5659_out_r_mix)),
/* Output Volume */
SND_SOC_DAPM_SWITCH("SPKVOL L", RT5659_PWR_VOL, RT5659_PWR_SV_L_BIT, 0,
&spkvol_l_switch),
SND_SOC_DAPM_SWITCH("SPKVOL R", RT5659_PWR_VOL, RT5659_PWR_SV_R_BIT, 0,
&spkvol_r_switch),
SND_SOC_DAPM_SWITCH("MONOVOL", RT5659_PWR_VOL, RT5659_PWR_MV_BIT, 0,
&monovol_switch),
SND_SOC_DAPM_SWITCH("OUTVOL L", RT5659_PWR_VOL, RT5659_PWR_OV_L_BIT, 0,
&outvol_l_switch),
SND_SOC_DAPM_SWITCH("OUTVOL R", RT5659_PWR_VOL, RT5659_PWR_OV_R_BIT, 0,
&outvol_r_switch),
/* SPO/MONO/HPO/LOUT */
SND_SOC_DAPM_MIXER("SPO L MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_l_mix,
ARRAY_SIZE(rt5659_spo_l_mix)),
SND_SOC_DAPM_MIXER("SPO R MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_r_mix,
ARRAY_SIZE(rt5659_spo_r_mix)),
SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5659_mono_mix,
ARRAY_SIZE(rt5659_mono_mix)),
SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_l_mix,
ARRAY_SIZE(rt5659_lout_l_mix)),
SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_r_mix,
ARRAY_SIZE(rt5659_lout_r_mix)),
SND_SOC_DAPM_PGA_S("SPK Amp", 1, RT5659_PWR_DIG_1, RT5659_PWR_CLS_D_BIT,
0, rt5659_spk_event, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_MA_BIT,
0, rt5659_mono_event, SND_SOC_DAPM_POST_PMD |
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5659_hp_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_LM_BIT,
0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
rt5659_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SWITCH("SPO Playback", SND_SOC_NOPM, 0, 0, &spo_switch),
SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
&mono_switch),
SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
&hpo_l_switch),
SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
&hpo_r_switch),
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
&lout_l_switch),
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
&lout_r_switch),
SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
&pdm_l_switch),
SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
&pdm_r_switch),
/* PDM */
SND_SOC_DAPM_SUPPLY("PDM Power", RT5659_PWR_DIG_2,
RT5659_PWR_PDM1_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL,
RT5659_M_PDM1_L_SFT, 1, &rt5659_pdm_l_mux),
SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL,
RT5659_M_PDM1_R_SFT, 1, &rt5659_pdm_r_mux),
/* SPDIF */
SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux),
SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLKDET", RT5659_CLK_DET, 0, 0, NULL, 0),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("PDML"),
SND_SOC_DAPM_OUTPUT("PDMR"),
SND_SOC_DAPM_OUTPUT("SPDIF"),
};
static const struct snd_soc_dapm_route rt5659_dapm_routes[] = {
/*PLL*/
{ "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
{ "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
{ "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
{ "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
{ "DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
{ "DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
{ "DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
/*ASRC*/
{ "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
{ "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
{ "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
{ "DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc },
{ "DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc },
{ "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
{ "SYS CLK DET", NULL, "CLKDET" },
{ "I2S1", NULL, "I2S1 ASRC" },
{ "I2S2", NULL, "I2S2 ASRC" },
{ "I2S3", NULL, "I2S3 ASRC" },
{ "DMIC1", NULL, "DMIC L1" },
{ "DMIC1", NULL, "DMIC R1" },
{ "DMIC2", NULL, "DMIC L2" },
{ "DMIC2", NULL, "DMIC R2" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST1", NULL, "BST1 Power" },
{ "BST2", NULL, "IN2P" },
{ "BST2", NULL, "IN2N" },
{ "BST2", NULL, "BST2 Power" },
{ "BST3", NULL, "IN3P" },
{ "BST3", NULL, "IN3N" },
{ "BST3", NULL, "BST3 Power" },
{ "BST4", NULL, "IN4P" },
{ "BST4", NULL, "IN4N" },
{ "BST4", NULL, "BST4 Power" },
{ "INL VOL", NULL, "IN2P" },
{ "INR VOL", NULL, "IN2N" },
{ "RECMIX1L", "SPKVOLL Switch", "SPKVOL L" },
{ "RECMIX1L", "INL Switch", "INL VOL" },
{ "RECMIX1L", "BST4 Switch", "BST4" },
{ "RECMIX1L", "BST3 Switch", "BST3" },
{ "RECMIX1L", "BST2 Switch", "BST2" },
{ "RECMIX1L", "BST1 Switch", "BST1" },
{ "RECMIX1R", "HPOVOLR Switch", "HPO R Playback" },
{ "RECMIX1R", "INR Switch", "INR VOL" },
{ "RECMIX1R", "BST4 Switch", "BST4" },
{ "RECMIX1R", "BST3 Switch", "BST3" },
{ "RECMIX1R", "BST2 Switch", "BST2" },
{ "RECMIX1R", "BST1 Switch", "BST1" },
{ "RECMIX2L", "SPKVOLL Switch", "SPKVOL L" },
{ "RECMIX2L", "OUTVOLL Switch", "OUTVOL L" },
{ "RECMIX2L", "BST4 Switch", "BST4" },
{ "RECMIX2L", "BST3 Switch", "BST3" },
{ "RECMIX2L", "BST2 Switch", "BST2" },
{ "RECMIX2L", "BST1 Switch", "BST1" },
{ "RECMIX2R", "MONOVOL Switch", "MONOVOL" },
{ "RECMIX2R", "OUTVOLR Switch", "OUTVOL R" },
{ "RECMIX2R", "BST4 Switch", "BST4" },
{ "RECMIX2R", "BST3 Switch", "BST3" },
{ "RECMIX2R", "BST2 Switch", "BST2" },
{ "RECMIX2R", "BST1 Switch", "BST1" },
{ "ADC1 L", NULL, "RECMIX1L" },
{ "ADC1 L", NULL, "ADC1 L Power" },
{ "ADC1 L", NULL, "ADC1 clock" },
{ "ADC1 R", NULL, "RECMIX1R" },
{ "ADC1 R", NULL, "ADC1 R Power" },
{ "ADC1 R", NULL, "ADC1 clock" },
{ "ADC2 L", NULL, "RECMIX2L" },
{ "ADC2 L", NULL, "ADC2 L Power" },
{ "ADC2 L", NULL, "ADC2 clock" },
{ "ADC2 R", NULL, "RECMIX2R" },
{ "ADC2 R", NULL, "ADC2 R Power" },
{ "ADC2 R", NULL, "ADC2 clock" },
{ "DMIC L1", NULL, "DMIC CLK" },
{ "DMIC L1", NULL, "DMIC1 Power" },
{ "DMIC R1", NULL, "DMIC CLK" },
{ "DMIC R1", NULL, "DMIC1 Power" },
{ "DMIC L2", NULL, "DMIC CLK" },
{ "DMIC L2", NULL, "DMIC2 Power" },
{ "DMIC R2", NULL, "DMIC CLK" },
{ "DMIC R2", NULL, "DMIC2 Power" },
{ "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" },
{ "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" },
{ "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" },
{ "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" },
{ "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" },
{ "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" },
{ "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" },
{ "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" },
{ "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
{ "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
{ "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
{ "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
{ "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
{ "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
{ "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
{ "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
{ "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
{ "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
{ "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
{ "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
{ "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
{ "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
{ "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
{ "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
{ "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
{ "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
{ "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
{ "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
{ "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
{ "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
{ "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
{ "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
{ "IF_ADC2", NULL, "Mono ADC MIXL" },
{ "IF_ADC2", NULL, "Mono ADC MIXR" },
{ "TDM AD1:AD2:DAC", NULL, "IF_ADC1" },
{ "TDM AD1:AD2:DAC", NULL, "IF_ADC2" },
{ "TDM AD1:AD2:DAC", NULL, "DAC_REF" },
{ "TDM AD2:DAC", NULL, "IF_ADC2" },
{ "TDM AD2:DAC", NULL, "DAC_REF" },
{ "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" },
{ "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" },
{ "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" },
{ "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" },
{ "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" },
{ "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
{ "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
{ "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
{ "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
{ "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
{ "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
{ "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
{ "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
{ "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
{ "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
{ "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
{ "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
{ "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
{ "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
{ "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
{ "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
{ "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
{ "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
{ "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
{ "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
{ "IF1 ADC", NULL, "I2S1" },
{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
{ "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
{ "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
{ "IF2 ADC", NULL, "IF2 ADC Mux"},
{ "IF2 ADC", NULL, "I2S2" },
{ "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
{ "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
{ "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
{ "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
{ "IF3 ADC", NULL, "IF3 ADC Mux"},
{ "IF3 ADC", NULL, "I2S3" },
{ "AIF1TX", NULL, "IF1 ADC" },
{ "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
{ "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
{ "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
{ "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
{ "AIF2TX", NULL, "IF2 ADC Swap Mux" },
{ "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
{ "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
{ "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
{ "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
{ "AIF3TX", NULL, "IF3 ADC Swap Mux" },
{ "IF1 DAC1", NULL, "AIF1RX" },
{ "IF1 DAC2", NULL, "AIF1RX" },
{ "IF2 DAC Swap Mux", "L/R", "AIF2RX" },
{ "IF2 DAC Swap Mux", "R/L", "AIF2RX" },
{ "IF2 DAC Swap Mux", "L/L", "AIF2RX" },
{ "IF2 DAC Swap Mux", "R/R", "AIF2RX" },
{ "IF2 DAC", NULL, "IF2 DAC Swap Mux" },
{ "IF3 DAC Swap Mux", "L/R", "AIF3RX" },
{ "IF3 DAC Swap Mux", "R/L", "AIF3RX" },
{ "IF3 DAC Swap Mux", "L/L", "AIF3RX" },
{ "IF3 DAC Swap Mux", "R/R", "AIF3RX" },
{ "IF3 DAC", NULL, "IF3 DAC Swap Mux" },
{ "IF1 DAC1", NULL, "I2S1" },
{ "IF1 DAC2", NULL, "I2S1" },
{ "IF2 DAC", NULL, "I2S2" },
{ "IF3 DAC", NULL, "I2S3" },
{ "IF1 DAC2 L", NULL, "IF1 DAC2" },
{ "IF1 DAC2 R", NULL, "IF1 DAC2" },
{ "IF1 DAC1 L", NULL, "IF1 DAC1" },
{ "IF1 DAC1 R", NULL, "IF1 DAC1" },
{ "IF2 DAC L", NULL, "IF2 DAC" },
{ "IF2 DAC R", NULL, "IF2 DAC" },
{ "IF3 DAC L", NULL, "IF3 DAC" },
{ "IF3 DAC R", NULL, "IF3 DAC" },
{ "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" },
{ "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" },
{ "DAC L1 Mux", NULL, "DAC Stereo1 Filter" },
{ "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" },
{ "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" },
{ "DAC R1 Mux", NULL, "DAC Stereo1 Filter" },
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
{ "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" },
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
{ "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" },
{ "DAC_REF", NULL, "DAC1 MIXL" },
{ "DAC_REF", NULL, "DAC1 MIXR" },
{ "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" },
{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
{ "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
{ "DAC L2 Mux", NULL, "DAC Mono Left Filter" },
{ "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" },
{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
{ "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
{ "DAC R2 Mux", NULL, "DAC Mono Right Filter" },
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
{ "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
{ "Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
{ "DAC MIXL", "Stereo DAC Mixer", "Stereo DAC MIXL" },
{ "DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL" },
{ "DAC MIXR", "Stereo DAC Mixer", "Stereo DAC MIXR" },
{ "DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR" },
{ "DAC L1 Source", NULL, "DAC L1 Power" },
{ "DAC L1 Source", "DAC", "DAC1 MIXL" },
{ "DAC L1 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
{ "DAC R1 Source", NULL, "DAC R1 Power" },
{ "DAC R1 Source", "DAC", "DAC1 MIXR" },
{ "DAC R1 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
{ "DAC L2 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
{ "DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL" },
{ "DAC L2 Source", NULL, "DAC L2 Power" },
{ "DAC R2 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
{ "DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR" },
{ "DAC R2 Source", NULL, "DAC R2 Power" },
{ "DAC L1", NULL, "DAC L1 Source" },
{ "DAC R1", NULL, "DAC R1 Source" },
{ "DAC L2", NULL, "DAC L2 Source" },
{ "DAC R2", NULL, "DAC R2 Source" },
{ "SPK MIXL", "DAC L2 Switch", "DAC L2" },
{ "SPK MIXL", "BST1 Switch", "BST1" },
{ "SPK MIXL", "INL Switch", "INL VOL" },
{ "SPK MIXL", "INR Switch", "INR VOL" },
{ "SPK MIXL", "BST3 Switch", "BST3" },
{ "SPK MIXR", "DAC R2 Switch", "DAC R2" },
{ "SPK MIXR", "BST4 Switch", "BST4" },
{ "SPK MIXR", "INL Switch", "INL VOL" },
{ "SPK MIXR", "INR Switch", "INR VOL" },
{ "SPK MIXR", "BST3 Switch", "BST3" },
{ "MONOVOL MIX", "DAC L2 Switch", "DAC L2" },
{ "MONOVOL MIX", "DAC R2 Switch", "DAC R2" },
{ "MONOVOL MIX", "BST1 Switch", "BST1" },
{ "MONOVOL MIX", "BST2 Switch", "BST2" },
{ "MONOVOL MIX", "BST3 Switch", "BST3" },
{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
{ "OUT MIXL", "INL Switch", "INL VOL" },
{ "OUT MIXL", "BST1 Switch", "BST1" },
{ "OUT MIXL", "BST2 Switch", "BST2" },
{ "OUT MIXL", "BST3 Switch", "BST3" },
{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
{ "OUT MIXR", "INR Switch", "INR VOL" },
{ "OUT MIXR", "BST2 Switch", "BST2" },
{ "OUT MIXR", "BST3 Switch", "BST3" },
{ "OUT MIXR", "BST4 Switch", "BST4" },
{ "SPKVOL L", "Switch", "SPK MIXL" },
{ "SPKVOL R", "Switch", "SPK MIXR" },
{ "SPO L MIX", "DAC L2 Switch", "DAC L2" },
{ "SPO L MIX", "SPKVOL L Switch", "SPKVOL L" },
{ "SPO R MIX", "DAC R2 Switch", "DAC R2" },
{ "SPO R MIX", "SPKVOL R Switch", "SPKVOL R" },
{ "SPK Amp", NULL, "SPO L MIX" },
{ "SPK Amp", NULL, "SPO R MIX" },
{ "SPK Amp", NULL, "SYS CLK DET" },
{ "SPO Playback", "Switch", "SPK Amp" },
{ "SPOL", NULL, "SPO Playback" },
{ "SPOR", NULL, "SPO Playback" },
{ "MONOVOL", "Switch", "MONOVOL MIX" },
{ "Mono MIX", "DAC L2 Switch", "DAC L2" },
{ "Mono MIX", "MONOVOL Switch", "MONOVOL" },
{ "Mono Amp", NULL, "Mono MIX" },
{ "Mono Amp", NULL, "Mono Vref" },
{ "Mono Amp", NULL, "SYS CLK DET" },
{ "Mono Playback", "Switch", "Mono Amp" },
{ "MONOOUT", NULL, "Mono Playback" },
{ "HP Amp", NULL, "DAC L1" },
{ "HP Amp", NULL, "DAC R1" },
{ "HP Amp", NULL, "Charge Pump" },
{ "HP Amp", NULL, "SYS CLK DET" },
{ "HPO L Playback", "Switch", "HP Amp"},
{ "HPO R Playback", "Switch", "HP Amp"},
{ "HPOL", NULL, "HPO L Playback" },
{ "HPOR", NULL, "HPO R Playback" },
{ "OUTVOL L", "Switch", "OUT MIXL" },
{ "OUTVOL R", "Switch", "OUT MIXR" },
{ "LOUT L MIX", "DAC L2 Switch", "DAC L2" },
{ "LOUT L MIX", "OUTVOL L Switch", "OUTVOL L" },
{ "LOUT R MIX", "DAC R2 Switch", "DAC R2" },
{ "LOUT R MIX", "OUTVOL R Switch", "OUTVOL R" },
{ "LOUT Amp", NULL, "LOUT L MIX" },
{ "LOUT Amp", NULL, "LOUT R MIX" },
{ "LOUT Amp", NULL, "Charge Pump" },
{ "LOUT Amp", NULL, "SYS CLK DET" },
{ "LOUT L Playback", "Switch", "LOUT Amp" },
{ "LOUT R Playback", "Switch", "LOUT Amp" },
{ "LOUTL", NULL, "LOUT L Playback" },
{ "LOUTR", NULL, "LOUT R Playback" },
{ "PDM L Mux", "Mono DAC", "Mono DAC MIXL" },
{ "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" },
{ "PDM L Mux", NULL, "PDM Power" },
{ "PDM R Mux", "Mono DAC", "Mono DAC MIXR" },
{ "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" },
{ "PDM R Mux", NULL, "PDM Power" },
{ "PDM L Playback", "Switch", "PDM L Mux" },
{ "PDM R Playback", "Switch", "PDM R Mux" },
{ "PDML", NULL, "PDM L Playback" },
{ "PDMR", NULL, "PDM R Playback" },
{ "SPDIF Mux", "IF3_DAC", "IF3 DAC" },
{ "SPDIF Mux", "IF2_DAC", "IF2 DAC" },
{ "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" },
{ "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" },
{ "SPDIF", NULL, "SPDIF Mux" },
};
static int rt5659_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, frame_size;
rt5659->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]);
if (pre_div < 0) {
dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
rt5659->lrck[dai->id], dai->id);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
rt5659->lrck[dai->id], pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5659_I2S_DL_20;
break;
case 24:
val_len |= RT5659_I2S_DL_24;
break;
case 8:
val_len |= RT5659_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5659_AIF1:
mask_clk = RT5659_I2S_PD1_MASK;
val_clk = pre_div << RT5659_I2S_PD1_SFT;
snd_soc_component_update_bits(component, RT5659_I2S1_SDP,
RT5659_I2S_DL_MASK, val_len);
break;
case RT5659_AIF2:
mask_clk = RT5659_I2S_PD2_MASK;
val_clk = pre_div << RT5659_I2S_PD2_SFT;
snd_soc_component_update_bits(component, RT5659_I2S2_SDP,
RT5659_I2S_DL_MASK, val_len);
break;
case RT5659_AIF3:
mask_clk = RT5659_I2S_PD3_MASK;
val_clk = pre_div << RT5659_I2S_PD3_SFT;
snd_soc_component_update_bits(component, RT5659_I2S3_SDP,
RT5659_I2S_DL_MASK, val_len);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, mask_clk, val_clk);
switch (rt5659->lrck[dai->id]) {
case 192000:
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_32);
break;
case 96000:
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_64);
break;
default:
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_128);
break;
}
return 0;
}
static int rt5659_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5659->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5659_I2S_MS_S;
rt5659->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5659_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5659_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5659_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5659_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5659_AIF1:
snd_soc_component_update_bits(component, RT5659_I2S1_SDP,
RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
RT5659_I2S_DF_MASK, reg_val);
break;
case RT5659_AIF2:
snd_soc_component_update_bits(component, RT5659_I2S2_SDP,
RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
RT5659_I2S_DF_MASK, reg_val);
break;
case RT5659_AIF3:
snd_soc_component_update_bits(component, RT5659_I2S3_SDP,
RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
RT5659_I2S_DF_MASK, reg_val);
break;
default:
dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5659_set_component_sysclk(struct snd_soc_component *component, int clk_id,
int source, unsigned int freq, int dir)
{
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
unsigned int reg_val = 0;
int ret;
if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src)
return 0;
switch (clk_id) {
case RT5659_SCLK_S_MCLK:
ret = clk_set_rate(rt5659->mclk, freq);
if (ret)
return ret;
reg_val |= RT5659_SCLK_SRC_MCLK;
break;
case RT5659_SCLK_S_PLL1:
reg_val |= RT5659_SCLK_SRC_PLL1;
break;
case RT5659_SCLK_S_RCCLK:
reg_val |= RT5659_SCLK_SRC_RCCLK;
break;
default:
dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5659_GLB_CLK,
RT5659_SCLK_SRC_MASK, reg_val);
rt5659->sysclk = freq;
rt5659->sysclk_src = clk_id;
dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
freq, clk_id);
return 0;
}
static int rt5659_set_component_pll(struct snd_soc_component *component, int pll_id,
int source, unsigned int freq_in,
unsigned int freq_out)
{
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5659->pll_src && freq_in == rt5659->pll_in &&
freq_out == rt5659->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(component->dev, "PLL disabled\n");
rt5659->pll_in = 0;
rt5659->pll_out = 0;
snd_soc_component_update_bits(component, RT5659_GLB_CLK,
RT5659_SCLK_SRC_MASK, RT5659_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5659_PLL1_S_MCLK:
snd_soc_component_update_bits(component, RT5659_GLB_CLK,
RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_MCLK);
break;
case RT5659_PLL1_S_BCLK1:
snd_soc_component_update_bits(component, RT5659_GLB_CLK,
RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK1);
break;
case RT5659_PLL1_S_BCLK2:
snd_soc_component_update_bits(component, RT5659_GLB_CLK,
RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK2);
break;
case RT5659_PLL1_S_BCLK3:
snd_soc_component_update_bits(component, RT5659_GLB_CLK,
RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK3);
break;
default:
dev_err(component->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
return ret;
}
dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_component_write(component, RT5659_PLL_CTRL_1,
pll_code.n_code << RT5659_PLL_N_SFT | pll_code.k_code);
snd_soc_component_write(component, RT5659_PLL_CTRL_2,
((pll_code.m_bp ? 0 : pll_code.m_code) << RT5659_PLL_M_SFT) |
(pll_code.m_bp << RT5659_PLL_M_BP_SFT));
rt5659->pll_in = freq_in;
rt5659->pll_out = freq_out;
rt5659->pll_src = source;
return 0;
}
static int rt5659_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
unsigned int val = 0;
if (rx_mask || tx_mask)
val |= (1 << 15);
switch (slots) {
case 4:
val |= (1 << 10);
val |= (1 << 8);
break;
case 6:
val |= (2 << 10);
val |= (2 << 8);
break;
case 8:
val |= (3 << 10);
val |= (3 << 8);
break;
case 2:
break;
default:
return -EINVAL;
}
switch (slot_width) {
case 20:
val |= (1 << 6);
val |= (1 << 4);
break;
case 24:
val |= (2 << 6);
val |= (2 << 4);
break;
case 32:
val |= (3 << 6);
val |= (3 << 4);
break;
case 16:
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, RT5659_TDM_CTRL_1, 0x8ff0, val);
return 0;
}
static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
{
struct snd_soc_component *component = dai->component;
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
rt5659->bclk[dai->id] = ratio;
if (ratio == 64) {
switch (dai->id) {
case RT5659_AIF2:
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
RT5659_I2S_BCLK_MS2_MASK,
RT5659_I2S_BCLK_MS2_64);
break;
case RT5659_AIF3:
snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
RT5659_I2S_BCLK_MS3_MASK,
RT5659_I2S_BCLK_MS3_64);
break;
}
}
return 0;
}
static int rt5659_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_PREPARE:
regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
RT5659_DIG_GATE_CTRL, RT5659_DIG_GATE_CTRL);
regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
RT5659_PWR_LDO, RT5659_PWR_LDO);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2,
RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2);
msleep(20);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
RT5659_PWR_FV1 | RT5659_PWR_FV2,
RT5659_PWR_FV1 | RT5659_PWR_FV2);
break;
case SND_SOC_BIAS_STANDBY:
if (dapm->bias_level == SND_SOC_BIAS_OFF) {
ret = clk_prepare_enable(rt5659->mclk);
if (ret) {
dev_err(component->dev,
"failed to enable MCLK: %d\n", ret);
return ret;
}
}
break;
case SND_SOC_BIAS_OFF:
regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
RT5659_PWR_LDO, 0);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2
| RT5659_PWR_FV1 | RT5659_PWR_FV2,
RT5659_PWR_MB | RT5659_PWR_VREF2);
regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
RT5659_DIG_GATE_CTRL, 0);
clk_disable_unprepare(rt5659->mclk);
break;
default:
break;
}
return 0;
}
static int rt5659_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm =
snd_soc_component_get_dapm(component);
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
rt5659->component = component;
switch (rt5659->pdata.jd_src) {
case RT5659_JD_HDA_HEADER:
break;
default:
snd_soc_dapm_new_controls(dapm,
rt5659_particular_dapm_widgets,
ARRAY_SIZE(rt5659_particular_dapm_widgets));
break;
}
return 0;
}
static void rt5659_remove(struct snd_soc_component *component)
{
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
regmap_write(rt5659->regmap, RT5659_RESET, 0);
}
#ifdef CONFIG_PM
static int rt5659_suspend(struct snd_soc_component *component)
{
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5659->regmap, true);
regcache_mark_dirty(rt5659->regmap);
return 0;
}
static int rt5659_resume(struct snd_soc_component *component)
{
struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
regcache_cache_only(rt5659->regmap, false);
regcache_sync(rt5659->regmap);
return 0;
}
#else
#define rt5659_suspend NULL
#define rt5659_resume NULL
#endif
#define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000
#define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static const struct snd_soc_dai_ops rt5659_aif_dai_ops = {
.hw_params = rt5659_hw_params,
.set_fmt = rt5659_set_dai_fmt,
.set_tdm_slot = rt5659_set_tdm_slot,
.set_bclk_ratio = rt5659_set_bclk_ratio,
};
static struct snd_soc_dai_driver rt5659_dai[] = {
{
.name = "rt5659-aif1",
.id = RT5659_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5659_STEREO_RATES,
.formats = RT5659_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5659_STEREO_RATES,
.formats = RT5659_FORMATS,
},
.ops = &rt5659_aif_dai_ops,
},
{
.name = "rt5659-aif2",
.id = RT5659_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5659_STEREO_RATES,
.formats = RT5659_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5659_STEREO_RATES,
.formats = RT5659_FORMATS,
},
.ops = &rt5659_aif_dai_ops,
},
{
.name = "rt5659-aif3",
.id = RT5659_AIF3,
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5659_STEREO_RATES,
.formats = RT5659_FORMATS,
},
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5659_STEREO_RATES,
.formats = RT5659_FORMATS,
},
.ops = &rt5659_aif_dai_ops,
},
};
static const struct snd_soc_component_driver soc_component_dev_rt5659 = {
.probe = rt5659_probe,
.remove = rt5659_remove,
.suspend = rt5659_suspend,
.resume = rt5659_resume,
.set_bias_level = rt5659_set_bias_level,
.controls = rt5659_snd_controls,
.num_controls = ARRAY_SIZE(rt5659_snd_controls),
.dapm_widgets = rt5659_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5659_dapm_widgets),
.dapm_routes = rt5659_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5659_dapm_routes),
.set_sysclk = rt5659_set_component_sysclk,
.set_pll = rt5659_set_component_pll,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config rt5659_regmap = {
.reg_bits = 16,
.val_bits = 16,
.max_register = 0x0400,
.volatile_reg = rt5659_volatile_register,
.readable_reg = rt5659_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt5659_reg,
.num_reg_defaults = ARRAY_SIZE(rt5659_reg),
};
static const struct i2c_device_id rt5659_i2c_id[] = {
{ "rt5658", 0 },
{ "rt5659", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5659_i2c_id);
static int rt5659_parse_dt(struct rt5659_priv *rt5659, struct device *dev)
{
rt5659->pdata.in1_diff = device_property_read_bool(dev,
"realtek,in1-differential");
rt5659->pdata.in3_diff = device_property_read_bool(dev,
"realtek,in3-differential");
rt5659->pdata.in4_diff = device_property_read_bool(dev,
"realtek,in4-differential");
device_property_read_u32(dev, "realtek,dmic1-data-pin",
&rt5659->pdata.dmic1_data_pin);
device_property_read_u32(dev, "realtek,dmic2-data-pin",
&rt5659->pdata.dmic2_data_pin);
device_property_read_u32(dev, "realtek,jd-src",
&rt5659->pdata.jd_src);
return 0;
}
static void rt5659_calibrate(struct rt5659_priv *rt5659)
{
int value, count;
/* Calibrate HPO Start */
/* Fine tune HP Performance */
regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502);
regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030);
regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00);
regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc);
regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280);
regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001);
regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e);
msleep(60);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e);
msleep(50);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004);
regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400);
msleep(50);
regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080);
usleep_range(10000, 10005);
regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009);
msleep(50);
regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80);
msleep(50);
regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16);
msleep(50);
/* Enalbe K ADC Power And Clock */
regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505);
msleep(50);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184);
regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1);
/* K Headphone */
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100);
msleep(60);
/* Manual K ADC Offset */
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016);
regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
0x8000, 0x8000);
count = 0;
while (true) {
regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 30) {
dev_err(rt5659->component->dev,
"HP Calibration 1 Failure\n");
return;
}
count++;
}
/* Manual K Internal Path Offset */
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f);
regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
0x8000, 0x8000);
count = 0;
while (true) {
regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 85) {
dev_err(rt5659->component->dev,
"HP Calibration 2 Failure\n");
return;
}
count++;
}
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
/* Calibrate HPO End */
/* Calibrate SPO Start */
regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260);
regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000);
regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000);
regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c);
regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000);
regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808);
regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e);
regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e);
regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803);
regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554);
regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103);
/* Enalbe K ADC Power And Clock */
regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909);
regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001,
0x0001);
/* Start Calibration */
regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021);
regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80);
regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1,
0x8000, 0x8000);
count = 0;
while (true) {
regmap_read(rt5659->regmap,
RT5659_SPK_DC_CAILB_CTRL_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 10) {
dev_err(rt5659->component->dev,
"SPK Calibration Failure\n");
return;
}
count++;
}
/* Calibrate SPO End */
/* Calibrate MONO Start */
regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000);
regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f);
regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a);
/* MONO NG2 GAIN 5dB */
regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003);
regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009);
/* Start Calibration */
regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f);
regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
0x8000, 0x8000);
count = 0;
while (true) {
regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
&value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
break;
if (count > 35) {
dev_err(rt5659->component->dev,
"Mono Calibration Failure\n");
return;
}
count++;
}
regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
/* Calibrate MONO End */
/* Power Off */
regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000);
regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005);
regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000);
regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011);
regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e);
regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a);
regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000);
regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000);
regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000);
regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e);
regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060);
regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000);
regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080);
regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080);
regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
}
static void rt5659_intel_hd_header_probe_setup(struct rt5659_priv *rt5659)
{
int value;
regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value);
if (!(value & 0x8)) {
rt5659->hda_hp_plugged = true;
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
0x10, 0x0);
} else {
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
0x10, 0x10);
}
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
RT5659_PWR_VREF2 | RT5659_PWR_MB,
RT5659_PWR_VREF2 | RT5659_PWR_MB);
msleep(20);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
RT5659_PWR_FV2, RT5659_PWR_FV2);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_3, RT5659_PWR_LDO2,
RT5659_PWR_LDO2);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_2, RT5659_PWR_MB1,
RT5659_PWR_MB1);
regmap_update_bits(rt5659->regmap, RT5659_PWR_VOL, RT5659_PWR_MIC_DET,
RT5659_PWR_MIC_DET);
msleep(20);
regmap_update_bits(rt5659->regmap, RT5659_4BTN_IL_CMD_2,
RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value);
regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
if (value & 0x2000) {
rt5659->hda_mic_plugged = true;
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
0x2, 0x2);
} else {
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
0x2, 0x0);
}
regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
}
static int rt5659_i2c_probe(struct i2c_client *i2c)
{
struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5659_priv *rt5659;
int ret;
unsigned int val;
rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv),
GFP_KERNEL);
if (rt5659 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5659);
if (pdata)
rt5659->pdata = *pdata;
else
rt5659_parse_dt(rt5659, &i2c->dev);
rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en",
GPIOD_OUT_HIGH);
if (IS_ERR(rt5659->gpiod_ldo1_en))
dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n");
rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset",
GPIOD_OUT_HIGH);
/* Sleep for 300 ms miniumum */
msleep(300);
rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap);
if (IS_ERR(rt5659->regmap)) {
ret = PTR_ERR(rt5659->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val);
if (val != DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt5659\n", val);
return -ENODEV;
}
regmap_write(rt5659->regmap, RT5659_RESET, 0);
/* Check if MCLK provided */
rt5659->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
if (IS_ERR(rt5659->mclk))
return PTR_ERR(rt5659->mclk);
rt5659_calibrate(rt5659);
/* line in diff mode*/
if (rt5659->pdata.in1_diff)
regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2,
RT5659_IN1_DF_MASK, RT5659_IN1_DF_MASK);
if (rt5659->pdata.in3_diff)
regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
RT5659_IN3_DF_MASK, RT5659_IN3_DF_MASK);
if (rt5659->pdata.in4_diff)
regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
RT5659_IN4_DF_MASK, RT5659_IN4_DF_MASK);
/* DMIC pin*/
if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL ||
rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) {
regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
RT5659_GP2_PIN_MASK, RT5659_GP2_PIN_DMIC1_SCL);
switch (rt5659->pdata.dmic1_data_pin) {
case RT5659_DMIC1_DATA_IN2N:
regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_IN2N);
break;
case RT5659_DMIC1_DATA_GPIO5:
regmap_update_bits(rt5659->regmap,
RT5659_GPIO_CTRL_3,
RT5659_I2S2_PIN_MASK,
RT5659_I2S2_PIN_GPIO);
regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO5);
regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
RT5659_GP5_PIN_MASK, RT5659_GP5_PIN_DMIC1_SDA);
break;
case RT5659_DMIC1_DATA_GPIO9:
regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO9);
regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
RT5659_GP9_PIN_MASK, RT5659_GP9_PIN_DMIC1_SDA);
break;
case RT5659_DMIC1_DATA_GPIO11:
regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO11);
regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
RT5659_GP11_PIN_MASK,
RT5659_GP11_PIN_DMIC1_SDA);
break;
default:
dev_dbg(&i2c->dev, "no DMIC1\n");
break;
}
switch (rt5659->pdata.dmic2_data_pin) {
case RT5659_DMIC2_DATA_IN2P:
regmap_update_bits(rt5659->regmap,
RT5659_DMIC_CTRL_1,
RT5659_DMIC_2_DP_MASK,
RT5659_DMIC_2_DP_IN2P);
break;
case RT5659_DMIC2_DATA_GPIO6:
regmap_update_bits(rt5659->regmap,
RT5659_DMIC_CTRL_1,
RT5659_DMIC_2_DP_MASK,
RT5659_DMIC_2_DP_GPIO6);
regmap_update_bits(rt5659->regmap,
RT5659_GPIO_CTRL_1,
RT5659_GP6_PIN_MASK,
RT5659_GP6_PIN_DMIC2_SDA);
break;
case RT5659_DMIC2_DATA_GPIO10:
regmap_update_bits(rt5659->regmap,
RT5659_DMIC_CTRL_1,
RT5659_DMIC_2_DP_MASK,
RT5659_DMIC_2_DP_GPIO10);
regmap_update_bits(rt5659->regmap,
RT5659_GPIO_CTRL_1,
RT5659_GP10_PIN_MASK,
RT5659_GP10_PIN_DMIC2_SDA);
break;
case RT5659_DMIC2_DATA_GPIO12:
regmap_update_bits(rt5659->regmap,
RT5659_DMIC_CTRL_1,
RT5659_DMIC_2_DP_MASK,
RT5659_DMIC_2_DP_GPIO12);
regmap_update_bits(rt5659->regmap,
RT5659_GPIO_CTRL_1,
RT5659_GP12_PIN_MASK,
RT5659_GP12_PIN_DMIC2_SDA);
break;
default:
dev_dbg(&i2c->dev, "no DMIC2\n");
break;
}
} else {
regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
RT5659_GP2_PIN_MASK | RT5659_GP5_PIN_MASK |
RT5659_GP9_PIN_MASK | RT5659_GP11_PIN_MASK |
RT5659_GP6_PIN_MASK | RT5659_GP10_PIN_MASK |
RT5659_GP12_PIN_MASK,
RT5659_GP2_PIN_GPIO2 | RT5659_GP5_PIN_GPIO5 |
RT5659_GP9_PIN_GPIO9 | RT5659_GP11_PIN_GPIO11 |
RT5659_GP6_PIN_GPIO6 | RT5659_GP10_PIN_GPIO10 |
RT5659_GP12_PIN_GPIO12);
regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
RT5659_DMIC_1_DP_MASK | RT5659_DMIC_2_DP_MASK,
RT5659_DMIC_1_DP_IN2N | RT5659_DMIC_2_DP_IN2P);
}
switch (rt5659->pdata.jd_src) {
case RT5659_JD3:
regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880);
regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000);
regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800);
regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
RT5659_PWR_MB, RT5659_PWR_MB);
regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001);
regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040);
INIT_DELAYED_WORK(&rt5659->jack_detect_work,
rt5659_jack_detect_work);
break;
case RT5659_JD_HDA_HEADER:
regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_3, 0x8000);
regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x0900);
regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0x70c0);
regmap_write(rt5659->regmap, RT5659_JD_CTRL_1, 0x2000);
regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_1, 0x0040);
INIT_DELAYED_WORK(&rt5659->jack_detect_work,
rt5659_jack_detect_intel_hd_header);
rt5659_intel_hd_header_probe_setup(rt5659);
break;
default:
break;
}
if (i2c->irq) {
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
rt5659_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
| IRQF_ONESHOT, "rt5659", rt5659);
if (ret)
dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
/* Enable IRQ output for GPIO1 pin any way */
regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
RT5659_GP1_PIN_MASK, RT5659_GP1_PIN_IRQ);
}
return devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_rt5659,
rt5659_dai, ARRAY_SIZE(rt5659_dai));
}
static void rt5659_i2c_shutdown(struct i2c_client *client)
{
struct rt5659_priv *rt5659 = i2c_get_clientdata(client);
regmap_write(rt5659->regmap, RT5659_RESET, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id rt5659_of_match[] = {
{ .compatible = "realtek,rt5658", },
{ .compatible = "realtek,rt5659", },
{ },
};
MODULE_DEVICE_TABLE(of, rt5659_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id rt5659_acpi_match[] = {
{ "10EC5658", 0, },
{ "10EC5659", 0, },
{ },
};
MODULE_DEVICE_TABLE(acpi, rt5659_acpi_match);
#endif
static struct i2c_driver rt5659_i2c_driver = {
.driver = {
.name = "rt5659",
.of_match_table = of_match_ptr(rt5659_of_match),
.acpi_match_table = ACPI_PTR(rt5659_acpi_match),
},
.probe = rt5659_i2c_probe,
.shutdown = rt5659_i2c_shutdown,
.id_table = rt5659_i2c_id,
};
module_i2c_driver(rt5659_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5659 driver");
MODULE_AUTHOR("Bard Liao <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/rt5659.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// rt712-sdca.c -- rt712 SDCA ALSA SoC audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/bitops.h>
#include <sound/core.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <sound/initval.h>
#include <sound/jack.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pm_runtime.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/slab.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "rt712-sdca.h"
static int rt712_sdca_index_write(struct rt712_sdca_priv *rt712,
unsigned int nid, unsigned int reg, unsigned int value)
{
int ret;
struct regmap *regmap = rt712->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_write(regmap, addr, value);
if (ret < 0)
dev_err(&rt712->slave->dev,
"Failed to set private value: %06x <= %04x ret=%d\n",
addr, value, ret);
return ret;
}
static int rt712_sdca_index_read(struct rt712_sdca_priv *rt712,
unsigned int nid, unsigned int reg, unsigned int *value)
{
int ret;
struct regmap *regmap = rt712->mbq_regmap;
unsigned int addr = (nid << 20) | reg;
ret = regmap_read(regmap, addr, value);
if (ret < 0)
dev_err(&rt712->slave->dev,
"Failed to get private value: %06x => %04x ret=%d\n",
addr, *value, ret);
return ret;
}
static int rt712_sdca_index_update_bits(struct rt712_sdca_priv *rt712,
unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
{
unsigned int tmp;
int ret;
ret = rt712_sdca_index_read(rt712, nid, reg, &tmp);
if (ret < 0)
return ret;
set_mask_bits(&tmp, mask, val);
return rt712_sdca_index_write(rt712, nid, reg, tmp);
}
static int rt712_sdca_calibration(struct rt712_sdca_priv *rt712)
{
unsigned int val, loop_rc = 0, loop_dc = 0;
struct device *dev;
struct regmap *regmap = rt712->regmap;
int chk_cnt = 100;
int ret = 0;
mutex_lock(&rt712->calibrate_mutex);
dev = regmap_get_device(regmap);
/* Set HP-JD source from JD1 */
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_CC_DET1, 0x043a);
/* FSM switch to calibration manual mode */
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_FSM_CTL, 0x4100);
/* Calibration setting */
rt712_sdca_index_write(rt712, RT712_VENDOR_CALI, RT712_DAC_DC_CALI_CTL1, 0x7883);
/* W1C Trigger DC calibration (HP & Class-D) */
rt712_sdca_index_write(rt712, RT712_VENDOR_CALI, RT712_DAC_DC_CALI_CTL1, 0xf893);
/* wait for calibration process */
rt712_sdca_index_read(rt712, RT712_VENDOR_CALI,
RT712_DAC_DC_CALI_CTL1, &val);
for (loop_dc = 0; loop_dc < chk_cnt &&
(val & RT712_DAC_DC_CALI_TRIGGER); loop_dc++) {
usleep_range(10000, 11000);
ret = rt712_sdca_index_read(rt712, RT712_VENDOR_CALI,
RT712_DAC_DC_CALI_CTL1, &val);
if (ret < 0)
goto _cali_fail_;
}
if (loop_dc == chk_cnt)
dev_err(dev, "%s, calibration time-out!\n", __func__);
if (loop_dc == chk_cnt || loop_rc == chk_cnt)
ret = -ETIMEDOUT;
_cali_fail_:
/* Enable Rldet in FSM */
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_FSM_CTL, 0x4500);
/* Sensing Lch+Rch */
rt712_sdca_index_write(rt712, RT712_VENDOR_IMS_DRE, RT712_IMS_DIGITAL_CTL1, 0x040f);
/* Sine gen path control */
rt712_sdca_index_write(rt712, RT712_VENDOR_IMS_DRE, RT712_IMS_DIGITAL_CTL5, 0x0000);
/* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_DIGITAL_MISC_CTRL4, 0x0010);
mutex_unlock(&rt712->calibrate_mutex);
dev_dbg(dev, "%s calibration complete, ret=%d\n", __func__, ret);
return ret;
}
static unsigned int rt712_sdca_button_detect(struct rt712_sdca_priv *rt712)
{
unsigned int btn_type = 0, offset, idx, val, owner;
int ret;
unsigned char buf[3];
/* get current UMP message owner */
ret = regmap_read(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_CURRENT_OWNER, 0),
&owner);
if (ret < 0)
return 0;
/* if owner is device then there is no button event from device */
if (owner == 1)
return 0;
/* read UMP message offset */
ret = regmap_read(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0),
&offset);
if (ret < 0)
goto _end_btn_det_;
for (idx = 0; idx < sizeof(buf); idx++) {
ret = regmap_read(rt712->regmap,
RT712_BUF_ADDR_HID1 + offset + idx, &val);
if (ret < 0)
goto _end_btn_det_;
buf[idx] = val & 0xff;
}
if (buf[0] == 0x11) {
switch (buf[1] & 0xf0) {
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
switch (buf[2]) {
case 0x01:
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x02:
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x04:
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x08:
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
}
_end_btn_det_:
/* Host is owner, so set back to device */
if (owner == 0)
/* set owner to device */
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01,
RT712_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE, 0), 0x01);
return btn_type;
}
static int rt712_sdca_headset_detect(struct rt712_sdca_priv *rt712)
{
unsigned int det_mode;
int ret;
/* get detected_mode */
ret = regmap_read(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_GE49, RT712_SDCA_CTL_DETECTED_MODE, 0),
&det_mode);
if (ret < 0)
goto io_error;
switch (det_mode) {
case 0x00:
rt712->jack_type = 0;
break;
case 0x03:
rt712->jack_type = SND_JACK_HEADPHONE;
break;
case 0x05:
rt712->jack_type = SND_JACK_HEADSET;
break;
}
/* write selected_mode */
if (det_mode) {
ret = regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_GE49, RT712_SDCA_CTL_SELECTED_MODE, 0),
det_mode);
if (ret < 0)
goto io_error;
}
dev_dbg(&rt712->slave->dev,
"%s, detected_mode=0x%x\n", __func__, det_mode);
return 0;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static void rt712_sdca_jack_detect_handler(struct work_struct *work)
{
struct rt712_sdca_priv *rt712 =
container_of(work, struct rt712_sdca_priv, jack_detect_work.work);
int btn_type = 0, ret;
if (!rt712->hs_jack)
return;
if (!rt712->component->card || !rt712->component->card->instantiated)
return;
/* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */
if (rt712->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) {
ret = rt712_sdca_headset_detect(rt712);
if (ret < 0)
return;
}
/* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
if (rt712->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
btn_type = rt712_sdca_button_detect(rt712);
if (rt712->jack_type == 0)
btn_type = 0;
dev_dbg(&rt712->slave->dev,
"in %s, jack_type=0x%x\n", __func__, rt712->jack_type);
dev_dbg(&rt712->slave->dev,
"in %s, btn_type=0x%x\n", __func__, btn_type);
dev_dbg(&rt712->slave->dev,
"in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt712->scp_sdca_stat1, rt712->scp_sdca_stat2);
snd_soc_jack_report(rt712->hs_jack, rt712->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt712->hs_jack, rt712->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt712->jack_btn_check_work, msecs_to_jiffies(200));
}
}
static void rt712_sdca_btn_check_handler(struct work_struct *work)
{
struct rt712_sdca_priv *rt712 =
container_of(work, struct rt712_sdca_priv, jack_btn_check_work.work);
int btn_type = 0, ret, idx;
unsigned int det_mode, offset, val;
unsigned char buf[3];
ret = regmap_read(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_GE49, RT712_SDCA_CTL_DETECTED_MODE, 0),
&det_mode);
if (ret < 0)
goto io_error;
/* pin attached */
if (det_mode) {
/* read UMP message offset */
ret = regmap_read(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_HID, RT712_SDCA_ENT_HID01, RT712_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0),
&offset);
if (ret < 0)
goto io_error;
for (idx = 0; idx < sizeof(buf); idx++) {
ret = regmap_read(rt712->regmap,
RT712_BUF_ADDR_HID1 + offset + idx, &val);
if (ret < 0)
goto io_error;
buf[idx] = val & 0xff;
}
if (buf[0] == 0x11) {
switch (buf[1] & 0xf0) {
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
switch (buf[2]) {
case 0x01:
case 0x10:
btn_type |= SND_JACK_BTN_2;
break;
case 0x02:
case 0x20:
btn_type |= SND_JACK_BTN_3;
break;
case 0x04:
case 0x40:
btn_type |= SND_JACK_BTN_0;
break;
case 0x08:
case 0x80:
btn_type |= SND_JACK_BTN_1;
break;
}
}
} else {
rt712->jack_type = 0;
}
dev_dbg(&rt712->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
snd_soc_jack_report(rt712->hs_jack, rt712->jack_type | btn_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
if (btn_type) {
/* button released */
snd_soc_jack_report(rt712->hs_jack, rt712->jack_type,
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3);
mod_delayed_work(system_power_efficient_wq,
&rt712->jack_btn_check_work, msecs_to_jiffies(200));
}
return;
io_error:
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
}
static void rt712_sdca_jack_init(struct rt712_sdca_priv *rt712)
{
mutex_lock(&rt712->calibrate_mutex);
if (rt712->hs_jack) {
/* Enable HID1 event & set button RTC mode */
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_UMP_HID_CTL5, 0xfff0);
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_UMP_HID_CTL0, 0x1100, 0x1100);
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_UMP_HID_CTL7, 0xf000, 0x0000);
/* detected_mode_change_event_en & hid1_push_button_event_en */
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_GE_RELATED_CTL1, 0x0c00, 0x0c00);
/* ge_inbox_en */
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_GE_RELATED_CTL2, 0x0020, 0x0000);
switch (rt712->jd_src) {
case RT712_JD1:
/* Set HP-JD source from JD1 */
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_CC_DET1, 0x043a);
break;
default:
dev_warn(rt712->component->dev, "Wrong JD source\n");
break;
}
/* set SCP_SDCA_IntMask1[0]=1 */
sdw_write_no_pm(rt712->slave, SDW_SCP_SDCA_INTMASK1, SDW_SCP_SDCA_INTMASK_SDCA_0);
/* set SCP_SDCA_IntMask2[0]=1 */
sdw_write_no_pm(rt712->slave, SDW_SCP_SDCA_INTMASK2, SDW_SCP_SDCA_INTMASK_SDCA_8);
dev_dbg(&rt712->slave->dev, "in %s enable\n", __func__);
/* trigger GE interrupt */
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_GE_RELATED_CTL1, 0x0080, 0x0080);
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_GE_RELATED_CTL1, 0x0080, 0x0000);
} else {
/* disable HID1 & detected_mode_change event */
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_GE_RELATED_CTL1, 0x0c00, 0x0000);
dev_dbg(&rt712->slave->dev, "in %s disable\n", __func__);
}
mutex_unlock(&rt712->calibrate_mutex);
}
static int rt712_sdca_set_jack_detect(struct snd_soc_component *component,
struct snd_soc_jack *hs_jack, void *data)
{
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
int ret;
rt712->hs_jack = hs_jack;
if (!rt712->first_hw_init)
return 0;
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
if (ret != -EACCES) {
dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
return ret;
}
/* pm_runtime not enabled yet */
dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
return 0;
}
rt712_sdca_jack_init(rt712);
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return 0;
}
/* For SDCA control DAC/ADC Gain */
static int rt712_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned int read_l, read_r, gain_l_val, gain_r_val;
unsigned int adc_vol_flag = 0;
unsigned int lvalue, rvalue;
const unsigned int interval_offset = 0xc0;
const unsigned int tendB = 0xa00;
if (strstr(ucontrol->id.name, "FU0F Capture Volume"))
adc_vol_flag = 1;
regmap_read(rt712->mbq_regmap, mc->reg, &lvalue);
regmap_read(rt712->mbq_regmap, mc->rreg, &rvalue);
/* L Channel */
gain_l_val = ucontrol->value.integer.value[0];
if (gain_l_val > mc->max)
gain_l_val = mc->max;
if (mc->shift == 8) /* boost gain */
gain_l_val = gain_l_val * tendB;
else {
/* ADC/DAC gain */
if (adc_vol_flag)
gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset);
else
gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
gain_l_val &= 0xffff;
}
/* R Channel */
gain_r_val = ucontrol->value.integer.value[1];
if (gain_r_val > mc->max)
gain_r_val = mc->max;
if (mc->shift == 8) /* boost gain */
gain_r_val = gain_r_val * tendB;
else {
/* ADC/DAC gain */
if (adc_vol_flag)
gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset);
else
gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
gain_r_val &= 0xffff;
}
if (lvalue == gain_l_val && rvalue == gain_r_val)
return 0;
/* Lch*/
regmap_write(rt712->mbq_regmap, mc->reg, gain_l_val);
/* Rch */
regmap_write(rt712->mbq_regmap, mc->rreg, gain_r_val);
regmap_read(rt712->mbq_regmap, mc->reg, &read_l);
regmap_read(rt712->mbq_regmap, mc->rreg, &read_r);
if (read_r == gain_r_val && read_l == gain_l_val)
return 1;
return -EIO;
}
static int rt712_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
unsigned int adc_vol_flag = 0;
const unsigned int interval_offset = 0xc0;
const unsigned int tendB = 0xa00;
if (strstr(ucontrol->id.name, "FU0F Capture Volume"))
adc_vol_flag = 1;
regmap_read(rt712->mbq_regmap, mc->reg, &read_l);
regmap_read(rt712->mbq_regmap, mc->rreg, &read_r);
if (mc->shift == 8) /* boost gain */
ctl_l = read_l / tendB;
else {
if (adc_vol_flag)
ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset);
else
ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
}
if (read_l != read_r) {
if (mc->shift == 8) /* boost gain */
ctl_r = read_r / tendB;
else { /* ADC/DAC gain */
if (adc_vol_flag)
ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset);
else
ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
}
} else
ctl_r = ctl_l;
ucontrol->value.integer.value[0] = ctl_l;
ucontrol->value.integer.value[1] = ctl_r;
return 0;
}
static int rt712_sdca_set_fu0f_capture_ctl(struct rt712_sdca_priv *rt712)
{
int err;
unsigned int ch_l, ch_r;
ch_l = (rt712->fu0f_dapm_mute || rt712->fu0f_mixer_l_mute) ? 0x01 : 0x00;
ch_r = (rt712->fu0f_dapm_mute || rt712->fu0f_mixer_r_mute) ? 0x01 : 0x00;
err = regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F,
RT712_SDCA_CTL_FU_MUTE, CH_L), ch_l);
if (err < 0)
return err;
err = regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F,
RT712_SDCA_CTL_FU_MUTE, CH_R), ch_r);
if (err < 0)
return err;
return 0;
}
static int rt712_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = !rt712->fu0f_mixer_l_mute;
ucontrol->value.integer.value[1] = !rt712->fu0f_mixer_r_mute;
return 0;
}
static int rt712_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
int err;
if (rt712->fu0f_mixer_l_mute == !ucontrol->value.integer.value[0] &&
rt712->fu0f_mixer_r_mute == !ucontrol->value.integer.value[1])
return 0;
rt712->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
rt712->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
err = rt712_sdca_set_fu0f_capture_ctl(rt712);
if (err < 0)
return err;
return 1;
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0);
static const struct snd_kcontrol_new rt712_sdca_controls[] = {
SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05, RT712_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05, RT712_SDCA_CTL_FU_VOLUME, CH_R),
0, 0x57, 0,
rt712_sdca_set_gain_get, rt712_sdca_set_gain_put, out_vol_tlv),
SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
rt712_sdca_fu0f_capture_get, rt712_sdca_fu0f_capture_put),
SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F, RT712_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F, RT712_SDCA_CTL_FU_VOLUME, CH_R),
0, 0x3f, 0,
rt712_sdca_set_gain_get, rt712_sdca_set_gain_put, mic_vol_tlv),
SOC_DOUBLE_R_EXT_TLV("FU44 Boost Volume",
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PLATFORM_FU44, RT712_SDCA_CTL_FU_CH_GAIN, CH_L),
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PLATFORM_FU44, RT712_SDCA_CTL_FU_CH_GAIN, CH_R),
8, 3, 0,
rt712_sdca_set_gain_get, rt712_sdca_set_gain_put, boost_vol_tlv),
};
static const struct snd_kcontrol_new rt712_sdca_spk_controls[] = {
SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume",
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_USER_FU06, RT712_SDCA_CTL_FU_VOLUME, CH_L),
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_USER_FU06, RT712_SDCA_CTL_FU_VOLUME, CH_R),
0, 0x57, 0,
rt712_sdca_set_gain_get, rt712_sdca_set_gain_put, out_vol_tlv),
};
static int rt712_sdca_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned int val = 0, mask = 0x3300;
rt712_sdca_index_read(rt712, RT712_VENDOR_HDA_CTL, RT712_MIXER_CTL1, &val);
val = val & mask;
switch (val) {
case 0x3000:
val = 1;
break;
case 0x0300:
val = 0;
break;
}
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int rt712_sdca_mux_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int mask_sft;
unsigned int val;
if (item[0] >= e->items)
return -EINVAL;
if (ucontrol->value.enumerated.item[0] == 0)
mask_sft = 12;
else if (ucontrol->value.enumerated.item[0] == 1)
mask_sft = 8;
else
return -EINVAL;
rt712_sdca_index_read(rt712, RT712_VENDOR_HDA_CTL, RT712_MIXER_CTL1, &val);
val = (val >> mask_sft) & 0x3;
if (!val)
return 0;
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_MIXER_CTL1, 0x3fff);
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_MIXER_CTL1, 0x3 << mask_sft, 0);
snd_soc_dapm_mux_update_power(dapm, kcontrol,
item[0], e, NULL);
return 1;
}
static const char * const adc_mux_text[] = {
"MIC2",
"LINE2",
};
static SOC_ENUM_SINGLE_DECL(
rt712_adc23_enum, SND_SOC_NOPM, 0, adc_mux_text);
static const struct snd_kcontrol_new rt712_sdca_adc23_mux =
SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt712_adc23_enum,
rt712_sdca_mux_get, rt712_sdca_mux_put);
static int rt712_sdca_fu05_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned char unmute = 0x0, mute = 0x1;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05,
RT712_SDCA_CTL_FU_MUTE, CH_L),
unmute);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05,
RT712_SDCA_CTL_FU_MUTE, CH_R),
unmute);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05,
RT712_SDCA_CTL_FU_MUTE, CH_L),
mute);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05,
RT712_SDCA_CTL_FU_MUTE, CH_R),
mute);
break;
}
return 0;
}
static int rt712_sdca_fu0f_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
rt712->fu0f_dapm_mute = false;
rt712_sdca_set_fu0f_capture_ctl(rt712);
break;
case SND_SOC_DAPM_PRE_PMD:
rt712->fu0f_dapm_mute = true;
rt712_sdca_set_fu0f_capture_ctl(rt712);
break;
}
return 0;
}
static int rt712_sdca_pde40_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PDE40,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PDE40,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static int rt712_sdca_pde12_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PDE12,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PDE12,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
}
return 0;
}
static int rt712_sdca_classd_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
unsigned char ps0 = 0x0, ps3 = 0x3;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_PDE23,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps0);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_PDE23,
RT712_SDCA_CTL_REQ_POWER_STATE, 0),
ps3);
break;
default:
break;
}
return 0;
}
static const struct snd_kcontrol_new rt712_spk_sto_dac =
SOC_DAPM_DOUBLE_R("Switch",
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_USER_FU06, RT712_SDCA_CTL_FU_MUTE, CH_L),
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_USER_FU06, RT712_SDCA_CTL_FU_MUTE, CH_R),
0, 1, 1);
static const struct snd_soc_dapm_widget rt712_sdca_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("LINE2"),
SND_SOC_DAPM_SUPPLY("PDE 40", SND_SOC_NOPM, 0, 0,
rt712_sdca_pde40_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0,
rt712_sdca_pde12_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_DAC_E("FU 05", NULL, SND_SOC_NOPM, 0, 0,
rt712_sdca_fu05_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("FU 0F", NULL, SND_SOC_NOPM, 0, 0,
rt712_sdca_fu0f_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
&rt712_sdca_adc23_mux),
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route rt712_sdca_audio_map[] = {
{ "FU 05", NULL, "DP1RX" },
{ "DP4TX", NULL, "FU 0F" },
{ "FU 0F", NULL, "PDE 12" },
{ "FU 0F", NULL, "ADC 23 Mux" },
{ "ADC 23 Mux", "LINE2", "LINE2" },
{ "ADC 23 Mux", "MIC2", "MIC2" },
{ "HP", NULL, "PDE 40" },
{ "HP", NULL, "FU 05" },
};
static const struct snd_soc_dapm_widget rt712_sdca_spk_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Playback", 0, SND_SOC_NOPM, 0, 0),
/* Digital Interface */
SND_SOC_DAPM_SWITCH("FU06", SND_SOC_NOPM, 0, 0, &rt712_spk_sto_dac),
/* Output */
SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
rt712_sdca_classd_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_OUTPUT("SPOL"),
SND_SOC_DAPM_OUTPUT("SPOR"),
};
static const struct snd_soc_dapm_route rt712_sdca_spk_dapm_routes[] = {
{ "FU06", "Switch", "DP3RX" },
{ "CLASS D", NULL, "FU06" },
{ "SPOL", NULL, "CLASS D" },
{ "SPOR", NULL, "CLASS D" },
};
static int rt712_sdca_parse_dt(struct rt712_sdca_priv *rt712, struct device *dev)
{
device_property_read_u32(dev, "realtek,jd-src", &rt712->jd_src);
return 0;
}
static int rt712_sdca_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
int ret;
rt712_sdca_parse_dt(rt712, &rt712->slave->dev);
rt712->component = component;
if (!rt712->first_hw_init)
return 0;
ret = pm_runtime_resume(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
/* add SPK route */
if (rt712->hw_id != RT712_DEV_ID_713) {
snd_soc_add_component_controls(component,
rt712_sdca_spk_controls, ARRAY_SIZE(rt712_sdca_spk_controls));
snd_soc_dapm_new_controls(dapm,
rt712_sdca_spk_dapm_widgets, ARRAY_SIZE(rt712_sdca_spk_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt712_sdca_spk_dapm_routes, ARRAY_SIZE(rt712_sdca_spk_dapm_routes));
}
return 0;
}
static const struct snd_soc_component_driver soc_sdca_dev_rt712 = {
.probe = rt712_sdca_probe,
.controls = rt712_sdca_controls,
.num_controls = ARRAY_SIZE(rt712_sdca_controls),
.dapm_widgets = rt712_sdca_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt712_sdca_dapm_widgets),
.dapm_routes = rt712_sdca_audio_map,
.num_dapm_routes = ARRAY_SIZE(rt712_sdca_audio_map),
.set_jack = rt712_sdca_set_jack_detect,
.endianness = 1,
};
static int rt712_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
int direction)
{
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
return 0;
}
static void rt712_sdca_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
snd_soc_dai_set_dma_data(dai, substream, NULL);
}
static int rt712_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
struct sdw_stream_config stream_config;
struct sdw_port_config port_config;
enum sdw_data_direction direction;
struct sdw_stream_runtime *sdw_stream;
int retval, port, num_channels;
unsigned int sampling_rate;
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
if (!sdw_stream)
return -EINVAL;
if (!rt712->slave)
return -EINVAL;
/* SoundWire specific configuration */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
direction = SDW_DATA_DIR_RX;
if (dai->id == RT712_AIF1)
port = 1;
else if (dai->id == RT712_AIF2)
port = 3;
else
return -EINVAL;
} else {
direction = SDW_DATA_DIR_TX;
if (dai->id == RT712_AIF1)
port = 4;
else
return -EINVAL;
}
stream_config.frame_rate = params_rate(params);
stream_config.ch_count = params_channels(params);
stream_config.bps = snd_pcm_format_width(params_format(params));
stream_config.direction = direction;
num_channels = params_channels(params);
port_config.ch_mask = GENMASK(num_channels - 1, 0);
port_config.num = port;
retval = sdw_stream_add_slave(rt712->slave, &stream_config,
&port_config, 1, sdw_stream);
if (retval) {
dev_err(dai->dev, "Unable to configure port\n");
return retval;
}
if (params_channels(params) > 16) {
dev_err(component->dev, "Unsupported channels %d\n",
params_channels(params));
return -EINVAL;
}
/* sampling rate configuration */
switch (params_rate(params)) {
case 44100:
sampling_rate = RT712_SDCA_RATE_44100HZ;
break;
case 48000:
sampling_rate = RT712_SDCA_RATE_48000HZ;
break;
case 96000:
sampling_rate = RT712_SDCA_RATE_96000HZ;
break;
case 192000:
sampling_rate = RT712_SDCA_RATE_192000HZ;
break;
default:
dev_err(component->dev, "Rate %d is not supported\n",
params_rate(params));
return -EINVAL;
}
/* set sampling frequency */
switch (dai->id) {
case RT712_AIF1:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_CS01, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_CS11, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
break;
case RT712_AIF2:
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_CS31, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
sampling_rate);
break;
default:
dev_err(component->dev, "Wrong DAI id\n");
return -EINVAL;
}
return 0;
}
static int rt712_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct rt712_sdca_priv *rt712 = snd_soc_component_get_drvdata(component);
struct sdw_stream_runtime *sdw_stream =
snd_soc_dai_get_dma_data(dai, substream);
if (!rt712->slave)
return -EINVAL;
sdw_stream_remove_slave(rt712->slave, sdw_stream);
return 0;
}
#define RT712_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000)
#define RT712_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops rt712_sdca_ops = {
.hw_params = rt712_sdca_pcm_hw_params,
.hw_free = rt712_sdca_pcm_hw_free,
.set_stream = rt712_sdca_set_sdw_stream,
.shutdown = rt712_sdca_shutdown,
};
static struct snd_soc_dai_driver rt712_sdca_dai[] = {
{
.name = "rt712-sdca-aif1",
.id = RT712_AIF1,
.playback = {
.stream_name = "DP1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT712_STEREO_RATES,
.formats = RT712_FORMATS,
},
.capture = {
.stream_name = "DP4 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT712_STEREO_RATES,
.formats = RT712_FORMATS,
},
.ops = &rt712_sdca_ops,
},
{
.name = "rt712-sdca-aif2",
.id = RT712_AIF2,
.playback = {
.stream_name = "DP3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT712_STEREO_RATES,
.formats = RT712_FORMATS,
},
.ops = &rt712_sdca_ops,
}
};
int rt712_sdca_init(struct device *dev, struct regmap *regmap,
struct regmap *mbq_regmap, struct sdw_slave *slave)
{
struct rt712_sdca_priv *rt712;
int ret;
rt712 = devm_kzalloc(dev, sizeof(*rt712), GFP_KERNEL);
if (!rt712)
return -ENOMEM;
dev_set_drvdata(dev, rt712);
rt712->slave = slave;
rt712->regmap = regmap;
rt712->mbq_regmap = mbq_regmap;
regcache_cache_only(rt712->regmap, true);
regcache_cache_only(rt712->mbq_regmap, true);
mutex_init(&rt712->calibrate_mutex);
mutex_init(&rt712->disable_irq_lock);
INIT_DELAYED_WORK(&rt712->jack_detect_work, rt712_sdca_jack_detect_handler);
INIT_DELAYED_WORK(&rt712->jack_btn_check_work, rt712_sdca_btn_check_handler);
/*
* Mark hw_init to false
* HW init will be performed when device reports present
*/
rt712->hw_init = false;
rt712->first_hw_init = false;
rt712->fu0f_dapm_mute = true;
rt712->fu0f_mixer_l_mute = rt712->fu0f_mixer_r_mute = true;
/* JD source uses JD1 in default */
rt712->jd_src = RT712_JD1;
if (slave->id.part_id != RT712_PART_ID_713)
ret = devm_snd_soc_register_component(dev,
&soc_sdca_dev_rt712, rt712_sdca_dai, ARRAY_SIZE(rt712_sdca_dai));
else
ret = devm_snd_soc_register_component(dev,
&soc_sdca_dev_rt712, rt712_sdca_dai, 1);
if (ret < 0)
return ret;
/* set autosuspend parameters */
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
/* make sure the device does not suspend immediately */
pm_runtime_mark_last_busy(dev);
pm_runtime_enable(dev);
/* important note: the device is NOT tagged as 'active' and will remain
* 'suspended' until the hardware is enumerated/initialized. This is required
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
* fail with -EACCESS because of race conditions between card creation and enumeration
*/
dev_dbg(dev, "%s\n", __func__);
return 0;
}
int rt712_sdca_io_init(struct device *dev, struct sdw_slave *slave)
{
struct rt712_sdca_priv *rt712 = dev_get_drvdata(dev);
int ret = 0;
unsigned int val, hibernation_flag;
rt712->disable_irq = false;
if (rt712->hw_init)
return 0;
regcache_cache_only(rt712->regmap, false);
regcache_cache_only(rt712->mbq_regmap, false);
if (rt712->first_hw_init) {
regcache_cache_bypass(rt712->regmap, true);
regcache_cache_bypass(rt712->mbq_regmap, true);
} else {
/*
* PM runtime status is marked as 'active' only when a Slave reports as Attached
*/
/* update count of parent 'active' children */
pm_runtime_set_active(&slave->dev);
}
pm_runtime_get_noresume(&slave->dev);
rt712_sdca_index_read(rt712, RT712_VENDOR_REG, RT712_JD_PRODUCT_NUM, &val);
rt712->hw_id = (val & 0xf000) >> 12;
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_ANALOG_BIAS_CTL3, 0xaa81);
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_LDO2_3_CTL1, 0xa1e0);
rt712_sdca_index_write(rt712, RT712_VENDOR_IMS_DRE, RT712_HP_DETECT_RLDET_CTL1, 0x0000);
rt712_sdca_index_write(rt712, RT712_VENDOR_IMS_DRE, RT712_HP_DETECT_RLDET_CTL2, 0x0000);
rt712_sdca_index_write(rt712, RT712_VENDOR_ANALOG_CTL, RT712_MISC_POWER_CTL7, 0x0000);
regmap_write(rt712->regmap, RT712_RC_CAL, 0x23);
/* calibration */
rt712_sdca_index_read(rt712, RT712_VENDOR_REG, RT712_SW_CONFIG1, &hibernation_flag);
if (!hibernation_flag) {
ret = rt712_sdca_calibration(rt712);
if (ret < 0)
dev_err(dev, "%s, calibration failed!\n", __func__);
}
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_MIXER_CTL1, 0x3000, 0x0000);
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_ADC0A_08_PDE_FLOAT_CTL, 0x1112);
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_MIC2_LINE2_PDE_FLOAT_CTL, 0x3412);
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL,
RT712_DAC03_HP_PDE_FLOAT_CTL, 0x4040);
rt712_sdca_index_update_bits(rt712, RT712_VENDOR_HDA_CTL,
RT712_HDA_LEGACY_GPIO_WAKE_EN_CTL, 0x0001, 0x0000);
regmap_write(rt712->regmap, 0x2f50, 0x00);
regmap_write(rt712->regmap, 0x2f54, 0x00);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_IT09, RT712_SDCA_CTL_VENDOR_DEF, 0), 0x01);
/* add SPK settings */
if (rt712->hw_id != RT712_DEV_ID_713) {
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL, RT712_AMP_PDE_FLOAT_CTL, 0x2323);
rt712_sdca_index_write(rt712, RT712_VENDOR_HDA_CTL, RT712_EAPD_CTL, 0x0002);
regmap_write(rt712->regmap,
SDW_SDCA_CTL(FUNC_NUM_AMP, RT712_SDCA_ENT_OT23, RT712_SDCA_CTL_VENDOR_DEF, 0), 0x04);
}
/*
* if set_jack callback occurred early than io_init,
* we set up the jack detection function now
*/
if (rt712->hs_jack)
rt712_sdca_jack_init(rt712);
if (!hibernation_flag)
rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_SW_CONFIG1, 0x0001);
if (rt712->first_hw_init) {
regcache_cache_bypass(rt712->regmap, false);
regcache_mark_dirty(rt712->regmap);
regcache_cache_bypass(rt712->mbq_regmap, false);
regcache_mark_dirty(rt712->mbq_regmap);
} else
rt712->first_hw_init = true;
/* Mark Slave initialization complete */
rt712->hw_init = true;
pm_runtime_mark_last_busy(&slave->dev);
pm_runtime_put_autosuspend(&slave->dev);
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
return 0;
}
MODULE_DESCRIPTION("ASoC RT712 SDCA SDW driver");
MODULE_AUTHOR("Shuming Fan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/rt712-sdca.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017, Maxim Integrated
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max98373.h"
static const u32 max98373_i2c_cache_reg[] = {
MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
MAX98373_R20B6_BDE_CUR_STATE_READBACK,
};
static struct reg_default max98373_reg[] = {
{MAX98373_R2000_SW_RESET, 0x00},
{MAX98373_R2001_INT_RAW1, 0x00},
{MAX98373_R2002_INT_RAW2, 0x00},
{MAX98373_R2003_INT_RAW3, 0x00},
{MAX98373_R2004_INT_STATE1, 0x00},
{MAX98373_R2005_INT_STATE2, 0x00},
{MAX98373_R2006_INT_STATE3, 0x00},
{MAX98373_R2007_INT_FLAG1, 0x00},
{MAX98373_R2008_INT_FLAG2, 0x00},
{MAX98373_R2009_INT_FLAG3, 0x00},
{MAX98373_R200A_INT_EN1, 0x00},
{MAX98373_R200B_INT_EN2, 0x00},
{MAX98373_R200C_INT_EN3, 0x00},
{MAX98373_R200D_INT_FLAG_CLR1, 0x00},
{MAX98373_R200E_INT_FLAG_CLR2, 0x00},
{MAX98373_R200F_INT_FLAG_CLR3, 0x00},
{MAX98373_R2010_IRQ_CTRL, 0x00},
{MAX98373_R2014_THERM_WARN_THRESH, 0x10},
{MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
{MAX98373_R2016_THERM_HYSTERESIS, 0x01},
{MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
{MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
{MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
{MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
{MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2022_PCM_TX_SRC_1, 0x00},
{MAX98373_R2023_PCM_TX_SRC_2, 0x00},
{MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
{MAX98373_R2025_AUDIO_IF_MODE, 0x00},
{MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
{MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
{MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
{MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
{MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
{MAX98373_R202B_PCM_RX_EN, 0x00},
{MAX98373_R202C_PCM_TX_EN, 0x00},
{MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
{MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
{MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
{MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
{MAX98373_R2034_ICC_TX_CNTL, 0x00},
{MAX98373_R2035_ICC_TX_EN, 0x00},
{MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
{MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
{MAX98373_R203E_AMP_PATH_GAIN, 0x08},
{MAX98373_R203F_AMP_DSP_CFG, 0x02},
{MAX98373_R2040_TONE_GEN_CFG, 0x00},
{MAX98373_R2041_AMP_CFG, 0x03},
{MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
{MAX98373_R2043_AMP_EN, 0x00},
{MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
{MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
{MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
{MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
{MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
{MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
{MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
{MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
{MAX98373_R2090_BDE_LVL_HOLD, 0x00},
{MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
{MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
{MAX98373_R2097_BDE_L1_THRESH, 0x00},
{MAX98373_R2098_BDE_L2_THRESH, 0x00},
{MAX98373_R2099_BDE_L3_THRESH, 0x00},
{MAX98373_R209A_BDE_L4_THRESH, 0x00},
{MAX98373_R209B_BDE_THRESH_HYST, 0x00},
{MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
{MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
{MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
{MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
{MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
{MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
{MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
{MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
{MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
{MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
{MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
{MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
{MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
{MAX98373_R20B5_BDE_EN, 0x00},
{MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
{MAX98373_R20D1_DHT_CFG, 0x01},
{MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
{MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
{MAX98373_R20D4_DHT_EN, 0x00},
{MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
{MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
{MAX98373_R20E2_LIMITER_EN, 0x00},
{MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
{MAX98373_R20FF_GLOBAL_SHDN, 0x00},
{MAX98373_R21FF_REV_ID, 0x42},
};
static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
unsigned int format = 0;
unsigned int invert = 0;
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(component->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98373_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98373_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98373_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98373_PCM_FORMAT_TDM_MODE0;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
return 0;
}
/* BCLKs per LRCLK */
static const int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
};
static int max98373_get_bclk_sel(int bclk)
{
int i;
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98373_set_clock(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98373->ch_size;
int value;
if (!max98373->tdm_mode) {
/* BCLK configuration */
value = max98373_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_CLK_SETUP_BSEL_MASK,
value);
}
return 0;
}
static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
max98373->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(component->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
break;
case 88200:
sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
break;
case 96000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
break;
default:
dev_err(component->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98373->regmap,
MAX98373_R2027_PCM_SR_SETUP_1,
MAX98373_PCM_SR_SET1_SR_MASK,
sampling_rate);
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_SR_MASK,
sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
if (max98373->interleave_mode &&
sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate - 3);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate);
return max98373_set_clock(component, params);
err:
return -EINVAL;
}
static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
int bsel = 0;
unsigned int chan_sz = 0;
unsigned int mask;
int x, slot_found;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98373->tdm_mode = false;
else
max98373->tdm_mode = true;
/* BCLK configuration */
bsel = max98373_get_bclk_sel(slots * slot_width);
if (bsel == 0) {
dev_err(component->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_CLK_SETUP_BSEL_MASK,
bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(component->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
slot_found = 0;
mask = rx_mask;
for (x = 0 ; x < 16 ; x++, mask >>= 1) {
if (mask & 0x1) {
if (slot_found == 0)
regmap_update_bits(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
else
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
x);
slot_found++;
if (slot_found > 1)
break;
}
}
/* Tx slot Hi-Z configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
~tx_mask & 0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
(~tx_mask & 0xFF00) >> 8);
return 0;
}
#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98373_dai_ops = {
.set_fmt = max98373_dai_set_fmt,
.hw_params = max98373_dai_hw_params,
.set_tdm_slot = max98373_dai_tdm_slot,
};
static bool max98373_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2000_SW_RESET:
case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
case MAX98373_R2010_IRQ_CTRL:
case MAX98373_R2014_THERM_WARN_THRESH
... MAX98373_R2018_THERM_FOLDBACK_EN:
case MAX98373_R201E_PIN_DRIVE_STRENGTH
... MAX98373_R2036_SOUNDWIRE_CTRL:
case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
... MAX98373_R2047_IV_SENSE_ADC_EN:
case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
case MAX98373_R2097_BDE_L1_THRESH
... MAX98373_R209B_BDE_THRESH_HYST:
case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
... MAX98373_R20FF_GLOBAL_SHDN:
case MAX98373_R21FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R20FF_GLOBAL_SHDN:
case MAX98373_R21FF_REV_ID:
return true;
default:
return false;
}
}
static struct snd_soc_dai_driver max98373_dai[] = {
{
.name = "max98373-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.ops = &max98373_dai_ops,
}
};
#ifdef CONFIG_PM_SLEEP
static int max98373_suspend(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
int i;
/* cache feedback register values before suspend */
for (i = 0; i < max98373->cache_num; i++)
regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
regcache_cache_only(max98373->regmap, true);
regcache_mark_dirty(max98373->regmap);
return 0;
}
static int max98373_resume(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
regcache_cache_only(max98373->regmap, false);
max98373_reset(max98373, dev);
regcache_sync(max98373->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98373_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
};
static const struct regmap_config max98373_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98373_R21FF_REV_ID,
.reg_defaults = max98373_reg,
.num_reg_defaults = ARRAY_SIZE(max98373_reg),
.readable_reg = max98373_readable_register,
.volatile_reg = max98373_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static int max98373_i2c_probe(struct i2c_client *i2c)
{
int ret = 0;
int reg = 0;
int i;
struct max98373_priv *max98373 = NULL;
max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
if (!max98373) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98373);
/* update interleave mode info */
if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
max98373->interleave_mode = true;
else
max98373->interleave_mode = false;
/* regmap initialization */
max98373->regmap = devm_regmap_init_i2c(i2c, &max98373_regmap);
if (IS_ERR(max98373->regmap)) {
ret = PTR_ERR(max98373->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
max98373->cache_num = ARRAY_SIZE(max98373_i2c_cache_reg);
max98373->cache = devm_kcalloc(&i2c->dev, max98373->cache_num,
sizeof(*max98373->cache),
GFP_KERNEL);
if (!max98373->cache) {
ret = -ENOMEM;
return ret;
}
for (i = 0; i < max98373->cache_num; i++)
max98373->cache[i].reg = max98373_i2c_cache_reg[i];
/* voltage/current slot & gpio configuration */
max98373_slot_config(&i2c->dev, max98373);
/* Power on device */
if (gpio_is_valid(max98373->reset_gpio)) {
ret = devm_gpio_request(&i2c->dev, max98373->reset_gpio,
"MAX98373_RESET");
if (ret) {
dev_err(&i2c->dev, "%s: Failed to request gpio %d\n",
__func__, max98373->reset_gpio);
return -EINVAL;
}
gpio_direction_output(max98373->reset_gpio, 0);
msleep(50);
gpio_direction_output(max98373->reset_gpio, 1);
msleep(20);
}
/* Check Revision ID */
ret = regmap_read(max98373->regmap,
MAX98373_R21FF_REV_ID, ®);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
/* codec registration */
ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
max98373_dai, ARRAY_SIZE(max98373_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static const struct i2c_device_id max98373_i2c_id[] = {
{ "max98373", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98373_of_match[] = {
{ .compatible = "maxim,max98373", },
{ }
};
MODULE_DEVICE_TABLE(of, max98373_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98373_acpi_match[] = {
{ "MX98373", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
#endif
static struct i2c_driver max98373_i2c_driver = {
.driver = {
.name = "max98373",
.of_match_table = of_match_ptr(max98373_of_match),
.acpi_match_table = ACPI_PTR(max98373_acpi_match),
.pm = &max98373_pm,
},
.probe = max98373_i2c_probe,
.id_table = max98373_i2c_id,
};
module_i2c_driver(max98373_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
MODULE_AUTHOR("Ryan Lee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/max98373-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8903.c -- WM8903 ALSA SoC Audio driver
*
* Copyright 2008-12 Wolfson Microelectronics
* Copyright 2011-2012 NVIDIA, Inc.
*
* Author: Mark Brown <[email protected]>
*
* TODO:
* - TDM mode configuration.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/gpio/driver.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/wm8903.h>
#include <trace/events/asoc.h>
#include "wm8903.h"
/* Register defaults at reset */
static const struct reg_default wm8903_reg_defaults[] = {
{ 4, 0x0018 }, /* R4 - Bias Control 0 */
{ 5, 0x0000 }, /* R5 - VMID Control 0 */
{ 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
{ 8, 0x0001 }, /* R8 - Analogue DAC 0 */
{ 10, 0x0001 }, /* R10 - Analogue ADC 0 */
{ 12, 0x0000 }, /* R12 - Power Management 0 */
{ 13, 0x0000 }, /* R13 - Power Management 1 */
{ 14, 0x0000 }, /* R14 - Power Management 2 */
{ 15, 0x0000 }, /* R15 - Power Management 3 */
{ 16, 0x0000 }, /* R16 - Power Management 4 */
{ 17, 0x0000 }, /* R17 - Power Management 5 */
{ 18, 0x0000 }, /* R18 - Power Management 6 */
{ 20, 0x0400 }, /* R20 - Clock Rates 0 */
{ 21, 0x0D07 }, /* R21 - Clock Rates 1 */
{ 22, 0x0000 }, /* R22 - Clock Rates 2 */
{ 24, 0x0050 }, /* R24 - Audio Interface 0 */
{ 25, 0x0242 }, /* R25 - Audio Interface 1 */
{ 26, 0x0008 }, /* R26 - Audio Interface 2 */
{ 27, 0x0022 }, /* R27 - Audio Interface 3 */
{ 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
{ 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
{ 32, 0x0000 }, /* R32 - DAC Digital 0 */
{ 33, 0x0000 }, /* R33 - DAC Digital 1 */
{ 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
{ 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
{ 38, 0x0000 }, /* R38 - ADC Digital 0 */
{ 39, 0x0073 }, /* R39 - Digital Microphone 0 */
{ 40, 0x09BF }, /* R40 - DRC 0 */
{ 41, 0x3241 }, /* R41 - DRC 1 */
{ 42, 0x0020 }, /* R42 - DRC 2 */
{ 43, 0x0000 }, /* R43 - DRC 3 */
{ 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
{ 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
{ 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
{ 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
{ 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
{ 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
{ 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
{ 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
{ 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
{ 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
{ 57, 0x002D }, /* R57 - Analogue OUT1 Left */
{ 58, 0x002D }, /* R58 - Analogue OUT1 Right */
{ 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
{ 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
{ 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
{ 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
{ 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
{ 67, 0x0010 }, /* R67 - DC Servo 0 */
{ 69, 0x00A4 }, /* R69 - DC Servo 2 */
{ 90, 0x0000 }, /* R90 - Analogue HP 0 */
{ 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
{ 98, 0x0000 }, /* R98 - Charge Pump 0 */
{ 104, 0x0000 }, /* R104 - Class W 0 */
{ 108, 0x0000 }, /* R108 - Write Sequencer 0 */
{ 109, 0x0000 }, /* R109 - Write Sequencer 1 */
{ 110, 0x0000 }, /* R110 - Write Sequencer 2 */
{ 111, 0x0000 }, /* R111 - Write Sequencer 3 */
{ 112, 0x0000 }, /* R112 - Write Sequencer 4 */
{ 114, 0x0000 }, /* R114 - Control Interface */
{ 116, 0x00A8 }, /* R116 - GPIO Control 1 */
{ 117, 0x00A8 }, /* R117 - GPIO Control 2 */
{ 118, 0x00A8 }, /* R118 - GPIO Control 3 */
{ 119, 0x0220 }, /* R119 - GPIO Control 4 */
{ 120, 0x01A0 }, /* R120 - GPIO Control 5 */
{ 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
{ 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
{ 126, 0x0000 }, /* R126 - Interrupt Control */
{ 129, 0x0000 }, /* R129 - Control Interface Test 1 */
{ 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
{ 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
{ 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
};
#define WM8903_NUM_SUPPLIES 4
static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = {
"AVDD",
"CPVDD",
"DBVDD",
"DCVDD",
};
struct wm8903_priv {
struct wm8903_platform_data *pdata;
struct device *dev;
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES];
int sysclk;
int irq;
struct mutex lock;
int fs;
int deemph;
int dcs_pending;
int dcs_cache[4];
/* Reference count */
int class_w_users;
struct snd_soc_jack *mic_jack;
int mic_det;
int mic_short;
int mic_last_report;
int mic_delay;
#ifdef CONFIG_GPIOLIB
struct gpio_chip gpio_chip;
#endif
};
static bool wm8903_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8903_SW_RESET_AND_ID:
case WM8903_REVISION_NUMBER:
case WM8903_BIAS_CONTROL_0:
case WM8903_VMID_CONTROL_0:
case WM8903_MIC_BIAS_CONTROL_0:
case WM8903_ANALOGUE_DAC_0:
case WM8903_ANALOGUE_ADC_0:
case WM8903_POWER_MANAGEMENT_0:
case WM8903_POWER_MANAGEMENT_1:
case WM8903_POWER_MANAGEMENT_2:
case WM8903_POWER_MANAGEMENT_3:
case WM8903_POWER_MANAGEMENT_4:
case WM8903_POWER_MANAGEMENT_5:
case WM8903_POWER_MANAGEMENT_6:
case WM8903_CLOCK_RATES_0:
case WM8903_CLOCK_RATES_1:
case WM8903_CLOCK_RATES_2:
case WM8903_AUDIO_INTERFACE_0:
case WM8903_AUDIO_INTERFACE_1:
case WM8903_AUDIO_INTERFACE_2:
case WM8903_AUDIO_INTERFACE_3:
case WM8903_DAC_DIGITAL_VOLUME_LEFT:
case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
case WM8903_DAC_DIGITAL_0:
case WM8903_DAC_DIGITAL_1:
case WM8903_ADC_DIGITAL_VOLUME_LEFT:
case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
case WM8903_ADC_DIGITAL_0:
case WM8903_DIGITAL_MICROPHONE_0:
case WM8903_DRC_0:
case WM8903_DRC_1:
case WM8903_DRC_2:
case WM8903_DRC_3:
case WM8903_ANALOGUE_LEFT_INPUT_0:
case WM8903_ANALOGUE_RIGHT_INPUT_0:
case WM8903_ANALOGUE_LEFT_INPUT_1:
case WM8903_ANALOGUE_RIGHT_INPUT_1:
case WM8903_ANALOGUE_LEFT_MIX_0:
case WM8903_ANALOGUE_RIGHT_MIX_0:
case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
case WM8903_ANALOGUE_OUT1_LEFT:
case WM8903_ANALOGUE_OUT1_RIGHT:
case WM8903_ANALOGUE_OUT2_LEFT:
case WM8903_ANALOGUE_OUT2_RIGHT:
case WM8903_ANALOGUE_OUT3_LEFT:
case WM8903_ANALOGUE_OUT3_RIGHT:
case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
case WM8903_DC_SERVO_0:
case WM8903_DC_SERVO_2:
case WM8903_DC_SERVO_READBACK_1:
case WM8903_DC_SERVO_READBACK_2:
case WM8903_DC_SERVO_READBACK_3:
case WM8903_DC_SERVO_READBACK_4:
case WM8903_ANALOGUE_HP_0:
case WM8903_ANALOGUE_LINEOUT_0:
case WM8903_CHARGE_PUMP_0:
case WM8903_CLASS_W_0:
case WM8903_WRITE_SEQUENCER_0:
case WM8903_WRITE_SEQUENCER_1:
case WM8903_WRITE_SEQUENCER_2:
case WM8903_WRITE_SEQUENCER_3:
case WM8903_WRITE_SEQUENCER_4:
case WM8903_CONTROL_INTERFACE:
case WM8903_GPIO_CONTROL_1:
case WM8903_GPIO_CONTROL_2:
case WM8903_GPIO_CONTROL_3:
case WM8903_GPIO_CONTROL_4:
case WM8903_GPIO_CONTROL_5:
case WM8903_INTERRUPT_STATUS_1:
case WM8903_INTERRUPT_STATUS_1_MASK:
case WM8903_INTERRUPT_POLARITY_1:
case WM8903_INTERRUPT_CONTROL:
case WM8903_CLOCK_RATE_TEST_4:
case WM8903_ANALOGUE_OUTPUT_BIAS_0:
return true;
default:
return false;
}
}
static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8903_SW_RESET_AND_ID:
case WM8903_REVISION_NUMBER:
case WM8903_INTERRUPT_STATUS_1:
case WM8903_WRITE_SEQUENCER_4:
case WM8903_DC_SERVO_READBACK_1:
case WM8903_DC_SERVO_READBACK_2:
case WM8903_DC_SERVO_READBACK_3:
case WM8903_DC_SERVO_READBACK_4:
return true;
default:
return false;
}
}
static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
WARN_ON(event != SND_SOC_DAPM_POST_PMU);
mdelay(4);
return 0;
}
static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
wm8903->dcs_pending |= 1 << w->shift;
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,
1 << w->shift, 0);
break;
}
return 0;
}
#define WM8903_DCS_MODE_WRITE_STOP 0
#define WM8903_DCS_MODE_START_STOP 2
static void wm8903_seq_notifier(struct snd_soc_component *component,
enum snd_soc_dapm_type event, int subseq)
{
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
int i, val;
/* Complete any pending DC servo starts */
if (wm8903->dcs_pending) {
dev_dbg(component->dev, "Starting DC servo for %x\n",
wm8903->dcs_pending);
/* If we've no cached values then we need to do startup */
for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
if (!(wm8903->dcs_pending & (1 << i)))
continue;
if (wm8903->dcs_cache[i]) {
dev_dbg(component->dev,
"Restore DC servo %d value %x\n",
3 - i, wm8903->dcs_cache[i]);
snd_soc_component_write(component, WM8903_DC_SERVO_4 + i,
wm8903->dcs_cache[i] & 0xff);
} else {
dev_dbg(component->dev,
"Calibrate DC servo %d\n", 3 - i);
dcs_mode = WM8903_DCS_MODE_START_STOP;
}
}
/* Don't trust the cache for analogue */
if (wm8903->class_w_users)
dcs_mode = WM8903_DCS_MODE_START_STOP;
snd_soc_component_update_bits(component, WM8903_DC_SERVO_2,
WM8903_DCS_MODE_MASK, dcs_mode);
snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,
WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
switch (dcs_mode) {
case WM8903_DCS_MODE_WRITE_STOP:
break;
case WM8903_DCS_MODE_START_STOP:
msleep(270);
/* Cache the measured offsets for digital */
if (wm8903->class_w_users)
break;
for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
if (!(wm8903->dcs_pending & (1 << i)))
continue;
val = snd_soc_component_read(component,
WM8903_DC_SERVO_READBACK_1 + i);
dev_dbg(component->dev, "DC servo %d: %x\n",
3 - i, val);
wm8903->dcs_cache[i] = val;
}
break;
default:
pr_warn("DCS mode %d delay not set\n", dcs_mode);
break;
}
wm8903->dcs_pending = 0;
}
}
/*
* When used with DAC outputs only the WM8903 charge pump supports
* operation in class W mode, providing very low power consumption
* when used with digital sources. Enable and disable this mode
* automatically depending on the mixer configuration.
*
* All the relevant controls are simple switches.
*/
static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
u16 reg;
int ret;
reg = snd_soc_component_read(component, WM8903_CLASS_W_0);
/* Turn it off if we're about to enable bypass */
if (ucontrol->value.integer.value[0]) {
if (wm8903->class_w_users == 0) {
dev_dbg(component->dev, "Disabling Class W\n");
snd_soc_component_write(component, WM8903_CLASS_W_0, reg &
~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
}
wm8903->class_w_users++;
}
/* Implement the change */
ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
/* If we've just disabled the last bypass path turn Class W on */
if (!ucontrol->value.integer.value[0]) {
if (wm8903->class_w_users == 1) {
dev_dbg(component->dev, "Enabling Class W\n");
snd_soc_component_write(component, WM8903_CLASS_W_0, reg |
WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
}
wm8903->class_w_users--;
}
dev_dbg(component->dev, "Bypass use count now %d\n",
wm8903->class_w_users);
return ret;
}
#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
snd_soc_dapm_get_volsw, wm8903_class_w_put)
static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
static int wm8903_set_deemph(struct snd_soc_component *component)
{
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
int val, i, best;
/* If we're using deemphasis select the nearest available sample
* rate.
*/
if (wm8903->deemph) {
best = 1;
for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
if (abs(wm8903_deemph[i] - wm8903->fs) <
abs(wm8903_deemph[best] - wm8903->fs))
best = i;
}
val = best << WM8903_DEEMPH_SHIFT;
} else {
best = 0;
val = 0;
}
dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n",
best, wm8903_deemph[best]);
return snd_soc_component_update_bits(component, WM8903_DAC_DIGITAL_1,
WM8903_DEEMPH_MASK, val);
}
static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = wm8903->deemph;
return 0;
}
static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
unsigned int deemph = ucontrol->value.integer.value[0];
int ret = 0;
if (deemph > 1)
return -EINVAL;
mutex_lock(&wm8903->lock);
if (wm8903->deemph != deemph) {
wm8903->deemph = deemph;
wm8903_set_deemph(component);
ret = 1;
}
mutex_unlock(&wm8903->lock);
return ret;
}
/* ALSA can only do steps of .01dB */
static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
static const char *hpf_mode_text[] = {
"Hi-fi", "Voice 1", "Voice 2", "Voice 3"
};
static SOC_ENUM_SINGLE_DECL(hpf_mode,
WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
static const char *osr_text[] = {
"Low power", "High performance"
};
static SOC_ENUM_SINGLE_DECL(adc_osr,
WM8903_ANALOGUE_ADC_0, 0, osr_text);
static SOC_ENUM_SINGLE_DECL(dac_osr,
WM8903_DAC_DIGITAL_1, 0, osr_text);
static const char *drc_slope_text[] = {
"1", "1/2", "1/4", "1/8", "1/16", "0"
};
static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
WM8903_DRC_2, 3, drc_slope_text);
static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
WM8903_DRC_2, 0, drc_slope_text);
static const char *drc_attack_text[] = {
"instantaneous",
"363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
"46.4ms", "92.8ms", "185.6ms"
};
static SOC_ENUM_SINGLE_DECL(drc_attack,
WM8903_DRC_1, 12, drc_attack_text);
static const char *drc_decay_text[] = {
"186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
"23.87s", "47.56s"
};
static SOC_ENUM_SINGLE_DECL(drc_decay,
WM8903_DRC_1, 8, drc_decay_text);
static const char *drc_ff_delay_text[] = {
"5 samples", "9 samples"
};
static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
WM8903_DRC_0, 5, drc_ff_delay_text);
static const char *drc_qr_decay_text[] = {
"0.725ms", "1.45ms", "5.8ms"
};
static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
WM8903_DRC_1, 4, drc_qr_decay_text);
static const char *drc_smoothing_text[] = {
"Low", "Medium", "High"
};
static SOC_ENUM_SINGLE_DECL(drc_smoothing,
WM8903_DRC_0, 11, drc_smoothing_text);
static const char *soft_mute_text[] = {
"Fast (fs/2)", "Slow (fs/32)"
};
static SOC_ENUM_SINGLE_DECL(soft_mute,
WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
static const char *mute_mode_text[] = {
"Hard", "Soft"
};
static SOC_ENUM_SINGLE_DECL(mute_mode,
WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
static const char *companding_text[] = {
"ulaw", "alaw"
};
static SOC_ENUM_SINGLE_DECL(dac_companding,
WM8903_AUDIO_INTERFACE_0, 0, companding_text);
static SOC_ENUM_SINGLE_DECL(adc_companding,
WM8903_AUDIO_INTERFACE_0, 2, companding_text);
static const char *input_mode_text[] = {
"Single-Ended", "Differential Line", "Differential Mic"
};
static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
static const char *linput_mux_text[] = {
"IN1L", "IN2L", "IN3L"
};
static SOC_ENUM_SINGLE_DECL(linput_enum,
WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
static const char *rinput_mux_text[] = {
"IN1R", "IN2R", "IN3R"
};
static SOC_ENUM_SINGLE_DECL(rinput_enum,
WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
static const char *sidetone_text[] = {
"None", "Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
WM8903_DAC_DIGITAL_0, 2, sidetone_text);
static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
WM8903_DAC_DIGITAL_0, 0, sidetone_text);
static const char *adcinput_text[] = {
"ADC", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(adcinput_enum,
WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
static const char *aif_text[] = {
"Left", "Right"
};
static SOC_ENUM_SINGLE_DECL(lcapture_enum,
WM8903_AUDIO_INTERFACE_0, 7, aif_text);
static SOC_ENUM_SINGLE_DECL(rcapture_enum,
WM8903_AUDIO_INTERFACE_0, 6, aif_text);
static SOC_ENUM_SINGLE_DECL(lplay_enum,
WM8903_AUDIO_INTERFACE_0, 5, aif_text);
static SOC_ENUM_SINGLE_DECL(rplay_enum,
WM8903_AUDIO_INTERFACE_0, 4, aif_text);
static const struct snd_kcontrol_new wm8903_snd_controls[] = {
/* Input PGAs - No TLV since the scale depends on PGA mode */
SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
7, 1, 1),
SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
0, 31, 0),
SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
6, 1, 0),
SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
7, 1, 1),
SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
0, 31, 0),
SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
6, 1, 0),
/* ADCs */
SOC_ENUM("ADC OSR", adc_osr),
SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
SOC_ENUM("HPF Mode", hpf_mode),
SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
drc_tlv_thresh),
SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
SOC_ENUM("DRC Attack Rate", drc_attack),
SOC_ENUM("DRC Decay Rate", drc_decay),
SOC_ENUM("DRC FF Delay", drc_ff_delay),
SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
SOC_ENUM("ADC Companding Mode", adc_companding),
SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
12, 0, digital_sidetone_tlv),
/* DAC */
SOC_ENUM("DAC OSR", dac_osr),
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
SOC_ENUM("DAC Soft Mute Rate", soft_mute),
SOC_ENUM("DAC Mute Mode", mute_mode),
SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
SOC_ENUM("DAC Companding Mode", dac_companding),
SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
dac_boost_tlv),
SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
wm8903_get_deemph, wm8903_put_deemph),
/* Headphones */
SOC_DOUBLE_R("Headphone Switch",
WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
8, 1, 1),
SOC_DOUBLE_R("Headphone ZC Switch",
WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
6, 1, 0),
SOC_DOUBLE_R_TLV("Headphone Volume",
WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
0, 63, 0, out_tlv),
/* Line out */
SOC_DOUBLE_R("Line Out Switch",
WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
8, 1, 1),
SOC_DOUBLE_R("Line Out ZC Switch",
WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
6, 1, 0),
SOC_DOUBLE_R_TLV("Line Out Volume",
WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
0, 63, 0, out_tlv),
/* Speaker */
SOC_DOUBLE_R("Speaker Switch",
WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
SOC_DOUBLE_R("Speaker ZC Switch",
WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Volume",
WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
0, 63, 0, out_tlv),
};
static const struct snd_kcontrol_new linput_mode_mux =
SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
static const struct snd_kcontrol_new rinput_mode_mux =
SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
static const struct snd_kcontrol_new linput_mux =
SOC_DAPM_ENUM("Left Input Mux", linput_enum);
static const struct snd_kcontrol_new linput_inv_mux =
SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
static const struct snd_kcontrol_new rinput_mux =
SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
static const struct snd_kcontrol_new rinput_inv_mux =
SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
static const struct snd_kcontrol_new lsidetone_mux =
SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
static const struct snd_kcontrol_new rsidetone_mux =
SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
static const struct snd_kcontrol_new adcinput_mux =
SOC_DAPM_ENUM("ADC Input", adcinput_enum);
static const struct snd_kcontrol_new lcapture_mux =
SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
static const struct snd_kcontrol_new rcapture_mux =
SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
static const struct snd_kcontrol_new lplay_mux =
SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
static const struct snd_kcontrol_new rplay_mux =
SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
static const struct snd_kcontrol_new left_output_mixer[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
};
static const struct snd_kcontrol_new right_output_mixer[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
};
static const struct snd_kcontrol_new left_speaker_mixer[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
0, 1, 0),
};
static const struct snd_kcontrol_new right_speaker_mixer[] = {
SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
1, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
0, 1, 0),
};
static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1L"),
SND_SOC_DAPM_INPUT("IN1R"),
SND_SOC_DAPM_INPUT("IN2L"),
SND_SOC_DAPM_INPUT("IN2R"),
SND_SOC_DAPM_INPUT("IN3L"),
SND_SOC_DAPM_INPUT("IN3R"),
SND_SOC_DAPM_INPUT("DMICDAT"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LINEOUTL"),
SND_SOC_DAPM_OUTPUT("LINEOUTR"),
SND_SOC_DAPM_OUTPUT("LOP"),
SND_SOC_DAPM_OUTPUT("LON"),
SND_SOC_DAPM_OUTPUT("ROP"),
SND_SOC_DAPM_OUTPUT("RON"),
SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
&linput_inv_mux),
SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
&rinput_inv_mux),
SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
left_output_mixer, ARRAY_SIZE(left_output_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
right_output_mixer, ARRAY_SIZE(right_output_mixer)),
SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
1, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
NULL, 0),
SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
};
static const struct snd_soc_dapm_route wm8903_intercon[] = {
{ "CLK_DSP", NULL, "CLK_SYS" },
{ "MICBIAS", NULL, "CLK_SYS" },
{ "HPL_DCS", NULL, "CLK_SYS" },
{ "HPR_DCS", NULL, "CLK_SYS" },
{ "LINEOUTL_DCS", NULL, "CLK_SYS" },
{ "LINEOUTR_DCS", NULL, "CLK_SYS" },
{ "Left Input Mux", "IN1L", "IN1L" },
{ "Left Input Mux", "IN2L", "IN2L" },
{ "Left Input Mux", "IN3L", "IN3L" },
{ "Left Input Inverting Mux", "IN1L", "IN1L" },
{ "Left Input Inverting Mux", "IN2L", "IN2L" },
{ "Left Input Inverting Mux", "IN3L", "IN3L" },
{ "Right Input Mux", "IN1R", "IN1R" },
{ "Right Input Mux", "IN2R", "IN2R" },
{ "Right Input Mux", "IN3R", "IN3R" },
{ "Right Input Inverting Mux", "IN1R", "IN1R" },
{ "Right Input Inverting Mux", "IN2R", "IN2R" },
{ "Right Input Inverting Mux", "IN3R", "IN3R" },
{ "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
{ "Left Input Mode Mux", "Differential Line",
"Left Input Mux" },
{ "Left Input Mode Mux", "Differential Line",
"Left Input Inverting Mux" },
{ "Left Input Mode Mux", "Differential Mic",
"Left Input Mux" },
{ "Left Input Mode Mux", "Differential Mic",
"Left Input Inverting Mux" },
{ "Right Input Mode Mux", "Single-Ended",
"Right Input Inverting Mux" },
{ "Right Input Mode Mux", "Differential Line",
"Right Input Mux" },
{ "Right Input Mode Mux", "Differential Line",
"Right Input Inverting Mux" },
{ "Right Input Mode Mux", "Differential Mic",
"Right Input Mux" },
{ "Right Input Mode Mux", "Differential Mic",
"Right Input Inverting Mux" },
{ "Left Input PGA", NULL, "Left Input Mode Mux" },
{ "Right Input PGA", NULL, "Right Input Mode Mux" },
{ "Left ADC Input", "ADC", "Left Input PGA" },
{ "Left ADC Input", "DMIC", "DMICDAT" },
{ "Right ADC Input", "ADC", "Right Input PGA" },
{ "Right ADC Input", "DMIC", "DMICDAT" },
{ "Left Capture Mux", "Left", "ADCL" },
{ "Left Capture Mux", "Right", "ADCR" },
{ "Right Capture Mux", "Left", "ADCL" },
{ "Right Capture Mux", "Right", "ADCR" },
{ "AIFTXL", NULL, "Left Capture Mux" },
{ "AIFTXR", NULL, "Right Capture Mux" },
{ "ADCL", NULL, "Left ADC Input" },
{ "ADCL", NULL, "CLK_DSP" },
{ "ADCR", NULL, "Right ADC Input" },
{ "ADCR", NULL, "CLK_DSP" },
{ "Left Playback Mux", "Left", "AIFRXL" },
{ "Left Playback Mux", "Right", "AIFRXR" },
{ "Right Playback Mux", "Left", "AIFRXL" },
{ "Right Playback Mux", "Right", "AIFRXR" },
{ "DACL Sidetone", "Left", "ADCL" },
{ "DACL Sidetone", "Right", "ADCR" },
{ "DACR Sidetone", "Left", "ADCL" },
{ "DACR Sidetone", "Right", "ADCR" },
{ "DACL", NULL, "Left Playback Mux" },
{ "DACL", NULL, "DACL Sidetone" },
{ "DACL", NULL, "CLK_DSP" },
{ "DACR", NULL, "Right Playback Mux" },
{ "DACR", NULL, "DACR Sidetone" },
{ "DACR", NULL, "CLK_DSP" },
{ "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
{ "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
{ "Left Output Mixer", "DACL Switch", "DACL" },
{ "Left Output Mixer", "DACR Switch", "DACR" },
{ "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
{ "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
{ "Right Output Mixer", "DACL Switch", "DACL" },
{ "Right Output Mixer", "DACR Switch", "DACR" },
{ "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
{ "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
{ "Left Speaker Mixer", "DACL Switch", "DACL" },
{ "Left Speaker Mixer", "DACR Switch", "DACR" },
{ "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
{ "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
{ "Right Speaker Mixer", "DACL Switch", "DACL" },
{ "Right Speaker Mixer", "DACR Switch", "DACR" },
{ "Left Line Output PGA", NULL, "Left Output Mixer" },
{ "Right Line Output PGA", NULL, "Right Output Mixer" },
{ "Left Headphone Output PGA", NULL, "Left Output Mixer" },
{ "Right Headphone Output PGA", NULL, "Right Output Mixer" },
{ "Left Speaker PGA", NULL, "Left Speaker Mixer" },
{ "Right Speaker PGA", NULL, "Right Speaker Mixer" },
{ "HPL_ENA", NULL, "Left Headphone Output PGA" },
{ "HPR_ENA", NULL, "Right Headphone Output PGA" },
{ "HPL_ENA_DLY", NULL, "HPL_ENA" },
{ "HPR_ENA_DLY", NULL, "HPR_ENA" },
{ "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
{ "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
{ "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
{ "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
{ "HPL_DCS", NULL, "DCS Master" },
{ "HPR_DCS", NULL, "DCS Master" },
{ "LINEOUTL_DCS", NULL, "DCS Master" },
{ "LINEOUTR_DCS", NULL, "DCS Master" },
{ "HPL_DCS", NULL, "HPL_ENA_DLY" },
{ "HPR_DCS", NULL, "HPR_ENA_DLY" },
{ "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
{ "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
{ "HPL_ENA_OUTP", NULL, "HPL_DCS" },
{ "HPR_ENA_OUTP", NULL, "HPR_DCS" },
{ "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
{ "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
{ "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
{ "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
{ "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
{ "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
{ "HPOUTL", NULL, "HPL_RMV_SHORT" },
{ "HPOUTR", NULL, "HPR_RMV_SHORT" },
{ "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
{ "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
{ "LOP", NULL, "Left Speaker PGA" },
{ "LON", NULL, "Left Speaker PGA" },
{ "ROP", NULL, "Right Speaker PGA" },
{ "RON", NULL, "Right Speaker PGA" },
{ "Charge Pump", NULL, "CLK_DSP" },
{ "Left Headphone Output PGA", NULL, "Charge Pump" },
{ "Right Headphone Output PGA", NULL, "Charge Pump" },
{ "Left Line Output PGA", NULL, "Charge Pump" },
{ "Right Line Output PGA", NULL, "Charge Pump" },
};
static int wm8903_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_RES_MASK,
WM8903_VMID_RES_50K);
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
WM8903_POBCTRL | WM8903_ISEL_MASK |
WM8903_STARTUP_BIAS_ENA |
WM8903_BIAS_ENA,
WM8903_POBCTRL |
(2 << WM8903_ISEL_SHIFT) |
WM8903_STARTUP_BIAS_ENA);
snd_soc_component_update_bits(component,
WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
WM8903_SPK_DISCHARGE,
WM8903_SPK_DISCHARGE);
msleep(33);
snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,
WM8903_SPKL_ENA | WM8903_SPKR_ENA,
WM8903_SPKL_ENA | WM8903_SPKR_ENA);
snd_soc_component_update_bits(component,
WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
WM8903_SPK_DISCHARGE, 0);
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_TIE_ENA |
WM8903_BUFIO_ENA |
WM8903_VMID_IO_ENA |
WM8903_VMID_SOFT_MASK |
WM8903_VMID_RES_MASK |
WM8903_VMID_BUF_ENA,
WM8903_VMID_TIE_ENA |
WM8903_BUFIO_ENA |
WM8903_VMID_IO_ENA |
(2 << WM8903_VMID_SOFT_SHIFT) |
WM8903_VMID_RES_250K |
WM8903_VMID_BUF_ENA);
msleep(129);
snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,
WM8903_SPKL_ENA | WM8903_SPKR_ENA,
0);
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_SOFT_MASK, 0);
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_RES_MASK,
WM8903_VMID_RES_50K);
snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
WM8903_BIAS_ENA | WM8903_POBCTRL,
WM8903_BIAS_ENA);
/* By default no bypass paths are enabled so
* enable Class W support.
*/
dev_dbg(component->dev, "Enabling Class W\n");
snd_soc_component_update_bits(component, WM8903_CLASS_W_0,
WM8903_CP_DYN_FREQ |
WM8903_CP_DYN_V,
WM8903_CP_DYN_FREQ |
WM8903_CP_DYN_V);
}
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_RES_MASK,
WM8903_VMID_RES_250K);
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
WM8903_BIAS_ENA, 0);
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_SOFT_MASK,
2 << WM8903_VMID_SOFT_SHIFT);
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_BUF_ENA, 0);
msleep(290);
snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
WM8903_VMID_SOFT_MASK |
WM8903_VMID_BUF_ENA, 0);
snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
WM8903_STARTUP_BIAS_ENA, 0);
break;
}
return 0;
}
static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
wm8903->sysclk = freq;
return 0;
}
static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);
aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBS_CFM:
aif1 |= WM8903_LRCLK_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
aif1 |= WM8903_BCLK_DIR;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
aif1 |= 0x3;
break;
case SND_SOC_DAIFMT_DSP_B:
aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_I2S:
aif1 |= 0x2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
aif1 |= 0x1;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
/* Clock inversion */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/* frame inversion not valid for DSP modes */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8903_AIF_BCLK_INV;
break;
default:
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_LEFT_J:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aif1 |= WM8903_AIF_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aif1 |= WM8903_AIF_LRCLK_INV;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);
return 0;
}
static int wm8903_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
u16 reg;
reg = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);
if (mute)
reg |= WM8903_DAC_MUTE;
else
reg &= ~WM8903_DAC_MUTE;
snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg);
return 0;
}
/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
* for optimal performance so we list the lower rates first and match
* on the last match we find. */
static struct {
int div;
int rate;
int mode;
int mclk_div;
} clk_sys_ratios[] = {
{ 64, 0x0, 0x0, 1 },
{ 68, 0x0, 0x1, 1 },
{ 125, 0x0, 0x2, 1 },
{ 128, 0x1, 0x0, 1 },
{ 136, 0x1, 0x1, 1 },
{ 192, 0x2, 0x0, 1 },
{ 204, 0x2, 0x1, 1 },
{ 64, 0x0, 0x0, 2 },
{ 68, 0x0, 0x1, 2 },
{ 125, 0x0, 0x2, 2 },
{ 128, 0x1, 0x0, 2 },
{ 136, 0x1, 0x1, 2 },
{ 192, 0x2, 0x0, 2 },
{ 204, 0x2, 0x1, 2 },
{ 250, 0x2, 0x2, 1 },
{ 256, 0x3, 0x0, 1 },
{ 272, 0x3, 0x1, 1 },
{ 384, 0x4, 0x0, 1 },
{ 408, 0x4, 0x1, 1 },
{ 375, 0x4, 0x2, 1 },
{ 512, 0x5, 0x0, 1 },
{ 544, 0x5, 0x1, 1 },
{ 500, 0x5, 0x2, 1 },
{ 768, 0x6, 0x0, 1 },
{ 816, 0x6, 0x1, 1 },
{ 750, 0x6, 0x2, 1 },
{ 1024, 0x7, 0x0, 1 },
{ 1088, 0x7, 0x1, 1 },
{ 1000, 0x7, 0x2, 1 },
{ 1408, 0x8, 0x0, 1 },
{ 1496, 0x8, 0x1, 1 },
{ 1536, 0x9, 0x0, 1 },
{ 1632, 0x9, 0x1, 1 },
{ 1500, 0x9, 0x2, 1 },
{ 250, 0x2, 0x2, 2 },
{ 256, 0x3, 0x0, 2 },
{ 272, 0x3, 0x1, 2 },
{ 384, 0x4, 0x0, 2 },
{ 408, 0x4, 0x1, 2 },
{ 375, 0x4, 0x2, 2 },
{ 512, 0x5, 0x0, 2 },
{ 544, 0x5, 0x1, 2 },
{ 500, 0x5, 0x2, 2 },
{ 768, 0x6, 0x0, 2 },
{ 816, 0x6, 0x1, 2 },
{ 750, 0x6, 0x2, 2 },
{ 1024, 0x7, 0x0, 2 },
{ 1088, 0x7, 0x1, 2 },
{ 1000, 0x7, 0x2, 2 },
{ 1408, 0x8, 0x0, 2 },
{ 1496, 0x8, 0x1, 2 },
{ 1536, 0x9, 0x0, 2 },
{ 1632, 0x9, 0x1, 2 },
{ 1500, 0x9, 0x2, 2 },
};
/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
static struct {
int ratio;
int div;
} bclk_divs[] = {
{ 10, 0 },
{ 20, 2 },
{ 30, 3 },
{ 40, 4 },
{ 50, 5 },
{ 60, 7 },
{ 80, 8 },
{ 100, 9 },
{ 120, 11 },
{ 160, 12 },
{ 200, 13 },
{ 220, 14 },
{ 240, 15 },
{ 300, 17 },
{ 320, 18 },
{ 440, 19 },
{ 480, 20 },
};
/* Sample rates for DSP */
static struct {
int rate;
int value;
} sample_rates[] = {
{ 8000, 0 },
{ 11025, 1 },
{ 12000, 2 },
{ 16000, 3 },
{ 22050, 4 },
{ 24000, 5 },
{ 32000, 6 },
{ 44100, 7 },
{ 48000, 8 },
{ 88200, 9 },
{ 96000, 10 },
{ 0, 0 },
};
static int wm8903_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
int fs = params_rate(params);
int bclk;
int bclk_div;
int i;
int dsp_config;
int clk_config;
int best_val;
int cur_val;
int clk_sys;
u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);
u16 aif2 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_2);
u16 aif3 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_3);
u16 clock0 = snd_soc_component_read(component, WM8903_CLOCK_RATES_0);
u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1);
u16 dac_digital1 = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);
/* Enable sloping stopband filter for low sample rates */
if (fs <= 24000)
dac_digital1 |= WM8903_DAC_SB_FILT;
else
dac_digital1 &= ~WM8903_DAC_SB_FILT;
/* Configure sample rate logic for DSP - choose nearest rate */
dsp_config = 0;
best_val = abs(sample_rates[dsp_config].rate - fs);
for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
cur_val = abs(sample_rates[i].rate - fs);
if (cur_val <= best_val) {
dsp_config = i;
best_val = cur_val;
}
}
dev_dbg(component->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
clock1 &= ~WM8903_SAMPLE_RATE_MASK;
clock1 |= sample_rates[dsp_config].value;
aif1 &= ~WM8903_AIF_WL_MASK;
bclk = 2 * fs;
switch (params_width(params)) {
case 16:
bclk *= 16;
break;
case 20:
bclk *= 20;
aif1 |= 0x4;
break;
case 24:
bclk *= 24;
aif1 |= 0x8;
break;
case 32:
bclk *= 32;
aif1 |= 0xc;
break;
default:
return -EINVAL;
}
dev_dbg(component->dev, "MCLK = %dHz, target sample rate = %dHz\n",
wm8903->sysclk, fs);
/* We may not have an MCLK which allows us to generate exactly
* the clock we want, particularly with USB derived inputs, so
* approximate.
*/
clk_config = 0;
best_val = abs((wm8903->sysclk /
(clk_sys_ratios[0].mclk_div *
clk_sys_ratios[0].div)) - fs);
for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
cur_val = abs((wm8903->sysclk /
(clk_sys_ratios[i].mclk_div *
clk_sys_ratios[i].div)) - fs);
if (cur_val <= best_val) {
clk_config = i;
best_val = cur_val;
}
}
if (clk_sys_ratios[clk_config].mclk_div == 2) {
clock0 |= WM8903_MCLKDIV2;
clk_sys = wm8903->sysclk / 2;
} else {
clock0 &= ~WM8903_MCLKDIV2;
clk_sys = wm8903->sysclk;
}
clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
WM8903_CLK_SYS_MODE_MASK);
clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
dev_dbg(component->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
clk_sys_ratios[clk_config].rate,
clk_sys_ratios[clk_config].mode,
clk_sys_ratios[clk_config].div);
dev_dbg(component->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
/* We may not get quite the right frequency if using
* approximate clocks so look for the closest match that is
* higher than the target (we need to ensure that there enough
* BCLKs to clock out the samples).
*/
bclk_div = 0;
i = 1;
while (i < ARRAY_SIZE(bclk_divs)) {
cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
if (cur_val < 0) /* BCLK table is sorted */
break;
bclk_div = i;
i++;
}
aif2 &= ~WM8903_BCLK_DIV_MASK;
aif3 &= ~WM8903_LRCLK_RATE_MASK;
dev_dbg(component->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
bclk_divs[bclk_div].ratio / 10, bclk,
(clk_sys * 10) / bclk_divs[bclk_div].ratio);
aif2 |= bclk_divs[bclk_div].div;
aif3 |= bclk / fs;
wm8903->fs = params_rate(params);
wm8903_set_deemph(component);
snd_soc_component_write(component, WM8903_CLOCK_RATES_0, clock0);
snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1);
snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);
snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_2, aif2);
snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_3, aif3);
snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, dac_digital1);
return 0;
}
/**
* wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
*
* @component: WM8903 component
* @jack: jack to report detection events on
* @det: value to report for presence detection
* @shrt: value to report for short detection
*
* Enable microphone detection via IRQ on the WM8903. If GPIOs are
* being used to bring out signals to the processor then only platform
* data configuration is needed for WM8903 and processor GPIOs should
* be configured using snd_soc_jack_add_gpios() instead.
*
* The current threasholds for detection should be configured using
* micdet_cfg in the platform data. Using this function will force on
* the microphone bias for the device.
*/
int wm8903_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
int det, int shrt)
{
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
dev_dbg(component->dev, "Enabling microphone detection: %x %x\n",
det, shrt);
/* Store the configuration */
wm8903->mic_jack = jack;
wm8903->mic_det = det;
wm8903->mic_short = shrt;
/* Enable interrupts we've got a report configured for */
if (det)
irq_mask &= ~WM8903_MICDET_EINT;
if (shrt)
irq_mask &= ~WM8903_MICSHRT_EINT;
snd_soc_component_update_bits(component, WM8903_INTERRUPT_STATUS_1_MASK,
WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
irq_mask);
if (det || shrt) {
/* Enable mic detection, this may not have been set through
* platform data (eg, if the defaults are OK). */
snd_soc_component_update_bits(component, WM8903_WRITE_SEQUENCER_0,
WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,
WM8903_MICDET_ENA, WM8903_MICDET_ENA);
} else {
snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,
WM8903_MICDET_ENA, 0);
}
return 0;
}
EXPORT_SYMBOL_GPL(wm8903_mic_detect);
static irqreturn_t wm8903_irq(int irq, void *data)
{
struct wm8903_priv *wm8903 = data;
int mic_report, ret;
unsigned int int_val, mask, int_pol;
ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
&mask);
if (ret != 0) {
dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
return IRQ_NONE;
}
ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
if (ret != 0) {
dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
return IRQ_NONE;
}
int_val &= ~mask;
if (int_val & WM8903_WSEQ_BUSY_EINT) {
dev_warn(wm8903->dev, "Write sequencer done\n");
}
/*
* The rest is microphone jack detection. We need to manually
* invert the polarity of the interrupt after each event - to
* simplify the code keep track of the last state we reported
* and just invert the relevant bits in both the report and
* the polarity register.
*/
mic_report = wm8903->mic_last_report;
ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
&int_pol);
if (ret != 0) {
dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
ret);
return IRQ_HANDLED;
}
#ifndef CONFIG_SND_SOC_WM8903_MODULE
if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
trace_snd_soc_jack_irq(dev_name(wm8903->dev));
#endif
if (int_val & WM8903_MICSHRT_EINT) {
dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
mic_report ^= wm8903->mic_short;
int_pol ^= WM8903_MICSHRT_INV;
}
if (int_val & WM8903_MICDET_EINT) {
dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
mic_report ^= wm8903->mic_det;
int_pol ^= WM8903_MICDET_INV;
msleep(wm8903->mic_delay);
}
regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
snd_soc_jack_report(wm8903->mic_jack, mic_report,
wm8903->mic_short | wm8903->mic_det);
wm8903->mic_last_report = mic_report;
return IRQ_HANDLED;
}
#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000)
#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct snd_soc_dai_ops wm8903_dai_ops = {
.hw_params = wm8903_hw_params,
.mute_stream = wm8903_mute,
.set_fmt = wm8903_set_dai_fmt,
.set_sysclk = wm8903_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver wm8903_dai = {
.name = "wm8903-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8903_PLAYBACK_RATES,
.formats = WM8903_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8903_CAPTURE_RATES,
.formats = WM8903_FORMATS,
},
.ops = &wm8903_dai_ops,
.symmetric_rate = 1,
};
static int wm8903_resume(struct snd_soc_component *component)
{
struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
regcache_sync(wm8903->regmap);
return 0;
}
#ifdef CONFIG_GPIOLIB
static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
{
if (offset >= WM8903_NUM_GPIO)
return -EINVAL;
return 0;
}
static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
unsigned int mask, val;
int ret;
mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
WM8903_GP1_DIR;
ret = regmap_update_bits(wm8903->regmap,
WM8903_GPIO_CONTROL_1 + offset, mask, val);
if (ret < 0)
return ret;
return 0;
}
static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
unsigned int reg;
regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®);
return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT);
}
static int wm8903_gpio_direction_out(struct gpio_chip *chip,
unsigned offset, int value)
{
struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
unsigned int mask, val;
int ret;
mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
(value << WM8903_GP2_LVL_SHIFT);
ret = regmap_update_bits(wm8903->regmap,
WM8903_GPIO_CONTROL_1 + offset, mask, val);
if (ret < 0)
return ret;
return 0;
}
static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
WM8903_GP1_LVL_MASK,
!!value << WM8903_GP1_LVL_SHIFT);
}
static const struct gpio_chip wm8903_template_chip = {
.label = "wm8903",
.owner = THIS_MODULE,
.request = wm8903_gpio_request,
.direction_input = wm8903_gpio_direction_in,
.get = wm8903_gpio_get,
.direction_output = wm8903_gpio_direction_out,
.set = wm8903_gpio_set,
.can_sleep = 1,
};
static void wm8903_init_gpio(struct wm8903_priv *wm8903)
{
struct wm8903_platform_data *pdata = wm8903->pdata;
int ret;
wm8903->gpio_chip = wm8903_template_chip;
wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
wm8903->gpio_chip.parent = wm8903->dev;
if (pdata->gpio_base)
wm8903->gpio_chip.base = pdata->gpio_base;
else
wm8903->gpio_chip.base = -1;
ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903);
if (ret != 0)
dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
}
static void wm8903_free_gpio(struct wm8903_priv *wm8903)
{
gpiochip_remove(&wm8903->gpio_chip);
}
#else
static void wm8903_init_gpio(struct wm8903_priv *wm8903)
{
}
static void wm8903_free_gpio(struct wm8903_priv *wm8903)
{
}
#endif
static const struct snd_soc_component_driver soc_component_dev_wm8903 = {
.resume = wm8903_resume,
.set_bias_level = wm8903_set_bias_level,
.seq_notifier = wm8903_seq_notifier,
.controls = wm8903_snd_controls,
.num_controls = ARRAY_SIZE(wm8903_snd_controls),
.dapm_widgets = wm8903_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
.dapm_routes = wm8903_intercon,
.num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config wm8903_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = WM8903_MAX_REGISTER,
.volatile_reg = wm8903_volatile_register,
.readable_reg = wm8903_readable_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8903_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
};
static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
struct wm8903_platform_data *pdata)
{
struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
if (!irq_data) {
dev_err(&i2c->dev, "Invalid IRQ: %d\n",
i2c->irq);
return -EINVAL;
}
switch (irqd_get_trigger_type(irq_data)) {
case IRQ_TYPE_NONE:
default:
/*
* We assume the controller imposes no restrictions,
* so we are able to select active-high
*/
fallthrough;
case IRQ_TYPE_LEVEL_HIGH:
pdata->irq_active_low = false;
break;
case IRQ_TYPE_LEVEL_LOW:
pdata->irq_active_low = true;
break;
}
return 0;
}
static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
struct wm8903_platform_data *pdata)
{
const struct device_node *np = i2c->dev.of_node;
u32 val32;
int i;
if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
pdata->micdet_cfg = val32;
if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
pdata->micdet_delay = val32;
if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
/*
* In device tree: 0 means "write 0",
* 0xffffffff means "don't touch".
*
* In platform data: 0 means "don't touch",
* 0x8000 means "write 0".
*
* Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
*
* Convert from DT to pdata representation here,
* so no other code needs to change.
*/
for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
if (pdata->gpio_cfg[i] == 0) {
pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
} else if (pdata->gpio_cfg[i] == 0xffffffff) {
pdata->gpio_cfg[i] = 0;
} else if (pdata->gpio_cfg[i] > 0x7fff) {
dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
i, pdata->gpio_cfg[i]);
return -EINVAL;
}
}
}
return 0;
}
static int wm8903_i2c_probe(struct i2c_client *i2c)
{
struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct wm8903_priv *wm8903;
int trigger;
bool mic_gpio = false;
unsigned int val, irq_pol;
int ret, i;
wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL);
if (wm8903 == NULL)
return -ENOMEM;
mutex_init(&wm8903->lock);
wm8903->dev = &i2c->dev;
wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
if (IS_ERR(wm8903->regmap)) {
ret = PTR_ERR(wm8903->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
i2c_set_clientdata(i2c, wm8903);
/* If no platform data was supplied, create storage for defaults */
if (pdata) {
wm8903->pdata = pdata;
} else {
wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata),
GFP_KERNEL);
if (!wm8903->pdata)
return -ENOMEM;
if (i2c->irq) {
ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
if (ret != 0)
return ret;
}
if (i2c->dev.of_node) {
ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
if (ret != 0)
return ret;
}
}
pdata = wm8903->pdata;
for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++)
wm8903->supplies[i].supply = wm8903_supply_names[i];
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies),
wm8903->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies),
wm8903->supplies);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
goto err;
}
if (val != 0x8903) {
dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
ret = -ENODEV;
goto err;
}
ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
goto err;
}
dev_info(&i2c->dev, "WM8903 revision %c\n",
(val & WM8903_CHIP_REV_MASK) + 'A');
/* Reset the device */
regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
wm8903_init_gpio(wm8903);
/* Set up GPIO pin state, detect if any are MIC detect outputs */
for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
if ((!pdata->gpio_cfg[i]) ||
(pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
continue;
regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
pdata->gpio_cfg[i] & 0x7fff);
val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
>> WM8903_GP1_FN_SHIFT;
switch (val) {
case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
mic_gpio = true;
break;
default:
break;
}
}
/* Set up microphone detection */
regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
pdata->micdet_cfg);
/* Microphone detection needs the WSEQ clock */
if (pdata->micdet_cfg)
regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
/* If microphone detection is enabled by pdata but
* detected via IRQ then interrupts can be lost before
* the machine driver has set up microphone detection
* IRQs as the IRQs are clear on read. The detection
* will be enabled when the machine driver configures.
*/
WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
wm8903->mic_delay = pdata->micdet_delay;
if (i2c->irq) {
if (pdata->irq_active_low) {
trigger = IRQF_TRIGGER_LOW;
irq_pol = WM8903_IRQ_POL;
} else {
trigger = IRQF_TRIGGER_HIGH;
irq_pol = 0;
}
regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
WM8903_IRQ_POL, irq_pol);
ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
trigger | IRQF_ONESHOT,
"wm8903", wm8903);
if (ret != 0) {
dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
ret);
goto err;
}
/* Enable write sequencer interrupts */
regmap_update_bits(wm8903->regmap,
WM8903_INTERRUPT_STATUS_1_MASK,
WM8903_IM_WSEQ_BUSY_EINT, 0);
}
/* Latch volume update bits */
regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
WM8903_ADCVU, WM8903_ADCVU);
regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
WM8903_ADCVU, WM8903_ADCVU);
regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
WM8903_DACVU, WM8903_DACVU);
regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
WM8903_DACVU, WM8903_DACVU);
regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
WM8903_HPOUTVU, WM8903_HPOUTVU);
regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
WM8903_HPOUTVU, WM8903_HPOUTVU);
regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
WM8903_LINEOUTVU, WM8903_LINEOUTVU);
regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
WM8903_LINEOUTVU, WM8903_LINEOUTVU);
regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
WM8903_SPKVU, WM8903_SPKVU);
regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
WM8903_SPKVU, WM8903_SPKVU);
/* Enable DAC soft mute by default */
regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_component_dev_wm8903, &wm8903_dai, 1);
if (ret != 0)
goto err;
return 0;
err:
regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
wm8903->supplies);
return ret;
}
static void wm8903_i2c_remove(struct i2c_client *client)
{
struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
wm8903->supplies);
if (client->irq)
free_irq(client->irq, wm8903);
wm8903_free_gpio(wm8903);
}
static const struct of_device_id wm8903_of_match[] = {
{ .compatible = "wlf,wm8903", },
{},
};
MODULE_DEVICE_TABLE(of, wm8903_of_match);
static const struct i2c_device_id wm8903_i2c_id[] = {
{ "wm8903", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
static struct i2c_driver wm8903_i2c_driver = {
.driver = {
.name = "wm8903",
.of_match_table = wm8903_of_match,
},
.probe = wm8903_i2c_probe,
.remove = wm8903_i2c_remove,
.id_table = wm8903_i2c_id,
};
module_i2c_driver(wm8903_i2c_driver);
MODULE_DESCRIPTION("ASoC WM8903 driver");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/wm8903.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l45.c - CS35L45 ALSA SoC audio driver
//
// Copyright 2019-2022 Cirrus Logic, Inc.
//
// Author: James Schulman <[email protected]>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/firmware.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "cs35l45.h"
static bool cs35l45_check_cspl_mbox_sts(const enum cs35l45_cspl_mboxcmd cmd,
enum cs35l45_cspl_mboxstate sts)
{
switch (cmd) {
case CSPL_MBOX_CMD_NONE:
case CSPL_MBOX_CMD_UNKNOWN_CMD:
return true;
case CSPL_MBOX_CMD_PAUSE:
case CSPL_MBOX_CMD_OUT_OF_HIBERNATE:
return (sts == CSPL_MBOX_STS_PAUSED);
case CSPL_MBOX_CMD_RESUME:
return (sts == CSPL_MBOX_STS_RUNNING);
case CSPL_MBOX_CMD_REINIT:
return (sts == CSPL_MBOX_STS_RUNNING);
case CSPL_MBOX_CMD_STOP_PRE_REINIT:
return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT);
case CSPL_MBOX_CMD_HIBERNATE:
return (sts == CSPL_MBOX_STS_HIBERNATE);
default:
return false;
}
}
static int cs35l45_set_cspl_mbox_cmd(struct cs35l45_private *cs35l45,
struct regmap *regmap,
const enum cs35l45_cspl_mboxcmd cmd)
{
unsigned int sts = 0, i;
int ret;
if (!cs35l45->dsp.cs_dsp.running) {
dev_err(cs35l45->dev, "DSP not running\n");
return -EPERM;
}
// Set mailbox cmd
ret = regmap_write(regmap, CS35L45_DSP_VIRT1_MBOX_1, cmd);
if (ret < 0) {
if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
dev_err(cs35l45->dev, "Failed to write MBOX: %d\n", ret);
return ret;
}
// Read mailbox status and verify it is appropriate for the given cmd
for (i = 0; i < 5; i++) {
usleep_range(1000, 1100);
ret = regmap_read(regmap, CS35L45_DSP_MBOX_2, &sts);
if (ret < 0) {
dev_err(cs35l45->dev, "Failed to read MBOX STS: %d\n", ret);
continue;
}
if (!cs35l45_check_cspl_mbox_sts(cmd, sts))
dev_dbg(cs35l45->dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts);
else
return 0;
}
if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
dev_err(cs35l45->dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts);
return -ENOMSG;
}
static int cs35l45_global_en_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
dev_dbg(cs35l45->dev, "%s event : %x\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES,
CS35L45_GLOBAL_EN_MASK);
usleep_range(CS35L45_POST_GLOBAL_EN_US, CS35L45_POST_GLOBAL_EN_US + 100);
break;
case SND_SOC_DAPM_PRE_PMD:
usleep_range(CS35L45_PRE_GLOBAL_DIS_US, CS35L45_PRE_GLOBAL_DIS_US + 100);
regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0);
break;
default:
break;
}
return 0;
}
static int cs35l45_dsp_preload_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (cs35l45->dsp.cs_dsp.booted)
return 0;
return wm_adsp_early_event(w, kcontrol, event);
case SND_SOC_DAPM_POST_PMU:
if (cs35l45->dsp.cs_dsp.running)
return 0;
regmap_set_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL,
CS35L45_MEM_RDY_MASK);
return wm_adsp_event(w, kcontrol, event);
case SND_SOC_DAPM_PRE_PMD:
if (cs35l45->dsp.preloaded)
return 0;
if (cs35l45->dsp.cs_dsp.running) {
ret = wm_adsp_event(w, kcontrol, event);
if (ret)
return ret;
}
return wm_adsp_early_event(w, kcontrol, event);
default:
return 0;
}
}
static int cs35l45_dsp_audio_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
CSPL_MBOX_CMD_RESUME);
case SND_SOC_DAPM_PRE_PMD:
return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
CSPL_MBOX_CMD_PAUSE);
default:
return 0;
}
return 0;
}
static const char * const cs35l45_asp_tx_txt[] = {
"Zero", "ASP_RX1", "ASP_RX2",
"VMON", "IMON", "ERR_VOL",
"VDD_BATTMON", "VDD_BSTMON",
"DSP_TX1", "DSP_TX2",
"Interpolator", "IL_TARGET",
};
static const unsigned int cs35l45_asp_tx_val[] = {
CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2,
CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, CS35L45_PCM_SRC_ERR_VOL,
CS35L45_PCM_SRC_VDD_BATTMON, CS35L45_PCM_SRC_VDD_BSTMON,
CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2,
CS35L45_PCM_SRC_INTERPOLATOR, CS35L45_PCM_SRC_IL_TARGET,
};
static const struct soc_enum cs35l45_asp_tx_enums[] = {
SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX1_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
cs35l45_asp_tx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX2_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
cs35l45_asp_tx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX3_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
cs35l45_asp_tx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX4_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
cs35l45_asp_tx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX5_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
cs35l45_asp_tx_val),
};
static const char * const cs35l45_dsp_rx_txt[] = {
"Zero", "ASP_RX1", "ASP_RX2",
"VMON", "IMON", "ERR_VOL",
"CLASSH_TGT", "VDD_BATTMON",
"VDD_BSTMON", "TEMPMON",
};
static const unsigned int cs35l45_dsp_rx_val[] = {
CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2,
CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, CS35L45_PCM_SRC_ERR_VOL,
CS35L45_PCM_SRC_CLASSH_TGT, CS35L45_PCM_SRC_VDD_BATTMON,
CS35L45_PCM_SRC_VDD_BSTMON, CS35L45_PCM_SRC_TEMPMON,
};
static const struct soc_enum cs35l45_dsp_rx_enums[] = {
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX1_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX2_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX3_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX4_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX5_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX6_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX7_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX8_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
cs35l45_dsp_rx_val),
};
static const char * const cs35l45_dac_txt[] = {
"Zero", "ASP_RX1", "ASP_RX2", "DSP_TX1", "DSP_TX2"
};
static const unsigned int cs35l45_dac_val[] = {
CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2,
CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2
};
static const struct soc_enum cs35l45_dacpcm_enums[] = {
SOC_VALUE_ENUM_SINGLE(CS35L45_DACPCM1_INPUT, 0, CS35L45_PCM_SRC_MASK,
ARRAY_SIZE(cs35l45_dac_txt), cs35l45_dac_txt,
cs35l45_dac_val),
};
static const struct snd_kcontrol_new cs35l45_asp_muxes[] = {
SOC_DAPM_ENUM("ASP_TX1 Source", cs35l45_asp_tx_enums[0]),
SOC_DAPM_ENUM("ASP_TX2 Source", cs35l45_asp_tx_enums[1]),
SOC_DAPM_ENUM("ASP_TX3 Source", cs35l45_asp_tx_enums[2]),
SOC_DAPM_ENUM("ASP_TX4 Source", cs35l45_asp_tx_enums[3]),
SOC_DAPM_ENUM("ASP_TX5 Source", cs35l45_asp_tx_enums[4]),
};
static const struct snd_kcontrol_new cs35l45_dsp_muxes[] = {
SOC_DAPM_ENUM("DSP_RX1 Source", cs35l45_dsp_rx_enums[0]),
SOC_DAPM_ENUM("DSP_RX2 Source", cs35l45_dsp_rx_enums[1]),
SOC_DAPM_ENUM("DSP_RX3 Source", cs35l45_dsp_rx_enums[2]),
SOC_DAPM_ENUM("DSP_RX4 Source", cs35l45_dsp_rx_enums[3]),
SOC_DAPM_ENUM("DSP_RX5 Source", cs35l45_dsp_rx_enums[4]),
SOC_DAPM_ENUM("DSP_RX6 Source", cs35l45_dsp_rx_enums[5]),
SOC_DAPM_ENUM("DSP_RX7 Source", cs35l45_dsp_rx_enums[6]),
SOC_DAPM_ENUM("DSP_RX8 Source", cs35l45_dsp_rx_enums[7]),
};
static const struct snd_kcontrol_new cs35l45_dac_muxes[] = {
SOC_DAPM_ENUM("DACPCM Source", cs35l45_dacpcm_enums[0]),
};
static const struct snd_soc_dapm_widget cs35l45_dapm_widgets[] = {
SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
cs35l45_dsp_preload_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
cs35l45_dsp_audio_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("GLOBAL_EN", SND_SOC_NOPM, 0, 0,
cs35l45_global_en_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("ASP_EN", CS35L45_BLOCK_ENABLES2, CS35L45_ASP_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SIGGEN("VMON_SRC"),
SND_SOC_DAPM_SIGGEN("IMON_SRC"),
SND_SOC_DAPM_SIGGEN("VDD_BATTMON_SRC"),
SND_SOC_DAPM_SIGGEN("VDD_BSTMON_SRC"),
SND_SOC_DAPM_SIGGEN("ERR_VOL"),
SND_SOC_DAPM_SIGGEN("AMP_INTP"),
SND_SOC_DAPM_SIGGEN("IL_TARGET"),
SND_SOC_DAPM_ADC("VMON", NULL, CS35L45_BLOCK_ENABLES, CS35L45_VMON_EN_SHIFT, 0),
SND_SOC_DAPM_ADC("IMON", NULL, CS35L45_BLOCK_ENABLES, CS35L45_IMON_EN_SHIFT, 0),
SND_SOC_DAPM_ADC("VDD_BATTMON", NULL, CS35L45_BLOCK_ENABLES,
CS35L45_VDD_BATTMON_EN_SHIFT, 0),
SND_SOC_DAPM_ADC("VDD_BSTMON", NULL, CS35L45_BLOCK_ENABLES,
CS35L45_VDD_BSTMON_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASP_RX1", NULL, 0, CS35L45_ASP_ENABLES1, CS35L45_ASP_RX1_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_IN("ASP_RX2", NULL, 1, CS35L45_ASP_ENABLES1, CS35L45_ASP_RX2_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP_TX1", NULL, 0, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX1_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP_TX2", NULL, 1, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX2_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP_TX3", NULL, 2, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX3_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP_TX4", NULL, 3, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX4_EN_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("ASP_TX5", NULL, 3, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX5_EN_SHIFT, 0),
SND_SOC_DAPM_MUX("ASP_TX1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[0]),
SND_SOC_DAPM_MUX("ASP_TX2 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[1]),
SND_SOC_DAPM_MUX("ASP_TX3 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[2]),
SND_SOC_DAPM_MUX("ASP_TX4 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[3]),
SND_SOC_DAPM_MUX("ASP_TX5 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[4]),
SND_SOC_DAPM_MUX("DSP_RX1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[0]),
SND_SOC_DAPM_MUX("DSP_RX2 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[1]),
SND_SOC_DAPM_MUX("DSP_RX3 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[2]),
SND_SOC_DAPM_MUX("DSP_RX4 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[3]),
SND_SOC_DAPM_MUX("DSP_RX5 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[4]),
SND_SOC_DAPM_MUX("DSP_RX6 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[5]),
SND_SOC_DAPM_MUX("DSP_RX7 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[6]),
SND_SOC_DAPM_MUX("DSP_RX8 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[7]),
SND_SOC_DAPM_MUX("DACPCM Source", SND_SOC_NOPM, 0, 0, &cs35l45_dac_muxes[0]),
SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPK"),
};
#define CS35L45_ASP_MUX_ROUTE(name) \
{ name" Source", "ASP_RX1", "ASP_RX1" }, \
{ name" Source", "ASP_RX2", "ASP_RX2" }, \
{ name" Source", "DSP_TX1", "DSP1" }, \
{ name" Source", "DSP_TX2", "DSP1" }, \
{ name" Source", "VMON", "VMON" }, \
{ name" Source", "IMON", "IMON" }, \
{ name" Source", "ERR_VOL", "ERR_VOL" }, \
{ name" Source", "VDD_BATTMON", "VDD_BATTMON" }, \
{ name" Source", "VDD_BSTMON", "VDD_BSTMON" }, \
{ name" Source", "Interpolator", "AMP_INTP" }, \
{ name" Source", "IL_TARGET", "IL_TARGET" }
#define CS35L45_DSP_MUX_ROUTE(name) \
{ name" Source", "ASP_RX1", "ASP_RX1" }, \
{ name" Source", "ASP_RX2", "ASP_RX2" }
#define CS35L45_DAC_MUX_ROUTE(name) \
{ name" Source", "ASP_RX1", "ASP_RX1" }, \
{ name" Source", "ASP_RX2", "ASP_RX2" }, \
{ name" Source", "DSP_TX1", "DSP1" }, \
{ name" Source", "DSP_TX2", "DSP1" }
static const struct snd_soc_dapm_route cs35l45_dapm_routes[] = {
/* Feedback */
{ "VMON", NULL, "VMON_SRC" },
{ "IMON", NULL, "IMON_SRC" },
{ "VDD_BATTMON", NULL, "VDD_BATTMON_SRC" },
{ "VDD_BSTMON", NULL, "VDD_BSTMON_SRC" },
{ "Capture", NULL, "ASP_TX1"},
{ "Capture", NULL, "ASP_TX2"},
{ "Capture", NULL, "ASP_TX3"},
{ "Capture", NULL, "ASP_TX4"},
{ "Capture", NULL, "ASP_TX5"},
{ "ASP_TX1", NULL, "ASP_TX1 Source"},
{ "ASP_TX2", NULL, "ASP_TX2 Source"},
{ "ASP_TX3", NULL, "ASP_TX3 Source"},
{ "ASP_TX4", NULL, "ASP_TX4 Source"},
{ "ASP_TX5", NULL, "ASP_TX5 Source"},
{ "ASP_TX1", NULL, "ASP_EN" },
{ "ASP_TX2", NULL, "ASP_EN" },
{ "ASP_TX3", NULL, "ASP_EN" },
{ "ASP_TX4", NULL, "ASP_EN" },
{ "ASP_TX1", NULL, "GLOBAL_EN" },
{ "ASP_TX2", NULL, "GLOBAL_EN" },
{ "ASP_TX3", NULL, "GLOBAL_EN" },
{ "ASP_TX4", NULL, "GLOBAL_EN" },
{ "ASP_TX5", NULL, "GLOBAL_EN" },
CS35L45_ASP_MUX_ROUTE("ASP_TX1"),
CS35L45_ASP_MUX_ROUTE("ASP_TX2"),
CS35L45_ASP_MUX_ROUTE("ASP_TX3"),
CS35L45_ASP_MUX_ROUTE("ASP_TX4"),
CS35L45_ASP_MUX_ROUTE("ASP_TX5"),
/* Playback */
{ "ASP_RX1", NULL, "Playback" },
{ "ASP_RX2", NULL, "Playback" },
{ "ASP_RX1", NULL, "ASP_EN" },
{ "ASP_RX2", NULL, "ASP_EN" },
{ "AMP", NULL, "DACPCM Source"},
{ "AMP", NULL, "GLOBAL_EN"},
CS35L45_DSP_MUX_ROUTE("DSP_RX1"),
CS35L45_DSP_MUX_ROUTE("DSP_RX2"),
CS35L45_DSP_MUX_ROUTE("DSP_RX3"),
CS35L45_DSP_MUX_ROUTE("DSP_RX4"),
CS35L45_DSP_MUX_ROUTE("DSP_RX5"),
CS35L45_DSP_MUX_ROUTE("DSP_RX6"),
CS35L45_DSP_MUX_ROUTE("DSP_RX7"),
CS35L45_DSP_MUX_ROUTE("DSP_RX8"),
{"DSP1", NULL, "DSP_RX1 Source"},
{"DSP1", NULL, "DSP_RX2 Source"},
{"DSP1", NULL, "DSP_RX3 Source"},
{"DSP1", NULL, "DSP_RX4 Source"},
{"DSP1", NULL, "DSP_RX5 Source"},
{"DSP1", NULL, "DSP_RX6 Source"},
{"DSP1", NULL, "DSP_RX7 Source"},
{"DSP1", NULL, "DSP_RX8 Source"},
{"DSP1 Preload", NULL, "DSP1 Preloader"},
{"DSP1", NULL, "DSP1 Preloader"},
CS35L45_DAC_MUX_ROUTE("DACPCM"),
{ "SPK", NULL, "AMP"},
};
static const DECLARE_TLV_DB_SCALE(cs35l45_dig_pcm_vol_tlv, -10225, 25, true);
static const struct snd_kcontrol_new cs35l45_controls[] = {
/* Ignore bit 0: it is beyond the resolution of TLV_DB_SCALE */
SOC_SINGLE_S_TLV("Digital PCM Volume",
CS35L45_AMP_PCM_CONTROL,
CS35L45_AMP_VOL_PCM_SHIFT + 1,
-409, 48,
(CS35L45_AMP_VOL_PCM_WIDTH - 1) - 1,
0, cs35l45_dig_pcm_vol_tlv),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
WM_ADSP_FW_CONTROL("DSP1", 0),
};
static int cs35l45_set_pll(struct cs35l45_private *cs35l45, unsigned int freq)
{
unsigned int val;
int freq_id;
freq_id = cs35l45_get_clk_freq_id(freq);
if (freq_id < 0) {
dev_err(cs35l45->dev, "Invalid freq: %u\n", freq);
return -EINVAL;
}
regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val);
val = (val & CS35L45_PLL_REFCLK_FREQ_MASK) >> CS35L45_PLL_REFCLK_FREQ_SHIFT;
if (val == freq_id)
return 0;
regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);
regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT,
CS35L45_PLL_REFCLK_FREQ_MASK,
freq_id << CS35L45_PLL_REFCLK_FREQ_SHIFT);
regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);
regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);
regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);
return 0;
}
static int cs35l45_asp_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(codec_dai->component);
unsigned int asp_fmt, fsync_inv, bclk_inv;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_err(cs35l45->dev, "Invalid DAI clocking\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
asp_fmt = CS35l45_ASP_FMT_DSP_A;
break;
case SND_SOC_DAIFMT_I2S:
asp_fmt = CS35L45_ASP_FMT_I2S;
break;
default:
dev_err(cs35l45->dev, "Invalid DAI format\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
fsync_inv = 1;
bclk_inv = 0;
break;
case SND_SOC_DAIFMT_IB_NF:
fsync_inv = 0;
bclk_inv = 1;
break;
case SND_SOC_DAIFMT_IB_IF:
fsync_inv = 1;
bclk_inv = 1;
break;
case SND_SOC_DAIFMT_NB_NF:
fsync_inv = 0;
bclk_inv = 0;
break;
default:
dev_warn(cs35l45->dev, "Invalid DAI clock polarity\n");
return -EINVAL;
}
regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
CS35L45_ASP_FMT_MASK |
CS35L45_ASP_FSYNC_INV_MASK |
CS35L45_ASP_BCLK_INV_MASK,
(asp_fmt << CS35L45_ASP_FMT_SHIFT) |
(fsync_inv << CS35L45_ASP_FSYNC_INV_SHIFT) |
(bclk_inv << CS35L45_ASP_BCLK_INV_SHIFT));
return 0;
}
static int cs35l45_asp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
unsigned int asp_width, asp_wl, global_fs, slot_multiple, asp_fmt;
int bclk;
switch (params_rate(params)) {
case 44100:
global_fs = CS35L45_44P100_KHZ;
break;
case 48000:
global_fs = CS35L45_48P0_KHZ;
break;
case 88200:
global_fs = CS35L45_88P200_KHZ;
break;
case 96000:
global_fs = CS35L45_96P0_KHZ;
break;
default:
dev_warn(cs35l45->dev, "Unsupported sample rate (%d)\n",
params_rate(params));
return -EINVAL;
}
regmap_update_bits(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE,
CS35L45_GLOBAL_FS_MASK,
global_fs << CS35L45_GLOBAL_FS_SHIFT);
asp_wl = params_width(params);
if (cs35l45->slot_width)
asp_width = cs35l45->slot_width;
else
asp_width = params_width(params);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
CS35L45_ASP_WIDTH_RX_MASK,
asp_width << CS35L45_ASP_WIDTH_RX_SHIFT);
regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL5,
CS35L45_ASP_WL_MASK,
asp_wl << CS35L45_ASP_WL_SHIFT);
} else {
regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
CS35L45_ASP_WIDTH_TX_MASK,
asp_width << CS35L45_ASP_WIDTH_TX_SHIFT);
regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL1,
CS35L45_ASP_WL_MASK,
asp_wl << CS35L45_ASP_WL_SHIFT);
}
if (cs35l45->sysclk_set)
return 0;
/* I2S always has an even number of channels */
regmap_read(cs35l45->regmap, CS35L45_ASP_CONTROL2, &asp_fmt);
asp_fmt = (asp_fmt & CS35L45_ASP_FMT_MASK) >> CS35L45_ASP_FMT_SHIFT;
if (asp_fmt == CS35L45_ASP_FMT_I2S)
slot_multiple = 2;
else
slot_multiple = 1;
bclk = snd_soc_tdm_params_to_bclk(params, asp_width,
cs35l45->slot_count, slot_multiple);
return cs35l45_set_pll(cs35l45, bclk);
}
static int cs35l45_asp_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
if (slot_width && ((slot_width < 16) || (slot_width > 128)))
return -EINVAL;
cs35l45->slot_width = slot_width;
cs35l45->slot_count = slots;
return 0;
}
static int cs35l45_asp_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
int ret;
if (clk_id != 0) {
dev_err(cs35l45->dev, "Invalid clk_id %d\n", clk_id);
return -EINVAL;
}
cs35l45->sysclk_set = false;
if (freq == 0)
return 0;
ret = cs35l45_set_pll(cs35l45, freq);
if (ret < 0)
return -EINVAL;
cs35l45->sysclk_set = true;
return 0;
}
static int cs35l45_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
unsigned int global_fs, val, hpf_tune;
if (mute)
return 0;
regmap_read(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE, &global_fs);
global_fs = (global_fs & CS35L45_GLOBAL_FS_MASK) >> CS35L45_GLOBAL_FS_SHIFT;
switch (global_fs) {
case CS35L45_44P100_KHZ:
hpf_tune = CS35L45_HPF_44P1;
break;
case CS35L45_88P200_KHZ:
hpf_tune = CS35L45_HPF_88P2;
break;
default:
hpf_tune = CS35l45_HPF_DEFAULT;
break;
}
regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_HPF_TST, &val);
if (val != hpf_tune) {
struct reg_sequence hpf_override_seq[] = {
{ 0x00000040, 0x00000055 },
{ 0x00000040, 0x000000AA },
{ 0x00000044, 0x00000055 },
{ 0x00000044, 0x000000AA },
{ CS35L45_AMP_PCM_HPF_TST, hpf_tune },
{ 0x00000040, 0x00000000 },
{ 0x00000044, 0x00000000 },
};
regmap_multi_reg_write(cs35l45->regmap, hpf_override_seq,
ARRAY_SIZE(hpf_override_seq));
}
return 0;
}
static const struct snd_soc_dai_ops cs35l45_asp_dai_ops = {
.set_fmt = cs35l45_asp_set_fmt,
.hw_params = cs35l45_asp_hw_params,
.set_tdm_slot = cs35l45_asp_set_tdm_slot,
.set_sysclk = cs35l45_asp_set_sysclk,
.mute_stream = cs35l45_mute_stream,
};
static struct snd_soc_dai_driver cs35l45_dai[] = {
{
.name = "cs35l45",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = CS35L45_RATES,
.formats = CS35L45_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 5,
.rates = CS35L45_RATES,
.formats = CS35L45_FORMATS,
},
.symmetric_rate = true,
.symmetric_sample_bits = true,
.ops = &cs35l45_asp_dai_ops,
},
};
static int cs35l45_component_probe(struct snd_soc_component *component)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
return wm_adsp2_component_probe(&cs35l45->dsp, component);
}
static void cs35l45_component_remove(struct snd_soc_component *component)
{
struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
wm_adsp2_component_remove(&cs35l45->dsp, component);
}
static const struct snd_soc_component_driver cs35l45_component = {
.probe = cs35l45_component_probe,
.remove = cs35l45_component_remove,
.dapm_widgets = cs35l45_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l45_dapm_widgets),
.dapm_routes = cs35l45_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs35l45_dapm_routes),
.controls = cs35l45_controls,
.num_controls = ARRAY_SIZE(cs35l45_controls),
.name = "cs35l45",
.endianness = 1,
};
static void cs35l45_setup_hibernate(struct cs35l45_private *cs35l45)
{
unsigned int wksrc;
if (cs35l45->bus_type == CONTROL_BUS_I2C)
wksrc = CS35L45_WKSRC_I2C;
else
wksrc = CS35L45_WKSRC_SPI;
regmap_update_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,
CS35L45_WKSRC_EN_MASK,
wksrc << CS35L45_WKSRC_EN_SHIFT);
regmap_set_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,
CS35L45_UPDT_WKCTL_MASK);
regmap_update_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,
CS35L45_WKI2C_ADDR_MASK, cs35l45->i2c_addr);
regmap_set_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,
CS35L45_UPDT_WKI2C_MASK);
}
static int cs35l45_enter_hibernate(struct cs35l45_private *cs35l45)
{
dev_dbg(cs35l45->dev, "Enter hibernate\n");
cs35l45_setup_hibernate(cs35l45);
// Don't wait for ACK since bus activity would wake the device
regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, CSPL_MBOX_CMD_HIBERNATE);
return 0;
}
static int cs35l45_exit_hibernate(struct cs35l45_private *cs35l45)
{
const int wake_retries = 20;
const int sleep_retries = 5;
int ret, i, j;
for (i = 0; i < sleep_retries; i++) {
dev_dbg(cs35l45->dev, "Exit hibernate\n");
for (j = 0; j < wake_retries; j++) {
ret = cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
CSPL_MBOX_CMD_OUT_OF_HIBERNATE);
if (!ret) {
dev_dbg(cs35l45->dev, "Wake success at cycle: %d\n", j);
return 0;
}
usleep_range(100, 200);
}
dev_err(cs35l45->dev, "Wake failed, re-enter hibernate: %d\n", ret);
cs35l45_setup_hibernate(cs35l45);
}
dev_err(cs35l45->dev, "Timed out waking device\n");
return -ETIMEDOUT;
}
static int __maybe_unused cs35l45_runtime_suspend(struct device *dev)
{
struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running)
return 0;
cs35l45_enter_hibernate(cs35l45);
regcache_cache_only(cs35l45->regmap, true);
regcache_mark_dirty(cs35l45->regmap);
dev_dbg(cs35l45->dev, "Runtime suspended\n");
return 0;
}
static int __maybe_unused cs35l45_runtime_resume(struct device *dev)
{
struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
int ret;
if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running)
return 0;
dev_dbg(cs35l45->dev, "Runtime resume\n");
regcache_cache_only(cs35l45->regmap, false);
ret = cs35l45_exit_hibernate(cs35l45);
if (ret)
return ret;
ret = regcache_sync(cs35l45->regmap);
if (ret != 0)
dev_warn(cs35l45->dev, "regcache_sync failed: %d\n", ret);
/* Clear global error status */
regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
regmap_set_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
return ret;
}
static int cs35l45_apply_property_config(struct cs35l45_private *cs35l45)
{
struct device_node *node = cs35l45->dev->of_node;
unsigned int gpio_regs[] = {CS35L45_GPIO1_CTRL1, CS35L45_GPIO2_CTRL1,
CS35L45_GPIO3_CTRL1};
unsigned int pad_regs[] = {CS35L45_SYNC_GPIO1,
CS35L45_INTB_GPIO2_MCLK_REF, CS35L45_GPIO3};
struct device_node *child;
unsigned int val;
char of_name[32];
int ret, i;
if (!node)
return 0;
for (i = 0; i < CS35L45_NUM_GPIOS; i++) {
sprintf(of_name, "cirrus,gpio-ctrl%d", i + 1);
child = of_get_child_by_name(node, of_name);
if (!child)
continue;
ret = of_property_read_u32(child, "gpio-dir", &val);
if (!ret)
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
CS35L45_GPIO_DIR_MASK,
val << CS35L45_GPIO_DIR_SHIFT);
ret = of_property_read_u32(child, "gpio-lvl", &val);
if (!ret)
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
CS35L45_GPIO_LVL_MASK,
val << CS35L45_GPIO_LVL_SHIFT);
ret = of_property_read_u32(child, "gpio-op-cfg", &val);
if (!ret)
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
CS35L45_GPIO_OP_CFG_MASK,
val << CS35L45_GPIO_OP_CFG_SHIFT);
ret = of_property_read_u32(child, "gpio-pol", &val);
if (!ret)
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
CS35L45_GPIO_POL_MASK,
val << CS35L45_GPIO_POL_SHIFT);
ret = of_property_read_u32(child, "gpio-ctrl", &val);
if (!ret)
regmap_update_bits(cs35l45->regmap, pad_regs[i],
CS35L45_GPIO_CTRL_MASK,
val << CS35L45_GPIO_CTRL_SHIFT);
ret = of_property_read_u32(child, "gpio-invert", &val);
if (!ret) {
regmap_update_bits(cs35l45->regmap, pad_regs[i],
CS35L45_GPIO_INVERT_MASK,
val << CS35L45_GPIO_INVERT_SHIFT);
if (i == 1)
cs35l45->irq_invert = val;
}
of_node_put(child);
}
if (device_property_read_u32(cs35l45->dev,
"cirrus,asp-sdout-hiz-ctrl", &val) == 0) {
regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL3,
CS35L45_ASP_DOUT_HIZ_CTRL_MASK,
val << CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT);
}
return 0;
}
static int cs35l45_dsp_virt2_mbox3_irq_handle(struct cs35l45_private *cs35l45,
const unsigned int cmd,
unsigned int data)
{
static char *speak_status = "Unknown";
switch (cmd) {
case EVENT_SPEAKER_STATUS:
switch (data) {
case 1:
speak_status = "All Clear";
break;
case 2:
speak_status = "Open Circuit";
break;
case 4:
speak_status = "Short Circuit";
break;
}
dev_info(cs35l45->dev, "MBOX event (SPEAKER_STATUS): %s\n",
speak_status);
break;
case EVENT_BOOT_DONE:
dev_dbg(cs35l45->dev, "MBOX event (BOOT_DONE)\n");
break;
default:
dev_err(cs35l45->dev, "MBOX event not supported %u\n", cmd);
return -EINVAL;
}
return 0;
}
static irqreturn_t cs35l45_dsp_virt2_mbox_cb(int irq, void *data)
{
struct cs35l45_private *cs35l45 = data;
unsigned int mbox_val;
int ret = 0;
ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_3, &mbox_val);
if (!ret && mbox_val)
cs35l45_dsp_virt2_mbox3_irq_handle(cs35l45, mbox_val & CS35L45_MBOX3_CMD_MASK,
(mbox_val & CS35L45_MBOX3_DATA_MASK) >> CS35L45_MBOX3_DATA_SHIFT);
/* Handle DSP trace log IRQ */
ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_4, &mbox_val);
if (!ret && mbox_val != 0) {
dev_err(cs35l45->dev, "Spurious DSP MBOX4 IRQ\n");
}
return IRQ_RETVAL(ret);
}
static irqreturn_t cs35l45_pll_unlock(int irq, void *data)
{
struct cs35l45_private *cs35l45 = data;
dev_dbg(cs35l45->dev, "PLL unlock detected!");
return IRQ_HANDLED;
}
static irqreturn_t cs35l45_pll_lock(int irq, void *data)
{
struct cs35l45_private *cs35l45 = data;
dev_dbg(cs35l45->dev, "PLL lock detected!");
return IRQ_HANDLED;
}
static irqreturn_t cs35l45_spk_safe_err(int irq, void *data);
static const struct cs35l45_irq cs35l45_irqs[] = {
CS35L45_IRQ(AMP_SHORT_ERR, "Amplifier short error", cs35l45_spk_safe_err),
CS35L45_IRQ(UVLO_VDDBATT_ERR, "VDDBATT undervoltage error", cs35l45_spk_safe_err),
CS35L45_IRQ(BST_SHORT_ERR, "Boost inductor error", cs35l45_spk_safe_err),
CS35L45_IRQ(BST_UVP_ERR, "Boost undervoltage error", cs35l45_spk_safe_err),
CS35L45_IRQ(TEMP_ERR, "Overtemperature error", cs35l45_spk_safe_err),
CS35L45_IRQ(AMP_CAL_ERR, "Amplifier calibration error", cs35l45_spk_safe_err),
CS35L45_IRQ(UVLO_VDDLV_ERR, "LV threshold detector error", cs35l45_spk_safe_err),
CS35L45_IRQ(GLOBAL_ERROR, "Global error", cs35l45_spk_safe_err),
CS35L45_IRQ(DSP_WDT_EXPIRE, "DSP Watchdog Timer", cs35l45_spk_safe_err),
CS35L45_IRQ(PLL_UNLOCK_FLAG_RISE, "PLL unlock", cs35l45_pll_unlock),
CS35L45_IRQ(PLL_LOCK_FLAG, "PLL lock", cs35l45_pll_lock),
CS35L45_IRQ(DSP_VIRT2_MBOX, "DSP virtual MBOX 2 write flag", cs35l45_dsp_virt2_mbox_cb),
};
static irqreturn_t cs35l45_spk_safe_err(int irq, void *data)
{
struct cs35l45_private *cs35l45 = data;
int i;
i = irq - regmap_irq_get_virq(cs35l45->irq_data, 0);
dev_err(cs35l45->dev, "%s condition detected!\n", cs35l45_irqs[i].name);
return IRQ_HANDLED;
}
static const struct regmap_irq cs35l45_reg_irqs[] = {
CS35L45_REG_IRQ(IRQ1_EINT_1, AMP_SHORT_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_1, UVLO_VDDBATT_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_1, BST_SHORT_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_1, BST_UVP_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_1, TEMP_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_3, AMP_CAL_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_18, UVLO_VDDLV_ERR),
CS35L45_REG_IRQ(IRQ1_EINT_18, GLOBAL_ERROR),
CS35L45_REG_IRQ(IRQ1_EINT_2, DSP_WDT_EXPIRE),
CS35L45_REG_IRQ(IRQ1_EINT_3, PLL_UNLOCK_FLAG_RISE),
CS35L45_REG_IRQ(IRQ1_EINT_3, PLL_LOCK_FLAG),
CS35L45_REG_IRQ(IRQ1_EINT_2, DSP_VIRT2_MBOX),
};
static const struct regmap_irq_chip cs35l45_regmap_irq_chip = {
.name = "cs35l45 IRQ1 Controller",
.main_status = CS35L45_IRQ1_STATUS,
.status_base = CS35L45_IRQ1_EINT_1,
.mask_base = CS35L45_IRQ1_MASK_1,
.ack_base = CS35L45_IRQ1_EINT_1,
.num_regs = 18,
.irqs = cs35l45_reg_irqs,
.num_irqs = ARRAY_SIZE(cs35l45_reg_irqs),
.runtime_pm = true,
};
static int cs35l45_initialize(struct cs35l45_private *cs35l45)
{
struct device *dev = cs35l45->dev;
unsigned int dev_id[5];
unsigned int sts;
int ret;
ret = regmap_read_poll_timeout(cs35l45->regmap, CS35L45_IRQ1_EINT_4, sts,
(sts & CS35L45_OTP_BOOT_DONE_STS_MASK),
1000, 5000);
if (ret < 0) {
dev_err(cs35l45->dev, "Timeout waiting for OTP boot\n");
return ret;
}
ret = regmap_bulk_read(cs35l45->regmap, CS35L45_DEVID, dev_id, ARRAY_SIZE(dev_id));
if (ret) {
dev_err(cs35l45->dev, "Get Device ID failed: %d\n", ret);
return ret;
}
switch (dev_id[0]) {
case 0x35A450:
case 0x35A460:
break;
default:
dev_err(cs35l45->dev, "Bad DEVID 0x%x\n", dev_id[0]);
return -ENODEV;
}
dev_info(cs35l45->dev, "Cirrus Logic CS35L45: REVID %02X OTPID %02X\n",
dev_id[1], dev_id[4]);
regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_4,
CS35L45_OTP_BOOT_DONE_STS_MASK | CS35L45_OTP_BUSY_MASK);
ret = cs35l45_apply_patch(cs35l45);
if (ret < 0) {
dev_err(dev, "Failed to apply init patch %d\n", ret);
return ret;
}
ret = cs35l45_apply_property_config(cs35l45);
if (ret < 0)
return ret;
return 0;
}
static const struct reg_sequence cs35l45_fs_errata_patch[] = {
{0x02B80080, 0x00000001},
{0x02B80088, 0x00000001},
{0x02B80090, 0x00000001},
{0x02B80098, 0x00000001},
{0x02B800A0, 0x00000001},
{0x02B800A8, 0x00000001},
{0x02B800B0, 0x00000001},
{0x02B800B8, 0x00000001},
{0x02B80280, 0x00000001},
{0x02B80288, 0x00000001},
{0x02B80290, 0x00000001},
{0x02B80298, 0x00000001},
{0x02B802A0, 0x00000001},
{0x02B802A8, 0x00000001},
{0x02B802B0, 0x00000001},
{0x02B802B8, 0x00000001},
};
static const struct cs_dsp_region cs35l45_dsp1_regions[] = {
{ .type = WMFW_HALO_PM_PACKED, .base = CS35L45_DSP1_PMEM_0 },
{ .type = WMFW_HALO_XM_PACKED, .base = CS35L45_DSP1_XMEM_PACK_0 },
{ .type = WMFW_HALO_YM_PACKED, .base = CS35L45_DSP1_YMEM_PACK_0 },
{. type = WMFW_ADSP2_XM, .base = CS35L45_DSP1_XMEM_UNPACK24_0},
{. type = WMFW_ADSP2_YM, .base = CS35L45_DSP1_YMEM_UNPACK24_0},
};
static int cs35l45_dsp_init(struct cs35l45_private *cs35l45)
{
struct wm_adsp *dsp = &cs35l45->dsp;
int ret;
dsp->part = "cs35l45";
dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
dsp->toggle_preload = true;
dsp->cs_dsp.num = 1;
dsp->cs_dsp.type = WMFW_HALO;
dsp->cs_dsp.rev = 0;
dsp->cs_dsp.dev = cs35l45->dev;
dsp->cs_dsp.regmap = cs35l45->regmap;
dsp->cs_dsp.base = CS35L45_DSP1_CLOCK_FREQ;
dsp->cs_dsp.base_sysinfo = CS35L45_DSP1_SYS_ID;
dsp->cs_dsp.mem = cs35l45_dsp1_regions;
dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l45_dsp1_regions);
dsp->cs_dsp.lock_regions = 0xFFFFFFFF;
ret = wm_halo_init(dsp);
regmap_multi_reg_write(cs35l45->regmap, cs35l45_fs_errata_patch,
ARRAY_SIZE(cs35l45_fs_errata_patch));
return ret;
}
int cs35l45_probe(struct cs35l45_private *cs35l45)
{
struct device *dev = cs35l45->dev;
unsigned long irq_pol = IRQF_ONESHOT | IRQF_SHARED;
int ret, i, irq;
cs35l45->vdd_batt = devm_regulator_get(dev, "vdd-batt");
if (IS_ERR(cs35l45->vdd_batt))
return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_batt),
"Failed to request vdd-batt\n");
cs35l45->vdd_a = devm_regulator_get(dev, "vdd-a");
if (IS_ERR(cs35l45->vdd_a))
return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_a),
"Failed to request vdd-a\n");
/* VDD_BATT must always be enabled before other supplies */
ret = regulator_enable(cs35l45->vdd_batt);
if (ret < 0)
return dev_err_probe(dev, ret, "Failed to enable vdd-batt\n");
ret = regulator_enable(cs35l45->vdd_a);
if (ret < 0)
return dev_err_probe(dev, ret, "Failed to enable vdd-a\n");
/* If reset is shared only one instance can claim it */
cs35l45->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(cs35l45->reset_gpio)) {
ret = PTR_ERR(cs35l45->reset_gpio);
cs35l45->reset_gpio = NULL;
if (ret == -EBUSY) {
dev_dbg(dev, "Reset line busy, assuming shared reset\n");
} else {
dev_err_probe(dev, ret, "Failed to get reset GPIO\n");
goto err;
}
}
if (cs35l45->reset_gpio) {
usleep_range(CS35L45_RESET_HOLD_US, CS35L45_RESET_HOLD_US + 100);
gpiod_set_value_cansleep(cs35l45->reset_gpio, 1);
}
usleep_range(CS35L45_RESET_US, CS35L45_RESET_US + 100);
ret = cs35l45_initialize(cs35l45);
if (ret < 0)
goto err_reset;
ret = cs35l45_dsp_init(cs35l45);
if (ret < 0)
goto err_reset;
pm_runtime_set_autosuspend_delay(cs35l45->dev, 3000);
pm_runtime_use_autosuspend(cs35l45->dev);
pm_runtime_mark_last_busy(cs35l45->dev);
pm_runtime_set_active(cs35l45->dev);
pm_runtime_get_noresume(cs35l45->dev);
pm_runtime_enable(cs35l45->dev);
if (cs35l45->irq) {
if (cs35l45->irq_invert)
irq_pol |= IRQF_TRIGGER_HIGH;
else
irq_pol |= IRQF_TRIGGER_LOW;
ret = devm_regmap_add_irq_chip(dev, cs35l45->regmap, cs35l45->irq, irq_pol, 0,
&cs35l45_regmap_irq_chip, &cs35l45->irq_data);
if (ret) {
dev_err(dev, "Failed to register IRQ chip: %d\n", ret);
goto err_dsp;
}
for (i = 0; i < ARRAY_SIZE(cs35l45_irqs); i++) {
irq = regmap_irq_get_virq(cs35l45->irq_data, cs35l45_irqs[i].irq);
if (irq < 0) {
dev_err(dev, "Failed to get %s\n", cs35l45_irqs[i].name);
ret = irq;
goto err_dsp;
}
ret = devm_request_threaded_irq(dev, irq, NULL, cs35l45_irqs[i].handler,
irq_pol, cs35l45_irqs[i].name, cs35l45);
if (ret) {
dev_err(dev, "Failed to request IRQ %s: %d\n",
cs35l45_irqs[i].name, ret);
goto err_dsp;
}
}
}
ret = devm_snd_soc_register_component(dev, &cs35l45_component,
cs35l45_dai,
ARRAY_SIZE(cs35l45_dai));
if (ret < 0)
goto err_dsp;
pm_runtime_put_autosuspend(cs35l45->dev);
return 0;
err_dsp:
pm_runtime_disable(cs35l45->dev);
pm_runtime_put_noidle(cs35l45->dev);
wm_adsp2_remove(&cs35l45->dsp);
err_reset:
gpiod_set_value_cansleep(cs35l45->reset_gpio, 0);
err:
regulator_disable(cs35l45->vdd_a);
regulator_disable(cs35l45->vdd_batt);
return ret;
}
EXPORT_SYMBOL_NS_GPL(cs35l45_probe, SND_SOC_CS35L45);
void cs35l45_remove(struct cs35l45_private *cs35l45)
{
pm_runtime_get_sync(cs35l45->dev);
pm_runtime_disable(cs35l45->dev);
wm_adsp2_remove(&cs35l45->dsp);
gpiod_set_value_cansleep(cs35l45->reset_gpio, 0);
pm_runtime_put_noidle(cs35l45->dev);
regulator_disable(cs35l45->vdd_a);
/* VDD_BATT must be the last to power-off */
regulator_disable(cs35l45->vdd_batt);
}
EXPORT_SYMBOL_NS_GPL(cs35l45_remove, SND_SOC_CS35L45);
const struct dev_pm_ops cs35l45_pm_ops = {
SET_RUNTIME_PM_OPS(cs35l45_runtime_suspend, cs35l45_runtime_resume, NULL)
};
EXPORT_SYMBOL_NS_GPL(cs35l45_pm_ops, SND_SOC_CS35L45);
MODULE_DESCRIPTION("ASoC CS35L45 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <[email protected]>");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l45.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments PCM186x Universal Audio ADC
*
* Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
* Andreas Dannenberg <[email protected]>
* Andrew F. Davis <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "pcm186x.h"
static const char * const pcm186x_supply_names[] = {
"avdd", /* Analog power supply. Connect to 3.3-V supply. */
"dvdd", /* Digital power supply. Connect to 3.3-V supply. */
"iovdd", /* I/O power supply. Connect to 3.3-V or 1.8-V. */
};
#define PCM186x_NUM_SUPPLIES ARRAY_SIZE(pcm186x_supply_names)
struct pcm186x_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[PCM186x_NUM_SUPPLIES];
unsigned int sysclk;
unsigned int tdm_offset;
bool is_tdm_mode;
bool is_provider_mode;
};
static const DECLARE_TLV_DB_SCALE(pcm186x_pga_tlv, -1200, 50, 0);
static const struct snd_kcontrol_new pcm1863_snd_controls[] = {
SOC_DOUBLE_R_S_TLV("ADC Capture Volume", PCM186X_PGA_VAL_CH1_L,
PCM186X_PGA_VAL_CH1_R, 0, -24, 80, 7, 0,
pcm186x_pga_tlv),
};
static const struct snd_kcontrol_new pcm1865_snd_controls[] = {
SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", PCM186X_PGA_VAL_CH1_L,
PCM186X_PGA_VAL_CH1_R, 0, -24, 80, 7, 0,
pcm186x_pga_tlv),
SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", PCM186X_PGA_VAL_CH2_L,
PCM186X_PGA_VAL_CH2_R, 0, -24, 80, 7, 0,
pcm186x_pga_tlv),
};
static const unsigned int pcm186x_adc_input_channel_sel_value[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x20, 0x30
};
static const char * const pcm186x_adcl_input_channel_sel_text[] = {
"No Select",
"VINL1[SE]", /* Default for ADC1L */
"VINL2[SE]", /* Default for ADC2L */
"VINL2[SE] + VINL1[SE]",
"VINL3[SE]",
"VINL3[SE] + VINL1[SE]",
"VINL3[SE] + VINL2[SE]",
"VINL3[SE] + VINL2[SE] + VINL1[SE]",
"VINL4[SE]",
"VINL4[SE] + VINL1[SE]",
"VINL4[SE] + VINL2[SE]",
"VINL4[SE] + VINL2[SE] + VINL1[SE]",
"VINL4[SE] + VINL3[SE]",
"VINL4[SE] + VINL3[SE] + VINL1[SE]",
"VINL4[SE] + VINL3[SE] + VINL2[SE]",
"VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE]",
"{VIN1P, VIN1M}[DIFF]",
"{VIN4P, VIN4M}[DIFF]",
"{VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF]"
};
static const char * const pcm186x_adcr_input_channel_sel_text[] = {
"No Select",
"VINR1[SE]", /* Default for ADC1R */
"VINR2[SE]", /* Default for ADC2R */
"VINR2[SE] + VINR1[SE]",
"VINR3[SE]",
"VINR3[SE] + VINR1[SE]",
"VINR3[SE] + VINR2[SE]",
"VINR3[SE] + VINR2[SE] + VINR1[SE]",
"VINR4[SE]",
"VINR4[SE] + VINR1[SE]",
"VINR4[SE] + VINR2[SE]",
"VINR4[SE] + VINR2[SE] + VINR1[SE]",
"VINR4[SE] + VINR3[SE]",
"VINR4[SE] + VINR3[SE] + VINR1[SE]",
"VINR4[SE] + VINR3[SE] + VINR2[SE]",
"VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE]",
"{VIN2P, VIN2M}[DIFF]",
"{VIN3P, VIN3M}[DIFF]",
"{VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF]"
};
static const struct soc_enum pcm186x_adc_input_channel_sel[] = {
SOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_L, 0,
PCM186X_ADC_INPUT_SEL_MASK,
ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),
pcm186x_adcl_input_channel_sel_text,
pcm186x_adc_input_channel_sel_value),
SOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_R, 0,
PCM186X_ADC_INPUT_SEL_MASK,
ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),
pcm186x_adcr_input_channel_sel_text,
pcm186x_adc_input_channel_sel_value),
SOC_VALUE_ENUM_SINGLE(PCM186X_ADC2_INPUT_SEL_L, 0,
PCM186X_ADC_INPUT_SEL_MASK,
ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),
pcm186x_adcl_input_channel_sel_text,
pcm186x_adc_input_channel_sel_value),
SOC_VALUE_ENUM_SINGLE(PCM186X_ADC2_INPUT_SEL_R, 0,
PCM186X_ADC_INPUT_SEL_MASK,
ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),
pcm186x_adcr_input_channel_sel_text,
pcm186x_adc_input_channel_sel_value),
};
static const struct snd_kcontrol_new pcm186x_adc_mux_controls[] = {
SOC_DAPM_ENUM("ADC1 Left Input", pcm186x_adc_input_channel_sel[0]),
SOC_DAPM_ENUM("ADC1 Right Input", pcm186x_adc_input_channel_sel[1]),
SOC_DAPM_ENUM("ADC2 Left Input", pcm186x_adc_input_channel_sel[2]),
SOC_DAPM_ENUM("ADC2 Right Input", pcm186x_adc_input_channel_sel[3]),
};
static const struct snd_soc_dapm_widget pcm1863_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("VINL1"),
SND_SOC_DAPM_INPUT("VINR1"),
SND_SOC_DAPM_INPUT("VINL2"),
SND_SOC_DAPM_INPUT("VINR2"),
SND_SOC_DAPM_INPUT("VINL3"),
SND_SOC_DAPM_INPUT("VINR3"),
SND_SOC_DAPM_INPUT("VINL4"),
SND_SOC_DAPM_INPUT("VINR4"),
SND_SOC_DAPM_MUX("ADC Left Capture Source", SND_SOC_NOPM, 0, 0,
&pcm186x_adc_mux_controls[0]),
SND_SOC_DAPM_MUX("ADC Right Capture Source", SND_SOC_NOPM, 0, 0,
&pcm186x_adc_mux_controls[1]),
/*
* Put the codec into SLEEP mode when not in use, allowing the
* Energysense mechanism to operate.
*/
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", PCM186X_POWER_CTRL, 1, 1),
};
static const struct snd_soc_dapm_widget pcm1865_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("VINL1"),
SND_SOC_DAPM_INPUT("VINR1"),
SND_SOC_DAPM_INPUT("VINL2"),
SND_SOC_DAPM_INPUT("VINR2"),
SND_SOC_DAPM_INPUT("VINL3"),
SND_SOC_DAPM_INPUT("VINR3"),
SND_SOC_DAPM_INPUT("VINL4"),
SND_SOC_DAPM_INPUT("VINR4"),
SND_SOC_DAPM_MUX("ADC1 Left Capture Source", SND_SOC_NOPM, 0, 0,
&pcm186x_adc_mux_controls[0]),
SND_SOC_DAPM_MUX("ADC1 Right Capture Source", SND_SOC_NOPM, 0, 0,
&pcm186x_adc_mux_controls[1]),
SND_SOC_DAPM_MUX("ADC2 Left Capture Source", SND_SOC_NOPM, 0, 0,
&pcm186x_adc_mux_controls[2]),
SND_SOC_DAPM_MUX("ADC2 Right Capture Source", SND_SOC_NOPM, 0, 0,
&pcm186x_adc_mux_controls[3]),
/*
* Put the codec into SLEEP mode when not in use, allowing the
* Energysense mechanism to operate.
*/
SND_SOC_DAPM_ADC("ADC1", "HiFi Capture 1", PCM186X_POWER_CTRL, 1, 1),
SND_SOC_DAPM_ADC("ADC2", "HiFi Capture 2", PCM186X_POWER_CTRL, 1, 1),
};
static const struct snd_soc_dapm_route pcm1863_dapm_routes[] = {
{ "ADC Left Capture Source", NULL, "VINL1" },
{ "ADC Left Capture Source", NULL, "VINR1" },
{ "ADC Left Capture Source", NULL, "VINL2" },
{ "ADC Left Capture Source", NULL, "VINR2" },
{ "ADC Left Capture Source", NULL, "VINL3" },
{ "ADC Left Capture Source", NULL, "VINR3" },
{ "ADC Left Capture Source", NULL, "VINL4" },
{ "ADC Left Capture Source", NULL, "VINR4" },
{ "ADC", NULL, "ADC Left Capture Source" },
{ "ADC Right Capture Source", NULL, "VINL1" },
{ "ADC Right Capture Source", NULL, "VINR1" },
{ "ADC Right Capture Source", NULL, "VINL2" },
{ "ADC Right Capture Source", NULL, "VINR2" },
{ "ADC Right Capture Source", NULL, "VINL3" },
{ "ADC Right Capture Source", NULL, "VINR3" },
{ "ADC Right Capture Source", NULL, "VINL4" },
{ "ADC Right Capture Source", NULL, "VINR4" },
{ "ADC", NULL, "ADC Right Capture Source" },
};
static const struct snd_soc_dapm_route pcm1865_dapm_routes[] = {
{ "ADC1 Left Capture Source", NULL, "VINL1" },
{ "ADC1 Left Capture Source", NULL, "VINR1" },
{ "ADC1 Left Capture Source", NULL, "VINL2" },
{ "ADC1 Left Capture Source", NULL, "VINR2" },
{ "ADC1 Left Capture Source", NULL, "VINL3" },
{ "ADC1 Left Capture Source", NULL, "VINR3" },
{ "ADC1 Left Capture Source", NULL, "VINL4" },
{ "ADC1 Left Capture Source", NULL, "VINR4" },
{ "ADC1", NULL, "ADC1 Left Capture Source" },
{ "ADC1 Right Capture Source", NULL, "VINL1" },
{ "ADC1 Right Capture Source", NULL, "VINR1" },
{ "ADC1 Right Capture Source", NULL, "VINL2" },
{ "ADC1 Right Capture Source", NULL, "VINR2" },
{ "ADC1 Right Capture Source", NULL, "VINL3" },
{ "ADC1 Right Capture Source", NULL, "VINR3" },
{ "ADC1 Right Capture Source", NULL, "VINL4" },
{ "ADC1 Right Capture Source", NULL, "VINR4" },
{ "ADC1", NULL, "ADC1 Right Capture Source" },
{ "ADC2 Left Capture Source", NULL, "VINL1" },
{ "ADC2 Left Capture Source", NULL, "VINR1" },
{ "ADC2 Left Capture Source", NULL, "VINL2" },
{ "ADC2 Left Capture Source", NULL, "VINR2" },
{ "ADC2 Left Capture Source", NULL, "VINL3" },
{ "ADC2 Left Capture Source", NULL, "VINR3" },
{ "ADC2 Left Capture Source", NULL, "VINL4" },
{ "ADC2 Left Capture Source", NULL, "VINR4" },
{ "ADC2", NULL, "ADC2 Left Capture Source" },
{ "ADC2 Right Capture Source", NULL, "VINL1" },
{ "ADC2 Right Capture Source", NULL, "VINR1" },
{ "ADC2 Right Capture Source", NULL, "VINL2" },
{ "ADC2 Right Capture Source", NULL, "VINR2" },
{ "ADC2 Right Capture Source", NULL, "VINL3" },
{ "ADC2 Right Capture Source", NULL, "VINR3" },
{ "ADC2 Right Capture Source", NULL, "VINL4" },
{ "ADC2 Right Capture Source", NULL, "VINR4" },
{ "ADC2", NULL, "ADC2 Right Capture Source" },
};
static int pcm186x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int rate = params_rate(params);
snd_pcm_format_t format = params_format(params);
unsigned int width = params_width(params);
unsigned int channels = params_channels(params);
unsigned int div_lrck;
unsigned int div_bck;
u8 tdm_tx_sel = 0;
u8 pcm_cfg = 0;
dev_dbg(component->dev, "%s() rate=%u format=0x%x width=%u channels=%u\n",
__func__, rate, format, width, channels);
switch (width) {
case 16:
pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_16 <<
PCM186X_PCM_CFG_RX_WLEN_SHIFT |
PCM186X_PCM_CFG_TX_WLEN_16 <<
PCM186X_PCM_CFG_TX_WLEN_SHIFT;
break;
case 20:
pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_20 <<
PCM186X_PCM_CFG_RX_WLEN_SHIFT |
PCM186X_PCM_CFG_TX_WLEN_20 <<
PCM186X_PCM_CFG_TX_WLEN_SHIFT;
break;
case 24:
pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_24 <<
PCM186X_PCM_CFG_RX_WLEN_SHIFT |
PCM186X_PCM_CFG_TX_WLEN_24 <<
PCM186X_PCM_CFG_TX_WLEN_SHIFT;
break;
case 32:
pcm_cfg = PCM186X_PCM_CFG_RX_WLEN_32 <<
PCM186X_PCM_CFG_RX_WLEN_SHIFT |
PCM186X_PCM_CFG_TX_WLEN_32 <<
PCM186X_PCM_CFG_TX_WLEN_SHIFT;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
PCM186X_PCM_CFG_RX_WLEN_MASK |
PCM186X_PCM_CFG_TX_WLEN_MASK,
pcm_cfg);
div_lrck = width * channels;
if (priv->is_tdm_mode) {
/* Select TDM transmission data */
switch (channels) {
case 2:
tdm_tx_sel = PCM186X_TDM_TX_SEL_2CH;
break;
case 4:
tdm_tx_sel = PCM186X_TDM_TX_SEL_4CH;
break;
case 6:
tdm_tx_sel = PCM186X_TDM_TX_SEL_6CH;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, PCM186X_TDM_TX_SEL,
PCM186X_TDM_TX_SEL_MASK, tdm_tx_sel);
/* In DSP/TDM mode, the LRCLK divider must be 256 */
div_lrck = 256;
/* Configure 1/256 duty cycle for LRCK */
snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
PCM186X_PCM_CFG_TDM_LRCK_MODE,
PCM186X_PCM_CFG_TDM_LRCK_MODE);
}
/* Only configure clock dividers in provider mode. */
if (priv->is_provider_mode) {
div_bck = priv->sysclk / (div_lrck * rate);
dev_dbg(component->dev,
"%s() master_clk=%u div_bck=%u div_lrck=%u\n",
__func__, priv->sysclk, div_bck, div_lrck);
snd_soc_component_write(component, PCM186X_BCK_DIV, div_bck - 1);
snd_soc_component_write(component, PCM186X_LRK_DIV, div_lrck - 1);
}
return 0;
}
static int pcm186x_set_fmt(struct snd_soc_dai *dai, unsigned int format)
{
struct snd_soc_component *component = dai->component;
struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
u8 clk_ctrl = 0;
u8 pcm_cfg = 0;
dev_dbg(component->dev, "%s() format=0x%x\n", __func__, format);
switch (format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
if (!priv->sysclk) {
dev_err(component->dev, "operating in provider mode requires sysclock to be configured\n");
return -EINVAL;
}
clk_ctrl |= PCM186X_CLK_CTRL_MST_MODE;
priv->is_provider_mode = true;
break;
case SND_SOC_DAIFMT_CBC_CFC:
priv->is_provider_mode = false;
break;
default:
dev_err(component->dev, "Invalid DAI master/slave interface\n");
return -EINVAL;
}
/* set interface polarity */
switch (format & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
dev_err(component->dev, "Inverted DAI clocks not supported\n");
return -EINVAL;
}
/* set interface format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pcm_cfg = PCM186X_PCM_CFG_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
pcm_cfg = PCM186X_PCM_CFG_FMT_LEFTJ;
break;
case SND_SOC_DAIFMT_DSP_A:
priv->tdm_offset += 1;
fallthrough;
/* DSP_A uses the same basic config as DSP_B
* except we need to shift the TDM output by one BCK cycle
*/
case SND_SOC_DAIFMT_DSP_B:
priv->is_tdm_mode = true;
pcm_cfg = PCM186X_PCM_CFG_FMT_TDM;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, PCM186X_CLK_CTRL,
PCM186X_CLK_CTRL_MST_MODE, clk_ctrl);
snd_soc_component_write(component, PCM186X_TDM_TX_OFFSET, priv->tdm_offset);
snd_soc_component_update_bits(component, PCM186X_PCM_CFG,
PCM186X_PCM_CFG_FMT_MASK, pcm_cfg);
return 0;
}
static int pcm186x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
unsigned int first_slot, last_slot, tdm_offset;
dev_dbg(component->dev,
"%s() tx_mask=0x%x rx_mask=0x%x slots=%d slot_width=%d\n",
__func__, tx_mask, rx_mask, slots, slot_width);
if (!tx_mask) {
dev_err(component->dev, "tdm tx mask must not be 0\n");
return -EINVAL;
}
first_slot = __ffs(tx_mask);
last_slot = __fls(tx_mask);
if (last_slot - first_slot != hweight32(tx_mask) - 1) {
dev_err(component->dev, "tdm tx mask must be contiguous\n");
return -EINVAL;
}
tdm_offset = first_slot * slot_width;
if (tdm_offset > 255) {
dev_err(component->dev, "tdm tx slot selection out of bounds\n");
return -EINVAL;
}
priv->tdm_offset = tdm_offset;
return 0;
}
static int pcm186x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
dev_dbg(component->dev, "%s() clk_id=%d freq=%u dir=%d\n",
__func__, clk_id, freq, dir);
priv->sysclk = freq;
return 0;
}
static const struct snd_soc_dai_ops pcm186x_dai_ops = {
.set_sysclk = pcm186x_set_dai_sysclk,
.set_tdm_slot = pcm186x_set_tdm_slot,
.set_fmt = pcm186x_set_fmt,
.hw_params = pcm186x_hw_params,
};
static struct snd_soc_dai_driver pcm1863_dai = {
.name = "pcm1863-aif",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = PCM186X_RATES,
.formats = PCM186X_FORMATS,
},
.ops = &pcm186x_dai_ops,
};
static struct snd_soc_dai_driver pcm1865_dai = {
.name = "pcm1865-aif",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = PCM186X_RATES,
.formats = PCM186X_FORMATS,
},
.ops = &pcm186x_dai_ops,
};
static int pcm186x_power_on(struct snd_soc_component *component)
{
struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
int ret = 0;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret)
return ret;
regcache_cache_only(priv->regmap, false);
ret = regcache_sync(priv->regmap);
if (ret) {
dev_err(component->dev, "Failed to restore cache\n");
regcache_cache_only(priv->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
priv->supplies);
return ret;
}
snd_soc_component_update_bits(component, PCM186X_POWER_CTRL,
PCM186X_PWR_CTRL_PWRDN, 0);
return 0;
}
static int pcm186x_power_off(struct snd_soc_component *component)
{
struct pcm186x_priv *priv = snd_soc_component_get_drvdata(component);
snd_soc_component_update_bits(component, PCM186X_POWER_CTRL,
PCM186X_PWR_CTRL_PWRDN, PCM186X_PWR_CTRL_PWRDN);
regcache_cache_only(priv->regmap, true);
return regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
priv->supplies);
}
static int pcm186x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
snd_soc_component_get_bias_level(component), level);
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
pcm186x_power_on(component);
break;
case SND_SOC_BIAS_OFF:
pcm186x_power_off(component);
break;
}
return 0;
}
static struct snd_soc_component_driver soc_codec_dev_pcm1863 = {
.set_bias_level = pcm186x_set_bias_level,
.controls = pcm1863_snd_controls,
.num_controls = ARRAY_SIZE(pcm1863_snd_controls),
.dapm_widgets = pcm1863_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm1863_dapm_widgets),
.dapm_routes = pcm1863_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm1863_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_component_driver soc_codec_dev_pcm1865 = {
.set_bias_level = pcm186x_set_bias_level,
.controls = pcm1865_snd_controls,
.num_controls = ARRAY_SIZE(pcm1865_snd_controls),
.dapm_widgets = pcm1865_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(pcm1865_dapm_widgets),
.dapm_routes = pcm1865_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(pcm1865_dapm_routes),
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static bool pcm186x_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case PCM186X_PAGE:
case PCM186X_DEVICE_STATUS:
case PCM186X_FSAMPLE_STATUS:
case PCM186X_DIV_STATUS:
case PCM186X_CLK_STATUS:
case PCM186X_SUPPLY_STATUS:
case PCM186X_MMAP_STAT_CTRL:
case PCM186X_MMAP_ADDRESS:
return true;
}
return false;
}
static const struct regmap_range_cfg pcm186x_range = {
.name = "Pages",
.range_max = PCM186X_MAX_REGISTER,
.selector_reg = PCM186X_PAGE,
.selector_mask = 0xff,
.window_len = PCM186X_PAGE_LEN,
};
const struct regmap_config pcm186x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = pcm186x_volatile,
.ranges = &pcm186x_range,
.num_ranges = 1,
.max_register = PCM186X_MAX_REGISTER,
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL_GPL(pcm186x_regmap);
int pcm186x_probe(struct device *dev, enum pcm186x_type type, int irq,
struct regmap *regmap)
{
struct pcm186x_priv *priv;
int i, ret;
priv = devm_kzalloc(dev, sizeof(struct pcm186x_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
dev_set_drvdata(dev, priv);
priv->regmap = regmap;
for (i = 0; i < ARRAY_SIZE(priv->supplies); i++)
priv->supplies[i].supply = pcm186x_supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret) {
dev_err(dev, "failed to request supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret) {
dev_err(dev, "failed enable supplies: %d\n", ret);
return ret;
}
/* Reset device registers for a consistent power-on like state */
ret = regmap_write(regmap, PCM186X_PAGE, PCM186X_RESET);
if (ret) {
dev_err(dev, "failed to write device: %d\n", ret);
return ret;
}
ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret) {
dev_err(dev, "failed disable supplies: %d\n", ret);
return ret;
}
switch (type) {
case PCM1865:
case PCM1864:
ret = devm_snd_soc_register_component(dev, &soc_codec_dev_pcm1865,
&pcm1865_dai, 1);
break;
case PCM1863:
case PCM1862:
default:
ret = devm_snd_soc_register_component(dev, &soc_codec_dev_pcm1863,
&pcm1863_dai, 1);
}
if (ret) {
dev_err(dev, "failed to register CODEC: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(pcm186x_probe);
MODULE_AUTHOR("Andreas Dannenberg <[email protected]>");
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("PCM186x Universal Audio ADC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm186x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TAS571x amplifier audio driver
*
* Copyright (C) 2015 Google, Inc.
* Copyright (c) 2013 Daniel Mack <[email protected]>
*
* TAS5721 support:
* Copyright (C) 2016 Petr Kulhavy, Barix AG <[email protected]>
*
* TAS5707 support:
* Copyright (C) 2018 Jerome Brunet, Baylibre SAS <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/stddef.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <asm/unaligned.h>
#include "tas571x.h"
#define TAS571X_MAX_SUPPLIES 6
struct tas571x_chip {
const char *const *supply_names;
int num_supply_names;
const struct snd_kcontrol_new *controls;
int num_controls;
const struct regmap_config *regmap_config;
int vol_reg_size;
};
struct tas571x_private {
const struct tas571x_chip *chip;
struct regmap *regmap;
struct regulator_bulk_data supplies[TAS571X_MAX_SUPPLIES];
struct clk *mclk;
unsigned int format;
struct gpio_desc *reset_gpio;
struct gpio_desc *pdn_gpio;
struct snd_soc_component_driver component_driver;
};
static int tas571x_register_size(struct tas571x_private *priv, unsigned int reg)
{
switch (reg) {
case TAS571X_MVOL_REG:
case TAS571X_CH1_VOL_REG:
case TAS571X_CH2_VOL_REG:
return priv->chip->vol_reg_size;
case TAS571X_INPUT_MUX_REG:
case TAS571X_CH4_SRC_SELECT_REG:
case TAS571X_PWM_MUX_REG:
case TAS5717_CH1_RIGHT_CH_MIX_REG:
case TAS5717_CH1_LEFT_CH_MIX_REG:
case TAS5717_CH2_LEFT_CH_MIX_REG:
case TAS5717_CH2_RIGHT_CH_MIX_REG:
return 4;
default:
return 1;
}
}
static int tas571x_reg_write(void *context, unsigned int reg,
unsigned int value)
{
struct i2c_client *client = context;
struct tas571x_private *priv = i2c_get_clientdata(client);
unsigned int i, size;
uint8_t buf[5];
int ret;
size = tas571x_register_size(priv, reg);
buf[0] = reg;
for (i = size; i >= 1; --i) {
buf[i] = value;
value >>= 8;
}
ret = i2c_master_send(client, buf, size + 1);
if (ret == size + 1)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int tas571x_reg_read(void *context, unsigned int reg,
unsigned int *value)
{
struct i2c_client *client = context;
struct tas571x_private *priv = i2c_get_clientdata(client);
uint8_t send_buf, recv_buf[4];
struct i2c_msg msgs[2];
unsigned int size;
unsigned int i;
int ret;
size = tas571x_register_size(priv, reg);
send_buf = reg;
msgs[0].addr = client->addr;
msgs[0].len = sizeof(send_buf);
msgs[0].buf = &send_buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = size;
msgs[1].buf = recv_buf;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
return ret;
else if (ret != ARRAY_SIZE(msgs))
return -EIO;
*value = 0;
for (i = 0; i < size; i++) {
*value <<= 8;
*value |= recv_buf[i];
}
return 0;
}
/*
* register write for 8- and 20-byte registers
*/
static int tas571x_reg_write_multiword(struct i2c_client *client,
unsigned int reg, const long values[], size_t len)
{
size_t i;
uint8_t *buf, *p;
int ret;
size_t send_size = 1 + len * sizeof(uint32_t);
buf = kzalloc(send_size, GFP_KERNEL | GFP_DMA);
if (!buf)
return -ENOMEM;
buf[0] = reg;
for (i = 0, p = buf + 1; i < len; i++, p += sizeof(uint32_t))
put_unaligned_be32(values[i], p);
ret = i2c_master_send(client, buf, send_size);
kfree(buf);
if (ret == send_size)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
/*
* register read for 8- and 20-byte registers
*/
static int tas571x_reg_read_multiword(struct i2c_client *client,
unsigned int reg, long values[], size_t len)
{
unsigned int i;
uint8_t send_buf;
uint8_t *recv_buf, *p;
struct i2c_msg msgs[2];
unsigned int recv_size = len * sizeof(uint32_t);
int ret;
recv_buf = kzalloc(recv_size, GFP_KERNEL | GFP_DMA);
if (!recv_buf)
return -ENOMEM;
send_buf = reg;
msgs[0].addr = client->addr;
msgs[0].len = sizeof(send_buf);
msgs[0].buf = &send_buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = recv_size;
msgs[1].buf = recv_buf;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret < 0)
goto err_ret;
else if (ret != ARRAY_SIZE(msgs)) {
ret = -EIO;
goto err_ret;
}
for (i = 0, p = recv_buf; i < len; i++, p += sizeof(uint32_t))
values[i] = get_unaligned_be32(p);
err_ret:
kfree(recv_buf);
return ret;
}
/*
* Integer array controls for setting biquad, mixer, DRC coefficients.
* According to the datasheet each coefficient is effectively 26bits,
* i.e. stored as 32bits, where bits [31:26] are ignored.
* TI's TAS57xx Graphical Development Environment tool however produces
* coefficients with more than 26 bits. For this reason we allow values
* in the full 32-bits reange.
* The coefficients are ordered as given in the TAS571x data sheet:
* b0, b1, b2, a1, a2
*/
static int tas571x_coefficient_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
int numcoef = kcontrol->private_value >> 16;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = numcoef;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 0xffffffff;
return 0;
}
static int tas571x_coefficient_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct i2c_client *i2c = to_i2c_client(component->dev);
int numcoef = kcontrol->private_value >> 16;
int index = kcontrol->private_value & 0xffff;
return tas571x_reg_read_multiword(i2c, index,
ucontrol->value.integer.value, numcoef);
}
static int tas571x_coefficient_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct i2c_client *i2c = to_i2c_client(component->dev);
int numcoef = kcontrol->private_value >> 16;
int index = kcontrol->private_value & 0xffff;
return tas571x_reg_write_multiword(i2c, index,
ucontrol->value.integer.value, numcoef);
}
static int tas571x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int format)
{
struct tas571x_private *priv = snd_soc_component_get_drvdata(dai->component);
priv->format = format;
return 0;
}
static int tas571x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tas571x_private *priv = snd_soc_component_get_drvdata(dai->component);
u32 val;
switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val = 0x00;
break;
case SND_SOC_DAIFMT_I2S:
val = 0x03;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = 0x06;
break;
default:
return -EINVAL;
}
if (params_width(params) >= 24)
val += 2;
else if (params_width(params) >= 20)
val += 1;
return regmap_update_bits(priv->regmap, TAS571X_SDI_REG,
TAS571X_SDI_FMT_MASK, val);
}
static int tas571x_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
u8 sysctl2;
int ret;
sysctl2 = mute ? TAS571X_SYS_CTRL_2_SDN_MASK : 0;
ret = snd_soc_component_update_bits(component,
TAS571X_SYS_CTRL_2_REG,
TAS571X_SYS_CTRL_2_SDN_MASK,
sysctl2);
usleep_range(1000, 2000);
return ret;
}
static int tas571x_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct tas571x_private *priv = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
if (!IS_ERR(priv->mclk)) {
ret = clk_prepare_enable(priv->mclk);
if (ret) {
dev_err(component->dev,
"Failed to enable master clock: %d\n",
ret);
return ret;
}
}
}
break;
case SND_SOC_BIAS_OFF:
if (!IS_ERR(priv->mclk))
clk_disable_unprepare(priv->mclk);
break;
}
return 0;
}
static const struct snd_soc_dai_ops tas571x_dai_ops = {
.set_fmt = tas571x_set_dai_fmt,
.hw_params = tas571x_hw_params,
.mute_stream = tas571x_mute,
.no_capture_mute = 1,
};
#define BIQUAD_COEFS(xname, reg) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = tas571x_coefficient_info, \
.get = tas571x_coefficient_get,\
.put = tas571x_coefficient_put, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.private_value = reg | (5 << 16) }
static const char *const tas5711_supply_names[] = {
"AVDD",
"DVDD",
"PVDD_A",
"PVDD_B",
"PVDD_C",
"PVDD_D",
};
static const DECLARE_TLV_DB_SCALE(tas5711_volume_tlv, -10350, 50, 1);
static const struct snd_kcontrol_new tas5711_controls[] = {
SOC_SINGLE_TLV("Master Volume",
TAS571X_MVOL_REG,
0, 0xff, 1, tas5711_volume_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume",
TAS571X_CH1_VOL_REG,
TAS571X_CH2_VOL_REG,
0, 0xff, 1, tas5711_volume_tlv),
SOC_DOUBLE("Speaker Switch",
TAS571X_SOFT_MUTE_REG,
TAS571X_SOFT_MUTE_CH1_SHIFT, TAS571X_SOFT_MUTE_CH2_SHIFT,
1, 1),
};
static const struct regmap_range tas571x_readonly_regs_range[] = {
regmap_reg_range(TAS571X_CLK_CTRL_REG, TAS571X_DEV_ID_REG),
};
static const struct regmap_range tas571x_volatile_regs_range[] = {
regmap_reg_range(TAS571X_CLK_CTRL_REG, TAS571X_ERR_STATUS_REG),
regmap_reg_range(TAS571X_OSC_TRIM_REG, TAS571X_OSC_TRIM_REG),
};
static const struct regmap_access_table tas571x_write_regs = {
.no_ranges = tas571x_readonly_regs_range,
.n_no_ranges = ARRAY_SIZE(tas571x_readonly_regs_range),
};
static const struct regmap_access_table tas571x_volatile_regs = {
.yes_ranges = tas571x_volatile_regs_range,
.n_yes_ranges = ARRAY_SIZE(tas571x_volatile_regs_range),
};
static const struct reg_default tas5711_reg_defaults[] = {
{ 0x04, 0x05 },
{ 0x05, 0x40 },
{ 0x06, 0x00 },
{ 0x07, 0xff },
{ 0x08, 0x30 },
{ 0x09, 0x30 },
{ 0x1b, 0x82 },
};
static const struct regmap_config tas5711_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.max_register = 0xff,
.reg_read = tas571x_reg_read,
.reg_write = tas571x_reg_write,
.reg_defaults = tas5711_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas5711_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.wr_table = &tas571x_write_regs,
.volatile_table = &tas571x_volatile_regs,
};
static const struct tas571x_chip tas5711_chip = {
.supply_names = tas5711_supply_names,
.num_supply_names = ARRAY_SIZE(tas5711_supply_names),
.controls = tas5711_controls,
.num_controls = ARRAY_SIZE(tas5711_controls),
.regmap_config = &tas5711_regmap_config,
.vol_reg_size = 1,
};
static const struct regmap_range tas5707_volatile_regs_range[] = {
regmap_reg_range(TAS571X_CLK_CTRL_REG, TAS571X_ERR_STATUS_REG),
regmap_reg_range(TAS571X_OSC_TRIM_REG, TAS571X_OSC_TRIM_REG),
regmap_reg_range(TAS5707_CH1_BQ0_REG, TAS5707_CH2_BQ6_REG),
};
static const struct regmap_access_table tas5707_volatile_regs = {
.yes_ranges = tas5707_volatile_regs_range,
.n_yes_ranges = ARRAY_SIZE(tas5707_volatile_regs_range),
};
static const DECLARE_TLV_DB_SCALE(tas5707_volume_tlv, -7900, 50, 1);
static const char * const tas5707_volume_slew_step_txt[] = {
"256", "512", "1024", "2048",
};
static const unsigned int tas5707_volume_slew_step_values[] = {
3, 0, 1, 2,
};
static SOC_VALUE_ENUM_SINGLE_DECL(tas5707_volume_slew_step_enum,
TAS571X_VOL_CFG_REG, 0, 0x3,
tas5707_volume_slew_step_txt,
tas5707_volume_slew_step_values);
static const struct snd_kcontrol_new tas5707_controls[] = {
SOC_SINGLE_TLV("Master Volume",
TAS571X_MVOL_REG,
0, 0xff, 1, tas5707_volume_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume",
TAS571X_CH1_VOL_REG,
TAS571X_CH2_VOL_REG,
0, 0xff, 1, tas5707_volume_tlv),
SOC_DOUBLE("Speaker Switch",
TAS571X_SOFT_MUTE_REG,
TAS571X_SOFT_MUTE_CH1_SHIFT, TAS571X_SOFT_MUTE_CH2_SHIFT,
1, 1),
SOC_ENUM("Slew Rate Steps", tas5707_volume_slew_step_enum),
BIQUAD_COEFS("CH1 - Biquad 0", TAS5707_CH1_BQ0_REG),
BIQUAD_COEFS("CH1 - Biquad 1", TAS5707_CH1_BQ1_REG),
BIQUAD_COEFS("CH1 - Biquad 2", TAS5707_CH1_BQ2_REG),
BIQUAD_COEFS("CH1 - Biquad 3", TAS5707_CH1_BQ3_REG),
BIQUAD_COEFS("CH1 - Biquad 4", TAS5707_CH1_BQ4_REG),
BIQUAD_COEFS("CH1 - Biquad 5", TAS5707_CH1_BQ5_REG),
BIQUAD_COEFS("CH1 - Biquad 6", TAS5707_CH1_BQ6_REG),
BIQUAD_COEFS("CH2 - Biquad 0", TAS5707_CH2_BQ0_REG),
BIQUAD_COEFS("CH2 - Biquad 1", TAS5707_CH2_BQ1_REG),
BIQUAD_COEFS("CH2 - Biquad 2", TAS5707_CH2_BQ2_REG),
BIQUAD_COEFS("CH2 - Biquad 3", TAS5707_CH2_BQ3_REG),
BIQUAD_COEFS("CH2 - Biquad 4", TAS5707_CH2_BQ4_REG),
BIQUAD_COEFS("CH2 - Biquad 5", TAS5707_CH2_BQ5_REG),
BIQUAD_COEFS("CH2 - Biquad 6", TAS5707_CH2_BQ6_REG),
};
static const struct reg_default tas5707_reg_defaults[] = {
{TAS571X_CLK_CTRL_REG, 0x6c},
{TAS571X_DEV_ID_REG, 0x70},
{TAS571X_ERR_STATUS_REG, 0x00},
{TAS571X_SYS_CTRL_1_REG, 0xa0},
{TAS571X_SDI_REG, 0x05},
{TAS571X_SYS_CTRL_2_REG, 0x40},
{TAS571X_SOFT_MUTE_REG, 0x00},
{TAS571X_MVOL_REG, 0xff},
{TAS571X_CH1_VOL_REG, 0x30},
{TAS571X_CH2_VOL_REG, 0x30},
{TAS571X_VOL_CFG_REG, 0x91},
{TAS571X_MODULATION_LIMIT_REG, 0x02},
{TAS571X_IC_DELAY_CH1_REG, 0xac},
{TAS571X_IC_DELAY_CH2_REG, 0x54},
{TAS571X_IC_DELAY_CH3_REG, 0xac},
{TAS571X_IC_DELAY_CH4_REG, 0x54},
{TAS571X_START_STOP_PERIOD_REG, 0x0f},
{TAS571X_OSC_TRIM_REG, 0x82},
{TAS571X_BKND_ERR_REG, 0x02},
{TAS571X_INPUT_MUX_REG, 0x17772},
{TAS571X_PWM_MUX_REG, 0x1021345},
};
static const struct regmap_config tas5707_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.max_register = 0xff,
.reg_read = tas571x_reg_read,
.reg_write = tas571x_reg_write,
.reg_defaults = tas5707_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas5707_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.wr_table = &tas571x_write_regs,
.volatile_table = &tas5707_volatile_regs,
};
static const struct tas571x_chip tas5707_chip = {
.supply_names = tas5711_supply_names,
.num_supply_names = ARRAY_SIZE(tas5711_supply_names),
.controls = tas5707_controls,
.num_controls = ARRAY_SIZE(tas5707_controls),
.regmap_config = &tas5707_regmap_config,
.vol_reg_size = 1,
};
static const char *const tas5717_supply_names[] = {
"AVDD",
"DVDD",
"HPVDD",
"PVDD_AB",
"PVDD_CD",
};
static const DECLARE_TLV_DB_SCALE(tas5717_volume_tlv, -10375, 25, 0);
static const struct snd_kcontrol_new tas5717_controls[] = {
/* MVOL LSB is ignored - see comments in tas571x_i2c_probe() */
SOC_SINGLE_TLV("Master Volume",
TAS571X_MVOL_REG, 1, 0x1ff, 1,
tas5717_volume_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume",
TAS571X_CH1_VOL_REG, TAS571X_CH2_VOL_REG,
1, 0x1ff, 1, tas5717_volume_tlv),
SOC_DOUBLE("Speaker Switch",
TAS571X_SOFT_MUTE_REG,
TAS571X_SOFT_MUTE_CH1_SHIFT, TAS571X_SOFT_MUTE_CH2_SHIFT,
1, 1),
SOC_DOUBLE_R_RANGE("CH1 Mixer Volume",
TAS5717_CH1_LEFT_CH_MIX_REG,
TAS5717_CH1_RIGHT_CH_MIX_REG,
16, 0, 0x80, 0),
SOC_DOUBLE_R_RANGE("CH2 Mixer Volume",
TAS5717_CH2_LEFT_CH_MIX_REG,
TAS5717_CH2_RIGHT_CH_MIX_REG,
16, 0, 0x80, 0),
/*
* The biquads are named according to the register names.
* Please note that TI's TAS57xx Graphical Development Environment
* tool names them different.
*/
BIQUAD_COEFS("CH1 - Biquad 0", TAS5717_CH1_BQ0_REG),
BIQUAD_COEFS("CH1 - Biquad 1", TAS5717_CH1_BQ1_REG),
BIQUAD_COEFS("CH1 - Biquad 2", TAS5717_CH1_BQ2_REG),
BIQUAD_COEFS("CH1 - Biquad 3", TAS5717_CH1_BQ3_REG),
BIQUAD_COEFS("CH1 - Biquad 4", TAS5717_CH1_BQ4_REG),
BIQUAD_COEFS("CH1 - Biquad 5", TAS5717_CH1_BQ5_REG),
BIQUAD_COEFS("CH1 - Biquad 6", TAS5717_CH1_BQ6_REG),
BIQUAD_COEFS("CH1 - Biquad 7", TAS5717_CH1_BQ7_REG),
BIQUAD_COEFS("CH1 - Biquad 8", TAS5717_CH1_BQ8_REG),
BIQUAD_COEFS("CH1 - Biquad 9", TAS5717_CH1_BQ9_REG),
BIQUAD_COEFS("CH1 - Biquad 10", TAS5717_CH1_BQ10_REG),
BIQUAD_COEFS("CH1 - Biquad 11", TAS5717_CH1_BQ11_REG),
BIQUAD_COEFS("CH2 - Biquad 0", TAS5717_CH2_BQ0_REG),
BIQUAD_COEFS("CH2 - Biquad 1", TAS5717_CH2_BQ1_REG),
BIQUAD_COEFS("CH2 - Biquad 2", TAS5717_CH2_BQ2_REG),
BIQUAD_COEFS("CH2 - Biquad 3", TAS5717_CH2_BQ3_REG),
BIQUAD_COEFS("CH2 - Biquad 4", TAS5717_CH2_BQ4_REG),
BIQUAD_COEFS("CH2 - Biquad 5", TAS5717_CH2_BQ5_REG),
BIQUAD_COEFS("CH2 - Biquad 6", TAS5717_CH2_BQ6_REG),
BIQUAD_COEFS("CH2 - Biquad 7", TAS5717_CH2_BQ7_REG),
BIQUAD_COEFS("CH2 - Biquad 8", TAS5717_CH2_BQ8_REG),
BIQUAD_COEFS("CH2 - Biquad 9", TAS5717_CH2_BQ9_REG),
BIQUAD_COEFS("CH2 - Biquad 10", TAS5717_CH2_BQ10_REG),
BIQUAD_COEFS("CH2 - Biquad 11", TAS5717_CH2_BQ11_REG),
BIQUAD_COEFS("CH3 - Biquad 0", TAS5717_CH3_BQ0_REG),
BIQUAD_COEFS("CH3 - Biquad 1", TAS5717_CH3_BQ1_REG),
BIQUAD_COEFS("CH4 - Biquad 0", TAS5717_CH4_BQ0_REG),
BIQUAD_COEFS("CH4 - Biquad 1", TAS5717_CH4_BQ1_REG),
};
static const struct reg_default tas5717_reg_defaults[] = {
{ 0x04, 0x05 },
{ 0x05, 0x40 },
{ 0x06, 0x00 },
{ 0x07, 0x03ff },
{ 0x08, 0x00c0 },
{ 0x09, 0x00c0 },
{ 0x1b, 0x82 },
{ TAS5717_CH1_RIGHT_CH_MIX_REG, 0x0 },
{ TAS5717_CH1_LEFT_CH_MIX_REG, 0x800000},
{ TAS5717_CH2_LEFT_CH_MIX_REG, 0x0 },
{ TAS5717_CH2_RIGHT_CH_MIX_REG, 0x800000},
};
static const struct regmap_config tas5717_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.max_register = 0xff,
.reg_read = tas571x_reg_read,
.reg_write = tas571x_reg_write,
.reg_defaults = tas5717_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas5717_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.wr_table = &tas571x_write_regs,
.volatile_table = &tas571x_volatile_regs,
};
/* This entry is reused for tas5719 as the software interface is identical. */
static const struct tas571x_chip tas5717_chip = {
.supply_names = tas5717_supply_names,
.num_supply_names = ARRAY_SIZE(tas5717_supply_names),
.controls = tas5717_controls,
.num_controls = ARRAY_SIZE(tas5717_controls),
.regmap_config = &tas5717_regmap_config,
.vol_reg_size = 2,
};
static const char *const tas5721_supply_names[] = {
"AVDD",
"DVDD",
"DRVDD",
"PVDD",
};
static const struct snd_kcontrol_new tas5721_controls[] = {
SOC_SINGLE_TLV("Master Volume",
TAS571X_MVOL_REG,
0, 0xff, 1, tas5711_volume_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume",
TAS571X_CH1_VOL_REG,
TAS571X_CH2_VOL_REG,
0, 0xff, 1, tas5711_volume_tlv),
SOC_DOUBLE("Speaker Switch",
TAS571X_SOFT_MUTE_REG,
TAS571X_SOFT_MUTE_CH1_SHIFT, TAS571X_SOFT_MUTE_CH2_SHIFT,
1, 1),
};
static const struct reg_default tas5721_reg_defaults[] = {
{TAS571X_CLK_CTRL_REG, 0x6c},
{TAS571X_DEV_ID_REG, 0x00},
{TAS571X_ERR_STATUS_REG, 0x00},
{TAS571X_SYS_CTRL_1_REG, 0xa0},
{TAS571X_SDI_REG, 0x05},
{TAS571X_SYS_CTRL_2_REG, 0x40},
{TAS571X_SOFT_MUTE_REG, 0x00},
{TAS571X_MVOL_REG, 0xff},
{TAS571X_CH1_VOL_REG, 0x30},
{TAS571X_CH2_VOL_REG, 0x30},
{TAS571X_CH3_VOL_REG, 0x30},
{TAS571X_VOL_CFG_REG, 0x91},
{TAS571X_MODULATION_LIMIT_REG, 0x02},
{TAS571X_IC_DELAY_CH1_REG, 0xac},
{TAS571X_IC_DELAY_CH2_REG, 0x54},
{TAS571X_IC_DELAY_CH3_REG, 0xac},
{TAS571X_IC_DELAY_CH4_REG, 0x54},
{TAS571X_PWM_CH_SDN_GROUP_REG, 0x30},
{TAS571X_START_STOP_PERIOD_REG, 0x0f},
{TAS571X_OSC_TRIM_REG, 0x82},
{TAS571X_BKND_ERR_REG, 0x02},
{TAS571X_INPUT_MUX_REG, 0x17772},
{TAS571X_CH4_SRC_SELECT_REG, 0x4303},
{TAS571X_PWM_MUX_REG, 0x1021345},
};
static const struct regmap_config tas5721_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.max_register = 0xff,
.reg_read = tas571x_reg_read,
.reg_write = tas571x_reg_write,
.reg_defaults = tas5721_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas5721_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.wr_table = &tas571x_write_regs,
.volatile_table = &tas571x_volatile_regs,
};
static const char *const tas5733_supply_names[] = {
"AVDD",
"DVDD",
"PVDD",
};
static const struct reg_default tas5733_reg_defaults[] = {
{TAS571X_CLK_CTRL_REG, 0x6c},
{TAS571X_DEV_ID_REG, 0x00},
{TAS571X_ERR_STATUS_REG, 0x00},
{TAS571X_SYS_CTRL_1_REG, 0xa0},
{TAS571X_SDI_REG, 0x05},
{TAS571X_SYS_CTRL_2_REG, 0x40},
{TAS571X_SOFT_MUTE_REG, 0x07},
{TAS571X_MVOL_REG, 0x03ff},
{TAS571X_CH1_VOL_REG, 0x00c0},
{TAS571X_CH2_VOL_REG, 0x00c0},
{TAS571X_CH3_VOL_REG, 0x00c0},
{TAS571X_VOL_CFG_REG, 0xf0},
{TAS571X_MODULATION_LIMIT_REG, 0x07},
{TAS571X_IC_DELAY_CH1_REG, 0xb8},
{TAS571X_IC_DELAY_CH2_REG, 0x60},
{TAS571X_IC_DELAY_CH3_REG, 0xa0},
{TAS571X_IC_DELAY_CH4_REG, 0x48},
{TAS571X_PWM_CH_SDN_GROUP_REG, 0x30},
{TAS571X_START_STOP_PERIOD_REG, 0x68},
{TAS571X_OSC_TRIM_REG, 0x82},
{TAS571X_BKND_ERR_REG, 0x02},
{TAS571X_INPUT_MUX_REG, 0x00897772},
{TAS571X_PWM_MUX_REG, 0x01021345},
{TAS5717_CH1_RIGHT_CH_MIX_REG, 0x00},
{TAS5717_CH1_LEFT_CH_MIX_REG, 0x800000},
{TAS5717_CH2_LEFT_CH_MIX_REG, 0x00},
{TAS5717_CH2_RIGHT_CH_MIX_REG, 0x800000},
};
static const struct regmap_config tas5733_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.max_register = 0xff,
.reg_read = tas571x_reg_read,
.reg_write = tas571x_reg_write,
.reg_defaults = tas5733_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tas5733_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.wr_table = &tas571x_write_regs,
.volatile_table = &tas571x_volatile_regs,
};
static const struct tas571x_chip tas5733_chip = {
.supply_names = tas5733_supply_names,
.num_supply_names = ARRAY_SIZE(tas5733_supply_names),
.controls = tas5717_controls,
.num_controls = ARRAY_SIZE(tas5717_controls),
.regmap_config = &tas5733_regmap_config,
.vol_reg_size = 2,
};
static const struct tas571x_chip tas5721_chip = {
.supply_names = tas5721_supply_names,
.num_supply_names = ARRAY_SIZE(tas5721_supply_names),
.controls = tas5721_controls,
.num_controls = ARRAY_SIZE(tas5721_controls),
.regmap_config = &tas5721_regmap_config,
.vol_reg_size = 1,
};
static const struct snd_soc_dapm_widget tas571x_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("OUT_A"),
SND_SOC_DAPM_OUTPUT("OUT_B"),
SND_SOC_DAPM_OUTPUT("OUT_C"),
SND_SOC_DAPM_OUTPUT("OUT_D"),
};
static const struct snd_soc_dapm_route tas571x_dapm_routes[] = {
{ "DACL", NULL, "Playback" },
{ "DACR", NULL, "Playback" },
{ "OUT_A", NULL, "DACL" },
{ "OUT_B", NULL, "DACL" },
{ "OUT_C", NULL, "DACR" },
{ "OUT_D", NULL, "DACR" },
};
static const struct snd_soc_component_driver tas571x_component = {
.set_bias_level = tas571x_set_bias_level,
.dapm_widgets = tas571x_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tas571x_dapm_widgets),
.dapm_routes = tas571x_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(tas571x_dapm_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver tas571x_dai = {
.name = "tas571x-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tas571x_dai_ops,
};
static const struct of_device_id tas571x_of_match[] __maybe_unused;
static const struct i2c_device_id tas571x_i2c_id[];
static int tas571x_i2c_probe(struct i2c_client *client)
{
struct tas571x_private *priv;
struct device *dev = &client->dev;
const struct of_device_id *of_id;
int i, ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
i2c_set_clientdata(client, priv);
of_id = of_match_device(tas571x_of_match, dev);
if (of_id)
priv->chip = of_id->data;
else {
const struct i2c_device_id *id =
i2c_match_id(tas571x_i2c_id, client);
priv->chip = (void *) id->driver_data;
}
priv->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(priv->mclk) && PTR_ERR(priv->mclk) != -ENOENT) {
dev_err(dev, "Failed to request mclk: %ld\n",
PTR_ERR(priv->mclk));
return PTR_ERR(priv->mclk);
}
if (WARN_ON(priv->chip->num_supply_names > TAS571X_MAX_SUPPLIES))
return -EINVAL;
for (i = 0; i < priv->chip->num_supply_names; i++)
priv->supplies[i].supply = priv->chip->supply_names[i];
ret = devm_regulator_bulk_get(dev, priv->chip->num_supply_names,
priv->supplies);
if (ret) {
dev_err(dev, "Failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(priv->chip->num_supply_names,
priv->supplies);
if (ret) {
dev_err(dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
priv->regmap = devm_regmap_init(dev, NULL, client,
priv->chip->regmap_config);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
goto disable_regs;
}
priv->pdn_gpio = devm_gpiod_get_optional(dev, "pdn", GPIOD_OUT_LOW);
if (IS_ERR(priv->pdn_gpio)) {
dev_err(dev, "error requesting pdn_gpio: %ld\n",
PTR_ERR(priv->pdn_gpio));
ret = PTR_ERR(priv->pdn_gpio);
goto disable_regs;
}
priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(priv->reset_gpio)) {
dev_err(dev, "error requesting reset_gpio: %ld\n",
PTR_ERR(priv->reset_gpio));
ret = PTR_ERR(priv->reset_gpio);
goto disable_regs;
} else if (priv->reset_gpio) {
/* pulse the active low reset line for ~100us */
usleep_range(100, 200);
gpiod_set_value(priv->reset_gpio, 0);
usleep_range(13500, 20000);
}
ret = regmap_write(priv->regmap, TAS571X_OSC_TRIM_REG, 0);
if (ret)
goto disable_regs;
usleep_range(50000, 60000);
memcpy(&priv->component_driver, &tas571x_component, sizeof(priv->component_driver));
priv->component_driver.controls = priv->chip->controls;
priv->component_driver.num_controls = priv->chip->num_controls;
if (priv->chip->vol_reg_size == 2) {
/*
* The master volume defaults to 0x3ff (mute), but we ignore
* (zero) the LSB because the hardware step size is 0.125 dB
* and TLV_DB_SCALE_ITEM has a resolution of 0.01 dB.
*/
ret = regmap_update_bits(priv->regmap, TAS571X_MVOL_REG, 1, 0);
if (ret)
goto disable_regs;
}
ret = devm_snd_soc_register_component(&client->dev,
&priv->component_driver,
&tas571x_dai, 1);
if (ret)
goto disable_regs;
return ret;
disable_regs:
regulator_bulk_disable(priv->chip->num_supply_names, priv->supplies);
return ret;
}
static void tas571x_i2c_remove(struct i2c_client *client)
{
struct tas571x_private *priv = i2c_get_clientdata(client);
regulator_bulk_disable(priv->chip->num_supply_names, priv->supplies);
}
static const struct of_device_id tas571x_of_match[] __maybe_unused = {
{ .compatible = "ti,tas5707", .data = &tas5707_chip, },
{ .compatible = "ti,tas5711", .data = &tas5711_chip, },
{ .compatible = "ti,tas5717", .data = &tas5717_chip, },
{ .compatible = "ti,tas5719", .data = &tas5717_chip, },
{ .compatible = "ti,tas5721", .data = &tas5721_chip, },
{ .compatible = "ti,tas5733", .data = &tas5733_chip, },
{ }
};
MODULE_DEVICE_TABLE(of, tas571x_of_match);
static const struct i2c_device_id tas571x_i2c_id[] = {
{ "tas5707", (kernel_ulong_t) &tas5707_chip },
{ "tas5711", (kernel_ulong_t) &tas5711_chip },
{ "tas5717", (kernel_ulong_t) &tas5717_chip },
{ "tas5719", (kernel_ulong_t) &tas5717_chip },
{ "tas5721", (kernel_ulong_t) &tas5721_chip },
{ "tas5733", (kernel_ulong_t) &tas5733_chip },
{ }
};
MODULE_DEVICE_TABLE(i2c, tas571x_i2c_id);
static struct i2c_driver tas571x_i2c_driver = {
.driver = {
.name = "tas571x",
.of_match_table = of_match_ptr(tas571x_of_match),
},
.probe = tas571x_i2c_probe,
.remove = tas571x_i2c_remove,
.id_table = tas571x_i2c_id,
};
module_i2c_driver(tas571x_i2c_driver);
MODULE_DESCRIPTION("ASoC TAS571x driver");
MODULE_AUTHOR("Kevin Cernekee <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/tas571x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for ADAU1361/ADAU1461/ADAU1761/ADAU1961 codec
*
* Copyright 2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "adau1761.h"
static const struct i2c_device_id adau1761_i2c_ids[];
static int adau1761_i2c_probe(struct i2c_client *client)
{
struct regmap_config config;
const struct i2c_device_id *id = i2c_match_id(adau1761_i2c_ids, client);
config = adau1761_regmap_config;
config.val_bits = 8;
config.reg_bits = 16;
return adau1761_probe(&client->dev,
devm_regmap_init_i2c(client, &config),
id->driver_data, NULL);
}
static void adau1761_i2c_remove(struct i2c_client *client)
{
adau17x1_remove(&client->dev);
}
static const struct i2c_device_id adau1761_i2c_ids[] = {
{ "adau1361", ADAU1361 },
{ "adau1461", ADAU1761 },
{ "adau1761", ADAU1761 },
{ "adau1961", ADAU1361 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adau1761_i2c_ids);
#if defined(CONFIG_OF)
static const struct of_device_id adau1761_i2c_dt_ids[] = {
{ .compatible = "adi,adau1361", },
{ .compatible = "adi,adau1461", },
{ .compatible = "adi,adau1761", },
{ .compatible = "adi,adau1961", },
{ },
};
MODULE_DEVICE_TABLE(of, adau1761_i2c_dt_ids);
#endif
static struct i2c_driver adau1761_i2c_driver = {
.driver = {
.name = "adau1761",
.of_match_table = of_match_ptr(adau1761_i2c_dt_ids),
},
.probe = adau1761_i2c_probe,
.remove = adau1761_i2c_remove,
.id_table = adau1761_i2c_ids,
};
module_i2c_driver(adau1761_i2c_driver);
MODULE_DESCRIPTION("ASoC ADAU1361/ADAU1461/ADAU1761/ADAU1961 CODEC I2C driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adau1761-i2c.c |
// SPDX-License-Identifier: GPL-2.0
//
// cs35l41.c -- CS35l41 ALSA SoC audio driver
//
// Copyright 2017-2021 Cirrus Logic, Inc.
//
// Author: David Rhodes <[email protected]>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "cs35l41.h"
static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
"VA",
"VP",
};
struct cs35l41_pll_sysclk_config {
int freq;
int clk_cfg;
};
static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
{ 32768, 0x00 },
{ 8000, 0x01 },
{ 11025, 0x02 },
{ 12000, 0x03 },
{ 16000, 0x04 },
{ 22050, 0x05 },
{ 24000, 0x06 },
{ 32000, 0x07 },
{ 44100, 0x08 },
{ 48000, 0x09 },
{ 88200, 0x0A },
{ 96000, 0x0B },
{ 128000, 0x0C },
{ 176400, 0x0D },
{ 192000, 0x0E },
{ 256000, 0x0F },
{ 352800, 0x10 },
{ 384000, 0x11 },
{ 512000, 0x12 },
{ 705600, 0x13 },
{ 750000, 0x14 },
{ 768000, 0x15 },
{ 1000000, 0x16 },
{ 1024000, 0x17 },
{ 1200000, 0x18 },
{ 1411200, 0x19 },
{ 1500000, 0x1A },
{ 1536000, 0x1B },
{ 2000000, 0x1C },
{ 2048000, 0x1D },
{ 2400000, 0x1E },
{ 2822400, 0x1F },
{ 3000000, 0x20 },
{ 3072000, 0x21 },
{ 3200000, 0x22 },
{ 4000000, 0x23 },
{ 4096000, 0x24 },
{ 4800000, 0x25 },
{ 5644800, 0x26 },
{ 6000000, 0x27 },
{ 6144000, 0x28 },
{ 6250000, 0x29 },
{ 6400000, 0x2A },
{ 6500000, 0x2B },
{ 6750000, 0x2C },
{ 7526400, 0x2D },
{ 8000000, 0x2E },
{ 8192000, 0x2F },
{ 9600000, 0x30 },
{ 11289600, 0x31 },
{ 12000000, 0x32 },
{ 12288000, 0x33 },
{ 12500000, 0x34 },
{ 12800000, 0x35 },
{ 13000000, 0x36 },
{ 13500000, 0x37 },
{ 19200000, 0x38 },
{ 22579200, 0x39 },
{ 24000000, 0x3A },
{ 24576000, 0x3B },
{ 25000000, 0x3C },
{ 25600000, 0x3D },
{ 26000000, 0x3E },
{ 27000000, 0x3F },
};
struct cs35l41_fs_mon_config {
int freq;
unsigned int fs1;
unsigned int fs2;
};
static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
{ 32768, 2254, 3754 },
{ 8000, 9220, 15364 },
{ 11025, 6148, 10244 },
{ 12000, 6148, 10244 },
{ 16000, 4612, 7684 },
{ 22050, 3076, 5124 },
{ 24000, 3076, 5124 },
{ 32000, 2308, 3844 },
{ 44100, 1540, 2564 },
{ 48000, 1540, 2564 },
{ 88200, 772, 1284 },
{ 96000, 772, 1284 },
{ 128000, 580, 964 },
{ 176400, 388, 644 },
{ 192000, 388, 644 },
{ 256000, 292, 484 },
{ 352800, 196, 324 },
{ 384000, 196, 324 },
{ 512000, 148, 244 },
{ 705600, 100, 164 },
{ 750000, 100, 164 },
{ 768000, 100, 164 },
{ 1000000, 76, 124 },
{ 1024000, 76, 124 },
{ 1200000, 64, 104 },
{ 1411200, 52, 84 },
{ 1500000, 52, 84 },
{ 1536000, 52, 84 },
{ 2000000, 40, 64 },
{ 2048000, 40, 64 },
{ 2400000, 34, 54 },
{ 2822400, 28, 44 },
{ 3000000, 28, 44 },
{ 3072000, 28, 44 },
{ 3200000, 27, 42 },
{ 4000000, 22, 34 },
{ 4096000, 22, 34 },
{ 4800000, 19, 29 },
{ 5644800, 16, 24 },
{ 6000000, 16, 24 },
{ 6144000, 16, 24 },
{ 12288000, 0, 0 },
};
static int cs35l41_get_fs_mon_config_index(int freq)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
if (cs35l41_fs_mon[i].freq == freq)
return i;
}
return -EINVAL;
}
static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0);
static const struct snd_kcontrol_new dre_ctrl =
SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
static const char * const cs35l41_pcm_sftramp_text[] = {
"Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
};
static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
CS35L41_AMP_DIG_VOL_CTRL, 0,
cs35l41_pcm_sftramp_text);
static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
int ret;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (cs35l41->dsp.cs_dsp.booted)
return 0;
return wm_adsp_early_event(w, kcontrol, event);
case SND_SOC_DAPM_PRE_PMD:
if (cs35l41->dsp.preloaded)
return 0;
if (cs35l41->dsp.cs_dsp.running) {
ret = wm_adsp_event(w, kcontrol, event);
if (ret)
return ret;
}
return wm_adsp_early_event(w, kcontrol, event);
default:
return 0;
}
}
static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
unsigned int fw_status;
int ret;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (!cs35l41->dsp.cs_dsp.running)
return wm_adsp_event(w, kcontrol, event);
ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status);
if (ret < 0) {
dev_err(cs35l41->dev,
"Failed to read firmware status: %d\n", ret);
return ret;
}
switch (fw_status) {
case CSPL_MBOX_STS_RUNNING:
case CSPL_MBOX_STS_PAUSED:
break;
default:
dev_err(cs35l41->dev, "Firmware status is invalid: %u\n",
fw_status);
return -EINVAL;
}
return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
CSPL_MBOX_CMD_RESUME);
case SND_SOC_DAPM_PRE_PMD:
return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
CSPL_MBOX_CMD_PAUSE);
default:
return 0;
}
}
static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
CS35L41_DAC_PCM1_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_pcm_source_texts,
cs35l41_pcm_source_values);
static const struct snd_kcontrol_new pcm_source_mux =
SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
static const char * const cs35l41_tx_input_texts[] = {
"Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
"VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
};
static const unsigned int cs35l41_tx_input_values[] = {
0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
};
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
CS35L41_ASP_TX1_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx1_mux =
SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
CS35L41_ASP_TX2_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx2_mux =
SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
CS35L41_ASP_TX3_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx3_mux =
SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
CS35L41_ASP_TX4_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new asp_tx4_mux =
SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum,
CS35L41_DSP1_RX1_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new dsp_rx1_mux =
SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum,
CS35L41_DSP1_RX2_SRC,
0, CS35L41_ASP_SOURCE_MASK,
cs35l41_tx_input_texts,
cs35l41_tx_input_values);
static const struct snd_kcontrol_new dsp_rx2_mux =
SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum);
static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
3, 0x4CF, 0x391, dig_vol_tlv),
SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
amp_gain_tlv),
SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
SOC_SINGLE("Aux Noise Gate CH1 Switch",
CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
SOC_SINGLE("Aux Noise Gate CH1 Threshold",
CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
SOC_SINGLE("Aux Noise Gate CH2 Switch",
CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
SOC_SINGLE("Aux Noise Gate CH2 Threshold",
CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
WM_ADSP_FW_CONTROL("DSP1", 0),
};
static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable)
{
switch (cs35l41->hw_cfg.bst_type) {
case CS35L41_INT_BOOST:
case CS35L41_SHD_BOOST_ACTV:
enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF;
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
enable << CS35L41_BST_EN_SHIFT);
break;
default:
break;
}
}
static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit,
unsigned int rel_err_bit)
{
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit);
regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit);
regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0);
}
static irqreturn_t cs35l41_irq(int irq, void *data)
{
struct cs35l41_private *cs35l41 = data;
unsigned int status[4] = { 0, 0, 0, 0 };
unsigned int masks[4] = { 0, 0, 0, 0 };
int ret = IRQ_NONE;
unsigned int i;
pm_runtime_get_sync(cs35l41->dev);
for (i = 0; i < ARRAY_SIZE(status); i++) {
regmap_read(cs35l41->regmap,
CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
&status[i]);
regmap_read(cs35l41->regmap,
CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
&masks[i]);
}
/* Check to see if unmasked bits are active */
if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
!(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
goto done;
if (status[3] & CS35L41_OTP_BOOT_DONE) {
regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
}
/*
* The following interrupts require a
* protection release cycle to get the
* speaker out of Safe-Mode.
*/
if (status[0] & CS35L41_AMP_SHORT_ERR) {
dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_TEMP_WARN) {
dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_TEMP_ERR) {
dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_BST_OVP_ERR) {
dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
cs35l41_boost_enable(cs35l41, 0);
cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS);
cs35l41_boost_enable(cs35l41, 1);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
cs35l41_boost_enable(cs35l41, 0);
cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS);
cs35l41_boost_enable(cs35l41, 1);
ret = IRQ_HANDLED;
}
if (status[0] & CS35L41_BST_SHORT_ERR) {
dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
cs35l41_boost_enable(cs35l41, 0);
cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS);
cs35l41_boost_enable(cs35l41, 1);
ret = IRQ_HANDLED;
}
if (status[2] & CS35L41_PLL_LOCK) {
regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK);
complete(&cs35l41->pll_lock);
ret = IRQ_HANDLED;
}
done:
pm_runtime_mark_last_busy(cs35l41->dev);
pm_runtime_put_autosuspend(cs35l41->dev);
return ret;
}
static const struct reg_sequence cs35l41_pup_patch[] = {
{ CS35L41_TEST_KEY_CTL, 0x00000055 },
{ CS35L41_TEST_KEY_CTL, 0x000000AA },
{ 0x00002084, 0x002F1AA0 },
{ CS35L41_TEST_KEY_CTL, 0x000000CC },
{ CS35L41_TEST_KEY_CTL, 0x00000033 },
};
static const struct reg_sequence cs35l41_pdn_patch[] = {
{ CS35L41_TEST_KEY_CTL, 0x00000055 },
{ CS35L41_TEST_KEY_CTL, 0x000000AA },
{ 0x00002084, 0x002F1AA3 },
{ CS35L41_TEST_KEY_CTL, 0x000000CC },
{ CS35L41_TEST_KEY_CTL, 0x00000033 },
};
static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_multi_reg_write_bypassed(cs35l41->regmap,
cs35l41_pup_patch,
ARRAY_SIZE(cs35l41_pup_patch));
ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
1, &cs35l41->pll_lock, cs35l41->dsp.cs_dsp.running);
break;
case SND_SOC_DAPM_POST_PMD:
ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
0, &cs35l41->pll_lock, cs35l41->dsp.cs_dsp.running);
regmap_multi_reg_write_bypassed(cs35l41->regmap,
cs35l41_pdn_patch,
ARRAY_SIZE(cs35l41_pdn_patch));
break;
default:
dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
ret = -EINVAL;
}
return ret;
}
static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
cs35l41_dsp_preload_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
cs35l41_dsp_audio_ev,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_OUTPUT("SPK"),
SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
SND_SOC_DAPM_SIGGEN("VSENSE"),
SND_SOC_DAPM_SIGGEN("ISENSE"),
SND_SOC_DAPM_SIGGEN("VP"),
SND_SOC_DAPM_SIGGEN("VBST"),
SND_SOC_DAPM_SIGGEN("TEMP"),
SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0),
SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
cs35l41_main_amp_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux),
SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux),
SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
};
static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
{"DSP RX1 Source", "ASPRX1", "ASPRX1"},
{"DSP RX1 Source", "ASPRX2", "ASPRX2"},
{"DSP RX2 Source", "ASPRX1", "ASPRX1"},
{"DSP RX2 Source", "ASPRX2", "ASPRX2"},
{"DSP1", NULL, "DSP RX1 Source"},
{"DSP1", NULL, "DSP RX2 Source"},
{"ASP TX1 Source", "VMON", "VMON ADC"},
{"ASP TX1 Source", "IMON", "IMON ADC"},
{"ASP TX1 Source", "VPMON", "VPMON ADC"},
{"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX1 Source", "DSPTX1", "DSP1"},
{"ASP TX1 Source", "DSPTX2", "DSP1"},
{"ASP TX1 Source", "ASPRX1", "ASPRX1" },
{"ASP TX1 Source", "ASPRX2", "ASPRX2" },
{"ASP TX2 Source", "VMON", "VMON ADC"},
{"ASP TX2 Source", "IMON", "IMON ADC"},
{"ASP TX2 Source", "VPMON", "VPMON ADC"},
{"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX2 Source", "DSPTX1", "DSP1"},
{"ASP TX2 Source", "DSPTX2", "DSP1"},
{"ASP TX2 Source", "ASPRX1", "ASPRX1" },
{"ASP TX2 Source", "ASPRX2", "ASPRX2" },
{"ASP TX3 Source", "VMON", "VMON ADC"},
{"ASP TX3 Source", "IMON", "IMON ADC"},
{"ASP TX3 Source", "VPMON", "VPMON ADC"},
{"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX3 Source", "DSPTX1", "DSP1"},
{"ASP TX3 Source", "DSPTX2", "DSP1"},
{"ASP TX3 Source", "ASPRX1", "ASPRX1" },
{"ASP TX3 Source", "ASPRX2", "ASPRX2" },
{"ASP TX4 Source", "VMON", "VMON ADC"},
{"ASP TX4 Source", "IMON", "IMON ADC"},
{"ASP TX4 Source", "VPMON", "VPMON ADC"},
{"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
{"ASP TX4 Source", "DSPTX1", "DSP1"},
{"ASP TX4 Source", "DSPTX2", "DSP1"},
{"ASP TX4 Source", "ASPRX1", "ASPRX1" },
{"ASP TX4 Source", "ASPRX2", "ASPRX2" },
{"ASPTX1", NULL, "ASP TX1 Source"},
{"ASPTX2", NULL, "ASP TX2 Source"},
{"ASPTX3", NULL, "ASP TX3 Source"},
{"ASPTX4", NULL, "ASP TX4 Source"},
{"AMP Capture", NULL, "ASPTX1"},
{"AMP Capture", NULL, "ASPTX2"},
{"AMP Capture", NULL, "ASPTX3"},
{"AMP Capture", NULL, "ASPTX4"},
{"DSP1", NULL, "VMON"},
{"DSP1", NULL, "IMON"},
{"DSP1", NULL, "VPMON"},
{"DSP1", NULL, "VBSTMON"},
{"DSP1", NULL, "TEMPMON"},
{"VMON ADC", NULL, "VMON"},
{"IMON ADC", NULL, "IMON"},
{"VPMON ADC", NULL, "VPMON"},
{"VBSTMON ADC", NULL, "VBSTMON"},
{"TEMPMON ADC", NULL, "TEMPMON"},
{"VMON ADC", NULL, "VSENSE"},
{"IMON ADC", NULL, "ISENSE"},
{"VPMON ADC", NULL, "VP"},
{"VBSTMON ADC", NULL, "VBST"},
{"TEMPMON ADC", NULL, "TEMP"},
{"DSP1 Preload", NULL, "DSP1 Preloader"},
{"DSP1", NULL, "DSP1 Preloader"},
{"ASPRX1", NULL, "AMP Playback"},
{"ASPRX2", NULL, "AMP Playback"},
{"DRE", "Switch", "CLASS H"},
{"Main AMP", NULL, "CLASS H"},
{"Main AMP", NULL, "DRE"},
{"SPK", NULL, "Main AMP"},
{"PCM Source", "ASP", "ASPRX1"},
{"PCM Source", "DSP", "DSP1"},
{"CLASS H", NULL, "PCM Source"},
};
static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n,
unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot);
}
static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
unsigned int daifmt = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK;
break;
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
break;
case SND_SOC_DAIFMT_I2S:
daifmt |= 2 << CS35L41_ASP_FMT_SHIFT;
break;
default:
dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
daifmt |= CS35L41_LRCLK_INV_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
daifmt |= CS35L41_SCLK_INV_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK;
break;
case SND_SOC_DAIFMT_NB_NF:
break;
default:
dev_warn(cs35l41->dev, "Invalid DAI clock INV\n");
return -EINVAL;
}
return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK |
CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK |
CS35L41_SCLK_INV_MASK, daifmt);
}
struct cs35l41_global_fs_config {
int rate;
int fs_cfg;
};
static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
{ 12000, 0x01 },
{ 24000, 0x02 },
{ 48000, 0x03 },
{ 96000, 0x04 },
{ 192000, 0x05 },
{ 11025, 0x09 },
{ 22050, 0x0A },
{ 44100, 0x0B },
{ 88200, 0x0C },
{ 176400, 0x0D },
{ 8000, 0x11 },
{ 16000, 0x12 },
{ 32000, 0x13 },
};
static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
unsigned int rate = params_rate(params);
u8 asp_wl;
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
if (rate == cs35l41_fs_rates[i].rate)
break;
}
if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate);
return -EINVAL;
}
asp_wl = params_width(params);
if (i < ARRAY_SIZE(cs35l41_fs_rates))
regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
CS35L41_GLOBAL_FS_MASK,
cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_ASP_WIDTH_RX_MASK,
asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
CS35L41_ASP_RX_WL_MASK,
asp_wl << CS35L41_ASP_RX_WL_SHIFT);
} else {
regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
CS35L41_ASP_WIDTH_TX_MASK,
asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
CS35L41_ASP_TX_WL_MASK,
asp_wl << CS35L41_ASP_TX_WL_SHIFT);
}
return 0;
}
static int cs35l41_get_clk_config(int freq)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
if (cs35l41_pll_sysclk[i].freq == freq)
return cs35l41_pll_sysclk[i].clk_cfg;
}
return -EINVAL;
}
static const unsigned int cs35l41_src_rates[] = {
8000, 12000, 11025, 16000, 22050, 24000, 32000,
44100, 48000, 88200, 96000, 176400, 192000
};
static const struct snd_pcm_hw_constraint_list cs35l41_constraints = {
.count = ARRAY_SIZE(cs35l41_src_rates),
.list = cs35l41_src_rates,
};
static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
reinit_completion(&cs35l41->pll_lock);
if (substream->runtime)
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&cs35l41_constraints);
return 0;
}
static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source,
unsigned int freq, int dir)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
int extclk_cfg, clksrc;
switch (clk_id) {
case CS35L41_CLKID_SCLK:
clksrc = CS35L41_PLLSRC_SCLK;
break;
case CS35L41_CLKID_LRCLK:
clksrc = CS35L41_PLLSRC_LRCLK;
break;
case CS35L41_CLKID_MCLK:
clksrc = CS35L41_PLLSRC_MCLK;
break;
default:
dev_err(cs35l41->dev, "Invalid CLK Config\n");
return -EINVAL;
}
extclk_cfg = cs35l41_get_clk_config(freq);
if (extclk_cfg < 0) {
dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
extclk_cfg, freq);
return -EINVAL;
}
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_OPENLOOP_MASK,
1 << CS35L41_PLL_OPENLOOP_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_REFCLK_FREQ_MASK,
extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_CLK_EN_MASK,
0 << CS35L41_PLL_CLK_EN_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_CLK_SEL_MASK, clksrc);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_OPENLOOP_MASK,
0 << CS35L41_PLL_OPENLOOP_SHIFT);
regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
CS35L41_PLL_CLK_EN_MASK,
1 << CS35L41_PLL_CLK_EN_SHIFT);
return 0;
}
static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
unsigned int fs1_val;
unsigned int fs2_val;
unsigned int val;
int fsindex;
fsindex = cs35l41_get_fs_mon_config_index(freq);
if (fsindex < 0) {
dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
return -EINVAL;
}
dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
if (freq <= 6144000) {
/* Use the lookup table */
fs1_val = cs35l41_fs_mon[fsindex].fs1;
fs2_val = cs35l41_fs_mon[fsindex].fs2;
} else {
/* Use hard-coded values */
fs1_val = 0x10;
fs2_val = 0x24;
}
val = fs1_val;
val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
return 0;
}
static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
{
struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
int ret;
if (!hw_cfg->valid)
return -EINVAL;
if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
return -EINVAL;
/* Required */
ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
if (ret)
return ret;
/* Optional */
if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0)
regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK,
hw_cfg->dout_hiz);
return 0;
}
static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = {
{"Main AMP", NULL, "VSPK"},
};
static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = {
SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0),
};
static int cs35l41_component_probe(struct snd_soc_component *component)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
int ret;
if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) {
ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget,
ARRAY_SIZE(cs35l41_ext_bst_widget));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes,
ARRAY_SIZE(cs35l41_ext_bst_routes));
if (ret)
return ret;
}
return wm_adsp2_component_probe(&cs35l41->dsp, component);
}
static void cs35l41_component_remove(struct snd_soc_component *component)
{
struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
wm_adsp2_component_remove(&cs35l41->dsp, component);
}
static const struct snd_soc_dai_ops cs35l41_ops = {
.startup = cs35l41_pcm_startup,
.set_fmt = cs35l41_set_dai_fmt,
.hw_params = cs35l41_pcm_hw_params,
.set_sysclk = cs35l41_dai_set_sysclk,
.set_channel_map = cs35l41_set_channel_map,
};
static struct snd_soc_dai_driver cs35l41_dai[] = {
{
.name = "cs35l41-pcm",
.id = 0,
.playback = {
.stream_name = "AMP Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L41_RX_FORMATS,
},
.capture = {
.stream_name = "AMP Capture",
.channels_min = 1,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = CS35L41_TX_FORMATS,
},
.ops = &cs35l41_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
.name = "cs35l41-codec",
.probe = cs35l41_component_probe,
.remove = cs35l41_component_remove,
.dapm_widgets = cs35l41_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
.dapm_routes = cs35l41_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
.controls = cs35l41_aud_controls,
.num_controls = ARRAY_SIZE(cs35l41_aud_controls),
.set_sysclk = cs35l41_component_set_sysclk,
.endianness = 1,
};
static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg)
{
struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
unsigned int val;
int ret;
/* Some ACPI systems received the Shared Boost feature before the upstream driver,
* leaving those systems with deprecated _DSD properties.
* To correctly configure those systems add shared-boost-active and shared-boost-passive
* properties mapped to the correct value in boost-type.
* These two are not DT properties and should not be used in new systems designs.
*/
if (device_property_read_bool(dev, "cirrus,shared-boost-active")) {
hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV;
} else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) {
hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS;
} else {
ret = device_property_read_u32(dev, "cirrus,boost-type", &val);
if (ret >= 0)
hw_cfg->bst_type = val;
}
ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
if (ret >= 0)
hw_cfg->bst_ipk = val;
else
hw_cfg->bst_ipk = -1;
ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
if (ret >= 0)
hw_cfg->bst_ind = val;
else
hw_cfg->bst_ind = -1;
ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
if (ret >= 0)
hw_cfg->bst_cap = val;
else
hw_cfg->bst_cap = -1;
ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
if (ret >= 0)
hw_cfg->dout_hiz = val;
else
hw_cfg->dout_hiz = -1;
/* GPIO1 Pin Config */
gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert");
gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable");
ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val);
if (ret >= 0) {
gpio1->func = val;
gpio1->valid = true;
}
/* GPIO2 Pin Config */
gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert");
gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable");
ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val);
if (ret >= 0) {
gpio2->func = val;
gpio2->valid = true;
}
hw_cfg->valid = true;
return 0;
}
static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
{
struct wm_adsp *dsp;
int ret;
dsp = &cs35l41->dsp;
dsp->part = "cs35l41";
dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
dsp->toggle_preload = true;
cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);
ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
if (ret < 0)
return ret;
ret = wm_halo_init(dsp);
if (ret) {
dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret);
return ret;
}
ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC,
CS35L41_INPUT_SRC_VPMON);
if (ret < 0) {
dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret);
goto err_dsp;
}
ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC,
CS35L41_INPUT_SRC_CLASSH);
if (ret < 0) {
dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret);
goto err_dsp;
}
ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,
CS35L41_INPUT_SRC_TEMPMON);
if (ret < 0) {
dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret);
goto err_dsp;
}
ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,
CS35L41_INPUT_SRC_RSVD);
if (ret < 0) {
dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret);
goto err_dsp;
}
return 0;
err_dsp:
wm_adsp2_remove(dsp);
return ret;
}
static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
{
acpi_handle handle = ACPI_HANDLE(cs35l41->dev);
const char *sub;
/* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */
if (!handle)
return 0;
sub = acpi_get_subsystem_id(handle);
if (IS_ERR(sub)) {
/* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */
if (PTR_ERR(sub) == -ENODATA)
return 0;
else
return PTR_ERR(sub);
}
cs35l41->dsp.system_name = sub;
dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name);
return 0;
}
int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg)
{
u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
int irq_pol = 0;
int ret;
if (hw_cfg) {
cs35l41->hw_cfg = *hw_cfg;
} else {
ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg);
if (ret != 0)
return ret;
}
for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
cs35l41->supplies[i].supply = cs35l41_supplies[i];
ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
cs35l41->supplies);
if (ret != 0) {
dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
if (ret != 0) {
dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret);
return ret;
}
/* returning NULL can be an option if in stereo mode */
cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(cs35l41->reset_gpio)) {
ret = PTR_ERR(cs35l41->reset_gpio);
cs35l41->reset_gpio = NULL;
if (ret == -EBUSY) {
dev_info(cs35l41->dev,
"Reset line busy, assuming shared reset\n");
} else {
dev_err(cs35l41->dev,
"Failed to get reset GPIO: %d\n", ret);
goto err;
}
}
if (cs35l41->reset_gpio) {
/* satisfy minimum reset pulse width spec */
usleep_range(2000, 2100);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
}
usleep_range(2000, 2100);
ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4,
int_status, int_status & CS35L41_OTP_BOOT_DONE,
1000, 100000);
if (ret) {
dev_err(cs35l41->dev,
"Failed waiting for OTP_BOOT_DONE: %d\n", ret);
goto err;
}
regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
if (int_status & CS35L41_OTP_BOOT_ERR) {
dev_err(cs35l41->dev, "OTP Boot error\n");
ret = -EINVAL;
goto err;
}
ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id);
if (ret < 0) {
dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret);
goto err;
}
ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid);
if (ret < 0) {
dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret);
goto err;
}
mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
/* CS35L41 will have even MTLREVID
* CS35L41R will have odd MTLREVID
*/
chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
if (regid != chipid_match) {
dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
regid, chipid_match);
ret = -ENODEV;
goto err;
}
cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
if (ret)
goto err;
ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
if (ret < 0) {
dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret);
goto err;
}
cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg);
/* Set interrupt masks for critical errors */
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
CS35L41_INT1_MASK_DEFAULT);
if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
0 << CS35L41_INT3_PLL_LOCK_SHIFT);
ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
IRQF_ONESHOT | IRQF_SHARED | irq_pol,
"cs35l41", cs35l41);
if (ret != 0) {
dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
goto err;
}
ret = cs35l41_set_pdata(cs35l41);
if (ret < 0) {
dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret);
goto err;
}
ret = cs35l41_acpi_get_name(cs35l41);
if (ret < 0)
goto err;
ret = cs35l41_dsp_init(cs35l41);
if (ret < 0)
goto err;
init_completion(&cs35l41->pll_lock);
pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
pm_runtime_use_autosuspend(cs35l41->dev);
pm_runtime_mark_last_busy(cs35l41->dev);
pm_runtime_set_active(cs35l41->dev);
pm_runtime_get_noresume(cs35l41->dev);
pm_runtime_enable(cs35l41->dev);
ret = devm_snd_soc_register_component(cs35l41->dev,
&soc_component_dev_cs35l41,
cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
if (ret < 0) {
dev_err(cs35l41->dev, "Register codec failed: %d\n", ret);
goto err_pm;
}
pm_runtime_put_autosuspend(cs35l41->dev);
dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
regid, reg_revid);
return 0;
err_pm:
pm_runtime_disable(cs35l41->dev);
pm_runtime_put_noidle(cs35l41->dev);
wm_adsp2_remove(&cs35l41->dsp);
err:
cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
return ret;
}
EXPORT_SYMBOL_GPL(cs35l41_probe);
void cs35l41_remove(struct cs35l41_private *cs35l41)
{
pm_runtime_get_sync(cs35l41->dev);
pm_runtime_disable(cs35l41->dev);
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1 << CS35L41_INT3_PLL_LOCK_SHIFT);
kfree(cs35l41->dsp.system_name);
wm_adsp2_remove(&cs35l41->dsp);
cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
pm_runtime_put_noidle(cs35l41->dev);
regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
}
EXPORT_SYMBOL_GPL(cs35l41_remove);
static int __maybe_unused cs35l41_runtime_suspend(struct device *dev)
{
struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
dev_dbg(cs35l41->dev, "Runtime suspend\n");
if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
return 0;
cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type);
regcache_cache_only(cs35l41->regmap, true);
regcache_mark_dirty(cs35l41->regmap);
return 0;
}
static int __maybe_unused cs35l41_runtime_resume(struct device *dev)
{
struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
int ret;
dev_dbg(cs35l41->dev, "Runtime resume\n");
if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
return 0;
regcache_cache_only(cs35l41->regmap, false);
ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
if (ret)
return ret;
/* Test key needs to be unlocked to allow the OTP settings to re-apply */
cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
ret = regcache_sync(cs35l41->regmap);
cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
if (ret) {
dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
return ret;
}
cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
return 0;
}
static int __maybe_unused cs35l41_sys_suspend(struct device *dev)
{
struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n");
disable_irq(cs35l41->irq);
return 0;
}
static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev)
{
struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n");
enable_irq(cs35l41->irq);
return 0;
}
static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev)
{
struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n");
disable_irq(cs35l41->irq);
return 0;
}
static int __maybe_unused cs35l41_sys_resume(struct device *dev)
{
struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n");
enable_irq(cs35l41->irq);
return 0;
}
const struct dev_pm_ops cs35l41_pm_ops = {
SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq)
};
EXPORT_SYMBOL_GPL(cs35l41_pm_ops);
MODULE_DESCRIPTION("ASoC CS35L41 driver");
MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/cs35l41.c |
// SPDX-License-Identifier: GPL-2.0-only
// cs4234.c -- ALSA SoC CS4234 driver
//
// Copyright (C) 2020 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
//
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/jiffies.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/workqueue.h>
#include "cs4234.h"
struct cs4234 {
struct device *dev;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
struct regulator_bulk_data core_supplies[2];
int num_core_supplies;
struct completion vq_ramp_complete;
struct delayed_work vq_ramp_delay;
struct clk *mclk;
unsigned long mclk_rate;
unsigned long lrclk_rate;
unsigned int format;
struct snd_ratnum rate_dividers[2];
struct snd_pcm_hw_constraint_ratnums rate_constraint;
};
/* -89.92dB to +6.02dB with step of 0.38dB */
static const DECLARE_TLV_DB_SCALE(dac_tlv, -8992, 38, 0);
static const char * const cs4234_dac14_delay_text[] = {
"0us", "100us", "150us", "200us", "225us", "250us", "275us", "300us",
"325us", "350us", "375us", "400us", "425us", "450us", "475us", "500us",
};
static SOC_ENUM_SINGLE_DECL(cs4234_dac14_group_delay, CS4234_TPS_CTRL,
CS4234_GRP_DELAY_SHIFT, cs4234_dac14_delay_text);
static const char * const cs4234_noise_gate_text[] = {
"72dB", "78dB", "84dB", "90dB", "96dB", "102dB", "138dB", "Disabled",
};
static SOC_ENUM_SINGLE_DECL(cs4234_ll_noise_gate, CS4234_LOW_LAT_CTRL1,
CS4234_LL_NG_SHIFT, cs4234_noise_gate_text);
static SOC_ENUM_SINGLE_DECL(cs4234_dac14_noise_gate, CS4234_DAC_CTRL1,
CS4234_DAC14_NG_SHIFT, cs4234_noise_gate_text);
static SOC_ENUM_SINGLE_DECL(cs4234_dac5_noise_gate, CS4234_DAC_CTRL2,
CS4234_DAC5_NG_SHIFT, cs4234_noise_gate_text);
static const char * const cs4234_dac5_config_fltr_sel_text[] = {
"Interpolation Filter", "Sample and Hold"
};
static SOC_ENUM_SINGLE_DECL(cs4234_dac5_config_fltr_sel, CS4234_DAC_CTRL1,
CS4234_DAC5_CFG_FLTR_SHIFT,
cs4234_dac5_config_fltr_sel_text);
static const char * const cs4234_mute_delay_text[] = {
"1x", "4x", "16x", "64x",
};
static SOC_ENUM_SINGLE_DECL(cs4234_mute_delay, CS4234_VOLUME_MODE,
CS4234_MUTE_DELAY_SHIFT, cs4234_mute_delay_text);
static const char * const cs4234_minmax_delay_text[] = {
"1x", "2x", "4x", "8x", "16x", "32x", "64x", "128x",
};
static SOC_ENUM_SINGLE_DECL(cs4234_min_delay, CS4234_VOLUME_MODE,
CS4234_MIN_DELAY_SHIFT, cs4234_minmax_delay_text);
static SOC_ENUM_SINGLE_DECL(cs4234_max_delay, CS4234_VOLUME_MODE,
CS4234_MAX_DELAY_SHIFT, cs4234_minmax_delay_text);
static int cs4234_dac14_grp_delay_put(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_value *uctrl)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kctrl);
struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
unsigned int val = 0;
int ret = 0;
snd_soc_dapm_mutex_lock(dapm);
regmap_read(cs4234->regmap, CS4234_ADC_CTRL2, &val);
if ((val & 0x0F) != 0x0F) { // are all the ADCs powerdown
ret = -EBUSY;
dev_err(component->dev, "Can't change group delay while ADC are ON\n");
goto exit;
}
regmap_read(cs4234->regmap, CS4234_DAC_CTRL4, &val);
if ((val & 0x1F) != 0x1F) { // are all the DACs powerdown
ret = -EBUSY;
dev_err(component->dev, "Can't change group delay while DAC are ON\n");
goto exit;
}
ret = snd_soc_put_enum_double(kctrl, uctrl);
exit:
snd_soc_dapm_mutex_unlock(dapm);
return ret;
}
static void cs4234_vq_ramp_done(struct work_struct *work)
{
struct delayed_work *dw = to_delayed_work(work);
struct cs4234 *cs4234 = container_of(dw, struct cs4234, vq_ramp_delay);
complete_all(&cs4234->vq_ramp_complete);
}
static int cs4234_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
switch (snd_soc_component_get_bias_level(component)) {
case SND_SOC_BIAS_STANDBY:
wait_for_completion(&cs4234->vq_ramp_complete);
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget cs4234_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("SDRX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDRX2", NULL, 1, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDRX3", NULL, 2, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDRX4", NULL, 3, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SDRX5", NULL, 4, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC1", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC1_SHIFT, 1),
SND_SOC_DAPM_DAC("DAC2", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC2_SHIFT, 1),
SND_SOC_DAPM_DAC("DAC3", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC3_SHIFT, 1),
SND_SOC_DAPM_DAC("DAC4", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC4_SHIFT, 1),
SND_SOC_DAPM_DAC("DAC5", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC5_SHIFT, 1),
SND_SOC_DAPM_OUTPUT("AOUT1"),
SND_SOC_DAPM_OUTPUT("AOUT2"),
SND_SOC_DAPM_OUTPUT("AOUT3"),
SND_SOC_DAPM_OUTPUT("AOUT4"),
SND_SOC_DAPM_OUTPUT("AOUT5"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN4"),
SND_SOC_DAPM_ADC("ADC1", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC1_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC2", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC2_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC3", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC3_SHIFT, 1),
SND_SOC_DAPM_ADC("ADC4", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC4_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT("SDTX1", NULL, 0, SND_SOC_NOPM, 0, 1),
SND_SOC_DAPM_AIF_OUT("SDTX2", NULL, 1, SND_SOC_NOPM, 0, 1),
SND_SOC_DAPM_AIF_OUT("SDTX3", NULL, 2, SND_SOC_NOPM, 0, 1),
SND_SOC_DAPM_AIF_OUT("SDTX4", NULL, 3, SND_SOC_NOPM, 0, 1),
};
static const struct snd_soc_dapm_route cs4234_dapm_routes[] = {
/* Playback */
{ "AOUT1", NULL, "DAC1" },
{ "AOUT2", NULL, "DAC2" },
{ "AOUT3", NULL, "DAC3" },
{ "AOUT4", NULL, "DAC4" },
{ "AOUT5", NULL, "DAC5" },
{ "DAC1", NULL, "SDRX1" },
{ "DAC2", NULL, "SDRX2" },
{ "DAC3", NULL, "SDRX3" },
{ "DAC4", NULL, "SDRX4" },
{ "DAC5", NULL, "SDRX5" },
{ "SDRX1", NULL, "Playback" },
{ "SDRX2", NULL, "Playback" },
{ "SDRX3", NULL, "Playback" },
{ "SDRX4", NULL, "Playback" },
{ "SDRX5", NULL, "Playback" },
/* Capture */
{ "ADC1", NULL, "AIN1" },
{ "ADC2", NULL, "AIN2" },
{ "ADC3", NULL, "AIN3" },
{ "ADC4", NULL, "AIN4" },
{ "SDTX1", NULL, "ADC1" },
{ "SDTX2", NULL, "ADC2" },
{ "SDTX3", NULL, "ADC3" },
{ "SDTX4", NULL, "ADC4" },
{ "Capture", NULL, "SDTX1" },
{ "Capture", NULL, "SDTX2" },
{ "Capture", NULL, "SDTX3" },
{ "Capture", NULL, "SDTX4" },
};
static const struct snd_kcontrol_new cs4234_snd_controls[] = {
SOC_SINGLE_TLV("Master Volume", CS4234_MASTER_VOL, 0, 0xff, 1, dac_tlv),
SOC_SINGLE_TLV("DAC1 Volume", CS4234_DAC1_VOL, 0, 0xff, 1, dac_tlv),
SOC_SINGLE_TLV("DAC2 Volume", CS4234_DAC2_VOL, 0, 0xff, 1, dac_tlv),
SOC_SINGLE_TLV("DAC3 Volume", CS4234_DAC3_VOL, 0, 0xff, 1, dac_tlv),
SOC_SINGLE_TLV("DAC4 Volume", CS4234_DAC4_VOL, 0, 0xff, 1, dac_tlv),
SOC_SINGLE_TLV("DAC5 Volume", CS4234_DAC5_VOL, 0, 0xff, 1, dac_tlv),
SOC_SINGLE("DAC5 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC5_ATT_SHIFT, 1, 1),
SOC_SINGLE("DAC1-4 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC14_ATT_SHIFT, 1, 1),
SOC_SINGLE("ADC HPF Switch", CS4234_ADC_CTRL1, CS4234_ENA_HPF_SHIFT, 1, 0),
SOC_ENUM_EXT("DAC1-4 Group Delay", cs4234_dac14_group_delay,
snd_soc_get_enum_double, cs4234_dac14_grp_delay_put),
SOC_SINGLE("ADC1 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC1_SHIFT, 1, 0),
SOC_SINGLE("ADC2 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC2_SHIFT, 1, 0),
SOC_SINGLE("ADC3 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC3_SHIFT, 1, 0),
SOC_SINGLE("ADC4 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC4_SHIFT, 1, 0),
SOC_SINGLE("DAC1 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC1_SHIFT, 1, 0),
SOC_SINGLE("DAC2 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC2_SHIFT, 1, 0),
SOC_SINGLE("DAC3 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC3_SHIFT, 1, 0),
SOC_SINGLE("DAC4 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC4_SHIFT, 1, 0),
SOC_SINGLE("DAC5 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC5_SHIFT, 1, 0),
SOC_SINGLE("ADC1 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC1_SHIFT, 1, 1),
SOC_SINGLE("ADC2 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC2_SHIFT, 1, 1),
SOC_SINGLE("ADC3 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC3_SHIFT, 1, 1),
SOC_SINGLE("ADC4 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC4_SHIFT, 1, 1),
SOC_SINGLE("DAC1 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC1_SHIFT, 1, 1),
SOC_SINGLE("DAC2 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC2_SHIFT, 1, 1),
SOC_SINGLE("DAC3 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC3_SHIFT, 1, 1),
SOC_SINGLE("DAC4 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC4_SHIFT, 1, 1),
SOC_SINGLE("DAC5 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC5_SHIFT, 1, 1),
SOC_SINGLE("Low-latency Switch", CS4234_DAC_CTRL3, CS4234_MUTE_LL_SHIFT, 1, 1),
SOC_SINGLE("DAC1 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
CS4234_INV_LL1_SHIFT, 1, 0),
SOC_SINGLE("DAC2 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
CS4234_INV_LL2_SHIFT, 1, 0),
SOC_SINGLE("DAC3 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
CS4234_INV_LL3_SHIFT, 1, 0),
SOC_SINGLE("DAC4 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1,
CS4234_INV_LL4_SHIFT, 1, 0),
SOC_ENUM("Low-latency Noise Gate", cs4234_ll_noise_gate),
SOC_ENUM("DAC1-4 Noise Gate", cs4234_dac14_noise_gate),
SOC_ENUM("DAC5 Noise Gate", cs4234_dac5_noise_gate),
SOC_SINGLE("DAC1-4 De-emphasis Switch", CS4234_DAC_CTRL1,
CS4234_DAC14_DE_SHIFT, 1, 0),
SOC_SINGLE("DAC5 De-emphasis Switch", CS4234_DAC_CTRL1,
CS4234_DAC5_DE_SHIFT, 1, 0),
SOC_SINGLE("DAC5 Master Controlled Switch", CS4234_DAC_CTRL1,
CS4234_DAC5_MVC_SHIFT, 1, 0),
SOC_ENUM("DAC5 Filter", cs4234_dac5_config_fltr_sel),
SOC_ENUM("Mute Delay", cs4234_mute_delay),
SOC_ENUM("Ramp Minimum Delay", cs4234_min_delay),
SOC_ENUM("Ramp Maximum Delay", cs4234_max_delay),
};
static int cs4234_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
unsigned int sp_ctrl = 0;
cs4234->format = format & SND_SOC_DAIFMT_FORMAT_MASK;
switch (cs4234->format) {
case SND_SOC_DAIFMT_LEFT_J:
sp_ctrl |= CS4234_LEFT_J << CS4234_SP_FORMAT_SHIFT;
break;
case SND_SOC_DAIFMT_I2S:
sp_ctrl |= CS4234_I2S << CS4234_SP_FORMAT_SHIFT;
break;
case SND_SOC_DAIFMT_DSP_A: /* TDM mode in datasheet */
sp_ctrl |= CS4234_TDM << CS4234_SP_FORMAT_SHIFT;
break;
default:
dev_err(component->dev, "Unsupported dai format\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
if (cs4234->format == SND_SOC_DAIFMT_DSP_A) {
dev_err(component->dev, "Unsupported DSP A format in master mode\n");
return -EINVAL;
}
sp_ctrl |= CS4234_MST_SLV_MASK;
break;
default:
dev_err(component->dev, "Unsupported master/slave mode\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
sp_ctrl |= CS4234_INVT_SCLK_MASK;
break;
default:
dev_err(component->dev, "Unsupported inverted clock setting\n");
return -EINVAL;
}
regmap_update_bits(cs4234->regmap, CS4234_SP_CTRL,
CS4234_SP_FORMAT_MASK | CS4234_MST_SLV_MASK | CS4234_INVT_SCLK_MASK,
sp_ctrl);
return 0;
}
static int cs4234_dai_hw_params(struct snd_pcm_substream *sub,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
unsigned int mclk_mult, double_speed = 0;
int ret = 0, rate_ad, sample_width;
cs4234->lrclk_rate = params_rate(params);
mclk_mult = cs4234->mclk_rate / cs4234->lrclk_rate;
if (cs4234->lrclk_rate > 48000) {
double_speed = 1;
mclk_mult *= 2;
}
switch (mclk_mult) {
case 256:
case 384:
case 512:
regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP,
CS4234_SPEED_MODE_MASK,
double_speed << CS4234_SPEED_MODE_SHIFT);
regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP,
CS4234_MCLK_RATE_MASK,
((mclk_mult / 128) - 2) << CS4234_MCLK_RATE_SHIFT);
break;
default:
dev_err(component->dev, "Unsupported mclk/lrclk rate\n");
return -EINVAL;
}
switch (cs4234->lrclk_rate) {
case 48000:
case 96000:
rate_ad = CS4234_48K;
break;
case 44100:
case 88200:
rate_ad = CS4234_44K1;
break;
case 32000:
case 64000:
rate_ad = CS4234_32K;
break;
default:
dev_err(component->dev, "Unsupported LR clock\n");
return -EINVAL;
}
regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP, CS4234_BASE_RATE_MASK,
rate_ad << CS4234_BASE_RATE_SHIFT);
sample_width = params_width(params);
switch (sample_width) {
case 16:
sample_width = 0;
break;
case 18:
sample_width = 1;
break;
case 20:
sample_width = 2;
break;
case 24:
sample_width = 3;
break;
default:
dev_err(component->dev, "Unsupported sample width\n");
return -EINVAL;
}
if (sub->stream == SNDRV_PCM_STREAM_CAPTURE)
regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH,
CS4234_SDOUTX_SW_MASK,
sample_width << CS4234_SDOUTX_SW_SHIFT);
else
regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH,
CS4234_INPUT_SW_MASK | CS4234_LOW_LAT_SW_MASK | CS4234_DAC5_SW_MASK,
sample_width << CS4234_INPUT_SW_SHIFT |
sample_width << CS4234_LOW_LAT_SW_SHIFT |
sample_width << CS4234_DAC5_SW_SHIFT);
return ret;
}
/* Scale MCLK rate by 64 to avoid overflow in the ratnum calculation */
#define CS4234_MCLK_SCALE 64
static const struct snd_ratnum cs4234_dividers[] = {
{
.num = 0,
.den_min = 256 / CS4234_MCLK_SCALE,
.den_max = 512 / CS4234_MCLK_SCALE,
.den_step = 128 / CS4234_MCLK_SCALE,
},
{
.num = 0,
.den_min = 128 / CS4234_MCLK_SCALE,
.den_max = 192 / CS4234_MCLK_SCALE,
.den_step = 64 / CS4234_MCLK_SCALE,
},
};
static int cs4234_dai_rule_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
{
struct cs4234 *cs4234 = rule->private;
int mclk = cs4234->mclk_rate;
struct snd_interval ranges[] = {
{ /* Single Speed Mode */
.min = mclk / clamp(mclk / 30000, 256, 512),
.max = mclk / clamp(mclk / 50000, 256, 512),
},
{ /* Double Speed Mode */
.min = mclk / clamp(mclk / 60000, 128, 256),
.max = mclk / clamp(mclk / 100000, 128, 256),
},
};
return snd_interval_ranges(hw_param_interval(params, rule->var),
ARRAY_SIZE(ranges), ranges, 0);
}
static int cs4234_dai_startup(struct snd_pcm_substream *sub, struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
struct cs4234 *cs4234 = snd_soc_component_get_drvdata(comp);
int i, ret;
switch (cs4234->format) {
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_I2S:
cs4234->rate_constraint.nrats = 2;
/*
* Playback only supports 24-bit samples in these modes.
* Note: SNDRV_PCM_HW_PARAM_SAMPLE_BITS constrains the physical
* width, which we don't care about, so constrain the format.
*/
if (sub->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_pcm_hw_constraint_mask64(
sub->runtime,
SNDRV_PCM_HW_PARAM_FORMAT,
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S24_3LE);
if (ret < 0)
return ret;
ret = snd_pcm_hw_constraint_minmax(sub->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS,
1, 4);
if (ret < 0)
return ret;
}
break;
case SND_SOC_DAIFMT_DSP_A:
cs4234->rate_constraint.nrats = 1;
break;
default:
dev_err(comp->dev, "Startup unsupported DAI format\n");
return -EINVAL;
}
for (i = 0; i < cs4234->rate_constraint.nrats; i++)
cs4234->rate_dividers[i].num = cs4234->mclk_rate / CS4234_MCLK_SCALE;
ret = snd_pcm_hw_constraint_ratnums(sub->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&cs4234->rate_constraint);
if (ret < 0)
return ret;
/*
* MCLK/rate may be a valid ratio but out-of-spec (e.g. 24576000/64000)
* so this rule limits the range of sample rate for given MCLK.
*/
return snd_pcm_hw_rule_add(sub->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
cs4234_dai_rule_rate, cs4234, -1);
}
static int cs4234_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_component *component = dai->component;
struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component);
unsigned int slot_offset, dac5_slot, dac5_mask_group;
uint8_t dac5_masks[4];
if (slot_width != 32) {
dev_err(component->dev, "Unsupported slot width\n");
return -EINVAL;
}
/* Either 4 or 5 consecutive bits, DAC5 is optional */
slot_offset = ffs(tx_mask) - 1;
tx_mask >>= slot_offset;
if ((slot_offset % 4) || ((tx_mask != 0x0F) && (tx_mask != 0x1F))) {
dev_err(component->dev, "Unsupported tx slots allocation\n");
return -EINVAL;
}
regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_DAC14_SRC_MASK,
(slot_offset / 4) << CS4234_DAC14_SRC_SHIFT);
regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_LL_SRC_MASK,
(slot_offset / 4) << CS4234_LL_SRC_SHIFT);
if (tx_mask == 0x1F) {
dac5_slot = slot_offset + 4;
memset(dac5_masks, 0xFF, sizeof(dac5_masks));
dac5_mask_group = dac5_slot / 8;
dac5_slot %= 8;
dac5_masks[dac5_mask_group] ^= BIT(7 - dac5_slot);
regmap_bulk_write(cs4234->regmap,
CS4234_SDIN1_MASK1,
dac5_masks,
ARRAY_SIZE(dac5_masks));
}
return 0;
}
static const struct snd_soc_dai_ops cs4234_dai_ops = {
.set_fmt = cs4234_dai_set_fmt,
.hw_params = cs4234_dai_hw_params,
.startup = cs4234_dai_startup,
.set_tdm_slot = cs4234_dai_set_tdm_slot,
};
static struct snd_soc_dai_driver cs4234_dai[] = {
{
.name = "cs4234-dai",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 5,
.rates = CS4234_PCM_RATES,
.formats = CS4234_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 4,
.rates = CS4234_PCM_RATES,
.formats = CS4234_FORMATS,
},
.ops = &cs4234_dai_ops,
.symmetric_rate = 1,
},
};
static const struct reg_default cs4234_default_reg[] = {
{ CS4234_CLOCK_SP, 0x04},
{ CS4234_SAMPLE_WIDTH, 0xFF},
{ CS4234_SP_CTRL, 0x48},
{ CS4234_SP_DATA_SEL, 0x01},
{ CS4234_SDIN1_MASK1, 0xFF},
{ CS4234_SDIN1_MASK2, 0xFF},
{ CS4234_SDIN2_MASK1, 0xFF},
{ CS4234_SDIN2_MASK2, 0xFF},
{ CS4234_TPS_CTRL, 0x00},
{ CS4234_ADC_CTRL1, 0xC0},
{ CS4234_ADC_CTRL2, 0xFF},
{ CS4234_LOW_LAT_CTRL1, 0xE0},
{ CS4234_DAC_CTRL1, 0xE0},
{ CS4234_DAC_CTRL2, 0xE0},
{ CS4234_DAC_CTRL3, 0xBF},
{ CS4234_DAC_CTRL4, 0x1F},
{ CS4234_VOLUME_MODE, 0x87},
{ CS4234_MASTER_VOL, 0x10},
{ CS4234_DAC1_VOL, 0x10},
{ CS4234_DAC2_VOL, 0x10},
{ CS4234_DAC3_VOL, 0x10},
{ CS4234_DAC4_VOL, 0x10},
{ CS4234_DAC5_VOL, 0x10},
{ CS4234_INT_CTRL, 0x40},
{ CS4234_INT_MASK1, 0x10},
{ CS4234_INT_MASK2, 0x20},
};
static bool cs4234_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4234_DEVID_AB ... CS4234_DEVID_EF:
case CS4234_REVID ... CS4234_DAC5_VOL:
case CS4234_INT_CTRL ... CS4234_MAX_REGISTER:
return true;
default:
return false;
}
}
static bool cs4234_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4234_INT_NOTIFY1:
case CS4234_INT_NOTIFY2:
return true;
default:
return false;
}
}
static bool cs4234_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS4234_DEVID_AB ... CS4234_REVID:
case CS4234_INT_NOTIFY1 ... CS4234_INT_NOTIFY2:
return false;
default:
return true;
}
}
static const struct snd_soc_component_driver soc_component_cs4234 = {
.dapm_widgets = cs4234_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs4234_dapm_widgets),
.dapm_routes = cs4234_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(cs4234_dapm_routes),
.controls = cs4234_snd_controls,
.num_controls = ARRAY_SIZE(cs4234_snd_controls),
.set_bias_level = cs4234_set_bias_level,
.idle_bias_on = 1,
.suspend_bias_off = 1,
.endianness = 1,
};
static const struct regmap_config cs4234_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CS4234_MAX_REGISTER,
.readable_reg = cs4234_readable_register,
.volatile_reg = cs4234_volatile_reg,
.writeable_reg = cs4234_writeable_register,
.reg_defaults = cs4234_default_reg,
.num_reg_defaults = ARRAY_SIZE(cs4234_default_reg),
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const char * const cs4234_core_supplies[] = {
"VA",
"VL",
};
static void cs4234_shutdown(struct cs4234 *cs4234)
{
cancel_delayed_work_sync(&cs4234->vq_ramp_delay);
reinit_completion(&cs4234->vq_ramp_complete);
regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK,
CS4234_VQ_RAMP_MASK);
msleep(50);
regcache_cache_only(cs4234->regmap, true);
/* Clear VQ Ramp Bit in cache for the next PowerUp */
regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK, 0);
gpiod_set_value_cansleep(cs4234->reset_gpio, 0);
regulator_bulk_disable(cs4234->num_core_supplies, cs4234->core_supplies);
clk_disable_unprepare(cs4234->mclk);
}
static int cs4234_powerup(struct cs4234 *cs4234)
{
int ret;
ret = clk_prepare_enable(cs4234->mclk);
if (ret) {
dev_err(cs4234->dev, "Failed to enable mclk: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(cs4234->num_core_supplies, cs4234->core_supplies);
if (ret) {
dev_err(cs4234->dev, "Failed to enable core supplies: %d\n", ret);
clk_disable_unprepare(cs4234->mclk);
return ret;
}
usleep_range(CS4234_HOLD_RESET_TIME_US, 2 * CS4234_HOLD_RESET_TIME_US);
gpiod_set_value_cansleep(cs4234->reset_gpio, 1);
/* Make sure hardware reset done 2 ms + (3000/MCLK) */
usleep_range(CS4234_BOOT_TIME_US, CS4234_BOOT_TIME_US * 2);
queue_delayed_work(system_power_efficient_wq,
&cs4234->vq_ramp_delay,
msecs_to_jiffies(CS4234_VQ_CHARGE_MS));
return 0;
}
static int cs4234_i2c_probe(struct i2c_client *i2c_client)
{
struct cs4234 *cs4234;
struct device *dev = &i2c_client->dev;
unsigned int revid;
uint32_t devid;
uint8_t ids[3];
int ret = 0, i;
cs4234 = devm_kzalloc(dev, sizeof(*cs4234), GFP_KERNEL);
if (!cs4234)
return -ENOMEM;
i2c_set_clientdata(i2c_client, cs4234);
cs4234->dev = dev;
init_completion(&cs4234->vq_ramp_complete);
INIT_DELAYED_WORK(&cs4234->vq_ramp_delay, cs4234_vq_ramp_done);
cs4234->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(cs4234->reset_gpio))
return PTR_ERR(cs4234->reset_gpio);
BUILD_BUG_ON(ARRAY_SIZE(cs4234->core_supplies) < ARRAY_SIZE(cs4234_core_supplies));
cs4234->num_core_supplies = ARRAY_SIZE(cs4234_core_supplies);
for (i = 0; i < ARRAY_SIZE(cs4234_core_supplies); i++)
cs4234->core_supplies[i].supply = cs4234_core_supplies[i];
ret = devm_regulator_bulk_get(dev, cs4234->num_core_supplies, cs4234->core_supplies);
if (ret) {
dev_err(dev, "Failed to request core supplies %d\n", ret);
return ret;
}
cs4234->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(cs4234->mclk)) {
ret = PTR_ERR(cs4234->mclk);
dev_err(dev, "Failed to get the mclk: %d\n", ret);
return ret;
}
cs4234->mclk_rate = clk_get_rate(cs4234->mclk);
if (cs4234->mclk_rate < 7680000 || cs4234->mclk_rate > 25600000) {
dev_err(dev, "Invalid Master Clock rate\n");
return -EINVAL;
}
cs4234->regmap = devm_regmap_init_i2c(i2c_client, &cs4234_regmap);
if (IS_ERR(cs4234->regmap)) {
ret = PTR_ERR(cs4234->regmap);
dev_err(dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret = cs4234_powerup(cs4234);
if (ret)
return ret;
ret = regmap_bulk_read(cs4234->regmap, CS4234_DEVID_AB, ids, ARRAY_SIZE(ids));
if (ret < 0) {
dev_err(dev, "Failed to read DEVID: %d\n", ret);
goto fail_shutdown;
}
devid = (ids[0] << 16) | (ids[1] << 8) | ids[2];
if (devid != CS4234_SUPPORTED_ID) {
dev_err(dev, "Unknown device ID: %x\n", devid);
ret = -EINVAL;
goto fail_shutdown;
}
ret = regmap_read(cs4234->regmap, CS4234_REVID, &revid);
if (ret < 0) {
dev_err(dev, "Failed to read CS4234_REVID: %d\n", ret);
goto fail_shutdown;
}
dev_info(dev, "Cirrus Logic CS4234, Alpha Rev: %02X, Numeric Rev: %02X\n",
(revid & 0xF0) >> 4, revid & 0x0F);
ret = regulator_get_voltage(cs4234->core_supplies[CS4234_SUPPLY_VA].consumer);
switch (ret) {
case 3135000 ... 3650000:
regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1,
CS4234_VA_SEL_MASK,
CS4234_3V3 << CS4234_VA_SEL_SHIFT);
break;
case 4750000 ... 5250000:
regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1,
CS4234_VA_SEL_MASK,
CS4234_5V << CS4234_VA_SEL_SHIFT);
break;
default:
dev_err(dev, "Invalid VA voltage\n");
ret = -EINVAL;
goto fail_shutdown;
}
pm_runtime_set_active(&i2c_client->dev);
pm_runtime_enable(&i2c_client->dev);
memcpy(&cs4234->rate_dividers, &cs4234_dividers, sizeof(cs4234_dividers));
cs4234->rate_constraint.rats = cs4234->rate_dividers;
ret = snd_soc_register_component(dev, &soc_component_cs4234, cs4234_dai,
ARRAY_SIZE(cs4234_dai));
if (ret < 0) {
dev_err(dev, "Failed to register component:%d\n", ret);
pm_runtime_disable(&i2c_client->dev);
goto fail_shutdown;
}
return ret;
fail_shutdown:
cs4234_shutdown(cs4234);
return ret;
}
static void cs4234_i2c_remove(struct i2c_client *i2c_client)
{
struct cs4234 *cs4234 = i2c_get_clientdata(i2c_client);
struct device *dev = &i2c_client->dev;
snd_soc_unregister_component(dev);
pm_runtime_disable(dev);
cs4234_shutdown(cs4234);
}
static int __maybe_unused cs4234_runtime_resume(struct device *dev)
{
struct cs4234 *cs4234 = dev_get_drvdata(dev);
int ret;
ret = cs4234_powerup(cs4234);
if (ret)
return ret;
regcache_mark_dirty(cs4234->regmap);
regcache_cache_only(cs4234->regmap, false);
ret = regcache_sync(cs4234->regmap);
if (ret) {
dev_err(dev, "Failed to sync regmap: %d\n", ret);
cs4234_shutdown(cs4234);
return ret;
}
return 0;
}
static int __maybe_unused cs4234_runtime_suspend(struct device *dev)
{
struct cs4234 *cs4234 = dev_get_drvdata(dev);
cs4234_shutdown(cs4234);
return 0;
}
static const struct dev_pm_ops cs4234_pm = {
SET_RUNTIME_PM_OPS(cs4234_runtime_suspend, cs4234_runtime_resume, NULL)
};
static const struct of_device_id cs4234_of_match[] = {
{ .compatible = "cirrus,cs4234", },
{ }
};
MODULE_DEVICE_TABLE(of, cs4234_of_match);
static struct i2c_driver cs4234_i2c_driver = {
.driver = {
.name = "cs4234",
.pm = &cs4234_pm,
.of_match_table = cs4234_of_match,
},
.probe = cs4234_i2c_probe,
.remove = cs4234_i2c_remove,
};
module_i2c_driver(cs4234_i2c_driver);
MODULE_DESCRIPTION("ASoC Cirrus Logic CS4234 driver");
MODULE_AUTHOR("Lucas Tanure <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/cs4234.c |
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