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// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI Hostless Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include "mt8183-afe-common.h"
/* dai component */
static const struct snd_soc_dapm_route mtk_dai_hostless_routes[] = {
/* Hostless ADDA Loopback */
{"ADDA_DL_CH1", "ADDA_UL_CH1", "Hostless LPBK DL"},
{"ADDA_DL_CH1", "ADDA_UL_CH2", "Hostless LPBK DL"},
{"ADDA_DL_CH2", "ADDA_UL_CH1", "Hostless LPBK DL"},
{"ADDA_DL_CH2", "ADDA_UL_CH2", "Hostless LPBK DL"},
{"Hostless LPBK UL", NULL, "ADDA Capture"},
/* Hostless Speech */
{"ADDA_DL_CH1", "PCM_1_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_1_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_1_CAP_CH2", "Hostless Speech DL"},
{"ADDA_DL_CH1", "PCM_2_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_2_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_2_CAP_CH2", "Hostless Speech DL"},
{"PCM_1_PB_CH1", "ADDA_UL_CH1", "Hostless Speech DL"},
{"PCM_1_PB_CH2", "ADDA_UL_CH2", "Hostless Speech DL"},
{"PCM_2_PB_CH1", "ADDA_UL_CH1", "Hostless Speech DL"},
{"PCM_2_PB_CH2", "ADDA_UL_CH2", "Hostless Speech DL"},
{"Hostless Speech UL", NULL, "PCM 1 Capture"},
{"Hostless Speech UL", NULL, "PCM 2 Capture"},
{"Hostless Speech UL", NULL, "ADDA Capture"},
};
/* dai ops */
static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
return snd_soc_set_runtime_hwparams(substream, afe->mtk_afe_hardware);
}
static const struct snd_soc_dai_ops mtk_dai_hostless_ops = {
.startup = mtk_dai_hostless_startup,
};
/* dai driver */
#define MTK_HOSTLESS_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_HOSTLESS_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_hostless_driver[] = {
{
.name = "Hostless LPBK DAI",
.id = MT8183_DAI_HOSTLESS_LPBK,
.playback = {
.stream_name = "Hostless LPBK DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless LPBK UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless Speech DAI",
.id = MT8183_DAI_HOSTLESS_SPEECH,
.playback = {
.stream_name = "Hostless Speech DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless Speech UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
};
int mt8183_dai_hostless_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_hostless_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_hostless_driver);
dai->dapm_routes = mtk_dai_hostless_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_hostless_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt8183/mt8183-dai-hostless.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI TDM Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8183-afe-clk.h"
#include "mt8183-afe-common.h"
#include "mt8183-interconnection.h"
#include "mt8183-reg.h"
struct mtk_afe_tdm_priv {
int bck_id;
int bck_rate;
int tdm_out_mode;
int bck_invert;
int lck_invert;
int mclk_id;
int mclk_multiple; /* according to sample rate */
int mclk_rate;
int mclk_apll;
};
enum {
TDM_OUT_I2S = 0,
TDM_OUT_TDM = 1,
};
enum {
TDM_BCK_NON_INV = 0,
TDM_BCK_INV = 1,
};
enum {
TDM_LCK_NON_INV = 0,
TDM_LCK_INV = 1,
};
enum {
TDM_WLEN_16_BIT = 1,
TDM_WLEN_32_BIT = 2,
};
enum {
TDM_CHANNEL_BCK_16 = 0,
TDM_CHANNEL_BCK_24 = 1,
TDM_CHANNEL_BCK_32 = 2,
};
enum {
TDM_CHANNEL_NUM_2 = 0,
TDM_CHANNEL_NUM_4 = 1,
TDM_CHANNEL_NUM_8 = 2,
};
enum {
TDM_CH_START_O30_O31 = 0,
TDM_CH_START_O32_O33,
TDM_CH_START_O34_O35,
TDM_CH_START_O36_O37,
TDM_CH_ZERO,
};
enum {
HDMI_BIT_WIDTH_16_BIT = 0,
HDMI_BIT_WIDTH_32_BIT = 1,
};
static unsigned int get_hdmi_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
HDMI_BIT_WIDTH_16_BIT : HDMI_BIT_WIDTH_32_BIT;
}
static unsigned int get_tdm_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
}
static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
}
static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) - 1;
}
static unsigned int get_tdm_ch(unsigned int ch)
{
switch (ch) {
case 1:
case 2:
return TDM_CHANNEL_NUM_2;
case 3:
case 4:
return TDM_CHANNEL_NUM_4;
case 5:
case 6:
case 7:
case 8:
default:
return TDM_CHANNEL_NUM_8;
}
}
static unsigned int get_tdm_ch_fixup(unsigned int channels)
{
if (channels > 4)
return 8;
else if (channels > 2)
return 4;
else
return 2;
}
static unsigned int get_tdm_ch_per_sdata(unsigned int mode,
unsigned int channels)
{
if (mode == TDM_OUT_TDM)
return get_tdm_ch_fixup(channels);
else
return 2;
}
/* interconnection */
enum {
HDMI_CONN_CH0 = 0,
HDMI_CONN_CH1,
HDMI_CONN_CH2,
HDMI_CONN_CH3,
HDMI_CONN_CH4,
HDMI_CONN_CH5,
HDMI_CONN_CH6,
HDMI_CONN_CH7,
};
static const char *const hdmi_conn_mux_map[] = {
"CH0", "CH1", "CH2", "CH3",
"CH4", "CH5", "CH6", "CH7",
};
static int hdmi_conn_mux_map_value[] = {
HDMI_CONN_CH0,
HDMI_CONN_CH1,
HDMI_CONN_CH2,
HDMI_CONN_CH3,
HDMI_CONN_CH4,
HDMI_CONN_CH5,
HDMI_CONN_CH6,
HDMI_CONN_CH7,
};
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_0_SFT,
HDMI_O_0_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch0_mux_control =
SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_1_SFT,
HDMI_O_1_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch1_mux_control =
SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_2_SFT,
HDMI_O_2_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch2_mux_control =
SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_3_SFT,
HDMI_O_3_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch3_mux_control =
SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_4_SFT,
HDMI_O_4_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch4_mux_control =
SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_5_SFT,
HDMI_O_5_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch5_mux_control =
SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_6_SFT,
HDMI_O_6_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch6_mux_control =
SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_7_SFT,
HDMI_O_7_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch7_mux_control =
SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_TDM_MCK_EN,
SUPPLY_SEQ_TDM_BCK_EN,
};
static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8183_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
break;
case SND_SOC_DAPM_POST_PMD:
mt8183_mck_disable(afe, tdm_priv->bck_id);
break;
default:
break;
}
return 0;
}
static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8183_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
break;
case SND_SOC_DAPM_POST_PMD:
tdm_priv->mclk_rate = 0;
mt8183_mck_disable(afe, tdm_priv->mclk_id);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch0_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch1_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch2_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch3_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch4_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch5_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch6_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch7_mux_control),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),
SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
SND_SOC_NOPM, 0, 0,
mtk_tdm_bck_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
SND_SOC_NOPM, 0, 0,
mtk_tdm_mck_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
int cur_apll;
/* which apll */
cur_apll = mt8183_get_apll_by_name(afe, source->name);
return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
}
static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
{"HDMI_CH0_MUX", "CH0", "HDMI"},
{"HDMI_CH0_MUX", "CH1", "HDMI"},
{"HDMI_CH0_MUX", "CH2", "HDMI"},
{"HDMI_CH0_MUX", "CH3", "HDMI"},
{"HDMI_CH0_MUX", "CH4", "HDMI"},
{"HDMI_CH0_MUX", "CH5", "HDMI"},
{"HDMI_CH0_MUX", "CH6", "HDMI"},
{"HDMI_CH0_MUX", "CH7", "HDMI"},
{"HDMI_CH1_MUX", "CH0", "HDMI"},
{"HDMI_CH1_MUX", "CH1", "HDMI"},
{"HDMI_CH1_MUX", "CH2", "HDMI"},
{"HDMI_CH1_MUX", "CH3", "HDMI"},
{"HDMI_CH1_MUX", "CH4", "HDMI"},
{"HDMI_CH1_MUX", "CH5", "HDMI"},
{"HDMI_CH1_MUX", "CH6", "HDMI"},
{"HDMI_CH1_MUX", "CH7", "HDMI"},
{"HDMI_CH2_MUX", "CH0", "HDMI"},
{"HDMI_CH2_MUX", "CH1", "HDMI"},
{"HDMI_CH2_MUX", "CH2", "HDMI"},
{"HDMI_CH2_MUX", "CH3", "HDMI"},
{"HDMI_CH2_MUX", "CH4", "HDMI"},
{"HDMI_CH2_MUX", "CH5", "HDMI"},
{"HDMI_CH2_MUX", "CH6", "HDMI"},
{"HDMI_CH2_MUX", "CH7", "HDMI"},
{"HDMI_CH3_MUX", "CH0", "HDMI"},
{"HDMI_CH3_MUX", "CH1", "HDMI"},
{"HDMI_CH3_MUX", "CH2", "HDMI"},
{"HDMI_CH3_MUX", "CH3", "HDMI"},
{"HDMI_CH3_MUX", "CH4", "HDMI"},
{"HDMI_CH3_MUX", "CH5", "HDMI"},
{"HDMI_CH3_MUX", "CH6", "HDMI"},
{"HDMI_CH3_MUX", "CH7", "HDMI"},
{"HDMI_CH4_MUX", "CH0", "HDMI"},
{"HDMI_CH4_MUX", "CH1", "HDMI"},
{"HDMI_CH4_MUX", "CH2", "HDMI"},
{"HDMI_CH4_MUX", "CH3", "HDMI"},
{"HDMI_CH4_MUX", "CH4", "HDMI"},
{"HDMI_CH4_MUX", "CH5", "HDMI"},
{"HDMI_CH4_MUX", "CH6", "HDMI"},
{"HDMI_CH4_MUX", "CH7", "HDMI"},
{"HDMI_CH5_MUX", "CH0", "HDMI"},
{"HDMI_CH5_MUX", "CH1", "HDMI"},
{"HDMI_CH5_MUX", "CH2", "HDMI"},
{"HDMI_CH5_MUX", "CH3", "HDMI"},
{"HDMI_CH5_MUX", "CH4", "HDMI"},
{"HDMI_CH5_MUX", "CH5", "HDMI"},
{"HDMI_CH5_MUX", "CH6", "HDMI"},
{"HDMI_CH5_MUX", "CH7", "HDMI"},
{"HDMI_CH6_MUX", "CH0", "HDMI"},
{"HDMI_CH6_MUX", "CH1", "HDMI"},
{"HDMI_CH6_MUX", "CH2", "HDMI"},
{"HDMI_CH6_MUX", "CH3", "HDMI"},
{"HDMI_CH6_MUX", "CH4", "HDMI"},
{"HDMI_CH6_MUX", "CH5", "HDMI"},
{"HDMI_CH6_MUX", "CH6", "HDMI"},
{"HDMI_CH6_MUX", "CH7", "HDMI"},
{"HDMI_CH7_MUX", "CH0", "HDMI"},
{"HDMI_CH7_MUX", "CH1", "HDMI"},
{"HDMI_CH7_MUX", "CH2", "HDMI"},
{"HDMI_CH7_MUX", "CH3", "HDMI"},
{"HDMI_CH7_MUX", "CH4", "HDMI"},
{"HDMI_CH7_MUX", "CH5", "HDMI"},
{"HDMI_CH7_MUX", "CH6", "HDMI"},
{"HDMI_CH7_MUX", "CH7", "HDMI"},
{"TDM", NULL, "HDMI_CH0_MUX"},
{"TDM", NULL, "HDMI_CH1_MUX"},
{"TDM", NULL, "HDMI_CH2_MUX"},
{"TDM", NULL, "HDMI_CH3_MUX"},
{"TDM", NULL, "HDMI_CH4_MUX"},
{"TDM", NULL, "HDMI_CH5_MUX"},
{"TDM", NULL, "HDMI_CH6_MUX"},
{"TDM", NULL, "HDMI_CH7_MUX"},
{"TDM", NULL, "aud_tdm_clk"},
{"TDM", NULL, "TDM_BCK"},
{"TDM_BCK", NULL, "TDM_MCK"},
{"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
{"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
};
/* dai ops */
static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
struct mtk_afe_tdm_priv *tdm_priv,
int freq)
{
int apll;
int apll_rate;
apll = mt8183_get_apll_by_rate(afe, freq);
apll_rate = mt8183_get_apll_rate(afe, apll);
if (!freq || freq > apll_rate) {
dev_warn(afe->dev,
"%s(), freq(%d Hz) invalid\n", __func__, freq);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_warn(afe->dev,
"%s(), APLL cannot generate %d Hz", __func__, freq);
return -EINVAL;
}
tdm_priv->mclk_rate = freq;
tdm_priv->mclk_apll = apll;
return 0;
}
static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int tdm_id = dai->id;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];
unsigned int tdm_out_mode = tdm_priv->tdm_out_mode;
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
unsigned int out_channels_per_sdata =
get_tdm_ch_per_sdata(tdm_out_mode, channels);
snd_pcm_format_t format = params_format(params);
unsigned int tdm_con = 0;
/* calculate mclk_rate, if not set explicitly */
if (!tdm_priv->mclk_rate) {
tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
mtk_dai_tdm_cal_mclk(afe,
tdm_priv,
tdm_priv->mclk_rate);
}
/* calculate bck */
tdm_priv->bck_rate = rate *
out_channels_per_sdata *
snd_pcm_format_physical_width(format);
if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
dev_warn(afe->dev, "%s(), bck_rate > mclk_rate rate", __func__);
if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
dev_warn(afe->dev, "%s(), bck cannot generate", __func__);
dev_info(afe->dev, "%s(), id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",
__func__,
tdm_id, rate, channels, format,
tdm_priv->mclk_rate, tdm_priv->bck_rate);
dev_info(afe->dev, "%s(), out_channels_per_sdata = %d\n",
__func__, out_channels_per_sdata);
/* set tdm */
if (tdm_priv->bck_invert)
regmap_update_bits(afe->regmap, AUDIO_TOP_CON3,
BCK_INVERSE_MASK_SFT,
0x1 << BCK_INVERSE_SFT);
if (tdm_priv->lck_invert)
tdm_con |= 1 << LRCK_INVERSE_SFT;
if (tdm_priv->tdm_out_mode == TDM_OUT_I2S) {
tdm_con |= 1 << DELAY_DATA_SFT;
tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
} else if (tdm_priv->tdm_out_mode == TDM_OUT_TDM) {
tdm_con |= 0 << DELAY_DATA_SFT;
tdm_con |= 0 << LRCK_TDM_WIDTH_SFT;
}
tdm_con |= 1 << LEFT_ALIGN_SFT;
tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
tdm_con |= get_tdm_ch(out_channels_per_sdata) << CHANNEL_NUM_SFT;
tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
if (out_channels_per_sdata == 2) {
switch (channels) {
case 1:
case 2:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
break;
case 3:
case 4:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
break;
case 5:
case 6:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
break;
case 7:
case 8:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
break;
default:
tdm_con = 0;
}
} else {
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
}
regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
AFE_HDMI_OUT_CH_NUM_MASK_SFT,
channels << AFE_HDMI_OUT_CH_NUM_SFT);
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT,
get_hdmi_wlen(format) << AFE_HDMI_OUT_BIT_WIDTH_SFT);
return 0;
}
static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream,
int cmd,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
/* enable Out control */
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
AFE_HDMI_OUT_ON_MASK_SFT,
0x1 << AFE_HDMI_OUT_ON_SFT);
/* enable tdm */
regmap_update_bits(afe->regmap, AFE_TDM_CON1,
TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
/* disable tdm */
regmap_update_bits(afe->regmap, AFE_TDM_CON1,
TDM_EN_MASK_SFT, 0);
/* disable Out control */
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
AFE_HDMI_OUT_ON_MASK_SFT,
0);
break;
default:
return -EINVAL;
}
return 0;
}
static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
if (dir != SND_SOC_CLOCK_OUT) {
dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
return -EINVAL;
}
dev_info(afe->dev, "%s(), freq %d\n", __func__, freq);
return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
}
static int mtk_dai_tdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
/* DAI mode*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
tdm_priv->tdm_out_mode = TDM_OUT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
tdm_priv->tdm_out_mode = TDM_OUT_TDM;
break;
default:
tdm_priv->tdm_out_mode = TDM_OUT_I2S;
}
/* DAI clock inversion*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
tdm_priv->bck_invert = TDM_BCK_NON_INV;
tdm_priv->lck_invert = TDM_LCK_NON_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
tdm_priv->bck_invert = TDM_BCK_NON_INV;
tdm_priv->lck_invert = TDM_LCK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
tdm_priv->bck_invert = TDM_BCK_INV;
tdm_priv->lck_invert = TDM_LCK_NON_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
default:
tdm_priv->bck_invert = TDM_BCK_INV;
tdm_priv->lck_invert = TDM_LCK_INV;
break;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
.hw_params = mtk_dai_tdm_hw_params,
.trigger = mtk_dai_tdm_trigger,
.set_sysclk = mtk_dai_tdm_set_sysclk,
.set_fmt = mtk_dai_tdm_set_fmt,
};
/* dai driver */
#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
{
.name = "TDM",
.id = MT8183_DAI_TDM,
.playback = {
.stream_name = "TDM",
.channels_min = 2,
.channels_max = 8,
.rates = MTK_TDM_RATES,
.formats = MTK_TDM_FORMATS,
},
.ops = &mtk_dai_tdm_ops,
},
};
int mt8183_dai_tdm_register(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv;
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_tdm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
dai->dapm_widgets = mtk_dai_tdm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
dai->dapm_routes = mtk_dai_tdm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
GFP_KERNEL);
if (!tdm_priv)
return -ENOMEM;
tdm_priv->mclk_multiple = 128;
tdm_priv->bck_id = MT8183_I2S4_BCK;
tdm_priv->mclk_id = MT8183_I2S4_MCK;
afe_priv->dai_priv[MT8183_DAI_TDM] = tdm_priv;
return 0;
}
| linux-master | sound/soc/mediatek/mt8183/mt8183-dai-tdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI ADDA Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/regmap.h>
#include <linux/delay.h>
#include "mt8183-afe-common.h"
#include "mt8183-interconnection.h"
#include "mt8183-reg.h"
enum {
AUDIO_SDM_LEVEL_MUTE = 0,
AUDIO_SDM_LEVEL_NORMAL = 0x1d,
/* if you change level normal */
/* you need to change formula of hp impedance and dc trim too */
};
enum {
DELAY_DATA_MISO1 = 0,
DELAY_DATA_MISO2,
};
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
};
static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_DL_RATE_48K;
}
}
static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_UL_RATE_48K;
}
}
/* dai component */
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
I_PCM_2_CAP_CH2, 1, 0),
};
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* update setting to dmic */
if (afe_priv->mtkaif_dmic) {
/* mtkaif_rxif_data_mode = 1, dmic */
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0x1, 0x1);
/* dmic mode, 3.25M*/
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0x0, 0xf << 20);
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
0x0, 0x1 << 5);
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
0x0, 0x3 << 14);
/* turn on dmic, ch1, ch2 */
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
0x1 << 1, 0x1 << 1);
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
0x3 << 21, 0x3 << 21);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
/* mtkaif dmic */
static const char * const mt8183_adda_off_on_str[] = {
"Off", "On"
};
static const struct soc_enum mt8183_adda_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
mt8183_adda_off_on_str),
};
static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
return 0;
}
static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
__func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
return 0;
}
static const struct snd_kcontrol_new mtk_adda_controls[] = {
SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
mt8183_adda_dmic_get, mt8183_adda_dmic_set),
};
enum {
SUPPLY_SEQ_ADDA_AFE_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_UL_ON,
};
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
/* adda */
SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch1_mix,
ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch2_mix,
ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
};
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
/* playback */
{"ADDA_DL_CH1", "DL1_CH1", "DL1"},
{"ADDA_DL_CH2", "DL1_CH1", "DL1"},
{"ADDA_DL_CH2", "DL1_CH2", "DL1"},
{"ADDA_DL_CH1", "DL2_CH1", "DL2"},
{"ADDA_DL_CH2", "DL2_CH1", "DL2"},
{"ADDA_DL_CH2", "DL2_CH2", "DL2"},
{"ADDA_DL_CH1", "DL3_CH1", "DL3"},
{"ADDA_DL_CH2", "DL3_CH1", "DL3"},
{"ADDA_DL_CH2", "DL3_CH2", "DL3"},
{"ADDA Playback", NULL, "ADDA_DL_CH1"},
{"ADDA Playback", NULL, "ADDA_DL_CH2"},
/* adda enable */
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
/* clk */
{"ADDA Playback", NULL, "mtkaif_26m_clk"},
{"ADDA Playback", NULL, "aud_dac_clk"},
{"ADDA Playback", NULL, "aud_dac_predis_clk"},
{"ADDA Capture", NULL, "mtkaif_26m_clk"},
{"ADDA Capture", NULL, "aud_adc_clk"},
};
static int set_mtkaif_rx(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int delay_data;
int delay_cycle;
switch (afe_priv->mtkaif_protocol) {
case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
/* mtkaif_rxif_clkinv_adc inverse for calibration */
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0x80010000);
if (afe_priv->mtkaif_phase_cycle[0] >=
afe_priv->mtkaif_phase_cycle[1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
afe_priv->mtkaif_phase_cycle[1];
} else {
delay_data = DELAY_DATA_MISO2;
delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
afe_priv->mtkaif_phase_cycle[0];
}
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
break;
case MT8183_MTKAIF_PROTOCOL_2:
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0x00010000);
break;
case MT8183_MTKAIF_PROTOCOL_1:
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
break;
default:
break;
}
return 0;
}
/* dai ops */
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, dai->id, substream->stream, rate);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
unsigned int dl_src2_con0 = 0;
unsigned int dl_src2_con1 = 0;
/* clean predistortion */
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
/* set sampling rate */
dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
/* set output mode */
switch (rate) {
case 192000:
dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
dl_src2_con0 |= 1 << 14;
break;
case 96000:
dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
dl_src2_con0 |= 1 << 14;
break;
default:
dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
break;
}
/* turn off mute function */
dl_src2_con0 |= (0x03 << 11);
/* set voice input data if input sample rate is 8k or 16k */
if (rate == 8000 || rate == 16000)
dl_src2_con0 |= 0x01 << 5;
/* SA suggest apply -0.3db to audio/speech path */
dl_src2_con1 = 0xf74f0000;
/* turn on down-link gain */
dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
/* set sdm gain */
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_DCCOMP_CON,
ATTGAIN_CTL_MASK_SFT,
AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
} else {
unsigned int voice_mode = 0;
unsigned int ul_src_con0 = 0; /* default value */
/* set mtkaif protocol */
set_mtkaif_rx(afe);
/* Using Internal ADC */
regmap_update_bits(afe->regmap,
AFE_ADDA_TOP_CON0,
0x1 << 0,
0x0 << 0);
voice_mode = adda_ul_rate_transform(afe, rate);
ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
/* enable iir */
ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
UL_IIR_ON_TMP_CTL_MASK_SFT;
/* 35Hz @ 48k */
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_02_01, 0x00000000);
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
/* mtkaif_rxif_data_mode = 0, amic */
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG0,
0x1 << 0,
0x0 << 0);
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "ADDA",
.id = MT8183_DAI_ADDA,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
int mt8183_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->controls = mtk_adda_controls;
dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt8183/mt8183-dai-adda.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8183-afe-common.h"
#include "mt8183-interconnection.h"
#include "mt8183-reg.h"
enum AUD_TX_LCH_RPT {
AUD_TX_LCH_RPT_NO_REPEAT = 0,
AUD_TX_LCH_RPT_REPEAT = 1
};
enum AUD_VBT_16K_MODE {
AUD_VBT_16K_MODE_DISABLE = 0,
AUD_VBT_16K_MODE_ENABLE = 1
};
enum AUD_EXT_MODEM {
AUD_EXT_MODEM_SELECT_INTERNAL = 0,
AUD_EXT_MODEM_SELECT_EXTERNAL = 1
};
enum AUD_PCM_SYNC_TYPE {
/* bck sync length = 1 */
AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
/* bck sync length = PCM_INTF_CON1[9:13] */
AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
};
enum AUD_BT_MODE {
AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
};
enum AUD_PCM_AFIFO_SRC {
/* slave mode & external modem uses different crystal */
AUD_PCM_AFIFO_ASRC = 0,
/* slave mode & external modem uses the same crystal */
AUD_PCM_AFIFO_AFIFO = 1
};
enum AUD_PCM_CLOCK_SOURCE {
AUD_PCM_CLOCK_MASTER_MODE = 0,
AUD_PCM_CLOCK_SLAVE_MODE = 1
};
enum AUD_PCM_WLEN {
AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
};
enum AUD_PCM_MODE {
AUD_PCM_MODE_PCM_MODE_8K = 0,
AUD_PCM_MODE_PCM_MODE_16K = 1,
AUD_PCM_MODE_PCM_MODE_32K = 2,
AUD_PCM_MODE_PCM_MODE_48K = 3,
};
enum AUD_PCM_FMT {
AUD_PCM_FMT_I2S = 0,
AUD_PCM_FMT_EIAJ = 1,
AUD_PCM_FMT_PCM_MODE_A = 2,
AUD_PCM_FMT_PCM_MODE_B = 3
};
enum AUD_BCLK_OUT_INV {
AUD_BCLK_OUT_INV_NO_INVERSE = 0,
AUD_BCLK_OUT_INV_INVERSE = 1
};
enum AUD_PCM_EN {
AUD_PCM_EN_DISABLE = 0,
AUD_PCM_EN_ENABLE = 1
};
/* dai component */
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN7,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN7,
I_DL2_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN8,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN8,
I_DL2_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN27,
I_DL1_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN17,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN17,
I_DL2_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN18,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN18,
I_DL2_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN24,
I_DL1_CH1, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH4", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch4_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch4_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch2_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH4", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch4_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch4_mix)),
SND_SOC_DAPM_SUPPLY("PCM_1_EN", PCM_INTF_CON1, PCM_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("PCM_2_EN", PCM2_INTF_CON, PCM2_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_INPUT("MD1_TO_AFE"),
SND_SOC_DAPM_INPUT("MD2_TO_AFE"),
SND_SOC_DAPM_OUTPUT("AFE_TO_MD1"),
SND_SOC_DAPM_OUTPUT("AFE_TO_MD2"),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH4"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH1"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH2"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH4"},
{"PCM 1 Playback", NULL, "PCM_1_EN"},
{"PCM 2 Playback", NULL, "PCM_2_EN"},
{"PCM 1 Capture", NULL, "PCM_1_EN"},
{"PCM 2 Capture", NULL, "PCM_2_EN"},
{"AFE_TO_MD1", NULL, "PCM 2 Playback"},
{"AFE_TO_MD2", NULL, "PCM 1 Playback"},
{"PCM 2 Capture", NULL, "MD1_TO_AFE"},
{"PCM 1 Capture", NULL, "MD2_TO_AFE"},
{"PCM_1_PB_CH1", "DL2_CH1", "DL2"},
{"PCM_1_PB_CH2", "DL2_CH2", "DL2"},
{"PCM_1_PB_CH4", "DL1_CH1", "DL1"},
{"PCM_2_PB_CH1", "DL2_CH1", "DL2"},
{"PCM_2_PB_CH2", "DL2_CH2", "DL2"},
{"PCM_2_PB_CH4", "DL1_CH1", "DL1"},
};
/* dai ops */
static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct snd_soc_dapm_widget *p = snd_soc_dai_get_widget_playback(dai);
struct snd_soc_dapm_widget *c = snd_soc_dai_get_widget_capture(dai);
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8183_rate_transform(afe->dev, rate, dai->id);
unsigned int pcm_con = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d, rate_reg %d, widget active p %d, c %d\n",
__func__,
dai->id,
substream->stream,
rate,
rate_reg,
p->active, c->active);
if (p->active || c->active)
return 0;
switch (dai->id) {
case MT8183_DAI_PCM_1:
pcm_con |= AUD_BCLK_OUT_INV_NO_INVERSE << PCM_BCLK_OUT_INV_SFT;
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
pcm_con |= AUD_EXT_MODEM_SELECT_INTERNAL << PCM_EXT_MODEM_SFT;
pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
pcm_con |= AUD_PCM_CLOCK_SLAVE_MODE << PCM_SLAVE_SFT;
pcm_con |= rate_reg << PCM_MODE_SFT;
pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM_FMT_SFT;
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
0xfffffffe, pcm_con);
break;
case MT8183_DAI_PCM_2:
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM2_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM2_VBT_16K_MODE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM2_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM2_AFIFO_SFT;
pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM2_WLEN_SFT;
pcm_con |= rate_reg << PCM2_MODE_SFT;
pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM2_FMT_SFT;
regmap_update_bits(afe->regmap, PCM2_INTF_CON,
0xfffffffe, pcm_con);
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, dai->id);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.hw_params = mtk_dai_pcm_hw_params,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM 1",
.id = MT8183_DAI_PCM_1,
.playback = {
.stream_name = "PCM 1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "PCM 2",
.id = MT8183_DAI_PCM_2,
.playback = {
.stream_name = "PCM 2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
int mt8183_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt8183/mt8183-dai-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8183-afe-clk.c -- Mediatek 8183 afe clock ctrl
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/clk.h>
#include "mt8183-afe-common.h"
#include "mt8183-afe-clk.h"
#include "mt8183-reg.h"
enum {
CLK_AFE = 0,
CLK_TML,
CLK_APLL22M,
CLK_APLL24M,
CLK_APLL1_TUNER,
CLK_APLL2_TUNER,
CLK_I2S1_BCLK_SW,
CLK_I2S2_BCLK_SW,
CLK_I2S3_BCLK_SW,
CLK_I2S4_BCLK_SW,
CLK_INFRA_SYS_AUDIO,
CLK_MUX_AUDIO,
CLK_MUX_AUDIOINTBUS,
CLK_TOP_SYSPLL_D2_D4,
/* apll related mux */
CLK_TOP_MUX_AUD_1,
CLK_TOP_APLL1_CK,
CLK_TOP_MUX_AUD_2,
CLK_TOP_APLL2_CK,
CLK_TOP_MUX_AUD_ENG1,
CLK_TOP_APLL1_D8,
CLK_TOP_MUX_AUD_ENG2,
CLK_TOP_APLL2_D8,
CLK_TOP_I2S0_M_SEL,
CLK_TOP_I2S1_M_SEL,
CLK_TOP_I2S2_M_SEL,
CLK_TOP_I2S3_M_SEL,
CLK_TOP_I2S4_M_SEL,
CLK_TOP_I2S5_M_SEL,
CLK_TOP_APLL12_DIV0,
CLK_TOP_APLL12_DIV1,
CLK_TOP_APLL12_DIV2,
CLK_TOP_APLL12_DIV3,
CLK_TOP_APLL12_DIV4,
CLK_TOP_APLL12_DIVB,
CLK_CLK26M,
CLK_NUM
};
static const char *aud_clks[CLK_NUM] = {
[CLK_AFE] = "aud_afe_clk",
[CLK_TML] = "aud_tml_clk",
[CLK_APLL22M] = "aud_apll22m_clk",
[CLK_APLL24M] = "aud_apll24m_clk",
[CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
[CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
[CLK_I2S1_BCLK_SW] = "aud_i2s1_bclk_sw",
[CLK_I2S2_BCLK_SW] = "aud_i2s2_bclk_sw",
[CLK_I2S3_BCLK_SW] = "aud_i2s3_bclk_sw",
[CLK_I2S4_BCLK_SW] = "aud_i2s4_bclk_sw",
[CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
[CLK_MUX_AUDIO] = "top_mux_audio",
[CLK_MUX_AUDIOINTBUS] = "top_mux_aud_intbus",
[CLK_TOP_SYSPLL_D2_D4] = "top_syspll_d2_d4",
[CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
[CLK_TOP_APLL1_CK] = "top_apll1_ck",
[CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
[CLK_TOP_APLL2_CK] = "top_apll2_ck",
[CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
[CLK_TOP_APLL1_D8] = "top_apll1_d8",
[CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
[CLK_TOP_APLL2_D8] = "top_apll2_d8",
[CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
[CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
[CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
[CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
[CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
[CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
[CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
[CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
[CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
[CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
[CLK_CLK26M] = "top_clk26m_clk",
};
int mt8183_init_clock(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int i;
afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
__func__, aud_clks[i],
PTR_ERR(afe_priv->clk[i]));
return PTR_ERR(afe_priv->clk[i]);
}
}
return 0;
}
int mt8183_afe_enable_clock(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
goto CLK_INFRA_SYS_AUDIO_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO], ret);
goto CLK_MUX_AUDIO_ERR;
}
ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO],
aud_clks[CLK_CLK26M], ret);
goto CLK_MUX_AUDIO_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
goto CLK_MUX_AUDIO_INTBUS_ERR;
}
ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);
goto CLK_MUX_AUDIO_INTBUS_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_AFE], ret);
goto CLK_AFE_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_I2S1_BCLK_SW], ret);
goto CLK_I2S1_BCLK_SW_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_I2S2_BCLK_SW], ret);
goto CLK_I2S2_BCLK_SW_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_I2S3_BCLK_SW], ret);
goto CLK_I2S3_BCLK_SW_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_I2S4_BCLK_SW], ret);
goto CLK_I2S4_BCLK_SW_ERR;
}
return 0;
CLK_I2S4_BCLK_SW_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
CLK_I2S3_BCLK_SW_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
CLK_I2S2_BCLK_SW_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
CLK_I2S1_BCLK_SW_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
CLK_AFE_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
CLK_MUX_AUDIO_INTBUS_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
CLK_MUX_AUDIO_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
CLK_INFRA_SYS_AUDIO_ERR:
return ret;
}
int mt8183_afe_disable_clock(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]);
clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
return 0;
}
/* apll */
static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int ret;
if (enable) {
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
goto ERR_ENABLE_CLK_TOP_MUX_AUD_1;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_TOP_APLL1_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_TOP_APLL1_CK], ret);
goto ERR_SELECT_CLK_TOP_MUX_AUD_1;
}
/* 180.6336 / 8 = 22.5792MHz */
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_TOP_APLL1_D8]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_TOP_APLL1_D8], ret);
goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
}
return 0;
ERR_SELECT_CLK_TOP_MUX_AUD_ENG1:
clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_CLK26M]);
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1:
ERR_SELECT_CLK_TOP_MUX_AUD_1:
clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_CLK26M]);
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
ERR_ENABLE_CLK_TOP_MUX_AUD_1:
EXIT:
return ret;
}
static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int ret;
if (enable) {
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
goto ERR_ENABLE_CLK_TOP_MUX_AUD_2;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_TOP_APLL2_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_TOP_APLL2_CK], ret);
goto ERR_SELECT_CLK_TOP_MUX_AUD_2;
}
/* 196.608 / 8 = 24.576MHz */
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_TOP_APLL2_D8]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_TOP_APLL2_D8], ret);
goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
}
return 0;
ERR_SELECT_CLK_TOP_MUX_AUD_ENG2:
clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_CLK26M]);
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2:
ERR_SELECT_CLK_TOP_MUX_AUD_2:
clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_CLK26M]);
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
ERR_ENABLE_CLK_TOP_MUX_AUD_2:
EXIT:
return ret;
}
int mt8183_apll1_enable(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int ret;
/* setting for APLL */
apll1_mux_setting(afe, true);
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL22M], ret);
goto ERR_CLK_APLL22M;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL1_TUNER], ret);
goto ERR_CLK_APLL1_TUNER;
}
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
0x0000FFF7, 0x00000832);
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_22M_ON_MASK_SFT,
0x1 << AFE_22M_ON_SFT);
return 0;
ERR_CLK_APLL1_TUNER:
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
ERR_CLK_APLL22M:
return ret;
}
void mt8183_apll1_disable(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_22M_ON_MASK_SFT,
0x0 << AFE_22M_ON_SFT);
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
apll1_mux_setting(afe, false);
}
int mt8183_apll2_enable(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int ret;
/* setting for APLL */
apll2_mux_setting(afe, true);
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL24M], ret);
goto ERR_CLK_APLL24M;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL2_TUNER], ret);
goto ERR_CLK_APLL2_TUNER;
}
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
0x0000FFF7, 0x00000634);
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_24M_ON_MASK_SFT,
0x1 << AFE_24M_ON_SFT);
return 0;
ERR_CLK_APLL2_TUNER:
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
ERR_CLK_APLL24M:
return ret;
}
void mt8183_apll2_disable(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_24M_ON_MASK_SFT,
0x0 << AFE_24M_ON_SFT);
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
apll2_mux_setting(afe, false);
}
int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll)
{
return (apll == MT8183_APLL1) ? 180633600 : 196608000;
}
int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
{
return ((rate % 8000) == 0) ? MT8183_APLL2 : MT8183_APLL1;
}
int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
{
if (strcmp(name, APLL1_W_NAME) == 0)
return MT8183_APLL1;
else
return MT8183_APLL2;
}
/* mck */
struct mt8183_mck_div {
int m_sel_id;
int div_clk_id;
};
static const struct mt8183_mck_div mck_div[MT8183_MCK_NUM] = {
[MT8183_I2S0_MCK] = {
.m_sel_id = CLK_TOP_I2S0_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV0,
},
[MT8183_I2S1_MCK] = {
.m_sel_id = CLK_TOP_I2S1_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV1,
},
[MT8183_I2S2_MCK] = {
.m_sel_id = CLK_TOP_I2S2_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV2,
},
[MT8183_I2S3_MCK] = {
.m_sel_id = CLK_TOP_I2S3_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV3,
},
[MT8183_I2S4_MCK] = {
.m_sel_id = CLK_TOP_I2S4_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV4,
},
[MT8183_I2S4_BCK] = {
.m_sel_id = -1,
.div_clk_id = CLK_TOP_APLL12_DIVB,
},
[MT8183_I2S5_MCK] = {
.m_sel_id = -1,
.div_clk_id = -1,
},
};
int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int apll = mt8183_get_apll_by_rate(afe, rate);
int apll_clk_id = apll == MT8183_APLL1 ?
CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
int m_sel_id = mck_div[mck_id].m_sel_id;
int div_clk_id = mck_div[mck_id].div_clk_id;
int ret;
/* i2s5 mck not support */
if (mck_id == MT8183_I2S5_MCK)
return 0;
/* select apll */
if (m_sel_id >= 0) {
ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[m_sel_id], ret);
goto ERR_ENABLE_MCLK;
}
ret = clk_set_parent(afe_priv->clk[m_sel_id],
afe_priv->clk[apll_clk_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[m_sel_id],
aud_clks[apll_clk_id], ret);
goto ERR_SELECT_MCLK;
}
}
/* enable div, set rate */
ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[div_clk_id], ret);
goto ERR_ENABLE_MCLK_DIV;
}
ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
__func__, aud_clks[div_clk_id],
rate, ret);
goto ERR_SET_MCLK_RATE;
}
return 0;
ERR_SET_MCLK_RATE:
clk_disable_unprepare(afe_priv->clk[div_clk_id]);
ERR_ENABLE_MCLK_DIV:
ERR_SELECT_MCLK:
if (m_sel_id >= 0)
clk_disable_unprepare(afe_priv->clk[m_sel_id]);
ERR_ENABLE_MCLK:
return ret;
}
void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int m_sel_id = mck_div[mck_id].m_sel_id;
int div_clk_id = mck_div[mck_id].div_clk_id;
/* i2s5 mck not support */
if (mck_id == MT8183_I2S5_MCK)
return;
clk_disable_unprepare(afe_priv->clk[div_clk_id]);
if (m_sel_id >= 0)
clk_disable_unprepare(afe_priv->clk[m_sel_id]);
}
| linux-master | sound/soc/mediatek/mt8183/mt8183-afe-clk.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra30_i2s.c - Tegra30 I2S driver
*
* Author: Stephen Warren <[email protected]>
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* Based on code copyright/by:
*
* Copyright (c) 2009-2010, NVIDIA Corporation.
* Scott Peterson <[email protected]>
*
* Copyright (C) 2010 Google, Inc.
* Iliyan Malchev <[email protected]>
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra30_ahub.h"
#include "tegra30_i2s.h"
#define DRV_NAME "tegra30-i2s"
static __maybe_unused int tegra30_i2s_runtime_suspend(struct device *dev)
{
struct tegra30_i2s *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
clk_disable_unprepare(i2s->clk_i2s);
return 0;
}
static __maybe_unused int tegra30_i2s_runtime_resume(struct device *dev)
{
struct tegra30_i2s *i2s = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s->clk_i2s);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
regcache_cache_only(i2s->regmap, false);
regcache_mark_dirty(i2s->regmap);
ret = regcache_sync(i2s->regmap);
if (ret)
goto disable_clocks;
return 0;
disable_clocks:
clk_disable_unprepare(i2s->clk_i2s);
return ret;
}
static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask = 0, val = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
break;
case SND_SOC_DAIFMT_BC_FC:
break;
default:
return -EINVAL;
}
mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
TEGRA30_I2S_CTRL_LRCK_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_DSP_B:
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
break;
case SND_SOC_DAIFMT_I2S:
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
break;
default:
return -EINVAL;
}
pm_runtime_get_sync(dai->dev);
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
pm_runtime_put(dai->dev);
return 0;
}
static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val, reg;
int ret, sample_size, srate, i2sclock, bitcnt;
struct tegra30_ahub_cif_conf cif_conf;
if (params_channels(params) != 2)
return -EINVAL;
mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
sample_size = 16;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
srate = params_rate(params);
/* Final "* 2" required by Tegra hardware */
i2sclock = srate * params_channels(params) * sample_size * 2;
bitcnt = (i2sclock / (2 * srate)) - 1;
if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
return -EINVAL;
ret = clk_set_rate(i2s->clk_i2s, i2sclock);
if (ret) {
dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
return ret;
}
val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
if (i2sclock % (2 * srate))
val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
cif_conf.threshold = 0;
cif_conf.audio_channels = 2;
cif_conf.client_channels = 2;
cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
cif_conf.expand = 0;
cif_conf.stereo_conv = 0;
cif_conf.replicate = 0;
cif_conf.truncate = 0;
cif_conf.mono_conv = 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
reg = TEGRA30_I2S_CIF_RX_CTRL;
} else {
cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
reg = TEGRA30_I2S_CIF_TX_CTRL;
}
i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
return 0;
}
static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
{
tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
TEGRA30_I2S_CTRL_XFER_EN_TX,
TEGRA30_I2S_CTRL_XFER_EN_TX);
}
static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
{
tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
}
static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
{
tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
TEGRA30_I2S_CTRL_XFER_EN_RX,
TEGRA30_I2S_CTRL_XFER_EN_RX);
}
static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
}
static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra30_i2s_start_playback(i2s);
else
tegra30_i2s_start_capture(i2s);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra30_i2s_stop_playback(i2s);
else
tegra30_i2s_stop_capture(i2s);
break;
default:
return -EINVAL;
}
return 0;
}
static int tegra30_i2s_set_tdm(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val;
dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n",
__func__, tx_mask, rx_mask, slots, slot_width);
mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK |
TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK |
TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) |
(rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) |
((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT);
pm_runtime_get_sync(dai->dev);
regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
/* set the fsync width to minimum of 1 clock width */
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL,
TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK, 0x0);
pm_runtime_put(dai->dev);
return 0;
}
static int tegra30_i2s_probe(struct snd_soc_dai *dai)
{
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
&i2s->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
.probe = tegra30_i2s_probe,
.set_fmt = tegra30_i2s_set_fmt,
.hw_params = tegra30_i2s_hw_params,
.trigger = tegra30_i2s_trigger,
.set_tdm_slot = tegra30_i2s_set_tdm,
};
static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tegra30_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver tegra30_i2s_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA30_I2S_CTRL:
case TEGRA30_I2S_TIMING:
case TEGRA30_I2S_OFFSET:
case TEGRA30_I2S_CH_CTRL:
case TEGRA30_I2S_SLOT_CTRL:
case TEGRA30_I2S_CIF_RX_CTRL:
case TEGRA30_I2S_CIF_TX_CTRL:
case TEGRA30_I2S_FLOWCTL:
case TEGRA30_I2S_TX_STEP:
case TEGRA30_I2S_FLOW_STATUS:
case TEGRA30_I2S_FLOW_TOTAL:
case TEGRA30_I2S_FLOW_OVER:
case TEGRA30_I2S_FLOW_UNDER:
case TEGRA30_I2S_LCOEF_1_4_0:
case TEGRA30_I2S_LCOEF_1_4_1:
case TEGRA30_I2S_LCOEF_1_4_2:
case TEGRA30_I2S_LCOEF_1_4_3:
case TEGRA30_I2S_LCOEF_1_4_4:
case TEGRA30_I2S_LCOEF_1_4_5:
case TEGRA30_I2S_LCOEF_2_4_0:
case TEGRA30_I2S_LCOEF_2_4_1:
case TEGRA30_I2S_LCOEF_2_4_2:
return true;
default:
return false;
}
}
static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA30_I2S_FLOW_STATUS:
case TEGRA30_I2S_FLOW_TOTAL:
case TEGRA30_I2S_FLOW_OVER:
case TEGRA30_I2S_FLOW_UNDER:
return true;
default:
return false;
}
}
static const struct regmap_config tegra30_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA30_I2S_LCOEF_2_4_2,
.writeable_reg = tegra30_i2s_wr_rd_reg,
.readable_reg = tegra30_i2s_wr_rd_reg,
.volatile_reg = tegra30_i2s_volatile_reg,
.cache_type = REGCACHE_FLAT,
};
static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
.set_audio_cif = tegra30_ahub_set_cif,
};
static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
.set_audio_cif = tegra124_ahub_set_cif,
};
static const struct of_device_id tegra30_i2s_of_match[] = {
{ .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
{ .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
{},
};
static int tegra30_i2s_platform_probe(struct platform_device *pdev)
{
struct tegra30_i2s *i2s;
const struct tegra30_i2s_soc_data *soc_data;
u32 cif_ids[2];
void __iomem *regs;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
if (!i2s) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, i2s);
soc_data = of_device_get_match_data(&pdev->dev);
if (!soc_data) {
dev_err(&pdev->dev, "Error: No device match found\n");
ret = -ENODEV;
goto err;
}
i2s->soc_data = soc_data;
i2s->dai = tegra30_i2s_dai_template;
i2s->dai.name = dev_name(&pdev->dev);
ret = of_property_read_u32_array(pdev->dev.of_node,
"nvidia,ahub-cif-ids", cif_ids,
ARRAY_SIZE(cif_ids));
if (ret < 0)
goto err;
i2s->playback_i2s_cif = cif_ids[0];
i2s->capture_i2s_cif = cif_ids[1];
i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(i2s->clk_i2s)) {
dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
ret = PTR_ERR(i2s->clk_i2s);
goto err;
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
goto err;
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra30_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
ret = PTR_ERR(i2s->regmap);
goto err;
}
regcache_cache_only(i2s->regmap, true);
pm_runtime_enable(&pdev->dev);
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->playback_dma_data.maxburst = 4;
ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
i2s->playback_dma_chan,
sizeof(i2s->playback_dma_chan),
&i2s->playback_dma_data.addr);
if (ret) {
dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
goto err_pm_disable;
}
ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
i2s->playback_fifo_cif);
if (ret) {
dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
goto err_free_tx_fifo;
}
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 4;
ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
i2s->capture_dma_chan,
sizeof(i2s->capture_dma_chan),
&i2s->capture_dma_data.addr);
if (ret) {
dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
goto err_unroute_tx_fifo;
}
ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
i2s->capture_i2s_cif);
if (ret) {
dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
goto err_free_rx_fifo;
}
ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
&i2s->dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
ret = -ENOMEM;
goto err_unroute_rx_fifo;
}
ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
&i2s->dma_config, i2s->playback_dma_chan,
i2s->capture_dma_chan);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
goto err_unregister_component;
}
return 0;
err_unregister_component:
snd_soc_unregister_component(&pdev->dev);
err_unroute_rx_fifo:
tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
err_free_rx_fifo:
tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
err_unroute_tx_fifo:
tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
err_free_tx_fifo:
tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err:
return ret;
}
static void tegra30_i2s_platform_remove(struct platform_device *pdev)
{
struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
tegra_pcm_platform_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra30_i2s_pm_ops = {
SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
tegra30_i2s_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra30_i2s_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = tegra30_i2s_of_match,
.pm = &tegra30_i2s_pm_ops,
},
.probe = tegra30_i2s_platform_probe,
.remove_new = tegra30_i2s_platform_remove,
};
module_platform_driver(tegra30_i2s_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
| linux-master | sound/soc/tegra/tegra30_i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_mixer.c - Tegra210 MIXER driver
//
// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_mixer.h"
#include "tegra_cif.h"
#define MIXER_REG(reg, id) ((reg) + ((id) * TEGRA210_MIXER_REG_STRIDE))
#define MIXER_REG_BASE(reg) ((reg) % TEGRA210_MIXER_REG_STRIDE)
#define MIXER_GAIN_CFG_RAM_ADDR(id) \
(TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0 + \
((id) * TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE))
#define MIXER_RX_REG_DEFAULTS(id) \
{ MIXER_REG(TEGRA210_MIXER_RX1_CIF_CTRL, id), 0x00007700}, \
{ MIXER_REG(TEGRA210_MIXER_RX1_CTRL, id), 0x00010823}, \
{ MIXER_REG(TEGRA210_MIXER_RX1_PEAK_CTRL, id), 0x000012c0}
#define MIXER_TX_REG_DEFAULTS(id) \
{ MIXER_REG(TEGRA210_MIXER_TX1_INT_MASK, (id)), 0x00000001}, \
{ MIXER_REG(TEGRA210_MIXER_TX1_CIF_CTRL, (id)), 0x00007700}
#define REG_DURATION_PARAM(reg, i) ((reg) + NUM_GAIN_POLY_COEFFS + 1 + (i))
static const struct reg_default tegra210_mixer_reg_defaults[] = {
/* Inputs */
MIXER_RX_REG_DEFAULTS(0),
MIXER_RX_REG_DEFAULTS(1),
MIXER_RX_REG_DEFAULTS(2),
MIXER_RX_REG_DEFAULTS(3),
MIXER_RX_REG_DEFAULTS(4),
MIXER_RX_REG_DEFAULTS(5),
MIXER_RX_REG_DEFAULTS(6),
MIXER_RX_REG_DEFAULTS(7),
MIXER_RX_REG_DEFAULTS(8),
MIXER_RX_REG_DEFAULTS(9),
/* Outputs */
MIXER_TX_REG_DEFAULTS(0),
MIXER_TX_REG_DEFAULTS(1),
MIXER_TX_REG_DEFAULTS(2),
MIXER_TX_REG_DEFAULTS(3),
MIXER_TX_REG_DEFAULTS(4),
{ TEGRA210_MIXER_CG, 0x00000001},
{ TEGRA210_MIXER_GAIN_CFG_RAM_CTRL, 0x00004000},
{ TEGRA210_MIXER_PEAKM_RAM_CTRL, 0x00004000},
{ TEGRA210_MIXER_ENABLE, 0x1 },
};
/* Default gain parameters */
static const struct tegra210_mixer_gain_params gain_params = {
/* Polynomial coefficients */
{ 0, 0, 0, 0, 0, 0, 0, 0x1000000, 0 },
/* Gain value */
0x10000,
/* Duration Parameters */
{ 0, 0, 0x400, 0x8000000 },
};
static int __maybe_unused tegra210_mixer_runtime_suspend(struct device *dev)
{
struct tegra210_mixer *mixer = dev_get_drvdata(dev);
regcache_cache_only(mixer->regmap, true);
regcache_mark_dirty(mixer->regmap);
return 0;
}
static int __maybe_unused tegra210_mixer_runtime_resume(struct device *dev)
{
struct tegra210_mixer *mixer = dev_get_drvdata(dev);
regcache_cache_only(mixer->regmap, false);
regcache_sync(mixer->regmap);
return 0;
}
static int tegra210_mixer_write_ram(struct tegra210_mixer *mixer,
unsigned int addr,
unsigned int coef)
{
unsigned int reg, val;
int err;
/* Check if busy */
err = regmap_read_poll_timeout(mixer->regmap,
TEGRA210_MIXER_GAIN_CFG_RAM_CTRL,
val, !(val & 0x80000000), 10, 10000);
if (err < 0)
return err;
reg = (addr << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT) &
TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_MASK;
reg |= TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN;
reg |= TEGRA210_MIXER_GAIN_CFG_RAM_RW_WRITE;
reg |= TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN;
regmap_write(mixer->regmap,
TEGRA210_MIXER_GAIN_CFG_RAM_CTRL,
reg);
regmap_write(mixer->regmap,
TEGRA210_MIXER_GAIN_CFG_RAM_DATA,
coef);
return 0;
}
static int tegra210_mixer_configure_gain(struct snd_soc_component *cmpnt,
unsigned int id, bool instant_gain)
{
struct tegra210_mixer *mixer = snd_soc_component_get_drvdata(cmpnt);
unsigned int reg = MIXER_GAIN_CFG_RAM_ADDR(id);
int err, i;
pm_runtime_get_sync(cmpnt->dev);
/* Write default gain poly coefficients */
for (i = 0; i < NUM_GAIN_POLY_COEFFS; i++) {
err = tegra210_mixer_write_ram(mixer, reg + i,
gain_params.poly_coeff[i]);
if (err < 0)
goto rpm_put;
}
/* Write stored gain value */
err = tegra210_mixer_write_ram(mixer, reg + NUM_GAIN_POLY_COEFFS,
mixer->gain_value[id]);
if (err < 0)
goto rpm_put;
/* Write duration parameters */
for (i = 0; i < NUM_DURATION_PARMS; i++) {
int val;
if (instant_gain)
val = 1;
else
val = gain_params.duration[i];
err = tegra210_mixer_write_ram(mixer,
REG_DURATION_PARAM(reg, i),
val);
if (err < 0)
goto rpm_put;
}
/* Trigger to apply gain configurations */
err = tegra210_mixer_write_ram(mixer, reg + REG_CFG_DONE_TRIGGER,
VAL_CFG_DONE_TRIGGER);
rpm_put:
pm_runtime_put(cmpnt->dev);
return err;
}
static int tegra210_mixer_get_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mixer *mixer = snd_soc_component_get_drvdata(cmpnt);
unsigned int reg = mc->reg;
unsigned int i;
i = (reg - TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0) /
TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE;
ucontrol->value.integer.value[0] = mixer->gain_value[i];
return 0;
}
static int tegra210_mixer_apply_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol,
bool instant_gain)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mixer *mixer = snd_soc_component_get_drvdata(cmpnt);
unsigned int reg = mc->reg, id;
int err;
/* Save gain value for specific MIXER input */
id = (reg - TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0) /
TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE;
if (mixer->gain_value[id] == ucontrol->value.integer.value[0])
return 0;
mixer->gain_value[id] = ucontrol->value.integer.value[0];
err = tegra210_mixer_configure_gain(cmpnt, id, instant_gain);
if (err) {
dev_err(cmpnt->dev, "Failed to apply gain\n");
return err;
}
return 1;
}
static int tegra210_mixer_put_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mixer_apply_gain(kcontrol, ucontrol, false);
}
static int tegra210_mixer_put_instant_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mixer_apply_gain(kcontrol, ucontrol, true);
}
static int tegra210_mixer_set_audio_cif(struct tegra210_mixer *mixer,
struct snd_pcm_hw_params *params,
unsigned int reg,
unsigned int id)
{
unsigned int channels, audio_bits;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = audio_bits;
tegra_set_cif(mixer->regmap,
reg + (id * TEGRA210_MIXER_REG_STRIDE),
&cif_conf);
return 0;
}
static int tegra210_mixer_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra210_mixer *mixer = snd_soc_dai_get_drvdata(dai);
int err;
err = tegra210_mixer_set_audio_cif(mixer, params,
TEGRA210_MIXER_RX1_CIF_CTRL,
dai->id);
if (err < 0)
return err;
return tegra210_mixer_configure_gain(dai->component, dai->id, false);
}
static int tegra210_mixer_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra210_mixer *mixer = snd_soc_dai_get_drvdata(dai);
return tegra210_mixer_set_audio_cif(mixer, params,
TEGRA210_MIXER_TX1_CIF_CTRL,
dai->id - TEGRA210_MIXER_RX_MAX);
}
static const struct snd_soc_dai_ops tegra210_mixer_out_dai_ops = {
.hw_params = tegra210_mixer_out_hw_params,
};
static const struct snd_soc_dai_ops tegra210_mixer_in_dai_ops = {
.hw_params = tegra210_mixer_in_hw_params,
};
#define IN_DAI(id) \
{ \
.name = "MIXER-RX-CIF"#id, \
.playback = { \
.stream_name = "RX" #id "-CIF-Playback",\
.channels_min = 1, \
.channels_max = 8, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "RX" #id "-CIF-Capture", \
.channels_min = 1, \
.channels_max = 8, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra210_mixer_in_dai_ops, \
}
#define OUT_DAI(id) \
{ \
.name = "MIXER-TX-CIF" #id, \
.playback = { \
.stream_name = "TX" #id "-CIF-Playback",\
.channels_min = 1, \
.channels_max = 8, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "TX" #id "-CIF-Capture", \
.channels_min = 1, \
.channels_max = 8, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra210_mixer_out_dai_ops, \
}
static struct snd_soc_dai_driver tegra210_mixer_dais[] = {
/* Mixer Input */
IN_DAI(1),
IN_DAI(2),
IN_DAI(3),
IN_DAI(4),
IN_DAI(5),
IN_DAI(6),
IN_DAI(7),
IN_DAI(8),
IN_DAI(9),
IN_DAI(10),
/* Mixer Output */
OUT_DAI(1),
OUT_DAI(2),
OUT_DAI(3),
OUT_DAI(4),
OUT_DAI(5),
};
#define ADDER_CTRL_DECL(name, reg) \
static const struct snd_kcontrol_new name[] = { \
SOC_DAPM_SINGLE("RX1", reg, 0, 1, 0), \
SOC_DAPM_SINGLE("RX2", reg, 1, 1, 0), \
SOC_DAPM_SINGLE("RX3", reg, 2, 1, 0), \
SOC_DAPM_SINGLE("RX4", reg, 3, 1, 0), \
SOC_DAPM_SINGLE("RX5", reg, 4, 1, 0), \
SOC_DAPM_SINGLE("RX6", reg, 5, 1, 0), \
SOC_DAPM_SINGLE("RX7", reg, 6, 1, 0), \
SOC_DAPM_SINGLE("RX8", reg, 7, 1, 0), \
SOC_DAPM_SINGLE("RX9", reg, 8, 1, 0), \
SOC_DAPM_SINGLE("RX10", reg, 9, 1, 0), \
}
ADDER_CTRL_DECL(adder1, TEGRA210_MIXER_TX1_ADDER_CONFIG);
ADDER_CTRL_DECL(adder2, TEGRA210_MIXER_TX2_ADDER_CONFIG);
ADDER_CTRL_DECL(adder3, TEGRA210_MIXER_TX3_ADDER_CONFIG);
ADDER_CTRL_DECL(adder4, TEGRA210_MIXER_TX4_ADDER_CONFIG);
ADDER_CTRL_DECL(adder5, TEGRA210_MIXER_TX5_ADDER_CONFIG);
#define GAIN_CTRL(id) \
SOC_SINGLE_EXT("RX" #id " Gain Volume", \
MIXER_GAIN_CFG_RAM_ADDR((id) - 1), 0, \
0x20000, 0, tegra210_mixer_get_gain, \
tegra210_mixer_put_gain), \
SOC_SINGLE_EXT("RX" #id " Instant Gain Volume", \
MIXER_GAIN_CFG_RAM_ADDR((id) - 1), 0, \
0x20000, 0, tegra210_mixer_get_gain, \
tegra210_mixer_put_instant_gain),
/* Volume controls for all MIXER inputs */
static const struct snd_kcontrol_new tegra210_mixer_gain_ctls[] = {
GAIN_CTRL(1)
GAIN_CTRL(2)
GAIN_CTRL(3)
GAIN_CTRL(4)
GAIN_CTRL(5)
GAIN_CTRL(6)
GAIN_CTRL(7)
GAIN_CTRL(8)
GAIN_CTRL(9)
GAIN_CTRL(10)
};
static const struct snd_soc_dapm_widget tegra210_mixer_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX7", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX8", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX9", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX10", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX1", NULL, 0, TEGRA210_MIXER_TX1_ENABLE, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX2", NULL, 0, TEGRA210_MIXER_TX2_ENABLE, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX3", NULL, 0, TEGRA210_MIXER_TX3_ENABLE, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX4", NULL, 0, TEGRA210_MIXER_TX4_ENABLE, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX5", NULL, 0, TEGRA210_MIXER_TX5_ENABLE, 0, 0),
SND_SOC_DAPM_MIXER("Adder1", SND_SOC_NOPM, 1, 0, adder1,
ARRAY_SIZE(adder1)),
SND_SOC_DAPM_MIXER("Adder2", SND_SOC_NOPM, 1, 0, adder2,
ARRAY_SIZE(adder2)),
SND_SOC_DAPM_MIXER("Adder3", SND_SOC_NOPM, 1, 0, adder3,
ARRAY_SIZE(adder3)),
SND_SOC_DAPM_MIXER("Adder4", SND_SOC_NOPM, 1, 0, adder4,
ARRAY_SIZE(adder4)),
SND_SOC_DAPM_MIXER("Adder5", SND_SOC_NOPM, 1, 0, adder5,
ARRAY_SIZE(adder5)),
};
#define RX_ROUTES(id, sname) \
{ "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
{ "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname }, \
{ "RX" #id, NULL, "RX" #id "-CIF-" sname }
#define MIXER_RX_ROUTES(id) \
RX_ROUTES(id, "Playback"), \
RX_ROUTES(id, "Capture")
#define ADDER_ROUTES(id, sname) \
{ "Adder" #id, "RX1", "RX1" }, \
{ "Adder" #id, "RX2", "RX2" }, \
{ "Adder" #id, "RX3", "RX3" }, \
{ "Adder" #id, "RX4", "RX4" }, \
{ "Adder" #id, "RX5", "RX5" }, \
{ "Adder" #id, "RX6", "RX6" }, \
{ "Adder" #id, "RX7", "RX7" }, \
{ "Adder" #id, "RX8", "RX8" }, \
{ "Adder" #id, "RX9", "RX9" }, \
{ "Adder" #id, "RX10", "RX10" }, \
{ "TX" #id, NULL, "Adder" #id }, \
{ "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
{ "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
{ "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname } \
#define TX_ROUTES(id, sname) \
ADDER_ROUTES(1, sname), \
ADDER_ROUTES(2, sname), \
ADDER_ROUTES(3, sname), \
ADDER_ROUTES(4, sname), \
ADDER_ROUTES(5, sname)
#define MIXER_TX_ROUTES(id) \
TX_ROUTES(id, "Playback"), \
TX_ROUTES(id, "Capture")
static const struct snd_soc_dapm_route tegra210_mixer_routes[] = {
/* Input */
MIXER_RX_ROUTES(1),
MIXER_RX_ROUTES(2),
MIXER_RX_ROUTES(3),
MIXER_RX_ROUTES(4),
MIXER_RX_ROUTES(5),
MIXER_RX_ROUTES(6),
MIXER_RX_ROUTES(7),
MIXER_RX_ROUTES(8),
MIXER_RX_ROUTES(9),
MIXER_RX_ROUTES(10),
/* Output */
MIXER_TX_ROUTES(1),
MIXER_TX_ROUTES(2),
MIXER_TX_ROUTES(3),
MIXER_TX_ROUTES(4),
MIXER_TX_ROUTES(5),
};
static const struct snd_soc_component_driver tegra210_mixer_cmpnt = {
.dapm_widgets = tegra210_mixer_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_mixer_widgets),
.dapm_routes = tegra210_mixer_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_mixer_routes),
.controls = tegra210_mixer_gain_ctls,
.num_controls = ARRAY_SIZE(tegra210_mixer_gain_ctls),
};
static bool tegra210_mixer_wr_reg(struct device *dev,
unsigned int reg)
{
if (reg < TEGRA210_MIXER_RX_LIMIT)
reg = MIXER_REG_BASE(reg);
else if (reg < TEGRA210_MIXER_TX_LIMIT)
reg = MIXER_REG_BASE(reg) + TEGRA210_MIXER_TX1_ENABLE;
switch (reg) {
case TEGRA210_MIXER_RX1_SOFT_RESET:
case TEGRA210_MIXER_RX1_CIF_CTRL ... TEGRA210_MIXER_RX1_PEAK_CTRL:
case TEGRA210_MIXER_TX1_ENABLE:
case TEGRA210_MIXER_TX1_SOFT_RESET:
case TEGRA210_MIXER_TX1_INT_MASK ... TEGRA210_MIXER_TX1_ADDER_CONFIG:
case TEGRA210_MIXER_ENABLE ... TEGRA210_MIXER_CG:
case TEGRA210_MIXER_GAIN_CFG_RAM_CTRL ... TEGRA210_MIXER_CTRL:
return true;
default:
return false;
}
}
static bool tegra210_mixer_rd_reg(struct device *dev,
unsigned int reg)
{
if (reg < TEGRA210_MIXER_RX_LIMIT)
reg = MIXER_REG_BASE(reg);
else if (reg < TEGRA210_MIXER_TX_LIMIT)
reg = MIXER_REG_BASE(reg) + TEGRA210_MIXER_TX1_ENABLE;
switch (reg) {
case TEGRA210_MIXER_RX1_SOFT_RESET ... TEGRA210_MIXER_RX1_SAMPLE_COUNT:
case TEGRA210_MIXER_TX1_ENABLE ... TEGRA210_MIXER_TX1_ADDER_CONFIG:
case TEGRA210_MIXER_ENABLE ... TEGRA210_MIXER_CTRL:
return true;
default:
return false;
}
}
static bool tegra210_mixer_volatile_reg(struct device *dev,
unsigned int reg)
{
if (reg < TEGRA210_MIXER_RX_LIMIT)
reg = MIXER_REG_BASE(reg);
else if (reg < TEGRA210_MIXER_TX_LIMIT)
reg = MIXER_REG_BASE(reg) + TEGRA210_MIXER_TX1_ENABLE;
switch (reg) {
case TEGRA210_MIXER_RX1_SOFT_RESET:
case TEGRA210_MIXER_RX1_STATUS:
case TEGRA210_MIXER_TX1_SOFT_RESET:
case TEGRA210_MIXER_TX1_STATUS:
case TEGRA210_MIXER_TX1_INT_STATUS:
case TEGRA210_MIXER_TX1_INT_SET:
case TEGRA210_MIXER_SOFT_RESET:
case TEGRA210_MIXER_STATUS:
case TEGRA210_MIXER_INT_STATUS:
case TEGRA210_MIXER_GAIN_CFG_RAM_CTRL:
case TEGRA210_MIXER_GAIN_CFG_RAM_DATA:
case TEGRA210_MIXER_PEAKM_RAM_CTRL:
case TEGRA210_MIXER_PEAKM_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_mixer_precious_reg(struct device *dev,
unsigned int reg)
{
switch (reg) {
case TEGRA210_MIXER_GAIN_CFG_RAM_DATA:
case TEGRA210_MIXER_PEAKM_RAM_DATA:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_mixer_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_MIXER_CTRL,
.writeable_reg = tegra210_mixer_wr_reg,
.readable_reg = tegra210_mixer_rd_reg,
.volatile_reg = tegra210_mixer_volatile_reg,
.precious_reg = tegra210_mixer_precious_reg,
.reg_defaults = tegra210_mixer_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_mixer_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra210_mixer_of_match[] = {
{ .compatible = "nvidia,tegra210-amixer" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_mixer_of_match);
static int tegra210_mixer_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_mixer *mixer;
void __iomem *regs;
int err, i;
mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
if (!mixer)
return -ENOMEM;
dev_set_drvdata(dev, mixer);
/* Use default gain value for all MIXER inputs */
for (i = 0; i < TEGRA210_MIXER_RX_MAX; i++)
mixer->gain_value[i] = gain_params.gain_value;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
mixer->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_mixer_regmap_config);
if (IS_ERR(mixer->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(mixer->regmap);
}
regcache_cache_only(mixer->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_mixer_cmpnt,
tegra210_mixer_dais,
ARRAY_SIZE(tegra210_mixer_dais));
if (err) {
dev_err(dev, "can't register MIXER component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra210_mixer_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_mixer_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_mixer_runtime_suspend,
tegra210_mixer_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra210_mixer_driver = {
.driver = {
.name = "tegra210_mixer",
.of_match_table = tegra210_mixer_of_match,
.pm = &tegra210_mixer_pm_ops,
},
.probe = tegra210_mixer_platform_probe,
.remove_new = tegra210_mixer_platform_remove,
};
module_platform_driver(tegra210_mixer_driver);
MODULE_AUTHOR("Arun Shamanna Lakshmi <[email protected]>");
MODULE_DESCRIPTION("Tegra210 MIXER ASoC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_mixer.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_i2s.c - Tegra210 I2S driver
//
// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_i2s.h"
#include "tegra_cif.h"
static const struct reg_default tegra210_i2s_reg_defaults[] = {
{ TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
{ TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
{ TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
{ TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
{ TEGRA210_I2S_CG, 0x1 },
{ TEGRA210_I2S_TIMING, 0x0000001f },
{ TEGRA210_I2S_ENABLE, 0x1 },
/*
* Below update does not have any effect on Tegra186 and Tegra194.
* On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
* is required to select i2s4b for it to be functional for I2S
* operation.
*/
{ TEGRA210_I2S_CYA, 0x1 },
};
static void tegra210_i2s_set_slot_ctrl(struct regmap *regmap,
unsigned int total_slots,
unsigned int tx_slot_mask,
unsigned int rx_slot_mask)
{
regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1);
regmap_write(regmap, TEGRA210_I2S_TX_SLOT_CTRL, tx_slot_mask);
regmap_write(regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask);
}
static int tegra210_i2s_set_clock_rate(struct device *dev,
unsigned int clock_rate)
{
struct tegra210_i2s *i2s = dev_get_drvdata(dev);
unsigned int val;
int err;
regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
/* No need to set rates if I2S is being operated in slave */
if (!(val & I2S_CTRL_MASTER_EN))
return 0;
err = clk_set_rate(i2s->clk_i2s, clock_rate);
if (err) {
dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
clock_rate, err);
return err;
}
if (!IS_ERR(i2s->clk_sync_input)) {
/*
* Other I/O modules in AHUB can use i2s bclk as reference
* clock. Below sets sync input clock rate as per bclk,
* which can be used as input to other I/O modules.
*/
err = clk_set_rate(i2s->clk_sync_input, clock_rate);
if (err) {
dev_err(dev,
"can't set I2S sync input rate %u, err = %d\n",
clock_rate, err);
return err;
}
}
return 0;
}
static int tegra210_i2s_sw_reset(struct snd_soc_component *compnt,
bool is_playback)
{
struct device *dev = compnt->dev;
struct tegra210_i2s *i2s = dev_get_drvdata(dev);
unsigned int reset_mask = I2S_SOFT_RESET_MASK;
unsigned int reset_en = I2S_SOFT_RESET_EN;
unsigned int reset_reg, cif_reg, stream_reg;
unsigned int cif_ctrl, stream_ctrl, i2s_ctrl, val;
int err;
if (is_playback) {
reset_reg = TEGRA210_I2S_RX_SOFT_RESET;
cif_reg = TEGRA210_I2S_RX_CIF_CTRL;
stream_reg = TEGRA210_I2S_RX_CTRL;
} else {
reset_reg = TEGRA210_I2S_TX_SOFT_RESET;
cif_reg = TEGRA210_I2S_TX_CIF_CTRL;
stream_reg = TEGRA210_I2S_TX_CTRL;
}
/* Store CIF and I2S control values */
regmap_read(i2s->regmap, cif_reg, &cif_ctrl);
regmap_read(i2s->regmap, stream_reg, &stream_ctrl);
regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl);
/* Reset to make sure the previous transactions are clean */
regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);
err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,
!(val & reset_mask & reset_en),
10, 10000);
if (err) {
dev_err(dev, "timeout: failed to reset I2S for %s\n",
is_playback ? "playback" : "capture");
return err;
}
/* Restore CIF and I2S control values */
regmap_write(i2s->regmap, cif_reg, cif_ctrl);
regmap_write(i2s->regmap, stream_reg, stream_ctrl);
regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl);
return 0;
}
static int tegra210_i2s_init(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm);
struct device *dev = compnt->dev;
struct tegra210_i2s *i2s = dev_get_drvdata(dev);
unsigned int val, status_reg;
bool is_playback;
int err;
switch (w->reg) {
case TEGRA210_I2S_RX_ENABLE:
is_playback = true;
status_reg = TEGRA210_I2S_RX_STATUS;
break;
case TEGRA210_I2S_TX_ENABLE:
is_playback = false;
status_reg = TEGRA210_I2S_TX_STATUS;
break;
default:
return -EINVAL;
}
/* Ensure I2S is in disabled state before new session */
err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,
!(val & I2S_EN_MASK & I2S_EN),
10, 10000);
if (err) {
dev_err(dev, "timeout: previous I2S %s is still active\n",
is_playback ? "playback" : "capture");
return err;
}
return tegra210_i2s_sw_reset(compnt, is_playback);
}
static int __maybe_unused tegra210_i2s_runtime_suspend(struct device *dev)
{
struct tegra210_i2s *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
regcache_mark_dirty(i2s->regmap);
clk_disable_unprepare(i2s->clk_i2s);
return 0;
}
static int __maybe_unused tegra210_i2s_runtime_resume(struct device *dev)
{
struct tegra210_i2s *i2s = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(i2s->clk_i2s);
if (err) {
dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err);
return err;
}
regcache_cache_only(i2s->regmap, false);
regcache_sync(i2s->regmap);
return 0;
}
static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
unsigned int data_offset)
{
/* Capture path */
regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL,
I2S_CTRL_DATA_OFFSET_MASK,
data_offset << I2S_DATA_SHIFT);
/* Playback path */
regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,
I2S_CTRL_DATA_OFFSET_MASK,
data_offset << I2S_DATA_SHIFT);
}
static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val;
mask = I2S_CTRL_MASTER_EN_MASK;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
val = 0;
break;
case SND_SOC_DAIFMT_BP_FP:
val = I2S_CTRL_MASTER_EN;
break;
default:
return -EINVAL;
}
mask |= I2S_CTRL_FRAME_FMT_MASK | I2S_CTRL_LRCK_POL_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
val |= I2S_CTRL_LRCK_POL_HIGH;
tegra210_i2s_set_data_offset(i2s, 1);
break;
case SND_SOC_DAIFMT_DSP_B:
val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
val |= I2S_CTRL_LRCK_POL_HIGH;
tegra210_i2s_set_data_offset(i2s, 0);
break;
/* I2S mode has data offset of 1 */
case SND_SOC_DAIFMT_I2S:
val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
val |= I2S_CTRL_LRCK_POL_LOW;
tegra210_i2s_set_data_offset(i2s, 1);
break;
/*
* For RJ mode data offset is dependent on the sample size
* and the bclk ratio, and so is set when hw_params is called.
*/
case SND_SOC_DAIFMT_RIGHT_J:
val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
val |= I2S_CTRL_LRCK_POL_HIGH;
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
val |= I2S_CTRL_LRCK_POL_HIGH;
tegra210_i2s_set_data_offset(i2s, 0);
break;
default:
return -EINVAL;
}
mask |= I2S_CTRL_EDGE_CTRL_MASK;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
break;
case SND_SOC_DAIFMT_NB_IF:
val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
val ^= I2S_CTRL_LRCK_POL_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
break;
case SND_SOC_DAIFMT_IB_IF:
val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
val ^= I2S_CTRL_LRCK_POL_MASK;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
return 0;
}
static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
/* Copy the required tx and rx mask */
i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ?
DEFAULT_I2S_SLOT_MASK : tx_mask;
i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ?
DEFAULT_I2S_SLOT_MASK : rx_mask;
return 0;
}
static int tegra210_i2s_get_loopback(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.integer.value[0] = i2s->loopback;
return 0;
}
static int tegra210_i2s_put_loopback(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
int value = ucontrol->value.integer.value[0];
if (value == i2s->loopback)
return 0;
i2s->loopback = value;
regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, I2S_CTRL_LPBK_MASK,
i2s->loopback << I2S_CTRL_LPBK_SHIFT);
return 1;
}
static int tegra210_i2s_get_fsync_width(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.integer.value[0] = i2s->fsync_width;
return 0;
}
static int tegra210_i2s_put_fsync_width(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
int value = ucontrol->value.integer.value[0];
if (value == i2s->fsync_width)
return 0;
i2s->fsync_width = value;
/*
* Frame sync width is used only for FSYNC modes and not
* applicable for LRCK modes. Reset value for this field is "0",
* which means the width is one bit clock wide.
* The width requirement may depend on the codec and in such
* cases mixer control is used to update custom values. A value
* of "N" here means, width is "N + 1" bit clock wide.
*/
regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
I2S_CTRL_FSYNC_WIDTH_MASK,
i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT);
return 1;
}
static int tegra210_i2s_cget_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH];
return 0;
}
static int tegra210_i2s_cput_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == i2s->stereo_to_mono[I2S_TX_PATH])
return 0;
i2s->stereo_to_mono[I2S_TX_PATH] = value;
return 1;
}
static int tegra210_i2s_cget_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH];
return 0;
}
static int tegra210_i2s_cput_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == i2s->mono_to_stereo[I2S_TX_PATH])
return 0;
i2s->mono_to_stereo[I2S_TX_PATH] = value;
return 1;
}
static int tegra210_i2s_pget_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH];
return 0;
}
static int tegra210_i2s_pput_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == i2s->stereo_to_mono[I2S_RX_PATH])
return 0;
i2s->stereo_to_mono[I2S_RX_PATH] = value;
return 1;
}
static int tegra210_i2s_pget_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH];
return 0;
}
static int tegra210_i2s_pput_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == i2s->mono_to_stereo[I2S_RX_PATH])
return 0;
i2s->mono_to_stereo[I2S_RX_PATH] = value;
return 1;
}
static int tegra210_i2s_pget_fifo_th(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.integer.value[0] = i2s->rx_fifo_th;
return 0;
}
static int tegra210_i2s_pput_fifo_th(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
int value = ucontrol->value.integer.value[0];
if (value == i2s->rx_fifo_th)
return 0;
i2s->rx_fifo_th = value;
return 1;
}
static int tegra210_i2s_get_bclk_ratio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
ucontrol->value.integer.value[0] = i2s->bclk_ratio;
return 0;
}
static int tegra210_i2s_put_bclk_ratio(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
int value = ucontrol->value.integer.value[0];
if (value == i2s->bclk_ratio)
return 0;
i2s->bclk_ratio = value;
return 1;
}
static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
i2s->bclk_ratio = ratio;
return 0;
}
static int tegra210_i2s_set_timing_params(struct device *dev,
unsigned int sample_size,
unsigned int srate,
unsigned int channels)
{
struct tegra210_i2s *i2s = dev_get_drvdata(dev);
unsigned int val, bit_count, bclk_rate, num_bclk = sample_size;
int err;
if (i2s->bclk_ratio)
num_bclk *= i2s->bclk_ratio;
if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)
tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);
/* I2S bit clock rate */
bclk_rate = srate * channels * num_bclk;
err = tegra210_i2s_set_clock_rate(dev, bclk_rate);
if (err) {
dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
bclk_rate, err);
return err;
}
regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
/*
* For LRCK mode, channel bit count depends on number of bit clocks
* on the left channel, where as for FSYNC mode bit count depends on
* the number of bit clocks in both left and right channels for DSP
* mode or the number of bit clocks in one TDM frame.
*
*/
switch (val & I2S_CTRL_FRAME_FMT_MASK) {
case I2S_CTRL_FRAME_FMT_LRCK_MODE:
bit_count = (bclk_rate / (srate * 2)) - 1;
break;
case I2S_CTRL_FRAME_FMT_FSYNC_MODE:
bit_count = (bclk_rate / srate) - 1;
tegra210_i2s_set_slot_ctrl(i2s->regmap, channels,
i2s->tx_mask, i2s->rx_mask);
break;
default:
dev_err(dev, "invalid I2S frame format\n");
return -EINVAL;
}
if (bit_count > I2S_TIMING_CH_BIT_CNT_MASK) {
dev_err(dev, "invalid I2S channel bit count %u\n", bit_count);
return -EINVAL;
}
regmap_write(i2s->regmap, TEGRA210_I2S_TIMING,
bit_count << I2S_TIMING_CH_BIT_CNT_SHIFT);
return 0;
}
static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int sample_size, channels, srate, val, reg, path;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
if (channels < 1) {
dev_err(dev, "invalid I2S %d channel configuration\n",
channels);
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
val = I2S_BITS_8;
sample_size = 8;
cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
cif_conf.client_bits = TEGRA_ACIF_BITS_8;
break;
case SNDRV_PCM_FORMAT_S16_LE:
val = I2S_BITS_16;
sample_size = 16;
cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
cif_conf.client_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
val = I2S_BITS_32;
sample_size = 32;
cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
cif_conf.client_bits = TEGRA_ACIF_BITS_32;
break;
default:
dev_err(dev, "unsupported format!\n");
return -EOPNOTSUPP;
}
/* Program sample size */
regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
I2S_CTRL_BIT_SIZE_MASK, val);
srate = params_rate(params);
/* For playback I2S RX-CIF and for capture TX-CIF is used */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
path = I2S_RX_PATH;
else
path = I2S_TX_PATH;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
unsigned int max_th;
/* FIFO threshold in terms of frames */
max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
if (i2s->rx_fifo_th > max_th)
i2s->rx_fifo_th = max_th;
cif_conf.threshold = i2s->rx_fifo_th;
reg = TEGRA210_I2S_RX_CIF_CTRL;
} else {
reg = TEGRA210_I2S_TX_CIF_CTRL;
}
cif_conf.mono_conv = i2s->mono_to_stereo[path];
cif_conf.stereo_conv = i2s->stereo_to_mono[path];
tegra_set_cif(i2s->regmap, reg, &cif_conf);
return tegra210_i2s_set_timing_params(dev, sample_size, srate,
cif_conf.client_ch);
}
static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = {
.set_fmt = tegra210_i2s_set_fmt,
.hw_params = tegra210_i2s_hw_params,
.set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio,
.set_tdm_slot = tegra210_i2s_set_tdm_slot,
};
static struct snd_soc_dai_driver tegra210_i2s_dais[] = {
{
.name = "I2S-CIF",
.playback = {
.stream_name = "CIF-Playback",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "CIF-Capture",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
{
.name = "I2S-DAP",
.playback = {
.stream_name = "DAP-Playback",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "DAP-Capture",
.channels_min = 1,
.channels_max = 16,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra210_i2s_dai_ops,
.symmetric_rate = 1,
},
};
static const char * const tegra210_i2s_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const char * const tegra210_i2s_mono_conv_text[] = {
"Zero", "Copy",
};
static const struct soc_enum tegra210_i2s_mono_conv_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_mono_conv_text),
tegra210_i2s_mono_conv_text);
static const struct soc_enum tegra210_i2s_stereo_conv_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_stereo_conv_text),
tegra210_i2s_stereo_conv_text);
static const struct snd_kcontrol_new tegra210_i2s_controls[] = {
SOC_SINGLE_EXT("Loopback", 0, 0, 1, 0, tegra210_i2s_get_loopback,
tegra210_i2s_put_loopback),
SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0,
tegra210_i2s_get_fsync_width,
tegra210_i2s_put_fsync_width),
SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum,
tegra210_i2s_cget_stereo_to_mono,
tegra210_i2s_cput_stereo_to_mono),
SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum,
tegra210_i2s_cget_mono_to_stereo,
tegra210_i2s_cput_mono_to_stereo),
SOC_ENUM_EXT("Playback Stereo To Mono", tegra210_i2s_stereo_conv_enum,
tegra210_i2s_pget_mono_to_stereo,
tegra210_i2s_pput_mono_to_stereo),
SOC_ENUM_EXT("Playback Mono To Stereo", tegra210_i2s_mono_conv_enum,
tegra210_i2s_pget_stereo_to_mono,
tegra210_i2s_pput_stereo_to_mono),
SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
0, tegra210_i2s_pget_fifo_th, tegra210_i2s_pput_fifo_th),
SOC_SINGLE_EXT("BCLK Ratio", 0, 0, INT_MAX, 0,
tegra210_i2s_get_bclk_ratio,
tegra210_i2s_put_bclk_ratio),
};
static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = {
SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE,
0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_I2S_TX_ENABLE,
0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MIC("MIC", NULL),
SND_SOC_DAPM_SPK("SPK", NULL),
};
static const struct snd_soc_dapm_route tegra210_i2s_routes[] = {
/* Playback route from XBAR */
{ "XBAR-Playback", NULL, "XBAR-TX" },
{ "CIF-Playback", NULL, "XBAR-Playback" },
{ "RX", NULL, "CIF-Playback" },
{ "DAP-Playback", NULL, "RX" },
{ "SPK", NULL, "DAP-Playback" },
/* Capture route to XBAR */
{ "XBAR-RX", NULL, "XBAR-Capture" },
{ "XBAR-Capture", NULL, "CIF-Capture" },
{ "CIF-Capture", NULL, "TX" },
{ "TX", NULL, "DAP-Capture" },
{ "DAP-Capture", NULL, "MIC" },
};
static const struct snd_soc_component_driver tegra210_i2s_cmpnt = {
.dapm_widgets = tegra210_i2s_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_i2s_widgets),
.dapm_routes = tegra210_i2s_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes),
.controls = tegra210_i2s_controls,
.num_controls = ARRAY_SIZE(tegra210_i2s_controls),
};
static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET:
case TEGRA210_I2S_RX_INT_MASK ... TEGRA210_I2S_RX_CLK_TRIM:
case TEGRA210_I2S_TX_ENABLE ... TEGRA210_I2S_TX_SOFT_RESET:
case TEGRA210_I2S_TX_INT_MASK ... TEGRA210_I2S_TX_CLK_TRIM:
case TEGRA210_I2S_ENABLE ... TEGRA210_I2S_CG:
case TEGRA210_I2S_CTRL ... TEGRA210_I2S_CYA:
return true;
default:
return false;
}
}
static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg)
{
if (tegra210_i2s_wr_reg(dev, reg))
return true;
switch (reg) {
case TEGRA210_I2S_RX_STATUS:
case TEGRA210_I2S_RX_INT_STATUS:
case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
case TEGRA210_I2S_TX_STATUS:
case TEGRA210_I2S_TX_INT_STATUS:
case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
case TEGRA210_I2S_STATUS:
case TEGRA210_I2S_INT_STATUS:
return true;
default:
return false;
}
}
static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_I2S_RX_STATUS:
case TEGRA210_I2S_RX_INT_STATUS:
case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
case TEGRA210_I2S_TX_STATUS:
case TEGRA210_I2S_TX_INT_STATUS:
case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
case TEGRA210_I2S_STATUS:
case TEGRA210_I2S_INT_STATUS:
case TEGRA210_I2S_RX_SOFT_RESET:
case TEGRA210_I2S_TX_SOFT_RESET:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_I2S_CYA,
.writeable_reg = tegra210_i2s_wr_reg,
.readable_reg = tegra210_i2s_rd_reg,
.volatile_reg = tegra210_i2s_volatile_reg,
.reg_defaults = tegra210_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int tegra210_i2s_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_i2s *i2s;
void __iomem *regs;
int err;
i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;
i2s->tx_mask = DEFAULT_I2S_SLOT_MASK;
i2s->rx_mask = DEFAULT_I2S_SLOT_MASK;
i2s->loopback = false;
dev_set_drvdata(dev, i2s);
i2s->clk_i2s = devm_clk_get(dev, "i2s");
if (IS_ERR(i2s->clk_i2s)) {
dev_err(dev, "can't retrieve I2S bit clock\n");
return PTR_ERR(i2s->clk_i2s);
}
/*
* Not an error, as this clock is needed only when some other I/O
* requires input clock from current I2S instance, which is
* configurable from DT.
*/
i2s->clk_sync_input = devm_clk_get(dev, "sync_input");
if (IS_ERR(i2s->clk_sync_input))
dev_dbg(dev, "can't retrieve I2S sync input clock\n");
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
i2s->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(i2s->regmap);
}
regcache_cache_only(i2s->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_i2s_cmpnt,
tegra210_i2s_dais,
ARRAY_SIZE(tegra210_i2s_dais));
if (err) {
dev_err(dev, "can't register I2S component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra210_i2s_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_i2s_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend,
tegra210_i2s_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct of_device_id tegra210_i2s_of_match[] = {
{ .compatible = "nvidia,tegra210-i2s" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match);
static struct platform_driver tegra210_i2s_driver = {
.driver = {
.name = "tegra210-i2s",
.of_match_table = tegra210_i2s_of_match,
.pm = &tegra210_i2s_pm_ops,
},
.probe = tegra210_i2s_probe,
.remove_new = tegra210_i2s_remove,
};
module_platform_driver(tegra210_i2s_driver)
MODULE_AUTHOR("Songhee Baek <[email protected]>");
MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_adx.c - Tegra210 ADX driver
//
// Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_adx.h"
#include "tegra_cif.h"
static const struct reg_default tegra210_adx_reg_defaults[] = {
{ TEGRA210_ADX_RX_INT_MASK, 0x00000001},
{ TEGRA210_ADX_RX_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_TX_INT_MASK, 0x0000000f },
{ TEGRA210_ADX_TX1_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_TX2_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_TX3_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_TX4_CIF_CTRL, 0x00007000},
{ TEGRA210_ADX_CG, 0x1},
{ TEGRA210_ADX_CFG_RAM_CTRL, 0x00004000},
};
static void tegra210_adx_write_map_ram(struct tegra210_adx *adx)
{
int i;
regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL,
TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN |
TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE);
for (i = 0; i < TEGRA210_ADX_RAM_DEPTH; i++)
regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA,
adx->map[i]);
regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN0, adx->byte_mask[0]);
regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN1, adx->byte_mask[1]);
}
static int tegra210_adx_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
unsigned int val;
int err;
/* Ensure if ADX status is disabled */
err = regmap_read_poll_timeout_atomic(adx->regmap, TEGRA210_ADX_STATUS,
val, !(val & 0x1), 10, 10000);
if (err < 0) {
dev_err(dai->dev, "failed to stop ADX, err = %d\n", err);
return err;
}
/*
* Soft Reset: Below performs module soft reset which clears
* all FSM logic, flushes flow control of FIFO and resets the
* state register. It also brings module back to disabled
* state (without flushing the data in the pipe).
*/
regmap_update_bits(adx->regmap, TEGRA210_ADX_SOFT_RESET,
TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK,
TEGRA210_ADX_SOFT_RESET_SOFT_EN);
err = regmap_read_poll_timeout(adx->regmap, TEGRA210_ADX_SOFT_RESET,
val, !(val & 0x1), 10, 10000);
if (err < 0) {
dev_err(dai->dev, "failed to reset ADX, err = %d\n", err);
return err;
}
return 0;
}
static int __maybe_unused tegra210_adx_runtime_suspend(struct device *dev)
{
struct tegra210_adx *adx = dev_get_drvdata(dev);
regcache_cache_only(adx->regmap, true);
regcache_mark_dirty(adx->regmap);
return 0;
}
static int __maybe_unused tegra210_adx_runtime_resume(struct device *dev)
{
struct tegra210_adx *adx = dev_get_drvdata(dev);
regcache_cache_only(adx->regmap, false);
regcache_sync(adx->regmap);
tegra210_adx_write_map_ram(adx);
return 0;
}
static int tegra210_adx_set_audio_cif(struct snd_soc_dai *dai,
unsigned int channels,
snd_pcm_format_t format,
unsigned int reg)
{
struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
struct tegra_cif_conf cif_conf;
int audio_bits;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
if (channels < 1 || channels > 16)
return -EINVAL;
switch (format) {
case SNDRV_PCM_FORMAT_S8:
audio_bits = TEGRA_ACIF_BITS_8;
break;
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = audio_bits;
tegra_set_cif(adx->regmap, reg, &cif_conf);
return 0;
}
static int tegra210_adx_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
return tegra210_adx_set_audio_cif(dai, params_channels(params),
params_format(params),
TEGRA210_ADX_TX1_CIF_CTRL + ((dai->id - 1) * TEGRA210_ADX_AUDIOCIF_CH_STRIDE));
}
static int tegra210_adx_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
return tegra210_adx_set_audio_cif(dai, params_channels(params),
params_format(params),
TEGRA210_ADX_RX_CIF_CTRL);
}
static int tegra210_adx_get_byte_map(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_adx *adx = snd_soc_component_get_drvdata(cmpnt);
struct soc_mixer_control *mc;
unsigned char *bytes_map = (unsigned char *)&adx->map;
int enabled;
mc = (struct soc_mixer_control *)kcontrol->private_value;
enabled = adx->byte_mask[mc->reg / 32] & (1 << (mc->reg % 32));
/*
* TODO: Simplify this logic to just return from bytes_map[]
*
* Presently below is required since bytes_map[] is
* tightly packed and cannot store the control value of 256.
* Byte mask state is used to know if 256 needs to be returned.
* Note that for control value of 256, the put() call stores 0
* in the bytes_map[] and disables the corresponding bit in
* byte_mask[].
*/
if (enabled)
ucontrol->value.integer.value[0] = bytes_map[mc->reg];
else
ucontrol->value.integer.value[0] = 256;
return 0;
}
static int tegra210_adx_put_byte_map(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_adx *adx = snd_soc_component_get_drvdata(cmpnt);
unsigned char *bytes_map = (unsigned char *)&adx->map;
int value = ucontrol->value.integer.value[0];
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int mask_val = adx->byte_mask[mc->reg / 32];
if (value >= 0 && value <= 255)
mask_val |= (1 << (mc->reg % 32));
else
mask_val &= ~(1 << (mc->reg % 32));
if (mask_val == adx->byte_mask[mc->reg / 32])
return 0;
/* Update byte map and slot */
bytes_map[mc->reg] = value % 256;
adx->byte_mask[mc->reg / 32] = mask_val;
return 1;
}
static const struct snd_soc_dai_ops tegra210_adx_in_dai_ops = {
.hw_params = tegra210_adx_in_hw_params,
.startup = tegra210_adx_startup,
};
static const struct snd_soc_dai_ops tegra210_adx_out_dai_ops = {
.hw_params = tegra210_adx_out_hw_params,
};
#define IN_DAI \
{ \
.name = "ADX-RX-CIF", \
.playback = { \
.stream_name = "RX-CIF-Playback", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "RX-CIF-Capture", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra210_adx_in_dai_ops, \
}
#define OUT_DAI(id) \
{ \
.name = "ADX-TX" #id "-CIF", \
.playback = { \
.stream_name = "TX" #id "-CIF-Playback",\
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "TX" #id "-CIF-Capture", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra210_adx_out_dai_ops, \
}
static struct snd_soc_dai_driver tegra210_adx_dais[] = {
IN_DAI,
OUT_DAI(1),
OUT_DAI(2),
OUT_DAI(3),
OUT_DAI(4),
};
static const struct snd_soc_dapm_widget tegra210_adx_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX", NULL, 0, TEGRA210_ADX_ENABLE,
TEGRA210_ADX_ENABLE_SHIFT, 0),
SND_SOC_DAPM_AIF_OUT("TX1", NULL, 0, TEGRA210_ADX_CTRL, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX2", NULL, 0, TEGRA210_ADX_CTRL, 1, 0),
SND_SOC_DAPM_AIF_OUT("TX3", NULL, 0, TEGRA210_ADX_CTRL, 2, 0),
SND_SOC_DAPM_AIF_OUT("TX4", NULL, 0, TEGRA210_ADX_CTRL, 3, 0),
};
#define STREAM_ROUTES(id, sname) \
{ "XBAR-" sname, NULL, "XBAR-TX" }, \
{ "RX-CIF-" sname, NULL, "XBAR-" sname }, \
{ "RX", NULL, "RX-CIF-" sname }, \
{ "TX" #id, NULL, "RX" }, \
{ "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
{ "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
{ "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname }
#define ADX_ROUTES(id) \
STREAM_ROUTES(id, "Playback"), \
STREAM_ROUTES(id, "Capture")
#define STREAM_ROUTES(id, sname) \
{ "XBAR-" sname, NULL, "XBAR-TX" }, \
{ "RX-CIF-" sname, NULL, "XBAR-" sname }, \
{ "RX", NULL, "RX-CIF-" sname }, \
{ "TX" #id, NULL, "RX" }, \
{ "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
{ "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
{ "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname }
#define ADX_ROUTES(id) \
STREAM_ROUTES(id, "Playback"), \
STREAM_ROUTES(id, "Capture")
static const struct snd_soc_dapm_route tegra210_adx_routes[] = {
ADX_ROUTES(1),
ADX_ROUTES(2),
ADX_ROUTES(3),
ADX_ROUTES(4),
};
#define TEGRA210_ADX_BYTE_MAP_CTRL(reg) \
SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \
tegra210_adx_get_byte_map, \
tegra210_adx_put_byte_map)
static struct snd_kcontrol_new tegra210_adx_controls[] = {
TEGRA210_ADX_BYTE_MAP_CTRL(0),
TEGRA210_ADX_BYTE_MAP_CTRL(1),
TEGRA210_ADX_BYTE_MAP_CTRL(2),
TEGRA210_ADX_BYTE_MAP_CTRL(3),
TEGRA210_ADX_BYTE_MAP_CTRL(4),
TEGRA210_ADX_BYTE_MAP_CTRL(5),
TEGRA210_ADX_BYTE_MAP_CTRL(6),
TEGRA210_ADX_BYTE_MAP_CTRL(7),
TEGRA210_ADX_BYTE_MAP_CTRL(8),
TEGRA210_ADX_BYTE_MAP_CTRL(9),
TEGRA210_ADX_BYTE_MAP_CTRL(10),
TEGRA210_ADX_BYTE_MAP_CTRL(11),
TEGRA210_ADX_BYTE_MAP_CTRL(12),
TEGRA210_ADX_BYTE_MAP_CTRL(13),
TEGRA210_ADX_BYTE_MAP_CTRL(14),
TEGRA210_ADX_BYTE_MAP_CTRL(15),
TEGRA210_ADX_BYTE_MAP_CTRL(16),
TEGRA210_ADX_BYTE_MAP_CTRL(17),
TEGRA210_ADX_BYTE_MAP_CTRL(18),
TEGRA210_ADX_BYTE_MAP_CTRL(19),
TEGRA210_ADX_BYTE_MAP_CTRL(20),
TEGRA210_ADX_BYTE_MAP_CTRL(21),
TEGRA210_ADX_BYTE_MAP_CTRL(22),
TEGRA210_ADX_BYTE_MAP_CTRL(23),
TEGRA210_ADX_BYTE_MAP_CTRL(24),
TEGRA210_ADX_BYTE_MAP_CTRL(25),
TEGRA210_ADX_BYTE_MAP_CTRL(26),
TEGRA210_ADX_BYTE_MAP_CTRL(27),
TEGRA210_ADX_BYTE_MAP_CTRL(28),
TEGRA210_ADX_BYTE_MAP_CTRL(29),
TEGRA210_ADX_BYTE_MAP_CTRL(30),
TEGRA210_ADX_BYTE_MAP_CTRL(31),
TEGRA210_ADX_BYTE_MAP_CTRL(32),
TEGRA210_ADX_BYTE_MAP_CTRL(33),
TEGRA210_ADX_BYTE_MAP_CTRL(34),
TEGRA210_ADX_BYTE_MAP_CTRL(35),
TEGRA210_ADX_BYTE_MAP_CTRL(36),
TEGRA210_ADX_BYTE_MAP_CTRL(37),
TEGRA210_ADX_BYTE_MAP_CTRL(38),
TEGRA210_ADX_BYTE_MAP_CTRL(39),
TEGRA210_ADX_BYTE_MAP_CTRL(40),
TEGRA210_ADX_BYTE_MAP_CTRL(41),
TEGRA210_ADX_BYTE_MAP_CTRL(42),
TEGRA210_ADX_BYTE_MAP_CTRL(43),
TEGRA210_ADX_BYTE_MAP_CTRL(44),
TEGRA210_ADX_BYTE_MAP_CTRL(45),
TEGRA210_ADX_BYTE_MAP_CTRL(46),
TEGRA210_ADX_BYTE_MAP_CTRL(47),
TEGRA210_ADX_BYTE_MAP_CTRL(48),
TEGRA210_ADX_BYTE_MAP_CTRL(49),
TEGRA210_ADX_BYTE_MAP_CTRL(50),
TEGRA210_ADX_BYTE_MAP_CTRL(51),
TEGRA210_ADX_BYTE_MAP_CTRL(52),
TEGRA210_ADX_BYTE_MAP_CTRL(53),
TEGRA210_ADX_BYTE_MAP_CTRL(54),
TEGRA210_ADX_BYTE_MAP_CTRL(55),
TEGRA210_ADX_BYTE_MAP_CTRL(56),
TEGRA210_ADX_BYTE_MAP_CTRL(57),
TEGRA210_ADX_BYTE_MAP_CTRL(58),
TEGRA210_ADX_BYTE_MAP_CTRL(59),
TEGRA210_ADX_BYTE_MAP_CTRL(60),
TEGRA210_ADX_BYTE_MAP_CTRL(61),
TEGRA210_ADX_BYTE_MAP_CTRL(62),
TEGRA210_ADX_BYTE_MAP_CTRL(63),
};
static const struct snd_soc_component_driver tegra210_adx_cmpnt = {
.dapm_widgets = tegra210_adx_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_adx_widgets),
.dapm_routes = tegra210_adx_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_adx_routes),
.controls = tegra210_adx_controls,
.num_controls = ARRAY_SIZE(tegra210_adx_controls),
};
static bool tegra210_adx_wr_reg(struct device *dev,
unsigned int reg)
{
switch (reg) {
case TEGRA210_ADX_TX_INT_MASK ... TEGRA210_ADX_TX4_CIF_CTRL:
case TEGRA210_ADX_RX_INT_MASK ... TEGRA210_ADX_RX_CIF_CTRL:
case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_CG:
case TEGRA210_ADX_CTRL ... TEGRA210_ADX_IN_BYTE_EN1:
case TEGRA210_ADX_CFG_RAM_CTRL ... TEGRA210_ADX_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_adx_rd_reg(struct device *dev,
unsigned int reg)
{
switch (reg) {
case TEGRA210_ADX_RX_STATUS ... TEGRA210_ADX_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_adx_volatile_reg(struct device *dev,
unsigned int reg)
{
switch (reg) {
case TEGRA210_ADX_RX_STATUS:
case TEGRA210_ADX_RX_INT_STATUS:
case TEGRA210_ADX_RX_INT_SET:
case TEGRA210_ADX_TX_STATUS:
case TEGRA210_ADX_TX_INT_STATUS:
case TEGRA210_ADX_TX_INT_SET:
case TEGRA210_ADX_SOFT_RESET:
case TEGRA210_ADX_STATUS:
case TEGRA210_ADX_INT_STATUS:
case TEGRA210_ADX_CFG_RAM_CTRL:
case TEGRA210_ADX_CFG_RAM_DATA:
return true;
default:
break;
}
return false;
}
static const struct regmap_config tegra210_adx_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_ADX_CFG_RAM_DATA,
.writeable_reg = tegra210_adx_wr_reg,
.readable_reg = tegra210_adx_rd_reg,
.volatile_reg = tegra210_adx_volatile_reg,
.reg_defaults = tegra210_adx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_adx_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra210_adx_of_match[] = {
{ .compatible = "nvidia,tegra210-adx" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_adx_of_match);
static int tegra210_adx_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_adx *adx;
void __iomem *regs;
int err;
adx = devm_kzalloc(dev, sizeof(*adx), GFP_KERNEL);
if (!adx)
return -ENOMEM;
dev_set_drvdata(dev, adx);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
adx->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_adx_regmap_config);
if (IS_ERR(adx->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(adx->regmap);
}
regcache_cache_only(adx->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_adx_cmpnt,
tegra210_adx_dais,
ARRAY_SIZE(tegra210_adx_dais));
if (err) {
dev_err(dev, "can't register ADX component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra210_adx_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_adx_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_adx_runtime_suspend,
tegra210_adx_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra210_adx_driver = {
.driver = {
.name = "tegra210-adx",
.of_match_table = tegra210_adx_of_match,
.pm = &tegra210_adx_pm_ops,
},
.probe = tegra210_adx_platform_probe,
.remove_new = tegra210_adx_platform_remove,
};
module_platform_driver(tegra210_adx_driver);
MODULE_AUTHOR("Arun Shamanna Lakshmi <[email protected]>");
MODULE_DESCRIPTION("Tegra210 ADX ASoC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_adx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra30_ahub.c - Tegra30 AHUB driver
*
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include "tegra30_ahub.h"
#define DRV_NAME "tegra30-ahub"
static struct tegra30_ahub *ahub;
static inline void tegra30_apbif_write(u32 reg, u32 val)
{
regmap_write(ahub->regmap_apbif, reg, val);
}
static inline u32 tegra30_apbif_read(u32 reg)
{
u32 val;
regmap_read(ahub->regmap_apbif, reg, &val);
return val;
}
static inline void tegra30_audio_write(u32 reg, u32 val)
{
regmap_write(ahub->regmap_ahub, reg, val);
}
static __maybe_unused int tegra30_ahub_runtime_suspend(struct device *dev)
{
regcache_cache_only(ahub->regmap_apbif, true);
regcache_cache_only(ahub->regmap_ahub, true);
clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks);
return 0;
}
/*
* clk_apbif isn't required for an I2S<->I2S configuration where no PCM data
* is read from or sent to memory. However, that's not something the rest of
* the driver supports right now, so we'll just treat the two clocks as one
* for now.
*
* These functions should not be a plain ref-count. Instead, each active stream
* contributes some requirement to the minimum clock rate, so starting or
* stopping streams should dynamically adjust the clock as required. However,
* this is not yet implemented.
*/
static __maybe_unused int tegra30_ahub_runtime_resume(struct device *dev)
{
int ret;
ret = reset_control_bulk_assert(ahub->nresets, ahub->resets);
if (ret)
return ret;
ret = clk_bulk_prepare_enable(ahub->nclocks, ahub->clocks);
if (ret)
return ret;
usleep_range(10, 100);
ret = reset_control_bulk_deassert(ahub->nresets, ahub->resets);
if (ret)
goto disable_clocks;
regcache_cache_only(ahub->regmap_apbif, false);
regcache_cache_only(ahub->regmap_ahub, false);
regcache_mark_dirty(ahub->regmap_apbif);
regcache_mark_dirty(ahub->regmap_ahub);
ret = regcache_sync(ahub->regmap_apbif);
if (ret)
goto disable_clocks;
ret = regcache_sync(ahub->regmap_ahub);
if (ret)
goto disable_clocks;
return 0;
disable_clocks:
clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks);
return ret;
}
int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
char *dmachan, int dmachan_len,
dma_addr_t *fiforeg)
{
int channel;
u32 reg, val;
struct tegra30_ahub_cif_conf cif_conf;
channel = find_first_zero_bit(ahub->rx_usage,
TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
return -EBUSY;
__set_bit(channel, ahub->rx_usage);
*rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
snprintf(dmachan, dmachan_len, "rx%d", channel);
*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
(channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg);
val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK |
TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK);
val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) |
TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN |
TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16;
tegra30_apbif_write(reg, val);
cif_conf.threshold = 0;
cif_conf.audio_channels = 2;
cif_conf.client_channels = 2;
cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
cif_conf.expand = 0;
cif_conf.stereo_conv = 0;
cif_conf.replicate = 0;
cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
cif_conf.truncate = 0;
cif_conf.mono_conv = 0;
reg = TEGRA30_AHUB_CIF_RX_CTRL +
(channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
{
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg);
val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
{
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg);
val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
{
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
__clear_bit(channel, ahub->rx_usage);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
char *dmachan, int dmachan_len,
dma_addr_t *fiforeg)
{
int channel;
u32 reg, val;
struct tegra30_ahub_cif_conf cif_conf;
channel = find_first_zero_bit(ahub->tx_usage,
TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
return -EBUSY;
__set_bit(channel, ahub->tx_usage);
*txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
snprintf(dmachan, dmachan_len, "tx%d", channel);
*fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
(channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg);
val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK |
TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK);
val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) |
TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN |
TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16;
tegra30_apbif_write(reg, val);
cif_conf.threshold = 0;
cif_conf.audio_channels = 2;
cif_conf.client_channels = 2;
cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
cif_conf.expand = 0;
cif_conf.stereo_conv = 0;
cif_conf.replicate = 0;
cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
cif_conf.truncate = 0;
cif_conf.mono_conv = 0;
reg = TEGRA30_AHUB_CIF_TX_CTRL +
(channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
{
int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg);
val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
{
int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg);
val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif)
{
int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
__clear_bit(channel, ahub->tx_usage);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo);
int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
enum tegra30_ahub_txcif txcif)
{
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_AUDIO_RX +
(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
tegra30_audio_write(reg, 1 << txcif);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
{
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_AUDIO_RX +
(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
tegra30_audio_write(reg, 0);
pm_runtime_put(ahub->dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
static const struct reset_control_bulk_data tegra30_ahub_resets_data[] = {
{ "d_audio" },
{ "apbif" },
{ "i2s0" },
{ "i2s1" },
{ "i2s2" },
{ "i2s3" },
{ "i2s4" },
{ "dam0" },
{ "dam1" },
{ "dam2" },
{ "spdif" },
{ "amx" }, /* Tegra114+ */
{ "adx" }, /* Tegra114+ */
{ "amx1" }, /* Tegra124 */
{ "adx1" }, /* Tegra124 */
{ "afc0" }, /* Tegra124 */
{ "afc1" }, /* Tegra124 */
{ "afc2" }, /* Tegra124 */
{ "afc3" }, /* Tegra124 */
{ "afc4" }, /* Tegra124 */
{ "afc5" }, /* Tegra124 */
};
#define LAST_REG(name) \
(TEGRA30_AHUB_##name + \
(TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4)
#define REG_IN_ARRAY(reg, name) \
((reg >= TEGRA30_AHUB_##name) && \
(reg <= LAST_REG(name) && \
(!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA30_AHUB_CONFIG_LINK_CTRL:
case TEGRA30_AHUB_MISC_CTRL:
case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
case TEGRA30_AHUB_I2S_LIVE_STATUS:
case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
case TEGRA30_AHUB_I2S_INT_MASK:
case TEGRA30_AHUB_DAM_INT_MASK:
case TEGRA30_AHUB_SPDIF_INT_MASK:
case TEGRA30_AHUB_APBIF_INT_MASK:
case TEGRA30_AHUB_I2S_INT_STATUS:
case TEGRA30_AHUB_DAM_INT_STATUS:
case TEGRA30_AHUB_SPDIF_INT_STATUS:
case TEGRA30_AHUB_APBIF_INT_STATUS:
case TEGRA30_AHUB_I2S_INT_SOURCE:
case TEGRA30_AHUB_DAM_INT_SOURCE:
case TEGRA30_AHUB_SPDIF_INT_SOURCE:
case TEGRA30_AHUB_APBIF_INT_SOURCE:
case TEGRA30_AHUB_I2S_INT_SET:
case TEGRA30_AHUB_DAM_INT_SET:
case TEGRA30_AHUB_SPDIF_INT_SET:
case TEGRA30_AHUB_APBIF_INT_SET:
return true;
default:
break;
}
if (REG_IN_ARRAY(reg, CHANNEL_CTRL) ||
REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
REG_IN_ARRAY(reg, CIF_TX_CTRL) ||
REG_IN_ARRAY(reg, CIF_RX_CTRL) ||
REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
return true;
return false;
}
static bool tegra30_ahub_apbif_volatile_reg(struct device *dev,
unsigned int reg)
{
switch (reg) {
case TEGRA30_AHUB_CONFIG_LINK_CTRL:
case TEGRA30_AHUB_MISC_CTRL:
case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
case TEGRA30_AHUB_I2S_LIVE_STATUS:
case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
case TEGRA30_AHUB_I2S_INT_STATUS:
case TEGRA30_AHUB_DAM_INT_STATUS:
case TEGRA30_AHUB_SPDIF_INT_STATUS:
case TEGRA30_AHUB_APBIF_INT_STATUS:
case TEGRA30_AHUB_I2S_INT_SET:
case TEGRA30_AHUB_DAM_INT_SET:
case TEGRA30_AHUB_SPDIF_INT_SET:
case TEGRA30_AHUB_APBIF_INT_SET:
return true;
default:
break;
}
if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
return true;
return false;
}
static bool tegra30_ahub_apbif_precious_reg(struct device *dev,
unsigned int reg)
{
if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
REG_IN_ARRAY(reg, CHANNEL_RXFIFO))
return true;
return false;
}
static const struct regmap_config tegra30_ahub_apbif_regmap_config = {
.name = "apbif",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TEGRA30_AHUB_APBIF_INT_SET,
.writeable_reg = tegra30_ahub_apbif_wr_rd_reg,
.readable_reg = tegra30_ahub_apbif_wr_rd_reg,
.volatile_reg = tegra30_ahub_apbif_volatile_reg,
.precious_reg = tegra30_ahub_apbif_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg)
{
if (REG_IN_ARRAY(reg, AUDIO_RX))
return true;
return false;
}
static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
.name = "ahub",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = LAST_REG(AUDIO_RX),
.writeable_reg = tegra30_ahub_ahub_wr_rd_reg,
.readable_reg = tegra30_ahub_ahub_wr_rd_reg,
.cache_type = REGCACHE_FLAT,
};
static struct tegra30_ahub_soc_data soc_data_tegra30 = {
.num_resets = 11,
.set_audio_cif = tegra30_ahub_set_cif,
};
static struct tegra30_ahub_soc_data soc_data_tegra114 = {
.num_resets = 13,
.set_audio_cif = tegra30_ahub_set_cif,
};
static struct tegra30_ahub_soc_data soc_data_tegra124 = {
.num_resets = 21,
.set_audio_cif = tegra124_ahub_set_cif,
};
static const struct of_device_id tegra30_ahub_of_match[] = {
{ .compatible = "nvidia,tegra124-ahub", .data = &soc_data_tegra124 },
{ .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 },
{ .compatible = "nvidia,tegra30-ahub", .data = &soc_data_tegra30 },
{},
};
static int tegra30_ahub_probe(struct platform_device *pdev)
{
const struct tegra30_ahub_soc_data *soc_data;
struct resource *res0;
void __iomem *regs_apbif, *regs_ahub;
int ret = 0;
soc_data = of_device_get_match_data(&pdev->dev);
if (!soc_data)
return -EINVAL;
ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
GFP_KERNEL);
if (!ahub)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, ahub);
BUILD_BUG_ON(sizeof(ahub->resets) != sizeof(tegra30_ahub_resets_data));
memcpy(ahub->resets, tegra30_ahub_resets_data, sizeof(ahub->resets));
ahub->nresets = soc_data->num_resets;
ahub->soc_data = soc_data;
ahub->dev = &pdev->dev;
ahub->clocks[ahub->nclocks++].id = "apbif";
ahub->clocks[ahub->nclocks++].id = "d_audio";
ret = devm_clk_bulk_get(&pdev->dev, ahub->nclocks, ahub->clocks);
if (ret)
goto err_unset_ahub;
ret = devm_reset_control_bulk_get_exclusive(&pdev->dev, ahub->nresets,
ahub->resets);
if (ret) {
dev_err(&pdev->dev, "Can't get resets: %d\n", ret);
goto err_unset_ahub;
}
regs_apbif = devm_platform_get_and_ioremap_resource(pdev, 0, &res0);
if (IS_ERR(regs_apbif)) {
ret = PTR_ERR(regs_apbif);
goto err_unset_ahub;
}
ahub->apbif_addr = res0->start;
ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif,
&tegra30_ahub_apbif_regmap_config);
if (IS_ERR(ahub->regmap_apbif)) {
dev_err(&pdev->dev, "apbif regmap init failed\n");
ret = PTR_ERR(ahub->regmap_apbif);
goto err_unset_ahub;
}
regcache_cache_only(ahub->regmap_apbif, true);
regs_ahub = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(regs_ahub)) {
ret = PTR_ERR(regs_ahub);
goto err_unset_ahub;
}
ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub,
&tegra30_ahub_ahub_regmap_config);
if (IS_ERR(ahub->regmap_ahub)) {
dev_err(&pdev->dev, "ahub regmap init failed\n");
ret = PTR_ERR(ahub->regmap_ahub);
goto err_unset_ahub;
}
regcache_cache_only(ahub->regmap_ahub, true);
pm_runtime_enable(&pdev->dev);
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
return 0;
err_unset_ahub:
ahub = NULL;
return ret;
}
static void tegra30_ahub_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
ahub = NULL;
}
static const struct dev_pm_ops tegra30_ahub_pm_ops = {
SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend,
tegra30_ahub_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra30_ahub_driver = {
.probe = tegra30_ahub_probe,
.remove_new = tegra30_ahub_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = tegra30_ahub_of_match,
.pm = &tegra30_ahub_pm_ops,
},
};
module_platform_driver(tegra30_ahub_driver);
void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg,
struct tegra30_ahub_cif_conf *conf)
{
unsigned int value;
value = (conf->threshold <<
TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
((conf->audio_channels - 1) <<
TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
((conf->client_channels - 1) <<
TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
(conf->audio_bits <<
TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
(conf->client_bits <<
TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
(conf->expand <<
TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
(conf->stereo_conv <<
TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
(conf->replicate <<
TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) |
(conf->direction <<
TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
(conf->truncate <<
TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
(conf->mono_conv <<
TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT);
regmap_write(regmap, reg, value);
}
EXPORT_SYMBOL_GPL(tegra30_ahub_set_cif);
void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
struct tegra30_ahub_cif_conf *conf)
{
unsigned int value;
value = (conf->threshold <<
TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
((conf->audio_channels - 1) <<
TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
((conf->client_channels - 1) <<
TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
(conf->audio_bits <<
TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
(conf->client_bits <<
TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
(conf->expand <<
TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
(conf->stereo_conv <<
TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
(conf->replicate <<
TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT) |
(conf->direction <<
TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
(conf->truncate <<
TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
(conf->mono_conv <<
TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT);
regmap_write(regmap, reg, value);
}
EXPORT_SYMBOL_GPL(tegra124_ahub_set_cif);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra30 AHUB driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match);
| linux-master | sound/soc/tegra/tegra30_ahub.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra_pcm.c - Tegra PCM driver
*
* Author: Stephen Warren <[email protected]>
* Copyright (C) 2010,2012 - NVIDIA, Inc.
*
* Based on code copyright/by:
*
* Copyright (c) 2009-2010, NVIDIA Corporation.
* Scott Peterson <[email protected]>
* Vijay Mali <[email protected]>
*
* Copyright (C) 2010 Google, Inc.
* Iliyan Malchev <[email protected]>
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra_pcm.h"
static const struct snd_pcm_hardware tegra_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED,
.period_bytes_min = 1024,
.period_bytes_max = PAGE_SIZE,
.periods_min = 2,
.periods_max = 8,
.buffer_bytes_max = PAGE_SIZE * 8,
.fifo_size = 4,
};
static const struct snd_dmaengine_pcm_config tegra_dmaengine_pcm_config = {
.pcm_hardware = &tegra_pcm_hardware,
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
.prealloc_buffer_size = PAGE_SIZE * 8,
};
int tegra_pcm_platform_register(struct device *dev)
{
return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config, 0);
}
EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);
int devm_tegra_pcm_platform_register(struct device *dev)
{
return devm_snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config, 0);
}
EXPORT_SYMBOL_GPL(devm_tegra_pcm_platform_register);
int tegra_pcm_platform_register_with_chan_names(struct device *dev,
struct snd_dmaengine_pcm_config *config,
char *txdmachan, char *rxdmachan)
{
*config = tegra_dmaengine_pcm_config;
config->dma_dev = dev->parent;
config->chan_names[0] = txdmachan;
config->chan_names[1] = rxdmachan;
return snd_dmaengine_pcm_register(dev, config, 0);
}
EXPORT_SYMBOL_GPL(tegra_pcm_platform_register_with_chan_names);
void tegra_pcm_platform_unregister(struct device *dev)
{
return snd_dmaengine_pcm_unregister(dev);
}
EXPORT_SYMBOL_GPL(tegra_pcm_platform_unregister);
int tegra_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_dmaengine_dai_dma_data *dmap;
struct dma_chan *chan;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
if (rtd->dai_link->no_pcm)
return 0;
dmap = snd_soc_dai_get_dma_data(cpu_dai, substream);
/* Set HW params now that initialization is complete */
snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
/* Ensure period size is multiple of 8 */
ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 0x8);
if (ret) {
dev_err(rtd->dev, "failed to set constraint %d\n", ret);
return ret;
}
chan = dma_request_slave_channel(cpu_dai->dev, dmap->chan_name);
if (!chan) {
dev_err(cpu_dai->dev,
"dmaengine request slave channel failed! (%s)\n",
dmap->chan_name);
return -ENODEV;
}
ret = snd_dmaengine_pcm_open(substream, chan);
if (ret) {
dev_err(rtd->dev,
"dmaengine pcm open failed with err %d (%s)\n", ret,
dmap->chan_name);
dma_release_channel(chan);
return ret;
}
/* Set wait time to 500ms by default */
substream->wait_time = 500;
return 0;
}
EXPORT_SYMBOL_GPL(tegra_pcm_open);
int tegra_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
if (rtd->dai_link->no_pcm)
return 0;
snd_dmaengine_pcm_close_release_chan(substream);
return 0;
}
EXPORT_SYMBOL_GPL(tegra_pcm_close);
int tegra_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_dmaengine_dai_dma_data *dmap;
struct dma_slave_config slave_config;
struct dma_chan *chan;
int ret;
if (rtd->dai_link->no_pcm)
return 0;
dmap = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
if (!dmap)
return 0;
chan = snd_dmaengine_pcm_get_chan(substream);
ret = snd_hwparams_to_dma_slave_config(substream, params,
&slave_config);
if (ret) {
dev_err(rtd->dev, "hw params config failed with err %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.dst_addr = dmap->addr;
slave_config.dst_maxburst = 8;
} else {
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.src_addr = dmap->addr;
slave_config.src_maxburst = 8;
}
ret = dmaengine_slave_config(chan, &slave_config);
if (ret < 0) {
dev_err(rtd->dev, "dma slave config failed with err %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(tegra_pcm_hw_params);
snd_pcm_uframes_t tegra_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
return snd_dmaengine_pcm_pointer(substream);
}
EXPORT_SYMBOL_GPL(tegra_pcm_pointer);
static int tegra_pcm_dma_allocate(struct device *dev, struct snd_soc_pcm_runtime *rtd,
size_t size)
{
struct snd_pcm *pcm = rtd->pcm;
int ret;
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret < 0)
return ret;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC, dev, size);
}
int tegra_pcm_construct(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *dev = component->dev;
/*
* Fallback for backwards-compatibility with older device trees that
* have the iommus property in the virtual, top-level "sound" node.
*/
if (!of_get_property(dev->of_node, "iommus", NULL))
dev = rtd->card->snd_card->dev;
return tegra_pcm_dma_allocate(dev, rtd, tegra_pcm_hardware.buffer_bytes_max);
}
EXPORT_SYMBOL_GPL(tegra_pcm_construct);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra PCM ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/tegra/tegra_pcm.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_peq.c - Tegra210 PEQ driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_ope.h"
#include "tegra210_peq.h"
static const struct reg_default tegra210_peq_reg_defaults[] = {
{ TEGRA210_PEQ_CFG, 0x00000013},
{ TEGRA210_PEQ_CFG_RAM_CTRL, 0x00004000},
{ TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL, 0x00004000},
};
static const u32 biquad_init_gains[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH] = {
1495012349, /* Pre-gain */
/* Gains : b0, b1, a0, a1, a2 */
536870912, -1073741824, 536870912, 2143508246, -1069773768, /* Band-0 */
134217728, -265414508, 131766272, 2140402222, -1071252997, /* Band-1 */
268435456, -233515765, -33935948, 1839817267, -773826124, /* Band-2 */
536870912, -672537913, 139851540, 1886437554, -824433167, /* Band-3 */
268435456, -114439279, 173723964, 205743566, 278809729, /* Band-4 */
1, 0, 0, 0, 0, /* Band-5 */
1, 0, 0, 0, 0, /* Band-6 */
1, 0, 0, 0, 0, /* Band-7 */
1, 0, 0, 0, 0, /* Band-8 */
1, 0, 0, 0, 0, /* Band-9 */
1, 0, 0, 0, 0, /* Band-10 */
1, 0, 0, 0, 0, /* Band-11 */
963423114, /* Post-gain */
};
static const u32 biquad_init_shifts[TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH] = {
23, /* Pre-shift */
30, 30, 30, 30, 30, 0, 0, 0, 0, 0, 0, 0, /* Shift for bands */
28, /* Post-shift */
};
static s32 biquad_coeff_buffer[TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH];
static void tegra210_peq_read_ram(struct regmap *regmap, unsigned int reg_ctrl,
unsigned int reg_data, unsigned int ram_offset,
unsigned int *data, size_t size)
{
unsigned int val;
unsigned int i;
val = ram_offset & TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK;
val |= TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN;
val |= TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN;
val |= TEGRA210_PEQ_RAM_CTRL_RW_READ;
regmap_write(regmap, reg_ctrl, val);
/*
* Since all ahub non-io modules work under same ahub clock it is not
* necessary to check ahub read busy bit after every read.
*/
for (i = 0; i < size; i++)
regmap_read(regmap, reg_data, &data[i]);
}
static void tegra210_peq_write_ram(struct regmap *regmap, unsigned int reg_ctrl,
unsigned int reg_data, unsigned int ram_offset,
unsigned int *data, size_t size)
{
unsigned int val;
unsigned int i;
val = ram_offset & TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK;
val |= TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN;
val |= TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN;
val |= TEGRA210_PEQ_RAM_CTRL_RW_WRITE;
regmap_write(regmap, reg_ctrl, val);
for (i = 0; i < size; i++)
regmap_write(regmap, reg_data, data[i]);
}
static int tegra210_peq_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
unsigned int mask = (1 << fls(mc->max)) - 1;
unsigned int val;
regmap_read(ope->peq_regmap, mc->reg, &val);
ucontrol->value.integer.value[0] = (val >> mc->shift) & mask;
if (!mc->invert)
return 0;
ucontrol->value.integer.value[0] =
mc->max - ucontrol->value.integer.value[0];
return 0;
}
static int tegra210_peq_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
unsigned int mask = (1 << fls(mc->max)) - 1;
bool change = false;
unsigned int val;
val = (ucontrol->value.integer.value[0] & mask);
if (mc->invert)
val = mc->max - val;
val = val << mc->shift;
regmap_update_bits_check(ope->peq_regmap, mc->reg, (mask << mc->shift),
val, &change);
return change ? 1 : 0;
}
static int tegra210_peq_ram_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 i, reg_ctrl = params->soc.base;
u32 reg_data = reg_ctrl + cmpnt->val_bytes;
s32 *data = (s32 *)biquad_coeff_buffer;
pm_runtime_get_sync(cmpnt->dev);
tegra210_peq_read_ram(ope->peq_regmap, reg_ctrl, reg_data,
params->shift, data, params->soc.num_regs);
pm_runtime_put_sync(cmpnt->dev);
for (i = 0; i < params->soc.num_regs; i++)
ucontrol->value.integer.value[i] = (long)data[i];
return 0;
}
static int tegra210_peq_ram_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 i, reg_ctrl = params->soc.base;
u32 reg_data = reg_ctrl + cmpnt->val_bytes;
s32 *data = (s32 *)biquad_coeff_buffer;
for (i = 0; i < params->soc.num_regs; i++)
data[i] = (s32)ucontrol->value.integer.value[i];
pm_runtime_get_sync(cmpnt->dev);
tegra210_peq_write_ram(ope->peq_regmap, reg_ctrl, reg_data,
params->shift, data, params->soc.num_regs);
pm_runtime_put_sync(cmpnt->dev);
return 1;
}
static int tegra210_peq_param_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct soc_bytes *params = (void *)kcontrol->private_value;
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->value.integer.min = INT_MIN;
uinfo->value.integer.max = INT_MAX;
uinfo->count = params->num_regs;
return 0;
}
#define TEGRA210_PEQ_GAIN_PARAMS_CTRL(chan) \
TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " Biquad Gain Params", \
TEGRA210_PEQ_CFG_RAM_CTRL, \
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH, \
(TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH * chan), 0xffffffff, \
tegra210_peq_ram_get, tegra210_peq_ram_put, \
tegra210_peq_param_info)
#define TEGRA210_PEQ_SHIFT_PARAMS_CTRL(chan) \
TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " Biquad Shift Params", \
TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL, \
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH, \
(TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH * chan), 0x1f, \
tegra210_peq_ram_get, tegra210_peq_ram_put, \
tegra210_peq_param_info)
static const struct snd_kcontrol_new tegra210_peq_controls[] = {
SOC_SINGLE_EXT("PEQ Active", TEGRA210_PEQ_CFG,
TEGRA210_PEQ_CFG_MODE_SHIFT, 1, 0,
tegra210_peq_get, tegra210_peq_put),
SOC_SINGLE_EXT("PEQ Biquad Stages", TEGRA210_PEQ_CFG,
TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT,
TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0,
tegra210_peq_get, tegra210_peq_put),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(0),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(1),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(2),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(3),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(4),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(5),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(6),
TEGRA210_PEQ_GAIN_PARAMS_CTRL(7),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(0),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(1),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(2),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(3),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(4),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(5),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(6),
TEGRA210_PEQ_SHIFT_PARAMS_CTRL(7),
};
static bool tegra210_peq_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_PEQ_SOFT_RESET:
case TEGRA210_PEQ_CG:
case TEGRA210_PEQ_CFG ... TEGRA210_PEQ_CFG_RAM_SHIFT_DATA:
return true;
default:
return false;
}
}
static bool tegra210_peq_rd_reg(struct device *dev, unsigned int reg)
{
if (tegra210_peq_wr_reg(dev, reg))
return true;
switch (reg) {
case TEGRA210_PEQ_STATUS:
return true;
default:
return false;
}
}
static bool tegra210_peq_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_PEQ_SOFT_RESET:
case TEGRA210_PEQ_STATUS:
case TEGRA210_PEQ_CFG_RAM_CTRL ... TEGRA210_PEQ_CFG_RAM_SHIFT_DATA:
return true;
default:
return false;
}
}
static bool tegra210_peq_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_PEQ_CFG_RAM_DATA:
case TEGRA210_PEQ_CFG_RAM_SHIFT_DATA:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_peq_regmap_config = {
.name = "peq",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
.writeable_reg = tegra210_peq_wr_reg,
.readable_reg = tegra210_peq_rd_reg,
.volatile_reg = tegra210_peq_volatile_reg,
.precious_reg = tegra210_peq_precious_reg,
.reg_defaults = tegra210_peq_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_peq_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
void tegra210_peq_restore(struct regmap *regmap, u32 *biquad_gains,
u32 *biquad_shifts)
{
unsigned int i;
for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
tegra210_peq_write_ram(regmap, TEGRA210_PEQ_CFG_RAM_CTRL,
TEGRA210_PEQ_CFG_RAM_DATA,
(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
biquad_gains,
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
tegra210_peq_write_ram(regmap,
TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL,
TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
biquad_shifts,
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
}
}
void tegra210_peq_save(struct regmap *regmap, u32 *biquad_gains,
u32 *biquad_shifts)
{
unsigned int i;
for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
tegra210_peq_read_ram(regmap,
TEGRA210_PEQ_CFG_RAM_CTRL,
TEGRA210_PEQ_CFG_RAM_DATA,
(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
biquad_gains,
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
tegra210_peq_read_ram(regmap,
TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL,
TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
biquad_shifts,
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
}
}
int tegra210_peq_component_init(struct snd_soc_component *cmpnt)
{
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
unsigned int i;
pm_runtime_get_sync(cmpnt->dev);
regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CFG,
TEGRA210_PEQ_CFG_MODE_MASK,
0 << TEGRA210_PEQ_CFG_MODE_SHIFT);
regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CFG,
TEGRA210_PEQ_CFG_BIQUAD_STAGES_MASK,
(TEGRA210_PEQ_BIQUAD_INIT_STAGE - 1) <<
TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT);
/* Initialize PEQ AHUB RAM with default params */
for (i = 0; i < TEGRA210_PEQ_MAX_CHANNELS; i++) {
/* Set default gain params */
tegra210_peq_write_ram(ope->peq_regmap,
TEGRA210_PEQ_CFG_RAM_CTRL,
TEGRA210_PEQ_CFG_RAM_DATA,
(i * TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH),
(u32 *)&biquad_init_gains,
TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH);
/* Set default shift params */
tegra210_peq_write_ram(ope->peq_regmap,
TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL,
TEGRA210_PEQ_CFG_RAM_SHIFT_DATA,
(i * TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH),
(u32 *)&biquad_init_shifts,
TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH);
}
pm_runtime_put_sync(cmpnt->dev);
snd_soc_add_component_controls(cmpnt, tegra210_peq_controls,
ARRAY_SIZE(tegra210_peq_controls));
return 0;
}
int tegra210_peq_regmap_init(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_ope *ope = dev_get_drvdata(dev);
struct device_node *child;
struct resource mem;
void __iomem *regs;
int err;
child = of_get_child_by_name(dev->of_node, "equalizer");
if (!child)
return -ENODEV;
err = of_address_to_resource(child, 0, &mem);
of_node_put(child);
if (err < 0) {
dev_err(dev, "fail to get PEQ resource\n");
return err;
}
mem.flags = IORESOURCE_MEM;
regs = devm_ioremap_resource(dev, &mem);
if (IS_ERR(regs))
return PTR_ERR(regs);
ope->peq_regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_peq_regmap_config);
if (IS_ERR(ope->peq_regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(ope->peq_regmap);
}
regcache_cache_only(ope->peq_regmap, true);
return 0;
}
| linux-master | sound/soc/tegra/tegra210_peq.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra186_dspk.c - Tegra186 DSPK driver
//
// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra186_dspk.h"
#include "tegra_cif.h"
static const struct reg_default tegra186_dspk_reg_defaults[] = {
{ TEGRA186_DSPK_RX_INT_MASK, 0x00000007 },
{ TEGRA186_DSPK_RX_CIF_CTRL, 0x00007700 },
{ TEGRA186_DSPK_CG, 0x00000001 },
{ TEGRA186_DSPK_CORE_CTRL, 0x00000310 },
{ TEGRA186_DSPK_CODEC_CTRL, 0x03000000 },
};
static int tegra186_dspk_get_fifo_th(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
return 0;
}
static int tegra186_dspk_put_fifo_th(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
int value = ucontrol->value.integer.value[0];
if (value == dspk->rx_fifo_th)
return 0;
dspk->rx_fifo_th = value;
return 1;
}
static int tegra186_dspk_get_osr_val(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = dspk->osr_val;
return 0;
}
static int tegra186_dspk_put_osr_val(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dspk->osr_val)
return 0;
dspk->osr_val = value;
return 1;
}
static int tegra186_dspk_get_pol_sel(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = dspk->lrsel;
return 0;
}
static int tegra186_dspk_put_pol_sel(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dspk->lrsel)
return 0;
dspk->lrsel = value;
return 1;
}
static int tegra186_dspk_get_ch_sel(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = dspk->ch_sel;
return 0;
}
static int tegra186_dspk_put_ch_sel(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dspk->ch_sel)
return 0;
dspk->ch_sel = value;
return 1;
}
static int tegra186_dspk_get_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = dspk->mono_to_stereo;
return 0;
}
static int tegra186_dspk_put_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dspk->mono_to_stereo)
return 0;
dspk->mono_to_stereo = value;
return 1;
}
static int tegra186_dspk_get_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
ucontrol->value.enumerated.item[0] = dspk->stereo_to_mono;
return 0;
}
static int tegra186_dspk_put_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dspk->stereo_to_mono)
return 0;
dspk->stereo_to_mono = value;
return 1;
}
static int __maybe_unused tegra186_dspk_runtime_suspend(struct device *dev)
{
struct tegra186_dspk *dspk = dev_get_drvdata(dev);
regcache_cache_only(dspk->regmap, true);
regcache_mark_dirty(dspk->regmap);
clk_disable_unprepare(dspk->clk_dspk);
return 0;
}
static int __maybe_unused tegra186_dspk_runtime_resume(struct device *dev)
{
struct tegra186_dspk *dspk = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(dspk->clk_dspk);
if (err) {
dev_err(dev, "failed to enable DSPK clock, err: %d\n", err);
return err;
}
regcache_cache_only(dspk->regmap, false);
regcache_sync(dspk->regmap);
return 0;
}
static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
unsigned int channels, srate, dspk_clk;
struct device *dev = dai->dev;
struct tegra_cif_conf cif_conf;
unsigned int max_th;
int err;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
cif_conf.audio_ch = channels;
/* Client channel */
switch (dspk->ch_sel) {
case DSPK_CH_SELECT_LEFT:
case DSPK_CH_SELECT_RIGHT:
cif_conf.client_ch = 1;
break;
case DSPK_CH_SELECT_STEREO:
cif_conf.client_ch = 2;
break;
default:
dev_err(dev, "Invalid DSPK client channels\n");
return -EINVAL;
}
cif_conf.client_bits = TEGRA_ACIF_BITS_24;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
dev_err(dev, "unsupported format!\n");
return -EOPNOTSUPP;
}
srate = params_rate(params);
/* RX FIFO threshold in terms of frames */
max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
if (dspk->rx_fifo_th > max_th)
dspk->rx_fifo_th = max_th;
cif_conf.threshold = dspk->rx_fifo_th;
cif_conf.mono_conv = dspk->mono_to_stereo;
cif_conf.stereo_conv = dspk->stereo_to_mono;
tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,
&cif_conf);
/*
* DSPK clock and PDM codec clock should be synchronous with 4:1 ratio,
* this is because it takes 4 clock cycles to send out one sample to
* codec by sigma delta modulator. Finally the clock rate is a multiple
* of 'Over Sampling Ratio', 'Sample Rate' and 'Interface Clock Ratio'.
*/
dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;
err = clk_set_rate(dspk->clk_dspk, dspk_clk);
if (err) {
dev_err(dev, "can't set DSPK clock rate %u, err: %d\n",
dspk_clk, err);
return err;
}
regmap_update_bits(dspk->regmap,
/* Reg */
TEGRA186_DSPK_CORE_CTRL,
/* Mask */
TEGRA186_DSPK_OSR_MASK |
TEGRA186_DSPK_CHANNEL_SELECT_MASK |
TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK,
/* Value */
(dspk->osr_val << DSPK_OSR_SHIFT) |
((dspk->ch_sel + 1) << CH_SEL_SHIFT) |
(dspk->lrsel << LRSEL_POL_SHIFT));
return 0;
}
static const struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
.hw_params = tegra186_dspk_hw_params,
};
static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
{
.name = "DSPK-CIF",
.playback = {
.stream_name = "CIF-Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
{
.name = "DSPK-DAP",
.playback = {
.stream_name = "DAP-Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra186_dspk_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0),
SND_SOC_DAPM_SPK("SPK", NULL),
};
static const struct snd_soc_dapm_route tegra186_dspk_routes[] = {
{ "XBAR-Playback", NULL, "XBAR-TX" },
{ "CIF-Playback", NULL, "XBAR-Playback" },
{ "RX", NULL, "CIF-Playback" },
{ "DAP-Playback", NULL, "RX" },
{ "SPK", NULL, "DAP-Playback" },
};
static const char * const tegra186_dspk_ch_sel_text[] = {
"Left", "Right", "Stereo",
};
static const struct soc_enum tegra186_dspk_ch_sel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_ch_sel_text),
tegra186_dspk_ch_sel_text);
static const char * const tegra186_dspk_osr_text[] = {
"OSR_32", "OSR_64", "OSR_128", "OSR_256",
};
static const struct soc_enum tegra186_dspk_osr_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_osr_text),
tegra186_dspk_osr_text);
static const char * const tegra186_dspk_lrsel_text[] = {
"Left", "Right",
};
static const char * const tegra186_dspk_mono_conv_text[] = {
"Zero", "Copy",
};
static const struct soc_enum tegra186_dspk_mono_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_mono_conv_text),
tegra186_dspk_mono_conv_text);
static const char * const tegra186_dspk_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const struct soc_enum tegra186_dspk_stereo_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_stereo_conv_text),
tegra186_dspk_stereo_conv_text);
static const struct soc_enum tegra186_dspk_lrsel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_lrsel_text),
tegra186_dspk_lrsel_text);
static const struct snd_kcontrol_new tegrat186_dspk_controls[] = {
SOC_SINGLE_EXT("FIFO Threshold", SND_SOC_NOPM, 0,
TEGRA186_DSPK_RX_FIFO_DEPTH - 1, 0,
tegra186_dspk_get_fifo_th, tegra186_dspk_put_fifo_th),
SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum,
tegra186_dspk_get_osr_val, tegra186_dspk_put_osr_val),
SOC_ENUM_EXT("LR Polarity Select", tegra186_dspk_lrsel_enum,
tegra186_dspk_get_pol_sel, tegra186_dspk_put_pol_sel),
SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum,
tegra186_dspk_get_ch_sel, tegra186_dspk_put_ch_sel),
SOC_ENUM_EXT("Mono To Stereo", tegra186_dspk_mono_conv_enum,
tegra186_dspk_get_mono_to_stereo,
tegra186_dspk_put_mono_to_stereo),
SOC_ENUM_EXT("Stereo To Mono", tegra186_dspk_stereo_conv_enum,
tegra186_dspk_get_stereo_to_mono,
tegra186_dspk_put_stereo_to_mono),
};
static const struct snd_soc_component_driver tegra186_dspk_cmpnt = {
.dapm_widgets = tegra186_dspk_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
.dapm_routes = tegra186_dspk_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
.controls = tegrat186_dspk_controls,
.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
};
static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA186_DSPK_RX_INT_MASK ... TEGRA186_DSPK_RX_CIF_CTRL:
case TEGRA186_DSPK_ENABLE ... TEGRA186_DSPK_CG:
case TEGRA186_DSPK_CORE_CTRL ... TEGRA186_DSPK_CODEC_CTRL:
return true;
default:
return false;
}
}
static bool tegra186_dspk_rd_reg(struct device *dev, unsigned int reg)
{
if (tegra186_dspk_wr_reg(dev, reg))
return true;
switch (reg) {
case TEGRA186_DSPK_RX_STATUS:
case TEGRA186_DSPK_RX_INT_STATUS:
case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS:
return true;
default:
return false;
}
}
static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA186_DSPK_RX_STATUS:
case TEGRA186_DSPK_RX_INT_STATUS:
case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS:
return true;
default:
return false;
}
}
static const struct regmap_config tegra186_dspk_regmap = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA186_DSPK_CODEC_CTRL,
.writeable_reg = tegra186_dspk_wr_reg,
.readable_reg = tegra186_dspk_rd_reg,
.volatile_reg = tegra186_dspk_volatile_reg,
.reg_defaults = tegra186_dspk_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra186_dspk_of_match[] = {
{ .compatible = "nvidia,tegra186-dspk" },
{},
};
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
static int tegra186_dspk_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra186_dspk *dspk;
void __iomem *regs;
int err;
dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);
if (!dspk)
return -ENOMEM;
dspk->osr_val = DSPK_OSR_64;
dspk->lrsel = DSPK_LRSEL_LEFT;
dspk->ch_sel = DSPK_CH_SELECT_STEREO;
dspk->mono_to_stereo = 0; /* "Zero" */
dev_set_drvdata(dev, dspk);
dspk->clk_dspk = devm_clk_get(dev, "dspk");
if (IS_ERR(dspk->clk_dspk)) {
dev_err(dev, "can't retrieve DSPK clock\n");
return PTR_ERR(dspk->clk_dspk);
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);
if (IS_ERR(dspk->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(dspk->regmap);
}
regcache_cache_only(dspk->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra186_dspk_cmpnt,
tegra186_dspk_dais,
ARRAY_SIZE(tegra186_dspk_dais));
if (err) {
dev_err(dev, "can't register DSPK component, err: %d\n",
err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra186_dspk_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra186_dspk_pm_ops = {
SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend,
tegra186_dspk_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra186_dspk_driver = {
.driver = {
.name = "tegra186-dspk",
.of_match_table = tegra186_dspk_of_match,
.pm = &tegra186_dspk_pm_ops,
},
.probe = tegra186_dspk_platform_probe,
.remove_new = tegra186_dspk_platform_remove,
};
module_platform_driver(tegra186_dspk_driver);
MODULE_AUTHOR("Mohan Kumar <[email protected]>");
MODULE_AUTHOR("Sameer Pujar <[email protected]>");
MODULE_DESCRIPTION("Tegra186 ASoC DSPK driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra186_dspk.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra_audio_graph_card.c - Audio Graph based Tegra Machine Driver
//
// Copyright (c) 2020-2021 NVIDIA CORPORATION. All rights reserved.
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <sound/graph_card.h>
#include <sound/pcm_params.h>
#include <sound/soc-dai.h>
#define MAX_PLLA_OUT0_DIV 128
#define simple_to_tegra_priv(simple) \
container_of(simple, struct tegra_audio_priv, simple)
enum srate_type {
/*
* Sample rates multiple of 8000 Hz and below are supported:
* ( 8000, 16000, 32000, 48000, 96000, 192000 Hz )
*/
x8_RATE,
/*
* Sample rates multiple of 11025 Hz and below are supported:
* ( 11025, 22050, 44100, 88200, 176400 Hz )
*/
x11_RATE,
NUM_RATE_TYPE,
};
struct tegra_audio_priv {
struct asoc_simple_priv simple;
struct clk *clk_plla_out0;
struct clk *clk_plla;
};
/* Tegra audio chip data */
struct tegra_audio_cdata {
unsigned int plla_rates[NUM_RATE_TYPE];
unsigned int plla_out0_rates[NUM_RATE_TYPE];
};
static bool need_clk_update(struct snd_soc_dai *dai)
{
if (snd_soc_dai_is_dummy(dai) ||
!dai->driver->ops ||
!dai->driver->name)
return false;
if (strstr(dai->driver->name, "I2S") ||
strstr(dai->driver->name, "DMIC") ||
strstr(dai->driver->name, "DSPK"))
return true;
return false;
}
/* Setup PLL clock as per the given sample rate */
static int tegra_audio_graph_update_pll(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct asoc_simple_priv *simple = snd_soc_card_get_drvdata(rtd->card);
struct tegra_audio_priv *priv = simple_to_tegra_priv(simple);
struct device *dev = rtd->card->dev;
const struct tegra_audio_cdata *data = of_device_get_match_data(dev);
unsigned int plla_rate, plla_out0_rate, bclk;
unsigned int srate = params_rate(params);
int err;
switch (srate) {
case 11025:
case 22050:
case 44100:
case 88200:
case 176400:
plla_out0_rate = data->plla_out0_rates[x11_RATE];
plla_rate = data->plla_rates[x11_RATE];
break;
case 8000:
case 16000:
case 32000:
case 48000:
case 96000:
case 192000:
plla_out0_rate = data->plla_out0_rates[x8_RATE];
plla_rate = data->plla_rates[x8_RATE];
break;
default:
dev_err(rtd->card->dev, "Unsupported sample rate %u\n",
srate);
return -EINVAL;
}
/*
* Below is the clock relation:
*
* PLLA
* |
* |--> PLLA_OUT0
* |
* |---> I2S modules
* |
* |---> DMIC modules
* |
* |---> DSPK modules
*
*
* Default PLLA_OUT0 rate might be too high when I/O is running
* at minimum PCM configurations. This may result in incorrect
* clock rates and glitchy audio. The maximum divider is 128
* and any thing higher than that won't work. Thus reduce PLLA_OUT0
* to work for lower configurations.
*
* This problem is seen for I2S only, as DMIC and DSPK minimum
* clock requirements are under allowed divider limits.
*/
bclk = srate * params_channels(params) * params_width(params);
if (div_u64(plla_out0_rate, bclk) > MAX_PLLA_OUT0_DIV)
plla_out0_rate >>= 1;
dev_dbg(rtd->card->dev,
"Update clock rates: PLLA(= %u Hz) and PLLA_OUT0(= %u Hz)\n",
plla_rate, plla_out0_rate);
/* Set PLLA rate */
err = clk_set_rate(priv->clk_plla, plla_rate);
if (err) {
dev_err(rtd->card->dev,
"Can't set plla rate for %u, err: %d\n",
plla_rate, err);
return err;
}
/* Set PLLA_OUT0 rate */
err = clk_set_rate(priv->clk_plla_out0, plla_out0_rate);
if (err) {
dev_err(rtd->card->dev,
"Can't set plla_out0 rate %u, err: %d\n",
plla_out0_rate, err);
return err;
}
return err;
}
static int tegra_audio_graph_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int err;
if (need_clk_update(cpu_dai)) {
err = tegra_audio_graph_update_pll(substream, params);
if (err)
return err;
}
return asoc_simple_hw_params(substream, params);
}
static const struct snd_soc_ops tegra_audio_graph_ops = {
.startup = asoc_simple_startup,
.shutdown = asoc_simple_shutdown,
.hw_params = tegra_audio_graph_hw_params,
};
static int tegra_audio_graph_card_probe(struct snd_soc_card *card)
{
struct asoc_simple_priv *simple = snd_soc_card_get_drvdata(card);
struct tegra_audio_priv *priv = simple_to_tegra_priv(simple);
priv->clk_plla = devm_clk_get(card->dev, "pll_a");
if (IS_ERR(priv->clk_plla)) {
dev_err(card->dev, "Can't retrieve clk pll_a\n");
return PTR_ERR(priv->clk_plla);
}
priv->clk_plla_out0 = devm_clk_get(card->dev, "plla_out0");
if (IS_ERR(priv->clk_plla_out0)) {
dev_err(card->dev, "Can't retrieve clk plla_out0\n");
return PTR_ERR(priv->clk_plla_out0);
}
return asoc_graph_card_probe(card);
}
static int tegra_audio_graph_probe(struct platform_device *pdev)
{
struct tegra_audio_priv *priv;
struct device *dev = &pdev->dev;
struct snd_soc_card *card;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
card = simple_priv_to_card(&priv->simple);
card->driver_name = "tegra-ape";
card->probe = tegra_audio_graph_card_probe;
/* audio_graph_parse_of() depends on below */
card->component_chaining = 1;
priv->simple.ops = &tegra_audio_graph_ops;
priv->simple.force_dpcm = 1;
return audio_graph_parse_of(&priv->simple, dev);
}
static const struct tegra_audio_cdata tegra210_data = {
/* PLLA */
.plla_rates[x8_RATE] = 368640000,
.plla_rates[x11_RATE] = 338688000,
/* PLLA_OUT0 */
.plla_out0_rates[x8_RATE] = 49152000,
.plla_out0_rates[x11_RATE] = 45158400,
};
static const struct tegra_audio_cdata tegra186_data = {
/* PLLA */
.plla_rates[x8_RATE] = 245760000,
.plla_rates[x11_RATE] = 270950400,
/* PLLA_OUT0 */
.plla_out0_rates[x8_RATE] = 49152000,
.plla_out0_rates[x11_RATE] = 45158400,
};
static const struct of_device_id graph_of_tegra_match[] = {
{ .compatible = "nvidia,tegra210-audio-graph-card",
.data = &tegra210_data },
{ .compatible = "nvidia,tegra186-audio-graph-card",
.data = &tegra186_data },
{},
};
MODULE_DEVICE_TABLE(of, graph_of_tegra_match);
static struct platform_driver tegra_audio_graph_card = {
.driver = {
.name = "tegra-audio-graph-card",
.pm = &snd_soc_pm_ops,
.of_match_table = graph_of_tegra_match,
},
.probe = tegra_audio_graph_probe,
.remove = asoc_simple_remove,
};
module_platform_driver(tegra_audio_graph_card);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ASoC Tegra Audio Graph Sound Card");
MODULE_AUTHOR("Sameer Pujar <[email protected]>");
| linux-master | sound/soc/tegra/tegra_audio_graph_card.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra20_das.c - Tegra20 DAS driver
*
* Author: Stephen Warren <[email protected]>
* Copyright (C) 2010 - NVIDIA, Inc.
*/
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/soc.h>
#define DRV_NAME "tegra20-das"
/* Register TEGRA20_DAS_DAP_CTRL_SEL */
#define TEGRA20_DAS_DAP_CTRL_SEL 0x00
#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
#define TEGRA20_DAS_DAP_SEL_DAC1 0
#define TEGRA20_DAS_DAP_SEL_DAC2 1
#define TEGRA20_DAS_DAP_SEL_DAC3 2
#define TEGRA20_DAS_DAP_SEL_DAP1 16
#define TEGRA20_DAS_DAP_SEL_DAP2 17
#define TEGRA20_DAS_DAP_SEL_DAP3 18
#define TEGRA20_DAS_DAP_SEL_DAP4 19
#define TEGRA20_DAS_DAP_SEL_DAP5 20
/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
/*
* Values for:
* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
*/
#define TEGRA20_DAS_DAC_SEL_DAP1 0
#define TEGRA20_DAS_DAC_SEL_DAP2 1
#define TEGRA20_DAS_DAC_SEL_DAP3 2
#define TEGRA20_DAS_DAC_SEL_DAP4 3
#define TEGRA20_DAS_DAC_SEL_DAP5 4
/*
* Names/IDs of the DACs/DAPs.
*/
#define TEGRA20_DAS_DAP_ID_1 0
#define TEGRA20_DAS_DAP_ID_2 1
#define TEGRA20_DAS_DAP_ID_3 2
#define TEGRA20_DAS_DAP_ID_4 3
#define TEGRA20_DAS_DAP_ID_5 4
#define TEGRA20_DAS_DAC_ID_1 0
#define TEGRA20_DAS_DAC_ID_2 1
#define TEGRA20_DAS_DAC_ID_3 2
struct tegra20_das {
struct regmap *regmap;
};
/*
* Terminology:
* DAS: Digital audio switch (HW module controlled by this driver)
* DAP: Digital audio port (port/pins on Tegra device)
* DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
*
* The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
* DAC, or another DAP. When DAPs are connected, one must be the master and
* one the slave. Each DAC allows selection of a specific DAP for input, to
* cater for the case where N DAPs are connected to 1 DAC for broadcast
* output.
*
* This driver is dumb; no attempt is made to ensure that a valid routing
* configuration is programmed.
*/
static inline void tegra20_das_write(struct tegra20_das *das, u32 reg, u32 val)
{
regmap_write(das->regmap, reg, val);
}
static void tegra20_das_connect_dap_to_dac(struct tegra20_das *das, int dap, int dac)
{
u32 addr;
u32 reg;
addr = TEGRA20_DAS_DAP_CTRL_SEL +
(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
tegra20_das_write(das, addr, reg);
}
static void tegra20_das_connect_dac_to_dap(struct tegra20_das *das, int dac, int dap)
{
u32 addr;
u32 reg;
addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
(dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
tegra20_das_write(das, addr, reg);
}
#define LAST_REG(name) \
(TEGRA20_DAS_##name + \
(TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1)))
static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg)
{
if (reg <= LAST_REG(DAP_CTRL_SEL))
return true;
if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) &&
(reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL)))
return true;
return false;
}
static const struct regmap_config tegra20_das_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL),
.writeable_reg = tegra20_das_wr_rd_reg,
.readable_reg = tegra20_das_wr_rd_reg,
.cache_type = REGCACHE_FLAT,
};
static int tegra20_das_probe(struct platform_device *pdev)
{
void __iomem *regs;
struct tegra20_das *das;
das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
if (!das)
return -ENOMEM;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
das->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra20_das_regmap_config);
if (IS_ERR(das->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(das->regmap);
}
tegra20_das_connect_dap_to_dac(das, TEGRA20_DAS_DAP_ID_1,
TEGRA20_DAS_DAP_SEL_DAC1);
tegra20_das_connect_dac_to_dap(das, TEGRA20_DAS_DAC_ID_1,
TEGRA20_DAS_DAC_SEL_DAP1);
tegra20_das_connect_dap_to_dac(das, TEGRA20_DAS_DAP_ID_3,
TEGRA20_DAS_DAP_SEL_DAC3);
tegra20_das_connect_dac_to_dap(das, TEGRA20_DAS_DAC_ID_3,
TEGRA20_DAS_DAC_SEL_DAP3);
return 0;
}
static const struct of_device_id tegra20_das_of_match[] = {
{ .compatible = "nvidia,tegra20-das", },
{},
};
static struct platform_driver tegra20_das_driver = {
.probe = tegra20_das_probe,
.driver = {
.name = DRV_NAME,
.of_match_table = tegra20_das_of_match,
},
};
module_platform_driver(tegra20_das_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra20 DAS driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_das_of_match);
| linux-master | sound/soc/tegra/tegra20_das.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_amx.c - Tegra210 AMX driver
//
// Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_amx.h"
#include "tegra_cif.h"
/*
* The counter is in terms of AHUB clock cycles. If a frame is not
* received within these clock cycles, the AMX input channel gets
* automatically disabled. For now the counter is calculated as a
* function of sample rate (8 kHz) and AHUB clock (49.152 MHz).
* If later an accurate number is needed, the counter needs to be
* calculated at runtime.
*
* count = ahub_clk / sample_rate
*/
#define TEGRA194_MAX_FRAME_IDLE_COUNT 0x1800
#define AMX_CH_REG(id, reg) ((reg) + ((id) * TEGRA210_AMX_AUDIOCIF_CH_STRIDE))
static const struct reg_default tegra210_amx_reg_defaults[] = {
{ TEGRA210_AMX_RX_INT_MASK, 0x0000000f},
{ TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_TX_INT_MASK, 0x00000001},
{ TEGRA210_AMX_TX_CIF_CTRL, 0x00007000},
{ TEGRA210_AMX_CG, 0x1},
{ TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000},
};
static void tegra210_amx_write_map_ram(struct tegra210_amx *amx)
{
int i;
regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL,
TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN |
TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE);
for (i = 0; i < TEGRA210_AMX_RAM_DEPTH; i++)
regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA,
amx->map[i]);
regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN0, amx->byte_mask[0]);
regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN1, amx->byte_mask[1]);
}
static int tegra210_amx_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
unsigned int val;
int err;
/* Ensure if AMX is disabled */
err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_STATUS, val,
!(val & 0x1), 10, 10000);
if (err < 0) {
dev_err(dai->dev, "failed to stop AMX, err = %d\n", err);
return err;
}
/*
* Soft Reset: Below performs module soft reset which clears
* all FSM logic, flushes flow control of FIFO and resets the
* state register. It also brings module back to disabled
* state (without flushing the data in the pipe).
*/
regmap_update_bits(amx->regmap, TEGRA210_AMX_SOFT_RESET,
TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK,
TEGRA210_AMX_SOFT_RESET_SOFT_EN);
err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_SOFT_RESET,
val, !(val & 0x1), 10, 10000);
if (err < 0) {
dev_err(dai->dev, "failed to reset AMX, err = %d\n", err);
return err;
}
return 0;
}
static int __maybe_unused tegra210_amx_runtime_suspend(struct device *dev)
{
struct tegra210_amx *amx = dev_get_drvdata(dev);
regcache_cache_only(amx->regmap, true);
regcache_mark_dirty(amx->regmap);
return 0;
}
static int __maybe_unused tegra210_amx_runtime_resume(struct device *dev)
{
struct tegra210_amx *amx = dev_get_drvdata(dev);
regcache_cache_only(amx->regmap, false);
regcache_sync(amx->regmap);
regmap_update_bits(amx->regmap,
TEGRA210_AMX_CTRL,
TEGRA210_AMX_CTRL_RX_DEP_MASK,
TEGRA210_AMX_WAIT_ON_ANY << TEGRA210_AMX_CTRL_RX_DEP_SHIFT);
tegra210_amx_write_map_ram(amx);
return 0;
}
static int tegra210_amx_set_audio_cif(struct snd_soc_dai *dai,
struct snd_pcm_hw_params *params,
unsigned int reg)
{
struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
int channels, audio_bits;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
audio_bits = TEGRA_ACIF_BITS_8;
break;
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = audio_bits;
tegra_set_cif(amx->regmap, reg, &cif_conf);
return 0;
}
static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
if (amx->soc_data->auto_disable) {
regmap_write(amx->regmap,
AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD),
TEGRA194_MAX_FRAME_IDLE_COUNT);
regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1);
}
return tegra210_amx_set_audio_cif(dai, params,
AMX_CH_REG(dai->id, TEGRA210_AMX_RX1_CIF_CTRL));
}
static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
return tegra210_amx_set_audio_cif(dai, params,
TEGRA210_AMX_TX_CIF_CTRL);
}
static int tegra210_amx_get_byte_map(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
unsigned char *bytes_map = (unsigned char *)&amx->map;
int reg = mc->reg;
int enabled;
if (reg > 31)
enabled = amx->byte_mask[1] & (1 << (reg - 32));
else
enabled = amx->byte_mask[0] & (1 << reg);
/*
* TODO: Simplify this logic to just return from bytes_map[]
*
* Presently below is required since bytes_map[] is
* tightly packed and cannot store the control value of 256.
* Byte mask state is used to know if 256 needs to be returned.
* Note that for control value of 256, the put() call stores 0
* in the bytes_map[] and disables the corresponding bit in
* byte_mask[].
*/
if (enabled)
ucontrol->value.integer.value[0] = bytes_map[reg];
else
ucontrol->value.integer.value[0] = 256;
return 0;
}
static int tegra210_amx_put_byte_map(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
unsigned char *bytes_map = (unsigned char *)&amx->map;
int reg = mc->reg;
int value = ucontrol->value.integer.value[0];
unsigned int mask_val = amx->byte_mask[reg / 32];
if (value >= 0 && value <= 255)
mask_val |= (1 << (reg % 32));
else
mask_val &= ~(1 << (reg % 32));
if (mask_val == amx->byte_mask[reg / 32])
return 0;
/* Update byte map and slot */
bytes_map[reg] = value % 256;
amx->byte_mask[reg / 32] = mask_val;
return 1;
}
static const struct snd_soc_dai_ops tegra210_amx_out_dai_ops = {
.hw_params = tegra210_amx_out_hw_params,
.startup = tegra210_amx_startup,
};
static const struct snd_soc_dai_ops tegra210_amx_in_dai_ops = {
.hw_params = tegra210_amx_in_hw_params,
};
#define IN_DAI(id) \
{ \
.name = "AMX-RX-CIF" #id, \
.playback = { \
.stream_name = "RX" #id "-CIF-Playback",\
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "RX" #id "-CIF-Capture", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra210_amx_in_dai_ops, \
}
#define OUT_DAI \
{ \
.name = "AMX-TX-CIF", \
.playback = { \
.stream_name = "TX-CIF-Playback", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "TX-CIF-Capture", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra210_amx_out_dai_ops, \
}
static struct snd_soc_dai_driver tegra210_amx_dais[] = {
IN_DAI(1),
IN_DAI(2),
IN_DAI(3),
IN_DAI(4),
OUT_DAI,
};
static const struct snd_soc_dapm_widget tegra210_amx_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, TEGRA210_AMX_CTRL, 0, 0),
SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, TEGRA210_AMX_CTRL, 1, 0),
SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, TEGRA210_AMX_CTRL, 2, 0),
SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, TEGRA210_AMX_CTRL, 3, 0),
SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_AMX_ENABLE,
TEGRA210_AMX_ENABLE_SHIFT, 0),
};
#define STREAM_ROUTES(id, sname) \
{ "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
{ "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname },\
{ "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
{ "TX", NULL, "RX" #id }, \
{ "TX-CIF-" sname, NULL, "TX" }, \
{ "XBAR-" sname, NULL, "TX-CIF-" sname }, \
{ "XBAR-RX", NULL, "XBAR-" sname }
#define AMX_ROUTES(id) \
STREAM_ROUTES(id, "Playback"), \
STREAM_ROUTES(id, "Capture")
static const struct snd_soc_dapm_route tegra210_amx_routes[] = {
AMX_ROUTES(1),
AMX_ROUTES(2),
AMX_ROUTES(3),
AMX_ROUTES(4),
};
#define TEGRA210_AMX_BYTE_MAP_CTRL(reg) \
SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \
tegra210_amx_get_byte_map, \
tegra210_amx_put_byte_map)
static struct snd_kcontrol_new tegra210_amx_controls[] = {
TEGRA210_AMX_BYTE_MAP_CTRL(0),
TEGRA210_AMX_BYTE_MAP_CTRL(1),
TEGRA210_AMX_BYTE_MAP_CTRL(2),
TEGRA210_AMX_BYTE_MAP_CTRL(3),
TEGRA210_AMX_BYTE_MAP_CTRL(4),
TEGRA210_AMX_BYTE_MAP_CTRL(5),
TEGRA210_AMX_BYTE_MAP_CTRL(6),
TEGRA210_AMX_BYTE_MAP_CTRL(7),
TEGRA210_AMX_BYTE_MAP_CTRL(8),
TEGRA210_AMX_BYTE_MAP_CTRL(9),
TEGRA210_AMX_BYTE_MAP_CTRL(10),
TEGRA210_AMX_BYTE_MAP_CTRL(11),
TEGRA210_AMX_BYTE_MAP_CTRL(12),
TEGRA210_AMX_BYTE_MAP_CTRL(13),
TEGRA210_AMX_BYTE_MAP_CTRL(14),
TEGRA210_AMX_BYTE_MAP_CTRL(15),
TEGRA210_AMX_BYTE_MAP_CTRL(16),
TEGRA210_AMX_BYTE_MAP_CTRL(17),
TEGRA210_AMX_BYTE_MAP_CTRL(18),
TEGRA210_AMX_BYTE_MAP_CTRL(19),
TEGRA210_AMX_BYTE_MAP_CTRL(20),
TEGRA210_AMX_BYTE_MAP_CTRL(21),
TEGRA210_AMX_BYTE_MAP_CTRL(22),
TEGRA210_AMX_BYTE_MAP_CTRL(23),
TEGRA210_AMX_BYTE_MAP_CTRL(24),
TEGRA210_AMX_BYTE_MAP_CTRL(25),
TEGRA210_AMX_BYTE_MAP_CTRL(26),
TEGRA210_AMX_BYTE_MAP_CTRL(27),
TEGRA210_AMX_BYTE_MAP_CTRL(28),
TEGRA210_AMX_BYTE_MAP_CTRL(29),
TEGRA210_AMX_BYTE_MAP_CTRL(30),
TEGRA210_AMX_BYTE_MAP_CTRL(31),
TEGRA210_AMX_BYTE_MAP_CTRL(32),
TEGRA210_AMX_BYTE_MAP_CTRL(33),
TEGRA210_AMX_BYTE_MAP_CTRL(34),
TEGRA210_AMX_BYTE_MAP_CTRL(35),
TEGRA210_AMX_BYTE_MAP_CTRL(36),
TEGRA210_AMX_BYTE_MAP_CTRL(37),
TEGRA210_AMX_BYTE_MAP_CTRL(38),
TEGRA210_AMX_BYTE_MAP_CTRL(39),
TEGRA210_AMX_BYTE_MAP_CTRL(40),
TEGRA210_AMX_BYTE_MAP_CTRL(41),
TEGRA210_AMX_BYTE_MAP_CTRL(42),
TEGRA210_AMX_BYTE_MAP_CTRL(43),
TEGRA210_AMX_BYTE_MAP_CTRL(44),
TEGRA210_AMX_BYTE_MAP_CTRL(45),
TEGRA210_AMX_BYTE_MAP_CTRL(46),
TEGRA210_AMX_BYTE_MAP_CTRL(47),
TEGRA210_AMX_BYTE_MAP_CTRL(48),
TEGRA210_AMX_BYTE_MAP_CTRL(49),
TEGRA210_AMX_BYTE_MAP_CTRL(50),
TEGRA210_AMX_BYTE_MAP_CTRL(51),
TEGRA210_AMX_BYTE_MAP_CTRL(52),
TEGRA210_AMX_BYTE_MAP_CTRL(53),
TEGRA210_AMX_BYTE_MAP_CTRL(54),
TEGRA210_AMX_BYTE_MAP_CTRL(55),
TEGRA210_AMX_BYTE_MAP_CTRL(56),
TEGRA210_AMX_BYTE_MAP_CTRL(57),
TEGRA210_AMX_BYTE_MAP_CTRL(58),
TEGRA210_AMX_BYTE_MAP_CTRL(59),
TEGRA210_AMX_BYTE_MAP_CTRL(60),
TEGRA210_AMX_BYTE_MAP_CTRL(61),
TEGRA210_AMX_BYTE_MAP_CTRL(62),
TEGRA210_AMX_BYTE_MAP_CTRL(63),
};
static const struct snd_soc_component_driver tegra210_amx_cmpnt = {
.dapm_widgets = tegra210_amx_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_amx_widgets),
.dapm_routes = tegra210_amx_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_amx_routes),
.controls = tegra210_amx_controls,
.num_controls = ARRAY_SIZE(tegra210_amx_controls),
};
static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL:
case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG:
case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA:
case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra194_amx_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
return true;
default:
return tegra210_amx_wr_reg(dev, reg);
}
}
static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra194_amx_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
return true;
default:
return tegra210_amx_rd_reg(dev, reg);
}
}
static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_AMX_RX_STATUS:
case TEGRA210_AMX_RX_INT_STATUS:
case TEGRA210_AMX_RX_INT_SET:
case TEGRA210_AMX_TX_STATUS:
case TEGRA210_AMX_TX_INT_STATUS:
case TEGRA210_AMX_TX_INT_SET:
case TEGRA210_AMX_SOFT_RESET:
case TEGRA210_AMX_STATUS:
case TEGRA210_AMX_INT_STATUS:
case TEGRA210_AMX_CFG_RAM_CTRL:
case TEGRA210_AMX_CFG_RAM_DATA:
return true;
default:
break;
}
return false;
}
static const struct regmap_config tegra210_amx_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_AMX_CFG_RAM_DATA,
.writeable_reg = tegra210_amx_wr_reg,
.readable_reg = tegra210_amx_rd_reg,
.volatile_reg = tegra210_amx_volatile_reg,
.reg_defaults = tegra210_amx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config tegra194_amx_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA194_AMX_RX4_LAST_FRAME_PERIOD,
.writeable_reg = tegra194_amx_wr_reg,
.readable_reg = tegra194_amx_rd_reg,
.volatile_reg = tegra210_amx_volatile_reg,
.reg_defaults = tegra210_amx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct tegra210_amx_soc_data soc_data_tegra210 = {
.regmap_conf = &tegra210_amx_regmap_config,
};
static const struct tegra210_amx_soc_data soc_data_tegra194 = {
.regmap_conf = &tegra194_amx_regmap_config,
.auto_disable = true,
};
static const struct of_device_id tegra210_amx_of_match[] = {
{ .compatible = "nvidia,tegra210-amx", .data = &soc_data_tegra210 },
{ .compatible = "nvidia,tegra194-amx", .data = &soc_data_tegra194 },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_amx_of_match);
static int tegra210_amx_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_amx *amx;
void __iomem *regs;
int err;
const struct of_device_id *match;
struct tegra210_amx_soc_data *soc_data;
match = of_match_device(tegra210_amx_of_match, dev);
soc_data = (struct tegra210_amx_soc_data *)match->data;
amx = devm_kzalloc(dev, sizeof(*amx), GFP_KERNEL);
if (!amx)
return -ENOMEM;
amx->soc_data = soc_data;
dev_set_drvdata(dev, amx);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
amx->regmap = devm_regmap_init_mmio(dev, regs,
soc_data->regmap_conf);
if (IS_ERR(amx->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(amx->regmap);
}
regcache_cache_only(amx->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt,
tegra210_amx_dais,
ARRAY_SIZE(tegra210_amx_dais));
if (err) {
dev_err(dev, "can't register AMX component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra210_amx_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_amx_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_amx_runtime_suspend,
tegra210_amx_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra210_amx_driver = {
.driver = {
.name = "tegra210-amx",
.of_match_table = tegra210_amx_of_match,
.pm = &tegra210_amx_pm_ops,
},
.probe = tegra210_amx_platform_probe,
.remove_new = tegra210_amx_platform_remove,
};
module_platform_driver(tegra210_amx_driver);
MODULE_AUTHOR("Songhee Baek <[email protected]>");
MODULE_DESCRIPTION("Tegra210 AMX ASoC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_amx.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra186_asrc.c - Tegra186 ASRC driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra186_asrc.h"
#include "tegra_cif.h"
#define ASRC_STREAM_SOURCE_SELECT(id) \
(TEGRA186_ASRC_CFG + ((id) * TEGRA186_ASRC_STREAM_STRIDE))
#define ASRC_STREAM_REG(reg, id) ((reg) + ((id) * TEGRA186_ASRC_STREAM_STRIDE))
#define ASRC_STREAM_REG_DEFAULTS(id) \
{ ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id), \
(((id) + 1) << 4) }, \
{ ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id), \
0x1 }, \
{ ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id), \
0x0 }, \
{ ASRC_STREAM_REG(TEGRA186_ASRC_MUTE_UNMUTE_DURATION, id), \
0x400 }, \
{ ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, id), \
0x7500 }, \
{ ASRC_STREAM_REG(TEGRA186_ASRC_TX_CIF_CTRL, id), \
0x7500 }
static const struct reg_default tegra186_asrc_reg_defaults[] = {
ASRC_STREAM_REG_DEFAULTS(0),
ASRC_STREAM_REG_DEFAULTS(1),
ASRC_STREAM_REG_DEFAULTS(2),
ASRC_STREAM_REG_DEFAULTS(3),
ASRC_STREAM_REG_DEFAULTS(4),
ASRC_STREAM_REG_DEFAULTS(5),
{ TEGRA186_ASRC_GLOBAL_ENB, 0},
{ TEGRA186_ASRC_GLOBAL_SOFT_RESET, 0},
{ TEGRA186_ASRC_GLOBAL_CG, 0x1 },
{ TEGRA186_ASRC_GLOBAL_CFG, 0x0 },
{ TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, 0},
{ TEGRA186_ASRC_GLOBAL_SCRATCH_CFG, 0x0c207980 },
{ TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL, 0x00115500 },
{ TEGRA186_ASRC_GLOBAL_INT_MASK, 0x0},
{ TEGRA186_ASRC_GLOBAL_INT_SET, 0x0},
{ TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x0},
{ TEGRA186_ASRC_GLOBAL_APR_CTRL, 0x0},
{ TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL, 0x0},
{ TEGRA186_ASRC_GLOBAL_DISARM_APR, 0x0},
{ TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL, 0x0},
{ TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS, 0x0},
{ TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL, 0x0},
{ TEGRA186_ASRC_CYA, 0x0},
};
static void tegra186_asrc_lock_stream(struct tegra186_asrc *asrc,
unsigned int id)
{
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_LOCK_STATUS,
id),
1);
}
static int __maybe_unused tegra186_asrc_runtime_suspend(struct device *dev)
{
struct tegra186_asrc *asrc = dev_get_drvdata(dev);
regcache_cache_only(asrc->regmap, true);
regcache_mark_dirty(asrc->regmap);
return 0;
}
static int __maybe_unused tegra186_asrc_runtime_resume(struct device *dev)
{
struct tegra186_asrc *asrc = dev_get_drvdata(dev);
int id;
regcache_cache_only(asrc->regmap, false);
/*
* Below sequence is recommended after a runtime PM cycle.
* This otherwise leads to transfer failures. The cache
* sync is done after this to restore other settings.
*/
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR,
TEGRA186_ASRC_ARAM_START_ADDR);
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB,
TEGRA186_ASRC_GLOBAL_EN);
regcache_sync(asrc->regmap);
for (id = 0; id < TEGRA186_ASRC_STREAM_MAX; id++) {
if (asrc->lane[id].ratio_source !=
TEGRA186_ASRC_RATIO_SOURCE_SW)
continue;
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART,
id),
asrc->lane[id].int_part);
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART,
id),
asrc->lane[id].frac_part);
tegra186_asrc_lock_stream(asrc, id);
}
return 0;
}
static int tegra186_asrc_set_audio_cif(struct tegra186_asrc *asrc,
struct snd_pcm_hw_params *params,
unsigned int reg)
{
int channels, audio_bits;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = TEGRA_ACIF_BITS_24;
tegra_set_cif(asrc->regmap, reg, &cif_conf);
return 0;
}
static int tegra186_asrc_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);
int ret, id = dai->id;
/* Set input threshold */
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, dai->id),
asrc->lane[id].input_thresh);
ret = tegra186_asrc_set_audio_cif(asrc, params,
ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, dai->id));
if (ret) {
dev_err(dev, "Can't set ASRC RX%d CIF: %d\n", dai->id, ret);
return ret;
}
return ret;
}
static int tegra186_asrc_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);
int ret, id = dai->id - 7;
/* Set output threshold */
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, id),
asrc->lane[id].output_thresh);
ret = tegra186_asrc_set_audio_cif(asrc, params,
ASRC_STREAM_REG(TEGRA186_ASRC_TX_CIF_CTRL, id));
if (ret) {
dev_err(dev, "Can't set ASRC TX%d CIF: %d\n", id, ret);
return ret;
}
/* Set ENABLE_HW_RATIO_COMP */
if (asrc->lane[id].hwcomp_disable) {
regmap_update_bits(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),
TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK,
TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE);
} else {
regmap_update_bits(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),
TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK,
TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE);
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_COMP, id),
TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE);
}
/* Set lock */
regmap_update_bits(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),
1, asrc->lane[id].ratio_source);
if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) {
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id),
asrc->lane[id].int_part);
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id),
asrc->lane[id].frac_part);
tegra186_asrc_lock_stream(asrc, id);
}
return ret;
}
static int tegra186_asrc_get_ratio_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *asrc_private =
(struct soc_enum *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source;
return 0;
}
static int tegra186_asrc_put_ratio_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *asrc_private =
(struct soc_enum *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
bool change = false;
asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0];
regmap_update_bits_check(asrc->regmap, asrc_private->reg,
TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK,
asrc->lane[id].ratio_source,
&change);
return change ? 1 : 0;
}
static int tegra186_asrc_get_ratio_int(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
regmap_read(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id),
&asrc->lane[id].int_part);
ucontrol->value.integer.value[0] = asrc->lane[id].int_part;
return 0;
}
static int tegra186_asrc_put_ratio_int(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
bool change = false;
if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {
dev_err(cmpnt->dev,
"Lane %d ratio source is ARAD, invalid SW update\n",
id);
return -EINVAL;
}
asrc->lane[id].int_part = ucontrol->value.integer.value[0];
regmap_update_bits_check(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART,
id),
TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK,
asrc->lane[id].int_part, &change);
tegra186_asrc_lock_stream(asrc, id);
return change ? 1 : 0;
}
static int tegra186_asrc_get_ratio_frac(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mreg_control *asrc_private =
(struct soc_mreg_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE;
regmap_read(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id),
&asrc->lane[id].frac_part);
ucontrol->value.integer.value[0] = asrc->lane[id].frac_part;
return 0;
}
static int tegra186_asrc_put_ratio_frac(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mreg_control *asrc_private =
(struct soc_mreg_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE;
bool change = false;
if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {
dev_err(cmpnt->dev,
"Lane %d ratio source is ARAD, invalid SW update\n",
id);
return -EINVAL;
}
asrc->lane[id].frac_part = ucontrol->value.integer.value[0];
regmap_update_bits_check(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART,
id),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
asrc->lane[id].frac_part, &change);
tegra186_asrc_lock_stream(asrc, id);
return change ? 1 : 0;
}
static int tegra186_asrc_get_hwcomp_disable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable;
return 0;
}
static int tegra186_asrc_put_hwcomp_disable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
int value = ucontrol->value.integer.value[0];
if (value == asrc->lane[id].hwcomp_disable)
return 0;
asrc->lane[id].hwcomp_disable = value;
return 1;
}
static int tegra186_asrc_get_input_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3);
return 0;
}
static int tegra186_asrc_put_input_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
int value = (asrc->lane[id].input_thresh & ~(0x3)) |
ucontrol->value.integer.value[0];
if (value == asrc->lane[id].input_thresh)
return 0;
asrc->lane[id].input_thresh = value;
return 1;
}
static int tegra186_asrc_get_output_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3);
return 0;
}
static int tegra186_asrc_put_output_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *asrc_private =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
int value = (asrc->lane[id].output_thresh & ~(0x3)) |
ucontrol->value.integer.value[0];
if (value == asrc->lane[id].output_thresh)
return 0;
asrc->lane[id].output_thresh = value;
return 1;
}
static int tegra186_asrc_widget_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct tegra186_asrc *asrc = dev_get_drvdata(cmpnt->dev);
unsigned int id =
(w->reg - TEGRA186_ASRC_ENABLE) / TEGRA186_ASRC_STREAM_STRIDE;
regmap_write(asrc->regmap,
ASRC_STREAM_REG(TEGRA186_ASRC_SOFT_RESET, id),
0x1);
return 0;
}
static const struct snd_soc_dai_ops tegra186_asrc_in_dai_ops = {
.hw_params = tegra186_asrc_in_hw_params,
};
static const struct snd_soc_dai_ops tegra186_asrc_out_dai_ops = {
.hw_params = tegra186_asrc_out_hw_params,
};
#define IN_DAI(id) \
{ \
.name = "ASRC-RX-CIF"#id, \
.playback = { \
.stream_name = "RX" #id "-CIF-Playback",\
.channels_min = 1, \
.channels_max = 12, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "RX" #id "-CIF-Capture", \
.channels_min = 1, \
.channels_max = 12, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra186_asrc_in_dai_ops, \
}
#define OUT_DAI(id) \
{ \
.name = "ASRC-TX-CIF"#id, \
.playback = { \
.stream_name = "TX" #id "-CIF-Playback",\
.channels_min = 1, \
.channels_max = 12, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = "TX" #id "-CIF-Capture", \
.channels_min = 1, \
.channels_max = 12, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra186_asrc_out_dai_ops, \
}
static struct snd_soc_dai_driver tegra186_asrc_dais[] = {
/* ASRC Input */
IN_DAI(1),
IN_DAI(2),
IN_DAI(3),
IN_DAI(4),
IN_DAI(5),
IN_DAI(6),
IN_DAI(7),
/* ASRC Output */
OUT_DAI(1),
OUT_DAI(2),
OUT_DAI(3),
OUT_DAI(4),
OUT_DAI(5),
OUT_DAI(6),
};
static const struct snd_soc_dapm_widget tegra186_asrc_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX7", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT_E("TX1", NULL, 0,
ASRC_STREAM_REG(TEGRA186_ASRC_ENABLE, 0),
TEGRA186_ASRC_STREAM_EN_SHIFT, 0,
tegra186_asrc_widget_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("TX2", NULL, 0,
ASRC_STREAM_REG(TEGRA186_ASRC_ENABLE, 1),
TEGRA186_ASRC_STREAM_EN_SHIFT, 0,
tegra186_asrc_widget_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("TX3", NULL, 0,
ASRC_STREAM_REG(TEGRA186_ASRC_ENABLE, 2),
TEGRA186_ASRC_STREAM_EN_SHIFT, 0,
tegra186_asrc_widget_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("TX4", NULL, 0,
ASRC_STREAM_REG(TEGRA186_ASRC_ENABLE, 3),
TEGRA186_ASRC_STREAM_EN_SHIFT, 0,
tegra186_asrc_widget_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("TX5", NULL, 0,
ASRC_STREAM_REG(TEGRA186_ASRC_ENABLE, 4),
TEGRA186_ASRC_STREAM_EN_SHIFT, 0,
tegra186_asrc_widget_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT_E("TX6", NULL, 0,
ASRC_STREAM_REG(TEGRA186_ASRC_ENABLE, 5),
TEGRA186_ASRC_STREAM_EN_SHIFT, 0,
tegra186_asrc_widget_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SPK("Depacketizer", NULL),
};
#define ASRC_STREAM_ROUTE(id, sname) \
{ "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
{ "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname }, \
{ "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
{ "TX" #id, NULL, "RX" #id }, \
{ "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
{ "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
{ "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname },
#define ASRC_ROUTE(id) \
ASRC_STREAM_ROUTE(id, "Playback") \
ASRC_STREAM_ROUTE(id, "Capture")
#define ASRC_RATIO_ROUTE(sname) \
{ "RX7 XBAR-" sname, NULL, "RX7 XBAR-TX" }, \
{ "RX7-CIF-" sname, NULL, "RX7 XBAR-" sname }, \
{ "RX7", NULL, "RX7-CIF-" sname }, \
{ "Depacketizer", NULL, "RX7" },
static const struct snd_soc_dapm_route tegra186_asrc_routes[] = {
ASRC_ROUTE(1)
ASRC_ROUTE(2)
ASRC_ROUTE(3)
ASRC_ROUTE(4)
ASRC_ROUTE(5)
ASRC_ROUTE(6)
ASRC_RATIO_ROUTE("Playback")
ASRC_RATIO_ROUTE("Capture")
};
static const char * const tegra186_asrc_ratio_source_text[] = {
"ARAD",
"SW",
};
#define ASRC_SOURCE_DECL(name, id) \
static const struct soc_enum name = \
SOC_ENUM_SINGLE(ASRC_STREAM_SOURCE_SELECT(id), \
0, 2, tegra186_asrc_ratio_source_text)
ASRC_SOURCE_DECL(src_select1, 0);
ASRC_SOURCE_DECL(src_select2, 1);
ASRC_SOURCE_DECL(src_select3, 2);
ASRC_SOURCE_DECL(src_select4, 3);
ASRC_SOURCE_DECL(src_select5, 4);
ASRC_SOURCE_DECL(src_select6, 5);
#define SOC_SINGLE_EXT_FRAC(xname, xregbase, xmax, xget, xput) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = (xname), \
.info = snd_soc_info_xr_sx, \
.get = xget, \
.put = xput, \
\
.private_value = (unsigned long)&(struct soc_mreg_control) \
{ \
.regbase = xregbase, \
.regcount = 1, \
.nbits = 32, \
.invert = 0, \
.min = 0, \
.max = xmax \
} \
}
static const struct snd_kcontrol_new tegra186_asrc_controls[] = {
/* Controls for integer part of ratio */
SOC_SINGLE_EXT("Ratio1 Integer Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 0),
0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
tegra186_asrc_get_ratio_int,
tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio2 Integer Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 1),
0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
tegra186_asrc_get_ratio_int,
tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio3 Integer Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 2),
0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
tegra186_asrc_get_ratio_int,
tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio4 Integer Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 3),
0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
tegra186_asrc_get_ratio_int,
tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio5 Integer Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 4),
0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
tegra186_asrc_get_ratio_int,
tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio6 Integer Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 5),
0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
tegra186_asrc_get_ratio_int,
tegra186_asrc_put_ratio_int),
/* Controls for fractional part of ratio */
SOC_SINGLE_EXT_FRAC("Ratio1 Fractional Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 0),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac,
tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT_FRAC("Ratio2 Fractional Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 1),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac,
tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT_FRAC("Ratio3 Fractional Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 2),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac,
tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT_FRAC("Ratio4 Fractional Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 3),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac,
tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT_FRAC("Ratio5 Fractional Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 4),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac,
tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT_FRAC("Ratio6 Fractional Part",
ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, 5),
TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK,
tegra186_asrc_get_ratio_frac,
tegra186_asrc_put_ratio_frac),
/* Source of ratio provider */
SOC_ENUM_EXT("Ratio1 Source", src_select1,
tegra186_asrc_get_ratio_source,
tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio2 Source", src_select2,
tegra186_asrc_get_ratio_source,
tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio3 Source", src_select3,
tegra186_asrc_get_ratio_source,
tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio4 Source", src_select4,
tegra186_asrc_get_ratio_source,
tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio5 Source", src_select5,
tegra186_asrc_get_ratio_source,
tegra186_asrc_put_ratio_source),
SOC_ENUM_EXT("Ratio6 Source", src_select6,
tegra186_asrc_get_ratio_source,
tegra186_asrc_put_ratio_source),
/* Disable HW managed overflow/underflow issue at input and output */
SOC_SINGLE_EXT("Stream1 HW Component Disable",
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, 0), 0, 1, 0,
tegra186_asrc_get_hwcomp_disable,
tegra186_asrc_put_hwcomp_disable),
SOC_SINGLE_EXT("Stream2 HW Component Disable",
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, 1), 0, 1, 0,
tegra186_asrc_get_hwcomp_disable,
tegra186_asrc_put_hwcomp_disable),
SOC_SINGLE_EXT("Stream3 HW Component Disable",
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, 2), 0, 1, 0,
tegra186_asrc_get_hwcomp_disable,
tegra186_asrc_put_hwcomp_disable),
SOC_SINGLE_EXT("Stream4 HW Component Disable",
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, 3), 0, 1, 0,
tegra186_asrc_get_hwcomp_disable,
tegra186_asrc_put_hwcomp_disable),
SOC_SINGLE_EXT("Stream5 HW Component Disable",
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, 4), 0, 1, 0,
tegra186_asrc_get_hwcomp_disable,
tegra186_asrc_put_hwcomp_disable),
SOC_SINGLE_EXT("Stream6 HW Component Disable",
ASRC_STREAM_REG(TEGRA186_ASRC_CFG, 5), 0, 1, 0,
tegra186_asrc_get_hwcomp_disable,
tegra186_asrc_put_hwcomp_disable),
/* Input threshold for watermark fields */
SOC_SINGLE_EXT("Stream1 Input Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 0), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),
SOC_SINGLE_EXT("Stream2 Input Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 1), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),
SOC_SINGLE_EXT("Stream3 Input Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 2), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),
SOC_SINGLE_EXT("Stream4 Input Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 3), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),
SOC_SINGLE_EXT("Stream5 Input Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 4), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),
SOC_SINGLE_EXT("Stream6 Input Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 4), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),
/* Output threshold for watermark fields */
SOC_SINGLE_EXT("Stream1 Output Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, 0), 0, 3, 0,
tegra186_asrc_get_output_threshold,
tegra186_asrc_put_output_threshold),
SOC_SINGLE_EXT("Stream2 Output Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, 1), 0, 3, 0,
tegra186_asrc_get_output_threshold,
tegra186_asrc_put_output_threshold),
SOC_SINGLE_EXT("Stream3 Output Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, 2), 0, 3, 0,
tegra186_asrc_get_output_threshold,
tegra186_asrc_put_output_threshold),
SOC_SINGLE_EXT("Stream4 Output Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, 3), 0, 3, 0,
tegra186_asrc_get_output_threshold,
tegra186_asrc_put_output_threshold),
SOC_SINGLE_EXT("Stream5 Output Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, 4), 0, 3, 0,
tegra186_asrc_get_output_threshold,
tegra186_asrc_put_output_threshold),
SOC_SINGLE_EXT("Stream6 Output Threshold",
ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, 5), 0, 3, 0,
tegra186_asrc_get_output_threshold,
tegra186_asrc_put_output_threshold),
};
static const struct snd_soc_component_driver tegra186_asrc_cmpnt = {
.dapm_widgets = tegra186_asrc_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra186_asrc_widgets),
.dapm_routes = tegra186_asrc_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_asrc_routes),
.controls = tegra186_asrc_controls,
.num_controls = ARRAY_SIZE(tegra186_asrc_controls),
};
static bool tegra186_asrc_wr_reg(struct device *dev, unsigned int reg)
{
if (reg < TEGRA186_ASRC_STREAM_LIMIT)
reg %= TEGRA186_ASRC_STREAM_STRIDE;
switch (reg) {
case TEGRA186_ASRC_CFG ... TEGRA186_ASRC_RATIO_COMP:
case TEGRA186_ASRC_RX_CIF_CTRL:
case TEGRA186_ASRC_TX_CIF_CTRL:
case TEGRA186_ASRC_ENABLE:
case TEGRA186_ASRC_SOFT_RESET:
case TEGRA186_ASRC_GLOBAL_ENB ... TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL:
case TEGRA186_ASRC_GLOBAL_INT_MASK ... TEGRA186_ASRC_GLOBAL_INT_CLEAR:
case TEGRA186_ASRC_GLOBAL_APR_CTRL ... TEGRA186_ASRC_CYA:
return true;
default:
return false;
}
}
static bool tegra186_asrc_rd_reg(struct device *dev, unsigned int reg)
{
if (reg < TEGRA186_ASRC_STREAM_LIMIT)
reg %= TEGRA186_ASRC_STREAM_STRIDE;
if (tegra186_asrc_wr_reg(dev, reg))
return true;
switch (reg) {
case TEGRA186_ASRC_RX_STATUS:
case TEGRA186_ASRC_TX_STATUS:
case TEGRA186_ASRC_STATUS ... TEGRA186_ASRC_OUTSAMPLEBUF_CFG:
case TEGRA186_ASRC_RATIO_UPD_RX_STATUS:
case TEGRA186_ASRC_GLOBAL_STATUS ... TEGRA186_ASRC_GLOBAL_INT_STATUS:
case TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG:
return true;
default:
return false;
}
}
static bool tegra186_asrc_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg < TEGRA186_ASRC_STREAM_LIMIT)
reg %= TEGRA186_ASRC_STREAM_STRIDE;
switch (reg) {
case TEGRA186_ASRC_RX_STATUS:
case TEGRA186_ASRC_TX_STATUS:
case TEGRA186_ASRC_SOFT_RESET:
case TEGRA186_ASRC_RATIO_INT_PART:
case TEGRA186_ASRC_RATIO_FRAC_PART:
case TEGRA186_ASRC_STATUS:
case TEGRA186_ASRC_RATIO_LOCK_STATUS:
case TEGRA186_ASRC_RATIO_UPD_RX_STATUS:
case TEGRA186_ASRC_GLOBAL_SOFT_RESET:
case TEGRA186_ASRC_GLOBAL_STATUS:
case TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS:
case TEGRA186_ASRC_GLOBAL_INT_STATUS:
case TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG:
return true;
default:
return false;
}
}
static const struct regmap_config tegra186_asrc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA186_ASRC_CYA,
.writeable_reg = tegra186_asrc_wr_reg,
.readable_reg = tegra186_asrc_rd_reg,
.volatile_reg = tegra186_asrc_volatile_reg,
.reg_defaults = tegra186_asrc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra186_asrc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra186_asrc_of_match[] = {
{ .compatible = "nvidia,tegra186-asrc" },
{},
};
MODULE_DEVICE_TABLE(of, tegra186_asrc_of_match);
static int tegra186_asrc_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra186_asrc *asrc;
void __iomem *regs;
unsigned int i;
int err;
asrc = devm_kzalloc(dev, sizeof(*asrc), GFP_KERNEL);
if (!asrc)
return -ENOMEM;
dev_set_drvdata(dev, asrc);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
asrc->regmap = devm_regmap_init_mmio(dev, regs,
&tegra186_asrc_regmap_config);
if (IS_ERR(asrc->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(asrc->regmap);
}
regcache_cache_only(asrc->regmap, true);
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG,
TEGRA186_ASRC_GLOBAL_CFG_FRAC_32BIT_PRECISION);
/* Initialize default output srate */
for (i = 0; i < TEGRA186_ASRC_STREAM_MAX; i++) {
asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW;
asrc->lane[i].int_part = 1;
asrc->lane[i].frac_part = 0;
asrc->lane[i].hwcomp_disable = 0;
asrc->lane[i].input_thresh =
TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG;
asrc->lane[i].output_thresh =
TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG;
}
err = devm_snd_soc_register_component(dev, &tegra186_asrc_cmpnt,
tegra186_asrc_dais,
ARRAY_SIZE(tegra186_asrc_dais));
if (err) {
dev_err(dev, "can't register ASRC component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra186_asrc_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra186_asrc_pm_ops = {
SET_RUNTIME_PM_OPS(tegra186_asrc_runtime_suspend,
tegra186_asrc_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra186_asrc_driver = {
.driver = {
.name = "tegra186-asrc",
.of_match_table = tegra186_asrc_of_match,
.pm = &tegra186_asrc_pm_ops,
},
.probe = tegra186_asrc_platform_probe,
.remove_new = tegra186_asrc_platform_remove,
};
module_platform_driver(tegra186_asrc_driver)
MODULE_AUTHOR("Junghyun Kim <[email protected]>");
MODULE_DESCRIPTION("Tegra186 ASRC ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/tegra/tegra186_asrc.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_admaif.c - Tegra ADMAIF driver
//
// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_admaif.h"
#include "tegra_cif.h"
#include "tegra_pcm.h"
#define CH_REG(offset, reg, id) \
((offset) + (reg) + (TEGRA_ADMAIF_CHANNEL_REG_STRIDE * (id)))
#define CH_TX_REG(reg, id) CH_REG(admaif->soc_data->tx_base, reg, id)
#define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base) \
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_INT_MASK, id), 0x00000001 }, \
{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), 0x00007700 }, \
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_INT_MASK, id), 0x00000001 }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), 0x00007700 }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_FIFO_CTRL, id), tx_ctrl }
#define ADMAIF_REG_DEFAULTS(id, chip) \
REG_DEFAULTS((id) - 1, \
chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX_BASE, \
chip ## _ADMAIF_RX_BASE)
static const struct reg_default tegra186_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA186),
ADMAIF_REG_DEFAULTS(2, TEGRA186),
ADMAIF_REG_DEFAULTS(3, TEGRA186),
ADMAIF_REG_DEFAULTS(4, TEGRA186),
ADMAIF_REG_DEFAULTS(5, TEGRA186),
ADMAIF_REG_DEFAULTS(6, TEGRA186),
ADMAIF_REG_DEFAULTS(7, TEGRA186),
ADMAIF_REG_DEFAULTS(8, TEGRA186),
ADMAIF_REG_DEFAULTS(9, TEGRA186),
ADMAIF_REG_DEFAULTS(10, TEGRA186),
ADMAIF_REG_DEFAULTS(11, TEGRA186),
ADMAIF_REG_DEFAULTS(12, TEGRA186),
ADMAIF_REG_DEFAULTS(13, TEGRA186),
ADMAIF_REG_DEFAULTS(14, TEGRA186),
ADMAIF_REG_DEFAULTS(15, TEGRA186),
ADMAIF_REG_DEFAULTS(16, TEGRA186),
ADMAIF_REG_DEFAULTS(17, TEGRA186),
ADMAIF_REG_DEFAULTS(18, TEGRA186),
ADMAIF_REG_DEFAULTS(19, TEGRA186),
ADMAIF_REG_DEFAULTS(20, TEGRA186)
};
static const struct reg_default tegra210_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA210),
ADMAIF_REG_DEFAULTS(2, TEGRA210),
ADMAIF_REG_DEFAULTS(3, TEGRA210),
ADMAIF_REG_DEFAULTS(4, TEGRA210),
ADMAIF_REG_DEFAULTS(5, TEGRA210),
ADMAIF_REG_DEFAULTS(6, TEGRA210),
ADMAIF_REG_DEFAULTS(7, TEGRA210),
ADMAIF_REG_DEFAULTS(8, TEGRA210),
ADMAIF_REG_DEFAULTS(9, TEGRA210),
ADMAIF_REG_DEFAULTS(10, TEGRA210)
};
static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)
{
struct tegra_admaif *admaif = dev_get_drvdata(dev);
unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
unsigned int num_ch = admaif->soc_data->num_ch;
unsigned int rx_base = admaif->soc_data->rx_base;
unsigned int tx_base = admaif->soc_data->tx_base;
unsigned int global_base = admaif->soc_data->global_base;
unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
unsigned int rx_max = rx_base + (num_ch * ch_stride);
unsigned int tx_max = tx_base + (num_ch * ch_stride);
if ((reg >= rx_base) && (reg < rx_max)) {
reg = (reg - rx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_RX_ENABLE) ||
(reg == TEGRA_ADMAIF_RX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_RX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CH_ACIF_RX_CTRL))
return true;
} else if ((reg >= tx_base) && (reg < tx_max)) {
reg = (reg - tx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_TX_ENABLE) ||
(reg == TEGRA_ADMAIF_TX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_TX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CH_ACIF_TX_CTRL))
return true;
} else if ((reg >= global_base) && (reg < reg_max)) {
if (reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE))
return true;
}
return false;
}
static bool tegra_admaif_rd_reg(struct device *dev, unsigned int reg)
{
struct tegra_admaif *admaif = dev_get_drvdata(dev);
unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
unsigned int num_ch = admaif->soc_data->num_ch;
unsigned int rx_base = admaif->soc_data->rx_base;
unsigned int tx_base = admaif->soc_data->tx_base;
unsigned int global_base = admaif->soc_data->global_base;
unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
unsigned int rx_max = rx_base + (num_ch * ch_stride);
unsigned int tx_max = tx_base + (num_ch * ch_stride);
if ((reg >= rx_base) && (reg < rx_max)) {
reg = (reg - rx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_RX_ENABLE) ||
(reg == TEGRA_ADMAIF_RX_STATUS) ||
(reg == TEGRA_ADMAIF_RX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_RX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_RX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CH_ACIF_RX_CTRL))
return true;
} else if ((reg >= tx_base) && (reg < tx_max)) {
reg = (reg - tx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_TX_ENABLE) ||
(reg == TEGRA_ADMAIF_TX_STATUS) ||
(reg == TEGRA_ADMAIF_TX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_TX_FIFO_CTRL) ||
(reg == TEGRA_ADMAIF_TX_SOFT_RESET) ||
(reg == TEGRA_ADMAIF_CH_ACIF_TX_CTRL))
return true;
} else if ((reg >= global_base) && (reg < reg_max)) {
if ((reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE)) ||
(reg == (global_base + TEGRA_ADMAIF_GLOBAL_CG_0)) ||
(reg == (global_base + TEGRA_ADMAIF_GLOBAL_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS)))
return true;
}
return false;
}
static bool tegra_admaif_volatile_reg(struct device *dev, unsigned int reg)
{
struct tegra_admaif *admaif = dev_get_drvdata(dev);
unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
unsigned int num_ch = admaif->soc_data->num_ch;
unsigned int rx_base = admaif->soc_data->rx_base;
unsigned int tx_base = admaif->soc_data->tx_base;
unsigned int global_base = admaif->soc_data->global_base;
unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
unsigned int rx_max = rx_base + (num_ch * ch_stride);
unsigned int tx_max = tx_base + (num_ch * ch_stride);
if ((reg >= rx_base) && (reg < rx_max)) {
reg = (reg - rx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_RX_ENABLE) ||
(reg == TEGRA_ADMAIF_RX_STATUS) ||
(reg == TEGRA_ADMAIF_RX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_RX_SOFT_RESET))
return true;
} else if ((reg >= tx_base) && (reg < tx_max)) {
reg = (reg - tx_base) % ch_stride;
if ((reg == TEGRA_ADMAIF_TX_ENABLE) ||
(reg == TEGRA_ADMAIF_TX_STATUS) ||
(reg == TEGRA_ADMAIF_TX_INT_STATUS) ||
(reg == TEGRA_ADMAIF_TX_SOFT_RESET))
return true;
} else if ((reg >= global_base) && (reg < reg_max)) {
if ((reg == (global_base + TEGRA_ADMAIF_GLOBAL_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS)) ||
(reg == (global_base +
TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS)))
return true;
}
return false;
}
static const struct regmap_config tegra210_admaif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_ADMAIF_LAST_REG,
.writeable_reg = tegra_admaif_wr_reg,
.readable_reg = tegra_admaif_rd_reg,
.volatile_reg = tegra_admaif_volatile_reg,
.reg_defaults = tegra210_admaif_reg_defaults,
.num_reg_defaults = TEGRA210_ADMAIF_CHANNEL_COUNT * 6 + 1,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config tegra186_admaif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA186_ADMAIF_LAST_REG,
.writeable_reg = tegra_admaif_wr_reg,
.readable_reg = tegra_admaif_rd_reg,
.volatile_reg = tegra_admaif_volatile_reg,
.reg_defaults = tegra186_admaif_reg_defaults,
.num_reg_defaults = TEGRA186_ADMAIF_CHANNEL_COUNT * 6 + 1,
.cache_type = REGCACHE_FLAT,
};
static int __maybe_unused tegra_admaif_runtime_suspend(struct device *dev)
{
struct tegra_admaif *admaif = dev_get_drvdata(dev);
regcache_cache_only(admaif->regmap, true);
regcache_mark_dirty(admaif->regmap);
return 0;
}
static int __maybe_unused tegra_admaif_runtime_resume(struct device *dev)
{
struct tegra_admaif *admaif = dev_get_drvdata(dev);
regcache_cache_only(admaif->regmap, false);
regcache_sync(admaif->regmap);
return 0;
}
static int tegra_admaif_set_pack_mode(struct regmap *map, unsigned int reg,
int valid_bit)
{
switch (valid_bit) {
case DATA_8BIT:
regmap_update_bits(map, reg, PACK8_EN_MASK, PACK8_EN);
regmap_update_bits(map, reg, PACK16_EN_MASK, 0);
break;
case DATA_16BIT:
regmap_update_bits(map, reg, PACK16_EN_MASK, PACK16_EN);
regmap_update_bits(map, reg, PACK8_EN_MASK, 0);
break;
case DATA_32BIT:
regmap_update_bits(map, reg, PACK16_EN_MASK, 0);
regmap_update_bits(map, reg, PACK8_EN_MASK, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int tegra_admaif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
struct tegra_cif_conf cif_conf;
unsigned int reg, path;
int valid_bit, channels;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
cif_conf.client_bits = TEGRA_ACIF_BITS_8;
valid_bit = DATA_8BIT;
break;
case SNDRV_PCM_FORMAT_S16_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
cif_conf.client_bits = TEGRA_ACIF_BITS_16;
valid_bit = DATA_16BIT;
break;
case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
cif_conf.client_bits = TEGRA_ACIF_BITS_32;
valid_bit = DATA_32BIT;
break;
default:
dev_err(dev, "unsupported format!\n");
return -EOPNOTSUPP;
}
channels = params_channels(params);
cif_conf.client_ch = channels;
cif_conf.audio_ch = channels;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
path = ADMAIF_TX_PATH;
reg = CH_TX_REG(TEGRA_ADMAIF_CH_ACIF_TX_CTRL, dai->id);
} else {
path = ADMAIF_RX_PATH;
reg = CH_RX_REG(TEGRA_ADMAIF_CH_ACIF_RX_CTRL, dai->id);
}
cif_conf.mono_conv = admaif->mono_to_stereo[path][dai->id];
cif_conf.stereo_conv = admaif->stereo_to_mono[path][dai->id];
tegra_admaif_set_pack_mode(admaif->regmap, reg, valid_bit);
tegra_set_cif(admaif->regmap, reg, &cif_conf);
return 0;
}
static int tegra_admaif_start(struct snd_soc_dai *dai, int direction)
{
struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
unsigned int reg, mask, val;
switch (direction) {
case SNDRV_PCM_STREAM_PLAYBACK:
mask = TX_ENABLE_MASK;
val = TX_ENABLE;
reg = CH_TX_REG(TEGRA_ADMAIF_TX_ENABLE, dai->id);
break;
case SNDRV_PCM_STREAM_CAPTURE:
mask = RX_ENABLE_MASK;
val = RX_ENABLE;
reg = CH_RX_REG(TEGRA_ADMAIF_RX_ENABLE, dai->id);
break;
default:
return -EINVAL;
}
regmap_update_bits(admaif->regmap, reg, mask, val);
return 0;
}
static int tegra_admaif_stop(struct snd_soc_dai *dai, int direction)
{
struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
unsigned int enable_reg, status_reg, reset_reg, mask, val;
char *dir_name;
int err, enable;
switch (direction) {
case SNDRV_PCM_STREAM_PLAYBACK:
mask = TX_ENABLE_MASK;
enable = TX_ENABLE;
dir_name = "TX";
enable_reg = CH_TX_REG(TEGRA_ADMAIF_TX_ENABLE, dai->id);
status_reg = CH_TX_REG(TEGRA_ADMAIF_TX_STATUS, dai->id);
reset_reg = CH_TX_REG(TEGRA_ADMAIF_TX_SOFT_RESET, dai->id);
break;
case SNDRV_PCM_STREAM_CAPTURE:
mask = RX_ENABLE_MASK;
enable = RX_ENABLE;
dir_name = "RX";
enable_reg = CH_RX_REG(TEGRA_ADMAIF_RX_ENABLE, dai->id);
status_reg = CH_RX_REG(TEGRA_ADMAIF_RX_STATUS, dai->id);
reset_reg = CH_RX_REG(TEGRA_ADMAIF_RX_SOFT_RESET, dai->id);
break;
default:
return -EINVAL;
}
/* Disable TX/RX channel */
regmap_update_bits(admaif->regmap, enable_reg, mask, ~enable);
/* Wait until ADMAIF TX/RX status is disabled */
err = regmap_read_poll_timeout_atomic(admaif->regmap, status_reg, val,
!(val & enable), 10, 10000);
if (err < 0)
dev_warn(dai->dev, "timeout: failed to disable ADMAIF%d_%s\n",
dai->id + 1, dir_name);
/* SW reset */
regmap_update_bits(admaif->regmap, reset_reg, SW_RESET_MASK, SW_RESET);
/* Wait till SW reset is complete */
err = regmap_read_poll_timeout_atomic(admaif->regmap, reset_reg, val,
!(val & SW_RESET_MASK & SW_RESET),
10, 10000);
if (err) {
dev_err(dai->dev, "timeout: SW reset failed for ADMAIF%d_%s\n",
dai->id + 1, dir_name);
return err;
}
return 0;
}
static int tegra_admaif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int err;
err = snd_dmaengine_pcm_trigger(substream, cmd);
if (err)
return err;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
return tegra_admaif_start(dai, substream->stream);
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
return tegra_admaif_stop(dai, substream->stream);
default:
return -EINVAL;
}
}
static int tegra210_admaif_pget_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
ucontrol->value.enumerated.item[0] =
admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg];
return 0;
}
static int tegra210_admaif_pput_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg])
return 0;
admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg] = value;
return 1;
}
static int tegra210_admaif_cget_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
ucontrol->value.enumerated.item[0] =
admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg];
return 0;
}
static int tegra210_admaif_cput_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg])
return 0;
admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg] = value;
return 1;
}
static int tegra210_admaif_pget_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
ucontrol->value.enumerated.item[0] =
admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg];
return 0;
}
static int tegra210_admaif_pput_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg])
return 0;
admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg] = value;
return 1;
}
static int tegra210_admaif_cget_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
ucontrol->value.enumerated.item[0] =
admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg];
return 0;
}
static int tegra210_admaif_cput_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg])
return 0;
admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg] = value;
return 1;
}
static int tegra_admaif_dai_probe(struct snd_soc_dai *dai)
{
struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &admaif->playback_dma_data[dai->id],
&admaif->capture_dma_data[dai->id]);
return 0;
}
static const struct snd_soc_dai_ops tegra_admaif_dai_ops = {
.probe = tegra_admaif_dai_probe,
.hw_params = tegra_admaif_hw_params,
.trigger = tegra_admaif_trigger,
};
#define DAI(dai_name) \
{ \
.name = dai_name, \
.playback = { \
.stream_name = dai_name " Playback", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = dai_name " Capture", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &tegra_admaif_dai_ops, \
}
static struct snd_soc_dai_driver tegra210_admaif_cmpnt_dais[] = {
DAI("ADMAIF1"),
DAI("ADMAIF2"),
DAI("ADMAIF3"),
DAI("ADMAIF4"),
DAI("ADMAIF5"),
DAI("ADMAIF6"),
DAI("ADMAIF7"),
DAI("ADMAIF8"),
DAI("ADMAIF9"),
DAI("ADMAIF10"),
};
static struct snd_soc_dai_driver tegra186_admaif_cmpnt_dais[] = {
DAI("ADMAIF1"),
DAI("ADMAIF2"),
DAI("ADMAIF3"),
DAI("ADMAIF4"),
DAI("ADMAIF5"),
DAI("ADMAIF6"),
DAI("ADMAIF7"),
DAI("ADMAIF8"),
DAI("ADMAIF9"),
DAI("ADMAIF10"),
DAI("ADMAIF11"),
DAI("ADMAIF12"),
DAI("ADMAIF13"),
DAI("ADMAIF14"),
DAI("ADMAIF15"),
DAI("ADMAIF16"),
DAI("ADMAIF17"),
DAI("ADMAIF18"),
DAI("ADMAIF19"),
DAI("ADMAIF20"),
};
static const char * const tegra_admaif_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const char * const tegra_admaif_mono_conv_text[] = {
"Zero", "Copy",
};
/*
* Below macro is added to avoid looping over all ADMAIFx controls related
* to mono/stereo conversions in get()/put() callbacks.
*/
#define NV_SOC_ENUM_EXT(xname, xreg, xhandler_get, xhandler_put, xenum_text) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.info = snd_soc_info_enum_double, \
.name = xname, \
.get = xhandler_get, \
.put = xhandler_put, \
.private_value = (unsigned long)&(struct soc_enum) \
SOC_ENUM_SINGLE(xreg, 0, ARRAY_SIZE(xenum_text), xenum_text) \
}
#define TEGRA_ADMAIF_CIF_CTRL(reg) \
NV_SOC_ENUM_EXT("ADMAIF" #reg " Playback Mono To Stereo", reg - 1, \
tegra210_admaif_pget_mono_to_stereo, \
tegra210_admaif_pput_mono_to_stereo, \
tegra_admaif_mono_conv_text), \
NV_SOC_ENUM_EXT("ADMAIF" #reg " Playback Stereo To Mono", reg - 1, \
tegra210_admaif_pget_stereo_to_mono, \
tegra210_admaif_pput_stereo_to_mono, \
tegra_admaif_stereo_conv_text), \
NV_SOC_ENUM_EXT("ADMAIF" #reg " Capture Mono To Stereo", reg - 1, \
tegra210_admaif_cget_mono_to_stereo, \
tegra210_admaif_cput_mono_to_stereo, \
tegra_admaif_mono_conv_text), \
NV_SOC_ENUM_EXT("ADMAIF" #reg " Capture Stereo To Mono", reg - 1, \
tegra210_admaif_cget_stereo_to_mono, \
tegra210_admaif_cput_stereo_to_mono, \
tegra_admaif_stereo_conv_text)
static struct snd_kcontrol_new tegra210_admaif_controls[] = {
TEGRA_ADMAIF_CIF_CTRL(1),
TEGRA_ADMAIF_CIF_CTRL(2),
TEGRA_ADMAIF_CIF_CTRL(3),
TEGRA_ADMAIF_CIF_CTRL(4),
TEGRA_ADMAIF_CIF_CTRL(5),
TEGRA_ADMAIF_CIF_CTRL(6),
TEGRA_ADMAIF_CIF_CTRL(7),
TEGRA_ADMAIF_CIF_CTRL(8),
TEGRA_ADMAIF_CIF_CTRL(9),
TEGRA_ADMAIF_CIF_CTRL(10),
};
static struct snd_kcontrol_new tegra186_admaif_controls[] = {
TEGRA_ADMAIF_CIF_CTRL(1),
TEGRA_ADMAIF_CIF_CTRL(2),
TEGRA_ADMAIF_CIF_CTRL(3),
TEGRA_ADMAIF_CIF_CTRL(4),
TEGRA_ADMAIF_CIF_CTRL(5),
TEGRA_ADMAIF_CIF_CTRL(6),
TEGRA_ADMAIF_CIF_CTRL(7),
TEGRA_ADMAIF_CIF_CTRL(8),
TEGRA_ADMAIF_CIF_CTRL(9),
TEGRA_ADMAIF_CIF_CTRL(10),
TEGRA_ADMAIF_CIF_CTRL(11),
TEGRA_ADMAIF_CIF_CTRL(12),
TEGRA_ADMAIF_CIF_CTRL(13),
TEGRA_ADMAIF_CIF_CTRL(14),
TEGRA_ADMAIF_CIF_CTRL(15),
TEGRA_ADMAIF_CIF_CTRL(16),
TEGRA_ADMAIF_CIF_CTRL(17),
TEGRA_ADMAIF_CIF_CTRL(18),
TEGRA_ADMAIF_CIF_CTRL(19),
TEGRA_ADMAIF_CIF_CTRL(20),
};
static const struct snd_soc_component_driver tegra210_admaif_cmpnt = {
.controls = tegra210_admaif_controls,
.num_controls = ARRAY_SIZE(tegra210_admaif_controls),
.pcm_construct = tegra_pcm_construct,
.open = tegra_pcm_open,
.close = tegra_pcm_close,
.hw_params = tegra_pcm_hw_params,
.pointer = tegra_pcm_pointer,
};
static const struct snd_soc_component_driver tegra186_admaif_cmpnt = {
.controls = tegra186_admaif_controls,
.num_controls = ARRAY_SIZE(tegra186_admaif_controls),
.pcm_construct = tegra_pcm_construct,
.open = tegra_pcm_open,
.close = tegra_pcm_close,
.hw_params = tegra_pcm_hw_params,
.pointer = tegra_pcm_pointer,
};
static const struct tegra_admaif_soc_data soc_data_tegra210 = {
.num_ch = TEGRA210_ADMAIF_CHANNEL_COUNT,
.cmpnt = &tegra210_admaif_cmpnt,
.dais = tegra210_admaif_cmpnt_dais,
.regmap_conf = &tegra210_admaif_regmap_config,
.global_base = TEGRA210_ADMAIF_GLOBAL_BASE,
.tx_base = TEGRA210_ADMAIF_TX_BASE,
.rx_base = TEGRA210_ADMAIF_RX_BASE,
};
static const struct tegra_admaif_soc_data soc_data_tegra186 = {
.num_ch = TEGRA186_ADMAIF_CHANNEL_COUNT,
.cmpnt = &tegra186_admaif_cmpnt,
.dais = tegra186_admaif_cmpnt_dais,
.regmap_conf = &tegra186_admaif_regmap_config,
.global_base = TEGRA186_ADMAIF_GLOBAL_BASE,
.tx_base = TEGRA186_ADMAIF_TX_BASE,
.rx_base = TEGRA186_ADMAIF_RX_BASE,
};
static const struct of_device_id tegra_admaif_of_match[] = {
{ .compatible = "nvidia,tegra210-admaif", .data = &soc_data_tegra210 },
{ .compatible = "nvidia,tegra186-admaif", .data = &soc_data_tegra186 },
{},
};
MODULE_DEVICE_TABLE(of, tegra_admaif_of_match);
static int tegra_admaif_probe(struct platform_device *pdev)
{
struct tegra_admaif *admaif;
void __iomem *regs;
struct resource *res;
int err, i;
admaif = devm_kzalloc(&pdev->dev, sizeof(*admaif), GFP_KERNEL);
if (!admaif)
return -ENOMEM;
admaif->soc_data = of_device_get_match_data(&pdev->dev);
dev_set_drvdata(&pdev->dev, admaif);
admaif->capture_dma_data =
devm_kcalloc(&pdev->dev,
admaif->soc_data->num_ch,
sizeof(struct snd_dmaengine_dai_dma_data),
GFP_KERNEL);
if (!admaif->capture_dma_data)
return -ENOMEM;
admaif->playback_dma_data =
devm_kcalloc(&pdev->dev,
admaif->soc_data->num_ch,
sizeof(struct snd_dmaengine_dai_dma_data),
GFP_KERNEL);
if (!admaif->playback_dma_data)
return -ENOMEM;
for (i = 0; i < ADMAIF_PATHS; i++) {
admaif->mono_to_stereo[i] =
devm_kcalloc(&pdev->dev, admaif->soc_data->num_ch,
sizeof(unsigned int), GFP_KERNEL);
if (!admaif->mono_to_stereo[i])
return -ENOMEM;
admaif->stereo_to_mono[i] =
devm_kcalloc(&pdev->dev, admaif->soc_data->num_ch,
sizeof(unsigned int), GFP_KERNEL);
if (!admaif->stereo_to_mono[i])
return -ENOMEM;
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
admaif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
admaif->soc_data->regmap_conf);
if (IS_ERR(admaif->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(admaif->regmap);
}
regcache_cache_only(admaif->regmap, true);
regmap_update_bits(admaif->regmap, admaif->soc_data->global_base +
TEGRA_ADMAIF_GLOBAL_ENABLE, 1, 1);
for (i = 0; i < admaif->soc_data->num_ch; i++) {
admaif->playback_dma_data[i].addr = res->start +
CH_TX_REG(TEGRA_ADMAIF_TX_FIFO_WRITE, i);
admaif->capture_dma_data[i].addr = res->start +
CH_RX_REG(TEGRA_ADMAIF_RX_FIFO_READ, i);
admaif->playback_dma_data[i].addr_width = 32;
if (of_property_read_string_index(pdev->dev.of_node,
"dma-names", (i * 2) + 1,
&admaif->playback_dma_data[i].chan_name) < 0) {
dev_err(&pdev->dev,
"missing property nvidia,dma-names\n");
return -ENODEV;
}
admaif->capture_dma_data[i].addr_width = 32;
if (of_property_read_string_index(pdev->dev.of_node,
"dma-names",
(i * 2),
&admaif->capture_dma_data[i].chan_name) < 0) {
dev_err(&pdev->dev,
"missing property nvidia,dma-names\n");
return -ENODEV;
}
}
err = devm_snd_soc_register_component(&pdev->dev,
admaif->soc_data->cmpnt,
admaif->soc_data->dais,
admaif->soc_data->num_ch);
if (err) {
dev_err(&pdev->dev,
"can't register ADMAIF component, err: %d\n", err);
return err;
}
pm_runtime_enable(&pdev->dev);
return 0;
}
static void tegra_admaif_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra_admaif_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_admaif_runtime_suspend,
tegra_admaif_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra_admaif_driver = {
.probe = tegra_admaif_probe,
.remove_new = tegra_admaif_remove,
.driver = {
.name = "tegra210-admaif",
.of_match_table = tegra_admaif_of_match,
.pm = &tegra_admaif_pm_ops,
},
};
module_platform_driver(tegra_admaif_driver);
MODULE_AUTHOR("Songhee Baek <[email protected]>");
MODULE_DESCRIPTION("Tegra210 ASoC ADMAIF driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_admaif.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra20_spdif.c - Tegra20 SPDIF driver
*
* Author: Stephen Warren <[email protected]>
* Copyright (C) 2011-2012 - NVIDIA, Inc.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra20_spdif.h"
static __maybe_unused int tegra20_spdif_runtime_suspend(struct device *dev)
{
struct tegra20_spdif *spdif = dev_get_drvdata(dev);
regcache_cache_only(spdif->regmap, true);
clk_disable_unprepare(spdif->clk_spdif_out);
return 0;
}
static __maybe_unused int tegra20_spdif_runtime_resume(struct device *dev)
{
struct tegra20_spdif *spdif = dev_get_drvdata(dev);
int ret;
ret = reset_control_assert(spdif->reset);
if (ret)
return ret;
ret = clk_prepare_enable(spdif->clk_spdif_out);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
usleep_range(10, 100);
ret = reset_control_deassert(spdif->reset);
if (ret)
goto disable_clocks;
regcache_cache_only(spdif->regmap, false);
regcache_mark_dirty(spdif->regmap);
ret = regcache_sync(spdif->regmap);
if (ret)
goto disable_clocks;
return 0;
disable_clocks:
clk_disable_unprepare(spdif->clk_spdif_out);
return ret;
}
static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
unsigned int mask = 0, val = 0;
int ret, spdifclock;
long rate;
mask |= TEGRA20_SPDIF_CTRL_PACK |
TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
val |= TEGRA20_SPDIF_CTRL_PACK |
TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
break;
default:
return -EINVAL;
}
regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
/*
* FIFO trigger level must be bigger than DMA burst or equal to it,
* otherwise data is discarded on overflow.
*/
regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK,
TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL);
switch (params_rate(params)) {
case 32000:
spdifclock = 4096000;
break;
case 44100:
spdifclock = 5644800;
break;
case 48000:
spdifclock = 6144000;
break;
case 88200:
spdifclock = 11289600;
break;
case 96000:
spdifclock = 12288000;
break;
case 176400:
spdifclock = 22579200;
break;
case 192000:
spdifclock = 24576000;
break;
default:
return -EINVAL;
}
ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
if (ret) {
dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret);
return ret;
}
rate = clk_get_rate(spdif->clk_spdif_out);
if (rate != spdifclock)
dev_warn_once(dai->dev,
"SPDIF clock rate %d doesn't match requested rate %lu\n",
spdifclock, rate);
return 0;
}
static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
{
regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
TEGRA20_SPDIF_CTRL_TX_EN,
TEGRA20_SPDIF_CTRL_TX_EN);
}
static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
{
regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
TEGRA20_SPDIF_CTRL_TX_EN, 0);
}
static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
tegra20_spdif_start_playback(spdif);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
tegra20_spdif_stop_playback(spdif);
break;
default:
return -EINVAL;
}
return 0;
}
static int tegra20_spdif_filter_rates(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_interval *r = hw_param_interval(params, rule->var);
struct snd_soc_dai *dai = rule->private;
struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
struct clk *parent = clk_get_parent(spdif->clk_spdif_out);
static const unsigned int rates[] = { 32000, 44100, 48000 };
unsigned long i, parent_rate, valid_rates = 0;
parent_rate = clk_get_rate(parent);
if (!parent_rate) {
dev_err(dai->dev, "Can't get parent clock rate\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(rates); i++) {
if (parent_rate % (rates[i] * 128) == 0)
valid_rates |= BIT(i);
}
/*
* At least one rate must be valid, otherwise the parent clock isn't
* audio PLL. Nothing should be filtered in this case.
*/
if (!valid_rates)
valid_rates = BIT(ARRAY_SIZE(rates)) - 1;
return snd_interval_list(r, ARRAY_SIZE(rates), rates, valid_rates);
}
static int tegra20_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
return 0;
/*
* SPDIF and I2S share audio PLL. HDMI takes audio packets from SPDIF
* and audio may not work on some TVs if clock rate isn't precise.
*
* PLL rate is controlled by I2S side. Filter out audio rates that
* don't match PLL rate at the start of stream to allow both SPDIF
* and I2S work simultaneously, assuming that PLL rate won't be
* changed later on.
*/
return snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
tegra20_spdif_filter_rates, dai,
SNDRV_PCM_HW_PARAM_RATE, -1);
}
static int tegra20_spdif_probe(struct snd_soc_dai *dai)
{
struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
snd_soc_dai_init_dma_data(dai, &spdif->playback_dma_data, NULL);
return 0;
}
static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
.probe = tegra20_spdif_probe,
.hw_params = tegra20_spdif_hw_params,
.trigger = tegra20_spdif_trigger,
.startup = tegra20_spdif_startup,
};
static struct snd_soc_dai_driver tegra20_spdif_dai = {
.name = "tegra20-spdif",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tegra20_spdif_dai_ops,
};
static const struct snd_soc_component_driver tegra20_spdif_component = {
.name = "tegra20-spdif",
.legacy_dai_naming = 1,
};
static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_SPDIF_CTRL:
case TEGRA20_SPDIF_STATUS:
case TEGRA20_SPDIF_STROBE_CTRL:
case TEGRA20_SPDIF_DATA_FIFO_CSR:
case TEGRA20_SPDIF_DATA_OUT:
case TEGRA20_SPDIF_DATA_IN:
case TEGRA20_SPDIF_CH_STA_RX_A:
case TEGRA20_SPDIF_CH_STA_RX_B:
case TEGRA20_SPDIF_CH_STA_RX_C:
case TEGRA20_SPDIF_CH_STA_RX_D:
case TEGRA20_SPDIF_CH_STA_RX_E:
case TEGRA20_SPDIF_CH_STA_RX_F:
case TEGRA20_SPDIF_CH_STA_TX_A:
case TEGRA20_SPDIF_CH_STA_TX_B:
case TEGRA20_SPDIF_CH_STA_TX_C:
case TEGRA20_SPDIF_CH_STA_TX_D:
case TEGRA20_SPDIF_CH_STA_TX_E:
case TEGRA20_SPDIF_CH_STA_TX_F:
case TEGRA20_SPDIF_USR_STA_RX_A:
case TEGRA20_SPDIF_USR_DAT_TX_A:
return true;
default:
return false;
}
}
static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_SPDIF_STATUS:
case TEGRA20_SPDIF_DATA_FIFO_CSR:
case TEGRA20_SPDIF_DATA_OUT:
case TEGRA20_SPDIF_DATA_IN:
case TEGRA20_SPDIF_CH_STA_RX_A:
case TEGRA20_SPDIF_CH_STA_RX_B:
case TEGRA20_SPDIF_CH_STA_RX_C:
case TEGRA20_SPDIF_CH_STA_RX_D:
case TEGRA20_SPDIF_CH_STA_RX_E:
case TEGRA20_SPDIF_CH_STA_RX_F:
case TEGRA20_SPDIF_USR_STA_RX_A:
case TEGRA20_SPDIF_USR_DAT_TX_A:
return true;
default:
return false;
}
}
static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_SPDIF_DATA_OUT:
case TEGRA20_SPDIF_DATA_IN:
case TEGRA20_SPDIF_USR_STA_RX_A:
case TEGRA20_SPDIF_USR_DAT_TX_A:
return true;
default:
return false;
}
}
static const struct regmap_config tegra20_spdif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
.writeable_reg = tegra20_spdif_wr_rd_reg,
.readable_reg = tegra20_spdif_wr_rd_reg,
.volatile_reg = tegra20_spdif_volatile_reg,
.precious_reg = tegra20_spdif_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static int tegra20_spdif_platform_probe(struct platform_device *pdev)
{
struct tegra20_spdif *spdif;
struct resource *mem;
void __iomem *regs;
int ret;
spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
GFP_KERNEL);
if (!spdif)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, spdif);
spdif->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(spdif->reset)) {
dev_err(&pdev->dev, "Can't retrieve spdif reset\n");
return PTR_ERR(spdif->reset);
}
spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out");
if (IS_ERR(spdif->clk_spdif_out)) {
dev_err(&pdev->dev, "Could not retrieve spdif clock\n");
return PTR_ERR(spdif->clk_spdif_out);
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(regs))
return PTR_ERR(regs);
spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra20_spdif_regmap_config);
if (IS_ERR(spdif->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(spdif->regmap);
}
spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
spdif->playback_dma_data.maxburst = 4;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_snd_soc_register_component(&pdev->dev,
&tegra20_spdif_component,
&tegra20_spdif_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
return ret;
}
ret = devm_tegra_pcm_platform_register(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
return ret;
}
return 0;
}
static const struct dev_pm_ops tegra20_spdif_pm_ops = {
SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
tegra20_spdif_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct of_device_id tegra20_spdif_of_match[] = {
{ .compatible = "nvidia,tegra20-spdif", },
{},
};
MODULE_DEVICE_TABLE(of, tegra20_spdif_of_match);
static struct platform_driver tegra20_spdif_driver = {
.driver = {
.name = "tegra20-spdif",
.pm = &tegra20_spdif_pm_ops,
.of_match_table = tegra20_spdif_of_match,
},
.probe = tegra20_spdif_platform_probe,
};
module_platform_driver(tegra20_spdif_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/tegra/tegra20_spdif.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra20_i2s.c - Tegra20 I2S driver
*
* Author: Stephen Warren <[email protected]>
* Copyright (C) 2010,2012 - NVIDIA, Inc.
*
* Based on code copyright/by:
*
* Copyright (c) 2009-2010, NVIDIA Corporation.
* Scott Peterson <[email protected]>
*
* Copyright (C) 2010 Google, Inc.
* Iliyan Malchev <[email protected]>
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra20_i2s.h"
#define DRV_NAME "tegra20-i2s"
static __maybe_unused int tegra20_i2s_runtime_suspend(struct device *dev)
{
struct tegra20_i2s *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
clk_disable_unprepare(i2s->clk_i2s);
return 0;
}
static __maybe_unused int tegra20_i2s_runtime_resume(struct device *dev)
{
struct tegra20_i2s *i2s = dev_get_drvdata(dev);
int ret;
ret = reset_control_assert(i2s->reset);
if (ret)
return ret;
ret = clk_prepare_enable(i2s->clk_i2s);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
usleep_range(10, 100);
ret = reset_control_deassert(i2s->reset);
if (ret)
goto disable_clocks;
regcache_cache_only(i2s->regmap, false);
regcache_mark_dirty(i2s->regmap);
ret = regcache_sync(i2s->regmap);
if (ret)
goto disable_clocks;
return 0;
disable_clocks:
clk_disable_unprepare(i2s->clk_i2s);
return ret;
}
static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask = 0, val = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
mask |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
val |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
break;
case SND_SOC_DAIFMT_BC_FC:
break;
default:
return -EINVAL;
}
mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
TEGRA20_I2S_CTRL_LRCK_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_DSP_B:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
val |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
break;
case SND_SOC_DAIFMT_I2S:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
return 0;
}
static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val;
int ret, sample_size, srate, i2sclock, bitcnt;
mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
val = TEGRA20_I2S_CTRL_BIT_SIZE_16;
sample_size = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val = TEGRA20_I2S_CTRL_BIT_SIZE_24;
sample_size = 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
val = TEGRA20_I2S_CTRL_BIT_SIZE_32;
sample_size = 32;
break;
default:
return -EINVAL;
}
mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
srate = params_rate(params);
/* Final "* 2" required by Tegra hardware */
i2sclock = srate * params_channels(params) * sample_size * 2;
ret = clk_set_rate(i2s->clk_i2s, i2sclock);
if (ret) {
dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
return ret;
}
bitcnt = (i2sclock / (2 * srate)) - 1;
if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
return -EINVAL;
val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
if (i2sclock % (2 * srate))
val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);
regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
return 0;
}
static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO1_ENABLE,
TEGRA20_I2S_CTRL_FIFO1_ENABLE);
}
static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0);
}
static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO2_ENABLE,
TEGRA20_I2S_CTRL_FIFO2_ENABLE);
}
static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
{
regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0);
}
static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra20_i2s_start_playback(i2s);
else
tegra20_i2s_start_capture(i2s);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra20_i2s_stop_playback(i2s);
else
tegra20_i2s_stop_capture(i2s);
break;
default:
return -EINVAL;
}
return 0;
}
static int tegra20_i2s_probe(struct snd_soc_dai *dai)
{
struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
&i2s->capture_dma_data);
return 0;
}
static const unsigned int tegra20_i2s_rates[] = {
8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000
};
static int tegra20_i2s_filter_rates(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_interval *r = hw_param_interval(params, rule->var);
struct snd_soc_dai *dai = rule->private;
struct tegra20_i2s *i2s = dev_get_drvdata(dai->dev);
struct clk *parent = clk_get_parent(i2s->clk_i2s);
unsigned long i, parent_rate, valid_rates = 0;
parent_rate = clk_get_rate(parent);
if (!parent_rate) {
dev_err(dai->dev, "Can't get parent clock rate\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(tegra20_i2s_rates); i++) {
if (parent_rate % (tegra20_i2s_rates[i] * 128) == 0)
valid_rates |= BIT(i);
}
/*
* At least one rate must be valid, otherwise the parent clock isn't
* audio PLL. Nothing should be filtered in this case.
*/
if (!valid_rates)
valid_rates = BIT(ARRAY_SIZE(tegra20_i2s_rates)) - 1;
return snd_interval_list(r, ARRAY_SIZE(tegra20_i2s_rates),
tegra20_i2s_rates, valid_rates);
}
static int tegra20_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate"))
return 0;
return snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
tegra20_i2s_filter_rates, dai,
SNDRV_PCM_HW_PARAM_RATE, -1);
}
static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
.probe = tegra20_i2s_probe,
.set_fmt = tegra20_i2s_set_fmt,
.hw_params = tegra20_i2s_hw_params,
.trigger = tegra20_i2s_trigger,
.startup = tegra20_i2s_startup,
};
static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tegra20_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver tegra20_i2s_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_I2S_CTRL:
case TEGRA20_I2S_STATUS:
case TEGRA20_I2S_TIMING:
case TEGRA20_I2S_FIFO_SCR:
case TEGRA20_I2S_PCM_CTRL:
case TEGRA20_I2S_NW_CTRL:
case TEGRA20_I2S_TDM_CTRL:
case TEGRA20_I2S_TDM_TX_RX_CTRL:
case TEGRA20_I2S_FIFO1:
case TEGRA20_I2S_FIFO2:
return true;
default:
return false;
}
}
static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_I2S_STATUS:
case TEGRA20_I2S_FIFO_SCR:
case TEGRA20_I2S_FIFO1:
case TEGRA20_I2S_FIFO2:
return true;
default:
return false;
}
}
static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_I2S_FIFO1:
case TEGRA20_I2S_FIFO2:
return true;
default:
return false;
}
}
static const struct regmap_config tegra20_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA20_I2S_FIFO2,
.writeable_reg = tegra20_i2s_wr_rd_reg,
.readable_reg = tegra20_i2s_wr_rd_reg,
.volatile_reg = tegra20_i2s_volatile_reg,
.precious_reg = tegra20_i2s_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static int tegra20_i2s_platform_probe(struct platform_device *pdev)
{
struct tegra20_i2s *i2s;
struct resource *mem;
void __iomem *regs;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
if (!i2s) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, i2s);
i2s->dai = tegra20_i2s_dai_template;
i2s->dai.name = dev_name(&pdev->dev);
i2s->reset = devm_reset_control_get_exclusive(&pdev->dev, "i2s");
if (IS_ERR(i2s->reset)) {
dev_err(&pdev->dev, "Can't retrieve i2s reset\n");
return PTR_ERR(i2s->reset);
}
i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(i2s->clk_i2s)) {
dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
ret = PTR_ERR(i2s->clk_i2s);
goto err;
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
goto err;
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra20_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
ret = PTR_ERR(i2s->regmap);
goto err;
}
i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 4;
i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->playback_dma_data.maxburst = 4;
pm_runtime_enable(&pdev->dev);
ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component,
&i2s->dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
ret = -ENOMEM;
goto err_pm_disable;
}
ret = tegra_pcm_platform_register(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
goto err_unregister_component;
}
return 0;
err_unregister_component:
snd_soc_unregister_component(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err:
return ret;
}
static void tegra20_i2s_platform_remove(struct platform_device *pdev)
{
tegra_pcm_platform_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static const struct of_device_id tegra20_i2s_of_match[] = {
{ .compatible = "nvidia,tegra20-i2s", },
{},
};
static const struct dev_pm_ops tegra20_i2s_pm_ops = {
SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
tegra20_i2s_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra20_i2s_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = tegra20_i2s_of_match,
.pm = &tegra20_i2s_pm_ops,
},
.probe = tegra20_i2s_platform_probe,
.remove_new = tegra20_i2s_platform_remove,
};
module_platform_driver(tegra20_i2s_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);
| linux-master | sound/soc/tegra/tegra20_i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_mbdrc.c - Tegra210 MBDRC driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "tegra210_mbdrc.h"
#include "tegra210_ope.h"
#define MBDRC_FILTER_REG(reg, id) \
((reg) + ((id) * TEGRA210_MBDRC_FILTER_PARAM_STRIDE))
#define MBDRC_FILTER_REG_DEFAULTS(id) \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IIR_CFG, id), 0x00000005}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_ATTACK, id), 0x3e48590c}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_RELEASE, id), 0x08414e9f}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_ATTACK, id), 0x7fffffff}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_THRESHOLD, id), 0x06145082}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_OUT_THRESHOLD, id), 0x060d379b}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_1ST, id), 0x0000a000}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_2ND, id), 0x00002000}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_3RD, id), 0x00000b33}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_4TH, id), 0x00000800}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_5TH, id), 0x0000019a}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_MAKEUP_GAIN, id), 0x00000002}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_INIT_GAIN, id), 0x00066666}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_ATTACK, id), 0x00d9ba0e}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_RELEASE, id), 0x3e48590c}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_RELEASE, id), 0x7ffff26a}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_CFG_RAM_CTRL, id), 0x4000}
static const struct reg_default tegra210_mbdrc_reg_defaults[] = {
{ TEGRA210_MBDRC_CFG, 0x0030de51},
{ TEGRA210_MBDRC_CHANNEL_MASK, 0x00000003},
{ TEGRA210_MBDRC_FAST_FACTOR, 0x30000800},
MBDRC_FILTER_REG_DEFAULTS(0),
MBDRC_FILTER_REG_DEFAULTS(1),
MBDRC_FILTER_REG_DEFAULTS(2),
};
/* Default MBDRC parameters */
static const struct tegra210_mbdrc_config mbdrc_init_config = {
.mode = 0, /* Bypass */
.rms_off = 48,
.peak_rms_mode = 1, /* PEAK */
.filter_structure = 0, /* All-pass tree */
.shift_ctrl = 30,
.frame_size = 32,
.channel_mask = 0x3,
.fa_factor = 2048,
.fr_factor = 14747,
.band_params[MBDRC_LOW_BAND] = {
.band = MBDRC_LOW_BAND,
.iir_stages = 5,
.in_attack_tc = 1044928780,
.in_release_tc = 138497695,
.fast_attack_tc = 2147483647,
.in_threshold = {130, 80, 20, 6},
.out_threshold = {155, 55, 13, 6},
.ratio = {40960, 8192, 2867, 2048, 410},
.makeup_gain = 4,
.gain_init = 419430,
.gain_attack_tc = 14268942,
.gain_release_tc = 1440547090,
.fast_release_tc = 2147480170,
.biquad_params = {
/*
* Gains:
*
* b0, b1, a0,
* a1, a2,
*/
/* Band-0 */
961046798, -2030431983, 1073741824,
2030431983, -961046798,
/* Band-1 */
1030244425, -2099481453, 1073741824,
2099481453, -1030244425,
/* Band-2 */
1067169294, -2136327263, 1073741824,
2136327263, -1067169294,
/* Band-3 */
434951949, -1306567134, 1073741824,
1306567134, -434951949,
/* Band-4 */
780656019, -1605955641, 1073741824,
1605955641, -780656019,
/* Band-5 */
1024497031, -1817128152, 1073741824,
1817128152, -1024497031,
/* Band-6 */
1073741824, 0, 0,
0, 0,
/* Band-7 */
1073741824, 0, 0,
0, 0,
}
},
.band_params[MBDRC_MID_BAND] = {
.band = MBDRC_MID_BAND,
.iir_stages = 5,
.in_attack_tc = 1581413104,
.in_release_tc = 35494783,
.fast_attack_tc = 2147483647,
.in_threshold = {130, 50, 30, 6},
.out_threshold = {106, 50, 30, 13},
.ratio = {40960, 2867, 4096, 2867, 410},
.makeup_gain = 6,
.gain_init = 419430,
.gain_attack_tc = 4766887,
.gain_release_tc = 1044928780,
.fast_release_tc = 2147480170,
.biquad_params = {
/*
* Gains:
*
* b0, b1, a0,
* a1, a2,
*/
/* Band-0 */
-1005668963, 1073741824, 0,
1005668963, 0,
/* Band-1 */
998437058, -2067742187, 1073741824,
2067742187, -998437058,
/* Band-2 */
1051963422, -2121153948, 1073741824,
2121153948, -1051963422,
/* Band-3 */
434951949, -1306567134, 1073741824,
1306567134, -434951949,
/* Band-4 */
780656019, -1605955641, 1073741824,
1605955641, -780656019,
/* Band-5 */
1024497031, -1817128152, 1073741824,
1817128152, -1024497031,
/* Band-6 */
1073741824, 0, 0,
0, 0,
/* Band-7 */
1073741824, 0, 0,
0, 0,
}
},
.band_params[MBDRC_HIGH_BAND] = {
.band = MBDRC_HIGH_BAND,
.iir_stages = 5,
.in_attack_tc = 2144750688,
.in_release_tc = 70402888,
.fast_attack_tc = 2147483647,
.in_threshold = {130, 50, 30, 6},
.out_threshold = {106, 50, 30, 13},
.ratio = {40960, 2867, 4096, 2867, 410},
.makeup_gain = 6,
.gain_init = 419430,
.gain_attack_tc = 4766887,
.gain_release_tc = 1044928780,
.fast_release_tc = 2147480170,
.biquad_params = {
/*
* Gains:
*
* b0, b1, a0,
* a1, a2,
*/
/* Band-0 */
1073741824, 0, 0,
0, 0,
/* Band-1 */
1073741824, 0, 0,
0, 0,
/* Band-2 */
1073741824, 0, 0,
0, 0,
/* Band-3 */
-619925131, 1073741824, 0,
619925131, 0,
/* Band-4 */
606839335, -1455425976, 1073741824,
1455425976, -606839335,
/* Band-5 */
917759617, -1724690840, 1073741824,
1724690840, -917759617,
/* Band-6 */
1073741824, 0, 0,
0, 0,
/* Band-7 */
1073741824, 0, 0,
0, 0,
}
}
};
static void tegra210_mbdrc_write_ram(struct regmap *regmap, unsigned int reg_ctrl,
unsigned int reg_data, unsigned int ram_offset,
unsigned int *data, size_t size)
{
unsigned int val;
unsigned int i;
val = ram_offset & TEGRA210_MBDRC_RAM_CTRL_RAM_ADDR_MASK;
val |= TEGRA210_MBDRC_RAM_CTRL_ADDR_INIT_EN;
val |= TEGRA210_MBDRC_RAM_CTRL_SEQ_ACCESS_EN;
val |= TEGRA210_MBDRC_RAM_CTRL_RW_WRITE;
regmap_write(regmap, reg_ctrl, val);
for (i = 0; i < size; i++)
regmap_write(regmap, reg_data, data[i]);
}
static int tegra210_mbdrc_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
unsigned int val;
regmap_read(ope->mbdrc_regmap, mc->reg, &val);
ucontrol->value.integer.value[0] = (val >> mc->shift) & mc->max;
return 0;
}
static int tegra210_mbdrc_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
unsigned int val = ucontrol->value.integer.value[0];
bool change = false;
val = val << mc->shift;
regmap_update_bits_check(ope->mbdrc_regmap, mc->reg,
(mc->max << mc->shift), val, &change);
return change ? 1 : 0;
}
static int tegra210_mbdrc_get_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int val;
regmap_read(ope->mbdrc_regmap, e->reg, &val);
ucontrol->value.enumerated.item[0] = (val >> e->shift_l) & e->mask;
return 0;
}
static int tegra210_mbdrc_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
bool change = false;
unsigned int val;
unsigned int mask;
if (ucontrol->value.enumerated.item[0] > e->items - 1)
return -EINVAL;
val = ucontrol->value.enumerated.item[0] << e->shift_l;
mask = e->mask << e->shift_l;
regmap_update_bits_check(ope->mbdrc_regmap, e->reg, mask, val,
&change);
return change ? 1 : 0;
}
static int tegra210_mbdrc_band_params_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 *data = (u32 *)ucontrol->value.bytes.data;
u32 regs = params->soc.base;
u32 mask = params->soc.mask;
u32 shift = params->shift;
unsigned int i;
for (i = 0; i < params->soc.num_regs; i++, regs += cmpnt->val_bytes) {
regmap_read(ope->mbdrc_regmap, regs, &data[i]);
data[i] = ((data[i] & mask) >> shift);
}
return 0;
}
static int tegra210_mbdrc_band_params_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 *data = (u32 *)ucontrol->value.bytes.data;
u32 regs = params->soc.base;
u32 mask = params->soc.mask;
u32 shift = params->shift;
bool change = false;
unsigned int i;
for (i = 0; i < params->soc.num_regs; i++, regs += cmpnt->val_bytes) {
bool update = false;
regmap_update_bits_check(ope->mbdrc_regmap, regs, mask,
data[i] << shift, &update);
change |= update;
}
return change ? 1 : 0;
}
static int tegra210_mbdrc_threshold_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 *data = (u32 *)ucontrol->value.bytes.data;
u32 regs = params->soc.base;
u32 num_regs = params->soc.num_regs;
u32 val;
unsigned int i;
for (i = 0; i < num_regs; i += 4, regs += cmpnt->val_bytes) {
regmap_read(ope->mbdrc_regmap, regs, &val);
data[i] = (val & TEGRA210_MBDRC_THRESH_1ST_MASK) >>
TEGRA210_MBDRC_THRESH_1ST_SHIFT;
data[i + 1] = (val & TEGRA210_MBDRC_THRESH_2ND_MASK) >>
TEGRA210_MBDRC_THRESH_2ND_SHIFT;
data[i + 2] = (val & TEGRA210_MBDRC_THRESH_3RD_MASK) >>
TEGRA210_MBDRC_THRESH_3RD_SHIFT;
data[i + 3] = (val & TEGRA210_MBDRC_THRESH_4TH_MASK) >>
TEGRA210_MBDRC_THRESH_4TH_SHIFT;
}
return 0;
}
static int tegra210_mbdrc_threshold_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 *data = (u32 *)ucontrol->value.bytes.data;
u32 regs = params->soc.base;
u32 num_regs = params->soc.num_regs;
bool change = false;
unsigned int i;
for (i = 0; i < num_regs; i += 4, regs += cmpnt->val_bytes) {
bool update = false;
data[i] = (((data[i] >> TEGRA210_MBDRC_THRESH_1ST_SHIFT) &
TEGRA210_MBDRC_THRESH_1ST_MASK) |
((data[i + 1] >> TEGRA210_MBDRC_THRESH_2ND_SHIFT) &
TEGRA210_MBDRC_THRESH_2ND_MASK) |
((data[i + 2] >> TEGRA210_MBDRC_THRESH_3RD_SHIFT) &
TEGRA210_MBDRC_THRESH_3RD_MASK) |
((data[i + 3] >> TEGRA210_MBDRC_THRESH_4TH_SHIFT) &
TEGRA210_MBDRC_THRESH_4TH_MASK));
regmap_update_bits_check(ope->mbdrc_regmap, regs, 0xffffffff,
data[i], &update);
change |= update;
}
return change ? 1 : 0;
}
static int tegra210_mbdrc_biquad_coeffs_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
u32 *data = (u32 *)ucontrol->value.bytes.data;
memset(data, 0, params->soc.num_regs * cmpnt->val_bytes);
return 0;
}
static int tegra210_mbdrc_biquad_coeffs_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct tegra_soc_bytes *params = (void *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
u32 reg_ctrl = params->soc.base;
u32 reg_data = reg_ctrl + cmpnt->val_bytes;
u32 *data = (u32 *)ucontrol->value.bytes.data;
tegra210_mbdrc_write_ram(ope->mbdrc_regmap, reg_ctrl, reg_data,
params->shift, data, params->soc.num_regs);
return 1;
}
static int tegra210_mbdrc_param_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct soc_bytes *params = (void *)kcontrol->private_value;
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = params->num_regs * sizeof(u32);
return 0;
}
static int tegra210_mbdrc_vol_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
int val;
regmap_read(ope->mbdrc_regmap, mc->reg, &val);
ucontrol->value.integer.value[0] =
((val >> mc->shift) - TEGRA210_MBDRC_MASTER_VOL_MIN);
return 0;
}
static int tegra210_mbdrc_vol_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
int val = ucontrol->value.integer.value[0];
bool change = false;
val += TEGRA210_MBDRC_MASTER_VOL_MIN;
regmap_update_bits_check(ope->mbdrc_regmap, mc->reg,
mc->max << mc->shift, val << mc->shift,
&change);
regmap_read(ope->mbdrc_regmap, mc->reg, &val);
return change ? 1 : 0;
}
static const char * const tegra210_mbdrc_mode_text[] = {
"Bypass", "Fullband", "Dualband", "Multiband"
};
static const struct soc_enum tegra210_mbdrc_mode_enum =
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG, TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT,
4, tegra210_mbdrc_mode_text);
static const char * const tegra210_mbdrc_peak_rms_text[] = {
"Peak", "RMS"
};
static const struct soc_enum tegra210_mbdrc_peak_rms_enum =
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG, TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT,
2, tegra210_mbdrc_peak_rms_text);
static const char * const tegra210_mbdrc_filter_structure_text[] = {
"All-pass-tree", "Flexible"
};
static const struct soc_enum tegra210_mbdrc_filter_structure_enum =
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT, 2,
tegra210_mbdrc_filter_structure_text);
static const char * const tegra210_mbdrc_frame_size_text[] = {
"N1", "N2", "N4", "N8", "N16", "N32", "N64"
};
static const struct soc_enum tegra210_mbdrc_frame_size_enum =
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG, TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT,
7, tegra210_mbdrc_frame_size_text);
#define TEGRA_MBDRC_BYTES_EXT(xname, xbase, xregs, xshift, xmask, xinfo) \
TEGRA_SOC_BYTES_EXT(xname, xbase, xregs, xshift, xmask, \
tegra210_mbdrc_band_params_get, \
tegra210_mbdrc_band_params_put, \
tegra210_mbdrc_param_info)
#define TEGRA_MBDRC_BAND_BYTES_EXT(xname, xbase, xshift, xmask, xinfo) \
TEGRA_MBDRC_BYTES_EXT(xname, xbase, TEGRA210_MBDRC_FILTER_COUNT, \
xshift, xmask, xinfo)
static const DECLARE_TLV_DB_MINMAX(mdbrc_vol_tlv, -25600, 25500);
static const struct snd_kcontrol_new tegra210_mbdrc_controls[] = {
SOC_ENUM_EXT("MBDRC Peak RMS Mode", tegra210_mbdrc_peak_rms_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_ENUM_EXT("MBDRC Filter Structure",
tegra210_mbdrc_filter_structure_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_ENUM_EXT("MBDRC Frame Size", tegra210_mbdrc_frame_size_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_ENUM_EXT("MBDRC Mode", tegra210_mbdrc_mode_enum,
tegra210_mbdrc_get_enum, tegra210_mbdrc_put_enum),
SOC_SINGLE_EXT("MBDRC RMS Offset", TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT, 0x1ff, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_EXT("MBDRC Shift Control", TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT, 0x1f, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_EXT("MBDRC Fast Attack Factor", TEGRA210_MBDRC_FAST_FACTOR,
TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT, 0xffff, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_EXT("MBDRC Fast Release Factor", TEGRA210_MBDRC_FAST_FACTOR,
TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT, 0xffff, 0,
tegra210_mbdrc_get, tegra210_mbdrc_put),
SOC_SINGLE_RANGE_EXT_TLV("MBDRC Master Volume",
TEGRA210_MBDRC_MASTER_VOL,
TEGRA210_MBDRC_MASTER_VOL_SHIFT,
0, 0x1ff, 0,
tegra210_mbdrc_vol_get, tegra210_mbdrc_vol_put,
mdbrc_vol_tlv),
TEGRA_SOC_BYTES_EXT("MBDRC IIR Stages", TEGRA210_MBDRC_IIR_CFG,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT,
TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC In Attack Time Const", TEGRA210_MBDRC_IN_ATTACK,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT,
TEGRA210_MBDRC_IN_ATTACK_TC_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC In Release Time Const", TEGRA210_MBDRC_IN_RELEASE,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT,
TEGRA210_MBDRC_IN_RELEASE_TC_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Fast Attack Time Const", TEGRA210_MBDRC_FAST_ATTACK,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT,
TEGRA210_MBDRC_FAST_ATTACK_TC_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC In Threshold", TEGRA210_MBDRC_IN_THRESHOLD,
TEGRA210_MBDRC_FILTER_COUNT * 4, 0, 0xffffffff,
tegra210_mbdrc_threshold_get,
tegra210_mbdrc_threshold_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Out Threshold", TEGRA210_MBDRC_OUT_THRESHOLD,
TEGRA210_MBDRC_FILTER_COUNT * 4, 0, 0xffffffff,
tegra210_mbdrc_threshold_get,
tegra210_mbdrc_threshold_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Ratio", TEGRA210_MBDRC_RATIO_1ST,
TEGRA210_MBDRC_FILTER_COUNT * 5,
TEGRA210_MBDRC_RATIO_1ST_SHIFT, TEGRA210_MBDRC_RATIO_1ST_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Makeup Gain", TEGRA210_MBDRC_MAKEUP_GAIN,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT,
TEGRA210_MBDRC_MAKEUP_GAIN_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Init Gain", TEGRA210_MBDRC_INIT_GAIN,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_INIT_GAIN_SHIFT,
TEGRA210_MBDRC_INIT_GAIN_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Attack Gain", TEGRA210_MBDRC_GAIN_ATTACK,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_GAIN_ATTACK_SHIFT,
TEGRA210_MBDRC_GAIN_ATTACK_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Release Gain", TEGRA210_MBDRC_GAIN_RELEASE,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_GAIN_RELEASE_SHIFT,
TEGRA210_MBDRC_GAIN_RELEASE_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Fast Release Gain",
TEGRA210_MBDRC_FAST_RELEASE,
TEGRA210_MBDRC_FILTER_COUNT,
TEGRA210_MBDRC_FAST_RELEASE_SHIFT,
TEGRA210_MBDRC_FAST_RELEASE_MASK,
tegra210_mbdrc_band_params_get,
tegra210_mbdrc_band_params_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Low Band Biquad Coeffs",
TEGRA210_MBDRC_CFG_RAM_CTRL,
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff,
tegra210_mbdrc_biquad_coeffs_get,
tegra210_mbdrc_biquad_coeffs_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC Mid Band Biquad Coeffs",
TEGRA210_MBDRC_CFG_RAM_CTRL +
TEGRA210_MBDRC_FILTER_PARAM_STRIDE,
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff,
tegra210_mbdrc_biquad_coeffs_get,
tegra210_mbdrc_biquad_coeffs_put,
tegra210_mbdrc_param_info),
TEGRA_SOC_BYTES_EXT("MBDRC High Band Biquad Coeffs",
TEGRA210_MBDRC_CFG_RAM_CTRL +
(TEGRA210_MBDRC_FILTER_PARAM_STRIDE * 2),
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5, 0, 0xffffffff,
tegra210_mbdrc_biquad_coeffs_get,
tegra210_mbdrc_biquad_coeffs_put,
tegra210_mbdrc_param_info),
};
static bool tegra210_mbdrc_wr_reg(struct device *dev, unsigned int reg)
{
if (reg >= TEGRA210_MBDRC_IIR_CFG)
reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) %
(TEGRA210_MBDRC_FILTER_PARAM_STRIDE *
TEGRA210_MBDRC_FILTER_COUNT));
switch (reg) {
case TEGRA210_MBDRC_SOFT_RESET:
case TEGRA210_MBDRC_CG:
case TEGRA210_MBDRC_CFG ... TEGRA210_MBDRC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_mbdrc_rd_reg(struct device *dev, unsigned int reg)
{
if (tegra210_mbdrc_wr_reg(dev, reg))
return true;
if (reg >= TEGRA210_MBDRC_IIR_CFG)
reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) %
(TEGRA210_MBDRC_FILTER_PARAM_STRIDE *
TEGRA210_MBDRC_FILTER_COUNT));
switch (reg) {
case TEGRA210_MBDRC_STATUS:
return true;
default:
return false;
}
}
static bool tegra210_mbdrc_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg >= TEGRA210_MBDRC_IIR_CFG)
reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) %
(TEGRA210_MBDRC_FILTER_PARAM_STRIDE *
TEGRA210_MBDRC_FILTER_COUNT));
switch (reg) {
case TEGRA210_MBDRC_SOFT_RESET:
case TEGRA210_MBDRC_STATUS:
case TEGRA210_MBDRC_CFG_RAM_CTRL:
case TEGRA210_MBDRC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_mbdrc_precious_reg(struct device *dev, unsigned int reg)
{
if (reg >= TEGRA210_MBDRC_IIR_CFG)
reg -= ((reg - TEGRA210_MBDRC_IIR_CFG) %
(TEGRA210_MBDRC_FILTER_PARAM_STRIDE *
TEGRA210_MBDRC_FILTER_COUNT));
switch (reg) {
case TEGRA210_MBDRC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_mbdrc_regmap_cfg = {
.name = "mbdrc",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_MBDRC_MAX_REG,
.writeable_reg = tegra210_mbdrc_wr_reg,
.readable_reg = tegra210_mbdrc_rd_reg,
.volatile_reg = tegra210_mbdrc_volatile_reg,
.precious_reg = tegra210_mbdrc_precious_reg,
.reg_defaults = tegra210_mbdrc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_mbdrc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt)
{
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
const struct tegra210_mbdrc_config *conf = &mbdrc_init_config;
u32 val = 0;
unsigned int i;
regmap_read(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, &val);
val &= TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK;
if (val == TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS)
return 0;
for (i = 0; i < MBDRC_NUM_BAND; i++) {
const struct tegra210_mbdrc_band_params *params =
&conf->band_params[i];
u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE;
tegra210_mbdrc_write_ram(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL,
reg_off + TEGRA210_MBDRC_CFG_RAM_DATA,
0, (u32 *)¶ms->biquad_params[0],
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5);
}
return 0;
}
int tegra210_mbdrc_component_init(struct snd_soc_component *cmpnt)
{
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
const struct tegra210_mbdrc_config *conf = &mbdrc_init_config;
unsigned int i;
u32 val;
pm_runtime_get_sync(cmpnt->dev);
/* Initialize MBDRC registers and AHUB RAM with default params */
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK,
conf->mode << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_RMS_OFFSET_MASK,
conf->rms_off << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_PEAK_RMS_MASK,
conf->peak_rms_mode << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK,
conf->filter_structure <<
TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK,
conf->shift_ctrl << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK,
__ffs(conf->frame_size) <<
TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CHANNEL_MASK,
TEGRA210_MBDRC_CHANNEL_MASK_MASK,
conf->channel_mask << TEGRA210_MBDRC_CHANNEL_MASK_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_FAST_FACTOR,
TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK,
conf->fa_factor << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_FAST_FACTOR,
TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK,
conf->fr_factor << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT);
for (i = 0; i < MBDRC_NUM_BAND; i++) {
const struct tegra210_mbdrc_band_params *params =
&conf->band_params[i];
u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE;
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_IIR_CFG,
TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK,
params->iir_stages <<
TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_IN_ATTACK,
TEGRA210_MBDRC_IN_ATTACK_TC_MASK,
params->in_attack_tc <<
TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_IN_RELEASE,
TEGRA210_MBDRC_IN_RELEASE_TC_MASK,
params->in_release_tc <<
TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_FAST_ATTACK,
TEGRA210_MBDRC_FAST_ATTACK_TC_MASK,
params->fast_attack_tc <<
TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT);
val = (((params->in_threshold[0] >>
TEGRA210_MBDRC_THRESH_1ST_SHIFT) &
TEGRA210_MBDRC_THRESH_1ST_MASK) |
((params->in_threshold[1] >>
TEGRA210_MBDRC_THRESH_2ND_SHIFT) &
TEGRA210_MBDRC_THRESH_2ND_MASK) |
((params->in_threshold[2] >>
TEGRA210_MBDRC_THRESH_3RD_SHIFT) &
TEGRA210_MBDRC_THRESH_3RD_MASK) |
((params->in_threshold[3] >>
TEGRA210_MBDRC_THRESH_4TH_SHIFT) &
TEGRA210_MBDRC_THRESH_4TH_MASK));
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_IN_THRESHOLD,
0xffffffff, val);
val = (((params->out_threshold[0] >>
TEGRA210_MBDRC_THRESH_1ST_SHIFT) &
TEGRA210_MBDRC_THRESH_1ST_MASK) |
((params->out_threshold[1] >>
TEGRA210_MBDRC_THRESH_2ND_SHIFT) &
TEGRA210_MBDRC_THRESH_2ND_MASK) |
((params->out_threshold[2] >>
TEGRA210_MBDRC_THRESH_3RD_SHIFT) &
TEGRA210_MBDRC_THRESH_3RD_MASK) |
((params->out_threshold[3] >>
TEGRA210_MBDRC_THRESH_4TH_SHIFT) &
TEGRA210_MBDRC_THRESH_4TH_MASK));
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_OUT_THRESHOLD,
0xffffffff, val);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_RATIO_1ST,
TEGRA210_MBDRC_RATIO_1ST_MASK,
params->ratio[0] << TEGRA210_MBDRC_RATIO_1ST_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_RATIO_2ND,
TEGRA210_MBDRC_RATIO_2ND_MASK,
params->ratio[1] << TEGRA210_MBDRC_RATIO_2ND_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_RATIO_3RD,
TEGRA210_MBDRC_RATIO_3RD_MASK,
params->ratio[2] << TEGRA210_MBDRC_RATIO_3RD_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_RATIO_4TH,
TEGRA210_MBDRC_RATIO_4TH_MASK,
params->ratio[3] << TEGRA210_MBDRC_RATIO_4TH_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_RATIO_5TH,
TEGRA210_MBDRC_RATIO_5TH_MASK,
params->ratio[4] << TEGRA210_MBDRC_RATIO_5TH_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_MAKEUP_GAIN,
TEGRA210_MBDRC_MAKEUP_GAIN_MASK,
params->makeup_gain <<
TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_INIT_GAIN,
TEGRA210_MBDRC_INIT_GAIN_MASK,
params->gain_init <<
TEGRA210_MBDRC_INIT_GAIN_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_GAIN_ATTACK,
TEGRA210_MBDRC_GAIN_ATTACK_MASK,
params->gain_attack_tc <<
TEGRA210_MBDRC_GAIN_ATTACK_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_GAIN_RELEASE,
TEGRA210_MBDRC_GAIN_RELEASE_MASK,
params->gain_release_tc <<
TEGRA210_MBDRC_GAIN_RELEASE_SHIFT);
regmap_update_bits(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_FAST_RELEASE,
TEGRA210_MBDRC_FAST_RELEASE_MASK,
params->fast_release_tc <<
TEGRA210_MBDRC_FAST_RELEASE_SHIFT);
tegra210_mbdrc_write_ram(ope->mbdrc_regmap,
reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL,
reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, 0,
(u32 *)¶ms->biquad_params[0],
TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5);
}
pm_runtime_put_sync(cmpnt->dev);
snd_soc_add_component_controls(cmpnt, tegra210_mbdrc_controls,
ARRAY_SIZE(tegra210_mbdrc_controls));
return 0;
}
int tegra210_mbdrc_regmap_init(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_ope *ope = dev_get_drvdata(dev);
struct device_node *child;
struct resource mem;
void __iomem *regs;
int err;
child = of_get_child_by_name(dev->of_node, "dynamic-range-compressor");
if (!child)
return -ENODEV;
err = of_address_to_resource(child, 0, &mem);
of_node_put(child);
if (err < 0) {
dev_err(dev, "fail to get MBDRC resource\n");
return err;
}
mem.flags = IORESOURCE_MEM;
regs = devm_ioremap_resource(dev, &mem);
if (IS_ERR(regs))
return PTR_ERR(regs);
ope->mbdrc_regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_mbdrc_regmap_cfg);
if (IS_ERR(ope->mbdrc_regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(ope->mbdrc_regmap);
}
regcache_cache_only(ope->mbdrc_regmap, true);
return 0;
}
| linux-master | sound/soc/tegra/tegra210_mbdrc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra20_ac97.c - Tegra20 AC97 platform driver
*
* Copyright (c) 2012 Lucas Stach <[email protected]>
*
* Partly based on code copyright/by:
*
* Copyright (c) 2011,2012 Toradex Inc.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "tegra20_ac97.h"
#define DRV_NAME "tegra20-ac97"
static struct tegra20_ac97 *workdata;
static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
{
u32 readback;
unsigned long timeout;
/* reset line is not driven by DAC pad group, have to toggle GPIO */
gpio_set_value(workdata->reset_gpio, 0);
udelay(2);
gpio_set_value(workdata->reset_gpio, 1);
udelay(2);
timeout = jiffies + msecs_to_jiffies(100);
do {
regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
break;
usleep_range(1000, 2000);
} while (!time_after(jiffies, timeout));
}
static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
{
u32 readback;
unsigned long timeout;
/*
* although sync line is driven by the DAC pad group warm reset using
* the controller cmd is not working, have to toggle sync line
* manually.
*/
gpio_request(workdata->sync_gpio, "codec-sync");
gpio_direction_output(workdata->sync_gpio, 1);
udelay(2);
gpio_set_value(workdata->sync_gpio, 0);
udelay(2);
gpio_free(workdata->sync_gpio);
timeout = jiffies + msecs_to_jiffies(100);
do {
regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
break;
usleep_range(1000, 2000);
} while (!time_after(jiffies, timeout));
}
static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
unsigned short reg)
{
u32 readback;
unsigned long timeout;
regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
(((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
TEGRA20_AC97_CMD_BUSY);
timeout = jiffies + msecs_to_jiffies(100);
do {
regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
break;
usleep_range(1000, 2000);
} while (!time_after(jiffies, timeout));
return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
}
static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
unsigned short reg, unsigned short val)
{
u32 readback;
unsigned long timeout;
regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
TEGRA20_AC97_CMD_CMD_DATA_MASK) |
TEGRA20_AC97_CMD_BUSY);
timeout = jiffies + msecs_to_jiffies(100);
do {
regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
if (!(readback & TEGRA20_AC97_CMD_BUSY))
break;
usleep_range(1000, 2000);
} while (!time_after(jiffies, timeout));
}
static struct snd_ac97_bus_ops tegra20_ac97_ops = {
.read = tegra20_ac97_codec_read,
.write = tegra20_ac97_codec_write,
.reset = tegra20_ac97_codec_reset,
.warm_reset = tegra20_ac97_codec_warm_reset,
};
static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
{
regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
TEGRA20_AC97_CTRL_PCM_DAC_EN |
TEGRA20_AC97_CTRL_STM_EN,
TEGRA20_AC97_CTRL_PCM_DAC_EN |
TEGRA20_AC97_CTRL_STM_EN);
}
static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
{
regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
}
static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
{
regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
}
static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
{
regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
}
static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra20_ac97_start_playback(ac97);
else
tegra20_ac97_start_capture(ac97);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra20_ac97_stop_playback(ac97);
else
tegra20_ac97_stop_capture(ac97);
break;
default:
return -EINVAL;
}
return 0;
}
static int tegra20_ac97_probe(struct snd_soc_dai *dai)
{
struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &ac97->playback_dma_data,
&ac97->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
.probe = tegra20_ac97_probe,
.trigger = tegra20_ac97_trigger,
};
static struct snd_soc_dai_driver tegra20_ac97_dai = {
.name = "tegra-ac97-pcm",
.playback = {
.stream_name = "PCM Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "PCM Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tegra20_ac97_dai_ops,
};
static const struct snd_soc_component_driver tegra20_ac97_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_AC97_CTRL:
case TEGRA20_AC97_CMD:
case TEGRA20_AC97_STATUS1:
case TEGRA20_AC97_FIFO1_SCR:
case TEGRA20_AC97_FIFO_TX1:
case TEGRA20_AC97_FIFO_RX1:
return true;
default:
break;
}
return false;
}
static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_AC97_STATUS1:
case TEGRA20_AC97_FIFO1_SCR:
case TEGRA20_AC97_FIFO_TX1:
case TEGRA20_AC97_FIFO_RX1:
return true;
default:
break;
}
return false;
}
static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA20_AC97_FIFO_TX1:
case TEGRA20_AC97_FIFO_RX1:
return true;
default:
break;
}
return false;
}
static const struct regmap_config tegra20_ac97_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA20_AC97_FIFO_RX1,
.writeable_reg = tegra20_ac97_wr_rd_reg,
.readable_reg = tegra20_ac97_wr_rd_reg,
.volatile_reg = tegra20_ac97_volatile_reg,
.precious_reg = tegra20_ac97_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static int tegra20_ac97_platform_probe(struct platform_device *pdev)
{
struct tegra20_ac97 *ac97;
struct resource *mem;
void __iomem *regs;
int ret = 0;
ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
GFP_KERNEL);
if (!ac97) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, ac97);
ac97->reset = devm_reset_control_get_exclusive(&pdev->dev, "ac97");
if (IS_ERR(ac97->reset)) {
dev_err(&pdev->dev, "Can't retrieve ac97 reset\n");
ret = PTR_ERR(ac97->reset);
goto err;
}
ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ac97->clk_ac97)) {
dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
ret = PTR_ERR(ac97->clk_ac97);
goto err;
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
goto err_clk_put;
}
ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra20_ac97_regmap_config);
if (IS_ERR(ac97->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
ret = PTR_ERR(ac97->regmap);
goto err_clk_put;
}
ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
"nvidia,codec-reset-gpio", 0);
if (gpio_is_valid(ac97->reset_gpio)) {
ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
GPIOF_OUT_INIT_HIGH, "codec-reset");
if (ret) {
dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
goto err_clk_put;
}
} else {
dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
ret = -EINVAL;
goto err_clk_put;
}
ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
"nvidia,codec-sync-gpio", 0);
if (!gpio_is_valid(ac97->sync_gpio)) {
dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
ret = -EINVAL;
goto err_clk_put;
}
ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
ac97->capture_dma_data.maxburst = 4;
ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
ac97->playback_dma_data.maxburst = 4;
ret = reset_control_assert(ac97->reset);
if (ret) {
dev_err(&pdev->dev, "Failed to assert AC'97 reset: %d\n", ret);
goto err_clk_put;
}
ret = clk_prepare_enable(ac97->clk_ac97);
if (ret) {
dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
goto err_clk_put;
}
usleep_range(10, 100);
ret = reset_control_deassert(ac97->reset);
if (ret) {
dev_err(&pdev->dev, "Failed to deassert AC'97 reset: %d\n", ret);
goto err_clk_disable_unprepare;
}
ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
if (ret) {
dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
goto err_clk_disable_unprepare;
}
ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
&tegra20_ac97_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
ret = -ENOMEM;
goto err_clk_disable_unprepare;
}
ret = tegra_pcm_platform_register(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
goto err_unregister_component;
}
/* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
workdata = ac97;
return 0;
err_unregister_component:
snd_soc_unregister_component(&pdev->dev);
err_clk_disable_unprepare:
clk_disable_unprepare(ac97->clk_ac97);
err_clk_put:
err:
snd_soc_set_ac97_ops(NULL);
return ret;
}
static void tegra20_ac97_platform_remove(struct platform_device *pdev)
{
struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
tegra_pcm_platform_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
clk_disable_unprepare(ac97->clk_ac97);
snd_soc_set_ac97_ops(NULL);
}
static const struct of_device_id tegra20_ac97_of_match[] = {
{ .compatible = "nvidia,tegra20-ac97", },
{},
};
static struct platform_driver tegra20_ac97_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = tegra20_ac97_of_match,
},
.probe = tegra20_ac97_platform_probe,
.remove_new = tegra20_ac97_platform_remove,
};
module_platform_driver(tegra20_ac97_driver);
MODULE_AUTHOR("Lucas Stach");
MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);
| linux-master | sound/soc/tegra/tegra20_ac97.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_sfc.c - Tegra210 SFC driver
//
// Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_sfc.h"
#include "tegra_cif.h"
#define UNSUPP_CONV ((void *)(-EOPNOTSUPP))
#define BYPASS_CONV NULL
static const struct reg_default tegra210_sfc_reg_defaults[] = {
{ TEGRA210_SFC_RX_INT_MASK, 0x00000001},
{ TEGRA210_SFC_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_SFC_TX_INT_MASK, 0x00000001},
{ TEGRA210_SFC_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_SFC_CG, 0x1},
{ TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000},
};
static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = {
8000,
11025,
16000,
22050,
24000,
32000,
44100,
48000,
64000,
88200,
96000,
176400,
192000,
};
/* coeff RAM tables required for SFC */
static u32 coef_8to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00235204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0000015f,//input gain
0x00a7909c, 0xff241c71, 0x005f5e00,
0xffca77f4, 0xff20dd50, 0x006855eb,
0xff86c552, 0xff18137a, 0x00773648,
0x00000001//output gain
};
static u32 coef_8to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_8to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00230204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000001//output gain
};
static u32 coef_8to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x0000a105,//header
0x000005e1,//input gain
0x00dca92f, 0xff45647a, 0x0046b59c,
0x00429d1e, 0xff4fec62, 0x00516d30,
0xffdea779, 0xff5e08ba, 0x0060185e,
0xffafbab2, 0xff698d5a, 0x006ce3ae,
0xff9a82d2, 0xff704674, 0x007633c5,
0xff923433, 0xff721128, 0x007cff42,
0x00000003//output gain
};
static u32 coef_8to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_8to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x0156105,//interpolation + IIR filter
0x0000d649,//input gain
0x00e87afb, 0xff5f69d0, 0x003df3cf,
0x007ce488, 0xff99a5c8, 0x0056a6a0,
0x00344928, 0xffcba3e5, 0x006be470,
0x00137aa7, 0xffe60276, 0x00773410,
0x0005fa2a, 0xfff1ac11, 0x007c795b,
0x00012d36, 0xfff5eca2, 0x007f10ef,
0x00000002,//ouptut gain
0x0021a102,//interpolation + IIR filter
0x00000e00,//input gain
0x00e2e000, 0xff6e1a00, 0x002aaa00,
0x00610a00, 0xff5dda00, 0x003ccc00,
0x00163a00, 0xff3c0400, 0x00633200,
0x00000003,//Output gain
0x00000204,//Farrow filter
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_8to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00156105,//interpolation + IIR Filter
0x0000d649,//input gain
0x00e87afb, 0xff5f69d0, 0x003df3cf,
0x007ce488, 0xff99a5c8, 0x0056a6a0,
0x00344928, 0xffcba3e5, 0x006be470,
0x00137aa7, 0xffe60276, 0x00773410,
0x0005fa2a, 0xfff1ac11, 0x007c795b,
0x00012d36, 0xfff5eca2, 0x007f10ef,
0x00000002,//ouptut gain
0x0000a102,//interpolation + IIR filter
0x00000e00,//input gain
0x00e2e000, 0xff6e1a00, 0x002aaa00,
0x00610a00, 0xff5dda00, 0x003ccc00,
0x00163a00, 0xff3c0400, 0x00633200,
0x00000003//output gain
};
static u32 coef_8to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x0024a102,//header
0x0000007d,//input gain
0x007d1f20, 0xff1a540e, 0x00678bf9,
0xff916625, 0xff16b0ff, 0x006e433a,
0xff5af660, 0xff0eb91f, 0x00797356,
0x00000003,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_8to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x0000a102,//header
0x0000007d,//input gain
0x007d1f20, 0xff1a540e, 0x00678bf9,
0xff916625, 0xff16b0ff, 0x006e433a,
0xff5af660, 0xff0eb91f, 0x00797356,
0x00000003//output gain
};
static u32 coef_11to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0000015f,//input gain
0x00a7909c, 0xff241c71, 0x005f5e00,
0xffca77f4, 0xff20dd50, 0x006855eb,
0xff86c552, 0xff18137a, 0x00773648,
0x00000002,//output gain
0x00186102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000002,//output gain
0x00239204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_11to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00009204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_11to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_11to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_11to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00009204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_11to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_11to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_11to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00006102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002//output gain
};
static u32 coef_11to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_16to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_16to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000fa103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000003,//output gain
0x001a5204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_16to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00235204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0000015f,//input gain
0x00a7909c, 0xff241c71, 0x005f5e00,
0xffca77f4, 0xff20dd50, 0x006855eb,
0xff86c552, 0xff18137a, 0x00773648,
0x00000001//output gain
};
static u32 coef_16to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x0015a105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000003,//output gain
0x00005105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000001//output gain
};
static u32 coef_16to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_16to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00156105,//interpolation + IIR filter
0x0000d649,//input gain
0x00e87afb, 0xff5f69d0, 0x003df3cf,
0x007ce488, 0xff99a5c8, 0x0056a6a0,
0x00344928, 0xffcba3e5, 0x006be470,
0x00137aa7, 0xffe60276, 0x00773410,
0x0005fa2a, 0xfff1ac11, 0x007c795b,
0x00012d36, 0xfff5eca2, 0x007f10ef,
0x00000002,//output gain
0x0021a102,//interpolation + IIR filter
0x00000e00,//input gain
0x00e2e000, 0xff6e1a00, 0x002aaa00,
0x00610a00, 0xff5dda00, 0x003ccc00,
0x00163a00, 0xff3c0400, 0x00633200,
0x00000003,//output gain
0x002c0204,//Farrow Filter
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005101,//IIR Filter + Decimator
0x0000203c,//input gain
0x00f52d35, 0xff2e2162, 0x005a21e0,
0x00c6f0f0, 0xff2ecd69, 0x006fa78d,
0x00000001//output gain
};
static u32 coef_16to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x0000a105,//interpolation + IIR Filter
0x00000784,//input gain
0x00cc516e, 0xff2c9639, 0x005ad5b3,
0x0013ad0d, 0xff3d4799, 0x0063ce75,
0xffb6f398, 0xff5138d1, 0x006e9e1f,
0xff9186e5, 0xff5f96a4, 0x0076a86e,
0xff82089c, 0xff676b81, 0x007b9f8a,
0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
0x00000003//output gain
};
static u32 coef_16to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_16to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0000a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003//output gain
};
static u32 coef_16to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x0024a102,//header
0x0000007d,//input gain
0x007d1f20, 0xff1a540e, 0x00678bf9,
0xff916625, 0xff16b0ff, 0x006e433a,
0xff5af660, 0xff0eb91f, 0x00797356,
0x00000003,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_16to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x0000a102,//header
0x0000007d,//input gain
0x007d1f20, 0xff1a540e, 0x00678bf9,
0xff916625, 0xff16b0ff, 0x006e433a,
0xff5af660, 0xff0eb91f, 0x00797356,
0x00000003//output gain
};
static u32 coef_22to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000002,//output gain
0x00179204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_22to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_22to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0000015f,//input gain
0x00a7909c, 0xff241c71, 0x005f5e00,
0xffca77f4, 0xff20dd50, 0x006855eb,
0xff86c552, 0xff18137a, 0x00773648,
0x00000002,//output gain
0x00186102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000002,//output gain
0x00239204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_22to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00235204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d029,//input gain
0x00f2a98b, 0xff92aa71, 0x001fcd16,
0x00ae9004, 0xffb85140, 0x0041813a,
0x007f8ed1, 0xffd585fc, 0x006a69e6,
0x00000001//output gain
};
static u32 coef_22to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00009204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_22to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_22to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_22to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_22to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_22to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00006102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002//output gain
};
static u32 coef_22to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_24to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00009105,//header
0x000005e1,//input gain
0x00dca92f, 0xff45647a, 0x0046b59c,
0x00429d1e, 0xff4fec62, 0x00516d30,
0xffdea779, 0xff5e08ba, 0x0060185e,
0xffafbab2, 0xff698d5a, 0x006ce3ae,
0xff9a82d2, 0xff704674, 0x007633c5,
0xff923433, 0xff721128, 0x007cff42,
0x00000001//output gain
};
static u32 coef_24to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000f6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x001a5204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_24to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00156105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000002,//output gain
0x00009105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000001//output gain
};
static u32 coef_24to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d029,//input gain
0x00f2a98b, 0xff92aa71, 0x001fcd16,
0x00ae9004, 0xffb85140, 0x0041813a,
0x007f8ed1, 0xffd585fc, 0x006a69e6,
0x00000002,//output gain
0x001b6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x00265204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_24to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00009102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001//output gain
};
static u32 coef_24to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00230204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x00001685,//input gain
0x00f53ae9, 0xff52f196, 0x003e3e08,
0x00b9f857, 0xff5d8985, 0x0050070a,
0x008c3e86, 0xff6053f0, 0x006d98ef,
0x00000001//output gain
};
static u32 coef_24to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_24to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x002f0204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x00000138,//input gain
0x00d5d232, 0xff2a3bf8, 0x005a785c,
0x0034001b, 0xff283109, 0x006462a6,
0xffe6746a, 0xff1fb09c, 0x00758a91,
0x00000001//output gain
};
static u32 coef_24to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_24to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_24to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00006102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002//output gain
};
static u32 coef_32to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_32to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000ca102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000003,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x0000d102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001//output gain
};
static u32 coef_32to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_32to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000fa103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000003,//output gain
0x001a5204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_32to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000ca102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000003,//output gain
0x0000d102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001//output gain
};
static u32 coef_32to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00235204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0000015f,//input gain
0x00a7909c, 0xff241c71, 0x005f5e00,
0xffca77f4, 0xff20dd50, 0x006855eb,
0xff86c552, 0xff18137a, 0x00773648,
0x00000001//output gain
};
static u32 coef_32to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x0015a105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000003,//output gain
0x00005105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000001//output gain
};
static u32 coef_32to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00230204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000001//output gain
};
static u32 coef_32to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x0000a105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000003//output gain
};
static u32 coef_32to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0018a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003,//output gain
0x00000204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_32to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x0000a102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000003//output gain
};
static u32 coef_44to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00120104,//IIR Filter
0x00000af2,//input gain
0x0057eebe, 0xff1e9863, 0x00652604,
0xff7206ea, 0xff22ad7e, 0x006d47e1,
0xff42a4d7, 0xff26e722, 0x0075fd83,
0xff352f66, 0xff29312b, 0x007b986b,
0xff310a07, 0xff296f51, 0x007eca7c,
0x00000001,//output gain
0x001d9204,//Farrow Filter + decimation
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005105,//IIR Filter + Decimator
0x0000d649,//input gain
0x00e87afb, 0xff5f69d0, 0x003df3cf,
0x007ce488, 0xff99a5c8, 0x0056a6a0,
0x00344928, 0xffcba3e5, 0x006be470,
0x00137aa7, 0xffe60276, 0x00773410,
0x0005fa2a, 0xfff1ac11, 0x007c795b,
0x00012d36, 0xfff5eca2, 0x007f10ef,
0x00000001//output gain
};
static u32 coef_44to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_44to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00126104,//IIR Filter + interpolation
0x00000af2,//input gain
0x0057eebe, 0xff1e9863, 0x00652604,
0xff7206ea, 0xff22ad7e, 0x006d47e1,
0xff42a4d7, 0xff26e722, 0x0075fd83,
0xff352f66, 0xff29312b, 0x007b986b,
0xff310a07, 0xff296f51, 0x007eca7c,
0x00000002,//output gain
0x001d9204,//Farrow Filter + decimation
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005105,//IIR Filter + Decimator
0x0000d649,//input gain
0x00e87afb, 0xff5f69d0, 0x003df3cf,
0x007ce488, 0xff99a5c8, 0x0056a6a0,
0x00344928, 0xffcba3e5, 0x006be470,
0x00137aa7, 0xffe60276, 0x00773410,
0x0005fa2a, 0xfff1ac11, 0x007c795b,
0x00012d36, 0xfff5eca2, 0x007f10ef,
0x00000001//output gain
};
static u32 coef_44to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_44to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x00001685,//input gain
0x00f53ae9, 0xff52f196, 0x003e3e08,
0x00b9f857, 0xff5d8985, 0x0050070a,
0x008c3e86, 0xff6053f0, 0x006d98ef,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_44to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0000015f,//input gain
0x00a7909c, 0xff241c71, 0x005f5e00,
0xffca77f4, 0xff20dd50, 0x006855eb,
0xff86c552, 0xff18137a, 0x00773648,
0x00000002,//output gain
0x00186102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000002,//output gain
0x00239204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_44to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00235204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d029,//input gain
0x00f2a98b, 0xff92aa71, 0x001fcd16,
0x00ae9004, 0xffb85140, 0x0041813a,
0x007f8ed1, 0xffd585fc, 0x006a69e6,
0x00000001//output gain
};
static u32 coef_44to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_44to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_44to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_44to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_48to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c9102,//IIR Filter + Decimator
0x00000e00,//input gain
0x00e2e000, 0xff6e1a00, 0x002aaa00,
0x00610a00, 0xff5dda00, 0x003ccc00,
0x00163a00, 0xff3c0400, 0x00633200,
0x00000001,//output gain
0x00005105,//IIR Filter + Decimator
0x0000d649,//input gain
0x00e87afb, 0xff5f69d0, 0x003df3cf,
0x007ce488, 0xff99a5c8, 0x0056a6a0,
0x00344928, 0xffcba3e5, 0x006be470,
0x00137aa7, 0xffe60276, 0x00773410,
0x0005fa2a, 0xfff1ac11, 0x007c795b,
0x00012d36, 0xfff5eca2, 0x007f10ef,
0x00000001//output gain
};
static u32 coef_48to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_48to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00009105,//IIR Filter + Decimator
0x00000784,//input gain
0x00cc516e, 0xff2c9639, 0x005ad5b3,
0x0013ad0d, 0xff3d4799, 0x0063ce75,
0xffb6f398, 0xff5138d1, 0x006e9e1f,
0xff9186e5, 0xff5f96a4, 0x0076a86e,
0xff82089c, 0xff676b81, 0x007b9f8a,
0xff7c48a5, 0xff6a31e7, 0x007ebb7b,
0x00000001//output gain
};
static u32 coef_48to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000f6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x001a5204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_48to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_48to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00156105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000002,//output gain
0x00009105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000001//output gain
};
static u32 coef_48to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d029,//input gain
0x00f2a98b, 0xff92aa71, 0x001fcd16,
0x00ae9004, 0xffb85140, 0x0041813a,
0x007f8ed1, 0xffd585fc, 0x006a69e6,
0x00000002,//output gain
0x001b6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x00265204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_48to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00230204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x00001685,//input gain
0x00f53ae9, 0xff52f196, 0x003e3e08,
0x00b9f857, 0xff5d8985, 0x0050070a,
0x008c3e86, 0xff6053f0, 0x006d98ef,
0x00000001//output gain
};
static u32 coef_48to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002//output gain
};
static u32 coef_48to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00186102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00246102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x002f0204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x00000138,//input gain
0x00d5d232, 0xff2a3bf8, 0x005a785c,
0x0034001b, 0xff283109, 0x006462a6,
0xffe6746a, 0xff1fb09c, 0x00758a91,
0x00000001//output gain
};
static u32 coef_48to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000002,//output gain
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_88to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x00000057,//input gain
0x00a8e717, 0xff1c748d, 0x0065b976,
0xffcbccab, 0xff190aff, 0x006cc1cf,
0xff871ce1, 0xff10d878, 0x0078cfc5,
0x00000001,//output gain
0x00179204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000001,//output gain
0x00185102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000001,//output gain
0x00179204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x00001685,//input gain
0x00f53ae9, 0xff52f196, 0x003e3e08,
0x00b9f857, 0xff5d8985, 0x0050070a,
0x008c3e86, 0xff6053f0, 0x006d98ef,
0x00000001,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000002,//output gain
0x00179204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x00001685,//input gain
0x00f53ae9, 0xff52f196, 0x003e3e08,
0x00b9f857, 0xff5d8985, 0x0050070a,
0x008c3e86, 0xff6053f0, 0x006d98ef,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_88to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_88to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002//output gain
};
static u32 coef_88to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000002,//output gain
0x00186102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_96to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c9102,//header
0x0000007d,//input gain
0x007d1f20, 0xff1a540e, 0x00678bf9,
0xff916625, 0xff16b0ff, 0x006e433a,
0xff5af660, 0xff0eb91f, 0x00797356,
0x00000001,//output gain
0x00185102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000001,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c9102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00009105,//header
0x00000292,//input gain
0x00e4320a, 0xff41d2d9, 0x004911ac,
0x005dd9e3, 0xff4c7d80, 0x0052103e,
0xfff8ebef, 0xff5b6fab, 0x005f0a0d,
0xffc4b414, 0xff68582c, 0x006b38e5,
0xffabb861, 0xff704bec, 0x0074de52,
0xffa19f4c, 0xff729059, 0x007c7e90,
0x00000001//output gain
};
static u32 coef_96to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000f6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x001a5204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_96to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000f6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x001a0204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001//output gain
};
static u32 coef_96to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000f6103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002,//output gain
0x001b6102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000002,//output gain
0x00260204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000001//output gain
};
static u32 coef_96to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00006103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000002//output gain
};
static u32 coef_176to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x00000057,//input gain
0x00a8e717, 0xff1c748d, 0x0065b976,
0xffcbccab, 0xff190aff, 0x006cc1cf,
0xff871ce1, 0xff10d878, 0x0078cfc5,
0x00000001,//output gain
0x00179204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_176to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000001,//output gain
0x00185102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_176to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x00000138,//input gain
0x00d5d232, 0xff2a3bf8, 0x005a785c,
0x0034001b, 0xff283109, 0x006462a6,
0xffe6746a, 0xff1fb09c, 0x00758a91,
0x00000001,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_176to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x000005f3,//input gain
0x00d816d6, 0xff385383, 0x004fe566,
0x003c548d, 0xff38c23d, 0x005d0b1c,
0xfff02f7d, 0xff31e983, 0x0072d65d,
0x00000001,//output gain
0x00179204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_176to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_176to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x00001685,//input gain
0x00f53ae9, 0xff52f196, 0x003e3e08,
0x00b9f857, 0xff5d8985, 0x0050070a,
0x008c3e86, 0xff6053f0, 0x006d98ef,
0x00000001,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_176to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001//output gain
};
static u32 coef_176to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000001//output gain
};
static u32 coef_176to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000002,//output gain
0x00005204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000
};
static u32 coef_192to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c9102,//header
0x0000007d,//input gain
0x007d1f20, 0xff1a540e, 0x00678bf9,
0xff916625, 0xff16b0ff, 0x006e433a,
0xff5af660, 0xff0eb91f, 0x00797356,
0x00000001,//output gain
0x00185102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_192to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c0102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000001,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_192to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000001,//output gain
0x00185102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_192to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c9102,//header
0x000005d6,//input gain
0x00c6543e, 0xff342935, 0x0052f116,
0x000a1d78, 0xff3330c0, 0x005f88a3,
0xffbee7c0, 0xff2b5ba5, 0x0073eb26,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_192to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00235102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_192to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c5102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001,//output gain
0x00005102,//header
0x0001d727,//input gain
0x00fc2fc7, 0xff9bb27b, 0x001c564c,
0x00e55557, 0xffcadd5b, 0x003d80ba,
0x00d13397, 0xfff232f8, 0x00683337,
0x00000001//output gain
};
static u32 coef_192to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000002,//output gain
0x00175204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x000013d9,//input gain
0x00ebd477, 0xff4ce383, 0x0042049d,
0x0089c278, 0xff54414d, 0x00531ded,
0x004a5e07, 0xff53cf41, 0x006efbdc,
0x00000001//output gain
};
static u32 coef_192to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x00005103,//header
0x000001e0,//input gain
0x00de44c0, 0xff380b7f, 0x004ffc73,
0x00494b44, 0xff3d493a, 0x005908bf,
0xffe9a3c8, 0xff425647, 0x006745f7,
0xffc42d61, 0xff40a6c7, 0x00776709,
0x00000001//output gain
};
static u32 coef_192to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {
0x000c6102,//header
0x000000af,//input gain
0x00c65663, 0xff23d2ce, 0x005f97d6,
0x00086ad6, 0xff20ec4f, 0x00683201,
0xffbbbef6, 0xff184447, 0x00770963,
0x00000002,//output gain
0x00170204,//farrow
0x000aaaab,
0xffaaaaab,
0xfffaaaab,
0x00555555,
0xff600000,
0xfff55555,
0x00155555,
0x00055555,
0xffeaaaab,
0x00200000,
0x00005102,//header
0x0000010a,//input gain
0x00c93dc4, 0xff26f5f6, 0x005d1041,
0x001002c4, 0xff245b76, 0x00666002,
0xffc30a45, 0xff1baecd, 0x00765921,
0x00000001//output gain
};
/*
* Coefficient table for various sample rate conversions. The sample
* rates available are as per tegra210_sfc_rates[].
*/
static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {
/* Convertions from 8 kHz */
{
BYPASS_CONV,
coef_8to11,
coef_8to16,
coef_8to22,
coef_8to24,
coef_8to32,
coef_8to44,
coef_8to48,
UNSUPP_CONV,
coef_8to88,
coef_8to96,
UNSUPP_CONV,
UNSUPP_CONV,
},
/* Convertions from 11.025 kHz */
{
coef_11to8,
BYPASS_CONV,
coef_11to16,
coef_11to22,
coef_11to24,
coef_11to32,
coef_11to44,
coef_11to48,
UNSUPP_CONV,
coef_11to88,
coef_11to96,
UNSUPP_CONV,
UNSUPP_CONV,
},
/* Convertions from 16 kHz */
{
coef_16to8,
coef_16to11,
BYPASS_CONV,
coef_16to22,
coef_16to24,
coef_16to32,
coef_16to44,
coef_16to48,
UNSUPP_CONV,
coef_16to88,
coef_16to96,
coef_16to176,
coef_16to192,
},
/* Convertions from 22.05 kHz */
{
coef_22to8,
coef_22to11,
coef_22to16,
BYPASS_CONV,
coef_22to24,
coef_22to32,
coef_22to44,
coef_22to48,
UNSUPP_CONV,
coef_22to88,
coef_22to96,
coef_22to176,
coef_22to192,
},
/* Convertions from 24 kHz */
{
coef_24to8,
coef_24to11,
coef_24to16,
coef_24to22,
BYPASS_CONV,
coef_24to32,
coef_24to44,
coef_24to48,
UNSUPP_CONV,
coef_24to88,
coef_24to96,
coef_24to176,
coef_24to192,
},
/* Convertions from 32 kHz */
{
coef_32to8,
coef_32to11,
coef_32to16,
coef_32to22,
coef_32to24,
BYPASS_CONV,
coef_32to44,
coef_32to48,
UNSUPP_CONV,
coef_32to88,
coef_32to96,
coef_32to176,
coef_32to192,
},
/* Convertions from 44.1 kHz */
{
coef_44to8,
coef_44to11,
coef_44to16,
coef_44to22,
coef_44to24,
coef_44to32,
BYPASS_CONV,
coef_44to48,
UNSUPP_CONV,
coef_44to88,
coef_44to96,
coef_44to176,
coef_44to192,
},
/* Convertions from 48 kHz */
{
coef_48to8,
coef_48to11,
coef_48to16,
coef_48to22,
coef_48to24,
coef_48to32,
coef_48to44,
BYPASS_CONV,
UNSUPP_CONV,
coef_48to88,
coef_48to96,
coef_48to176,
coef_48to192,
},
/* Convertions from 64 kHz */
{
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
UNSUPP_CONV,
},
/* Convertions from 88.2 kHz */
{
coef_88to8,
coef_88to11,
coef_88to16,
coef_88to22,
coef_88to24,
coef_88to32,
coef_88to44,
coef_88to48,
UNSUPP_CONV,
BYPASS_CONV,
coef_88to96,
coef_88to176,
coef_88to192,
},
/* Convertions from 96 kHz */
{ coef_96to8,
coef_96to11,
coef_96to16,
coef_96to22,
coef_96to24,
coef_96to32,
coef_96to44,
coef_96to48,
UNSUPP_CONV,
coef_96to88,
BYPASS_CONV,
coef_96to176,
coef_96to192,
},
/* Convertions from 176.4 kHz */
{
UNSUPP_CONV,
UNSUPP_CONV,
coef_176to16,
coef_176to22,
coef_176to24,
coef_176to32,
coef_176to44,
coef_176to48,
UNSUPP_CONV,
coef_176to88,
coef_176to96,
BYPASS_CONV,
coef_176to192,
},
/* Convertions from 192 kHz */
{
UNSUPP_CONV,
UNSUPP_CONV,
coef_192to16,
coef_192to22,
coef_192to24,
coef_192to32,
coef_192to44,
coef_192to48,
UNSUPP_CONV,
coef_192to88,
coef_192to96,
coef_192to176,
BYPASS_CONV,
},
};
static int __maybe_unused tegra210_sfc_runtime_suspend(struct device *dev)
{
struct tegra210_sfc *sfc = dev_get_drvdata(dev);
regcache_cache_only(sfc->regmap, true);
regcache_mark_dirty(sfc->regmap);
return 0;
}
static int __maybe_unused tegra210_sfc_runtime_resume(struct device *dev)
{
struct tegra210_sfc *sfc = dev_get_drvdata(dev);
regcache_cache_only(sfc->regmap, false);
regcache_sync(sfc->regmap);
return 0;
}
static inline void tegra210_sfc_write_ram(struct regmap *regmap,
s32 *data)
{
int i;
regmap_write(regmap, TEGRA210_SFC_CFG_RAM_CTRL,
TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN |
TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN |
TEGRA210_SFC_RAM_CTRL_RW_WRITE);
for (i = 0; i < TEGRA210_SFC_COEF_RAM_DEPTH; i++)
regmap_write(regmap, TEGRA210_SFC_CFG_RAM_DATA, data[i]);
}
static int tegra210_sfc_write_coeff_ram(struct snd_soc_component *cmpnt)
{
struct tegra210_sfc *sfc = dev_get_drvdata(cmpnt->dev);
s32 *coeff_ram;
/* Bypass */
if (sfc->srate_in == sfc->srate_out)
return 0;
coeff_ram = coef_addr_table[sfc->srate_in][sfc->srate_out];
if (IS_ERR_OR_NULL(coeff_ram)) {
dev_err(cmpnt->dev,
"Conversion from %d to %d Hz is not supported\n",
sfc->srate_in, sfc->srate_out);
return PTR_ERR_OR_ZERO(coeff_ram);
}
tegra210_sfc_write_ram(sfc->regmap, coeff_ram);
regmap_update_bits(sfc->regmap,
TEGRA210_SFC_COEF_RAM,
TEGRA210_SFC_COEF_RAM_EN,
TEGRA210_SFC_COEF_RAM_EN);
return 0;
}
static int tegra210_sfc_set_audio_cif(struct tegra210_sfc *sfc,
struct snd_pcm_hw_params *params,
unsigned int reg)
{
unsigned int channels, audio_bits, path;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EOPNOTSUPP;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = TEGRA_ACIF_BITS_32;
if (reg == TEGRA210_SFC_RX_CIF_CTRL)
path = SFC_RX_PATH;
else
path = SFC_TX_PATH;
cif_conf.stereo_conv = sfc->stereo_to_mono[path];
cif_conf.mono_conv = sfc->mono_to_stereo[path];
tegra_set_cif(sfc->regmap, reg, &cif_conf);
return 0;
}
static int tegra210_sfc_soft_reset(struct tegra210_sfc *sfc)
{
u32 val;
/*
* Soft Reset: Below performs module soft reset which clears
* all FSM logic, flushes flow control of FIFO and resets the
* state register. It also brings module back to disabled
* state (without flushing the data in the pipe).
*/
regmap_update_bits(sfc->regmap, TEGRA210_SFC_SOFT_RESET,
TEGRA210_SFC_SOFT_RESET_EN, 1);
return regmap_read_poll_timeout(sfc->regmap,
TEGRA210_SFC_SOFT_RESET,
val,
!(val & TEGRA210_SFC_SOFT_RESET_EN),
10, 10000);
}
static int tegra210_sfc_rate_to_idx(struct device *dev, int rate,
int *rate_idx)
{
int i;
for (i = 0; i < ARRAY_SIZE(tegra210_sfc_rates); i++) {
if (rate == tegra210_sfc_rates[i]) {
*rate_idx = i;
return 0;
}
}
dev_err(dev, "Sample rate %d Hz is not supported\n", rate);
return -EOPNOTSUPP;
}
static int tegra210_sfc_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
int err;
regmap_update_bits(sfc->regmap, TEGRA210_SFC_COEF_RAM,
TEGRA210_SFC_COEF_RAM_EN, 0);
err = tegra210_sfc_soft_reset(sfc);
if (err < 0) {
dev_err(dai->dev, "Failed to reset SFC in %s, err = %d\n",
__func__, err);
return err;
}
return 0;
}
static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
struct device *dev = dai->dev;
int err;
err = tegra210_sfc_rate_to_idx(dev, params_rate(params),
&sfc->srate_in);
if (err < 0)
return err;
err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_RX_CIF_CTRL);
if (err < 0) {
dev_err(dev, "Can't set SFC RX CIF: %d\n", err);
return err;
}
regmap_write(sfc->regmap, TEGRA210_SFC_RX_FREQ, sfc->srate_in);
return err;
}
static int tegra210_sfc_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);
struct device *dev = dai->dev;
int err;
err = tegra210_sfc_rate_to_idx(dev, params_rate(params),
&sfc->srate_out);
if (err < 0)
return err;
err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_TX_CIF_CTRL);
if (err < 0) {
dev_err(dev, "Can't set SFC TX CIF: %d\n", err);
return err;
}
regmap_write(sfc->regmap, TEGRA210_SFC_TX_FREQ, sfc->srate_out);
return 0;
}
static int tegra210_sfc_init(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
return tegra210_sfc_write_coeff_ram(cmpnt);
}
static int tegra210_sfc_iget_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_RX_PATH];
return 0;
}
static int tegra210_sfc_iput_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == sfc->stereo_to_mono[SFC_RX_PATH])
return 0;
sfc->stereo_to_mono[SFC_RX_PATH] = value;
return 1;
}
static int tegra210_sfc_iget_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_RX_PATH];
return 0;
}
static int tegra210_sfc_iput_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == sfc->mono_to_stereo[SFC_RX_PATH])
return 0;
sfc->mono_to_stereo[SFC_RX_PATH] = value;
return 1;
}
static int tegra210_sfc_oget_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_TX_PATH];
return 0;
}
static int tegra210_sfc_oput_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == sfc->stereo_to_mono[SFC_TX_PATH])
return 0;
sfc->stereo_to_mono[SFC_TX_PATH] = value;
return 1;
}
static int tegra210_sfc_oget_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_TX_PATH];
return 0;
}
static int tegra210_sfc_oput_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == sfc->mono_to_stereo[SFC_TX_PATH])
return 0;
sfc->mono_to_stereo[SFC_TX_PATH] = value;
return 1;
}
static const struct snd_soc_dai_ops tegra210_sfc_in_dai_ops = {
.hw_params = tegra210_sfc_in_hw_params,
.startup = tegra210_sfc_startup,
};
static const struct snd_soc_dai_ops tegra210_sfc_out_dai_ops = {
.hw_params = tegra210_sfc_out_hw_params,
};
static struct snd_soc_dai_driver tegra210_sfc_dais[] = {
{
.name = "SFC-RX-CIF",
.playback = {
.stream_name = "RX-CIF-Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "RX-CIF-Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra210_sfc_in_dai_ops,
},
{
.name = "SFC-TX-CIF",
.playback = {
.stream_name = "TX-CIF-Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "TX-CIF-Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra210_sfc_out_dai_ops,
},
};
static const struct snd_soc_dapm_widget tegra210_sfc_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_SFC_ENABLE,
TEGRA210_SFC_EN_SHIFT, 0,
tegra210_sfc_init, SND_SOC_DAPM_PRE_PMU),
};
#define RESAMPLE_ROUTE(sname) \
{ "RX XBAR-" sname, NULL, "XBAR-TX" }, \
{ "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \
{ "RX", NULL, "RX-CIF-" sname }, \
{ "TX-CIF-" sname, NULL, "TX" }, \
{ "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \
{ "XBAR-RX", NULL, "TX XBAR-" sname }
static const struct snd_soc_dapm_route tegra210_sfc_routes[] = {
{ "TX", NULL, "RX" },
RESAMPLE_ROUTE("Playback"),
RESAMPLE_ROUTE("Capture"),
};
static const char * const tegra210_sfc_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const char * const tegra210_sfc_mono_conv_text[] = {
"Zero", "Copy",
};
static const struct soc_enum tegra210_sfc_stereo_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra210_sfc_stereo_conv_text),
tegra210_sfc_stereo_conv_text);
static const struct soc_enum tegra210_sfc_mono_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra210_sfc_mono_conv_text),
tegra210_sfc_mono_conv_text);
static const struct snd_kcontrol_new tegra210_sfc_controls[] = {
SOC_ENUM_EXT("Input Stereo To Mono", tegra210_sfc_stereo_conv_enum,
tegra210_sfc_iget_stereo_to_mono,
tegra210_sfc_iput_stereo_to_mono),
SOC_ENUM_EXT("Input Mono To Stereo", tegra210_sfc_mono_conv_enum,
tegra210_sfc_iget_mono_to_stereo,
tegra210_sfc_iput_mono_to_stereo),
SOC_ENUM_EXT("Output Stereo To Mono", tegra210_sfc_stereo_conv_enum,
tegra210_sfc_oget_stereo_to_mono,
tegra210_sfc_oput_stereo_to_mono),
SOC_ENUM_EXT("Output Mono To Stereo", tegra210_sfc_mono_conv_enum,
tegra210_sfc_oget_mono_to_stereo,
tegra210_sfc_oput_mono_to_stereo),
};
static const struct snd_soc_component_driver tegra210_sfc_cmpnt = {
.dapm_widgets = tegra210_sfc_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_sfc_widgets),
.dapm_routes = tegra210_sfc_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_sfc_routes),
.controls = tegra210_sfc_controls,
.num_controls = ARRAY_SIZE(tegra210_sfc_controls),
};
static bool tegra210_sfc_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_SFC_RX_INT_MASK ... TEGRA210_SFC_RX_FREQ:
case TEGRA210_SFC_TX_INT_MASK ... TEGRA210_SFC_TX_FREQ:
case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_CG:
case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_sfc_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_SFC_RX_STATUS ... TEGRA210_SFC_RX_FREQ:
case TEGRA210_SFC_TX_STATUS ... TEGRA210_SFC_TX_FREQ:
case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_INT_STATUS:
case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_sfc_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_SFC_RX_STATUS:
case TEGRA210_SFC_RX_INT_STATUS:
case TEGRA210_SFC_RX_INT_SET:
case TEGRA210_SFC_TX_STATUS:
case TEGRA210_SFC_TX_INT_STATUS:
case TEGRA210_SFC_TX_INT_SET:
case TEGRA210_SFC_SOFT_RESET:
case TEGRA210_SFC_STATUS:
case TEGRA210_SFC_INT_STATUS:
case TEGRA210_SFC_CFG_RAM_CTRL:
case TEGRA210_SFC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_sfc_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_SFC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_sfc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_SFC_CFG_RAM_DATA,
.writeable_reg = tegra210_sfc_wr_reg,
.readable_reg = tegra210_sfc_rd_reg,
.volatile_reg = tegra210_sfc_volatile_reg,
.precious_reg = tegra210_sfc_precious_reg,
.reg_defaults = tegra210_sfc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_sfc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra210_sfc_of_match[] = {
{ .compatible = "nvidia,tegra210-sfc" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_sfc_of_match);
static int tegra210_sfc_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_sfc *sfc;
void __iomem *regs;
int err;
sfc = devm_kzalloc(dev, sizeof(*sfc), GFP_KERNEL);
if (!sfc)
return -ENOMEM;
dev_set_drvdata(dev, sfc);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
sfc->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_sfc_regmap_config);
if (IS_ERR(sfc->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(sfc->regmap);
}
regcache_cache_only(sfc->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_sfc_cmpnt,
tegra210_sfc_dais,
ARRAY_SIZE(tegra210_sfc_dais));
if (err) {
dev_err(dev, "can't register SFC component, err: %d\n", err);
return err;
}
pm_runtime_enable(&pdev->dev);
return 0;
}
static void tegra210_sfc_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_sfc_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_sfc_runtime_suspend,
tegra210_sfc_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra210_sfc_driver = {
.driver = {
.name = "tegra210-sfc",
.of_match_table = tegra210_sfc_of_match,
.pm = &tegra210_sfc_pm_ops,
},
.probe = tegra210_sfc_platform_probe,
.remove_new = tegra210_sfc_platform_remove,
};
module_platform_driver(tegra210_sfc_driver)
MODULE_AUTHOR("Arun Shamanna Lakshmi <[email protected]>");
MODULE_DESCRIPTION("Tegra210 SFC ASoC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_sfc.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_ahub.c - Tegra210 AHUB driver
//
// Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tegra210_ahub.h"
static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *uctl)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *e = (struct soc_enum *)kctl->private_value;
unsigned int reg, i, bit_pos = 0;
/*
* Find the bit position of current MUX input.
* If nothing is set, position would be 0 and it corresponds to 'None'.
*/
for (i = 0; i < ahub->soc_data->reg_count; i++) {
unsigned int reg_val;
reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
reg_val = snd_soc_component_read(cmpnt, reg);
reg_val &= ahub->soc_data->mask[i];
if (reg_val) {
bit_pos = ffs(reg_val) +
(8 * cmpnt->val_bytes * i);
break;
}
}
/* Find index related to the item in array *_ahub_mux_texts[] */
for (i = 0; i < e->items; i++) {
if (bit_pos == e->values[i]) {
uctl->value.enumerated.item[0] = i;
break;
}
}
return 0;
}
static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *uctl)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl);
struct soc_enum *e = (struct soc_enum *)kctl->private_value;
struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { };
unsigned int *item = uctl->value.enumerated.item;
unsigned int value = e->values[item[0]];
unsigned int i, bit_pos, reg_idx = 0, reg_val = 0;
int change = 0;
if (item[0] >= e->items)
return -EINVAL;
if (value) {
/* Get the register index and value to set */
reg_idx = (value - 1) / (8 * cmpnt->val_bytes);
bit_pos = (value - 1) % (8 * cmpnt->val_bytes);
reg_val = BIT(bit_pos);
}
/*
* Run through all parts of a MUX register to find the state changes.
* There will be an additional update if new MUX input value is from
* different part of the MUX register.
*/
for (i = 0; i < ahub->soc_data->reg_count; i++) {
update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
update[i].val = (i == reg_idx) ? reg_val : 0;
update[i].mask = ahub->soc_data->mask[i];
update[i].kcontrol = kctl;
/* Update widget power if state has changed */
if (snd_soc_component_test_bits(cmpnt, update[i].reg,
update[i].mask,
update[i].val))
change |= snd_soc_dapm_mux_update_power(dapm, kctl,
item[0], e,
&update[i]);
}
return change;
}
static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
DAI(ADMAIF1),
DAI(ADMAIF2),
DAI(ADMAIF3),
DAI(ADMAIF4),
DAI(ADMAIF5),
DAI(ADMAIF6),
DAI(ADMAIF7),
DAI(ADMAIF8),
DAI(ADMAIF9),
DAI(ADMAIF10),
/* XBAR <-> I2S <-> Codec */
DAI(I2S1),
DAI(I2S2),
DAI(I2S3),
DAI(I2S4),
DAI(I2S5),
/* XBAR <- DMIC <- Codec */
DAI(DMIC1),
DAI(DMIC2),
DAI(DMIC3),
/* XBAR -> SFC -> XBAR */
DAI(SFC1 RX),
DAI(SFC1 TX),
DAI(SFC2 RX),
DAI(SFC2 TX),
DAI(SFC3 RX),
DAI(SFC3 TX),
DAI(SFC4 RX),
DAI(SFC4 TX),
/* XBAR -> MVC -> XBAR */
DAI(MVC1 RX),
DAI(MVC1 TX),
DAI(MVC2 RX),
DAI(MVC2 TX),
/* XBAR -> AMX(4:1) -> XBAR */
DAI(AMX1 RX1),
DAI(AMX1 RX2),
DAI(AMX1 RX3),
DAI(AMX1 RX4),
DAI(AMX1),
DAI(AMX2 RX1),
DAI(AMX2 RX2),
DAI(AMX2 RX3),
DAI(AMX2 RX4),
DAI(AMX2),
/* XBAR -> ADX(1:4) -> XBAR */
DAI(ADX1),
DAI(ADX1 TX1),
DAI(ADX1 TX2),
DAI(ADX1 TX3),
DAI(ADX1 TX4),
DAI(ADX2),
DAI(ADX2 TX1),
DAI(ADX2 TX2),
DAI(ADX2 TX3),
DAI(ADX2 TX4),
/* XBAR -> MIXER(10:5) -> XBAR */
DAI(MIXER1 RX1),
DAI(MIXER1 RX2),
DAI(MIXER1 RX3),
DAI(MIXER1 RX4),
DAI(MIXER1 RX5),
DAI(MIXER1 RX6),
DAI(MIXER1 RX7),
DAI(MIXER1 RX8),
DAI(MIXER1 RX9),
DAI(MIXER1 RX10),
DAI(MIXER1 TX1),
DAI(MIXER1 TX2),
DAI(MIXER1 TX3),
DAI(MIXER1 TX4),
DAI(MIXER1 TX5),
/* XBAR -> OPE -> XBAR */
DAI(OPE1 RX),
DAI(OPE1 TX),
DAI(OPE2 RX),
DAI(OPE2 TX),
};
static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
DAI(ADMAIF1),
DAI(ADMAIF2),
DAI(ADMAIF3),
DAI(ADMAIF4),
DAI(ADMAIF5),
DAI(ADMAIF6),
DAI(ADMAIF7),
DAI(ADMAIF8),
DAI(ADMAIF9),
DAI(ADMAIF10),
DAI(ADMAIF11),
DAI(ADMAIF12),
DAI(ADMAIF13),
DAI(ADMAIF14),
DAI(ADMAIF15),
DAI(ADMAIF16),
DAI(ADMAIF17),
DAI(ADMAIF18),
DAI(ADMAIF19),
DAI(ADMAIF20),
/* XBAR <-> I2S <-> Codec */
DAI(I2S1),
DAI(I2S2),
DAI(I2S3),
DAI(I2S4),
DAI(I2S5),
DAI(I2S6),
/* XBAR <- DMIC <- Codec */
DAI(DMIC1),
DAI(DMIC2),
DAI(DMIC3),
DAI(DMIC4),
/* XBAR -> DSPK -> Codec */
DAI(DSPK1),
DAI(DSPK2),
/* XBAR -> SFC -> XBAR */
DAI(SFC1 RX),
DAI(SFC1 TX),
DAI(SFC2 RX),
DAI(SFC2 TX),
DAI(SFC3 RX),
DAI(SFC3 TX),
DAI(SFC4 RX),
DAI(SFC4 TX),
/* XBAR -> MVC -> XBAR */
DAI(MVC1 RX),
DAI(MVC1 TX),
DAI(MVC2 RX),
DAI(MVC2 TX),
/* XBAR -> AMX(4:1) -> XBAR */
DAI(AMX1 RX1),
DAI(AMX1 RX2),
DAI(AMX1 RX3),
DAI(AMX1 RX4),
DAI(AMX1),
DAI(AMX2 RX1),
DAI(AMX2 RX2),
DAI(AMX2 RX3),
DAI(AMX2 RX4),
DAI(AMX2),
DAI(AMX3 RX1),
DAI(AMX3 RX2),
DAI(AMX3 RX3),
DAI(AMX3 RX4),
DAI(AMX3),
DAI(AMX4 RX1),
DAI(AMX4 RX2),
DAI(AMX4 RX3),
DAI(AMX4 RX4),
DAI(AMX4),
/* XBAR -> ADX(1:4) -> XBAR */
DAI(ADX1),
DAI(ADX1 TX1),
DAI(ADX1 TX2),
DAI(ADX1 TX3),
DAI(ADX1 TX4),
DAI(ADX2),
DAI(ADX2 TX1),
DAI(ADX2 TX2),
DAI(ADX2 TX3),
DAI(ADX2 TX4),
DAI(ADX3),
DAI(ADX3 TX1),
DAI(ADX3 TX2),
DAI(ADX3 TX3),
DAI(ADX3 TX4),
DAI(ADX4),
DAI(ADX4 TX1),
DAI(ADX4 TX2),
DAI(ADX4 TX3),
DAI(ADX4 TX4),
/* XBAR -> MIXER1(10:5) -> XBAR */
DAI(MIXER1 RX1),
DAI(MIXER1 RX2),
DAI(MIXER1 RX3),
DAI(MIXER1 RX4),
DAI(MIXER1 RX5),
DAI(MIXER1 RX6),
DAI(MIXER1 RX7),
DAI(MIXER1 RX8),
DAI(MIXER1 RX9),
DAI(MIXER1 RX10),
DAI(MIXER1 TX1),
DAI(MIXER1 TX2),
DAI(MIXER1 TX3),
DAI(MIXER1 TX4),
DAI(MIXER1 TX5),
/* XBAR -> ASRC -> XBAR */
DAI(ASRC1 RX1),
DAI(ASRC1 TX1),
DAI(ASRC1 RX2),
DAI(ASRC1 TX2),
DAI(ASRC1 RX3),
DAI(ASRC1 TX3),
DAI(ASRC1 RX4),
DAI(ASRC1 TX4),
DAI(ASRC1 RX5),
DAI(ASRC1 TX5),
DAI(ASRC1 RX6),
DAI(ASRC1 TX6),
DAI(ASRC1 RX7),
/* XBAR -> OPE -> XBAR */
DAI(OPE1 RX),
DAI(OPE1 TX),
};
static const char * const tegra210_ahub_mux_texts[] = {
"None",
"ADMAIF1",
"ADMAIF2",
"ADMAIF3",
"ADMAIF4",
"ADMAIF5",
"ADMAIF6",
"ADMAIF7",
"ADMAIF8",
"ADMAIF9",
"ADMAIF10",
"I2S1",
"I2S2",
"I2S3",
"I2S4",
"I2S5",
"DMIC1",
"DMIC2",
"DMIC3",
"SFC1",
"SFC2",
"SFC3",
"SFC4",
"MVC1",
"MVC2",
"AMX1",
"AMX2",
"ADX1 TX1",
"ADX1 TX2",
"ADX1 TX3",
"ADX1 TX4",
"ADX2 TX1",
"ADX2 TX2",
"ADX2 TX3",
"ADX2 TX4",
"MIXER1 TX1",
"MIXER1 TX2",
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
"OPE1",
"OPE2",
};
static const char * const tegra186_ahub_mux_texts[] = {
"None",
"ADMAIF1",
"ADMAIF2",
"ADMAIF3",
"ADMAIF4",
"ADMAIF5",
"ADMAIF6",
"ADMAIF7",
"ADMAIF8",
"ADMAIF9",
"ADMAIF10",
"ADMAIF11",
"ADMAIF12",
"ADMAIF13",
"ADMAIF14",
"ADMAIF15",
"ADMAIF16",
"I2S1",
"I2S2",
"I2S3",
"I2S4",
"I2S5",
"I2S6",
"ADMAIF17",
"ADMAIF18",
"ADMAIF19",
"ADMAIF20",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
"SFC1",
"SFC2",
"SFC3",
"SFC4",
"MVC1",
"MVC2",
"AMX1",
"AMX2",
"AMX3",
"AMX4",
"ADX1 TX1",
"ADX1 TX2",
"ADX1 TX3",
"ADX1 TX4",
"ADX2 TX1",
"ADX2 TX2",
"ADX2 TX3",
"ADX2 TX4",
"ADX3 TX1",
"ADX3 TX2",
"ADX3 TX3",
"ADX3 TX4",
"ADX4 TX1",
"ADX4 TX2",
"ADX4 TX3",
"ADX4 TX4",
"MIXER1 TX1",
"MIXER1 TX2",
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
"ASRC1 TX1",
"ASRC1 TX2",
"ASRC1 TX3",
"ASRC1 TX4",
"ASRC1 TX5",
"ASRC1 TX6",
"OPE1",
};
static const unsigned int tegra210_ahub_mux_values[] = {
0,
/* ADMAIF */
MUX_VALUE(0, 0),
MUX_VALUE(0, 1),
MUX_VALUE(0, 2),
MUX_VALUE(0, 3),
MUX_VALUE(0, 4),
MUX_VALUE(0, 5),
MUX_VALUE(0, 6),
MUX_VALUE(0, 7),
MUX_VALUE(0, 8),
MUX_VALUE(0, 9),
/* I2S */
MUX_VALUE(0, 16),
MUX_VALUE(0, 17),
MUX_VALUE(0, 18),
MUX_VALUE(0, 19),
MUX_VALUE(0, 20),
/* DMIC */
MUX_VALUE(2, 18),
MUX_VALUE(2, 19),
MUX_VALUE(2, 20),
/* SFC */
MUX_VALUE(0, 24),
MUX_VALUE(0, 25),
MUX_VALUE(0, 26),
MUX_VALUE(0, 27),
/* MVC */
MUX_VALUE(2, 8),
MUX_VALUE(2, 9),
/* AMX */
MUX_VALUE(1, 8),
MUX_VALUE(1, 9),
/* ADX */
MUX_VALUE(2, 24),
MUX_VALUE(2, 25),
MUX_VALUE(2, 26),
MUX_VALUE(2, 27),
MUX_VALUE(2, 28),
MUX_VALUE(2, 29),
MUX_VALUE(2, 30),
MUX_VALUE(2, 31),
/* MIXER */
MUX_VALUE(1, 0),
MUX_VALUE(1, 1),
MUX_VALUE(1, 2),
MUX_VALUE(1, 3),
MUX_VALUE(1, 4),
/* OPE */
MUX_VALUE(2, 0),
MUX_VALUE(2, 1),
};
static const unsigned int tegra186_ahub_mux_values[] = {
0,
/* ADMAIF */
MUX_VALUE(0, 0),
MUX_VALUE(0, 1),
MUX_VALUE(0, 2),
MUX_VALUE(0, 3),
MUX_VALUE(0, 4),
MUX_VALUE(0, 5),
MUX_VALUE(0, 6),
MUX_VALUE(0, 7),
MUX_VALUE(0, 8),
MUX_VALUE(0, 9),
MUX_VALUE(0, 10),
MUX_VALUE(0, 11),
MUX_VALUE(0, 12),
MUX_VALUE(0, 13),
MUX_VALUE(0, 14),
MUX_VALUE(0, 15),
/* I2S */
MUX_VALUE(0, 16),
MUX_VALUE(0, 17),
MUX_VALUE(0, 18),
MUX_VALUE(0, 19),
MUX_VALUE(0, 20),
MUX_VALUE(0, 21),
/* ADMAIF */
MUX_VALUE(3, 16),
MUX_VALUE(3, 17),
MUX_VALUE(3, 18),
MUX_VALUE(3, 19),
/* DMIC */
MUX_VALUE(2, 18),
MUX_VALUE(2, 19),
MUX_VALUE(2, 20),
MUX_VALUE(2, 21),
/* SFC */
MUX_VALUE(0, 24),
MUX_VALUE(0, 25),
MUX_VALUE(0, 26),
MUX_VALUE(0, 27),
/* MVC */
MUX_VALUE(2, 8),
MUX_VALUE(2, 9),
/* AMX */
MUX_VALUE(1, 8),
MUX_VALUE(1, 9),
MUX_VALUE(1, 10),
MUX_VALUE(1, 11),
/* ADX */
MUX_VALUE(2, 24),
MUX_VALUE(2, 25),
MUX_VALUE(2, 26),
MUX_VALUE(2, 27),
MUX_VALUE(2, 28),
MUX_VALUE(2, 29),
MUX_VALUE(2, 30),
MUX_VALUE(2, 31),
MUX_VALUE(3, 0),
MUX_VALUE(3, 1),
MUX_VALUE(3, 2),
MUX_VALUE(3, 3),
MUX_VALUE(3, 4),
MUX_VALUE(3, 5),
MUX_VALUE(3, 6),
MUX_VALUE(3, 7),
/* MIXER */
MUX_VALUE(1, 0),
MUX_VALUE(1, 1),
MUX_VALUE(1, 2),
MUX_VALUE(1, 3),
MUX_VALUE(1, 4),
/* ASRC */
MUX_VALUE(3, 24),
MUX_VALUE(3, 25),
MUX_VALUE(3, 26),
MUX_VALUE(3, 27),
MUX_VALUE(3, 28),
MUX_VALUE(3, 29),
/* OPE */
MUX_VALUE(2, 0),
};
/* Controls for t210 */
MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00);
MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01);
MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02);
MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03);
MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04);
MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05);
MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06);
MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07);
MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08);
MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09);
MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10);
MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18);
MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19);
MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a);
MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b);
MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48);
MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49);
MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50);
MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51);
MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52);
MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53);
MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54);
MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55);
MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56);
MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57);
MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58);
MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59);
MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20);
MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21);
MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22);
MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23);
MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24);
MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25);
MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26);
MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27);
MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28);
MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29);
MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40);
MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41);
/* Controls for t186 */
MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01);
MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02);
MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03);
MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04);
MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05);
MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06);
MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07);
MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08);
MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09);
MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10);
MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11);
MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12);
MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13);
MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14);
MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a);
MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b);
MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c);
MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d);
MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e);
MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f);
MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15);
MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30);
MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31);
MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18);
MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19);
MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a);
MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b);
MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48);
MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49);
MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50);
MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51);
MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52);
MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53);
MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54);
MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55);
MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56);
MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57);
MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58);
MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59);
MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a);
MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b);
MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64);
MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65);
MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66);
MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67);
MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60);
MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61);
MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62);
MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63);
MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20);
MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21);
MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22);
MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23);
MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24);
MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25);
MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26);
MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27);
MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28);
MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29);
MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c);
MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d);
MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e);
MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f);
MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70);
MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71);
MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72);
MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40);
/* Controls for t234 */
MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44);
MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45);
MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48);
MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49);
MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a);
MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b);
MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c);
MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d);
MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e);
MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f);
MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50);
MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51);
MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52);
MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53);
MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58);
MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59);
MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a);
MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b);
MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c);
MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d);
MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e);
MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f);
MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60);
MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61);
MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62);
MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63);
MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64);
MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65);
MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66);
MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67);
MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68);
MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69);
MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a);
static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
WIDGETS("ADMAIF1", t210_admaif1_tx),
WIDGETS("ADMAIF2", t210_admaif2_tx),
WIDGETS("ADMAIF3", t210_admaif3_tx),
WIDGETS("ADMAIF4", t210_admaif4_tx),
WIDGETS("ADMAIF5", t210_admaif5_tx),
WIDGETS("ADMAIF6", t210_admaif6_tx),
WIDGETS("ADMAIF7", t210_admaif7_tx),
WIDGETS("ADMAIF8", t210_admaif8_tx),
WIDGETS("ADMAIF9", t210_admaif9_tx),
WIDGETS("ADMAIF10", t210_admaif10_tx),
WIDGETS("I2S1", t210_i2s1_tx),
WIDGETS("I2S2", t210_i2s2_tx),
WIDGETS("I2S3", t210_i2s3_tx),
WIDGETS("I2S4", t210_i2s4_tx),
WIDGETS("I2S5", t210_i2s5_tx),
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
WIDGETS("SFC1", t210_sfc1_tx),
WIDGETS("SFC2", t210_sfc2_tx),
WIDGETS("SFC3", t210_sfc3_tx),
WIDGETS("SFC4", t210_sfc4_tx),
WIDGETS("MVC1", t210_mvc1_tx),
WIDGETS("MVC2", t210_mvc2_tx),
WIDGETS("AMX1 RX1", t210_amx11_tx),
WIDGETS("AMX1 RX2", t210_amx12_tx),
WIDGETS("AMX1 RX3", t210_amx13_tx),
WIDGETS("AMX1 RX4", t210_amx14_tx),
WIDGETS("AMX2 RX1", t210_amx21_tx),
WIDGETS("AMX2 RX2", t210_amx22_tx),
WIDGETS("AMX2 RX3", t210_amx23_tx),
WIDGETS("AMX2 RX4", t210_amx24_tx),
TX_WIDGETS("AMX1"),
TX_WIDGETS("AMX2"),
WIDGETS("ADX1", t210_adx1_tx),
WIDGETS("ADX2", t210_adx2_tx),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
WIDGETS("MIXER1 RX1", t210_mixer11_tx),
WIDGETS("MIXER1 RX2", t210_mixer12_tx),
WIDGETS("MIXER1 RX3", t210_mixer13_tx),
WIDGETS("MIXER1 RX4", t210_mixer14_tx),
WIDGETS("MIXER1 RX5", t210_mixer15_tx),
WIDGETS("MIXER1 RX6", t210_mixer16_tx),
WIDGETS("MIXER1 RX7", t210_mixer17_tx),
WIDGETS("MIXER1 RX8", t210_mixer18_tx),
WIDGETS("MIXER1 RX9", t210_mixer19_tx),
WIDGETS("MIXER1 RX10", t210_mixer110_tx),
TX_WIDGETS("MIXER1 TX1"),
TX_WIDGETS("MIXER1 TX2"),
TX_WIDGETS("MIXER1 TX3"),
TX_WIDGETS("MIXER1 TX4"),
TX_WIDGETS("MIXER1 TX5"),
WIDGETS("OPE1", t210_ope1_tx),
WIDGETS("OPE2", t210_ope2_tx),
};
static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
WIDGETS("ADMAIF1", t186_admaif1_tx),
WIDGETS("ADMAIF2", t186_admaif2_tx),
WIDGETS("ADMAIF3", t186_admaif3_tx),
WIDGETS("ADMAIF4", t186_admaif4_tx),
WIDGETS("ADMAIF5", t186_admaif5_tx),
WIDGETS("ADMAIF6", t186_admaif6_tx),
WIDGETS("ADMAIF7", t186_admaif7_tx),
WIDGETS("ADMAIF8", t186_admaif8_tx),
WIDGETS("ADMAIF9", t186_admaif9_tx),
WIDGETS("ADMAIF10", t186_admaif10_tx),
WIDGETS("ADMAIF11", t186_admaif11_tx),
WIDGETS("ADMAIF12", t186_admaif12_tx),
WIDGETS("ADMAIF13", t186_admaif13_tx),
WIDGETS("ADMAIF14", t186_admaif14_tx),
WIDGETS("ADMAIF15", t186_admaif15_tx),
WIDGETS("ADMAIF16", t186_admaif16_tx),
WIDGETS("ADMAIF17", t186_admaif17_tx),
WIDGETS("ADMAIF18", t186_admaif18_tx),
WIDGETS("ADMAIF19", t186_admaif19_tx),
WIDGETS("ADMAIF20", t186_admaif20_tx),
WIDGETS("I2S1", t186_i2s1_tx),
WIDGETS("I2S2", t186_i2s2_tx),
WIDGETS("I2S3", t186_i2s3_tx),
WIDGETS("I2S4", t186_i2s4_tx),
WIDGETS("I2S5", t186_i2s5_tx),
WIDGETS("I2S6", t186_i2s6_tx),
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
TX_WIDGETS("DMIC4"),
WIDGETS("DSPK1", t186_dspk1_tx),
WIDGETS("DSPK2", t186_dspk2_tx),
WIDGETS("SFC1", t186_sfc1_tx),
WIDGETS("SFC2", t186_sfc2_tx),
WIDGETS("SFC3", t186_sfc3_tx),
WIDGETS("SFC4", t186_sfc4_tx),
WIDGETS("MVC1", t186_mvc1_tx),
WIDGETS("MVC2", t186_mvc2_tx),
WIDGETS("AMX1 RX1", t186_amx11_tx),
WIDGETS("AMX1 RX2", t186_amx12_tx),
WIDGETS("AMX1 RX3", t186_amx13_tx),
WIDGETS("AMX1 RX4", t186_amx14_tx),
WIDGETS("AMX2 RX1", t186_amx21_tx),
WIDGETS("AMX2 RX2", t186_amx22_tx),
WIDGETS("AMX2 RX3", t186_amx23_tx),
WIDGETS("AMX2 RX4", t186_amx24_tx),
WIDGETS("AMX3 RX1", t186_amx31_tx),
WIDGETS("AMX3 RX2", t186_amx32_tx),
WIDGETS("AMX3 RX3", t186_amx33_tx),
WIDGETS("AMX3 RX4", t186_amx34_tx),
WIDGETS("AMX4 RX1", t186_amx41_tx),
WIDGETS("AMX4 RX2", t186_amx42_tx),
WIDGETS("AMX4 RX3", t186_amx43_tx),
WIDGETS("AMX4 RX4", t186_amx44_tx),
TX_WIDGETS("AMX1"),
TX_WIDGETS("AMX2"),
TX_WIDGETS("AMX3"),
TX_WIDGETS("AMX4"),
WIDGETS("ADX1", t186_adx1_tx),
WIDGETS("ADX2", t186_adx2_tx),
WIDGETS("ADX3", t186_adx3_tx),
WIDGETS("ADX4", t186_adx4_tx),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
TX_WIDGETS("ADX3 TX1"),
TX_WIDGETS("ADX3 TX2"),
TX_WIDGETS("ADX3 TX3"),
TX_WIDGETS("ADX3 TX4"),
TX_WIDGETS("ADX4 TX1"),
TX_WIDGETS("ADX4 TX2"),
TX_WIDGETS("ADX4 TX3"),
TX_WIDGETS("ADX4 TX4"),
WIDGETS("MIXER1 RX1", t186_mixer11_tx),
WIDGETS("MIXER1 RX2", t186_mixer12_tx),
WIDGETS("MIXER1 RX3", t186_mixer13_tx),
WIDGETS("MIXER1 RX4", t186_mixer14_tx),
WIDGETS("MIXER1 RX5", t186_mixer15_tx),
WIDGETS("MIXER1 RX6", t186_mixer16_tx),
WIDGETS("MIXER1 RX7", t186_mixer17_tx),
WIDGETS("MIXER1 RX8", t186_mixer18_tx),
WIDGETS("MIXER1 RX9", t186_mixer19_tx),
WIDGETS("MIXER1 RX10", t186_mixer110_tx),
TX_WIDGETS("MIXER1 TX1"),
TX_WIDGETS("MIXER1 TX2"),
TX_WIDGETS("MIXER1 TX3"),
TX_WIDGETS("MIXER1 TX4"),
TX_WIDGETS("MIXER1 TX5"),
WIDGETS("ASRC1 RX1", t186_asrc11_tx),
WIDGETS("ASRC1 RX2", t186_asrc12_tx),
WIDGETS("ASRC1 RX3", t186_asrc13_tx),
WIDGETS("ASRC1 RX4", t186_asrc14_tx),
WIDGETS("ASRC1 RX5", t186_asrc15_tx),
WIDGETS("ASRC1 RX6", t186_asrc16_tx),
WIDGETS("ASRC1 RX7", t186_asrc17_tx),
TX_WIDGETS("ASRC1 TX1"),
TX_WIDGETS("ASRC1 TX2"),
TX_WIDGETS("ASRC1 TX3"),
TX_WIDGETS("ASRC1 TX4"),
TX_WIDGETS("ASRC1 TX5"),
TX_WIDGETS("ASRC1 TX6"),
WIDGETS("OPE1", t186_ope1_tx),
};
static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
WIDGETS("ADMAIF1", t186_admaif1_tx),
WIDGETS("ADMAIF2", t186_admaif2_tx),
WIDGETS("ADMAIF3", t186_admaif3_tx),
WIDGETS("ADMAIF4", t186_admaif4_tx),
WIDGETS("ADMAIF5", t186_admaif5_tx),
WIDGETS("ADMAIF6", t186_admaif6_tx),
WIDGETS("ADMAIF7", t186_admaif7_tx),
WIDGETS("ADMAIF8", t186_admaif8_tx),
WIDGETS("ADMAIF9", t186_admaif9_tx),
WIDGETS("ADMAIF10", t186_admaif10_tx),
WIDGETS("ADMAIF11", t186_admaif11_tx),
WIDGETS("ADMAIF12", t186_admaif12_tx),
WIDGETS("ADMAIF13", t186_admaif13_tx),
WIDGETS("ADMAIF14", t186_admaif14_tx),
WIDGETS("ADMAIF15", t186_admaif15_tx),
WIDGETS("ADMAIF16", t186_admaif16_tx),
WIDGETS("ADMAIF17", t234_admaif17_tx),
WIDGETS("ADMAIF18", t234_admaif18_tx),
WIDGETS("ADMAIF19", t234_admaif19_tx),
WIDGETS("ADMAIF20", t234_admaif20_tx),
WIDGETS("I2S1", t186_i2s1_tx),
WIDGETS("I2S2", t186_i2s2_tx),
WIDGETS("I2S3", t186_i2s3_tx),
WIDGETS("I2S4", t186_i2s4_tx),
WIDGETS("I2S5", t186_i2s5_tx),
WIDGETS("I2S6", t186_i2s6_tx),
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
TX_WIDGETS("DMIC4"),
WIDGETS("DSPK1", t186_dspk1_tx),
WIDGETS("DSPK2", t186_dspk2_tx),
WIDGETS("SFC1", t186_sfc1_tx),
WIDGETS("SFC2", t186_sfc2_tx),
WIDGETS("SFC3", t186_sfc3_tx),
WIDGETS("SFC4", t186_sfc4_tx),
WIDGETS("MVC1", t234_mvc1_tx),
WIDGETS("MVC2", t234_mvc2_tx),
WIDGETS("AMX1 RX1", t234_amx11_tx),
WIDGETS("AMX1 RX2", t234_amx12_tx),
WIDGETS("AMX1 RX3", t234_amx13_tx),
WIDGETS("AMX1 RX4", t234_amx14_tx),
WIDGETS("AMX2 RX1", t234_amx21_tx),
WIDGETS("AMX2 RX2", t234_amx22_tx),
WIDGETS("AMX2 RX3", t234_amx23_tx),
WIDGETS("AMX2 RX4", t234_amx24_tx),
WIDGETS("AMX3 RX1", t234_amx31_tx),
WIDGETS("AMX3 RX2", t234_amx32_tx),
WIDGETS("AMX3 RX3", t234_amx33_tx),
WIDGETS("AMX3 RX4", t234_amx34_tx),
WIDGETS("AMX4 RX1", t234_amx41_tx),
WIDGETS("AMX4 RX2", t234_amx42_tx),
WIDGETS("AMX4 RX3", t234_amx43_tx),
WIDGETS("AMX4 RX4", t234_amx44_tx),
TX_WIDGETS("AMX1"),
TX_WIDGETS("AMX2"),
TX_WIDGETS("AMX3"),
TX_WIDGETS("AMX4"),
WIDGETS("ADX1", t234_adx1_tx),
WIDGETS("ADX2", t234_adx2_tx),
WIDGETS("ADX3", t234_adx3_tx),
WIDGETS("ADX4", t234_adx4_tx),
TX_WIDGETS("ADX1 TX1"),
TX_WIDGETS("ADX1 TX2"),
TX_WIDGETS("ADX1 TX3"),
TX_WIDGETS("ADX1 TX4"),
TX_WIDGETS("ADX2 TX1"),
TX_WIDGETS("ADX2 TX2"),
TX_WIDGETS("ADX2 TX3"),
TX_WIDGETS("ADX2 TX4"),
TX_WIDGETS("ADX3 TX1"),
TX_WIDGETS("ADX3 TX2"),
TX_WIDGETS("ADX3 TX3"),
TX_WIDGETS("ADX3 TX4"),
TX_WIDGETS("ADX4 TX1"),
TX_WIDGETS("ADX4 TX2"),
TX_WIDGETS("ADX4 TX3"),
TX_WIDGETS("ADX4 TX4"),
WIDGETS("MIXER1 RX1", t186_mixer11_tx),
WIDGETS("MIXER1 RX2", t186_mixer12_tx),
WIDGETS("MIXER1 RX3", t186_mixer13_tx),
WIDGETS("MIXER1 RX4", t186_mixer14_tx),
WIDGETS("MIXER1 RX5", t186_mixer15_tx),
WIDGETS("MIXER1 RX6", t186_mixer16_tx),
WIDGETS("MIXER1 RX7", t186_mixer17_tx),
WIDGETS("MIXER1 RX8", t186_mixer18_tx),
WIDGETS("MIXER1 RX9", t186_mixer19_tx),
WIDGETS("MIXER1 RX10", t186_mixer110_tx),
TX_WIDGETS("MIXER1 TX1"),
TX_WIDGETS("MIXER1 TX2"),
TX_WIDGETS("MIXER1 TX3"),
TX_WIDGETS("MIXER1 TX4"),
TX_WIDGETS("MIXER1 TX5"),
WIDGETS("ASRC1 RX1", t234_asrc11_tx),
WIDGETS("ASRC1 RX2", t234_asrc12_tx),
WIDGETS("ASRC1 RX3", t234_asrc13_tx),
WIDGETS("ASRC1 RX4", t234_asrc14_tx),
WIDGETS("ASRC1 RX5", t234_asrc15_tx),
WIDGETS("ASRC1 RX6", t234_asrc16_tx),
WIDGETS("ASRC1 RX7", t234_asrc17_tx),
TX_WIDGETS("ASRC1 TX1"),
TX_WIDGETS("ASRC1 TX2"),
TX_WIDGETS("ASRC1 TX3"),
TX_WIDGETS("ASRC1 TX4"),
TX_WIDGETS("ASRC1 TX5"),
TX_WIDGETS("ASRC1 TX6"),
WIDGETS("OPE1", t186_ope1_tx),
};
#define TEGRA_COMMON_MUX_ROUTES(name) \
{ name " XBAR-TX", NULL, name " Mux" }, \
{ name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \
{ name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \
{ name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \
{ name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \
{ name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \
{ name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \
{ name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \
{ name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \
{ name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \
{ name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \
{ name " Mux", "I2S1", "I2S1 XBAR-RX" }, \
{ name " Mux", "I2S2", "I2S2 XBAR-RX" }, \
{ name " Mux", "I2S3", "I2S3 XBAR-RX" }, \
{ name " Mux", "I2S4", "I2S4 XBAR-RX" }, \
{ name " Mux", "I2S5", "I2S5 XBAR-RX" }, \
{ name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \
{ name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \
{ name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \
{ name " Mux", "SFC1", "SFC1 XBAR-RX" }, \
{ name " Mux", "SFC2", "SFC2 XBAR-RX" }, \
{ name " Mux", "SFC3", "SFC3 XBAR-RX" }, \
{ name " Mux", "SFC4", "SFC4 XBAR-RX" }, \
{ name " Mux", "MVC1", "MVC1 XBAR-RX" }, \
{ name " Mux", "MVC2", "MVC2 XBAR-RX" }, \
{ name " Mux", "AMX1", "AMX1 XBAR-RX" }, \
{ name " Mux", "AMX2", "AMX2 XBAR-RX" }, \
{ name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \
{ name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \
{ name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \
{ name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \
{ name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \
{ name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \
{ name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \
{ name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, \
{ name " Mux", "OPE1", "OPE1 XBAR-RX" },
#define TEGRA210_ONLY_MUX_ROUTES(name) \
{ name " Mux", "OPE2", "OPE2 XBAR-RX" },
#define TEGRA186_ONLY_MUX_ROUTES(name) \
{ name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \
{ name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \
{ name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \
{ name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \
{ name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \
{ name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \
{ name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \
{ name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \
{ name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \
{ name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \
{ name " Mux", "I2S6", "I2S6 XBAR-RX" }, \
{ name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \
{ name " Mux", "AMX3", "AMX3 XBAR-RX" }, \
{ name " Mux", "AMX4", "AMX4 XBAR-RX" }, \
{ name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \
{ name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \
{ name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \
{ name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \
{ name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \
{ name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \
{ name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \
{ name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" },
#define TEGRA210_MUX_ROUTES(name) \
TEGRA_COMMON_MUX_ROUTES(name) \
TEGRA210_ONLY_MUX_ROUTES(name)
#define TEGRA186_MUX_ROUTES(name) \
TEGRA_COMMON_MUX_ROUTES(name) \
TEGRA186_ONLY_MUX_ROUTES(name)
/* Connect FEs with XBAR */
#define TEGRA_FE_ROUTES(name) \
{ name " XBAR-Playback", NULL, name " Playback" }, \
{ name " XBAR-RX", NULL, name " XBAR-Playback"}, \
{ name " XBAR-Capture", NULL, name " XBAR-TX" }, \
{ name " Capture", NULL, name " XBAR-Capture" },
static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
TEGRA_FE_ROUTES("ADMAIF1")
TEGRA_FE_ROUTES("ADMAIF2")
TEGRA_FE_ROUTES("ADMAIF3")
TEGRA_FE_ROUTES("ADMAIF4")
TEGRA_FE_ROUTES("ADMAIF5")
TEGRA_FE_ROUTES("ADMAIF6")
TEGRA_FE_ROUTES("ADMAIF7")
TEGRA_FE_ROUTES("ADMAIF8")
TEGRA_FE_ROUTES("ADMAIF9")
TEGRA_FE_ROUTES("ADMAIF10")
TEGRA210_MUX_ROUTES("ADMAIF1")
TEGRA210_MUX_ROUTES("ADMAIF2")
TEGRA210_MUX_ROUTES("ADMAIF3")
TEGRA210_MUX_ROUTES("ADMAIF4")
TEGRA210_MUX_ROUTES("ADMAIF5")
TEGRA210_MUX_ROUTES("ADMAIF6")
TEGRA210_MUX_ROUTES("ADMAIF7")
TEGRA210_MUX_ROUTES("ADMAIF8")
TEGRA210_MUX_ROUTES("ADMAIF9")
TEGRA210_MUX_ROUTES("ADMAIF10")
TEGRA210_MUX_ROUTES("I2S1")
TEGRA210_MUX_ROUTES("I2S2")
TEGRA210_MUX_ROUTES("I2S3")
TEGRA210_MUX_ROUTES("I2S4")
TEGRA210_MUX_ROUTES("I2S5")
TEGRA210_MUX_ROUTES("SFC1")
TEGRA210_MUX_ROUTES("SFC2")
TEGRA210_MUX_ROUTES("SFC3")
TEGRA210_MUX_ROUTES("SFC4")
TEGRA210_MUX_ROUTES("MVC1")
TEGRA210_MUX_ROUTES("MVC2")
TEGRA210_MUX_ROUTES("AMX1 RX1")
TEGRA210_MUX_ROUTES("AMX1 RX2")
TEGRA210_MUX_ROUTES("AMX1 RX3")
TEGRA210_MUX_ROUTES("AMX1 RX4")
TEGRA210_MUX_ROUTES("AMX2 RX1")
TEGRA210_MUX_ROUTES("AMX2 RX2")
TEGRA210_MUX_ROUTES("AMX2 RX3")
TEGRA210_MUX_ROUTES("AMX2 RX4")
TEGRA210_MUX_ROUTES("ADX1")
TEGRA210_MUX_ROUTES("ADX2")
TEGRA210_MUX_ROUTES("MIXER1 RX1")
TEGRA210_MUX_ROUTES("MIXER1 RX2")
TEGRA210_MUX_ROUTES("MIXER1 RX3")
TEGRA210_MUX_ROUTES("MIXER1 RX4")
TEGRA210_MUX_ROUTES("MIXER1 RX5")
TEGRA210_MUX_ROUTES("MIXER1 RX6")
TEGRA210_MUX_ROUTES("MIXER1 RX7")
TEGRA210_MUX_ROUTES("MIXER1 RX8")
TEGRA210_MUX_ROUTES("MIXER1 RX9")
TEGRA210_MUX_ROUTES("MIXER1 RX10")
TEGRA210_MUX_ROUTES("OPE1")
TEGRA210_MUX_ROUTES("OPE2")
};
static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
TEGRA_FE_ROUTES("ADMAIF1")
TEGRA_FE_ROUTES("ADMAIF2")
TEGRA_FE_ROUTES("ADMAIF3")
TEGRA_FE_ROUTES("ADMAIF4")
TEGRA_FE_ROUTES("ADMAIF5")
TEGRA_FE_ROUTES("ADMAIF6")
TEGRA_FE_ROUTES("ADMAIF7")
TEGRA_FE_ROUTES("ADMAIF8")
TEGRA_FE_ROUTES("ADMAIF9")
TEGRA_FE_ROUTES("ADMAIF10")
TEGRA_FE_ROUTES("ADMAIF11")
TEGRA_FE_ROUTES("ADMAIF12")
TEGRA_FE_ROUTES("ADMAIF13")
TEGRA_FE_ROUTES("ADMAIF14")
TEGRA_FE_ROUTES("ADMAIF15")
TEGRA_FE_ROUTES("ADMAIF16")
TEGRA_FE_ROUTES("ADMAIF17")
TEGRA_FE_ROUTES("ADMAIF18")
TEGRA_FE_ROUTES("ADMAIF19")
TEGRA_FE_ROUTES("ADMAIF20")
TEGRA186_MUX_ROUTES("ADMAIF1")
TEGRA186_MUX_ROUTES("ADMAIF2")
TEGRA186_MUX_ROUTES("ADMAIF3")
TEGRA186_MUX_ROUTES("ADMAIF4")
TEGRA186_MUX_ROUTES("ADMAIF5")
TEGRA186_MUX_ROUTES("ADMAIF6")
TEGRA186_MUX_ROUTES("ADMAIF7")
TEGRA186_MUX_ROUTES("ADMAIF8")
TEGRA186_MUX_ROUTES("ADMAIF9")
TEGRA186_MUX_ROUTES("ADMAIF10")
TEGRA186_MUX_ROUTES("ADMAIF11")
TEGRA186_MUX_ROUTES("ADMAIF12")
TEGRA186_MUX_ROUTES("ADMAIF13")
TEGRA186_MUX_ROUTES("ADMAIF14")
TEGRA186_MUX_ROUTES("ADMAIF15")
TEGRA186_MUX_ROUTES("ADMAIF16")
TEGRA186_MUX_ROUTES("ADMAIF17")
TEGRA186_MUX_ROUTES("ADMAIF18")
TEGRA186_MUX_ROUTES("ADMAIF19")
TEGRA186_MUX_ROUTES("ADMAIF20")
TEGRA186_MUX_ROUTES("I2S1")
TEGRA186_MUX_ROUTES("I2S2")
TEGRA186_MUX_ROUTES("I2S3")
TEGRA186_MUX_ROUTES("I2S4")
TEGRA186_MUX_ROUTES("I2S5")
TEGRA186_MUX_ROUTES("I2S6")
TEGRA186_MUX_ROUTES("DSPK1")
TEGRA186_MUX_ROUTES("DSPK2")
TEGRA186_MUX_ROUTES("SFC1")
TEGRA186_MUX_ROUTES("SFC2")
TEGRA186_MUX_ROUTES("SFC3")
TEGRA186_MUX_ROUTES("SFC4")
TEGRA186_MUX_ROUTES("MVC1")
TEGRA186_MUX_ROUTES("MVC2")
TEGRA186_MUX_ROUTES("AMX1 RX1")
TEGRA186_MUX_ROUTES("AMX1 RX2")
TEGRA186_MUX_ROUTES("AMX1 RX3")
TEGRA186_MUX_ROUTES("AMX1 RX4")
TEGRA186_MUX_ROUTES("AMX2 RX1")
TEGRA186_MUX_ROUTES("AMX2 RX2")
TEGRA186_MUX_ROUTES("AMX2 RX3")
TEGRA186_MUX_ROUTES("AMX2 RX4")
TEGRA186_MUX_ROUTES("AMX3 RX1")
TEGRA186_MUX_ROUTES("AMX3 RX2")
TEGRA186_MUX_ROUTES("AMX3 RX3")
TEGRA186_MUX_ROUTES("AMX3 RX4")
TEGRA186_MUX_ROUTES("AMX4 RX1")
TEGRA186_MUX_ROUTES("AMX4 RX2")
TEGRA186_MUX_ROUTES("AMX4 RX3")
TEGRA186_MUX_ROUTES("AMX4 RX4")
TEGRA186_MUX_ROUTES("ADX1")
TEGRA186_MUX_ROUTES("ADX2")
TEGRA186_MUX_ROUTES("ADX3")
TEGRA186_MUX_ROUTES("ADX4")
TEGRA186_MUX_ROUTES("MIXER1 RX1")
TEGRA186_MUX_ROUTES("MIXER1 RX2")
TEGRA186_MUX_ROUTES("MIXER1 RX3")
TEGRA186_MUX_ROUTES("MIXER1 RX4")
TEGRA186_MUX_ROUTES("MIXER1 RX5")
TEGRA186_MUX_ROUTES("MIXER1 RX6")
TEGRA186_MUX_ROUTES("MIXER1 RX7")
TEGRA186_MUX_ROUTES("MIXER1 RX8")
TEGRA186_MUX_ROUTES("MIXER1 RX9")
TEGRA186_MUX_ROUTES("MIXER1 RX10")
TEGRA186_MUX_ROUTES("ASRC1 RX1")
TEGRA186_MUX_ROUTES("ASRC1 RX2")
TEGRA186_MUX_ROUTES("ASRC1 RX3")
TEGRA186_MUX_ROUTES("ASRC1 RX4")
TEGRA186_MUX_ROUTES("ASRC1 RX5")
TEGRA186_MUX_ROUTES("ASRC1 RX6")
TEGRA186_MUX_ROUTES("ASRC1 RX7")
TEGRA186_MUX_ROUTES("OPE1")
};
static const struct snd_soc_component_driver tegra210_ahub_component = {
.dapm_widgets = tegra210_ahub_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets),
.dapm_routes = tegra210_ahub_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes),
};
static const struct snd_soc_component_driver tegra186_ahub_component = {
.dapm_widgets = tegra186_ahub_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets),
.dapm_routes = tegra186_ahub_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
};
static const struct snd_soc_component_driver tegra234_ahub_component = {
.dapm_widgets = tegra234_ahub_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets),
.dapm_routes = tegra186_ahub_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
};
static const struct regmap_config tegra210_ahub_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TEGRA210_MAX_REGISTER_ADDR,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config tegra186_ahub_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TEGRA186_MAX_REGISTER_ADDR,
.cache_type = REGCACHE_FLAT,
};
static const struct tegra_ahub_soc_data soc_data_tegra210 = {
.cmpnt_drv = &tegra210_ahub_component,
.dai_drv = tegra210_ahub_dais,
.num_dais = ARRAY_SIZE(tegra210_ahub_dais),
.regmap_config = &tegra210_ahub_regmap_config,
.mask[0] = TEGRA210_XBAR_REG_MASK_0,
.mask[1] = TEGRA210_XBAR_REG_MASK_1,
.mask[2] = TEGRA210_XBAR_REG_MASK_2,
.mask[3] = TEGRA210_XBAR_REG_MASK_3,
.reg_count = TEGRA210_XBAR_UPDATE_MAX_REG,
};
static const struct tegra_ahub_soc_data soc_data_tegra186 = {
.cmpnt_drv = &tegra186_ahub_component,
.dai_drv = tegra186_ahub_dais,
.num_dais = ARRAY_SIZE(tegra186_ahub_dais),
.regmap_config = &tegra186_ahub_regmap_config,
.mask[0] = TEGRA186_XBAR_REG_MASK_0,
.mask[1] = TEGRA186_XBAR_REG_MASK_1,
.mask[2] = TEGRA186_XBAR_REG_MASK_2,
.mask[3] = TEGRA186_XBAR_REG_MASK_3,
.reg_count = TEGRA186_XBAR_UPDATE_MAX_REG,
};
static const struct tegra_ahub_soc_data soc_data_tegra234 = {
.cmpnt_drv = &tegra234_ahub_component,
.dai_drv = tegra186_ahub_dais,
.num_dais = ARRAY_SIZE(tegra186_ahub_dais),
.regmap_config = &tegra186_ahub_regmap_config,
.mask[0] = TEGRA186_XBAR_REG_MASK_0,
.mask[1] = TEGRA186_XBAR_REG_MASK_1,
.mask[2] = TEGRA186_XBAR_REG_MASK_2,
.mask[3] = TEGRA186_XBAR_REG_MASK_3,
.reg_count = TEGRA186_XBAR_UPDATE_MAX_REG,
};
static const struct of_device_id tegra_ahub_of_match[] = {
{ .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
{ .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
{ .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 },
{},
};
MODULE_DEVICE_TABLE(of, tegra_ahub_of_match);
static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev)
{
struct tegra_ahub *ahub = dev_get_drvdata(dev);
regcache_cache_only(ahub->regmap, true);
regcache_mark_dirty(ahub->regmap);
clk_disable_unprepare(ahub->clk);
return 0;
}
static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev)
{
struct tegra_ahub *ahub = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(ahub->clk);
if (err) {
dev_err(dev, "failed to enable AHUB clock, err: %d\n", err);
return err;
}
regcache_cache_only(ahub->regmap, false);
regcache_sync(ahub->regmap);
return 0;
}
static int tegra_ahub_probe(struct platform_device *pdev)
{
struct tegra_ahub *ahub;
void __iomem *regs;
int err;
ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL);
if (!ahub)
return -ENOMEM;
ahub->soc_data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, ahub);
ahub->clk = devm_clk_get(&pdev->dev, "ahub");
if (IS_ERR(ahub->clk)) {
dev_err(&pdev->dev, "can't retrieve AHUB clock\n");
return PTR_ERR(ahub->clk);
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
ahub->soc_data->regmap_config);
if (IS_ERR(ahub->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(ahub->regmap);
}
regcache_cache_only(ahub->regmap, true);
err = devm_snd_soc_register_component(&pdev->dev,
ahub->soc_data->cmpnt_drv,
ahub->soc_data->dai_drv,
ahub->soc_data->num_dais);
if (err) {
dev_err(&pdev->dev, "can't register AHUB component, err: %d\n",
err);
return err;
}
err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (err)
return err;
pm_runtime_enable(&pdev->dev);
return 0;
}
static void tegra_ahub_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra_ahub_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend,
tegra_ahub_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra_ahub_driver = {
.probe = tegra_ahub_probe,
.remove_new = tegra_ahub_remove,
.driver = {
.name = "tegra210-ahub",
.of_match_table = tegra_ahub_of_match,
.pm = &tegra_ahub_pm_ops,
},
};
module_platform_driver(tegra_ahub_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_AUTHOR("Mohan Kumar <[email protected]>");
MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_ahub.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_ope.c - Tegra210 OPE driver
//
// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_mbdrc.h"
#include "tegra210_ope.h"
#include "tegra210_peq.h"
#include "tegra_cif.h"
static const struct reg_default tegra210_ope_reg_defaults[] = {
{ TEGRA210_OPE_RX_INT_MASK, 0x00000001},
{ TEGRA210_OPE_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_OPE_TX_INT_MASK, 0x00000001},
{ TEGRA210_OPE_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_OPE_CG, 0x1},
};
static int tegra210_ope_set_audio_cif(struct tegra210_ope *ope,
struct snd_pcm_hw_params *params,
unsigned int reg)
{
int channels, audio_bits;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
if (channels < 2)
return -EINVAL;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = audio_bits;
tegra_set_cif(ope->regmap, reg, &cif_conf);
return 0;
}
static int tegra210_ope_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra210_ope *ope = snd_soc_dai_get_drvdata(dai);
int err;
/* Set RX and TX CIF */
err = tegra210_ope_set_audio_cif(ope, params,
TEGRA210_OPE_RX_CIF_CTRL);
if (err) {
dev_err(dev, "Can't set OPE RX CIF: %d\n", err);
return err;
}
err = tegra210_ope_set_audio_cif(ope, params,
TEGRA210_OPE_TX_CIF_CTRL);
if (err) {
dev_err(dev, "Can't set OPE TX CIF: %d\n", err);
return err;
}
tegra210_mbdrc_hw_params(dai->component);
return err;
}
static int tegra210_ope_component_probe(struct snd_soc_component *cmpnt)
{
struct tegra210_ope *ope = dev_get_drvdata(cmpnt->dev);
tegra210_peq_component_init(cmpnt);
tegra210_mbdrc_component_init(cmpnt);
/*
* The OPE, PEQ and MBDRC functionalities are combined under one
* device registered by OPE driver. In fact OPE HW block includes
* sub blocks PEQ and MBDRC. However driver registers separate
* regmap interfaces for each of these. ASoC core depends on
* dev_get_regmap() to populate the regmap field for a given ASoC
* component. A component can have one regmap reference and since
* the DAPM routes depend on OPE regmap only, below explicit
* assignment is done to highlight this. This is needed for ASoC
* core to access correct regmap during DAPM path setup.
*/
snd_soc_component_init_regmap(cmpnt, ope->regmap);
return 0;
}
static const struct snd_soc_dai_ops tegra210_ope_dai_ops = {
.hw_params = tegra210_ope_hw_params,
};
static struct snd_soc_dai_driver tegra210_ope_dais[] = {
{
.name = "OPE-RX-CIF",
.playback = {
.stream_name = "RX-CIF-Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "RX-CIF-Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
{
.name = "OPE-TX-CIF",
.playback = {
.stream_name = "TX-CIF-Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "TX-CIF-Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra210_ope_dai_ops,
}
};
static const struct snd_soc_dapm_widget tegra210_ope_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_OPE_ENABLE,
TEGRA210_OPE_EN_SHIFT, 0),
};
#define OPE_ROUTES(sname) \
{ "RX XBAR-" sname, NULL, "XBAR-TX" }, \
{ "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \
{ "RX", NULL, "RX-CIF-" sname }, \
{ "TX-CIF-" sname, NULL, "TX" }, \
{ "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \
{ "XBAR-RX", NULL, "TX XBAR-" sname }
static const struct snd_soc_dapm_route tegra210_ope_routes[] = {
{ "TX", NULL, "RX" },
OPE_ROUTES("Playback"),
OPE_ROUTES("Capture"),
};
static const char * const tegra210_ope_data_dir_text[] = {
"MBDRC to PEQ",
"PEQ to MBDRC"
};
static const struct soc_enum tegra210_ope_data_dir_enum =
SOC_ENUM_SINGLE(TEGRA210_OPE_DIR, TEGRA210_OPE_DIR_SHIFT,
2, tegra210_ope_data_dir_text);
static int tegra210_ope_get_data_dir(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.enumerated.item[0] = ope->data_dir;
return 0;
}
static int tegra210_ope_put_data_dir(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == ope->data_dir)
return 0;
ope->data_dir = value;
return 1;
}
static const struct snd_kcontrol_new tegra210_ope_controls[] = {
SOC_ENUM_EXT("Data Flow Direction", tegra210_ope_data_dir_enum,
tegra210_ope_get_data_dir, tegra210_ope_put_data_dir),
};
static const struct snd_soc_component_driver tegra210_ope_cmpnt = {
.probe = tegra210_ope_component_probe,
.dapm_widgets = tegra210_ope_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_ope_widgets),
.dapm_routes = tegra210_ope_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_ope_routes),
.controls = tegra210_ope_controls,
.num_controls = ARRAY_SIZE(tegra210_ope_controls),
};
static bool tegra210_ope_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_OPE_RX_INT_MASK ... TEGRA210_OPE_RX_CIF_CTRL:
case TEGRA210_OPE_TX_INT_MASK ... TEGRA210_OPE_TX_CIF_CTRL:
case TEGRA210_OPE_ENABLE ... TEGRA210_OPE_CG:
case TEGRA210_OPE_DIR:
return true;
default:
return false;
}
}
static bool tegra210_ope_rd_reg(struct device *dev, unsigned int reg)
{
if (tegra210_ope_wr_reg(dev, reg))
return true;
switch (reg) {
case TEGRA210_OPE_RX_STATUS:
case TEGRA210_OPE_RX_INT_STATUS:
case TEGRA210_OPE_TX_STATUS:
case TEGRA210_OPE_TX_INT_STATUS:
case TEGRA210_OPE_STATUS:
case TEGRA210_OPE_INT_STATUS:
return true;
default:
return false;
}
}
static bool tegra210_ope_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_OPE_RX_STATUS:
case TEGRA210_OPE_RX_INT_STATUS:
case TEGRA210_OPE_TX_STATUS:
case TEGRA210_OPE_TX_INT_STATUS:
case TEGRA210_OPE_SOFT_RESET:
case TEGRA210_OPE_STATUS:
case TEGRA210_OPE_INT_STATUS:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_ope_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_OPE_DIR,
.writeable_reg = tegra210_ope_wr_reg,
.readable_reg = tegra210_ope_rd_reg,
.volatile_reg = tegra210_ope_volatile_reg,
.reg_defaults = tegra210_ope_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_ope_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int tegra210_ope_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_ope *ope;
void __iomem *regs;
int err;
ope = devm_kzalloc(dev, sizeof(*ope), GFP_KERNEL);
if (!ope)
return -ENOMEM;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
ope->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_ope_regmap_config);
if (IS_ERR(ope->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(ope->regmap);
}
regcache_cache_only(ope->regmap, true);
dev_set_drvdata(dev, ope);
err = tegra210_peq_regmap_init(pdev);
if (err < 0) {
dev_err(dev, "PEQ init failed\n");
return err;
}
err = tegra210_mbdrc_regmap_init(pdev);
if (err < 0) {
dev_err(dev, "MBDRC init failed\n");
return err;
}
err = devm_snd_soc_register_component(dev, &tegra210_ope_cmpnt,
tegra210_ope_dais,
ARRAY_SIZE(tegra210_ope_dais));
if (err) {
dev_err(dev, "can't register OPE component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra210_ope_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused tegra210_ope_runtime_suspend(struct device *dev)
{
struct tegra210_ope *ope = dev_get_drvdata(dev);
tegra210_peq_save(ope->peq_regmap, ope->peq_biquad_gains,
ope->peq_biquad_shifts);
regcache_cache_only(ope->mbdrc_regmap, true);
regcache_cache_only(ope->peq_regmap, true);
regcache_cache_only(ope->regmap, true);
regcache_mark_dirty(ope->regmap);
regcache_mark_dirty(ope->peq_regmap);
regcache_mark_dirty(ope->mbdrc_regmap);
return 0;
}
static int __maybe_unused tegra210_ope_runtime_resume(struct device *dev)
{
struct tegra210_ope *ope = dev_get_drvdata(dev);
regcache_cache_only(ope->regmap, false);
regcache_cache_only(ope->peq_regmap, false);
regcache_cache_only(ope->mbdrc_regmap, false);
regcache_sync(ope->regmap);
regcache_sync(ope->peq_regmap);
regcache_sync(ope->mbdrc_regmap);
tegra210_peq_restore(ope->peq_regmap, ope->peq_biquad_gains,
ope->peq_biquad_shifts);
return 0;
}
static const struct dev_pm_ops tegra210_ope_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_ope_runtime_suspend,
tegra210_ope_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct of_device_id tegra210_ope_of_match[] = {
{ .compatible = "nvidia,tegra210-ope" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_ope_of_match);
static struct platform_driver tegra210_ope_driver = {
.driver = {
.name = "tegra210-ope",
.of_match_table = tegra210_ope_of_match,
.pm = &tegra210_ope_pm_ops,
},
.probe = tegra210_ope_probe,
.remove_new = tegra210_ope_remove,
};
module_platform_driver(tegra210_ope_driver)
MODULE_AUTHOR("Sumit Bhattacharya <[email protected]>");
MODULE_DESCRIPTION("Tegra210 OPE ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/tegra/tegra210_ope.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra_asoc_machine.c - Universal ASoC machine driver for NVIDIA Tegra boards.
*/
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra_asoc_machine.h"
/* Headphones Jack */
static struct snd_soc_jack tegra_machine_hp_jack;
static struct snd_soc_jack_pin tegra_machine_hp_jack_pins[] = {
{ .pin = "Headphone", .mask = SND_JACK_HEADPHONE },
{ .pin = "Headphones", .mask = SND_JACK_HEADPHONE },
};
static struct snd_soc_jack_gpio tegra_machine_hp_jack_gpio = {
.name = "Headphones detection",
.report = SND_JACK_HEADPHONE,
.debounce_time = 150,
};
/* Headset Jack */
static struct snd_soc_jack tegra_machine_headset_jack;
static struct snd_soc_jack_pin tegra_machine_headset_jack_pins[] = {
{ .pin = "Headset Mic", .mask = SND_JACK_MICROPHONE },
{ .pin = "Headset Stereophone", .mask = SND_JACK_HEADPHONE },
};
static struct snd_soc_jack_gpio tegra_machine_headset_jack_gpio = {
.name = "Headset detection",
.report = SND_JACK_HEADSET,
.debounce_time = 150,
};
/* Mic Jack */
static int coupled_mic_hp_check(void *data)
{
struct tegra_machine *machine = (struct tegra_machine *)data;
/* Detect mic insertion only if 3.5 jack is in */
if (gpiod_get_value_cansleep(machine->gpiod_hp_det) &&
gpiod_get_value_cansleep(machine->gpiod_mic_det))
return SND_JACK_MICROPHONE;
return 0;
}
static struct snd_soc_jack tegra_machine_mic_jack;
static struct snd_soc_jack_pin tegra_machine_mic_jack_pins[] = {
{ .pin = "Mic Jack", .mask = SND_JACK_MICROPHONE },
{ .pin = "Headset Mic", .mask = SND_JACK_MICROPHONE },
};
static struct snd_soc_jack_gpio tegra_machine_mic_jack_gpio = {
.name = "Mic detection",
.report = SND_JACK_MICROPHONE,
.debounce_time = 150,
};
static int tegra_machine_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct tegra_machine *machine = snd_soc_card_get_drvdata(dapm->card);
if (!strcmp(w->name, "Int Spk") || !strcmp(w->name, "Speakers"))
gpiod_set_value_cansleep(machine->gpiod_spkr_en,
SND_SOC_DAPM_EVENT_ON(event));
if (!strcmp(w->name, "Mic Jack") || !strcmp(w->name, "Headset Mic"))
gpiod_set_value_cansleep(machine->gpiod_ext_mic_en,
SND_SOC_DAPM_EVENT_ON(event));
if (!strcmp(w->name, "Int Mic") || !strcmp(w->name, "Internal Mic 2"))
gpiod_set_value_cansleep(machine->gpiod_int_mic_en,
SND_SOC_DAPM_EVENT_ON(event));
if (!strcmp(w->name, "Headphone") || !strcmp(w->name, "Headphone Jack"))
gpiod_set_value_cansleep(machine->gpiod_hp_mute,
!SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
static const struct snd_soc_dapm_widget tegra_machine_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", tegra_machine_event),
SND_SOC_DAPM_HP("Headphone", tegra_machine_event),
SND_SOC_DAPM_HP("Headset Stereophone", NULL),
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_SPK("Speakers", tegra_machine_event),
SND_SOC_DAPM_SPK("Int Spk", tegra_machine_event),
SND_SOC_DAPM_SPK("Earpiece", NULL),
SND_SOC_DAPM_MIC("Int Mic", tegra_machine_event),
SND_SOC_DAPM_MIC("Mic Jack", tegra_machine_event),
SND_SOC_DAPM_MIC("Internal Mic 1", NULL),
SND_SOC_DAPM_MIC("Internal Mic 2", tegra_machine_event),
SND_SOC_DAPM_MIC("Headset Mic", tegra_machine_event),
SND_SOC_DAPM_MIC("Digital Mic", NULL),
SND_SOC_DAPM_MIC("Mic", NULL),
SND_SOC_DAPM_LINE("Line In Jack", NULL),
SND_SOC_DAPM_LINE("Line In", NULL),
SND_SOC_DAPM_LINE("LineIn", NULL),
};
static const struct snd_kcontrol_new tegra_machine_controls[] = {
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Int Spk"),
SOC_DAPM_PIN_SWITCH("Earpiece"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Internal Mic 1"),
SOC_DAPM_PIN_SWITCH("Internal Mic 2"),
SOC_DAPM_PIN_SWITCH("Headphones"),
SOC_DAPM_PIN_SWITCH("Mic Jack"),
};
int tegra_asoc_machine_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct tegra_machine *machine = snd_soc_card_get_drvdata(card);
const char *jack_name;
int err;
if (machine->gpiod_hp_det && machine->asoc->add_hp_jack) {
if (machine->asoc->hp_jack_name)
jack_name = machine->asoc->hp_jack_name;
else
jack_name = "Headphones Jack";
err = snd_soc_card_jack_new_pins(card, jack_name,
SND_JACK_HEADPHONE,
&tegra_machine_hp_jack,
tegra_machine_hp_jack_pins,
ARRAY_SIZE(tegra_machine_hp_jack_pins));
if (err) {
dev_err(rtd->dev,
"Headphones Jack creation failed: %d\n", err);
return err;
}
tegra_machine_hp_jack_gpio.desc = machine->gpiod_hp_det;
err = snd_soc_jack_add_gpios(&tegra_machine_hp_jack, 1,
&tegra_machine_hp_jack_gpio);
if (err)
dev_err(rtd->dev, "HP GPIOs not added: %d\n", err);
}
if (machine->gpiod_hp_det && machine->asoc->add_headset_jack) {
err = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET,
&tegra_machine_headset_jack,
tegra_machine_headset_jack_pins,
ARRAY_SIZE(tegra_machine_headset_jack_pins));
if (err) {
dev_err(rtd->dev,
"Headset Jack creation failed: %d\n", err);
return err;
}
tegra_machine_headset_jack_gpio.desc = machine->gpiod_hp_det;
err = snd_soc_jack_add_gpios(&tegra_machine_headset_jack, 1,
&tegra_machine_headset_jack_gpio);
if (err)
dev_err(rtd->dev, "Headset GPIOs not added: %d\n", err);
}
if (machine->gpiod_mic_det && machine->asoc->add_mic_jack) {
err = snd_soc_card_jack_new_pins(rtd->card, "Mic Jack",
SND_JACK_MICROPHONE,
&tegra_machine_mic_jack,
tegra_machine_mic_jack_pins,
ARRAY_SIZE(tegra_machine_mic_jack_pins));
if (err) {
dev_err(rtd->dev, "Mic Jack creation failed: %d\n", err);
return err;
}
tegra_machine_mic_jack_gpio.data = machine;
tegra_machine_mic_jack_gpio.desc = machine->gpiod_mic_det;
if (of_property_read_bool(card->dev->of_node,
"nvidia,coupled-mic-hp-det")) {
tegra_machine_mic_jack_gpio.desc = machine->gpiod_hp_det;
tegra_machine_mic_jack_gpio.jack_status_check = coupled_mic_hp_check;
}
err = snd_soc_jack_add_gpios(&tegra_machine_mic_jack, 1,
&tegra_machine_mic_jack_gpio);
if (err)
dev_err(rtd->dev, "Mic GPIOs not added: %d\n", err);
}
return 0;
}
EXPORT_SYMBOL_GPL(tegra_asoc_machine_init);
static unsigned int tegra_machine_mclk_rate_128(unsigned int srate)
{
return 128 * srate;
}
static unsigned int tegra_machine_mclk_rate_256(unsigned int srate)
{
return 256 * srate;
}
static unsigned int tegra_machine_mclk_rate_512(unsigned int srate)
{
return 512 * srate;
}
static unsigned int tegra_machine_mclk_rate_12mhz(unsigned int srate)
{
unsigned int mclk;
switch (srate) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
default:
mclk = 12000000;
break;
}
return mclk;
}
static unsigned int tegra_machine_mclk_rate_6mhz(unsigned int srate)
{
unsigned int mclk;
switch (srate) {
case 8000:
case 16000:
case 64000:
mclk = 8192000;
break;
case 11025:
case 22050:
case 88200:
mclk = 11289600;
break;
case 96000:
mclk = 12288000;
break;
default:
mclk = 256 * srate;
break;
}
return mclk;
}
static int tegra_machine_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct tegra_machine *machine = snd_soc_card_get_drvdata(card);
unsigned int srate = params_rate(params);
unsigned int mclk = machine->asoc->mclk_rate(srate);
unsigned int clk_id = machine->asoc->mclk_id;
unsigned int new_baseclock;
int err;
switch (srate) {
case 11025:
case 22050:
case 44100:
case 88200:
if (of_machine_is_compatible("nvidia,tegra20"))
new_baseclock = 56448000;
else if (of_machine_is_compatible("nvidia,tegra30"))
new_baseclock = 564480000;
else
new_baseclock = 282240000;
break;
case 8000:
case 16000:
case 32000:
case 48000:
case 64000:
case 96000:
if (of_machine_is_compatible("nvidia,tegra20"))
new_baseclock = 73728000;
else if (of_machine_is_compatible("nvidia,tegra30"))
new_baseclock = 552960000;
else
new_baseclock = 368640000;
break;
default:
dev_err(card->dev, "Invalid sound rate: %u\n", srate);
return -EINVAL;
}
if (new_baseclock != machine->set_baseclock ||
mclk != machine->set_mclk) {
machine->set_baseclock = 0;
machine->set_mclk = 0;
clk_disable_unprepare(machine->clk_cdev1);
err = clk_set_rate(machine->clk_pll_a, new_baseclock);
if (err) {
dev_err(card->dev, "Can't set pll_a rate: %d\n", err);
return err;
}
err = clk_set_rate(machine->clk_pll_a_out0, mclk);
if (err) {
dev_err(card->dev, "Can't set pll_a_out0 rate: %d\n", err);
return err;
}
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
err = clk_prepare_enable(machine->clk_cdev1);
if (err) {
dev_err(card->dev, "Can't enable cdev1: %d\n", err);
return err;
}
machine->set_baseclock = new_baseclock;
machine->set_mclk = mclk;
}
err = snd_soc_dai_set_sysclk(codec_dai, clk_id, mclk, SND_SOC_CLOCK_IN);
if (err < 0) {
dev_err(card->dev, "codec_dai clock not set: %d\n", err);
return err;
}
return 0;
}
static const struct snd_soc_ops tegra_machine_snd_ops = {
.hw_params = tegra_machine_hw_params,
};
static void tegra_machine_node_release(void *of_node)
{
of_node_put(of_node);
}
static struct device_node *
tegra_machine_parse_phandle(struct device *dev, const char *name)
{
struct device_node *np;
int err;
np = of_parse_phandle(dev->of_node, name, 0);
if (!np) {
dev_err(dev, "Property '%s' missing or invalid\n", name);
return ERR_PTR(-EINVAL);
}
err = devm_add_action_or_reset(dev, tegra_machine_node_release, np);
if (err)
return ERR_PTR(err);
return np;
}
static void tegra_machine_unregister_codec(void *pdev)
{
platform_device_unregister(pdev);
}
static int tegra_machine_register_codec(struct device *dev, const char *name)
{
struct platform_device *pdev;
int err;
if (!name)
return 0;
pdev = platform_device_register_simple(name, -1, NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
err = devm_add_action_or_reset(dev, tegra_machine_unregister_codec,
pdev);
if (err)
return err;
return 0;
}
int tegra_asoc_machine_probe(struct platform_device *pdev)
{
struct device_node *np_codec, *np_i2s, *np_ac97;
const struct tegra_asoc_data *asoc;
struct device *dev = &pdev->dev;
struct tegra_machine *machine;
struct snd_soc_card *card;
struct gpio_desc *gpiod;
int err;
machine = devm_kzalloc(dev, sizeof(*machine), GFP_KERNEL);
if (!machine)
return -ENOMEM;
asoc = of_device_get_match_data(dev);
card = asoc->card;
card->dev = dev;
machine->asoc = asoc;
machine->mic_jack = &tegra_machine_mic_jack;
machine->hp_jack_gpio = &tegra_machine_hp_jack_gpio;
snd_soc_card_set_drvdata(card, machine);
gpiod = devm_gpiod_get_optional(dev, "nvidia,hp-mute", GPIOD_OUT_HIGH);
machine->gpiod_hp_mute = gpiod;
if (IS_ERR(gpiod))
return PTR_ERR(gpiod);
gpiod = devm_gpiod_get_optional(dev, "nvidia,hp-det", GPIOD_IN);
machine->gpiod_hp_det = gpiod;
if (IS_ERR(gpiod))
return PTR_ERR(gpiod);
gpiod = devm_gpiod_get_optional(dev, "nvidia,mic-det", GPIOD_IN);
machine->gpiod_mic_det = gpiod;
if (IS_ERR(gpiod))
return PTR_ERR(gpiod);
gpiod = devm_gpiod_get_optional(dev, "nvidia,spkr-en", GPIOD_OUT_LOW);
machine->gpiod_spkr_en = gpiod;
if (IS_ERR(gpiod))
return PTR_ERR(gpiod);
gpiod = devm_gpiod_get_optional(dev, "nvidia,int-mic-en", GPIOD_OUT_LOW);
machine->gpiod_int_mic_en = gpiod;
if (IS_ERR(gpiod))
return PTR_ERR(gpiod);
gpiod = devm_gpiod_get_optional(dev, "nvidia,ext-mic-en", GPIOD_OUT_LOW);
machine->gpiod_ext_mic_en = gpiod;
if (IS_ERR(gpiod))
return PTR_ERR(gpiod);
err = snd_soc_of_parse_card_name(card, "nvidia,model");
if (err)
return err;
if (!card->dapm_routes) {
err = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
if (err)
return err;
}
if (asoc->set_ac97) {
err = tegra_machine_register_codec(dev, asoc->codec_dev_name);
if (err)
return err;
np_ac97 = tegra_machine_parse_phandle(dev, "nvidia,ac97-controller");
if (IS_ERR(np_ac97))
return PTR_ERR(np_ac97);
card->dai_link->cpus->of_node = np_ac97;
card->dai_link->platforms->of_node = np_ac97;
} else {
np_codec = tegra_machine_parse_phandle(dev, "nvidia,audio-codec");
if (IS_ERR(np_codec))
return PTR_ERR(np_codec);
np_i2s = tegra_machine_parse_phandle(dev, "nvidia,i2s-controller");
if (IS_ERR(np_i2s))
return PTR_ERR(np_i2s);
card->dai_link->cpus->of_node = np_i2s;
card->dai_link->codecs->of_node = np_codec;
card->dai_link->platforms->of_node = np_i2s;
}
if (asoc->add_common_controls) {
card->controls = tegra_machine_controls;
card->num_controls = ARRAY_SIZE(tegra_machine_controls);
}
if (asoc->add_common_dapm_widgets) {
card->dapm_widgets = tegra_machine_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(tegra_machine_dapm_widgets);
}
if (asoc->add_common_snd_ops)
card->dai_link->ops = &tegra_machine_snd_ops;
if (!card->owner)
card->owner = THIS_MODULE;
if (!card->driver_name)
card->driver_name = "tegra";
machine->clk_pll_a = devm_clk_get(dev, "pll_a");
if (IS_ERR(machine->clk_pll_a)) {
dev_err(dev, "Can't retrieve clk pll_a\n");
return PTR_ERR(machine->clk_pll_a);
}
machine->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
if (IS_ERR(machine->clk_pll_a_out0)) {
dev_err(dev, "Can't retrieve clk pll_a_out0\n");
return PTR_ERR(machine->clk_pll_a_out0);
}
machine->clk_cdev1 = devm_clk_get(dev, "mclk");
if (IS_ERR(machine->clk_cdev1)) {
dev_err(dev, "Can't retrieve clk cdev1\n");
return PTR_ERR(machine->clk_cdev1);
}
/*
* If clock parents are not set in DT, configure here to use clk_out_1
* as mclk and extern1 as parent for Tegra30 and higher.
*/
if (!of_property_present(dev->of_node, "assigned-clock-parents") &&
!of_machine_is_compatible("nvidia,tegra20")) {
struct clk *clk_out_1, *clk_extern1;
dev_warn(dev, "Configuring clocks for a legacy device-tree\n");
dev_warn(dev, "Please update DT to use assigned-clock-parents\n");
clk_extern1 = devm_clk_get(dev, "extern1");
if (IS_ERR(clk_extern1)) {
dev_err(dev, "Can't retrieve clk extern1\n");
return PTR_ERR(clk_extern1);
}
err = clk_set_parent(clk_extern1, machine->clk_pll_a_out0);
if (err < 0) {
dev_err(dev, "Set parent failed for clk extern1\n");
return err;
}
clk_out_1 = devm_clk_get(dev, "pmc_clk_out_1");
if (IS_ERR(clk_out_1)) {
dev_err(dev, "Can't retrieve pmc_clk_out_1\n");
return PTR_ERR(clk_out_1);
}
err = clk_set_parent(clk_out_1, clk_extern1);
if (err < 0) {
dev_err(dev, "Set parent failed for pmc_clk_out_1\n");
return err;
}
machine->clk_cdev1 = clk_out_1;
}
if (asoc->set_ac97) {
/*
* AC97 rate is fixed at 24.576MHz and is used for both the
* host controller and the external codec
*/
err = clk_set_rate(machine->clk_pll_a, 73728000);
if (err) {
dev_err(dev, "Can't set pll_a rate: %d\n", err);
return err;
}
err = clk_set_rate(machine->clk_pll_a_out0, 24576000);
if (err) {
dev_err(dev, "Can't set pll_a_out0 rate: %d\n", err);
return err;
}
machine->set_baseclock = 73728000;
machine->set_mclk = 24576000;
}
/*
* FIXME: There is some unknown dependency between audio MCLK disable
* and suspend-resume functionality on Tegra30, although audio MCLK is
* only needed for audio.
*/
err = clk_prepare_enable(machine->clk_cdev1);
if (err) {
dev_err(dev, "Can't enable cdev1: %d\n", err);
return err;
}
err = devm_snd_soc_register_card(dev, card);
if (err)
return err;
return 0;
}
EXPORT_SYMBOL_GPL(tegra_asoc_machine_probe);
/* WM8753 machine */
SND_SOC_DAILINK_DEFS(wm8753_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8753-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_wm8753_dai = {
.name = "WM8753",
.stream_name = "WM8753 PCM",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(wm8753_hifi),
};
static struct snd_soc_card snd_soc_tegra_wm8753 = {
.components = "codec:wm8753",
.dai_link = &tegra_wm8753_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_wm8753_data = {
.mclk_rate = tegra_machine_mclk_rate_12mhz,
.card = &snd_soc_tegra_wm8753,
.add_common_dapm_widgets = true,
.add_common_snd_ops = true,
};
/* WM9712 machine */
static int tegra_wm9712_init(struct snd_soc_pcm_runtime *rtd)
{
return snd_soc_dapm_force_enable_pin(&rtd->card->dapm, "Mic Bias");
}
SND_SOC_DAILINK_DEFS(wm9712_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9712-codec", "wm9712-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_wm9712_dai = {
.name = "AC97 HiFi",
.stream_name = "AC97 HiFi",
.init = tegra_wm9712_init,
SND_SOC_DAILINK_REG(wm9712_hifi),
};
static struct snd_soc_card snd_soc_tegra_wm9712 = {
.components = "codec:wm9712",
.dai_link = &tegra_wm9712_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_wm9712_data = {
.card = &snd_soc_tegra_wm9712,
.add_common_dapm_widgets = true,
.codec_dev_name = "wm9712-codec",
.set_ac97 = true,
};
/* MAX98090 machine */
SND_SOC_DAILINK_DEFS(max98090_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_max98090_dai = {
.name = "max98090",
.stream_name = "max98090 PCM",
.init = tegra_asoc_machine_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(max98090_hifi),
};
static struct snd_soc_card snd_soc_tegra_max98090 = {
.components = "codec:max98090",
.dai_link = &tegra_max98090_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_max98090_data = {
.mclk_rate = tegra_machine_mclk_rate_12mhz,
.card = &snd_soc_tegra_max98090,
.hp_jack_name = "Headphones",
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_mic_jack = true,
.add_hp_jack = true,
};
/* MAX98088 machine */
SND_SOC_DAILINK_DEFS(max98088_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_max98088_dai = {
.name = "MAX98088",
.stream_name = "MAX98088 PCM",
.init = tegra_asoc_machine_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(max98088_hifi),
};
static struct snd_soc_card snd_soc_tegra_max98088 = {
.components = "codec:max98088",
.dai_link = &tegra_max98088_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_max98088_data = {
.mclk_rate = tegra_machine_mclk_rate_12mhz,
.card = &snd_soc_tegra_max98088,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_mic_jack = true,
.add_hp_jack = true,
};
/* SGTL5000 machine */
SND_SOC_DAILINK_DEFS(sgtl5000_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "sgtl5000")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_sgtl5000_dai = {
.name = "sgtl5000",
.stream_name = "HiFi",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(sgtl5000_hifi),
};
static struct snd_soc_card snd_soc_tegra_sgtl5000 = {
.components = "codec:sgtl5000",
.dai_link = &tegra_sgtl5000_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_sgtl5000_data = {
.mclk_rate = tegra_machine_mclk_rate_12mhz,
.card = &snd_soc_tegra_sgtl5000,
.add_common_dapm_widgets = true,
.add_common_snd_ops = true,
};
/* TLV320AIC23 machine */
static const struct snd_soc_dapm_widget trimslice_dapm_widgets[] = {
SND_SOC_DAPM_HP("Line Out", NULL),
SND_SOC_DAPM_LINE("Line In", NULL),
};
static const struct snd_soc_dapm_route trimslice_audio_map[] = {
{"Line Out", NULL, "LOUT"},
{"Line Out", NULL, "ROUT"},
{"LLINEIN", NULL, "Line In"},
{"RLINEIN", NULL, "Line In"},
};
SND_SOC_DAILINK_DEFS(tlv320aic23_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "tlv320aic23-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_tlv320aic23_dai = {
.name = "TLV320AIC23",
.stream_name = "AIC23",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(tlv320aic23_hifi),
};
static struct snd_soc_card snd_soc_tegra_trimslice = {
.name = "tegra-trimslice",
.components = "codec:tlv320aic23",
.dai_link = &tegra_tlv320aic23_dai,
.num_links = 1,
.dapm_widgets = trimslice_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(trimslice_dapm_widgets),
.dapm_routes = trimslice_audio_map,
.num_dapm_routes = ARRAY_SIZE(trimslice_audio_map),
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_trimslice_data = {
.mclk_rate = tegra_machine_mclk_rate_128,
.card = &snd_soc_tegra_trimslice,
.add_common_snd_ops = true,
};
/* RT5677 machine */
static int tegra_rt5677_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
int err;
err = tegra_asoc_machine_init(rtd);
if (err)
return err;
snd_soc_dapm_force_enable_pin(&card->dapm, "MICBIAS1");
return 0;
}
SND_SOC_DAILINK_DEFS(rt5677_aif1,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5677-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_rt5677_dai = {
.name = "RT5677",
.stream_name = "RT5677 PCM",
.init = tegra_rt5677_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(rt5677_aif1),
};
static struct snd_soc_card snd_soc_tegra_rt5677 = {
.components = "codec:rt5677",
.dai_link = &tegra_rt5677_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_rt5677_data = {
.mclk_rate = tegra_machine_mclk_rate_256,
.card = &snd_soc_tegra_rt5677,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_mic_jack = true,
.add_hp_jack = true,
};
/* RT5640 machine */
SND_SOC_DAILINK_DEFS(rt5640_aif1,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5640-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_rt5640_dai = {
.name = "RT5640",
.stream_name = "RT5640 PCM",
.init = tegra_asoc_machine_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(rt5640_aif1),
};
static struct snd_soc_card snd_soc_tegra_rt5640 = {
.components = "codec:rt5640",
.dai_link = &tegra_rt5640_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_rt5640_data = {
.mclk_rate = tegra_machine_mclk_rate_256,
.card = &snd_soc_tegra_rt5640,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_hp_jack = true,
};
/* RT5632 machine */
SND_SOC_DAILINK_DEFS(rt5632_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "alc5632-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_rt5632_dai = {
.name = "ALC5632",
.stream_name = "ALC5632 PCM",
.init = tegra_rt5677_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(rt5632_hifi),
};
static struct snd_soc_card snd_soc_tegra_rt5632 = {
.components = "codec:rt5632",
.dai_link = &tegra_rt5632_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_rt5632_data = {
.mclk_rate = tegra_machine_mclk_rate_512,
.card = &snd_soc_tegra_rt5632,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_headset_jack = true,
};
/* RT5631 machine */
SND_SOC_DAILINK_DEFS(rt5631_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5631-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_rt5631_dai = {
.name = "RT5631",
.stream_name = "RT5631 PCM",
.init = tegra_asoc_machine_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(rt5631_hifi),
};
static struct snd_soc_card snd_soc_tegra_rt5631 = {
.components = "codec:rt5631",
.dai_link = &tegra_rt5631_dai,
.num_links = 1,
.fully_routed = true,
};
static const struct tegra_asoc_data tegra_rt5631_data = {
.mclk_rate = tegra_machine_mclk_rate_6mhz,
.card = &snd_soc_tegra_rt5631,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_mic_jack = true,
.add_hp_jack = true,
};
static const struct of_device_id tegra_machine_of_match[] = {
{ .compatible = "nvidia,tegra-audio-trimslice", .data = &tegra_trimslice_data },
{ .compatible = "nvidia,tegra-audio-max98090", .data = &tegra_max98090_data },
{ .compatible = "nvidia,tegra-audio-max98088", .data = &tegra_max98088_data },
{ .compatible = "nvidia,tegra-audio-max98089", .data = &tegra_max98088_data },
{ .compatible = "nvidia,tegra-audio-sgtl5000", .data = &tegra_sgtl5000_data },
{ .compatible = "nvidia,tegra-audio-wm9712", .data = &tegra_wm9712_data },
{ .compatible = "nvidia,tegra-audio-wm8753", .data = &tegra_wm8753_data },
{ .compatible = "nvidia,tegra-audio-rt5677", .data = &tegra_rt5677_data },
{ .compatible = "nvidia,tegra-audio-rt5640", .data = &tegra_rt5640_data },
{ .compatible = "nvidia,tegra-audio-alc5632", .data = &tegra_rt5632_data },
{ .compatible = "nvidia,tegra-audio-rt5631", .data = &tegra_rt5631_data },
{},
};
MODULE_DEVICE_TABLE(of, tegra_machine_of_match);
static struct platform_driver tegra_asoc_machine_driver = {
.driver = {
.name = "tegra-audio",
.of_match_table = tegra_machine_of_match,
.pm = &snd_soc_pm_ops,
},
.probe = tegra_asoc_machine_probe,
};
module_platform_driver(tegra_asoc_machine_driver);
MODULE_AUTHOR("Anatol Pomozov <[email protected]>");
MODULE_AUTHOR("Andrey Danin <[email protected]>");
MODULE_AUTHOR("Dmitry Osipenko <[email protected]>");
MODULE_AUTHOR("Ion Agorria <[email protected]>");
MODULE_AUTHOR("Leon Romanovsky <[email protected]>");
MODULE_AUTHOR("Lucas Stach <[email protected]>");
MODULE_AUTHOR("Marc Dietrich <[email protected]>");
MODULE_AUTHOR("Marcel Ziswiler <[email protected]>");
MODULE_AUTHOR("Mike Rapoport <[email protected]>");
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_AUTHOR("Svyatoslav Ryhel <[email protected]>");
MODULE_DESCRIPTION("Tegra machine ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/tegra/tegra_asoc_machine.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_mvc.c - Tegra210 MVC driver
//
// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_mvc.h"
#include "tegra_cif.h"
static const struct reg_default tegra210_mvc_reg_defaults[] = {
{ TEGRA210_MVC_RX_INT_MASK, 0x00000001},
{ TEGRA210_MVC_RX_CIF_CTRL, 0x00007700},
{ TEGRA210_MVC_TX_INT_MASK, 0x00000001},
{ TEGRA210_MVC_TX_CIF_CTRL, 0x00007700},
{ TEGRA210_MVC_CG, 0x1},
{ TEGRA210_MVC_CTRL, TEGRA210_MVC_CTRL_DEFAULT},
{ TEGRA210_MVC_INIT_VOL, 0x00800000},
{ TEGRA210_MVC_TARGET_VOL, 0x00800000},
{ TEGRA210_MVC_DURATION, 0x000012c0},
{ TEGRA210_MVC_DURATION_INV, 0x0006d3a0},
{ TEGRA210_MVC_POLY_N1, 0x0000007d},
{ TEGRA210_MVC_POLY_N2, 0x00000271},
{ TEGRA210_MVC_PEAK_CTRL, 0x000012c0},
{ TEGRA210_MVC_CFG_RAM_CTRL, 0x00004000},
};
static const struct tegra210_mvc_gain_params gain_params = {
.poly_coeff = { 23738319, 659403, -3680,
15546680, 2530732, -120985,
12048422, 5527252, -785042 },
.poly_n1 = 16,
.poly_n2 = 63,
.duration = 150,
.duration_inv = 14316558,
};
static int __maybe_unused tegra210_mvc_runtime_suspend(struct device *dev)
{
struct tegra210_mvc *mvc = dev_get_drvdata(dev);
regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &(mvc->ctrl_value));
regcache_cache_only(mvc->regmap, true);
regcache_mark_dirty(mvc->regmap);
return 0;
}
static int __maybe_unused tegra210_mvc_runtime_resume(struct device *dev)
{
struct tegra210_mvc *mvc = dev_get_drvdata(dev);
regcache_cache_only(mvc->regmap, false);
regcache_sync(mvc->regmap);
regmap_write(mvc->regmap, TEGRA210_MVC_CTRL, mvc->ctrl_value);
regmap_update_bits(mvc->regmap,
TEGRA210_MVC_SWITCH,
TEGRA210_MVC_VOLUME_SWITCH_MASK,
TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
return 0;
}
static void tegra210_mvc_write_ram(struct regmap *regmap)
{
int i;
regmap_write(regmap, TEGRA210_MVC_CFG_RAM_CTRL,
TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN |
TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN |
TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE);
for (i = 0; i < NUM_GAIN_POLY_COEFFS; i++)
regmap_write(regmap, TEGRA210_MVC_CFG_RAM_DATA,
gain_params.poly_coeff[i]);
}
static void tegra210_mvc_conv_vol(struct tegra210_mvc *mvc, u8 chan, s32 val)
{
/*
* Volume control read from mixer control is with
* 100x scaling; for CURVE_POLY the reg range
* is 0-100 (linear, Q24) and for CURVE_LINEAR
* it is -120dB to +40dB (Q8)
*/
if (mvc->curve_type == CURVE_POLY) {
if (val > 10000)
val = 10000;
mvc->volume[chan] = ((val * (1<<8)) / 100) << 16;
} else {
val -= 12000;
mvc->volume[chan] = (val * (1<<8)) / 100;
}
}
static u32 tegra210_mvc_get_ctrl_reg(struct snd_kcontrol *kcontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
u32 val;
pm_runtime_get_sync(cmpnt->dev);
regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &val);
pm_runtime_put(cmpnt->dev);
return val;
}
static int tegra210_mvc_get_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u32 val = tegra210_mvc_get_ctrl_reg(kcontrol);
u8 mute_mask = TEGRA210_GET_MUTE_VAL(val);
/*
* If per channel control is enabled, then return
* exact mute/unmute setting of all channels.
*
* Else report setting based on CH0 bit to reflect
* the correct HW state.
*/
if (val & TEGRA210_MVC_PER_CHAN_CTRL_EN) {
ucontrol->value.integer.value[0] = mute_mask;
} else {
if (mute_mask & TEGRA210_MVC_CH0_MUTE_EN)
ucontrol->value.integer.value[0] =
TEGRA210_MUTE_MASK_EN;
else
ucontrol->value.integer.value[0] = 0;
}
return 0;
}
static int tegra210_mvc_get_master_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u32 val = tegra210_mvc_get_ctrl_reg(kcontrol);
u8 mute_mask = TEGRA210_GET_MUTE_VAL(val);
/*
* If per channel control is disabled, then return
* master mute/unmute setting based on CH0 bit.
*
* Else report settings based on state of all
* channels.
*/
if (!(val & TEGRA210_MVC_PER_CHAN_CTRL_EN)) {
ucontrol->value.integer.value[0] =
mute_mask & TEGRA210_MVC_CH0_MUTE_EN;
} else {
if (mute_mask == TEGRA210_MUTE_MASK_EN)
ucontrol->value.integer.value[0] =
TEGRA210_MVC_CH0_MUTE_EN;
else
ucontrol->value.integer.value[0] = 0;
}
return 0;
}
static int tegra210_mvc_volume_switch_timeout(struct snd_soc_component *cmpnt)
{
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
u32 value;
int err;
err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SWITCH,
value, !(value & TEGRA210_MVC_VOLUME_SWITCH_MASK),
10, 10000);
if (err < 0)
dev_err(cmpnt->dev,
"Volume switch trigger is still active, err = %d\n",
err);
return err;
}
static int tegra210_mvc_update_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol,
bool per_chan_ctrl)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
u32 mute_val = ucontrol->value.integer.value[0];
u32 per_ch_ctrl_val;
bool change = false;
int err;
pm_runtime_get_sync(cmpnt->dev);
err = tegra210_mvc_volume_switch_timeout(cmpnt);
if (err < 0)
goto end;
if (per_chan_ctrl) {
per_ch_ctrl_val = TEGRA210_MVC_PER_CHAN_CTRL_EN;
} else {
per_ch_ctrl_val = 0;
if (mute_val)
mute_val = TEGRA210_MUTE_MASK_EN;
}
regmap_update_bits_check(mvc->regmap, TEGRA210_MVC_CTRL,
TEGRA210_MVC_MUTE_MASK,
mute_val << TEGRA210_MVC_MUTE_SHIFT,
&change);
if (change) {
regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK,
per_ch_ctrl_val);
regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
TEGRA210_MVC_VOLUME_SWITCH_MASK,
TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
}
end:
pm_runtime_put(cmpnt->dev);
if (err < 0)
return err;
if (change)
return 1;
return 0;
}
static int tegra210_mvc_put_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mvc_update_mute(kcontrol, ucontrol, true);
}
static int tegra210_mvc_put_master_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mvc_update_mute(kcontrol, ucontrol, false);
}
static int tegra210_mvc_get_vol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
u8 chan = TEGRA210_MVC_GET_CHAN(mc->reg, TEGRA210_MVC_TARGET_VOL);
s32 val = mvc->volume[chan];
if (mvc->curve_type == CURVE_POLY) {
val = ((val >> 16) * 100) >> 8;
} else {
val = (val * 100) >> 8;
val += 12000;
}
ucontrol->value.integer.value[0] = val;
return 0;
}
static int tegra210_mvc_get_master_vol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mvc_get_vol(kcontrol, ucontrol);
}
static int tegra210_mvc_update_vol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol,
bool per_ch_enable)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
u8 chan = TEGRA210_MVC_GET_CHAN(mc->reg, TEGRA210_MVC_TARGET_VOL);
int old_volume = mvc->volume[chan];
int err, i;
pm_runtime_get_sync(cmpnt->dev);
err = tegra210_mvc_volume_switch_timeout(cmpnt);
if (err < 0)
goto end;
tegra210_mvc_conv_vol(mvc, chan, ucontrol->value.integer.value[0]);
if (mvc->volume[chan] == old_volume) {
err = 0;
goto end;
}
if (per_ch_enable) {
regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK,
TEGRA210_MVC_PER_CHAN_CTRL_EN);
} else {
regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK, 0);
for (i = 1; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++)
mvc->volume[i] = mvc->volume[chan];
}
/* Configure init volume same as target volume */
regmap_write(mvc->regmap,
TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_INIT_VOL, chan),
mvc->volume[chan]);
regmap_write(mvc->regmap, mc->reg, mvc->volume[chan]);
regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
TEGRA210_MVC_VOLUME_SWITCH_MASK,
TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
err = 1;
end:
pm_runtime_put(cmpnt->dev);
return err;
}
static int tegra210_mvc_put_vol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mvc_update_vol(kcontrol, ucontrol, true);
}
static int tegra210_mvc_put_master_vol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return tegra210_mvc_update_vol(kcontrol, ucontrol, false);
}
static void tegra210_mvc_reset_vol_settings(struct tegra210_mvc *mvc,
struct device *dev)
{
int i;
/* Change volume to default init for new curve type */
if (mvc->curve_type == CURVE_POLY) {
for (i = 0; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++)
mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_POLY;
} else {
for (i = 0; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++)
mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR;
}
pm_runtime_get_sync(dev);
/* Program curve type */
regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
TEGRA210_MVC_CURVE_TYPE_MASK,
mvc->curve_type <<
TEGRA210_MVC_CURVE_TYPE_SHIFT);
/* Init volume for all channels */
for (i = 0; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++) {
regmap_write(mvc->regmap,
TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_INIT_VOL, i),
mvc->volume[i]);
regmap_write(mvc->regmap,
TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_TARGET_VOL, i),
mvc->volume[i]);
}
/* Trigger volume switch */
regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
TEGRA210_MVC_VOLUME_SWITCH_MASK,
TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
pm_runtime_put(dev);
}
static int tegra210_mvc_get_curve_type(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.enumerated.item[0] = mvc->curve_type;
return 0;
}
static int tegra210_mvc_put_curve_type(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
unsigned int value;
regmap_read(mvc->regmap, TEGRA210_MVC_ENABLE, &value);
if (value & TEGRA210_MVC_EN) {
dev_err(cmpnt->dev,
"Curve type can't be set when MVC is running\n");
return -EINVAL;
}
if (mvc->curve_type == ucontrol->value.enumerated.item[0])
return 0;
mvc->curve_type = ucontrol->value.enumerated.item[0];
tegra210_mvc_reset_vol_settings(mvc, cmpnt->dev);
return 1;
}
static int tegra210_mvc_set_audio_cif(struct tegra210_mvc *mvc,
struct snd_pcm_hw_params *params,
unsigned int reg)
{
unsigned int channels, audio_bits;
struct tegra_cif_conf cif_conf;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
return -EINVAL;
}
cif_conf.audio_ch = channels;
cif_conf.client_ch = channels;
cif_conf.audio_bits = audio_bits;
cif_conf.client_bits = audio_bits;
tegra_set_cif(mvc->regmap, reg, &cif_conf);
return 0;
}
static int tegra210_mvc_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra210_mvc *mvc = snd_soc_dai_get_drvdata(dai);
int err, val;
/*
* Soft Reset: Below performs module soft reset which clears
* all FSM logic, flushes flow control of FIFO and resets the
* state register. It also brings module back to disabled
* state (without flushing the data in the pipe).
*/
regmap_write(mvc->regmap, TEGRA210_MVC_SOFT_RESET, 1);
err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SOFT_RESET,
val, !val, 10, 10000);
if (err < 0) {
dev_err(dev, "SW reset failed, err = %d\n", err);
return err;
}
/* Set RX CIF */
err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_RX_CIF_CTRL);
if (err) {
dev_err(dev, "Can't set MVC RX CIF: %d\n", err);
return err;
}
/* Set TX CIF */
err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_TX_CIF_CTRL);
if (err) {
dev_err(dev, "Can't set MVC TX CIF: %d\n", err);
return err;
}
tegra210_mvc_write_ram(mvc->regmap);
/* Program poly_n1, poly_n2, duration */
regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N1, gain_params.poly_n1);
regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N2, gain_params.poly_n2);
regmap_write(mvc->regmap, TEGRA210_MVC_DURATION, gain_params.duration);
/* Program duration_inv */
regmap_write(mvc->regmap, TEGRA210_MVC_DURATION_INV,
gain_params.duration_inv);
return 0;
}
static const struct snd_soc_dai_ops tegra210_mvc_dai_ops = {
.hw_params = tegra210_mvc_hw_params,
};
static const char * const tegra210_mvc_curve_type_text[] = {
"Poly",
"Linear",
};
static const struct soc_enum tegra210_mvc_curve_type_ctrl =
SOC_ENUM_SINGLE_EXT(2, tegra210_mvc_curve_type_text);
#define TEGRA210_MVC_VOL_CTRL(chan) \
SOC_SINGLE_EXT("Channel" #chan " Volume", \
TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_TARGET_VOL, \
(chan - 1)), \
0, 16000, 0, tegra210_mvc_get_vol, \
tegra210_mvc_put_vol)
static const struct snd_kcontrol_new tegra210_mvc_vol_ctrl[] = {
/* Per channel volume control */
TEGRA210_MVC_VOL_CTRL(1),
TEGRA210_MVC_VOL_CTRL(2),
TEGRA210_MVC_VOL_CTRL(3),
TEGRA210_MVC_VOL_CTRL(4),
TEGRA210_MVC_VOL_CTRL(5),
TEGRA210_MVC_VOL_CTRL(6),
TEGRA210_MVC_VOL_CTRL(7),
TEGRA210_MVC_VOL_CTRL(8),
/* Per channel mute */
SOC_SINGLE_EXT("Per Chan Mute Mask",
TEGRA210_MVC_CTRL, 0, TEGRA210_MUTE_MASK_EN, 0,
tegra210_mvc_get_mute, tegra210_mvc_put_mute),
/* Master volume */
SOC_SINGLE_EXT("Volume", TEGRA210_MVC_TARGET_VOL, 0, 16000, 0,
tegra210_mvc_get_master_vol,
tegra210_mvc_put_master_vol),
/* Master mute */
SOC_SINGLE_EXT("Mute", TEGRA210_MVC_CTRL, 0, 1, 0,
tegra210_mvc_get_master_mute,
tegra210_mvc_put_master_mute),
SOC_ENUM_EXT("Curve Type", tegra210_mvc_curve_type_ctrl,
tegra210_mvc_get_curve_type, tegra210_mvc_put_curve_type),
};
static struct snd_soc_dai_driver tegra210_mvc_dais[] = {
/* Input */
{
.name = "MVC-RX-CIF",
.playback = {
.stream_name = "RX-CIF-Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "RX-CIF-Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
/* Output */
{
.name = "MVC-TX-CIF",
.playback = {
.stream_name = "TX-CIF-Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.stream_name = "TX-CIF-Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra210_mvc_dai_ops,
}
};
static const struct snd_soc_dapm_widget tegra210_mvc_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_MVC_ENABLE,
TEGRA210_MVC_EN_SHIFT, 0),
};
#define MVC_ROUTES(sname) \
{ "RX XBAR-" sname, NULL, "XBAR-TX" }, \
{ "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \
{ "RX", NULL, "RX-CIF-" sname }, \
{ "TX-CIF-" sname, NULL, "TX" }, \
{ "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \
{ "XBAR-RX", NULL, "TX XBAR-" sname }
static const struct snd_soc_dapm_route tegra210_mvc_routes[] = {
{ "TX", NULL, "RX" },
MVC_ROUTES("Playback"),
MVC_ROUTES("Capture"),
};
static const struct snd_soc_component_driver tegra210_mvc_cmpnt = {
.dapm_widgets = tegra210_mvc_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_mvc_widgets),
.dapm_routes = tegra210_mvc_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_mvc_routes),
.controls = tegra210_mvc_vol_ctrl,
.num_controls = ARRAY_SIZE(tegra210_mvc_vol_ctrl),
};
static bool tegra210_mvc_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_MVC_RX_STATUS ... TEGRA210_MVC_CONFIG_ERR_TYPE:
return true;
default:
return false;
};
}
static bool tegra210_mvc_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_MVC_RX_INT_MASK ... TEGRA210_MVC_RX_CIF_CTRL:
case TEGRA210_MVC_TX_INT_MASK ... TEGRA210_MVC_TX_CIF_CTRL:
case TEGRA210_MVC_ENABLE ... TEGRA210_MVC_CG:
case TEGRA210_MVC_CTRL ... TEGRA210_MVC_CFG_RAM_DATA:
return true;
default:
return false;
}
}
static bool tegra210_mvc_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_MVC_RX_STATUS:
case TEGRA210_MVC_RX_INT_STATUS:
case TEGRA210_MVC_RX_INT_SET:
case TEGRA210_MVC_TX_STATUS:
case TEGRA210_MVC_TX_INT_STATUS:
case TEGRA210_MVC_TX_INT_SET:
case TEGRA210_MVC_SOFT_RESET:
case TEGRA210_MVC_STATUS:
case TEGRA210_MVC_INT_STATUS:
case TEGRA210_MVC_SWITCH:
case TEGRA210_MVC_CFG_RAM_CTRL:
case TEGRA210_MVC_CFG_RAM_DATA:
case TEGRA210_MVC_PEAK_VALUE:
case TEGRA210_MVC_CTRL:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_mvc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_MVC_CONFIG_ERR_TYPE,
.writeable_reg = tegra210_mvc_wr_reg,
.readable_reg = tegra210_mvc_rd_reg,
.volatile_reg = tegra210_mvc_volatile_reg,
.reg_defaults = tegra210_mvc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_mvc_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id tegra210_mvc_of_match[] = {
{ .compatible = "nvidia,tegra210-mvc" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_mvc_of_match);
static int tegra210_mvc_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_mvc *mvc;
void __iomem *regs;
int err;
mvc = devm_kzalloc(dev, sizeof(*mvc), GFP_KERNEL);
if (!mvc)
return -ENOMEM;
dev_set_drvdata(dev, mvc);
mvc->curve_type = CURVE_LINEAR;
mvc->ctrl_value = TEGRA210_MVC_CTRL_DEFAULT;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
mvc->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_mvc_regmap_config);
if (IS_ERR(mvc->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(mvc->regmap);
}
regcache_cache_only(mvc->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_mvc_cmpnt,
tegra210_mvc_dais,
ARRAY_SIZE(tegra210_mvc_dais));
if (err) {
dev_err(dev, "can't register MVC component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
tegra210_mvc_reset_vol_settings(mvc, &pdev->dev);
return 0;
}
static void tegra210_mvc_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_mvc_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_mvc_runtime_suspend,
tegra210_mvc_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra210_mvc_driver = {
.driver = {
.name = "tegra210-mvc",
.of_match_table = tegra210_mvc_of_match,
.pm = &tegra210_mvc_pm_ops,
},
.probe = tegra210_mvc_platform_probe,
.remove_new = tegra210_mvc_platform_remove,
};
module_platform_driver(tegra210_mvc_driver)
MODULE_AUTHOR("Arun Shamanna Lakshmi <[email protected]>");
MODULE_DESCRIPTION("Tegra210 MVC ASoC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_mvc.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// tegra210_dmic.c - Tegra210 DMIC driver
//
// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "tegra210_dmic.h"
#include "tegra_cif.h"
static const struct reg_default tegra210_dmic_reg_defaults[] = {
{ TEGRA210_DMIC_TX_INT_MASK, 0x00000001 },
{ TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700 },
{ TEGRA210_DMIC_CG, 0x1 },
{ TEGRA210_DMIC_CTRL, 0x00000301 },
/* Below enables all filters - DCR, LP and SC */
{ TEGRA210_DMIC_DBG_CTRL, 0xe },
/* Below as per latest POR value */
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0x0 },
/* LP filter is configured for pass through and used to apply gain */
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x0 },
};
static int __maybe_unused tegra210_dmic_runtime_suspend(struct device *dev)
{
struct tegra210_dmic *dmic = dev_get_drvdata(dev);
regcache_cache_only(dmic->regmap, true);
regcache_mark_dirty(dmic->regmap);
clk_disable_unprepare(dmic->clk_dmic);
return 0;
}
static int __maybe_unused tegra210_dmic_runtime_resume(struct device *dev)
{
struct tegra210_dmic *dmic = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(dmic->clk_dmic);
if (err) {
dev_err(dev, "failed to enable DMIC clock, err: %d\n", err);
return err;
}
regcache_cache_only(dmic->regmap, false);
regcache_sync(dmic->regmap);
return 0;
}
static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai);
unsigned int srate, clk_rate, channels;
struct tegra_cif_conf cif_conf;
unsigned long long gain_q23 = DEFAULT_GAIN_Q23;
int err;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params);
cif_conf.audio_ch = channels;
switch (dmic->ch_select) {
case DMIC_CH_SELECT_LEFT:
case DMIC_CH_SELECT_RIGHT:
cif_conf.client_ch = 1;
break;
case DMIC_CH_SELECT_STEREO:
cif_conf.client_ch = 2;
break;
default:
dev_err(dai->dev, "invalid DMIC client channels\n");
return -EINVAL;
}
srate = params_rate(params);
/*
* DMIC clock rate is a multiple of 'Over Sampling Ratio' and
* 'Sample Rate'. The supported OSR values are 64, 128 and 256.
*/
clk_rate = (DMIC_OSR_FACTOR << dmic->osr_val) * srate;
err = clk_set_rate(dmic->clk_dmic, clk_rate);
if (err) {
dev_err(dai->dev, "can't set DMIC clock rate %u, err: %d\n",
clk_rate, err);
return err;
}
regmap_update_bits(dmic->regmap,
/* Reg */
TEGRA210_DMIC_CTRL,
/* Mask */
TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK |
TEGRA210_DMIC_CTRL_OSR_MASK |
TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK,
/* Value */
(dmic->lrsel << LRSEL_POL_SHIFT) |
(dmic->osr_val << OSR_SHIFT) |
((dmic->ch_select + 1) << CH_SEL_SHIFT));
/*
* Use LP filter gain register to apply boost.
* Boost Gain Volume control has 100x factor.
*/
if (dmic->boost_gain)
gain_q23 = div_u64(gain_q23 * dmic->boost_gain, 100);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_FILTER_GAIN,
(unsigned int)gain_q23);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
break;
default:
dev_err(dai->dev, "unsupported format!\n");
return -EOPNOTSUPP;
}
cif_conf.client_bits = TEGRA_ACIF_BITS_24;
cif_conf.mono_conv = dmic->mono_to_stereo;
cif_conf.stereo_conv = dmic->stereo_to_mono;
tegra_set_cif(dmic->regmap, TEGRA210_DMIC_TX_CIF_CTRL, &cif_conf);
return 0;
}
static int tegra210_dmic_get_boost_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
ucontrol->value.integer.value[0] = dmic->boost_gain;
return 0;
}
static int tegra210_dmic_put_boost_gain(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
int value = ucontrol->value.integer.value[0];
if (value == dmic->boost_gain)
return 0;
dmic->boost_gain = value;
return 1;
}
static int tegra210_dmic_get_ch_select(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = dmic->ch_select;
return 0;
}
static int tegra210_dmic_put_ch_select(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dmic->ch_select)
return 0;
dmic->ch_select = value;
return 1;
}
static int tegra210_dmic_get_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = dmic->mono_to_stereo;
return 0;
}
static int tegra210_dmic_put_mono_to_stereo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dmic->mono_to_stereo)
return 0;
dmic->mono_to_stereo = value;
return 1;
}
static int tegra210_dmic_get_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = dmic->stereo_to_mono;
return 0;
}
static int tegra210_dmic_put_stereo_to_mono(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dmic->stereo_to_mono)
return 0;
dmic->stereo_to_mono = value;
return 1;
}
static int tegra210_dmic_get_osr_val(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = dmic->osr_val;
return 0;
}
static int tegra210_dmic_put_osr_val(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dmic->osr_val)
return 0;
dmic->osr_val = value;
return 1;
}
static int tegra210_dmic_get_pol_sel(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = dmic->lrsel;
return 0;
}
static int tegra210_dmic_put_pol_sel(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
unsigned int value = ucontrol->value.enumerated.item[0];
if (value == dmic->lrsel)
return 0;
dmic->lrsel = value;
return 1;
}
static const struct snd_soc_dai_ops tegra210_dmic_dai_ops = {
.hw_params = tegra210_dmic_hw_params,
};
static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
{
.name = "DMIC-CIF",
.capture = {
.stream_name = "CIF-Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
{
.name = "DMIC-DAP",
.capture = {
.stream_name = "DAP-Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &tegra210_dmic_dai_ops,
.symmetric_rate = 1,
},
};
static const struct snd_soc_dapm_widget tegra210_dmic_widgets[] = {
SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_DMIC_ENABLE, 0, 0),
SND_SOC_DAPM_MIC("MIC", NULL),
};
static const struct snd_soc_dapm_route tegra210_dmic_routes[] = {
{ "XBAR-RX", NULL, "XBAR-Capture" },
{ "XBAR-Capture", NULL, "CIF-Capture" },
{ "CIF-Capture", NULL, "TX" },
{ "TX", NULL, "DAP-Capture" },
{ "DAP-Capture", NULL, "MIC" },
};
static const char * const tegra210_dmic_ch_select[] = {
"Left", "Right", "Stereo",
};
static const struct soc_enum tegra210_dmic_ch_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_ch_select),
tegra210_dmic_ch_select);
static const char * const tegra210_dmic_mono_conv_text[] = {
"Zero", "Copy",
};
static const char * const tegra210_dmic_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const struct soc_enum tegra210_dmic_mono_conv_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_mono_conv_text),
tegra210_dmic_mono_conv_text);
static const struct soc_enum tegra210_dmic_stereo_conv_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_stereo_conv_text),
tegra210_dmic_stereo_conv_text);
static const char * const tegra210_dmic_osr_text[] = {
"OSR_64", "OSR_128", "OSR_256",
};
static const struct soc_enum tegra210_dmic_osr_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_osr_text),
tegra210_dmic_osr_text);
static const char * const tegra210_dmic_lrsel_text[] = {
"Left", "Right",
};
static const struct soc_enum tegra210_dmic_lrsel_enum =
SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_lrsel_text),
tegra210_dmic_lrsel_text);
static const struct snd_kcontrol_new tegra210_dmic_controls[] = {
SOC_SINGLE_EXT("Boost Gain Volume", 0, 0, MAX_BOOST_GAIN, 0,
tegra210_dmic_get_boost_gain,
tegra210_dmic_put_boost_gain),
SOC_ENUM_EXT("Channel Select", tegra210_dmic_ch_enum,
tegra210_dmic_get_ch_select, tegra210_dmic_put_ch_select),
SOC_ENUM_EXT("Mono To Stereo",
tegra210_dmic_mono_conv_enum,
tegra210_dmic_get_mono_to_stereo,
tegra210_dmic_put_mono_to_stereo),
SOC_ENUM_EXT("Stereo To Mono",
tegra210_dmic_stereo_conv_enum,
tegra210_dmic_get_stereo_to_mono,
tegra210_dmic_put_stereo_to_mono),
SOC_ENUM_EXT("OSR Value", tegra210_dmic_osr_enum,
tegra210_dmic_get_osr_val, tegra210_dmic_put_osr_val),
SOC_ENUM_EXT("LR Polarity Select", tegra210_dmic_lrsel_enum,
tegra210_dmic_get_pol_sel, tegra210_dmic_put_pol_sel),
};
static const struct snd_soc_component_driver tegra210_dmic_compnt = {
.dapm_widgets = tegra210_dmic_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_dmic_widgets),
.dapm_routes = tegra210_dmic_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_dmic_routes),
.controls = tegra210_dmic_controls,
.num_controls = ARRAY_SIZE(tegra210_dmic_controls),
};
static bool tegra210_dmic_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_DMIC_TX_INT_MASK ... TEGRA210_DMIC_TX_CIF_CTRL:
case TEGRA210_DMIC_ENABLE ... TEGRA210_DMIC_CG:
case TEGRA210_DMIC_CTRL:
case TEGRA210_DMIC_DBG_CTRL:
case TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 ... TEGRA210_DMIC_LP_BIQUAD_1_COEF_4:
return true;
default:
return false;
}
}
static bool tegra210_dmic_rd_reg(struct device *dev, unsigned int reg)
{
if (tegra210_dmic_wr_reg(dev, reg))
return true;
switch (reg) {
case TEGRA210_DMIC_TX_STATUS:
case TEGRA210_DMIC_TX_INT_STATUS:
case TEGRA210_DMIC_STATUS:
case TEGRA210_DMIC_INT_STATUS:
return true;
default:
return false;
}
}
static bool tegra210_dmic_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA210_DMIC_TX_STATUS:
case TEGRA210_DMIC_TX_INT_STATUS:
case TEGRA210_DMIC_TX_INT_SET:
case TEGRA210_DMIC_SOFT_RESET:
case TEGRA210_DMIC_STATUS:
case TEGRA210_DMIC_INT_STATUS:
return true;
default:
return false;
}
}
static const struct regmap_config tegra210_dmic_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA210_DMIC_LP_BIQUAD_1_COEF_4,
.writeable_reg = tegra210_dmic_wr_reg,
.readable_reg = tegra210_dmic_rd_reg,
.volatile_reg = tegra210_dmic_volatile_reg,
.reg_defaults = tegra210_dmic_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_dmic_reg_defaults),
.cache_type = REGCACHE_FLAT,
};
static int tegra210_dmic_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tegra210_dmic *dmic;
void __iomem *regs;
int err;
dmic = devm_kzalloc(dev, sizeof(*dmic), GFP_KERNEL);
if (!dmic)
return -ENOMEM;
dmic->osr_val = DMIC_OSR_64;
dmic->ch_select = DMIC_CH_SELECT_STEREO;
dmic->lrsel = DMIC_LRSEL_LEFT;
dmic->boost_gain = 0;
dmic->stereo_to_mono = 0; /* "CH0" */
dev_set_drvdata(dev, dmic);
dmic->clk_dmic = devm_clk_get(dev, "dmic");
if (IS_ERR(dmic->clk_dmic)) {
dev_err(dev, "can't retrieve DMIC clock\n");
return PTR_ERR(dmic->clk_dmic);
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
dmic->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_dmic_regmap_config);
if (IS_ERR(dmic->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(dmic->regmap);
}
regcache_cache_only(dmic->regmap, true);
err = devm_snd_soc_register_component(dev, &tegra210_dmic_compnt,
tegra210_dmic_dais,
ARRAY_SIZE(tegra210_dmic_dais));
if (err) {
dev_err(dev, "can't register DMIC component, err: %d\n", err);
return err;
}
pm_runtime_enable(dev);
return 0;
}
static void tegra210_dmic_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct dev_pm_ops tegra210_dmic_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_dmic_runtime_suspend,
tegra210_dmic_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct of_device_id tegra210_dmic_of_match[] = {
{ .compatible = "nvidia,tegra210-dmic" },
{},
};
MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match);
static struct platform_driver tegra210_dmic_driver = {
.driver = {
.name = "tegra210-dmic",
.of_match_table = tegra210_dmic_of_match,
.pm = &tegra210_dmic_pm_ops,
},
.probe = tegra210_dmic_probe,
.remove_new = tegra210_dmic_remove,
};
module_platform_driver(tegra210_dmic_driver)
MODULE_AUTHOR("Rahul Mittal <[email protected]>");
MODULE_DESCRIPTION("Tegra210 ASoC DMIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/tegra/tegra210_dmic.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra_wm8903.c - Tegra machine ASoC driver for boards using WM8903 codec.
*
* Author: Stephen Warren <[email protected]>
* Copyright (C) 2010-2012 - NVIDIA, Inc.
*
* Based on code copyright/by:
*
* (c) 2009, 2010 Nvidia Graphics Pvt. Ltd.
*
* Copyright 2007 Wolfson Microelectronics PLC.
* Author: Graeme Gregory
* [email protected] or [email protected]
*/
#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include "../codecs/wm8903.h"
#include "tegra_asoc_machine.h"
static struct snd_soc_jack_pin tegra_wm8903_mic_jack_pins[] = {
{ .pin = "Mic Jack", .mask = SND_JACK_MICROPHONE },
};
static unsigned int tegra_wm8903_mclk_rate(unsigned int srate)
{
unsigned int mclk;
switch (srate) {
case 64000:
case 88200:
case 96000:
mclk = 128 * srate;
break;
default:
mclk = 256 * srate;
break;
}
/* FIXME: Codec only requires >= 3MHz if OSR==0 */
while (mclk < 6000000)
mclk *= 2;
return mclk;
}
static int tegra_wm8903_init(struct snd_soc_pcm_runtime *rtd)
{
struct tegra_machine *machine = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_card *card = rtd->card;
int err;
/*
* Older version of machine driver was ignoring GPIO polarity,
* forcing it to active-low. This means that all older device-trees
* which set the polarity to active-high are wrong and we need to fix
* them up.
*/
if (machine->asoc->hp_jack_gpio_active_low) {
bool active_low = gpiod_is_active_low(machine->gpiod_hp_det);
machine->hp_jack_gpio->invert = !active_low;
}
err = tegra_asoc_machine_init(rtd);
if (err)
return err;
if (!machine->gpiod_mic_det && machine->asoc->add_mic_jack) {
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
int shrt = 0;
err = snd_soc_card_jack_new_pins(rtd->card, "Mic Jack",
SND_JACK_MICROPHONE,
machine->mic_jack,
tegra_wm8903_mic_jack_pins,
ARRAY_SIZE(tegra_wm8903_mic_jack_pins));
if (err) {
dev_err(rtd->dev, "Mic Jack creation failed: %d\n", err);
return err;
}
if (of_property_read_bool(card->dev->of_node, "nvidia,headset"))
shrt = SND_JACK_MICROPHONE;
wm8903_mic_detect(component, machine->mic_jack,
SND_JACK_MICROPHONE, shrt);
}
snd_soc_dapm_force_enable_pin(&card->dapm, "MICBIAS");
return 0;
}
static int tegra_wm8903_remove(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link = &card->dai_link[0];
struct snd_soc_pcm_runtime *rtd = snd_soc_get_pcm_runtime(card, link);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
wm8903_mic_detect(component, NULL, 0, 0);
return 0;
}
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8903-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tegra_wm8903_dai = {
.name = "WM8903",
.stream_name = "WM8903 PCM",
.init = tegra_wm8903_init,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(hifi),
};
static struct snd_soc_card snd_soc_tegra_wm8903 = {
.components = "codec:wm8903",
.owner = THIS_MODULE,
.dai_link = &tegra_wm8903_dai,
.num_links = 1,
.remove = tegra_wm8903_remove,
.fully_routed = true,
};
/* older device-trees used wrong polarity for the headphones-detection GPIO */
static const struct tegra_asoc_data tegra_wm8903_data_legacy = {
.mclk_rate = tegra_wm8903_mclk_rate,
.card = &snd_soc_tegra_wm8903,
.hp_jack_gpio_active_low = true,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_mic_jack = true,
.add_hp_jack = true,
};
static const struct tegra_asoc_data tegra_wm8903_data = {
.mclk_rate = tegra_wm8903_mclk_rate,
.card = &snd_soc_tegra_wm8903,
.add_common_dapm_widgets = true,
.add_common_controls = true,
.add_common_snd_ops = true,
.add_mic_jack = true,
.add_hp_jack = true,
};
static const struct of_device_id tegra_wm8903_of_match[] = {
{ .compatible = "ad,tegra-audio-plutux", .data = &tegra_wm8903_data_legacy },
{ .compatible = "ad,tegra-audio-wm8903-medcom-wide", .data = &tegra_wm8903_data_legacy },
{ .compatible = "ad,tegra-audio-wm8903-tec", .data = &tegra_wm8903_data_legacy },
{ .compatible = "nvidia,tegra-audio-wm8903-cardhu", .data = &tegra_wm8903_data_legacy },
{ .compatible = "nvidia,tegra-audio-wm8903-harmony", .data = &tegra_wm8903_data_legacy },
{ .compatible = "nvidia,tegra-audio-wm8903-picasso", .data = &tegra_wm8903_data_legacy },
{ .compatible = "nvidia,tegra-audio-wm8903-seaboard", .data = &tegra_wm8903_data_legacy },
{ .compatible = "nvidia,tegra-audio-wm8903-ventana", .data = &tegra_wm8903_data_legacy },
{ .compatible = "nvidia,tegra-audio-wm8903", .data = &tegra_wm8903_data },
{},
};
MODULE_DEVICE_TABLE(of, tegra_wm8903_of_match);
static struct platform_driver tegra_wm8903_driver = {
.driver = {
.name = "tegra-wm8903",
.of_match_table = tegra_wm8903_of_match,
.pm = &snd_soc_pm_ops,
},
.probe = tegra_asoc_machine_probe,
};
module_platform_driver(tegra_wm8903_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Tegra+WM8903 machine ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/tegra/tegra_wm8903.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IMG I2S input controller driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define IMG_I2S_IN_RX_FIFO 0x0
#define IMG_I2S_IN_CTL 0x4
#define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK 0xfffffffc
#define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT 2
#define IMG_I2S_IN_CTL_16PACK_MASK BIT(1)
#define IMG_I2S_IN_CTL_ME_MASK BIT(0)
#define IMG_I2S_IN_CH_CTL 0x4
#define IMG_I2S_IN_CH_CTL_CCDEL_MASK 0x38000
#define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT 15
#define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14)
#define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13)
#define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12)
#define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10)
#define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9)
#define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8)
#define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7)
#define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6)
#define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3)
#define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2)
#define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1)
#define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0)
#define IMG_I2S_IN_CH_STRIDE 0x20
struct img_i2s_in {
void __iomem *base;
struct clk *clk_sys;
struct snd_dmaengine_dai_dma_data dma_data;
struct device *dev;
unsigned int max_i2s_chan;
void __iomem *channel_base;
unsigned int active_channels;
struct snd_soc_dai_driver dai_driver;
u32 suspend_ctl;
u32 *suspend_ch_ctl;
};
static int img_i2s_in_runtime_suspend(struct device *dev)
{
struct img_i2s_in *i2s = dev_get_drvdata(dev);
clk_disable_unprepare(i2s->clk_sys);
return 0;
}
static int img_i2s_in_runtime_resume(struct device *dev)
{
struct img_i2s_in *i2s = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s->clk_sys);
if (ret) {
dev_err(dev, "Unable to enable sys clock\n");
return ret;
}
return 0;
}
static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
{
writel(val, i2s->base + reg);
}
static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
{
return readl(i2s->base + reg);
}
static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
u32 val, u32 reg)
{
writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
}
static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
u32 reg)
{
return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
}
static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
{
u32 reg;
reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
}
static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
{
u32 reg;
reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
}
static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
{
u32 reg;
reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
reg &= ~IMG_I2S_IN_CTL_ME_MASK;
img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
}
static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
{
u32 reg;
reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
reg |= IMG_I2S_IN_CTL_ME_MASK;
img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
}
static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
{
int i;
u32 reg;
for (i = 0; i < i2s->active_channels; i++) {
reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
}
}
static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
img_i2s_in_enable(i2s);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
img_i2s_in_disable(i2s);
break;
default:
return -EINVAL;
}
return 0;
}
static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
unsigned int sample_rate, unsigned int frame_size,
unsigned int *bclk_filter_enable,
unsigned int *bclk_filter_value)
{
unsigned int bclk_freq, cur_freq;
bclk_freq = sample_rate * frame_size;
cur_freq = clk_get_rate(i2s->clk_sys);
if (cur_freq >= bclk_freq * 8) {
*bclk_filter_enable = 1;
*bclk_filter_value = 0;
} else if (cur_freq >= bclk_freq * 7) {
*bclk_filter_enable = 1;
*bclk_filter_value = 1;
} else if (cur_freq >= bclk_freq * 6) {
*bclk_filter_enable = 0;
*bclk_filter_value = 0;
} else {
dev_err(i2s->dev,
"Sys clock rate %u insufficient for sample rate %u\n",
cur_freq, sample_rate);
return -EINVAL;
}
return 0;
}
static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int rate, channels, i2s_channels, frame_size;
unsigned int bclk_filter_enable, bclk_filter_value;
int i, ret = 0;
u32 reg, control_mask, chan_control_mask;
u32 control_set = 0, chan_control_set = 0;
snd_pcm_format_t format;
rate = params_rate(params);
format = params_format(params);
channels = params_channels(params);
i2s_channels = channels / 2;
switch (format) {
case SNDRV_PCM_FORMAT_S32_LE:
frame_size = 64;
chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
break;
case SNDRV_PCM_FORMAT_S24_LE:
frame_size = 64;
chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
break;
case SNDRV_PCM_FORMAT_S16_LE:
frame_size = 32;
control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
break;
default:
return -EINVAL;
}
if ((channels < 2) ||
(channels > (i2s->max_i2s_chan * 2)) ||
(channels % 2))
return -EINVAL;
control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
ret = img_i2s_in_check_rate(i2s, rate, frame_size,
&bclk_filter_enable, &bclk_filter_value);
if (ret < 0)
return ret;
if (bclk_filter_enable)
chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
if (bclk_filter_value)
chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
IMG_I2S_IN_CH_CTL_FEN_MASK |
IMG_I2S_IN_CH_CTL_FMODE_MASK |
IMG_I2S_IN_CH_CTL_SW_MASK |
IMG_I2S_IN_CH_CTL_FW_MASK |
IMG_I2S_IN_CH_CTL_PACKH_MASK;
reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
reg = (reg & ~control_mask) | control_set;
img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
for (i = 0; i < i2s->active_channels; i++)
img_i2s_in_ch_disable(i2s, i);
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
reg = (reg & ~chan_control_mask) | chan_control_set;
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
}
i2s->active_channels = i2s_channels;
img_i2s_in_flush(i2s);
for (i = 0; i < i2s->active_channels; i++)
img_i2s_in_ch_enable(i2s, i);
return 0;
}
static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
int i, ret;
u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
u32 reg;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
case SND_SOC_DAIFMT_IB_NF:
lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
break;
case SND_SOC_DAIFMT_IB_IF:
blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
break;
default:
return -EINVAL;
}
chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
ret = pm_runtime_resume_and_get(i2s->dev);
if (ret < 0)
return ret;
for (i = 0; i < i2s->active_channels; i++)
img_i2s_in_ch_disable(i2s, i);
/*
* BLKP and LRD must be set during separate register writes
*/
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
reg = (reg & ~chan_control_mask) | chan_control_set;
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
}
for (i = 0; i < i2s->active_channels; i++)
img_i2s_in_ch_enable(i2s, i);
pm_runtime_put(i2s->dev);
return 0;
}
static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
{
struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
return 0;
}
static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
.probe = img_i2s_in_dai_probe,
.trigger = img_i2s_in_trigger,
.hw_params = img_i2s_in_hw_params,
.set_fmt = img_i2s_in_set_fmt
};
static const struct snd_soc_component_driver img_i2s_in_component = {
.name = "img-i2s-in",
.legacy_dai_naming = 1,
};
static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
{
unsigned int i2s_channels = params_channels(params) / 2;
struct snd_soc_pcm_runtime *rtd = st->private_data;
struct snd_dmaengine_dai_dma_data *dma_data;
int ret;
dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
ret = snd_hwparams_to_dma_slave_config(st, params, sc);
if (ret)
return ret;
sc->src_addr = dma_data->addr;
sc->src_addr_width = dma_data->addr_width;
sc->src_maxburst = 4 * i2s_channels;
return 0;
}
static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
.prepare_slave_config = img_i2s_in_dma_prepare_slave_config
};
static int img_i2s_in_probe(struct platform_device *pdev)
{
struct img_i2s_in *i2s;
struct resource *res;
void __iomem *base;
int ret, i;
struct reset_control *rst;
unsigned int max_i2s_chan_pow_2;
struct device *dev = &pdev->dev;
i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
platform_set_drvdata(pdev, i2s);
i2s->dev = dev;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
i2s->base = base;
if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
&i2s->max_i2s_chan)) {
dev_err(dev, "No img,i2s-channels property\n");
return -EINVAL;
}
max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
i2s->clk_sys = devm_clk_get(dev, "sys");
if (IS_ERR(i2s->clk_sys))
return dev_err_probe(dev, PTR_ERR(i2s->clk_sys),
"Failed to acquire clock 'sys'\n");
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = img_i2s_in_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_suspend;
i2s->active_channels = 1;
i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
i2s->dma_data.addr_width = 4;
i2s->dai_driver.capture.channels_min = 2;
i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
i2s->dai_driver.ops = &img_i2s_in_dai_ops;
rst = devm_reset_control_get_exclusive(dev, "rst");
if (IS_ERR(rst)) {
if (PTR_ERR(rst) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
pm_runtime_put(&pdev->dev);
goto err_suspend;
}
dev_dbg(dev, "No top level reset found\n");
img_i2s_in_disable(i2s);
for (i = 0; i < i2s->max_i2s_chan; i++)
img_i2s_in_ch_disable(i2s, i);
} else {
reset_control_assert(rst);
reset_control_deassert(rst);
}
img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
for (i = 0; i < i2s->max_i2s_chan; i++)
img_i2s_in_ch_writel(i2s, i,
(4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
IMG_I2S_IN_CH_CTL_JUST_MASK |
IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
pm_runtime_put(&pdev->dev);
i2s->suspend_ch_ctl = devm_kcalloc(dev,
i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
if (!i2s->suspend_ch_ctl) {
ret = -ENOMEM;
goto err_suspend;
}
ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
&i2s->dai_driver, 1);
if (ret)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
if (ret)
goto err_suspend;
return 0;
err_suspend:
if (!pm_runtime_enabled(&pdev->dev))
img_i2s_in_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void img_i2s_in_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
img_i2s_in_runtime_suspend(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int img_i2s_in_suspend(struct device *dev)
{
struct img_i2s_in *i2s = dev_get_drvdata(dev);
int i, ret;
u32 reg;
if (pm_runtime_status_suspended(dev)) {
ret = img_i2s_in_runtime_resume(dev);
if (ret)
return ret;
}
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
i2s->suspend_ch_ctl[i] = reg;
}
i2s->suspend_ctl = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
img_i2s_in_runtime_suspend(dev);
return 0;
}
static int img_i2s_in_resume(struct device *dev)
{
struct img_i2s_in *i2s = dev_get_drvdata(dev);
int i, ret;
u32 reg;
ret = img_i2s_in_runtime_resume(dev);
if (ret)
return ret;
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = i2s->suspend_ch_ctl[i];
img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
}
img_i2s_in_writel(i2s, i2s->suspend_ctl, IMG_I2S_IN_CTL);
if (pm_runtime_status_suspended(dev))
img_i2s_in_runtime_suspend(dev);
return 0;
}
#endif
static const struct of_device_id img_i2s_in_of_match[] = {
{ .compatible = "img,i2s-in" },
{}
};
MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
static const struct dev_pm_ops img_i2s_in_pm_ops = {
SET_RUNTIME_PM_OPS(img_i2s_in_runtime_suspend,
img_i2s_in_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(img_i2s_in_suspend, img_i2s_in_resume)
};
static struct platform_driver img_i2s_in_driver = {
.driver = {
.name = "img-i2s-in",
.of_match_table = img_i2s_in_of_match,
.pm = &img_i2s_in_pm_ops
},
.probe = img_i2s_in_probe,
.remove_new = img_i2s_in_dev_remove
};
module_platform_driver(img_i2s_in_driver);
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_DESCRIPTION("IMG I2S Input Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/img/img-i2s-in.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IMG SPDIF input controller driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define IMG_SPDIF_IN_RX_FIFO_OFFSET 0
#define IMG_SPDIF_IN_CTL 0x4
#define IMG_SPDIF_IN_CTL_LOCKLO_MASK 0xff
#define IMG_SPDIF_IN_CTL_LOCKLO_SHIFT 0
#define IMG_SPDIF_IN_CTL_LOCKHI_MASK 0xff00
#define IMG_SPDIF_IN_CTL_LOCKHI_SHIFT 8
#define IMG_SPDIF_IN_CTL_TRK_MASK 0xff0000
#define IMG_SPDIF_IN_CTL_TRK_SHIFT 16
#define IMG_SPDIF_IN_CTL_SRD_MASK 0x70000000
#define IMG_SPDIF_IN_CTL_SRD_SHIFT 28
#define IMG_SPDIF_IN_CTL_SRT_MASK BIT(31)
#define IMG_SPDIF_IN_STATUS 0x8
#define IMG_SPDIF_IN_STATUS_SAM_MASK 0x7000
#define IMG_SPDIF_IN_STATUS_SAM_SHIFT 12
#define IMG_SPDIF_IN_STATUS_LOCK_MASK BIT(15)
#define IMG_SPDIF_IN_STATUS_LOCK_SHIFT 15
#define IMG_SPDIF_IN_CLKGEN 0x1c
#define IMG_SPDIF_IN_CLKGEN_NOM_MASK 0x3ff
#define IMG_SPDIF_IN_CLKGEN_NOM_SHIFT 0
#define IMG_SPDIF_IN_CLKGEN_HLD_MASK 0x3ff0000
#define IMG_SPDIF_IN_CLKGEN_HLD_SHIFT 16
#define IMG_SPDIF_IN_CSL 0x20
#define IMG_SPDIF_IN_CSH 0x24
#define IMG_SPDIF_IN_CSH_MASK 0xff
#define IMG_SPDIF_IN_CSH_SHIFT 0
#define IMG_SPDIF_IN_SOFT_RESET 0x28
#define IMG_SPDIF_IN_SOFT_RESET_MASK BIT(0)
#define IMG_SPDIF_IN_ACLKGEN_START 0x2c
#define IMG_SPDIF_IN_ACLKGEN_NOM_MASK 0x3ff
#define IMG_SPDIF_IN_ACLKGEN_NOM_SHIFT 0
#define IMG_SPDIF_IN_ACLKGEN_HLD_MASK 0xffc00
#define IMG_SPDIF_IN_ACLKGEN_HLD_SHIFT 10
#define IMG_SPDIF_IN_ACLKGEN_TRK_MASK 0xff00000
#define IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT 20
#define IMG_SPDIF_IN_NUM_ACLKGEN 4
struct img_spdif_in {
spinlock_t lock;
void __iomem *base;
struct clk *clk_sys;
struct snd_dmaengine_dai_dma_data dma_data;
struct device *dev;
unsigned int trk;
bool multi_freq;
int lock_acquire;
int lock_release;
unsigned int single_freq;
unsigned int multi_freqs[IMG_SPDIF_IN_NUM_ACLKGEN];
bool active;
u32 suspend_clkgen;
u32 suspend_ctl;
/* Write-only registers */
unsigned int aclkgen_regs[IMG_SPDIF_IN_NUM_ACLKGEN];
};
static int img_spdif_in_runtime_suspend(struct device *dev)
{
struct img_spdif_in *spdif = dev_get_drvdata(dev);
clk_disable_unprepare(spdif->clk_sys);
return 0;
}
static int img_spdif_in_runtime_resume(struct device *dev)
{
struct img_spdif_in *spdif = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(spdif->clk_sys);
if (ret) {
dev_err(dev, "Unable to enable sys clock\n");
return ret;
}
return 0;
}
static inline void img_spdif_in_writel(struct img_spdif_in *spdif,
u32 val, u32 reg)
{
writel(val, spdif->base + reg);
}
static inline u32 img_spdif_in_readl(struct img_spdif_in *spdif, u32 reg)
{
return readl(spdif->base + reg);
}
static inline void img_spdif_in_aclkgen_writel(struct img_spdif_in *spdif,
u32 index)
{
img_spdif_in_writel(spdif, spdif->aclkgen_regs[index],
IMG_SPDIF_IN_ACLKGEN_START + (index * 0x4));
}
static int img_spdif_in_check_max_rate(struct img_spdif_in *spdif,
unsigned int sample_rate, unsigned long *actual_freq)
{
unsigned long min_freq, freq_t;
/* Clock rate must be at least 24x the bit rate */
min_freq = sample_rate * 2 * 32 * 24;
freq_t = clk_get_rate(spdif->clk_sys);
if (freq_t < min_freq)
return -EINVAL;
*actual_freq = freq_t;
return 0;
}
static int img_spdif_in_do_clkgen_calc(unsigned int rate, unsigned int *pnom,
unsigned int *phld, unsigned long clk_rate)
{
unsigned int ori, nom, hld;
/*
* Calculate oversampling ratio, nominal phase increment and hold
* increment for the given rate / frequency
*/
if (!rate)
return -EINVAL;
ori = clk_rate / (rate * 64);
if (!ori)
return -EINVAL;
nom = (4096 / ori) + 1;
do
hld = 4096 - (--nom * (ori - 1));
while (hld < 120);
*pnom = nom;
*phld = hld;
return 0;
}
static int img_spdif_in_do_clkgen_single(struct img_spdif_in *spdif,
unsigned int rate)
{
unsigned int nom, hld;
unsigned long flags, clk_rate;
int ret = 0;
u32 reg;
ret = img_spdif_in_check_max_rate(spdif, rate, &clk_rate);
if (ret)
return ret;
ret = img_spdif_in_do_clkgen_calc(rate, &nom, &hld, clk_rate);
if (ret)
return ret;
reg = (nom << IMG_SPDIF_IN_CLKGEN_NOM_SHIFT) &
IMG_SPDIF_IN_CLKGEN_NOM_MASK;
reg |= (hld << IMG_SPDIF_IN_CLKGEN_HLD_SHIFT) &
IMG_SPDIF_IN_CLKGEN_HLD_MASK;
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->active) {
spin_unlock_irqrestore(&spdif->lock, flags);
return -EBUSY;
}
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CLKGEN);
spdif->single_freq = rate;
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_do_clkgen_multi(struct img_spdif_in *spdif,
unsigned int multi_freqs[])
{
unsigned int nom, hld, rate, max_rate = 0;
unsigned long flags, clk_rate;
int i, ret = 0;
u32 reg, trk_reg, temp_regs[IMG_SPDIF_IN_NUM_ACLKGEN];
for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++)
if (multi_freqs[i] > max_rate)
max_rate = multi_freqs[i];
ret = img_spdif_in_check_max_rate(spdif, max_rate, &clk_rate);
if (ret)
return ret;
for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++) {
rate = multi_freqs[i];
ret = img_spdif_in_do_clkgen_calc(rate, &nom, &hld, clk_rate);
if (ret)
return ret;
reg = (nom << IMG_SPDIF_IN_ACLKGEN_NOM_SHIFT) &
IMG_SPDIF_IN_ACLKGEN_NOM_MASK;
reg |= (hld << IMG_SPDIF_IN_ACLKGEN_HLD_SHIFT) &
IMG_SPDIF_IN_ACLKGEN_HLD_MASK;
temp_regs[i] = reg;
}
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->active) {
spin_unlock_irqrestore(&spdif->lock, flags);
return -EBUSY;
}
trk_reg = spdif->trk << IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT;
for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++) {
spdif->aclkgen_regs[i] = temp_regs[i] | trk_reg;
img_spdif_in_aclkgen_writel(spdif, i);
}
spdif->multi_freq = true;
spdif->multi_freqs[0] = multi_freqs[0];
spdif->multi_freqs[1] = multi_freqs[1];
spdif->multi_freqs[2] = multi_freqs[2];
spdif->multi_freqs[3] = multi_freqs[3];
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_iec958_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int img_spdif_in_get_status_mask(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.iec958.status[0] = 0xff;
ucontrol->value.iec958.status[1] = 0xff;
ucontrol->value.iec958.status[2] = 0xff;
ucontrol->value.iec958.status[3] = 0xff;
ucontrol->value.iec958.status[4] = 0xff;
return 0;
}
static int img_spdif_in_get_status(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
u32 reg;
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CSL);
ucontrol->value.iec958.status[0] = reg & 0xff;
ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CSH);
ucontrol->value.iec958.status[4] = (reg & IMG_SPDIF_IN_CSH_MASK)
>> IMG_SPDIF_IN_CSH_SHIFT;
return 0;
}
static int img_spdif_in_info_multi_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = IMG_SPDIF_IN_NUM_ACLKGEN;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = LONG_MAX;
return 0;
}
static int img_spdif_in_get_multi_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->multi_freq) {
ucontrol->value.integer.value[0] = spdif->multi_freqs[0];
ucontrol->value.integer.value[1] = spdif->multi_freqs[1];
ucontrol->value.integer.value[2] = spdif->multi_freqs[2];
ucontrol->value.integer.value[3] = spdif->multi_freqs[3];
} else {
ucontrol->value.integer.value[0] = 0;
ucontrol->value.integer.value[1] = 0;
ucontrol->value.integer.value[2] = 0;
ucontrol->value.integer.value[3] = 0;
}
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_set_multi_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
unsigned int multi_freqs[IMG_SPDIF_IN_NUM_ACLKGEN];
bool multi_freq;
unsigned long flags;
if ((ucontrol->value.integer.value[0] == 0) &&
(ucontrol->value.integer.value[1] == 0) &&
(ucontrol->value.integer.value[2] == 0) &&
(ucontrol->value.integer.value[3] == 0)) {
multi_freq = false;
} else {
multi_freqs[0] = ucontrol->value.integer.value[0];
multi_freqs[1] = ucontrol->value.integer.value[1];
multi_freqs[2] = ucontrol->value.integer.value[2];
multi_freqs[3] = ucontrol->value.integer.value[3];
multi_freq = true;
}
if (multi_freq)
return img_spdif_in_do_clkgen_multi(spdif, multi_freqs);
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->active) {
spin_unlock_irqrestore(&spdif->lock, flags);
return -EBUSY;
}
spdif->multi_freq = false;
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_info_lock_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = LONG_MAX;
return 0;
}
static int img_spdif_in_get_lock_freq(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *uc)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
u32 reg;
int i;
unsigned long flags;
spin_lock_irqsave(&spdif->lock, flags);
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_STATUS);
if (reg & IMG_SPDIF_IN_STATUS_LOCK_MASK) {
if (spdif->multi_freq) {
i = ((reg & IMG_SPDIF_IN_STATUS_SAM_MASK) >>
IMG_SPDIF_IN_STATUS_SAM_SHIFT) - 1;
uc->value.integer.value[0] = spdif->multi_freqs[i];
} else {
uc->value.integer.value[0] = spdif->single_freq;
}
} else {
uc->value.integer.value[0] = 0;
}
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_info_trk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 255;
return 0;
}
static int img_spdif_in_get_trk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
ucontrol->value.integer.value[0] = spdif->trk;
return 0;
}
static int img_spdif_in_set_trk(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
int i;
u32 reg;
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->active) {
spin_unlock_irqrestore(&spdif->lock, flags);
return -EBUSY;
}
spdif->trk = ucontrol->value.integer.value[0];
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
reg &= ~IMG_SPDIF_IN_CTL_TRK_MASK;
reg |= spdif->trk << IMG_SPDIF_IN_CTL_TRK_SHIFT;
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++) {
spdif->aclkgen_regs[i] = (spdif->aclkgen_regs[i] &
~IMG_SPDIF_IN_ACLKGEN_TRK_MASK) |
(spdif->trk << IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT);
img_spdif_in_aclkgen_writel(spdif, i);
}
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_info_lock(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = -128;
uinfo->value.integer.max = 127;
return 0;
}
static int img_spdif_in_get_lock_acquire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
ucontrol->value.integer.value[0] = spdif->lock_acquire;
return 0;
}
static int img_spdif_in_set_lock_acquire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
u32 reg;
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->active) {
spin_unlock_irqrestore(&spdif->lock, flags);
return -EBUSY;
}
spdif->lock_acquire = ucontrol->value.integer.value[0];
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
reg &= ~IMG_SPDIF_IN_CTL_LOCKHI_MASK;
reg |= (spdif->lock_acquire << IMG_SPDIF_IN_CTL_LOCKHI_SHIFT) &
IMG_SPDIF_IN_CTL_LOCKHI_MASK;
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_in_get_lock_release(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
ucontrol->value.integer.value[0] = spdif->lock_release;
return 0;
}
static int img_spdif_in_set_lock_release(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
u32 reg;
spin_lock_irqsave(&spdif->lock, flags);
if (spdif->active) {
spin_unlock_irqrestore(&spdif->lock, flags);
return -EBUSY;
}
spdif->lock_release = ucontrol->value.integer.value[0];
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
reg &= ~IMG_SPDIF_IN_CTL_LOCKLO_MASK;
reg |= (spdif->lock_release << IMG_SPDIF_IN_CTL_LOCKLO_SHIFT) &
IMG_SPDIF_IN_CTL_LOCKLO_MASK;
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static struct snd_kcontrol_new img_spdif_in_controls[] = {
{
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
.info = img_spdif_in_iec958_info,
.get = img_spdif_in_get_status_mask
},
{
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
.info = img_spdif_in_iec958_info,
.get = img_spdif_in_get_status
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "SPDIF In Multi Frequency Acquire",
.info = img_spdif_in_info_multi_freq,
.get = img_spdif_in_get_multi_freq,
.put = img_spdif_in_set_multi_freq
},
{
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "SPDIF In Lock Frequency",
.info = img_spdif_in_info_lock_freq,
.get = img_spdif_in_get_lock_freq
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "SPDIF In Lock TRK",
.info = img_spdif_in_info_trk,
.get = img_spdif_in_get_trk,
.put = img_spdif_in_set_trk
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "SPDIF In Lock Acquire Threshold",
.info = img_spdif_in_info_lock,
.get = img_spdif_in_get_lock_acquire,
.put = img_spdif_in_set_lock_acquire
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "SPDIF In Lock Release Threshold",
.info = img_spdif_in_info_lock,
.get = img_spdif_in_get_lock_release,
.put = img_spdif_in_set_lock_release
}
};
static int img_spdif_in_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
unsigned long flags;
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(dai);
int ret = 0;
u32 reg;
spin_lock_irqsave(&spdif->lock, flags);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
if (spdif->multi_freq)
reg &= ~IMG_SPDIF_IN_CTL_SRD_MASK;
else
reg |= (1UL << IMG_SPDIF_IN_CTL_SRD_SHIFT);
reg |= IMG_SPDIF_IN_CTL_SRT_MASK;
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
spdif->active = true;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
reg &= ~IMG_SPDIF_IN_CTL_SRT_MASK;
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
spdif->active = false;
break;
default:
ret = -EINVAL;
}
spin_unlock_irqrestore(&spdif->lock, flags);
return ret;
}
static int img_spdif_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(dai);
unsigned int rate, channels;
snd_pcm_format_t format;
rate = params_rate(params);
channels = params_channels(params);
format = params_format(params);
if (format != SNDRV_PCM_FORMAT_S32_LE)
return -EINVAL;
if (channels != 2)
return -EINVAL;
return img_spdif_in_do_clkgen_single(spdif, rate);
}
static int img_spdif_in_dai_probe(struct snd_soc_dai *dai)
{
struct img_spdif_in *spdif = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, NULL, &spdif->dma_data);
snd_soc_add_dai_controls(dai, img_spdif_in_controls,
ARRAY_SIZE(img_spdif_in_controls));
return 0;
}
static const struct snd_soc_dai_ops img_spdif_in_dai_ops = {
.probe = img_spdif_in_dai_probe,
.trigger = img_spdif_in_trigger,
.hw_params = img_spdif_in_hw_params
};
static struct snd_soc_dai_driver img_spdif_in_dai = {
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE
},
.ops = &img_spdif_in_dai_ops
};
static const struct snd_soc_component_driver img_spdif_in_component = {
.name = "img-spdif-in",
.legacy_dai_naming = 1,
};
static int img_spdif_in_probe(struct platform_device *pdev)
{
struct img_spdif_in *spdif;
struct resource *res;
void __iomem *base;
int ret;
struct reset_control *rst;
u32 reg;
struct device *dev = &pdev->dev;
spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
if (!spdif)
return -ENOMEM;
platform_set_drvdata(pdev, spdif);
spdif->dev = &pdev->dev;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
spdif->base = base;
spdif->clk_sys = devm_clk_get(dev, "sys");
if (IS_ERR(spdif->clk_sys))
return dev_err_probe(dev, PTR_ERR(spdif->clk_sys),
"Failed to acquire clock 'sys'\n");
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = img_spdif_in_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_suspend;
rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
if (IS_ERR(rst)) {
if (PTR_ERR(rst) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto err_pm_put;
}
dev_dbg(dev, "No top level reset found\n");
img_spdif_in_writel(spdif, IMG_SPDIF_IN_SOFT_RESET_MASK,
IMG_SPDIF_IN_SOFT_RESET);
img_spdif_in_writel(spdif, 0, IMG_SPDIF_IN_SOFT_RESET);
} else {
reset_control_assert(rst);
reset_control_deassert(rst);
}
spin_lock_init(&spdif->lock);
spdif->dma_data.addr = res->start + IMG_SPDIF_IN_RX_FIFO_OFFSET;
spdif->dma_data.addr_width = 4;
spdif->dma_data.maxburst = 4;
spdif->trk = 0x80;
spdif->lock_acquire = 4;
spdif->lock_release = -128;
reg = (spdif->lock_acquire << IMG_SPDIF_IN_CTL_LOCKHI_SHIFT) &
IMG_SPDIF_IN_CTL_LOCKHI_MASK;
reg |= (spdif->lock_release << IMG_SPDIF_IN_CTL_LOCKLO_SHIFT) &
IMG_SPDIF_IN_CTL_LOCKLO_MASK;
reg |= (spdif->trk << IMG_SPDIF_IN_CTL_TRK_SHIFT) &
IMG_SPDIF_IN_CTL_TRK_MASK;
img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL);
pm_runtime_put(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&img_spdif_in_component, &img_spdif_in_dai, 1);
if (ret)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_suspend;
return 0;
err_pm_put:
pm_runtime_put(&pdev->dev);
err_suspend:
if (!pm_runtime_enabled(&pdev->dev))
img_spdif_in_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void img_spdif_in_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
img_spdif_in_runtime_suspend(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int img_spdif_in_suspend(struct device *dev)
{
struct img_spdif_in *spdif = dev_get_drvdata(dev);
int ret;
if (pm_runtime_status_suspended(dev)) {
ret = img_spdif_in_runtime_resume(dev);
if (ret)
return ret;
}
spdif->suspend_clkgen = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CLKGEN);
spdif->suspend_ctl = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL);
img_spdif_in_runtime_suspend(dev);
return 0;
}
static int img_spdif_in_resume(struct device *dev)
{
struct img_spdif_in *spdif = dev_get_drvdata(dev);
int i, ret;
ret = img_spdif_in_runtime_resume(dev);
if (ret)
return ret;
for (i = 0; i < IMG_SPDIF_IN_NUM_ACLKGEN; i++)
img_spdif_in_aclkgen_writel(spdif, i);
img_spdif_in_writel(spdif, spdif->suspend_clkgen, IMG_SPDIF_IN_CLKGEN);
img_spdif_in_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_IN_CTL);
if (pm_runtime_status_suspended(dev))
img_spdif_in_runtime_suspend(dev);
return 0;
}
#endif
static const struct of_device_id img_spdif_in_of_match[] = {
{ .compatible = "img,spdif-in" },
{}
};
MODULE_DEVICE_TABLE(of, img_spdif_in_of_match);
static const struct dev_pm_ops img_spdif_in_pm_ops = {
SET_RUNTIME_PM_OPS(img_spdif_in_runtime_suspend,
img_spdif_in_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(img_spdif_in_suspend, img_spdif_in_resume)
};
static struct platform_driver img_spdif_in_driver = {
.driver = {
.name = "img-spdif-in",
.of_match_table = img_spdif_in_of_match,
.pm = &img_spdif_in_pm_ops
},
.probe = img_spdif_in_probe,
.remove_new = img_spdif_in_dev_remove
};
module_platform_driver(img_spdif_in_driver);
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_DESCRIPTION("IMG SPDIF Input driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/img/img-spdif-in.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IMG SPDIF output controller driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define IMG_SPDIF_OUT_TX_FIFO 0x0
#define IMG_SPDIF_OUT_CTL 0x4
#define IMG_SPDIF_OUT_CTL_FS_MASK BIT(4)
#define IMG_SPDIF_OUT_CTL_CLK_MASK BIT(2)
#define IMG_SPDIF_OUT_CTL_SRT_MASK BIT(0)
#define IMG_SPDIF_OUT_CSL 0x14
#define IMG_SPDIF_OUT_CSH_UV 0x18
#define IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT 0
#define IMG_SPDIF_OUT_CSH_UV_CSH_MASK 0xff
struct img_spdif_out {
spinlock_t lock;
void __iomem *base;
struct clk *clk_sys;
struct clk *clk_ref;
struct snd_dmaengine_dai_dma_data dma_data;
struct device *dev;
struct reset_control *rst;
u32 suspend_ctl;
u32 suspend_csl;
u32 suspend_csh;
};
static int img_spdif_out_runtime_suspend(struct device *dev)
{
struct img_spdif_out *spdif = dev_get_drvdata(dev);
clk_disable_unprepare(spdif->clk_ref);
clk_disable_unprepare(spdif->clk_sys);
return 0;
}
static int img_spdif_out_runtime_resume(struct device *dev)
{
struct img_spdif_out *spdif = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(spdif->clk_sys);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(spdif->clk_ref);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
clk_disable_unprepare(spdif->clk_sys);
return ret;
}
return 0;
}
static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val,
u32 reg)
{
writel(val, spdif->base + reg);
}
static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg)
{
return readl(spdif->base + reg);
}
static void img_spdif_out_reset(struct img_spdif_out *spdif)
{
u32 ctl, status_low, status_high;
ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL) &
~IMG_SPDIF_OUT_CTL_SRT_MASK;
status_low = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
status_high = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
reset_control_assert(spdif->rst);
reset_control_deassert(spdif->rst);
img_spdif_out_writel(spdif, ctl, IMG_SPDIF_OUT_CTL);
img_spdif_out_writel(spdif, status_low, IMG_SPDIF_OUT_CSL);
img_spdif_out_writel(spdif, status_high, IMG_SPDIF_OUT_CSH_UV);
}
static int img_spdif_out_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int img_spdif_out_get_status_mask(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.iec958.status[0] = 0xff;
ucontrol->value.iec958.status[1] = 0xff;
ucontrol->value.iec958.status[2] = 0xff;
ucontrol->value.iec958.status[3] = 0xff;
ucontrol->value.iec958.status[4] = 0xff;
return 0;
}
static int img_spdif_out_get_status(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
u32 reg;
unsigned long flags;
spin_lock_irqsave(&spdif->lock, flags);
reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
ucontrol->value.iec958.status[0] = reg & 0xff;
ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
ucontrol->value.iec958.status[4] =
(reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >>
IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static int img_spdif_out_set_status(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
u32 reg;
unsigned long flags;
reg = ((u32)ucontrol->value.iec958.status[3] << 24);
reg |= ((u32)ucontrol->value.iec958.status[2] << 16);
reg |= ((u32)ucontrol->value.iec958.status[1] << 8);
reg |= (u32)ucontrol->value.iec958.status[0];
spin_lock_irqsave(&spdif->lock, flags);
img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL);
reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK;
reg |= (u32)ucontrol->value.iec958.status[4] <<
IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV);
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
}
static struct snd_kcontrol_new img_spdif_out_controls[] = {
{
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
.info = img_spdif_out_info,
.get = img_spdif_out_get_status_mask
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.info = img_spdif_out_info,
.get = img_spdif_out_get_status,
.put = img_spdif_out_set_status
}
};
static int img_spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
u32 reg;
unsigned long flags;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
reg |= IMG_SPDIF_OUT_CTL_SRT_MASK;
img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
spin_lock_irqsave(&spdif->lock, flags);
img_spdif_out_reset(spdif);
spin_unlock_irqrestore(&spdif->lock, flags);
break;
default:
return -EINVAL;
}
return 0;
}
static int img_spdif_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
unsigned int channels;
long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
u32 reg;
snd_pcm_format_t format;
rate = params_rate(params);
format = params_format(params);
channels = params_channels(params);
dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
rate, channels, format);
if (format != SNDRV_PCM_FORMAT_S32_LE)
return -EINVAL;
if (channels != 2)
return -EINVAL;
pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
if (pre_div_a < 0)
return pre_div_a;
pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
if (pre_div_b < 0)
return pre_div_b;
diff_a = abs((pre_div_a / 256) - rate);
diff_b = abs((pre_div_b / 384) - rate);
/* If diffs are equal, use lower clock rate */
if (diff_a > diff_b)
clk_set_rate(spdif->clk_ref, pre_div_b);
else
clk_set_rate(spdif->clk_ref, pre_div_a);
/*
* Another driver (eg machine driver) may have rejected the above
* change. Get the current rate and set the register bit according to
* the new min diff
*/
clk_rate = clk_get_rate(spdif->clk_ref);
diff_a = abs((clk_rate / 256) - rate);
diff_b = abs((clk_rate / 384) - rate);
reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
if (diff_a <= diff_b)
reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK;
else
reg |= IMG_SPDIF_OUT_CTL_CLK_MASK;
img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
return 0;
}
static int img_spdif_out_dai_probe(struct snd_soc_dai *dai)
{
struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
snd_soc_add_dai_controls(dai, img_spdif_out_controls,
ARRAY_SIZE(img_spdif_out_controls));
return 0;
}
static const struct snd_soc_dai_ops img_spdif_out_dai_ops = {
.probe = img_spdif_out_dai_probe,
.trigger = img_spdif_out_trigger,
.hw_params = img_spdif_out_hw_params
};
static struct snd_soc_dai_driver img_spdif_out_dai = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE
},
.ops = &img_spdif_out_dai_ops
};
static const struct snd_soc_component_driver img_spdif_out_component = {
.name = "img-spdif-out",
.legacy_dai_naming = 1,
};
static int img_spdif_out_probe(struct platform_device *pdev)
{
struct img_spdif_out *spdif;
struct resource *res;
void __iomem *base;
int ret;
struct device *dev = &pdev->dev;
spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
if (!spdif)
return -ENOMEM;
platform_set_drvdata(pdev, spdif);
spdif->dev = &pdev->dev;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
spdif->base = base;
spdif->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
if (IS_ERR(spdif->rst))
return dev_err_probe(&pdev->dev, PTR_ERR(spdif->rst),
"No top level reset found\n");
spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
if (IS_ERR(spdif->clk_sys))
return dev_err_probe(dev, PTR_ERR(spdif->clk_sys),
"Failed to acquire clock 'sys'\n");
spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
if (IS_ERR(spdif->clk_ref))
return dev_err_probe(dev, PTR_ERR(spdif->clk_ref),
"Failed to acquire clock 'ref'\n");
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = img_spdif_out_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_suspend;
img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
IMG_SPDIF_OUT_CTL);
img_spdif_out_reset(spdif);
pm_runtime_put(&pdev->dev);
spin_lock_init(&spdif->lock);
spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
spdif->dma_data.addr_width = 4;
spdif->dma_data.maxburst = 4;
ret = devm_snd_soc_register_component(&pdev->dev,
&img_spdif_out_component,
&img_spdif_out_dai, 1);
if (ret)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_suspend;
dev_dbg(&pdev->dev, "Probe successful\n");
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
img_spdif_out_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void img_spdif_out_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
img_spdif_out_runtime_suspend(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int img_spdif_out_suspend(struct device *dev)
{
struct img_spdif_out *spdif = dev_get_drvdata(dev);
int ret;
if (pm_runtime_status_suspended(dev)) {
ret = img_spdif_out_runtime_resume(dev);
if (ret)
return ret;
}
spdif->suspend_ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
spdif->suspend_csl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
spdif->suspend_csh = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
img_spdif_out_runtime_suspend(dev);
return 0;
}
static int img_spdif_out_resume(struct device *dev)
{
struct img_spdif_out *spdif = dev_get_drvdata(dev);
int ret;
ret = img_spdif_out_runtime_resume(dev);
if (ret)
return ret;
img_spdif_out_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_OUT_CTL);
img_spdif_out_writel(spdif, spdif->suspend_csl, IMG_SPDIF_OUT_CSL);
img_spdif_out_writel(spdif, spdif->suspend_csh, IMG_SPDIF_OUT_CSH_UV);
if (pm_runtime_status_suspended(dev))
img_spdif_out_runtime_suspend(dev);
return 0;
}
#endif
static const struct of_device_id img_spdif_out_of_match[] = {
{ .compatible = "img,spdif-out" },
{}
};
MODULE_DEVICE_TABLE(of, img_spdif_out_of_match);
static const struct dev_pm_ops img_spdif_out_pm_ops = {
SET_RUNTIME_PM_OPS(img_spdif_out_runtime_suspend,
img_spdif_out_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(img_spdif_out_suspend, img_spdif_out_resume)
};
static struct platform_driver img_spdif_out_driver = {
.driver = {
.name = "img-spdif-out",
.of_match_table = img_spdif_out_of_match,
.pm = &img_spdif_out_pm_ops
},
.probe = img_spdif_out_probe,
.remove_new = img_spdif_out_dev_remove
};
module_platform_driver(img_spdif_out_driver);
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_DESCRIPTION("IMG SPDIF Output driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/img/img-spdif-out.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IMG I2S output controller driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define IMG_I2S_OUT_TX_FIFO 0x0
#define IMG_I2S_OUT_CTL 0x4
#define IMG_I2S_OUT_CTL_DATA_EN_MASK BIT(24)
#define IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK 0xffe000
#define IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT 13
#define IMG_I2S_OUT_CTL_FRM_SIZE_MASK BIT(8)
#define IMG_I2S_OUT_CTL_MASTER_MASK BIT(6)
#define IMG_I2S_OUT_CTL_CLK_MASK BIT(5)
#define IMG_I2S_OUT_CTL_CLK_EN_MASK BIT(4)
#define IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK BIT(3)
#define IMG_I2S_OUT_CTL_BCLK_POL_MASK BIT(2)
#define IMG_I2S_OUT_CTL_ME_MASK BIT(0)
#define IMG_I2S_OUT_CH_CTL 0x4
#define IMG_I2S_OUT_CHAN_CTL_CH_MASK BIT(11)
#define IMG_I2S_OUT_CHAN_CTL_LT_MASK BIT(10)
#define IMG_I2S_OUT_CHAN_CTL_FMT_MASK 0xf0
#define IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT 4
#define IMG_I2S_OUT_CHAN_CTL_JUST_MASK BIT(3)
#define IMG_I2S_OUT_CHAN_CTL_CLKT_MASK BIT(1)
#define IMG_I2S_OUT_CHAN_CTL_ME_MASK BIT(0)
#define IMG_I2S_OUT_CH_STRIDE 0x20
struct img_i2s_out {
void __iomem *base;
struct clk *clk_sys;
struct clk *clk_ref;
struct snd_dmaengine_dai_dma_data dma_data;
struct device *dev;
unsigned int max_i2s_chan;
void __iomem *channel_base;
bool force_clk_active;
unsigned int active_channels;
struct reset_control *rst;
struct snd_soc_dai_driver dai_driver;
u32 suspend_ctl;
u32 *suspend_ch_ctl;
};
static int img_i2s_out_runtime_suspend(struct device *dev)
{
struct img_i2s_out *i2s = dev_get_drvdata(dev);
clk_disable_unprepare(i2s->clk_ref);
clk_disable_unprepare(i2s->clk_sys);
return 0;
}
static int img_i2s_out_runtime_resume(struct device *dev)
{
struct img_i2s_out *i2s = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s->clk_sys);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(i2s->clk_ref);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
clk_disable_unprepare(i2s->clk_sys);
return ret;
}
return 0;
}
static inline void img_i2s_out_writel(struct img_i2s_out *i2s, u32 val,
u32 reg)
{
writel(val, i2s->base + reg);
}
static inline u32 img_i2s_out_readl(struct img_i2s_out *i2s, u32 reg)
{
return readl(i2s->base + reg);
}
static inline void img_i2s_out_ch_writel(struct img_i2s_out *i2s,
u32 chan, u32 val, u32 reg)
{
writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
}
static inline u32 img_i2s_out_ch_readl(struct img_i2s_out *i2s, u32 chan,
u32 reg)
{
return readl(i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
}
static inline void img_i2s_out_ch_disable(struct img_i2s_out *i2s, u32 chan)
{
u32 reg;
reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
reg &= ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
}
static inline void img_i2s_out_ch_enable(struct img_i2s_out *i2s, u32 chan)
{
u32 reg;
reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
reg |= IMG_I2S_OUT_CHAN_CTL_ME_MASK;
img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
}
static inline void img_i2s_out_disable(struct img_i2s_out *i2s)
{
u32 reg;
reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
reg &= ~IMG_I2S_OUT_CTL_ME_MASK;
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
}
static inline void img_i2s_out_enable(struct img_i2s_out *i2s)
{
u32 reg;
reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
reg |= IMG_I2S_OUT_CTL_ME_MASK;
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
}
static void img_i2s_out_reset(struct img_i2s_out *i2s)
{
int i;
u32 core_ctl, chan_ctl;
core_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL) &
~IMG_I2S_OUT_CTL_ME_MASK &
~IMG_I2S_OUT_CTL_DATA_EN_MASK;
if (!i2s->force_clk_active)
core_ctl &= ~IMG_I2S_OUT_CTL_CLK_EN_MASK;
chan_ctl = img_i2s_out_ch_readl(i2s, 0, IMG_I2S_OUT_CH_CTL) &
~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
reset_control_assert(i2s->rst);
reset_control_deassert(i2s->rst);
for (i = 0; i < i2s->max_i2s_chan; i++)
img_i2s_out_ch_writel(i2s, i, chan_ctl, IMG_I2S_OUT_CH_CTL);
for (i = 0; i < i2s->active_channels; i++)
img_i2s_out_ch_enable(i2s, i);
img_i2s_out_writel(i2s, core_ctl, IMG_I2S_OUT_CTL);
img_i2s_out_enable(i2s);
}
static int img_i2s_out_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
u32 reg;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
if (!i2s->force_clk_active)
reg |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
reg |= IMG_I2S_OUT_CTL_DATA_EN_MASK;
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
img_i2s_out_reset(i2s);
break;
default:
return -EINVAL;
}
return 0;
}
static int img_i2s_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int channels, i2s_channels;
long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
int i;
u32 reg, control_mask, control_set = 0;
snd_pcm_format_t format;
rate = params_rate(params);
format = params_format(params);
channels = params_channels(params);
i2s_channels = channels / 2;
if (format != SNDRV_PCM_FORMAT_S32_LE)
return -EINVAL;
if ((channels < 2) ||
(channels > (i2s->max_i2s_chan * 2)) ||
(channels % 2))
return -EINVAL;
pre_div_a = clk_round_rate(i2s->clk_ref, rate * 256);
if (pre_div_a < 0)
return pre_div_a;
pre_div_b = clk_round_rate(i2s->clk_ref, rate * 384);
if (pre_div_b < 0)
return pre_div_b;
diff_a = abs((pre_div_a / 256) - rate);
diff_b = abs((pre_div_b / 384) - rate);
/* If diffs are equal, use lower clock rate */
if (diff_a > diff_b)
clk_set_rate(i2s->clk_ref, pre_div_b);
else
clk_set_rate(i2s->clk_ref, pre_div_a);
/*
* Another driver (eg alsa machine driver) may have rejected the above
* change. Get the current rate and set the register bit according to
* the new minimum diff
*/
clk_rate = clk_get_rate(i2s->clk_ref);
diff_a = abs((clk_rate / 256) - rate);
diff_b = abs((clk_rate / 384) - rate);
if (diff_a > diff_b)
control_set |= IMG_I2S_OUT_CTL_CLK_MASK;
control_set |= ((i2s_channels - 1) <<
IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT) &
IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
control_mask = IMG_I2S_OUT_CTL_CLK_MASK |
IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
img_i2s_out_disable(i2s);
reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
reg = (reg & ~control_mask) | control_set;
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
for (i = 0; i < i2s_channels; i++)
img_i2s_out_ch_enable(i2s, i);
for (; i < i2s->max_i2s_chan; i++)
img_i2s_out_ch_disable(i2s, i);
img_i2s_out_enable(i2s);
i2s->active_channels = i2s_channels;
return 0;
}
static int img_i2s_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
int i, ret;
bool force_clk_active;
u32 chan_control_mask, control_mask, chan_control_set = 0;
u32 reg, control_set = 0;
force_clk_active = ((fmt & SND_SOC_DAIFMT_CLOCK_MASK) ==
SND_SOC_DAIFMT_CONT);
if (force_clk_active)
control_set |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
break;
case SND_SOC_DAIFMT_BP_FP:
control_set |= IMG_I2S_OUT_CTL_MASTER_MASK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
break;
case SND_SOC_DAIFMT_NB_IF:
control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
chan_control_set |= IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
break;
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
control_mask = IMG_I2S_OUT_CTL_CLK_EN_MASK |
IMG_I2S_OUT_CTL_MASTER_MASK |
IMG_I2S_OUT_CTL_BCLK_POL_MASK |
IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
chan_control_mask = IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
ret = pm_runtime_resume_and_get(i2s->dev);
if (ret < 0)
return ret;
img_i2s_out_disable(i2s);
reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
reg = (reg & ~control_mask) | control_set;
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
for (i = 0; i < i2s->active_channels; i++)
img_i2s_out_ch_disable(i2s, i);
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
reg = (reg & ~chan_control_mask) | chan_control_set;
img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
}
for (i = 0; i < i2s->active_channels; i++)
img_i2s_out_ch_enable(i2s, i);
img_i2s_out_enable(i2s);
pm_runtime_put(i2s->dev);
i2s->force_clk_active = force_clk_active;
return 0;
}
static int img_i2s_out_dai_probe(struct snd_soc_dai *dai)
{
struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &i2s->dma_data, NULL);
return 0;
}
static const struct snd_soc_dai_ops img_i2s_out_dai_ops = {
.probe = img_i2s_out_dai_probe,
.trigger = img_i2s_out_trigger,
.hw_params = img_i2s_out_hw_params,
.set_fmt = img_i2s_out_set_fmt
};
static const struct snd_soc_component_driver img_i2s_out_component = {
.name = "img-i2s-out",
.legacy_dai_naming = 1,
};
static int img_i2s_out_dma_prepare_slave_config(struct snd_pcm_substream *st,
struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
{
unsigned int i2s_channels = params_channels(params) / 2;
struct snd_soc_pcm_runtime *rtd = st->private_data;
struct snd_dmaengine_dai_dma_data *dma_data;
int ret;
dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
ret = snd_hwparams_to_dma_slave_config(st, params, sc);
if (ret)
return ret;
sc->dst_addr = dma_data->addr;
sc->dst_addr_width = dma_data->addr_width;
sc->dst_maxburst = 4 * i2s_channels;
return 0;
}
static const struct snd_dmaengine_pcm_config img_i2s_out_dma_config = {
.prepare_slave_config = img_i2s_out_dma_prepare_slave_config
};
static int img_i2s_out_probe(struct platform_device *pdev)
{
struct img_i2s_out *i2s;
struct resource *res;
void __iomem *base;
int i, ret;
unsigned int max_i2s_chan_pow_2;
u32 reg;
struct device *dev = &pdev->dev;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
platform_set_drvdata(pdev, i2s);
i2s->dev = &pdev->dev;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
i2s->base = base;
if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
&i2s->max_i2s_chan)) {
dev_err(&pdev->dev, "No img,i2s-channels property\n");
return -EINVAL;
}
max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
if (IS_ERR(i2s->rst))
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->rst),
"No top level reset found\n");
i2s->clk_sys = devm_clk_get(&pdev->dev, "sys");
if (IS_ERR(i2s->clk_sys))
return dev_err_probe(dev, PTR_ERR(i2s->clk_sys),
"Failed to acquire clock 'sys'\n");
i2s->clk_ref = devm_clk_get(&pdev->dev, "ref");
if (IS_ERR(i2s->clk_ref))
return dev_err_probe(dev, PTR_ERR(i2s->clk_ref),
"Failed to acquire clock 'ref'\n");
i2s->suspend_ch_ctl = devm_kcalloc(dev,
i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
if (!i2s->suspend_ch_ctl)
return -ENOMEM;
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = img_i2s_out_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_suspend;
reg = IMG_I2S_OUT_CTL_FRM_SIZE_MASK;
img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
reg = IMG_I2S_OUT_CHAN_CTL_JUST_MASK |
IMG_I2S_OUT_CHAN_CTL_LT_MASK |
IMG_I2S_OUT_CHAN_CTL_CH_MASK |
(8 << IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT);
for (i = 0; i < i2s->max_i2s_chan; i++)
img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
img_i2s_out_reset(i2s);
pm_runtime_put(&pdev->dev);
i2s->active_channels = 1;
i2s->dma_data.addr = res->start + IMG_I2S_OUT_TX_FIFO;
i2s->dma_data.addr_width = 4;
i2s->dma_data.maxburst = 4;
i2s->dai_driver.playback.channels_min = 2;
i2s->dai_driver.playback.channels_max = i2s->max_i2s_chan * 2;
i2s->dai_driver.playback.rates = SNDRV_PCM_RATE_8000_192000;
i2s->dai_driver.playback.formats = SNDRV_PCM_FMTBIT_S32_LE;
i2s->dai_driver.ops = &img_i2s_out_dai_ops;
ret = devm_snd_soc_register_component(&pdev->dev,
&img_i2s_out_component, &i2s->dai_driver, 1);
if (ret)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
&img_i2s_out_dma_config, 0);
if (ret)
goto err_suspend;
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
img_i2s_out_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void img_i2s_out_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
img_i2s_out_runtime_suspend(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int img_i2s_out_suspend(struct device *dev)
{
struct img_i2s_out *i2s = dev_get_drvdata(dev);
int i, ret;
u32 reg;
if (pm_runtime_status_suspended(dev)) {
ret = img_i2s_out_runtime_resume(dev);
if (ret)
return ret;
}
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
i2s->suspend_ch_ctl[i] = reg;
}
i2s->suspend_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
img_i2s_out_runtime_suspend(dev);
return 0;
}
static int img_i2s_out_resume(struct device *dev)
{
struct img_i2s_out *i2s = dev_get_drvdata(dev);
int i, ret;
u32 reg;
ret = img_i2s_out_runtime_resume(dev);
if (ret)
return ret;
for (i = 0; i < i2s->max_i2s_chan; i++) {
reg = i2s->suspend_ch_ctl[i];
img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
}
img_i2s_out_writel(i2s, i2s->suspend_ctl, IMG_I2S_OUT_CTL);
if (pm_runtime_status_suspended(dev))
img_i2s_out_runtime_suspend(dev);
return 0;
}
#endif
static const struct of_device_id img_i2s_out_of_match[] = {
{ .compatible = "img,i2s-out" },
{}
};
MODULE_DEVICE_TABLE(of, img_i2s_out_of_match);
static const struct dev_pm_ops img_i2s_out_pm_ops = {
SET_RUNTIME_PM_OPS(img_i2s_out_runtime_suspend,
img_i2s_out_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(img_i2s_out_suspend, img_i2s_out_resume)
};
static struct platform_driver img_i2s_out_driver = {
.driver = {
.name = "img-i2s-out",
.of_match_table = img_i2s_out_of_match,
.pm = &img_i2s_out_pm_ops
},
.probe = img_i2s_out_probe,
.remove_new = img_i2s_out_dev_remove
};
module_platform_driver(img_i2s_out_driver);
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_DESCRIPTION("IMG I2S Output Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/img/img-i2s-out.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pistachio internal dac driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define PISTACHIO_INTERNAL_DAC_CTRL 0x40
#define PISTACHIO_INTERNAL_DAC_CTRL_PWR_SEL_MASK 0x2
#define PISTACHIO_INTERNAL_DAC_CTRL_PWRDN_MASK 0x1
#define PISTACHIO_INTERNAL_DAC_SRST 0x44
#define PISTACHIO_INTERNAL_DAC_SRST_MASK 0x1
#define PISTACHIO_INTERNAL_DAC_GTI_CTRL 0x48
#define PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_SHIFT 0
#define PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_MASK 0xFFF
#define PISTACHIO_INTERNAL_DAC_GTI_CTRL_WE_MASK 0x1000
#define PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_SHIFT 13
#define PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_MASK 0x1FE000
#define PISTACHIO_INTERNAL_DAC_PWR 0x1
#define PISTACHIO_INTERNAL_DAC_PWR_MASK 0x1
#define PISTACHIO_INTERNAL_DAC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
/* codec private data */
struct pistachio_internal_dac {
struct regmap *regmap;
struct regulator *supply;
bool mute;
};
static const struct snd_kcontrol_new pistachio_internal_dac_snd_controls[] = {
SOC_SINGLE("Playback Switch", PISTACHIO_INTERNAL_DAC_CTRL, 2, 1, 1)
};
static const struct snd_soc_dapm_widget pistachio_internal_dac_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("AOUTL"),
SND_SOC_DAPM_OUTPUT("AOUTR"),
};
static const struct snd_soc_dapm_route pistachio_internal_dac_routes[] = {
{ "AOUTL", NULL, "DAC" },
{ "AOUTR", NULL, "DAC" },
};
static void pistachio_internal_dac_reg_writel(struct regmap *top_regs,
u32 val, u32 reg)
{
regmap_update_bits(top_regs, PISTACHIO_INTERNAL_DAC_GTI_CTRL,
PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_MASK,
reg << PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_SHIFT);
regmap_update_bits(top_regs, PISTACHIO_INTERNAL_DAC_GTI_CTRL,
PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_MASK,
val << PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_SHIFT);
regmap_update_bits(top_regs, PISTACHIO_INTERNAL_DAC_GTI_CTRL,
PISTACHIO_INTERNAL_DAC_GTI_CTRL_WE_MASK,
PISTACHIO_INTERNAL_DAC_GTI_CTRL_WE_MASK);
regmap_update_bits(top_regs, PISTACHIO_INTERNAL_DAC_GTI_CTRL,
PISTACHIO_INTERNAL_DAC_GTI_CTRL_WE_MASK, 0);
}
static void pistachio_internal_dac_pwr_off(struct pistachio_internal_dac *dac)
{
regmap_update_bits(dac->regmap, PISTACHIO_INTERNAL_DAC_CTRL,
PISTACHIO_INTERNAL_DAC_CTRL_PWRDN_MASK,
PISTACHIO_INTERNAL_DAC_CTRL_PWRDN_MASK);
pistachio_internal_dac_reg_writel(dac->regmap, 0,
PISTACHIO_INTERNAL_DAC_PWR);
}
static void pistachio_internal_dac_pwr_on(struct pistachio_internal_dac *dac)
{
regmap_update_bits(dac->regmap, PISTACHIO_INTERNAL_DAC_SRST,
PISTACHIO_INTERNAL_DAC_SRST_MASK,
PISTACHIO_INTERNAL_DAC_SRST_MASK);
regmap_update_bits(dac->regmap, PISTACHIO_INTERNAL_DAC_SRST,
PISTACHIO_INTERNAL_DAC_SRST_MASK, 0);
pistachio_internal_dac_reg_writel(dac->regmap,
PISTACHIO_INTERNAL_DAC_PWR_MASK,
PISTACHIO_INTERNAL_DAC_PWR);
regmap_update_bits(dac->regmap, PISTACHIO_INTERNAL_DAC_CTRL,
PISTACHIO_INTERNAL_DAC_CTRL_PWRDN_MASK, 0);
}
static struct snd_soc_dai_driver pistachio_internal_dac_dais[] = {
{
.name = "pistachio_internal_dac",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = PISTACHIO_INTERNAL_DAC_FORMATS,
}
},
};
static int pistachio_internal_dac_codec_probe(struct snd_soc_component *component)
{
struct pistachio_internal_dac *dac = snd_soc_component_get_drvdata(component);
snd_soc_component_init_regmap(component, dac->regmap);
return 0;
}
static const struct snd_soc_component_driver pistachio_internal_dac_driver = {
.probe = pistachio_internal_dac_codec_probe,
.controls = pistachio_internal_dac_snd_controls,
.num_controls = ARRAY_SIZE(pistachio_internal_dac_snd_controls),
.dapm_widgets = pistachio_internal_dac_widgets,
.num_dapm_widgets = ARRAY_SIZE(pistachio_internal_dac_widgets),
.dapm_routes = pistachio_internal_dac_routes,
.num_dapm_routes = ARRAY_SIZE(pistachio_internal_dac_routes),
.use_pmdown_time = 1,
.endianness = 1,
};
static int pistachio_internal_dac_probe(struct platform_device *pdev)
{
struct pistachio_internal_dac *dac;
int ret, voltage;
struct device *dev = &pdev->dev;
u32 reg;
dac = devm_kzalloc(dev, sizeof(*dac), GFP_KERNEL);
if (!dac)
return -ENOMEM;
platform_set_drvdata(pdev, dac);
dac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"img,cr-top");
if (IS_ERR(dac->regmap))
return PTR_ERR(dac->regmap);
dac->supply = devm_regulator_get(dev, "VDD");
if (IS_ERR(dac->supply))
return dev_err_probe(dev, PTR_ERR(dac->supply),
"failed to acquire supply 'VDD-supply'\n");
ret = regulator_enable(dac->supply);
if (ret) {
dev_err(dev, "failed to enable supply: %d\n", ret);
return ret;
}
voltage = regulator_get_voltage(dac->supply);
switch (voltage) {
case 1800000:
reg = 0;
break;
case 3300000:
reg = PISTACHIO_INTERNAL_DAC_CTRL_PWR_SEL_MASK;
break;
default:
dev_err(dev, "invalid voltage: %d\n", voltage);
ret = -EINVAL;
goto err_regulator;
}
regmap_update_bits(dac->regmap, PISTACHIO_INTERNAL_DAC_CTRL,
PISTACHIO_INTERNAL_DAC_CTRL_PWR_SEL_MASK, reg);
pistachio_internal_dac_pwr_off(dac);
pistachio_internal_dac_pwr_on(dac);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_idle(dev);
ret = devm_snd_soc_register_component(dev,
&pistachio_internal_dac_driver,
pistachio_internal_dac_dais,
ARRAY_SIZE(pistachio_internal_dac_dais));
if (ret) {
dev_err(dev, "failed to register component: %d\n", ret);
goto err_pwr;
}
return 0;
err_pwr:
pm_runtime_disable(&pdev->dev);
pistachio_internal_dac_pwr_off(dac);
err_regulator:
regulator_disable(dac->supply);
return ret;
}
static void pistachio_internal_dac_remove(struct platform_device *pdev)
{
struct pistachio_internal_dac *dac = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pistachio_internal_dac_pwr_off(dac);
regulator_disable(dac->supply);
}
#ifdef CONFIG_PM
static int pistachio_internal_dac_rt_resume(struct device *dev)
{
struct pistachio_internal_dac *dac = dev_get_drvdata(dev);
int ret;
ret = regulator_enable(dac->supply);
if (ret) {
dev_err(dev, "failed to enable supply: %d\n", ret);
return ret;
}
pistachio_internal_dac_pwr_on(dac);
return 0;
}
static int pistachio_internal_dac_rt_suspend(struct device *dev)
{
struct pistachio_internal_dac *dac = dev_get_drvdata(dev);
pistachio_internal_dac_pwr_off(dac);
regulator_disable(dac->supply);
return 0;
}
#endif
static const struct dev_pm_ops pistachio_internal_dac_pm_ops = {
SET_RUNTIME_PM_OPS(pistachio_internal_dac_rt_suspend,
pistachio_internal_dac_rt_resume, NULL)
};
static const struct of_device_id pistachio_internal_dac_of_match[] = {
{ .compatible = "img,pistachio-internal-dac" },
{}
};
MODULE_DEVICE_TABLE(of, pistachio_internal_dac_of_match);
static struct platform_driver pistachio_internal_dac_plat_driver = {
.driver = {
.name = "img-pistachio-internal-dac",
.of_match_table = pistachio_internal_dac_of_match,
.pm = &pistachio_internal_dac_pm_ops
},
.probe = pistachio_internal_dac_probe,
.remove_new = pistachio_internal_dac_remove
};
module_platform_driver(pistachio_internal_dac_plat_driver);
MODULE_DESCRIPTION("Pistachio Internal DAC driver");
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/img/pistachio-internal-dac.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* IMG parallel output controller driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define IMG_PRL_OUT_TX_FIFO 0
#define IMG_PRL_OUT_CTL 0x4
#define IMG_PRL_OUT_CTL_CH_MASK BIT(4)
#define IMG_PRL_OUT_CTL_PACKH_MASK BIT(3)
#define IMG_PRL_OUT_CTL_EDGE_MASK BIT(2)
#define IMG_PRL_OUT_CTL_ME_MASK BIT(1)
#define IMG_PRL_OUT_CTL_SRST_MASK BIT(0)
struct img_prl_out {
void __iomem *base;
struct clk *clk_sys;
struct clk *clk_ref;
struct snd_dmaengine_dai_dma_data dma_data;
struct device *dev;
struct reset_control *rst;
};
static int img_prl_out_suspend(struct device *dev)
{
struct img_prl_out *prl = dev_get_drvdata(dev);
clk_disable_unprepare(prl->clk_ref);
return 0;
}
static int img_prl_out_resume(struct device *dev)
{
struct img_prl_out *prl = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(prl->clk_ref);
if (ret) {
dev_err(dev, "clk_enable failed: %d\n", ret);
return ret;
}
return 0;
}
static inline void img_prl_out_writel(struct img_prl_out *prl,
u32 val, u32 reg)
{
writel(val, prl->base + reg);
}
static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
{
return readl(prl->base + reg);
}
static void img_prl_out_reset(struct img_prl_out *prl)
{
u32 ctl;
ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
~IMG_PRL_OUT_CTL_ME_MASK;
reset_control_assert(prl->rst);
reset_control_deassert(prl->rst);
img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
}
static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
u32 reg;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
reg |= IMG_PRL_OUT_CTL_ME_MASK;
img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
img_prl_out_reset(prl);
break;
default:
return -EINVAL;
}
return 0;
}
static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
unsigned int rate, channels;
u32 reg, control_set = 0;
rate = params_rate(params);
channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S32_LE:
control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
break;
case SNDRV_PCM_FORMAT_S24_LE:
break;
default:
return -EINVAL;
}
if (channels != 2)
return -EINVAL;
clk_set_rate(prl->clk_ref, rate * 256);
reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
return 0;
}
static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
u32 reg, control_set = 0;
int ret;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
break;
default:
return -EINVAL;
}
ret = pm_runtime_resume_and_get(prl->dev);
if (ret < 0)
return ret;
reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
pm_runtime_put(prl->dev);
return 0;
}
static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
{
struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
return 0;
}
static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
.probe = img_prl_out_dai_probe,
.trigger = img_prl_out_trigger,
.hw_params = img_prl_out_hw_params,
.set_fmt = img_prl_out_set_fmt
};
static struct snd_soc_dai_driver img_prl_out_dai = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
},
.ops = &img_prl_out_dai_ops
};
static const struct snd_soc_component_driver img_prl_out_component = {
.name = "img-prl-out",
.legacy_dai_naming = 1,
};
static int img_prl_out_probe(struct platform_device *pdev)
{
struct img_prl_out *prl;
struct resource *res;
void __iomem *base;
int ret;
struct device *dev = &pdev->dev;
prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
if (!prl)
return -ENOMEM;
platform_set_drvdata(pdev, prl);
prl->dev = &pdev->dev;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
prl->base = base;
prl->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
if (IS_ERR(prl->rst))
return dev_err_probe(&pdev->dev, PTR_ERR(prl->rst),
"No top level reset found\n");
prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
if (IS_ERR(prl->clk_sys))
return dev_err_probe(dev, PTR_ERR(prl->clk_sys),
"Failed to acquire clock 'sys'\n");
prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
if (IS_ERR(prl->clk_ref))
return dev_err_probe(dev, PTR_ERR(prl->clk_ref),
"Failed to acquire clock 'ref'\n");
ret = clk_prepare_enable(prl->clk_sys);
if (ret)
return ret;
img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
img_prl_out_reset(prl);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = img_prl_out_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
prl->dma_data.addr_width = 4;
prl->dma_data.maxburst = 4;
ret = devm_snd_soc_register_component(&pdev->dev,
&img_prl_out_component,
&img_prl_out_dai, 1);
if (ret)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_suspend;
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
img_prl_out_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
clk_disable_unprepare(prl->clk_sys);
return ret;
}
static void img_prl_out_dev_remove(struct platform_device *pdev)
{
struct img_prl_out *prl = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
img_prl_out_suspend(&pdev->dev);
clk_disable_unprepare(prl->clk_sys);
}
static const struct of_device_id img_prl_out_of_match[] = {
{ .compatible = "img,parallel-out" },
{}
};
MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
static const struct dev_pm_ops img_prl_out_pm_ops = {
SET_RUNTIME_PM_OPS(img_prl_out_suspend,
img_prl_out_resume, NULL)
};
static struct platform_driver img_prl_out_driver = {
.driver = {
.name = "img-parallel-out",
.of_match_table = img_prl_out_of_match,
.pm = &img_prl_out_pm_ops
},
.probe = img_prl_out_probe,
.remove_new = img_prl_out_dev_remove
};
module_platform_driver(img_prl_out_driver);
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_DESCRIPTION("IMG Parallel Output Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/img/img-parallel-out.c |
// SPDX-License-Identifier: MIT
//
// Machine driver for AMD ACP Audio engine using DA7219, RT5682 & MAX98357 codec
//
//Copyright 2017-2021 Advanced Micro Devices, Inc.
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/driver.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/acpi.h>
#include "acp.h"
#include "../codecs/da7219.h"
#include "../codecs/rt5682.h"
#define CZ_PLAT_CLK 48000000
#define DUAL_CHANNEL 2
#define RT5682_PLL_FREQ (48000 * 512)
static struct snd_soc_jack cz_jack;
static struct snd_soc_jack_pin cz_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Line Out",
.mask = SND_JACK_LINEOUT,
},
};
static struct clk *da7219_dai_wclk;
static struct clk *da7219_dai_bclk;
static struct clk *rt5682_dai_wclk;
static struct clk *rt5682_dai_bclk;
void *acp_soc_is_rltk_max(struct device *dev);
static int cz_da7219_init(struct snd_soc_pcm_runtime *rtd)
{
int ret;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name);
ret = snd_soc_dai_set_sysclk(codec_dai, DA7219_CLKSRC_MCLK,
CZ_PLAT_CLK, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_PLL,
CZ_PLAT_CLK, DA7219_PLL_FREQ_OUT_98304);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
da7219_dai_wclk = devm_clk_get(component->dev, "da7219-dai-wclk");
if (IS_ERR(da7219_dai_wclk))
return PTR_ERR(da7219_dai_wclk);
da7219_dai_bclk = devm_clk_get(component->dev, "da7219-dai-bclk");
if (IS_ERR(da7219_dai_bclk))
return PTR_ERR(da7219_dai_bclk);
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&cz_jack,
cz_jack_pins,
ARRAY_SIZE(cz_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
snd_soc_component_set_jack(component, &cz_jack, NULL);
return 0;
}
static int da7219_clk_enable(struct snd_pcm_substream *substream)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
/*
* Set wclk to 48000 because the rate constraint of this driver is
* 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is
* minimum of 64x the LRCLK sample rate." DA7219 is the only clk
* source so for all codecs we have to limit bclk to 64X lrclk.
*/
clk_set_rate(da7219_dai_wclk, 48000);
clk_set_rate(da7219_dai_bclk, 48000 * 64);
ret = clk_prepare_enable(da7219_dai_bclk);
if (ret < 0) {
dev_err(rtd->dev, "can't enable master clock %d\n", ret);
return ret;
}
return ret;
}
static void da7219_clk_disable(void)
{
clk_disable_unprepare(da7219_dai_bclk);
}
static int cz_rt5682_init(struct snd_soc_pcm_runtime *rtd)
{
int ret;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
dev_info(codec_dai->dev, "codec dai name = %s\n", codec_dai->name);
/* Set codec sysclk */
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682_SCLK_S_PLL2,
RT5682_PLL_FREQ, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev,
"Failed to set rt5682 SYSCLK: %d\n", ret);
return ret;
}
/* set codec PLL */
ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL2, RT5682_PLL2_S_MCLK,
CZ_PLAT_CLK, RT5682_PLL_FREQ);
if (ret < 0) {
dev_err(codec_dai->dev, "can't set rt5682 PLL: %d\n", ret);
return ret;
}
rt5682_dai_wclk = devm_clk_get(component->dev, "rt5682-dai-wclk");
if (IS_ERR(rt5682_dai_wclk))
return PTR_ERR(rt5682_dai_wclk);
rt5682_dai_bclk = devm_clk_get(component->dev, "rt5682-dai-bclk");
if (IS_ERR(rt5682_dai_bclk))
return PTR_ERR(rt5682_dai_bclk);
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&cz_jack,
cz_jack_pins,
ARRAY_SIZE(cz_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
snd_jack_set_key(cz_jack.jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
ret = snd_soc_component_set_jack(component, &cz_jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return 0;
}
static int rt5682_clk_enable(struct snd_pcm_substream *substream)
{
int ret;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
/*
* Set wclk to 48000 because the rate constraint of this driver is
* 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is
* minimum of 64x the LRCLK sample rate." RT5682 is the only clk
* source so for all codecs we have to limit bclk to 64X lrclk.
*/
ret = clk_set_rate(rt5682_dai_wclk, 48000);
if (ret) {
dev_err(rtd->dev, "Error setting wclk rate: %d\n", ret);
return ret;
}
ret = clk_set_rate(rt5682_dai_bclk, 48000 * 64);
if (ret) {
dev_err(rtd->dev, "Error setting bclk rate: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(rt5682_dai_wclk);
if (ret < 0) {
dev_err(rtd->dev, "can't enable wclk %d\n", ret);
return ret;
}
return ret;
}
static void rt5682_clk_disable(void)
{
clk_disable_unprepare(rt5682_dai_wclk);
}
static const unsigned int channels[] = {
DUAL_CHANNEL,
};
static const unsigned int rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
static int cz_da7219_play_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->play_i2s_instance = I2S_SP_INSTANCE;
return da7219_clk_enable(substream);
}
static int cz_da7219_cap_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->cap_i2s_instance = I2S_SP_INSTANCE;
machine->capture_channel = CAP_CHANNEL1;
return da7219_clk_enable(substream);
}
static int cz_max_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->play_i2s_instance = I2S_BT_INSTANCE;
return da7219_clk_enable(substream);
}
static int cz_dmic0_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->cap_i2s_instance = I2S_BT_INSTANCE;
return da7219_clk_enable(substream);
}
static int cz_dmic1_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->cap_i2s_instance = I2S_SP_INSTANCE;
machine->capture_channel = CAP_CHANNEL0;
return da7219_clk_enable(substream);
}
static void cz_da7219_shutdown(struct snd_pcm_substream *substream)
{
da7219_clk_disable();
}
static int cz_rt5682_play_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->play_i2s_instance = I2S_SP_INSTANCE;
return rt5682_clk_enable(substream);
}
static int cz_rt5682_cap_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->cap_i2s_instance = I2S_SP_INSTANCE;
machine->capture_channel = CAP_CHANNEL1;
return rt5682_clk_enable(substream);
}
static int cz_rt5682_max_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->play_i2s_instance = I2S_BT_INSTANCE;
return rt5682_clk_enable(substream);
}
static int cz_rt5682_dmic0_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->cap_i2s_instance = I2S_BT_INSTANCE;
return rt5682_clk_enable(substream);
}
static int cz_rt5682_dmic1_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_platform_info *machine = snd_soc_card_get_drvdata(card);
/*
* On this platform for PCM device we support stereo
*/
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
machine->cap_i2s_instance = I2S_SP_INSTANCE;
machine->capture_channel = CAP_CHANNEL0;
return rt5682_clk_enable(substream);
}
static void cz_rt5682_shutdown(struct snd_pcm_substream *substream)
{
rt5682_clk_disable();
}
static const struct snd_soc_ops cz_da7219_play_ops = {
.startup = cz_da7219_play_startup,
.shutdown = cz_da7219_shutdown,
};
static const struct snd_soc_ops cz_da7219_cap_ops = {
.startup = cz_da7219_cap_startup,
.shutdown = cz_da7219_shutdown,
};
static const struct snd_soc_ops cz_max_play_ops = {
.startup = cz_max_startup,
.shutdown = cz_da7219_shutdown,
};
static const struct snd_soc_ops cz_dmic0_cap_ops = {
.startup = cz_dmic0_startup,
.shutdown = cz_da7219_shutdown,
};
static const struct snd_soc_ops cz_dmic1_cap_ops = {
.startup = cz_dmic1_startup,
.shutdown = cz_da7219_shutdown,
};
static const struct snd_soc_ops cz_rt5682_play_ops = {
.startup = cz_rt5682_play_startup,
.shutdown = cz_rt5682_shutdown,
};
static const struct snd_soc_ops cz_rt5682_cap_ops = {
.startup = cz_rt5682_cap_startup,
.shutdown = cz_rt5682_shutdown,
};
static const struct snd_soc_ops cz_rt5682_max_play_ops = {
.startup = cz_rt5682_max_startup,
.shutdown = cz_rt5682_shutdown,
};
static const struct snd_soc_ops cz_rt5682_dmic0_cap_ops = {
.startup = cz_rt5682_dmic0_startup,
.shutdown = cz_rt5682_shutdown,
};
static const struct snd_soc_ops cz_rt5682_dmic1_cap_ops = {
.startup = cz_rt5682_dmic1_startup,
.shutdown = cz_rt5682_shutdown,
};
SND_SOC_DAILINK_DEF(designware1,
DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.1.auto")));
SND_SOC_DAILINK_DEF(designware2,
DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.2.auto")));
SND_SOC_DAILINK_DEF(designware3,
DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.3.auto")));
SND_SOC_DAILINK_DEF(dlgs,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-DLGS7219:00", "da7219-hifi")));
SND_SOC_DAILINK_DEF(rt5682,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5682:00", "rt5682-aif1")));
SND_SOC_DAILINK_DEF(mx,
DAILINK_COMP_ARRAY(COMP_CODEC("MX98357A:00", "HiFi")));
SND_SOC_DAILINK_DEF(adau,
DAILINK_COMP_ARRAY(COMP_CODEC("ADAU7002:00", "adau7002-hifi")));
SND_SOC_DAILINK_DEF(platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_audio_dma.0.auto")));
static struct snd_soc_dai_link cz_dai_7219_98357[] = {
{
.name = "amd-da7219-play",
.stream_name = "Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.init = cz_da7219_init,
.dpcm_playback = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_da7219_play_ops,
SND_SOC_DAILINK_REG(designware1, dlgs, platform),
},
{
.name = "amd-da7219-cap",
.stream_name = "Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_da7219_cap_ops,
SND_SOC_DAILINK_REG(designware2, dlgs, platform),
},
{
.name = "amd-max98357-play",
.stream_name = "HiFi Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_playback = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_max_play_ops,
SND_SOC_DAILINK_REG(designware3, mx, platform),
},
{
/* C panel DMIC */
.name = "dmic0",
.stream_name = "DMIC0 Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_dmic0_cap_ops,
SND_SOC_DAILINK_REG(designware3, adau, platform),
},
{
/* A/B panel DMIC */
.name = "dmic1",
.stream_name = "DMIC1 Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_dmic1_cap_ops,
SND_SOC_DAILINK_REG(designware2, adau, platform),
},
};
static struct snd_soc_dai_link cz_dai_5682_98357[] = {
{
.name = "amd-rt5682-play",
.stream_name = "Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.init = cz_rt5682_init,
.dpcm_playback = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_rt5682_play_ops,
SND_SOC_DAILINK_REG(designware1, rt5682, platform),
},
{
.name = "amd-rt5682-cap",
.stream_name = "Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_rt5682_cap_ops,
SND_SOC_DAILINK_REG(designware2, rt5682, platform),
},
{
.name = "amd-max98357-play",
.stream_name = "HiFi Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_playback = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_rt5682_max_play_ops,
SND_SOC_DAILINK_REG(designware3, mx, platform),
},
{
/* C panel DMIC */
.name = "dmic0",
.stream_name = "DMIC0 Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_rt5682_dmic0_cap_ops,
SND_SOC_DAILINK_REG(designware3, adau, platform),
},
{
/* A/B panel DMIC */
.name = "dmic1",
.stream_name = "DMIC1 Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.ops = &cz_rt5682_dmic1_cap_ops,
SND_SOC_DAILINK_REG(designware2, adau, platform),
},
};
static const struct snd_soc_dapm_widget cz_widgets[] = {
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_LINE("Line Out", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
};
static const struct snd_soc_dapm_route cz_audio_route[] = {
{"Headphones", NULL, "HPL"},
{"Headphones", NULL, "HPR"},
{"MIC", NULL, "Headset Mic"},
{"Speakers", NULL, "Speaker"},
{"PDM_DAT", NULL, "Int Mic"},
};
static const struct snd_soc_dapm_route cz_rt5682_audio_route[] = {
{"Headphones", NULL, "HPOL"},
{"Headphones", NULL, "HPOR"},
{"IN1P", NULL, "Headset Mic"},
{"Speakers", NULL, "Speaker"},
{"PDM_DAT", NULL, "Int Mic"},
};
static const struct snd_kcontrol_new cz_mc_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphones"),
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Line Out"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
};
static struct snd_soc_card cz_card = {
.name = "acpd7219m98357",
.owner = THIS_MODULE,
.dai_link = cz_dai_7219_98357,
.num_links = ARRAY_SIZE(cz_dai_7219_98357),
.dapm_widgets = cz_widgets,
.num_dapm_widgets = ARRAY_SIZE(cz_widgets),
.dapm_routes = cz_audio_route,
.num_dapm_routes = ARRAY_SIZE(cz_audio_route),
.controls = cz_mc_controls,
.num_controls = ARRAY_SIZE(cz_mc_controls),
};
static struct snd_soc_card cz_rt5682_card = {
.name = "acpr5682m98357",
.owner = THIS_MODULE,
.dai_link = cz_dai_5682_98357,
.num_links = ARRAY_SIZE(cz_dai_5682_98357),
.dapm_widgets = cz_widgets,
.num_dapm_widgets = ARRAY_SIZE(cz_widgets),
.dapm_routes = cz_rt5682_audio_route,
.controls = cz_mc_controls,
.num_controls = ARRAY_SIZE(cz_mc_controls),
};
void *acp_soc_is_rltk_max(struct device *dev)
{
const struct acpi_device_id *match;
match = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!match)
return NULL;
return (void *)match->driver_data;
}
static struct regulator_consumer_supply acp_da7219_supplies[] = {
REGULATOR_SUPPLY("VDD", "i2c-DLGS7219:00"),
REGULATOR_SUPPLY("VDDMIC", "i2c-DLGS7219:00"),
REGULATOR_SUPPLY("VDDIO", "i2c-DLGS7219:00"),
REGULATOR_SUPPLY("IOVDD", "ADAU7002:00"),
};
static struct regulator_init_data acp_da7219_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(acp_da7219_supplies),
.consumer_supplies = acp_da7219_supplies,
};
static struct regulator_config acp_da7219_cfg = {
.init_data = &acp_da7219_data,
};
static struct regulator_ops acp_da7219_ops = {
};
static const struct regulator_desc acp_da7219_desc = {
.name = "reg-fixed-1.8V",
.type = REGULATOR_VOLTAGE,
.owner = THIS_MODULE,
.ops = &acp_da7219_ops,
.fixed_uV = 1800000, /* 1.8V */
.n_voltages = 1,
};
static int cz_probe(struct platform_device *pdev)
{
int ret;
struct snd_soc_card *card;
struct acp_platform_info *machine;
struct regulator_dev *rdev;
struct device *dev = &pdev->dev;
card = (struct snd_soc_card *)acp_soc_is_rltk_max(dev);
if (!card)
return -ENODEV;
if (!strcmp(card->name, "acpd7219m98357")) {
acp_da7219_cfg.dev = &pdev->dev;
rdev = devm_regulator_register(&pdev->dev, &acp_da7219_desc,
&acp_da7219_cfg);
if (IS_ERR(rdev)) {
dev_err(&pdev->dev, "Failed to register regulator: %d\n",
(int)PTR_ERR(rdev));
return -EINVAL;
}
}
machine = devm_kzalloc(&pdev->dev, sizeof(struct acp_platform_info),
GFP_KERNEL);
if (!machine)
return -ENOMEM;
card->dev = &pdev->dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
return dev_err_probe(&pdev->dev, ret,
"devm_snd_soc_register_card(%s) failed\n",
card->name);
}
acp_bt_uart_enable = !device_property_read_bool(&pdev->dev,
"bt-pad-enable");
return 0;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id cz_audio_acpi_match[] = {
{ "AMD7219", (unsigned long)&cz_card },
{ "AMDI5682", (unsigned long)&cz_rt5682_card},
{},
};
MODULE_DEVICE_TABLE(acpi, cz_audio_acpi_match);
#endif
static struct platform_driver cz_pcm_driver = {
.driver = {
.name = "cz-da7219-max98357a",
.acpi_match_table = ACPI_PTR(cz_audio_acpi_match),
.pm = &snd_soc_pm_ops,
},
.probe = cz_probe,
};
module_platform_driver(cz_pcm_driver);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("DA7219, RT5682 & MAX98357A audio support");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp-da7219-max98357a.c |
/*
* Machine driver for AMD ACP Audio engine using Realtek RT5645 codec
*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* This file is modified from rt288 machine driver
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/acpi.h>
#include "../codecs/rt5645.h"
#define CZ_PLAT_CLK 24000000
static struct snd_soc_jack cz_jack;
static struct snd_soc_jack_pin cz_jack_pins[] = {
{
.pin = "Headphones",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int cz_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
CZ_PLAT_CLK, params_rate(params) * 512);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
params_rate(params) * 512, SND_SOC_CLOCK_OUT);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
return ret;
}
return ret;
}
static int cz_init(struct snd_soc_pcm_runtime *rtd)
{
int ret;
struct snd_soc_card *card;
struct snd_soc_component *codec;
codec = asoc_rtd_to_codec(rtd, 0)->component;
card = rtd->card;
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&cz_jack,
cz_jack_pins,
ARRAY_SIZE(cz_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
rt5645_set_jack_detect(codec, &cz_jack, &cz_jack, &cz_jack);
return 0;
}
static const struct snd_soc_ops cz_aif1_ops = {
.hw_params = cz_aif1_hw_params,
};
SND_SOC_DAILINK_DEF(designware1,
DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.1.auto")));
SND_SOC_DAILINK_DEF(designware2,
DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.2.auto")));
SND_SOC_DAILINK_DEF(codec,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5650:00", "rt5645-aif1")));
SND_SOC_DAILINK_DEF(platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_audio_dma.0.auto")));
static struct snd_soc_dai_link cz_dai_rt5650[] = {
{
.name = "amd-rt5645-play",
.stream_name = "RT5645_AIF1",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.init = cz_init,
.ops = &cz_aif1_ops,
SND_SOC_DAILINK_REG(designware1, codec, platform),
},
{
.name = "amd-rt5645-cap",
.stream_name = "RT5645_AIF1",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.ops = &cz_aif1_ops,
SND_SOC_DAILINK_REG(designware2, codec, platform),
},
};
static const struct snd_soc_dapm_widget cz_widgets[] = {
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
};
static const struct snd_soc_dapm_route cz_audio_route[] = {
{"Headphones", NULL, "HPOL"},
{"Headphones", NULL, "HPOR"},
{"RECMIXL", NULL, "Headset Mic"},
{"RECMIXR", NULL, "Headset Mic"},
{"Speakers", NULL, "SPOL"},
{"Speakers", NULL, "SPOR"},
{"DMIC L2", NULL, "Int Mic"},
{"DMIC R2", NULL, "Int Mic"},
};
static const struct snd_kcontrol_new cz_mc_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphones"),
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
};
static struct snd_soc_card cz_card = {
.name = "acprt5650",
.owner = THIS_MODULE,
.dai_link = cz_dai_rt5650,
.num_links = ARRAY_SIZE(cz_dai_rt5650),
.dapm_widgets = cz_widgets,
.num_dapm_widgets = ARRAY_SIZE(cz_widgets),
.dapm_routes = cz_audio_route,
.num_dapm_routes = ARRAY_SIZE(cz_audio_route),
.controls = cz_mc_controls,
.num_controls = ARRAY_SIZE(cz_mc_controls),
};
static int cz_probe(struct platform_device *pdev)
{
int ret;
struct snd_soc_card *card;
card = &cz_card;
cz_card.dev = &pdev->dev;
platform_set_drvdata(pdev, card);
ret = devm_snd_soc_register_card(&pdev->dev, &cz_card);
if (ret) {
dev_err(&pdev->dev,
"devm_snd_soc_register_card(%s) failed: %d\n",
cz_card.name, ret);
return ret;
}
return 0;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id cz_audio_acpi_match[] = {
{ "AMDI1002", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, cz_audio_acpi_match);
#endif
static struct platform_driver cz_pcm_driver = {
.driver = {
.name = "cz-rt5645",
.acpi_match_table = ACPI_PTR(cz_audio_acpi_match),
.pm = &snd_soc_pm_ops,
},
.probe = cz_probe,
};
module_platform_driver(cz_pcm_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("cz-rt5645 audio support");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp-rt5645.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
//
/* ACP machine configuration module */
#include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/dmi.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "../sof/amd/acp.h"
#include "mach-config.h"
static int acp_quirk_data;
static const struct config_entry config_table[] = {
{
.flags = FLAG_AMD_SOF,
.device = ACP_PCI_DEV_ID,
.dmi_table = (const struct dmi_system_id []) {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "AMD"),
DMI_MATCH(DMI_PRODUCT_NAME, "Majolica-CZN"),
},
},
{}
},
},
{
.flags = FLAG_AMD_SOF,
.device = ACP_PCI_DEV_ID,
.dmi_table = (const struct dmi_system_id []) {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Google"),
},
},
{}
},
},
{
.flags = FLAG_AMD_SOF,
.device = ACP_PCI_DEV_ID,
.dmi_table = (const struct dmi_system_id []) {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
DMI_MATCH(DMI_PRODUCT_FAMILY, "Sephiroth"),
},
},
{}
},
},
};
int snd_amd_acp_find_config(struct pci_dev *pci)
{
const struct config_entry *table = config_table;
u16 device = pci->device;
int i;
/* Do not enable FLAGS on older platforms with Rev id zero */
if (!pci->revision)
return 0;
for (i = 0; i < ARRAY_SIZE(config_table); i++, table++) {
if (table->device != device)
continue;
if (table->dmi_table && !dmi_check_system(table->dmi_table))
continue;
acp_quirk_data = table->flags;
return table->flags;
}
return 0;
}
EXPORT_SYMBOL(snd_amd_acp_find_config);
static struct snd_soc_acpi_codecs amp_rt1019 = {
.num_codecs = 1,
.codecs = {"10EC1019"}
};
static struct snd_soc_acpi_codecs amp_max = {
.num_codecs = 1,
.codecs = {"MX98360A"}
};
static struct snd_soc_acpi_codecs amp_max98388 = {
.num_codecs = 1,
.codecs = {"ADS8388"}
};
struct snd_soc_acpi_mach snd_soc_acpi_amd_sof_machines[] = {
{
.id = "10EC5682",
.drv_name = "rt5682-rt1019",
.pdata = (void *)&acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_rt1019,
.fw_filename = "sof-rn.ri",
.sof_tplg_filename = "sof-rn-rt5682-rt1019.tplg",
},
{
.id = "10EC5682",
.drv_name = "rt5682-max",
.pdata = (void *)&acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_max,
.fw_filename = "sof-rn.ri",
.sof_tplg_filename = "sof-rn-rt5682-max98360.tplg",
},
{
.id = "RTL5682",
.drv_name = "rt5682s-max",
.pdata = (void *)&acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_max,
.fw_filename = "sof-rn.ri",
.sof_tplg_filename = "sof-rn-rt5682-max98360.tplg",
},
{
.id = "RTL5682",
.drv_name = "rt5682s-rt1019",
.pdata = (void *)&acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_rt1019,
.fw_filename = "sof-rn.ri",
.sof_tplg_filename = "sof-rn-rt5682-rt1019.tplg",
},
{
.id = "AMDI1019",
.drv_name = "renoir-dsp",
.pdata = (void *)&acp_quirk_data,
.fw_filename = "sof-rn.ri",
.sof_tplg_filename = "sof-acp.tplg",
},
{},
};
EXPORT_SYMBOL(snd_soc_acpi_amd_sof_machines);
struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[] = {
{
.id = "NVTN2020",
.drv_name = "nau8821-max",
.pdata = &acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_max98388,
.fw_filename = "sof-vangogh.ri",
.sof_tplg_filename = "sof-vangogh-nau8821-max.tplg",
},
{},
};
EXPORT_SYMBOL(snd_soc_acpi_amd_vangogh_sof_machines);
struct snd_soc_acpi_mach snd_soc_acpi_amd_rmb_sof_machines[] = {
{
.id = "AMDI1019",
.drv_name = "rmb-dsp",
.pdata = &acp_quirk_data,
.fw_filename = "sof-rmb.ri",
.sof_tplg_filename = "sof-acp-rmb.tplg",
},
{
.id = "10508825",
.drv_name = "nau8825-max",
.pdata = &acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_max,
.fw_filename = "sof-rmb.ri",
.sof_tplg_filename = "sof-rmb-nau8825-max98360.tplg",
},
{
.id = "RTL5682",
.drv_name = "rt5682s-hs-rt1019",
.pdata = &acp_quirk_data,
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_rt1019,
.fw_filename = "sof-rmb.ri",
.sof_tplg_filename = "sof-rmb-rt5682s-rt1019.tplg",
},
{},
};
EXPORT_SYMBOL(snd_soc_acpi_amd_rmb_sof_machines);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/amd/acp-config.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Machine driver for AMD Stoney platform using ES8336 Codec
*
* Copyright 2022 Advanced Micro Devices, Inc.
*/
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/dmi.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/acpi.h>
#include "acp.h"
#define DUAL_CHANNEL 2
#define DRV_NAME "acp2x_mach"
#define ST_JADEITE 1
#define ES8336_PLL_FREQ (48000 * 256)
static unsigned long acp2x_machine_id;
static struct snd_soc_jack st_jack;
static struct device *codec_dev;
static struct gpio_desc *gpio_pa;
static int sof_es8316_speaker_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
if (SND_SOC_DAPM_EVENT_ON(event))
gpiod_set_value_cansleep(gpio_pa, true);
else
gpiod_set_value_cansleep(gpio_pa, false);
return 0;
}
static struct snd_soc_jack_pin st_es8316_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int st_es8336_init(struct snd_soc_pcm_runtime *rtd)
{
int ret;
struct snd_soc_card *card;
struct snd_soc_component *codec;
codec = asoc_rtd_to_codec(rtd, 0)->component;
card = rtd->card;
ret = snd_soc_card_jack_new_pins(card, "Headset", SND_JACK_HEADSET | SND_JACK_BTN_0,
&st_jack, st_es8316_jack_pins,
ARRAY_SIZE(st_es8316_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(st_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
ret = snd_soc_component_set_jack(codec, &st_jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return 0;
}
static const unsigned int st_channels[] = {
DUAL_CHANNEL,
};
static const unsigned int st_rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list st_constraints_rates = {
.count = ARRAY_SIZE(st_rates),
.list = st_rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list st_constraints_channels = {
.count = ARRAY_SIZE(st_channels),
.list = st_channels,
.mask = 0,
};
static int st_es8336_codec_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_card *card;
struct acp_platform_info *machine;
struct snd_soc_dai *codec_dai;
int ret;
runtime = substream->runtime;
rtd = asoc_substream_to_rtd(substream);
card = rtd->card;
machine = snd_soc_card_get_drvdata(card);
codec_dai = asoc_rtd_to_codec(rtd, 0);
ret = snd_soc_dai_set_sysclk(codec_dai, 0, ES8336_PLL_FREQ, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
return ret;
}
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&st_constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&st_constraints_rates);
machine->play_i2s_instance = I2S_MICSP_INSTANCE;
machine->cap_i2s_instance = I2S_MICSP_INSTANCE;
machine->capture_channel = CAP_CHANNEL0;
return 0;
}
static const struct snd_soc_ops st_es8336_ops = {
.startup = st_es8336_codec_startup,
};
SND_SOC_DAILINK_DEF(designware1,
DAILINK_COMP_ARRAY(COMP_CPU("designware-i2s.2.auto")));
SND_SOC_DAILINK_DEF(codec,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-ESSX8336:00", "ES8316 HiFi")));
SND_SOC_DAILINK_DEF(platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_audio_dma.1.auto")));
static struct snd_soc_dai_link st_dai_es8336[] = {
{
.name = "amdes8336",
.stream_name = "ES8336 HiFi Play",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.trigger_stop = SND_SOC_TRIGGER_ORDER_LDC,
.dpcm_capture = 1,
.dpcm_playback = 1,
.init = st_es8336_init,
.ops = &st_es8336_ops,
SND_SOC_DAILINK_REG(designware1, codec, platform),
},
};
static const struct snd_soc_dapm_widget st_widgets[] = {
SND_SOC_DAPM_SPK("Speaker", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Internal Mic", NULL),
SND_SOC_DAPM_SUPPLY("Speaker Power", SND_SOC_NOPM, 0, 0,
sof_es8316_speaker_power_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
};
static const struct snd_soc_dapm_route st_audio_route[] = {
{"Speaker", NULL, "HPOL"},
{"Speaker", NULL, "HPOR"},
{"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"},
{"MIC1", NULL, "Headset Mic"},
{"MIC2", NULL, "Internal Mic"},
{"Speaker", NULL, "Speaker Power"},
};
static const struct snd_kcontrol_new st_mc_controls[] = {
SOC_DAPM_PIN_SWITCH("Speaker"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Internal Mic"),
};
static const struct acpi_gpio_params pa_enable_gpio = { 0, 0, false };
static const struct acpi_gpio_mapping acpi_es8336_gpios[] = {
{ "pa-enable-gpios", &pa_enable_gpio, 1 },
{ }
};
static int st_es8336_late_probe(struct snd_soc_card *card)
{
struct acpi_device *adev;
int ret;
adev = acpi_dev_get_first_match_dev("ESSX8336", NULL, -1);
if (!adev)
return -ENODEV;
codec_dev = acpi_get_first_physical_node(adev);
acpi_dev_put(adev);
if (!codec_dev)
dev_err(card->dev, "can not find codec dev\n");
ret = devm_acpi_dev_add_driver_gpios(codec_dev, acpi_es8336_gpios);
if (ret)
dev_warn(card->dev, "Failed to add driver gpios\n");
gpio_pa = gpiod_get_optional(codec_dev, "pa-enable", GPIOD_OUT_LOW);
if (IS_ERR(gpio_pa)) {
ret = dev_err_probe(card->dev, PTR_ERR(gpio_pa),
"could not get pa-enable GPIO\n");
put_device(codec_dev);
return ret;
}
return 0;
}
static struct snd_soc_card st_card = {
.name = "acpes8336",
.owner = THIS_MODULE,
.dai_link = st_dai_es8336,
.num_links = ARRAY_SIZE(st_dai_es8336),
.dapm_widgets = st_widgets,
.num_dapm_widgets = ARRAY_SIZE(st_widgets),
.dapm_routes = st_audio_route,
.num_dapm_routes = ARRAY_SIZE(st_audio_route),
.controls = st_mc_controls,
.num_controls = ARRAY_SIZE(st_mc_controls),
.late_probe = st_es8336_late_probe,
};
static int st_es8336_quirk_cb(const struct dmi_system_id *id)
{
acp2x_machine_id = ST_JADEITE;
return 1;
}
static const struct dmi_system_id st_es8336_quirk_table[] = {
{
.callback = st_es8336_quirk_cb,
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"),
},
},
{
.callback = st_es8336_quirk_cb,
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"),
},
},
{
.callback = st_es8336_quirk_cb,
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"),
},
},
{}
};
static int st_es8336_probe(struct platform_device *pdev)
{
int ret;
struct snd_soc_card *card;
struct acp_platform_info *machine;
machine = devm_kzalloc(&pdev->dev, sizeof(struct acp_platform_info), GFP_KERNEL);
if (!machine)
return -ENOMEM;
dmi_check_system(st_es8336_quirk_table);
switch (acp2x_machine_id) {
case ST_JADEITE:
card = &st_card;
st_card.dev = &pdev->dev;
break;
default:
return -ENODEV;
}
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, &st_card);
if (ret) {
return dev_err_probe(&pdev->dev, ret,
"devm_snd_soc_register_card(%s) failed\n",
card->name);
}
return 0;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id st_audio_acpi_match[] = {
{"AMDI8336", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, st_audio_acpi_match);
#endif
static struct platform_driver st_mach_driver = {
.driver = {
.name = "st-es8316",
.acpi_match_table = ACPI_PTR(st_audio_acpi_match),
.pm = &snd_soc_pm_ops,
},
.probe = st_es8336_probe,
};
module_platform_driver(st_mach_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("st-es8316 audio support");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp-es8336.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AMD ALSA SoC PCM Driver for ACP 2.x
*
* Copyright 2014-2015 Advanced Micro Devices, Inc.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <drm/amd_asic_type.h>
#include "acp.h"
#define DRV_NAME "acp_audio_dma"
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 2
#define PLAYBACK_MAX_PERIOD_SIZE 16384
#define PLAYBACK_MIN_PERIOD_SIZE 1024
#define CAPTURE_MIN_NUM_PERIODS 2
#define CAPTURE_MAX_NUM_PERIODS 2
#define CAPTURE_MAX_PERIOD_SIZE 16384
#define CAPTURE_MIN_PERIOD_SIZE 1024
#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
#define MIN_BUFFER MAX_BUFFER
#define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
#define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE
#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
#define ST_MIN_BUFFER ST_MAX_BUFFER
#define DRV_NAME "acp_audio_dma"
bool acp_bt_uart_enable = true;
EXPORT_SYMBOL(acp_bt_uart_enable);
static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = ST_MAX_BUFFER,
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.buffer_bytes_max = ST_MAX_BUFFER,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
{
return readl(acp_mmio + (reg * 4));
}
static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
{
writel(val, acp_mmio + (reg * 4));
}
/*
* Configure a given dma channel parameters - enable/disable,
* number of descriptors, priority
*/
static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
u16 dscr_strt_idx, u16 num_dscrs,
enum acp_dma_priority_level priority_level)
{
u32 dma_ctrl;
/* disable the channel run field */
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/* program a DMA channel with first descriptor to be processed. */
acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
& dscr_strt_idx),
acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
/*
* program a DMA channel with the number of descriptors to be
* processed in the transfer
*/
acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
/* set DMA channel priority */
acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
}
/* Initialize a dma descriptor in SRAM based on descriptor information passed */
static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
u16 descr_idx,
acp_dma_dscr_transfer_t *descr_info)
{
u32 sram_offset;
sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
/* program the source base address. */
acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* program the destination base address. */
acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* program the number of bytes to be transferred for this descriptor. */
acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
}
static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)
{
u32 dma_ctrl;
int ret;
/* clear the reset bit */
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/* check the reset bit before programming configuration registers */
ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),
dma_ctrl,
!(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),
100, ACP_DMA_RESET_TIME);
if (ret < 0)
pr_err("Failed to clear reset of channel : %d\n", ch_num);
}
/*
* Initialize the DMA descriptor information for transfer between
* system memory <-> ACP SRAM
*/
static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
u32 size, int direction,
u32 pte_offset, u16 ch,
u32 sram_bank, u16 dma_dscr_idx,
u32 asic_type)
{
u16 i;
acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
dmadscr[i].xfer_val = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
dma_dscr_idx = dma_dscr_idx + i;
dmadscr[i].dest = sram_bank + (i * (size / 2));
dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) + (i * (size / 2));
switch (asic_type) {
case CHIP_STONEY:
dmadscr[i].xfer_val |=
(ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) |
(size / 2);
break;
default:
dmadscr[i].xfer_val |=
(ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) |
(size / 2);
}
} else {
dma_dscr_idx = dma_dscr_idx + i;
dmadscr[i].src = sram_bank + (i * (size / 2));
dmadscr[i].dest =
ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
(pte_offset * SZ_4K) + (i * (size / 2));
switch (asic_type) {
case CHIP_STONEY:
dmadscr[i].xfer_val |=
(ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
(size / 2);
break;
default:
dmadscr[i].xfer_val |=
(ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
(size / 2);
}
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
&dmadscr[i]);
}
pre_config_reset(acp_mmio, ch);
config_acp_dma_channel(acp_mmio, ch,
dma_dscr_idx - 1,
NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL);
}
/*
* Initialize the DMA descriptor information for transfer between
* ACP SRAM <-> I2S
*/
static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
int direction, u32 sram_bank,
u16 destination, u16 ch,
u16 dma_dscr_idx, u32 asic_type)
{
u16 i;
acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
dmadscr[i].xfer_val = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
dma_dscr_idx = dma_dscr_idx + i;
dmadscr[i].src = sram_bank + (i * (size / 2));
/* dmadscr[i].dest is unused by hardware. */
dmadscr[i].dest = 0;
dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
(size / 2);
} else {
dma_dscr_idx = dma_dscr_idx + i;
/* dmadscr[i].src is unused by hardware. */
dmadscr[i].src = 0;
dmadscr[i].dest =
sram_bank + (i * (size / 2));
dmadscr[i].xfer_val |= BIT(22) |
(destination << 16) | (size / 2);
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
&dmadscr[i]);
}
pre_config_reset(acp_mmio, ch);
/* Configure the DMA channel with the above descriptor */
config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
NUM_DSCRS_PER_CHANNEL,
ACP_DMA_PRIORITY_LEVEL_NORMAL);
}
/* Create page table entries in ACP SRAM for the allocated memory */
static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
u16 num_of_pages, u32 pte_offset)
{
u16 page_idx;
u32 low;
u32 high;
u32 offset;
offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
acp_reg_write((offset + (page_idx * 8)),
acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
low = lower_32_bits(addr);
high = upper_32_bits(addr);
acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* Load the High address of page int ACP SRAM through SRBM */
acp_reg_write((offset + (page_idx * 8) + 4),
acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
/* page enable in ACP */
high |= BIT(31);
acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
/* Move to next physically contiguous page */
addr += PAGE_SIZE;
}
}
static void config_acp_dma(void __iomem *acp_mmio,
struct audio_substream_data *rtd,
u32 asic_type)
{
u16 ch_acp_sysmem, ch_acp_i2s;
acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,
rtd->pte_offset);
if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
ch_acp_sysmem = rtd->ch1;
ch_acp_i2s = rtd->ch2;
} else {
ch_acp_i2s = rtd->ch1;
ch_acp_sysmem = rtd->ch2;
}
/* Configure System memory <-> ACP SRAM DMA descriptors */
set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
rtd->direction, rtd->pte_offset,
ch_acp_sysmem, rtd->sram_bank,
rtd->dma_dscr_idx_1, asic_type);
/* Configure ACP SRAM <-> I2S DMA descriptors */
set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
rtd->direction, rtd->sram_bank,
rtd->destination, ch_acp_i2s,
rtd->dma_dscr_idx_2, asic_type);
}
static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
u16 cap_channel)
{
u32 val, ch_reg, imr_reg, res_reg;
switch (cap_channel) {
case CAP_CHANNEL1:
ch_reg = mmACP_I2SMICSP_RER1;
res_reg = mmACP_I2SMICSP_RCR1;
imr_reg = mmACP_I2SMICSP_IMR1;
break;
case CAP_CHANNEL0:
default:
ch_reg = mmACP_I2SMICSP_RER0;
res_reg = mmACP_I2SMICSP_RCR0;
imr_reg = mmACP_I2SMICSP_IMR0;
break;
}
val = acp_reg_read(acp_mmio,
mmACP_I2S_16BIT_RESOLUTION_EN);
if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
acp_reg_write(0x0, acp_mmio, ch_reg);
/* Set 16bit resolution on capture */
acp_reg_write(0x2, acp_mmio, res_reg);
}
val = acp_reg_read(acp_mmio, imr_reg);
val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
acp_reg_write(val, acp_mmio, imr_reg);
acp_reg_write(0x1, acp_mmio, ch_reg);
}
static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
u16 cap_channel)
{
u32 val, ch_reg, imr_reg;
switch (cap_channel) {
case CAP_CHANNEL1:
imr_reg = mmACP_I2SMICSP_IMR1;
ch_reg = mmACP_I2SMICSP_RER1;
break;
case CAP_CHANNEL0:
default:
imr_reg = mmACP_I2SMICSP_IMR0;
ch_reg = mmACP_I2SMICSP_RER0;
break;
}
val = acp_reg_read(acp_mmio, imr_reg);
val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
acp_reg_write(val, acp_mmio, imr_reg);
acp_reg_write(0x0, acp_mmio, ch_reg);
}
/* Start a given DMA channel transfer */
static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)
{
u32 dma_ctrl;
/* read the dma control register and disable the channel run field */
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/* Invalidating the DAGB cache */
acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
/*
* configure the DMA channel and start the DMA transfer
* set dmachrun bit to start the transfer and enable the
* interrupt on completion of the dma transfer
*/
dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
switch (ch_num) {
case ACP_TO_I2S_DMA_CH_NUM:
case I2S_TO_ACP_DMA_CH_NUM:
case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
case ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM:
dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
break;
default:
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
break;
}
/* enable for ACP to SRAM DMA channel */
if (is_circular == true)
dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
else
dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
}
/* Stop a given DMA channel transfer */
static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
{
u32 dma_ctrl;
u32 dma_ch_sts;
u32 count = ACP_DMA_RESET_TIME;
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
/*
* clear the dma control register fields before writing zero
* in reset bit
*/
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
if (dma_ch_sts & BIT(ch_num)) {
/*
* set the reset bit for this channel to stop the dma
* transfer
*/
dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
}
/* check the channel status bit for some time and return the status */
while (true) {
dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
if (!(dma_ch_sts & BIT(ch_num))) {
/*
* clear the reset flag after successfully stopping
* the dma transfer and break from the loop
*/
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
+ ch_num);
break;
}
if (--count == 0) {
pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
return -ETIMEDOUT;
}
udelay(100);
}
return 0;
}
static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
bool power_on)
{
u32 val, req_reg, sts_reg, sts_reg_mask;
u32 loops = 1000;
if (bank < 32) {
req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
sts_reg_mask = 0xFFFFFFFF;
} else {
bank -= 32;
req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
sts_reg_mask = 0x0000FFFF;
}
val = acp_reg_read(acp_mmio, req_reg);
if (val & (1 << bank)) {
/* bank is in off state */
if (power_on == true)
/* request to on */
val &= ~(1 << bank);
else
/* request to off */
return;
} else {
/* bank is in on state */
if (power_on == false)
/* request to off */
val |= 1 << bank;
else
/* request to on */
return;
}
acp_reg_write(val, acp_mmio, req_reg);
while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
if (!loops--) {
pr_err("ACP SRAM bank %d state change failed\n", bank);
break;
}
cpu_relax();
}
}
/* Initialize and bring ACP hardware to default state. */
static int acp_init(void __iomem *acp_mmio, u32 asic_type)
{
u16 bank;
u32 val, count, sram_pte_offset;
/* Assert Soft reset of ACP */
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
val |= ACP_SOFT_RESET__SoftResetAud_MASK;
acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
/* Enable clock to ACP and wait until the clock is enabled */
val = acp_reg_read(acp_mmio, mmACP_CONTROL);
val = val | ACP_CONTROL__ClkEn_MASK;
acp_reg_write(val, acp_mmio, mmACP_CONTROL);
count = ACP_CLOCK_EN_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_STATUS);
if (val & (u32)0x1)
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
/* Deassert the SOFT RESET flags */
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
/* For BT instance change pins from UART to BT */
if (!acp_bt_uart_enable) {
val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
val |= ACP_BT_UART_PAD_SELECT_MASK;
acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
}
/* initialize Onion control DAGB register */
acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
mmACP_AXI2DAGB_ONION_CNTL);
/* initialize Garlic control DAGB registers */
acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
mmACP_AXI2DAGB_GARLIC_CNTL);
sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
mmACP_DAGB_PAGE_SIZE_GRP_1);
acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
mmACP_DMA_DESC_BASE_ADDR);
/* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */
acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
/*
* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
* Now, turn off all of them. This can't be done in 'poweron' of
* ACP pm domain, as this requires ACP to be initialized.
* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks is ON.
* Setting SRAM bank state code skipped for STONEY platform.
*/
if (asic_type != CHIP_STONEY) {
for (bank = 1; bank < 48; bank++)
acp_set_sram_bank_state(acp_mmio, bank, false);
}
return 0;
}
/* Deinitialize ACP */
static int acp_deinit(void __iomem *acp_mmio)
{
u32 val;
u32 count;
/* Assert Soft reset of ACP */
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
val |= ACP_SOFT_RESET__SoftResetAud_MASK;
acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
/* Disable ACP clock */
val = acp_reg_read(acp_mmio, mmACP_CONTROL);
val &= ~ACP_CONTROL__ClkEn_MASK;
acp_reg_write(val, acp_mmio, mmACP_CONTROL);
count = ACP_CLOCK_EN_TIME_OUT_VALUE;
while (true) {
val = acp_reg_read(acp_mmio, mmACP_STATUS);
if (!(val & (u32)0x1))
break;
if (--count == 0) {
pr_err("Failed to reset ACP\n");
return -ETIMEDOUT;
}
udelay(100);
}
return 0;
}
/* ACP DMA irq handler routine for playback, capture usecases */
static irqreturn_t dma_irq_handler(int irq, void *arg)
{
u16 dscr_idx;
u32 intr_flag, ext_intr_status;
struct audio_drv_data *irq_data;
void __iomem *acp_mmio;
struct device *dev = arg;
bool valid_irq = false;
irq_data = dev_get_drvdata(dev);
acp_mmio = irq_data->acp_mmio;
ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
intr_flag = (((ext_intr_status &
ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
valid_irq = true;
snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if ((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) != 0) {
valid_irq = true;
snd_pcm_period_elapsed(irq_data->play_i2s_micsp_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
valid_irq = true;
snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
acp_reg_write((intr_flag &
BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
valid_irq = true;
if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==
CAPTURE_START_DMA_DESCR_CH15)
dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
else
dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
1, 0);
acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
valid_irq = true;
if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==
CAPTURE_START_DMA_DESCR_CH11)
dscr_idx = CAPTURE_END_DMA_DESCR_CH10;
else
dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
config_acp_dma_channel(acp_mmio,
ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
dscr_idx, 1, 0);
acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
false);
snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
acp_reg_write((intr_flag &
BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
if (valid_irq)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static int acp_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
u16 bank;
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
struct audio_substream_data *adata =
kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
if (!adata)
return -ENOMEM;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (intr_data->asic_type) {
case CHIP_STONEY:
runtime->hw = acp_st_pcm_hardware_playback;
break;
default:
runtime->hw = acp_pcm_hardware_playback;
}
} else {
switch (intr_data->asic_type) {
case CHIP_STONEY:
runtime->hw = acp_st_pcm_hardware_capture;
break;
default:
runtime->hw = acp_pcm_hardware_capture;
}
}
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(adata);
return ret;
}
adata->acp_mmio = intr_data->acp_mmio;
runtime->private_data = adata;
/*
* Enable ACP irq, when neither playback or capture streams are
* active by the time when a new stream is being opened.
* This enablement is not required for another stream, if current
* stream is not closed
*/
if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
!intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream &&
!intr_data->play_i2s_micsp_stream)
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/*
* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks is ON.
* Setting SRAM bank state code skipped for STONEY platform.
*/
if (intr_data->asic_type != CHIP_STONEY) {
for (bank = 1; bank <= 4; bank++)
acp_set_sram_bank_state(intr_data->acp_mmio,
bank, true);
}
} else {
if (intr_data->asic_type != CHIP_STONEY) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(intr_data->acp_mmio,
bank, true);
}
}
return 0;
}
static int acp_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
uint64_t size;
u32 val = 0;
struct snd_pcm_runtime *runtime;
struct audio_substream_data *rtd;
struct snd_soc_pcm_runtime *prtd = asoc_substream_to_rtd(substream);
struct audio_drv_data *adata = dev_get_drvdata(component->dev);
struct snd_soc_card *card = prtd->card;
struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
runtime = substream->runtime;
rtd = runtime->private_data;
if (WARN_ON(!rtd))
return -EINVAL;
if (pinfo) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
rtd->i2s_instance = pinfo->play_i2s_instance;
} else {
rtd->i2s_instance = pinfo->cap_i2s_instance;
rtd->capture_channel = pinfo->capture_channel;
}
}
if (adata->asic_type == CHIP_STONEY) {
val = acp_reg_read(adata->acp_mmio,
mmACP_I2S_16BIT_RESOLUTION_EN);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
break;
case I2S_MICSP_INSTANCE:
val |= ACP_I2S_MICSP_16BIT_RESOLUTION_EN;
break;
case I2S_SP_INSTANCE:
default:
val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
break;
case I2S_MICSP_INSTANCE:
case I2S_SP_INSTANCE:
default:
val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
}
}
acp_reg_write(val, adata->acp_mmio,
mmACP_I2S_16BIT_RESOLUTION_EN);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
rtd->destination = TO_BLUETOOTH;
rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
rtd->byte_cnt_high_reg_offset =
mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
rtd->byte_cnt_low_reg_offset =
mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
adata->play_i2sbt_stream = substream;
break;
case I2S_MICSP_INSTANCE:
switch (adata->asic_type) {
case CHIP_STONEY:
rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
break;
default:
rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
}
rtd->ch1 = SYSRAM_TO_ACP_MICSP_INSTANCE_CH_NUM;
rtd->ch2 = ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM;
rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
rtd->destination = TO_ACP_I2S_2;
rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH4;
rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH5;
rtd->byte_cnt_high_reg_offset =
mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH;
rtd->byte_cnt_low_reg_offset =
mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW;
adata->play_i2s_micsp_stream = substream;
break;
case I2S_SP_INSTANCE:
default:
switch (adata->asic_type) {
case CHIP_STONEY:
rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
break;
default:
rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
}
rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
rtd->destination = TO_ACP_I2S_1;
rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
rtd->byte_cnt_high_reg_offset =
mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
rtd->byte_cnt_low_reg_offset =
mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
adata->play_i2ssp_stream = substream;
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
rtd->destination = FROM_BLUETOOTH;
rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
rtd->byte_cnt_high_reg_offset =
mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
rtd->byte_cnt_low_reg_offset =
mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11;
adata->capture_i2sbt_stream = substream;
break;
case I2S_MICSP_INSTANCE:
case I2S_SP_INSTANCE:
default:
rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;
rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;
switch (adata->asic_type) {
case CHIP_STONEY:
rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
break;
default:
rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
}
rtd->destination = FROM_ACP_I2S_1;
rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
rtd->byte_cnt_high_reg_offset =
mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
rtd->byte_cnt_low_reg_offset =
mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15;
adata->capture_i2ssp_stream = substream;
}
}
size = params_buffer_bytes(params);
acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
/* Save for runtime private data */
rtd->dma_addr = runtime->dma_addr;
rtd->order = get_order(size);
/* Fill the page table entries in ACP SRAM */
rtd->size = size;
rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
rtd->direction = substream->stream;
config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
return 0;
}
static u64 acp_get_byte_count(struct audio_substream_data *rtd)
{
union acp_dma_count byte_count;
byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
rtd->byte_cnt_high_reg_offset);
byte_count.bcount.low = acp_reg_read(rtd->acp_mmio,
rtd->byte_cnt_low_reg_offset);
return byte_count.bytescount;
}
static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
u32 buffersize;
u32 pos = 0;
u64 bytescount = 0;
u16 dscr;
u32 period_bytes, delay;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
struct audio_drv_data *adata = dev_get_drvdata(component->dev);
if (!rtd)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
period_bytes = frames_to_bytes(runtime, runtime->period_size);
bytescount = acp_get_byte_count(rtd);
if (bytescount >= rtd->bytescount)
bytescount -= rtd->bytescount;
if (bytescount < period_bytes) {
pos = 0;
} else {
dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);
if (dscr == rtd->dma_dscr_idx_1)
pos = period_bytes;
else
pos = 0;
}
if (bytescount > 0) {
delay = do_div(bytescount, period_bytes);
adata->delay += bytes_to_frames(runtime, delay);
}
} else {
buffersize = frames_to_bytes(runtime, runtime->buffer_size);
bytescount = acp_get_byte_count(rtd);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
}
return bytes_to_frames(runtime, pos);
}
static snd_pcm_sframes_t acp_dma_delay(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct audio_drv_data *adata = dev_get_drvdata(component->dev);
snd_pcm_sframes_t delay = adata->delay;
adata->delay = 0;
return delay;
}
static int acp_dma_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
u16 ch_acp_sysmem, ch_acp_i2s;
if (!rtd)
return -EINVAL;
if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
ch_acp_sysmem = rtd->ch1;
ch_acp_i2s = rtd->ch2;
} else {
ch_acp_i2s = rtd->ch1;
ch_acp_sysmem = rtd->ch2;
}
config_acp_dma_channel(rtd->acp_mmio,
ch_acp_sysmem,
rtd->dma_dscr_idx_1,
NUM_DSCRS_PER_CHANNEL, 0);
config_acp_dma_channel(rtd->acp_mmio,
ch_acp_i2s,
rtd->dma_dscr_idx_2,
NUM_DSCRS_PER_CHANNEL, 0);
return 0;
}
static int acp_dma_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
int ret;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
if (!rtd)
return -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
rtd->bytescount = acp_get_byte_count(rtd);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
if (rtd->capture_channel == CAP_CHANNEL0) {
acp_dma_cap_channel_disable(rtd->acp_mmio,
CAP_CHANNEL1);
acp_dma_cap_channel_enable(rtd->acp_mmio,
CAP_CHANNEL0);
}
if (rtd->capture_channel == CAP_CHANNEL1) {
acp_dma_cap_channel_disable(rtd->acp_mmio,
CAP_CHANNEL0);
acp_dma_cap_channel_enable(rtd->acp_mmio,
CAP_CHANNEL1);
}
acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
} else {
acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
}
ret = 0;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
acp_dma_stop(rtd->acp_mmio, rtd->ch2);
ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int acp_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct audio_drv_data *adata = dev_get_drvdata(component->dev);
struct device *parent = component->dev->parent;
switch (adata->asic_type) {
case CHIP_STONEY:
snd_pcm_set_managed_buffer_all(rtd->pcm,
SNDRV_DMA_TYPE_DEV,
parent,
ST_MIN_BUFFER,
ST_MAX_BUFFER);
break;
default:
snd_pcm_set_managed_buffer_all(rtd->pcm,
SNDRV_DMA_TYPE_DEV,
parent,
MIN_BUFFER,
MAX_BUFFER);
break;
}
return 0;
}
static int acp_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
u16 bank;
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
struct audio_drv_data *adata = dev_get_drvdata(component->dev);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
adata->play_i2sbt_stream = NULL;
break;
case I2S_MICSP_INSTANCE:
adata->play_i2s_micsp_stream = NULL;
break;
case I2S_SP_INSTANCE:
default:
adata->play_i2ssp_stream = NULL;
/*
* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks
* is ON.Setting SRAM bank state code skipped for STONEY
* platform. Added condition checks for Carrizo platform
* only.
*/
if (adata->asic_type != CHIP_STONEY) {
for (bank = 1; bank <= 4; bank++)
acp_set_sram_bank_state(adata->acp_mmio,
bank, false);
}
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
adata->capture_i2sbt_stream = NULL;
break;
case I2S_MICSP_INSTANCE:
case I2S_SP_INSTANCE:
default:
adata->capture_i2ssp_stream = NULL;
if (adata->asic_type != CHIP_STONEY) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(adata->acp_mmio,
bank, false);
}
}
}
/*
* Disable ACP irq, when the current stream is being closed and
* another stream is also not active.
*/
if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
!adata->play_i2sbt_stream && !adata->capture_i2sbt_stream &&
!adata->play_i2s_micsp_stream)
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
kfree(rtd);
return 0;
}
static const struct snd_soc_component_driver acp_asoc_platform = {
.name = DRV_NAME,
.open = acp_dma_open,
.close = acp_dma_close,
.hw_params = acp_dma_hw_params,
.trigger = acp_dma_trigger,
.pointer = acp_dma_pointer,
.delay = acp_dma_delay,
.prepare = acp_dma_prepare,
.pcm_construct = acp_dma_new,
};
static int acp_audio_probe(struct platform_device *pdev)
{
int status, irq;
struct audio_drv_data *audio_drv_data;
const u32 *pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "Missing platform data\n");
return -ENODEV;
}
audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
GFP_KERNEL);
if (!audio_drv_data)
return -ENOMEM;
audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(audio_drv_data->acp_mmio))
return PTR_ERR(audio_drv_data->acp_mmio);
/*
* The following members gets populated in device 'open'
* function. Till then interrupts are disabled in 'acp_init'
* and device doesn't generate any interrupts.
*/
audio_drv_data->play_i2ssp_stream = NULL;
audio_drv_data->capture_i2ssp_stream = NULL;
audio_drv_data->play_i2sbt_stream = NULL;
audio_drv_data->capture_i2sbt_stream = NULL;
audio_drv_data->play_i2s_micsp_stream = NULL;
audio_drv_data->asic_type = *pdata;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENODEV;
status = devm_request_irq(&pdev->dev, irq, dma_irq_handler,
0, "ACP_IRQ", &pdev->dev);
if (status) {
dev_err(&pdev->dev, "ACP IRQ request failed\n");
return status;
}
dev_set_drvdata(&pdev->dev, audio_drv_data);
/* Initialize the ACP */
status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
if (status) {
dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
return status;
}
status = devm_snd_soc_register_component(&pdev->dev,
&acp_asoc_platform, NULL, 0);
if (status != 0) {
dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
return status;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return status;
}
static void acp_audio_remove(struct platform_device *pdev)
{
int status;
struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
status = acp_deinit(adata->acp_mmio);
if (status)
dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
pm_runtime_disable(&pdev->dev);
}
static int acp_pcm_resume(struct device *dev)
{
u16 bank;
int status;
struct audio_substream_data *rtd;
struct audio_drv_data *adata = dev_get_drvdata(dev);
status = acp_init(adata->acp_mmio, adata->asic_type);
if (status) {
dev_err(dev, "ACP Init failed status:%d\n", status);
return status;
}
if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
/*
* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks is ON.
* Setting SRAM bank state code skipped for STONEY platform.
*/
if (adata->asic_type != CHIP_STONEY) {
for (bank = 1; bank <= 4; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
true);
}
rtd = adata->play_i2ssp_stream->runtime->private_data;
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
}
if (adata->capture_i2ssp_stream &&
adata->capture_i2ssp_stream->runtime) {
if (adata->asic_type != CHIP_STONEY) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
true);
}
rtd = adata->capture_i2ssp_stream->runtime->private_data;
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
}
if (adata->asic_type != CHIP_CARRIZO) {
if (adata->play_i2s_micsp_stream &&
adata->play_i2s_micsp_stream->runtime) {
rtd = adata->play_i2s_micsp_stream->runtime->private_data;
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
}
if (adata->play_i2sbt_stream &&
adata->play_i2sbt_stream->runtime) {
rtd = adata->play_i2sbt_stream->runtime->private_data;
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
}
if (adata->capture_i2sbt_stream &&
adata->capture_i2sbt_stream->runtime) {
rtd = adata->capture_i2sbt_stream->runtime->private_data;
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
}
}
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp_pcm_runtime_suspend(struct device *dev)
{
int status;
struct audio_drv_data *adata = dev_get_drvdata(dev);
status = acp_deinit(adata->acp_mmio);
if (status)
dev_err(dev, "ACP Deinit failed status:%d\n", status);
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp_pcm_runtime_resume(struct device *dev)
{
int status;
struct audio_drv_data *adata = dev_get_drvdata(dev);
status = acp_init(adata->acp_mmio, adata->asic_type);
if (status) {
dev_err(dev, "ACP Init failed status:%d\n", status);
return status;
}
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static const struct dev_pm_ops acp_pm_ops = {
.resume = acp_pcm_resume,
.runtime_suspend = acp_pcm_runtime_suspend,
.runtime_resume = acp_pcm_runtime_resume,
};
static struct platform_driver acp_dma_driver = {
.probe = acp_audio_probe,
.remove_new = acp_audio_remove,
.driver = {
.name = DRV_NAME,
.pm = &acp_pm_ops,
},
};
module_platform_driver(acp_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP PCM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:"DRV_NAME);
| linux-master | sound/soc/amd/acp-pcm-dma.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Machine driver for AMD ACP Audio engine using DA7219 & MAX98357 codec.
//
//Copyright 2016 Advanced Micro Devices, Inc.
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/acpi.h>
#include "raven/acp3x.h"
#include "../codecs/rt5682.h"
#include "../codecs/rt1015.h"
#define PCO_PLAT_CLK 48000000
#define RT5682_PLL_FREQ (48000 * 512)
#define DUAL_CHANNEL 2
static struct snd_soc_jack pco_jack;
static struct snd_soc_jack_pin pco_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static struct clk *rt5682_dai_wclk;
static struct clk *rt5682_dai_bclk;
static struct gpio_desc *dmic_sel;
void *soc_is_rltk_max(struct device *dev);
enum {
RT5682 = 0,
MAX,
EC,
};
static int acp3x_5682_init(struct snd_soc_pcm_runtime *rtd)
{
int ret;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name);
/* set rt5682 dai fmt */
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP);
if (ret < 0) {
dev_err(rtd->card->dev,
"Failed to set rt5682 dai fmt: %d\n", ret);
return ret;
}
/* set codec PLL */
ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL2, RT5682_PLL2_S_MCLK,
PCO_PLAT_CLK, RT5682_PLL_FREQ);
if (ret < 0) {
dev_err(rtd->dev, "can't set rt5682 PLL: %d\n", ret);
return ret;
}
/* Set codec sysclk */
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682_SCLK_S_PLL2,
RT5682_PLL_FREQ, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev,
"Failed to set rt5682 SYSCLK: %d\n", ret);
return ret;
}
/* Set tdm/i2s1 master bclk ratio */
ret = snd_soc_dai_set_bclk_ratio(codec_dai, 64);
if (ret < 0) {
dev_err(rtd->dev,
"Failed to set rt5682 tdm bclk ratio: %d\n", ret);
return ret;
}
rt5682_dai_wclk = clk_get(component->dev, "rt5682-dai-wclk");
rt5682_dai_bclk = clk_get(component->dev, "rt5682-dai-bclk");
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&pco_jack,
pco_jack_pins,
ARRAY_SIZE(pco_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(pco_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(pco_jack.jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(pco_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(pco_jack.jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ret = snd_soc_component_set_jack(component, &pco_jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return ret;
}
static int rt5682_clk_enable(struct snd_pcm_substream *substream)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
/* RT5682 will support only 48K output with 48M mclk */
clk_set_rate(rt5682_dai_wclk, 48000);
clk_set_rate(rt5682_dai_bclk, 48000 * 64);
ret = clk_prepare_enable(rt5682_dai_wclk);
if (ret < 0) {
dev_err(rtd->dev, "can't enable wclk %d\n", ret);
return ret;
}
return ret;
}
static int acp3x_1015_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai;
int srate, i, ret;
ret = 0;
srate = params_rate(params);
for_each_rtd_codec_dais(rtd, i, codec_dai) {
if (strcmp(codec_dai->name, "rt1015-aif"))
continue;
ret = snd_soc_dai_set_pll(codec_dai, 0, RT1015_PLL_S_BCLK,
64 * srate, 256 * srate);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(codec_dai, RT1015_SCLK_S_PLL,
256 * srate, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
}
return ret;
}
static void rt5682_clk_disable(void)
{
clk_disable_unprepare(rt5682_dai_wclk);
}
static const unsigned int channels[] = {
DUAL_CHANNEL,
};
static const unsigned int rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
static int acp3x_5682_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp3x_platform_info *machine = snd_soc_card_get_drvdata(card);
machine->play_i2s_instance = I2S_SP_INSTANCE;
machine->cap_i2s_instance = I2S_SP_INSTANCE;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return rt5682_clk_enable(substream);
}
static int acp3x_max_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp3x_platform_info *machine = snd_soc_card_get_drvdata(card);
machine->play_i2s_instance = I2S_BT_INSTANCE;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return rt5682_clk_enable(substream);
}
static int acp3x_ec_dmic0_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct acp3x_platform_info *machine = snd_soc_card_get_drvdata(card);
machine->cap_i2s_instance = I2S_BT_INSTANCE;
snd_soc_dai_set_bclk_ratio(codec_dai, 64);
return rt5682_clk_enable(substream);
}
static int dmic_switch;
static int dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = dmic_switch;
return 0;
}
static int dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
if (dmic_sel) {
dmic_switch = ucontrol->value.integer.value[0];
gpiod_set_value(dmic_sel, dmic_switch);
}
return 0;
}
static void rt5682_shutdown(struct snd_pcm_substream *substream)
{
rt5682_clk_disable();
}
static const struct snd_soc_ops acp3x_5682_ops = {
.startup = acp3x_5682_startup,
.shutdown = rt5682_shutdown,
};
static const struct snd_soc_ops acp3x_max_play_ops = {
.startup = acp3x_max_startup,
.shutdown = rt5682_shutdown,
.hw_params = acp3x_1015_hw_params,
};
static const struct snd_soc_ops acp3x_ec_cap0_ops = {
.startup = acp3x_ec_dmic0_startup,
.shutdown = rt5682_shutdown,
};
SND_SOC_DAILINK_DEF(acp3x_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("acp3x_i2s_playcap.0")));
SND_SOC_DAILINK_DEF(acp3x_bt,
DAILINK_COMP_ARRAY(COMP_CPU("acp3x_i2s_playcap.2")));
SND_SOC_DAILINK_DEF(rt5682,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5682:00", "rt5682-aif1")));
SND_SOC_DAILINK_DEF(max,
DAILINK_COMP_ARRAY(COMP_CODEC("MX98357A:00", "HiFi")));
SND_SOC_DAILINK_DEF(rt1015p,
DAILINK_COMP_ARRAY(COMP_CODEC("RTL1015:00", "HiFi")));
SND_SOC_DAILINK_DEF(rt1015,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC1015:00", "rt1015-aif"),
COMP_CODEC("i2c-10EC1015:01", "rt1015-aif")));
SND_SOC_DAILINK_DEF(cros_ec,
DAILINK_COMP_ARRAY(COMP_CODEC("GOOG0013:00", "EC Codec I2S RX")));
SND_SOC_DAILINK_DEF(platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp3x_rv_i2s_dma.0")));
static struct snd_soc_codec_conf rt1015_conf[] = {
{
.dlc = COMP_CODEC_CONF("i2c-10EC1015:00"),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF("i2c-10EC1015:01"),
.name_prefix = "Right",
},
};
static struct snd_soc_dai_link acp3x_dai[] = {
[RT5682] = {
.name = "acp3x-5682-play",
.stream_name = "Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBP_CFP,
.init = acp3x_5682_init,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ops = &acp3x_5682_ops,
SND_SOC_DAILINK_REG(acp3x_i2s, rt5682, platform),
},
[MAX] = {
.name = "acp3x-max98357-play",
.stream_name = "HiFi Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
.ops = &acp3x_max_play_ops,
.cpus = acp3x_bt,
.num_cpus = ARRAY_SIZE(acp3x_bt),
.platforms = platform,
.num_platforms = ARRAY_SIZE(platform),
},
[EC] = {
.name = "acp3x-ec-dmic0-capture",
.stream_name = "Capture DMIC0",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBC_CFC,
.dpcm_capture = 1,
.ops = &acp3x_ec_cap0_ops,
SND_SOC_DAILINK_REG(acp3x_bt, cros_ec, platform),
},
};
static const char * const dmic_mux_text[] = {
"Front Mic",
"Rear Mic",
};
static SOC_ENUM_SINGLE_DECL(
acp3x_dmic_enum, SND_SOC_NOPM, 0, dmic_mux_text);
static const struct snd_kcontrol_new acp3x_dmic_mux_control =
SOC_DAPM_ENUM_EXT("DMIC Select Mux", acp3x_dmic_enum,
dmic_get, dmic_set);
static const struct snd_soc_dapm_widget acp3x_5682_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_SPK("Spk", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0,
&acp3x_dmic_mux_control),
};
static const struct snd_soc_dapm_route acp3x_5682_audio_route[] = {
{"Headphone Jack", NULL, "HPOL"},
{"Headphone Jack", NULL, "HPOR"},
{"IN1P", NULL, "Headset Mic"},
{"Spk", NULL, "Speaker"},
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
};
static const struct snd_kcontrol_new acp3x_5682_mc_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Spk"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_card acp3x_5682 = {
.name = "acp3xalc5682m98357",
.owner = THIS_MODULE,
.dai_link = acp3x_dai,
.num_links = ARRAY_SIZE(acp3x_dai),
.dapm_widgets = acp3x_5682_widgets,
.num_dapm_widgets = ARRAY_SIZE(acp3x_5682_widgets),
.dapm_routes = acp3x_5682_audio_route,
.num_dapm_routes = ARRAY_SIZE(acp3x_5682_audio_route),
.controls = acp3x_5682_mc_controls,
.num_controls = ARRAY_SIZE(acp3x_5682_mc_controls),
};
static const struct snd_soc_dapm_widget acp3x_1015_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0,
&acp3x_dmic_mux_control),
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
};
static const struct snd_soc_dapm_route acp3x_1015_route[] = {
{"Headphone Jack", NULL, "HPOL"},
{"Headphone Jack", NULL, "HPOR"},
{"IN1P", NULL, "Headset Mic"},
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
{"Left Spk", NULL, "Left SPO"},
{"Right Spk", NULL, "Right SPO"},
};
static const struct snd_kcontrol_new acp3x_mc_1015_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
};
static struct snd_soc_card acp3x_1015 = {
.name = "acp3xalc56821015",
.owner = THIS_MODULE,
.dai_link = acp3x_dai,
.num_links = ARRAY_SIZE(acp3x_dai),
.dapm_widgets = acp3x_1015_widgets,
.num_dapm_widgets = ARRAY_SIZE(acp3x_1015_widgets),
.dapm_routes = acp3x_1015_route,
.num_dapm_routes = ARRAY_SIZE(acp3x_1015_route),
.codec_conf = rt1015_conf,
.num_configs = ARRAY_SIZE(rt1015_conf),
.controls = acp3x_mc_1015_controls,
.num_controls = ARRAY_SIZE(acp3x_mc_1015_controls),
};
static const struct snd_soc_dapm_widget acp3x_1015p_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0,
&acp3x_dmic_mux_control),
SND_SOC_DAPM_SPK("Speakers", NULL),
};
static const struct snd_soc_dapm_route acp3x_1015p_route[] = {
{"Headphone Jack", NULL, "HPOL"},
{"Headphone Jack", NULL, "HPOR"},
{"IN1P", NULL, "Headset Mic"},
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
/* speaker */
{ "Speakers", NULL, "Speaker" },
};
static const struct snd_kcontrol_new acp3x_mc_1015p_controls[] = {
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_card acp3x_1015p = {
.name = "acp3xalc56821015p",
.owner = THIS_MODULE,
.dai_link = acp3x_dai,
.num_links = ARRAY_SIZE(acp3x_dai),
.dapm_widgets = acp3x_1015p_widgets,
.num_dapm_widgets = ARRAY_SIZE(acp3x_1015p_widgets),
.dapm_routes = acp3x_1015p_route,
.num_dapm_routes = ARRAY_SIZE(acp3x_1015p_route),
.controls = acp3x_mc_1015p_controls,
.num_controls = ARRAY_SIZE(acp3x_mc_1015p_controls),
};
void *soc_is_rltk_max(struct device *dev)
{
const struct acpi_device_id *match;
match = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!match)
return NULL;
return (void *)match->driver_data;
}
static void card_spk_dai_link_present(struct snd_soc_dai_link *links,
const char *card_name)
{
if (!strcmp(card_name, "acp3xalc56821015")) {
links[1].codecs = rt1015;
links[1].num_codecs = ARRAY_SIZE(rt1015);
} else if (!strcmp(card_name, "acp3xalc56821015p")) {
links[1].codecs = rt1015p;
links[1].num_codecs = ARRAY_SIZE(rt1015p);
} else {
links[1].codecs = max;
links[1].num_codecs = ARRAY_SIZE(max);
}
}
static int acp3x_probe(struct platform_device *pdev)
{
int ret;
struct snd_soc_card *card;
struct acp3x_platform_info *machine;
struct device *dev = &pdev->dev;
card = (struct snd_soc_card *)soc_is_rltk_max(dev);
if (!card)
return -ENODEV;
machine = devm_kzalloc(&pdev->dev, sizeof(*machine), GFP_KERNEL);
if (!machine)
return -ENOMEM;
card_spk_dai_link_present(card->dai_link, card->name);
card->dev = &pdev->dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
dmic_sel = devm_gpiod_get(&pdev->dev, "dmic", GPIOD_OUT_LOW);
if (IS_ERR(dmic_sel)) {
dev_err(&pdev->dev, "DMIC gpio failed err=%ld\n",
PTR_ERR(dmic_sel));
return PTR_ERR(dmic_sel);
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
return dev_err_probe(&pdev->dev, ret,
"devm_snd_soc_register_card(%s) failed\n",
card->name);
}
return 0;
}
static const struct acpi_device_id acp3x_audio_acpi_match[] = {
{ "AMDI5682", (unsigned long)&acp3x_5682},
{ "AMDI1015", (unsigned long)&acp3x_1015},
{ "10021015", (unsigned long)&acp3x_1015p},
{},
};
MODULE_DEVICE_TABLE(acpi, acp3x_audio_acpi_match);
static struct platform_driver acp3x_audio = {
.driver = {
.name = "acp3x-alc5682-max98357",
.acpi_match_table = ACPI_PTR(acp3x_audio_acpi_match),
.pm = &snd_soc_pm_ops,
},
.probe = acp3x_probe,
};
module_platform_driver(acp3x_audio);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("ALC5682 ALC1015, ALC1015P & MAX98357 audio support");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp3x-rt5682-max9836.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AMD Yellow Carp ACP PCI Driver
*
* Copyright 2021 Advanced Micro Devices, Inc.
*/
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <sound/pcm_params.h>
#include <linux/pm_runtime.h>
#include "acp6x.h"
struct acp6x_dev_data {
void __iomem *acp6x_base;
struct resource *res;
bool acp6x_audio_mode;
struct platform_device *pdev[ACP6x_DEVS];
};
static int acp6x_power_on(void __iomem *acp_base)
{
u32 val;
int timeout;
val = acp6x_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return val;
if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
acp6x_writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
val = acp6x_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int acp6x_reset(void __iomem *acp_base)
{
u32 val;
int timeout;
acp6x_writel(1, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = acp6x_readl(acp_base + ACP_SOFT_RESET);
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
break;
cpu_relax();
}
acp6x_writel(0, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = acp6x_readl(acp_base + ACP_SOFT_RESET);
if (!val)
return 0;
cpu_relax();
}
return -ETIMEDOUT;
}
static void acp6x_enable_interrupts(void __iomem *acp_base)
{
acp6x_writel(0x01, acp_base + ACP_EXTERNAL_INTR_ENB);
}
static void acp6x_disable_interrupts(void __iomem *acp_base)
{
acp6x_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
ACP_EXTERNAL_INTR_STAT);
acp6x_writel(0x00, acp_base + ACP_EXTERNAL_INTR_CNTL);
acp6x_writel(0x00, acp_base + ACP_EXTERNAL_INTR_ENB);
}
static int acp6x_init(void __iomem *acp_base)
{
int ret;
/* power on */
ret = acp6x_power_on(acp_base);
if (ret) {
pr_err("ACP power on failed\n");
return ret;
}
acp6x_writel(0x01, acp_base + ACP_CONTROL);
/* Reset */
ret = acp6x_reset(acp_base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
acp6x_writel(0x03, acp_base + ACP_CLKMUX_SEL);
acp6x_enable_interrupts(acp_base);
return 0;
}
static int acp6x_deinit(void __iomem *acp_base)
{
int ret;
acp6x_disable_interrupts(acp_base);
/* Reset */
ret = acp6x_reset(acp_base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
acp6x_writel(0x00, acp_base + ACP_CLKMUX_SEL);
acp6x_writel(0x00, acp_base + ACP_CONTROL);
return 0;
}
static irqreturn_t acp6x_irq_handler(int irq, void *dev_id)
{
struct acp6x_dev_data *adata;
struct pdm_dev_data *yc_pdm_data;
u32 val;
adata = dev_id;
if (!adata)
return IRQ_NONE;
val = acp6x_readl(adata->acp6x_base + ACP_EXTERNAL_INTR_STAT);
if (val & BIT(PDM_DMA_STAT)) {
yc_pdm_data = dev_get_drvdata(&adata->pdev[0]->dev);
acp6x_writel(BIT(PDM_DMA_STAT), adata->acp6x_base + ACP_EXTERNAL_INTR_STAT);
if (yc_pdm_data->capture_stream)
snd_pcm_period_elapsed(yc_pdm_data->capture_stream);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int snd_acp6x_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct acp6x_dev_data *adata;
struct platform_device_info pdevinfo[ACP6x_DEVS];
int index = 0;
int val = 0x00;
u32 addr;
unsigned int irqflags, flag;
int ret;
irqflags = IRQF_SHARED;
/* Return if acp config flag is defined */
flag = snd_amd_acp_find_config(pci);
if (flag)
return -ENODEV;
/* Yellow Carp device check */
switch (pci->revision) {
case 0x60:
case 0x6f:
break;
default:
dev_dbg(&pci->dev, "acp6x pci device not found\n");
return -ENODEV;
}
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
return -ENODEV;
}
ret = pci_request_regions(pci, "AMD ACP3x audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
adata = devm_kzalloc(&pci->dev, sizeof(struct acp6x_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
goto release_regions;
}
addr = pci_resource_start(pci, 0);
adata->acp6x_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
if (!adata->acp6x_base) {
ret = -ENOMEM;
goto release_regions;
}
pci_set_master(pci);
pci_set_drvdata(pci, adata);
ret = acp6x_init(adata->acp6x_base);
if (ret)
goto release_regions;
val = acp6x_readl(adata->acp6x_base + ACP_PIN_CONFIG);
switch (val) {
case ACP_CONFIG_0:
case ACP_CONFIG_1:
case ACP_CONFIG_2:
case ACP_CONFIG_3:
case ACP_CONFIG_9:
case ACP_CONFIG_15:
dev_info(&pci->dev, "Audio Mode %d\n", val);
break;
default:
adata->res = devm_kzalloc(&pci->dev,
sizeof(struct resource),
GFP_KERNEL);
if (!adata->res) {
ret = -ENOMEM;
goto de_init;
}
adata->res->name = "acp_iomem";
adata->res->flags = IORESOURCE_MEM;
adata->res->start = addr;
adata->res->end = addr + (ACP6x_REG_END - ACP6x_REG_START);
adata->acp6x_audio_mode = ACP6x_PDM_MODE;
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo[0].name = "acp_yc_pdm_dma";
pdevinfo[0].id = 0;
pdevinfo[0].parent = &pci->dev;
pdevinfo[0].num_res = 1;
pdevinfo[0].res = adata->res;
pdevinfo[1].name = "dmic-codec";
pdevinfo[1].id = 0;
pdevinfo[1].parent = &pci->dev;
pdevinfo[2].name = "acp_yc_mach";
pdevinfo[2].id = 0;
pdevinfo[2].parent = &pci->dev;
for (index = 0; index < ACP6x_DEVS; index++) {
adata->pdev[index] =
platform_device_register_full(&pdevinfo[index]);
if (IS_ERR(adata->pdev[index])) {
dev_err(&pci->dev, "cannot register %s device\n",
pdevinfo[index].name);
ret = PTR_ERR(adata->pdev[index]);
goto unregister_devs;
}
}
break;
}
ret = devm_request_irq(&pci->dev, pci->irq, acp6x_irq_handler,
irqflags, "ACP_PCI_IRQ", adata);
if (ret) {
dev_err(&pci->dev, "ACP PCI IRQ request failed\n");
goto unregister_devs;
}
pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return 0;
unregister_devs:
for (--index; index >= 0; index--)
platform_device_unregister(adata->pdev[index]);
de_init:
if (acp6x_deinit(adata->acp6x_base))
dev_err(&pci->dev, "ACP de-init failed\n");
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
}
static int __maybe_unused snd_acp6x_suspend(struct device *dev)
{
struct acp6x_dev_data *adata;
int ret;
adata = dev_get_drvdata(dev);
ret = acp6x_deinit(adata->acp6x_base);
if (ret)
dev_err(dev, "ACP de-init failed\n");
return ret;
}
static int __maybe_unused snd_acp6x_resume(struct device *dev)
{
struct acp6x_dev_data *adata;
int ret;
adata = dev_get_drvdata(dev);
ret = acp6x_init(adata->acp6x_base);
if (ret)
dev_err(dev, "ACP init failed\n");
return ret;
}
static const struct dev_pm_ops acp6x_pm = {
SET_RUNTIME_PM_OPS(snd_acp6x_suspend, snd_acp6x_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(snd_acp6x_suspend, snd_acp6x_resume)
};
static void snd_acp6x_remove(struct pci_dev *pci)
{
struct acp6x_dev_data *adata;
int ret, index;
adata = pci_get_drvdata(pci);
if (adata->acp6x_audio_mode == ACP6x_PDM_MODE) {
for (index = 0; index < ACP6x_DEVS; index++)
platform_device_unregister(adata->pdev[index]);
}
ret = acp6x_deinit(adata->acp6x_base);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
pci_release_regions(pci);
pci_disable_device(pci);
}
static const struct pci_device_id snd_acp6x_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_acp6x_ids);
static struct pci_driver yc_acp6x_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_acp6x_ids,
.probe = snd_acp6x_probe,
.remove = snd_acp6x_remove,
.driver = {
.pm = &acp6x_pm,
}
};
module_pci_driver(yc_acp6x_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP Yellow Carp PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/yc/pci-acp6x.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Machine driver for AMD Yellow Carp platform using DMIC
*
* Copyright 2021 Advanced Micro Devices, Inc.
*/
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/io.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include "acp6x.h"
#define DRV_NAME "acp_yc_mach"
SND_SOC_DAILINK_DEF(acp6x_pdm,
DAILINK_COMP_ARRAY(COMP_CPU("acp_yc_pdm_dma.0")));
SND_SOC_DAILINK_DEF(dmic_codec,
DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec.0",
"dmic-hifi")));
SND_SOC_DAILINK_DEF(pdm_platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_yc_pdm_dma.0")));
static struct snd_soc_dai_link acp6x_dai_pdm[] = {
{
.name = "acp6x-dmic-capture",
.stream_name = "DMIC capture",
.capture_only = 1,
SND_SOC_DAILINK_REG(acp6x_pdm, dmic_codec, pdm_platform),
},
};
static struct snd_soc_card acp6x_card = {
.name = "acp6x",
.owner = THIS_MODULE,
.dai_link = acp6x_dai_pdm,
.num_links = 1,
};
static const struct dmi_system_id yc_acp_quirk_table[] = {
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Dell Inc."),
DMI_MATCH(DMI_PRODUCT_NAME, "Dell G15 5525"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D0"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D0"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D1"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D2"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D3"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D4"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21D5"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CF"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CG"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CQ"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CR"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CM"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CN"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CH"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CJ"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CK"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21CL"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21EF"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21EM"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21EN"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21HY"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21J5"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "21J6"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "82QF"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "82TL"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "82UG"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "82V2"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "UM5302TA"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "M5402RA"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "M6400RC"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "M3402RA"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_PRODUCT_NAME, "M6500RC"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Micro-Star International Co., Ltd."),
DMI_MATCH(DMI_PRODUCT_NAME, "Bravo 15 B7ED"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Alienware"),
DMI_MATCH(DMI_PRODUCT_NAME, "Alienware m17 R5 AMD"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "TIMI"),
DMI_MATCH(DMI_PRODUCT_NAME, "Redmi Book Pro 14 2022"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "TIMI"),
DMI_MATCH(DMI_PRODUCT_NAME, "Redmi Book Pro 15 2022"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Razer"),
DMI_MATCH(DMI_PRODUCT_NAME, "Blade 14 (2022) - RZ09-0427"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "RB"),
DMI_MATCH(DMI_PRODUCT_NAME, "Swift SFA16-41"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "IRBIS"),
DMI_MATCH(DMI_PRODUCT_NAME, "15NBC1011"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
DMI_MATCH(DMI_PRODUCT_NAME, "OMEN by HP Gaming Laptop 16z-n000"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
DMI_MATCH(DMI_BOARD_NAME, "8A42"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
DMI_MATCH(DMI_BOARD_NAME, "8A43"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
DMI_MATCH(DMI_BOARD_NAME, "8A22"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
DMI_MATCH(DMI_BOARD_NAME, "8A3E"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "MECHREVO"),
DMI_MATCH(DMI_BOARD_NAME, "MRID6"),
}
},
{
.driver_data = &acp6x_card,
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "System76"),
DMI_MATCH(DMI_PRODUCT_VERSION, "pang12"),
}
},
{}
};
static int acp6x_probe(struct platform_device *pdev)
{
const struct dmi_system_id *dmi_id;
struct acp6x_pdm *machine = NULL;
struct snd_soc_card *card;
struct acpi_device *adev;
int ret;
/* check the parent device's firmware node has _DSD or not */
adev = ACPI_COMPANION(pdev->dev.parent);
if (adev) {
const union acpi_object *obj;
if (!acpi_dev_get_property(adev, "AcpDmicConnected", ACPI_TYPE_INTEGER, &obj) &&
obj->integer.value == 1)
platform_set_drvdata(pdev, &acp6x_card);
}
/* check for any DMI overrides */
dmi_id = dmi_first_match(yc_acp_quirk_table);
if (dmi_id)
platform_set_drvdata(pdev, dmi_id->driver_data);
card = platform_get_drvdata(pdev);
if (!card)
return -ENODEV;
dev_info(&pdev->dev, "Enabling ACP DMIC support via %s", dmi_id ? "DMI" : "ACPI");
acp6x_card.dev = &pdev->dev;
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
return dev_err_probe(&pdev->dev, ret,
"snd_soc_register_card(%s) failed\n",
card->name);
}
return 0;
}
static struct platform_driver acp6x_mach_driver = {
.driver = {
.name = "acp_yc_mach",
.pm = &snd_soc_pm_ops,
},
.probe = acp6x_probe,
};
module_platform_driver(acp6x_mach_driver);
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/yc/acp6x-mach.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AMD ALSA SoC Yellow Carp PDM Driver
*
* Copyright 2021 Advanced Micro Devices, Inc.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/pm_runtime.h>
#include "acp6x.h"
#define DRV_NAME "acp_yc_pdm_dma"
static int pdm_gain = 3;
module_param(pdm_gain, int, 0644);
MODULE_PARM_DESC(pdm_gain, "Gain control (0-3)");
static const struct snd_pcm_hardware acp6x_pdm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static void acp6x_init_pdm_ring_buffer(u32 physical_addr, u32 buffer_size,
u32 watermark_size, void __iomem *acp_base)
{
acp6x_writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
acp6x_writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
acp6x_writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
acp6x_writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
}
static void acp6x_enable_pdm_clock(void __iomem *acp_base)
{
u32 pdm_clk_enable, pdm_ctrl;
pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK;
pdm_ctrl = 0x00;
acp6x_writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
pdm_ctrl = acp6x_readl(acp_base + ACP_WOV_MISC_CTRL);
pdm_ctrl &= ~ACP_WOV_GAIN_CONTROL;
pdm_ctrl |= FIELD_PREP(ACP_WOV_GAIN_CONTROL, clamp(pdm_gain, 0, 3));
acp6x_writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
}
static void acp6x_enable_pdm_interrupts(void __iomem *acp_base)
{
u32 ext_int_ctrl;
ext_int_ctrl = acp6x_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl |= PDM_DMA_INTR_MASK;
acp6x_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
static void acp6x_disable_pdm_interrupts(void __iomem *acp_base)
{
u32 ext_int_ctrl;
ext_int_ctrl = acp6x_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl &= ~PDM_DMA_INTR_MASK;
acp6x_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
static bool acp6x_check_pdm_dma_status(void __iomem *acp_base)
{
bool pdm_dma_status;
u32 pdm_enable, pdm_dma_enable;
pdm_dma_status = false;
pdm_enable = acp6x_readl(acp_base + ACP_WOV_PDM_ENABLE);
pdm_dma_enable = acp6x_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable & ACP_PDM_DMA_EN_STATUS))
pdm_dma_status = true;
return pdm_dma_status;
}
static int acp6x_start_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable;
u32 pdm_dma_enable;
int timeout;
pdm_enable = 0x01;
pdm_dma_enable = 0x01;
acp6x_enable_pdm_clock(acp_base);
acp6x_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
acp6x_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
pdm_dma_enable = acp6x_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS)
return 0;
udelay(DELAY_US);
}
return -ETIMEDOUT;
}
static int acp6x_stop_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable, pdm_dma_enable;
int timeout;
pdm_enable = 0x00;
pdm_dma_enable = 0x00;
pdm_enable = acp6x_readl(acp_base + ACP_WOV_PDM_ENABLE);
pdm_dma_enable = acp6x_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if (pdm_dma_enable & 0x01) {
pdm_dma_enable = 0x02;
acp6x_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
pdm_dma_enable = acp6x_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == 0x00)
break;
udelay(DELAY_US);
}
if (timeout == ACP_COUNTER)
return -ETIMEDOUT;
}
if (pdm_enable == ACP_PDM_ENABLE) {
pdm_enable = ACP_PDM_DISABLE;
acp6x_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
}
acp6x_writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
return 0;
}
static void acp6x_config_dma(struct pdm_stream_instance *rtd, int direction)
{
u16 page_idx;
u32 low, high, val;
dma_addr_t addr;
addr = rtd->dma_addr;
val = PDM_PTE_OFFSET;
/* Group Enable */
acp6x_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp6x_base +
ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
acp6x_writel(PAGE_SIZE_4K_ENABLE, rtd->acp6x_base +
ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
acp6x_writel(low, rtd->acp6x_base + ACP_SCRATCH_REG_0 + val);
high |= BIT(31);
acp6x_writel(high, rtd->acp6x_base + ACP_SCRATCH_REG_0 + val + 4);
val += 8;
addr += PAGE_SIZE;
}
}
static int acp6x_pdm_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct pdm_dev_data *adata;
struct pdm_stream_instance *pdm_data;
int ret;
runtime = substream->runtime;
adata = dev_get_drvdata(component->dev);
pdm_data = kzalloc(sizeof(*pdm_data), GFP_KERNEL);
if (!pdm_data)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = acp6x_pdm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(pdm_data);
return ret;
}
acp6x_enable_pdm_interrupts(adata->acp6x_base);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
adata->capture_stream = substream;
pdm_data->acp6x_base = adata->acp6x_base;
runtime->private_data = pdm_data;
return ret;
}
static int acp6x_pdm_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct pdm_stream_instance *rtd;
size_t size, period_bytes;
rtd = substream->runtime->private_data;
if (!rtd)
return -EINVAL;
size = params_buffer_bytes(params);
period_bytes = params_period_bytes(params);
rtd->dma_addr = substream->runtime->dma_addr;
rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
acp6x_config_dma(rtd, substream->stream);
acp6x_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, size,
period_bytes, rtd->acp6x_base);
return 0;
}
static u64 acp6x_pdm_get_byte_count(struct pdm_stream_instance *rtd,
int direction)
{
union acp_pdm_dma_count byte_count;
byte_count.bcount.high =
acp6x_readl(rtd->acp6x_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
byte_count.bcount.low =
acp6x_readl(rtd->acp6x_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
return byte_count.bytescount;
}
static snd_pcm_uframes_t acp6x_pdm_dma_pointer(struct snd_soc_component *comp,
struct snd_pcm_substream *stream)
{
struct pdm_stream_instance *rtd;
u32 pos, buffersize;
u64 bytescount;
rtd = stream->runtime->private_data;
buffersize = frames_to_bytes(stream->runtime,
stream->runtime->buffer_size);
bytescount = acp6x_pdm_get_byte_count(rtd, stream->stream);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(stream->runtime, pos);
}
static int acp6x_pdm_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, MIN_BUFFER, MAX_BUFFER);
return 0;
}
static int acp6x_pdm_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct pdm_dev_data *adata = dev_get_drvdata(component->dev);
acp6x_disable_pdm_interrupts(adata->acp6x_base);
adata->capture_stream = NULL;
return 0;
}
static int acp6x_pdm_dai_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct pdm_stream_instance *rtd;
int ret;
bool pdm_status;
unsigned int ch_mask;
rtd = substream->runtime->private_data;
ret = 0;
switch (substream->runtime->channels) {
case TWO_CH:
ch_mask = 0x00;
break;
default:
return -EINVAL;
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
acp6x_writel(ch_mask, rtd->acp6x_base + ACP_WOV_PDM_NO_OF_CHANNELS);
acp6x_writel(PDM_DECIMATION_FACTOR, rtd->acp6x_base +
ACP_WOV_PDM_DECIMATION_FACTOR);
rtd->bytescount = acp6x_pdm_get_byte_count(rtd, substream->stream);
pdm_status = acp6x_check_pdm_dma_status(rtd->acp6x_base);
if (!pdm_status)
ret = acp6x_start_pdm_dma(rtd->acp6x_base);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
pdm_status = acp6x_check_pdm_dma_status(rtd->acp6x_base);
if (pdm_status)
ret = acp6x_stop_pdm_dma(rtd->acp6x_base);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct snd_soc_dai_ops acp6x_pdm_dai_ops = {
.trigger = acp6x_pdm_dai_trigger,
};
static struct snd_soc_dai_driver acp6x_pdm_dai_driver = {
.capture = {
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 48000,
.rate_max = 48000,
},
.ops = &acp6x_pdm_dai_ops,
};
static const struct snd_soc_component_driver acp6x_pdm_component = {
.name = DRV_NAME,
.open = acp6x_pdm_dma_open,
.close = acp6x_pdm_dma_close,
.hw_params = acp6x_pdm_dma_hw_params,
.pointer = acp6x_pdm_dma_pointer,
.pcm_construct = acp6x_pdm_dma_new,
.legacy_dai_naming = 1,
};
static int acp6x_pdm_audio_probe(struct platform_device *pdev)
{
struct resource *res;
struct pdm_dev_data *adata;
int status;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
if (!adata)
return -ENOMEM;
adata->acp6x_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!adata->acp6x_base)
return -ENOMEM;
adata->capture_stream = NULL;
dev_set_drvdata(&pdev->dev, adata);
status = devm_snd_soc_register_component(&pdev->dev,
&acp6x_pdm_component,
&acp6x_pdm_dai_driver, 1);
if (status) {
dev_err(&pdev->dev, "Fail to register acp pdm dai\n");
return -ENODEV;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void acp6x_pdm_audio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused acp6x_pdm_resume(struct device *dev)
{
struct pdm_dev_data *adata;
struct snd_pcm_runtime *runtime;
struct pdm_stream_instance *rtd;
u32 period_bytes, buffer_len;
adata = dev_get_drvdata(dev);
if (adata->capture_stream && adata->capture_stream->runtime) {
runtime = adata->capture_stream->runtime;
rtd = runtime->private_data;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
acp6x_config_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
acp6x_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, buffer_len,
period_bytes, adata->acp6x_base);
}
acp6x_enable_pdm_interrupts(adata->acp6x_base);
return 0;
}
static int __maybe_unused acp6x_pdm_suspend(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
acp6x_disable_pdm_interrupts(adata->acp6x_base);
return 0;
}
static int __maybe_unused acp6x_pdm_runtime_resume(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
acp6x_enable_pdm_interrupts(adata->acp6x_base);
return 0;
}
static const struct dev_pm_ops acp6x_pdm_pm_ops = {
SET_RUNTIME_PM_OPS(acp6x_pdm_suspend, acp6x_pdm_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(acp6x_pdm_suspend, acp6x_pdm_resume)
};
static struct platform_driver acp6x_pdm_dma_driver = {
.probe = acp6x_pdm_audio_probe,
.remove_new = acp6x_pdm_audio_remove,
.driver = {
.name = "acp_yc_pdm_dma",
.pm = &acp6x_pdm_pm_ops,
},
};
module_platform_driver(acp6x_pdm_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP6x YC PDM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/yc/acp6x-pdm-dma.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Machine driver for AMD Vangogh platform using either
* NAU8821 & CS35L41 or NAU8821 & MAX98388 codecs.
*
* Copyright 2021 Advanced Micro Devices, Inc.
*/
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/input-event-codes.h>
#include <linux/module.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "../../codecs/nau8821.h"
#include "acp5x.h"
#define DRV_NAME "acp5x_mach"
#define DUAL_CHANNEL 2
#define ACP5X_NAU8821_BCLK 3072000
#define ACP5X_NAU8821_FREQ_OUT 12288000
#define ACP5X_NAU8821_COMP_NAME "i2c-NVTN2020:00"
#define ACP5X_NAU8821_DAI_NAME "nau8821-hifi"
#define ACP5X_CS35L41_COMP_LNAME "spi-VLV1776:00"
#define ACP5X_CS35L41_COMP_RNAME "spi-VLV1776:01"
#define ACP5X_CS35L41_DAI_NAME "cs35l41-pcm"
#define ACP5X_MAX98388_COMP_LNAME "i2c-ADS8388:00"
#define ACP5X_MAX98388_COMP_RNAME "i2c-ADS8388:01"
#define ACP5X_MAX98388_DAI_NAME "max98388-aif1"
static struct snd_soc_jack vg_headset;
SND_SOC_DAILINK_DEF(platform, DAILINK_COMP_ARRAY(COMP_PLATFORM("acp5x_i2s_dma.0")));
SND_SOC_DAILINK_DEF(acp5x_i2s, DAILINK_COMP_ARRAY(COMP_CPU("acp5x_i2s_playcap.0")));
SND_SOC_DAILINK_DEF(acp5x_bt, DAILINK_COMP_ARRAY(COMP_CPU("acp5x_i2s_playcap.1")));
SND_SOC_DAILINK_DEF(nau8821, DAILINK_COMP_ARRAY(COMP_CODEC(ACP5X_NAU8821_COMP_NAME,
ACP5X_NAU8821_DAI_NAME)));
static struct snd_soc_jack_pin acp5x_nau8821_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_kcontrol_new acp5x_8821_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
};
static int platform_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct snd_soc_card *card = dapm->card;
struct snd_soc_dai *dai;
int ret = 0;
dai = snd_soc_card_get_codec_dai(card, ACP5X_NAU8821_DAI_NAME);
if (!dai) {
dev_err(card->dev, "Codec dai not found\n");
return -EIO;
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
ret = snd_soc_dai_set_sysclk(dai, NAU8821_CLK_INTERNAL, 0, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "set sysclk err = %d\n", ret);
return -EIO;
}
} else {
ret = snd_soc_dai_set_sysclk(dai, NAU8821_CLK_FLL_BLK, 0, SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(dai->dev, "can't set BLK clock %d\n", ret);
ret = snd_soc_dai_set_pll(dai, 0, 0, ACP5X_NAU8821_BCLK, ACP5X_NAU8821_FREQ_OUT);
if (ret < 0)
dev_err(dai->dev, "can't set FLL: %d\n", ret);
}
return ret;
}
static int acp5x_8821_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
int ret;
/*
* Headset buttons map to the google Reference headset.
* These can be configured by userspace.
*/
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_BTN_0,
&vg_headset, acp5x_nau8821_jack_pins,
ARRAY_SIZE(acp5x_nau8821_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(vg_headset.jack, SND_JACK_BTN_0, KEY_MEDIA);
nau8821_enable_jack_detect(component, &vg_headset);
return ret;
}
static const unsigned int rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const unsigned int channels[] = {
2,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
static const unsigned int acp5x_nau8821_format[] = {32};
static struct snd_pcm_hw_constraint_list constraints_sample_bits = {
.list = acp5x_nau8821_format,
.count = ARRAY_SIZE(acp5x_nau8821_format),
};
static int acp5x_8821_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct acp5x_platform_info *machine = snd_soc_card_get_drvdata(rtd->card);
machine->play_i2s_instance = I2S_SP_INSTANCE;
machine->cap_i2s_instance = I2S_SP_INSTANCE;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
&constraints_sample_bits);
return 0;
}
static int acp5x_nau8821_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *dai = snd_soc_card_get_codec_dai(card, ACP5X_NAU8821_DAI_NAME);
int ret, bclk;
if (!dai)
return -EINVAL;
ret = snd_soc_dai_set_sysclk(dai, NAU8821_CLK_FLL_BLK, 0, SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(card->dev, "can't set FS clock %d\n", ret);
bclk = snd_soc_params_to_bclk(params);
if (bclk < 0) {
dev_err(dai->dev, "Fail to get BCLK rate: %d\n", bclk);
return bclk;
}
ret = snd_soc_dai_set_pll(dai, 0, 0, bclk, params_rate(params) * 256);
if (ret < 0)
dev_err(card->dev, "can't set FLL: %d\n", ret);
return ret;
}
static const struct snd_soc_ops acp5x_8821_ops = {
.startup = acp5x_8821_startup,
.hw_params = acp5x_nau8821_hw_params,
};
static int acp5x_cs35l41_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct acp5x_platform_info *machine = snd_soc_card_get_drvdata(rtd->card);
struct snd_pcm_runtime *runtime = substream->runtime;
machine->play_i2s_instance = I2S_HS_INSTANCE;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return 0;
}
static int acp5x_cs35l41_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int bclk, rate = params_rate(params);
struct snd_soc_component *comp;
int ret, i;
switch (rate) {
case 48000:
bclk = 1536000;
break;
default:
bclk = 0;
break;
}
for_each_rtd_components(rtd, i, comp) {
if (!(strcmp(comp->name, ACP5X_CS35L41_COMP_LNAME)) ||
!(strcmp(comp->name, ACP5X_CS35L41_COMP_RNAME))) {
if (!bclk) {
dev_err(comp->dev, "Invalid sample rate: 0x%x\n", rate);
return -EINVAL;
}
ret = snd_soc_component_set_sysclk(comp, 0, 0, bclk, SND_SOC_CLOCK_IN);
if (ret) {
dev_err(comp->dev, "failed to set SYSCLK: %d\n", ret);
return ret;
}
}
}
return 0;
}
static const struct snd_soc_ops acp5x_cs35l41_play_ops = {
.startup = acp5x_cs35l41_startup,
.hw_params = acp5x_cs35l41_hw_params,
};
static struct snd_soc_codec_conf acp5x_cs35l41_conf[] = {
{
.dlc = COMP_CODEC_CONF(ACP5X_CS35L41_COMP_LNAME),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF(ACP5X_CS35L41_COMP_RNAME),
.name_prefix = "Right",
},
};
SND_SOC_DAILINK_DEF(cs35l41, DAILINK_COMP_ARRAY(COMP_CODEC(ACP5X_CS35L41_COMP_LNAME,
ACP5X_CS35L41_DAI_NAME),
COMP_CODEC(ACP5X_CS35L41_COMP_RNAME,
ACP5X_CS35L41_DAI_NAME)));
static struct snd_soc_dai_link acp5x_8821_35l41_dai[] = {
{
.name = "acp5x-8821-play",
.stream_name = "Playback/Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ops = &acp5x_8821_ops,
.init = acp5x_8821_init,
SND_SOC_DAILINK_REG(acp5x_i2s, nau8821, platform),
},
{
.name = "acp5x-CS35L41-Stereo",
.stream_name = "CS35L41 Stereo Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
.playback_only = 1,
.ops = &acp5x_cs35l41_play_ops,
SND_SOC_DAILINK_REG(acp5x_bt, cs35l41, platform),
},
};
static const struct snd_soc_dapm_widget acp5x_8821_35l41_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
platform_clock_control,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route acp5x_8821_35l41_audio_route[] = {
/* HP jack connectors - unknown if we have jack detection */
{ "Headphone", NULL, "HPOL" },
{ "Headphone", NULL, "HPOR" },
{ "MICL", NULL, "Headset Mic" },
{ "MICR", NULL, "Headset Mic" },
{ "DMIC", NULL, "Int Mic" },
{ "Headphone", NULL, "Platform Clock" },
{ "Headset Mic", NULL, "Platform Clock" },
{ "Int Mic", NULL, "Platform Clock" },
};
static struct snd_soc_card acp5x_8821_35l41_card = {
.name = "acp5x",
.owner = THIS_MODULE,
.dai_link = acp5x_8821_35l41_dai,
.num_links = ARRAY_SIZE(acp5x_8821_35l41_dai),
.dapm_widgets = acp5x_8821_35l41_widgets,
.num_dapm_widgets = ARRAY_SIZE(acp5x_8821_35l41_widgets),
.dapm_routes = acp5x_8821_35l41_audio_route,
.num_dapm_routes = ARRAY_SIZE(acp5x_8821_35l41_audio_route),
.codec_conf = acp5x_cs35l41_conf,
.num_configs = ARRAY_SIZE(acp5x_cs35l41_conf),
.controls = acp5x_8821_controls,
.num_controls = ARRAY_SIZE(acp5x_8821_controls),
};
static int acp5x_max98388_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct acp5x_platform_info *machine = snd_soc_card_get_drvdata(rtd->card);
struct snd_pcm_runtime *runtime = substream->runtime;
machine->play_i2s_instance = I2S_HS_INSTANCE;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return 0;
}
static const struct snd_soc_ops acp5x_max98388_play_ops = {
.startup = acp5x_max98388_startup,
};
static struct snd_soc_codec_conf acp5x_max98388_conf[] = {
{
.dlc = COMP_CODEC_CONF(ACP5X_MAX98388_COMP_LNAME),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF(ACP5X_MAX98388_COMP_RNAME),
.name_prefix = "Right",
},
};
SND_SOC_DAILINK_DEF(max98388, DAILINK_COMP_ARRAY(COMP_CODEC(ACP5X_MAX98388_COMP_LNAME,
ACP5X_MAX98388_DAI_NAME),
COMP_CODEC(ACP5X_MAX98388_COMP_RNAME,
ACP5X_MAX98388_DAI_NAME)));
static struct snd_soc_dai_link acp5x_8821_98388_dai[] = {
{
.name = "acp5x-8821-play",
.stream_name = "Playback/Capture",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ops = &acp5x_8821_ops,
.init = acp5x_8821_init,
SND_SOC_DAILINK_REG(acp5x_i2s, nau8821, platform),
},
{
.name = "acp5x-max98388-play",
.stream_name = "MAX98388 Playback",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
.playback_only = 1,
.ops = &acp5x_max98388_play_ops,
SND_SOC_DAILINK_REG(acp5x_bt, max98388, platform),
},
};
static const struct snd_soc_dapm_widget acp5x_8821_98388_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
platform_clock_control,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SPK("SPK", NULL),
};
static const struct snd_soc_dapm_route acp5x_8821_98388_route[] = {
{ "Headphone", NULL, "HPOL" },
{ "Headphone", NULL, "HPOR" },
{ "MICL", NULL, "Headset Mic" },
{ "MICR", NULL, "Headset Mic" },
{ "DMIC", NULL, "Int Mic" },
{ "Headphone", NULL, "Platform Clock" },
{ "Headset Mic", NULL, "Platform Clock" },
{ "Int Mic", NULL, "Platform Clock" },
{ "SPK", NULL, "Left BE_OUT" },
{ "SPK", NULL, "Right BE_OUT" },
};
static struct snd_soc_card acp5x_8821_98388_card = {
.name = "acp5x-max98388",
.owner = THIS_MODULE,
.dai_link = acp5x_8821_98388_dai,
.num_links = ARRAY_SIZE(acp5x_8821_98388_dai),
.dapm_widgets = acp5x_8821_98388_widgets,
.num_dapm_widgets = ARRAY_SIZE(acp5x_8821_98388_widgets),
.dapm_routes = acp5x_8821_98388_route,
.num_dapm_routes = ARRAY_SIZE(acp5x_8821_98388_route),
.codec_conf = acp5x_max98388_conf,
.num_configs = ARRAY_SIZE(acp5x_max98388_conf),
.controls = acp5x_8821_controls,
.num_controls = ARRAY_SIZE(acp5x_8821_controls),
};
static const struct dmi_system_id acp5x_vg_quirk_table[] = {
{
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Valve"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jupiter"),
}
},
{}
};
static int acp5x_probe(struct platform_device *pdev)
{
const struct dmi_system_id *dmi_id;
struct acp5x_platform_info *machine;
struct device *dev = &pdev->dev;
struct snd_soc_card *card;
int ret;
card = (struct snd_soc_card *)device_get_match_data(dev);
if (!card) {
/*
* This is normally the result of directly probing the driver
* in pci-acp5x through platform_device_register_full(), which
* is necessary for the CS35L41 variant, as it doesn't support
* ACPI probing and relies on DMI quirks.
*/
dmi_id = dmi_first_match(acp5x_vg_quirk_table);
if (!dmi_id)
return -ENODEV;
card = &acp5x_8821_35l41_card;
}
machine = devm_kzalloc(dev, sizeof(*machine), GFP_KERNEL);
if (!machine)
return -ENOMEM;
card->dev = dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(dev, card);
if (ret)
return dev_err_probe(dev, ret, "Register card (%s) failed\n", card->name);
return 0;
}
static const struct acpi_device_id acp5x_acpi_match[] = {
{ "AMDI8821", (kernel_ulong_t)&acp5x_8821_98388_card },
{},
};
MODULE_DEVICE_TABLE(acpi, acp5x_acpi_match);
static struct platform_driver acp5x_mach_driver = {
.driver = {
.name = DRV_NAME,
.pm = &snd_soc_pm_ops,
.acpi_match_table = acp5x_acpi_match,
},
.probe = acp5x_probe,
};
module_platform_driver(acp5x_mach_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("NAU8821/CS35L41 & NAU8821/MAX98388 audio support");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/vangogh/acp5x-mach.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD ALSA SoC PCM Driver
//
// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
#include "acp5x.h"
#define DRV_NAME "acp5x_i2s_playcap"
static int acp5x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct i2s_dev_data *adata;
int mode;
adata = snd_soc_dai_get_drvdata(cpu_dai);
mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
switch (mode) {
case SND_SOC_DAIFMT_I2S:
adata->tdm_mode = TDM_DISABLE;
break;
case SND_SOC_DAIFMT_DSP_A:
adata->tdm_mode = TDM_ENABLE;
break;
default:
return -EINVAL;
}
mode = fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
switch (mode) {
case SND_SOC_DAIFMT_BP_FP:
adata->master_mode = I2S_MASTER_MODE_ENABLE;
break;
case SND_SOC_DAIFMT_BC_FC:
adata->master_mode = I2S_MASTER_MODE_DISABLE;
break;
}
return 0;
}
static int acp5x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
u32 tx_mask, u32 rx_mask,
int slots, int slot_width)
{
struct i2s_dev_data *adata;
u32 frm_len;
u16 slot_len;
adata = snd_soc_dai_get_drvdata(cpu_dai);
/* These values are as per Hardware Spec */
switch (slot_width) {
case SLOT_WIDTH_8:
slot_len = 8;
break;
case SLOT_WIDTH_16:
slot_len = 16;
break;
case SLOT_WIDTH_24:
slot_len = 24;
break;
case SLOT_WIDTH_32:
slot_len = 0;
break;
default:
return -EINVAL;
}
frm_len = FRM_LEN | (slots << 15) | (slot_len << 18);
adata->tdm_fmt = frm_len;
return 0;
}
static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct i2s_stream_instance *rtd;
struct snd_soc_pcm_runtime *prtd;
struct snd_soc_card *card;
struct acp5x_platform_info *pinfo;
struct i2s_dev_data *adata;
u32 val;
u32 reg_val, frmt_reg;
u32 lrclk_div_val, bclk_div_val;
lrclk_div_val = 0;
bclk_div_val = 0;
prtd = asoc_substream_to_rtd(substream);
rtd = substream->runtime->private_data;
card = prtd->card;
adata = snd_soc_dai_get_drvdata(dai);
pinfo = snd_soc_card_get_drvdata(card);
if (pinfo) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
rtd->i2s_instance = pinfo->play_i2s_instance;
else
rtd->i2s_instance = pinfo->cap_i2s_instance;
}
/* These values are as per Hardware Spec */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8:
case SNDRV_PCM_FORMAT_S8:
rtd->xfer_resolution = 0x0;
break;
case SNDRV_PCM_FORMAT_S16_LE:
rtd->xfer_resolution = 0x02;
break;
case SNDRV_PCM_FORMAT_S24_LE:
rtd->xfer_resolution = 0x04;
break;
case SNDRV_PCM_FORMAT_S32_LE:
rtd->xfer_resolution = 0x05;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_ITER;
frmt_reg = ACP_HSTDM_TXFRMT;
break;
case I2S_SP_INSTANCE:
default:
reg_val = ACP_I2STDM_ITER;
frmt_reg = ACP_I2STDM_TXFRMT;
}
} else {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_IRER;
frmt_reg = ACP_HSTDM_RXFRMT;
break;
case I2S_SP_INSTANCE:
default:
reg_val = ACP_I2STDM_IRER;
frmt_reg = ACP_I2STDM_RXFRMT;
}
}
if (adata->tdm_mode) {
val = acp_readl(rtd->acp5x_base + reg_val);
acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
}
val = acp_readl(rtd->acp5x_base + reg_val);
val &= ~ACP5x_ITER_IRER_SAMP_LEN_MASK;
val = val | (rtd->xfer_resolution << 3);
acp_writel(val, rtd->acp5x_base + reg_val);
if (adata->master_mode) {
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
switch (params_rate(params)) {
case 8000:
bclk_div_val = 768;
break;
case 16000:
bclk_div_val = 384;
break;
case 24000:
bclk_div_val = 256;
break;
case 32000:
bclk_div_val = 192;
break;
case 44100:
case 48000:
bclk_div_val = 128;
break;
case 88200:
case 96000:
bclk_div_val = 64;
break;
case 192000:
bclk_div_val = 32;
break;
default:
return -EINVAL;
}
lrclk_div_val = 32;
break;
case SNDRV_PCM_FORMAT_S32_LE:
switch (params_rate(params)) {
case 8000:
bclk_div_val = 384;
break;
case 16000:
bclk_div_val = 192;
break;
case 24000:
bclk_div_val = 128;
break;
case 32000:
bclk_div_val = 96;
break;
case 44100:
case 48000:
bclk_div_val = 64;
break;
case 88200:
case 96000:
bclk_div_val = 32;
break;
case 192000:
bclk_div_val = 16;
break;
default:
return -EINVAL;
}
lrclk_div_val = 64;
break;
default:
return -EINVAL;
}
rtd->lrclk_div = lrclk_div_val;
rtd->bclk_div = bclk_div_val;
}
return 0;
}
static int acp5x_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct i2s_stream_instance *rtd;
struct i2s_dev_data *adata;
u32 ret, val, period_bytes, reg_val, ier_val, water_val;
u32 buf_size, buf_reg;
adata = snd_soc_dai_get_drvdata(dai);
rtd = substream->runtime->private_data;
period_bytes = frames_to_bytes(substream->runtime,
substream->runtime->period_size);
buf_size = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
rtd->bytescount = acp_get_byte_count(rtd,
substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
water_val =
ACP_HS_TX_INTR_WATERMARK_SIZE;
reg_val = ACP_HSTDM_ITER;
ier_val = ACP_HSTDM_IER;
buf_reg = ACP_HS_TX_RINGBUFSIZE;
break;
case I2S_SP_INSTANCE:
default:
water_val =
ACP_I2S_TX_INTR_WATERMARK_SIZE;
reg_val = ACP_I2STDM_ITER;
ier_val = ACP_I2STDM_IER;
buf_reg = ACP_I2S_TX_RINGBUFSIZE;
}
} else {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
water_val =
ACP_HS_RX_INTR_WATERMARK_SIZE;
reg_val = ACP_HSTDM_IRER;
ier_val = ACP_HSTDM_IER;
buf_reg = ACP_HS_RX_RINGBUFSIZE;
break;
case I2S_SP_INSTANCE:
default:
water_val =
ACP_I2S_RX_INTR_WATERMARK_SIZE;
reg_val = ACP_I2STDM_IRER;
ier_val = ACP_I2STDM_IER;
buf_reg = ACP_I2S_RX_RINGBUFSIZE;
}
}
acp_writel(period_bytes, rtd->acp5x_base + water_val);
acp_writel(buf_size, rtd->acp5x_base + buf_reg);
if (adata->master_mode)
acp5x_set_i2s_clk(adata, rtd);
val = acp_readl(rtd->acp5x_base + reg_val);
val = val | BIT(0);
acp_writel(val, rtd->acp5x_base + reg_val);
acp_writel(1, rtd->acp5x_base + ier_val);
ret = 0;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_ITER;
break;
case I2S_SP_INSTANCE:
default:
reg_val = ACP_I2STDM_ITER;
}
} else {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_IRER;
break;
case I2S_SP_INSTANCE:
default:
reg_val = ACP_I2STDM_IRER;
}
}
val = acp_readl(rtd->acp5x_base + reg_val);
val = val & ~BIT(0);
acp_writel(val, rtd->acp5x_base + reg_val);
if (!(acp_readl(rtd->acp5x_base + ACP_HSTDM_ITER) & BIT(0)) &&
!(acp_readl(rtd->acp5x_base + ACP_HSTDM_IRER) & BIT(0)))
acp_writel(0, rtd->acp5x_base + ACP_HSTDM_IER);
if (!(acp_readl(rtd->acp5x_base + ACP_I2STDM_ITER) & BIT(0)) &&
!(acp_readl(rtd->acp5x_base + ACP_I2STDM_IRER) & BIT(0)))
acp_writel(0, rtd->acp5x_base + ACP_I2STDM_IER);
ret = 0;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct snd_soc_dai_ops acp5x_i2s_dai_ops = {
.hw_params = acp5x_i2s_hwparams,
.trigger = acp5x_i2s_trigger,
.set_fmt = acp5x_i2s_set_fmt,
.set_tdm_slot = acp5x_i2s_set_tdm_slot,
};
static const struct snd_soc_component_driver acp5x_dai_component = {
.name = "acp5x-i2s",
.legacy_dai_naming = 1,
};
static struct snd_soc_dai_driver acp5x_i2s_dai = {
.playback = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 96000,
},
.ops = &acp5x_i2s_dai_ops,
};
static int acp5x_dai_probe(struct platform_device *pdev)
{
struct resource *res;
struct i2s_dev_data *adata;
int ret;
adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
GFP_KERNEL);
if (!adata)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENOMEM;
}
adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!adata->acp5x_base)
return -ENOMEM;
adata->master_mode = I2S_MASTER_MODE_ENABLE;
dev_set_drvdata(&pdev->dev, adata);
ret = devm_snd_soc_register_component(&pdev->dev,
&acp5x_dai_component,
&acp5x_i2s_dai, 1);
if (ret)
dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
return ret;
}
static struct platform_driver acp5x_dai_driver = {
.probe = acp5x_dai_probe,
.driver = {
.name = "acp5x_i2s_playcap",
},
};
module_platform_driver(acp5x_dai_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP5.x CPU DAI Driver");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/vangogh/acp5x-i2s.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD ALSA SoC PCM Driver
//
// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "acp5x.h"
#define DRV_NAME "acp5x_i2s_dma"
static const struct snd_pcm_hardware acp5x_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp5x_pcm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
{
struct i2s_dev_data *vg_i2s_data;
u16 irq_flag;
u32 val;
vg_i2s_data = dev_id;
if (!vg_i2s_data)
return IRQ_NONE;
irq_flag = 0;
val = acp_readl(vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
if ((val & BIT(HS_TX_THRESHOLD)) && vg_i2s_data->play_stream) {
acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
ACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(vg_i2s_data->play_stream);
irq_flag = 1;
}
if ((val & BIT(I2S_TX_THRESHOLD)) && vg_i2s_data->i2ssp_play_stream) {
acp_writel(BIT(I2S_TX_THRESHOLD),
vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(vg_i2s_data->i2ssp_play_stream);
irq_flag = 1;
}
if ((val & BIT(HS_RX_THRESHOLD)) && vg_i2s_data->capture_stream) {
acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
ACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(vg_i2s_data->capture_stream);
irq_flag = 1;
}
if ((val & BIT(I2S_RX_THRESHOLD)) && vg_i2s_data->i2ssp_capture_stream) {
acp_writel(BIT(I2S_RX_THRESHOLD),
vg_i2s_data->acp5x_base + ACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(vg_i2s_data->i2ssp_capture_stream);
irq_flag = 1;
}
if (irq_flag)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void config_acp5x_dma(struct i2s_stream_instance *rtd, int direction)
{
u16 page_idx;
u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
u32 reg_dma_size, reg_fifo_size;
dma_addr_t addr;
addr = rtd->dma_addr;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
val = ACP_SRAM_HS_PB_PTE_OFFSET;
break;
case I2S_SP_INSTANCE:
default:
val = ACP_SRAM_SP_PB_PTE_OFFSET;
}
} else {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
val = ACP_SRAM_HS_CP_PTE_OFFSET;
break;
case I2S_SP_INSTANCE:
default:
val = ACP_SRAM_SP_CP_PTE_OFFSET;
}
}
/* Group Enable */
acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
high |= BIT(31);
acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val + 4);
/* Move to next physically contiguous page */
val += 8;
addr += PAGE_SIZE;
}
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
reg_dma_size = ACP_HS_TX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
HS_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_HS_TX_FIFOADDR;
reg_fifo_size = ACP_HS_TX_FIFOSIZE;
acp_writel(I2S_HS_TX_MEM_WINDOW_START,
rtd->acp5x_base + ACP_HS_TX_RINGBUFADDR);
break;
case I2S_SP_INSTANCE:
default:
reg_dma_size = ACP_I2S_TX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
SP_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
acp_writel(I2S_SP_TX_MEM_WINDOW_START,
rtd->acp5x_base + ACP_I2S_TX_RINGBUFADDR);
}
} else {
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
reg_dma_size = ACP_HS_RX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
HS_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_HS_RX_FIFOADDR;
reg_fifo_size = ACP_HS_RX_FIFOSIZE;
acp_writel(I2S_HS_RX_MEM_WINDOW_START,
rtd->acp5x_base + ACP_HS_RX_RINGBUFADDR);
break;
case I2S_SP_INSTANCE:
default:
reg_dma_size = ACP_I2S_RX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
SP_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
acp_writel(I2S_SP_RX_MEM_WINDOW_START,
rtd->acp5x_base + ACP_I2S_RX_RINGBUFADDR);
}
}
acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
| BIT(I2S_TX_THRESHOLD) | BIT(HS_TX_THRESHOLD),
rtd->acp5x_base + ACP_EXTERNAL_INTR_CNTL);
}
static int acp5x_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct snd_soc_pcm_runtime *prtd;
struct i2s_dev_data *adata;
struct i2s_stream_instance *i2s_data;
int ret;
runtime = substream->runtime;
prtd = asoc_substream_to_rtd(substream);
component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
adata = dev_get_drvdata(component->dev);
i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
if (!i2s_data)
return -ENOMEM;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = acp5x_pcm_hardware_playback;
else
runtime->hw = acp5x_pcm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(i2s_data);
return ret;
}
i2s_data->acp5x_base = adata->acp5x_base;
runtime->private_data = i2s_data;
return ret;
}
static int acp5x_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct i2s_stream_instance *rtd;
struct snd_soc_pcm_runtime *prtd;
struct snd_soc_card *card;
struct acp5x_platform_info *pinfo;
struct i2s_dev_data *adata;
u64 size;
prtd = asoc_substream_to_rtd(substream);
card = prtd->card;
pinfo = snd_soc_card_get_drvdata(card);
adata = dev_get_drvdata(component->dev);
rtd = substream->runtime->private_data;
if (!rtd)
return -EINVAL;
if (pinfo) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
rtd->i2s_instance = pinfo->play_i2s_instance;
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
adata->play_stream = substream;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_play_stream = substream;
}
} else {
rtd->i2s_instance = pinfo->cap_i2s_instance;
switch (rtd->i2s_instance) {
case I2S_HS_INSTANCE:
adata->capture_stream = substream;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_capture_stream = substream;
}
}
} else {
dev_err(component->dev, "pinfo failed\n");
return -EINVAL;
}
size = params_buffer_bytes(params);
rtd->dma_addr = substream->runtime->dma_addr;
rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
config_acp5x_dma(rtd, substream->stream);
return 0;
}
static snd_pcm_uframes_t acp5x_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct i2s_stream_instance *rtd;
u32 pos;
u32 buffersize;
u64 bytescount;
rtd = substream->runtime->private_data;
buffersize = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
bytescount = acp_get_byte_count(rtd, substream->stream);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(substream->runtime, pos);
}
static int acp5x_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, MIN_BUFFER, MAX_BUFFER);
return 0;
}
static int acp5x_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *prtd;
struct i2s_dev_data *adata;
struct i2s_stream_instance *ins;
prtd = asoc_substream_to_rtd(substream);
component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
adata = dev_get_drvdata(component->dev);
ins = substream->runtime->private_data;
if (!ins)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (ins->i2s_instance) {
case I2S_HS_INSTANCE:
adata->play_stream = NULL;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_play_stream = NULL;
}
} else {
switch (ins->i2s_instance) {
case I2S_HS_INSTANCE:
adata->capture_stream = NULL;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_capture_stream = NULL;
}
}
kfree(ins);
return 0;
}
static const struct snd_soc_component_driver acp5x_i2s_component = {
.name = DRV_NAME,
.open = acp5x_dma_open,
.close = acp5x_dma_close,
.hw_params = acp5x_dma_hw_params,
.pointer = acp5x_dma_pointer,
.pcm_construct = acp5x_dma_new,
};
static int acp5x_audio_probe(struct platform_device *pdev)
{
struct resource *res;
struct i2s_dev_data *adata;
unsigned int irqflags;
int status;
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "platform_data not retrieved\n");
return -ENODEV;
}
irqflags = *((unsigned int *)(pdev->dev.platform_data));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
if (!adata)
return -ENOMEM;
adata->acp5x_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!adata->acp5x_base)
return -ENOMEM;
status = platform_get_irq(pdev, 0);
if (status < 0)
return status;
adata->i2s_irq = status;
dev_set_drvdata(&pdev->dev, adata);
status = devm_snd_soc_register_component(&pdev->dev,
&acp5x_i2s_component,
NULL, 0);
if (status) {
dev_err(&pdev->dev, "Fail to register acp i2s component\n");
return status;
}
status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
irqflags, "ACP5x_I2S_IRQ", adata);
if (status) {
dev_err(&pdev->dev, "ACP5x I2S IRQ request failed\n");
return status;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void acp5x_audio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused acp5x_pcm_resume(struct device *dev)
{
struct i2s_dev_data *adata;
struct i2s_stream_instance *rtd;
u32 val;
adata = dev_get_drvdata(dev);
if (adata->play_stream && adata->play_stream->runtime) {
rtd = adata->play_stream->runtime->private_data;
config_acp5x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_HSTDM_ITER);
if (adata->tdm_mode == TDM_ENABLE) {
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_HSTDM_TXFRMT);
val = acp_readl(adata->acp5x_base + ACP_HSTDM_ITER);
acp_writel(val | 0x2, adata->acp5x_base + ACP_HSTDM_ITER);
}
}
if (adata->i2ssp_play_stream && adata->i2ssp_play_stream->runtime) {
rtd = adata->i2ssp_play_stream->runtime->private_data;
config_acp5x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_I2STDM_ITER);
if (adata->tdm_mode == TDM_ENABLE) {
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_I2STDM_TXFRMT);
val = acp_readl(adata->acp5x_base + ACP_I2STDM_ITER);
acp_writel(val | 0x2, adata->acp5x_base + ACP_I2STDM_ITER);
}
}
if (adata->capture_stream && adata->capture_stream->runtime) {
rtd = adata->capture_stream->runtime->private_data;
config_acp5x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_HSTDM_IRER);
if (adata->tdm_mode == TDM_ENABLE) {
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_HSTDM_RXFRMT);
val = acp_readl(adata->acp5x_base + ACP_HSTDM_IRER);
acp_writel(val | 0x2, adata->acp5x_base + ACP_HSTDM_IRER);
}
}
if (adata->i2ssp_capture_stream && adata->i2ssp_capture_stream->runtime) {
rtd = adata->i2ssp_capture_stream->runtime->private_data;
config_acp5x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_I2STDM_IRER);
if (adata->tdm_mode == TDM_ENABLE) {
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_I2STDM_RXFRMT);
val = acp_readl(adata->acp5x_base + ACP_I2STDM_IRER);
acp_writel(val | 0x2, adata->acp5x_base + ACP_I2STDM_IRER);
}
}
acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
return 0;
}
static int __maybe_unused acp5x_pcm_suspend(struct device *dev)
{
struct i2s_dev_data *adata;
adata = dev_get_drvdata(dev);
acp_writel(0, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
return 0;
}
static int __maybe_unused acp5x_pcm_runtime_resume(struct device *dev)
{
struct i2s_dev_data *adata;
adata = dev_get_drvdata(dev);
acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
return 0;
}
static const struct dev_pm_ops acp5x_pm_ops = {
SET_RUNTIME_PM_OPS(acp5x_pcm_suspend,
acp5x_pcm_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(acp5x_pcm_suspend, acp5x_pcm_resume)
};
static struct platform_driver acp5x_dma_driver = {
.probe = acp5x_audio_probe,
.remove_new = acp5x_audio_remove,
.driver = {
.name = "acp5x_i2s_dma",
.pm = &acp5x_pm_ops,
},
};
module_platform_driver(acp5x_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP 5.x PCM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/vangogh/acp5x-pcm-dma.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD Vangogh ACP PCI Driver
//
// Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include "acp5x.h"
struct acp5x_dev_data {
void __iomem *acp5x_base;
bool acp5x_audio_mode;
struct resource *res;
struct platform_device *pdev[ACP5x_DEVS];
};
static int acp5x_power_on(void __iomem *acp5x_base)
{
u32 val;
int timeout;
val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
if (val == 0)
return val;
if ((val & ACP_PGFSM_STATUS_MASK) !=
ACP_POWER_ON_IN_PROGRESS)
acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
acp5x_base + ACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
val = acp_readl(acp5x_base + ACP_PGFSM_STATUS);
if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_ON)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int acp5x_reset(void __iomem *acp5x_base)
{
u32 val;
int timeout;
acp_writel(1, acp5x_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = acp_readl(acp5x_base + ACP_SOFT_RESET);
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
break;
cpu_relax();
}
acp_writel(0, acp5x_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = acp_readl(acp5x_base + ACP_SOFT_RESET);
if (!val)
return 0;
cpu_relax();
}
return -ETIMEDOUT;
}
static void acp5x_enable_interrupts(void __iomem *acp5x_base)
{
acp_writel(0x01, acp5x_base + ACP_EXTERNAL_INTR_ENB);
}
static void acp5x_disable_interrupts(void __iomem *acp5x_base)
{
acp_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp5x_base +
ACP_EXTERNAL_INTR_STAT);
acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_CNTL);
acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_ENB);
}
static int acp5x_init(void __iomem *acp5x_base)
{
int ret;
/* power on */
ret = acp5x_power_on(acp5x_base);
if (ret) {
pr_err("ACP5x power on failed\n");
return ret;
}
acp_writel(0x01, acp5x_base + ACP_CONTROL);
/* Reset */
ret = acp5x_reset(acp5x_base);
if (ret) {
pr_err("ACP5x reset failed\n");
return ret;
}
acp_writel(0x03, acp5x_base + ACP_CLKMUX_SEL);
acp5x_enable_interrupts(acp5x_base);
return 0;
}
static int acp5x_deinit(void __iomem *acp5x_base)
{
int ret;
acp5x_disable_interrupts(acp5x_base);
/* Reset */
ret = acp5x_reset(acp5x_base);
if (ret) {
pr_err("ACP5x reset failed\n");
return ret;
}
acp_writel(0x00, acp5x_base + ACP_CLKMUX_SEL);
acp_writel(0x00, acp5x_base + ACP_CONTROL);
return 0;
}
static int snd_acp5x_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct acp5x_dev_data *adata;
struct platform_device_info pdevinfo[ACP5x_DEVS];
unsigned int irqflags, flag;
int ret, i;
u32 addr, val;
/* Return if acp config flag is defined */
flag = snd_amd_acp_find_config(pci);
if (flag)
return -ENODEV;
irqflags = IRQF_SHARED;
if (pci->revision != 0x50)
return -ENODEV;
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
return -ENODEV;
}
ret = pci_request_regions(pci, "AMD ACP5x audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
adata = devm_kzalloc(&pci->dev, sizeof(struct acp5x_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
goto release_regions;
}
addr = pci_resource_start(pci, 0);
adata->acp5x_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
if (!adata->acp5x_base) {
ret = -ENOMEM;
goto release_regions;
}
pci_set_master(pci);
pci_set_drvdata(pci, adata);
ret = acp5x_init(adata->acp5x_base);
if (ret)
goto release_regions;
val = acp_readl(adata->acp5x_base + ACP_PIN_CONFIG);
switch (val) {
case I2S_MODE:
adata->res = devm_kzalloc(&pci->dev,
sizeof(struct resource) * ACP5x_RES,
GFP_KERNEL);
if (!adata->res) {
ret = -ENOMEM;
goto de_init;
}
adata->res[0].name = "acp5x_i2s_iomem";
adata->res[0].flags = IORESOURCE_MEM;
adata->res[0].start = addr;
adata->res[0].end = addr + (ACP5x_REG_END - ACP5x_REG_START);
adata->res[1].name = "acp5x_i2s_sp";
adata->res[1].flags = IORESOURCE_MEM;
adata->res[1].start = addr + ACP5x_I2STDM_REG_START;
adata->res[1].end = addr + ACP5x_I2STDM_REG_END;
adata->res[2].name = "acp5x_i2s_hs";
adata->res[2].flags = IORESOURCE_MEM;
adata->res[2].start = addr + ACP5x_HS_TDM_REG_START;
adata->res[2].end = addr + ACP5x_HS_TDM_REG_END;
adata->res[3].name = "acp5x_i2s_irq";
adata->res[3].flags = IORESOURCE_IRQ;
adata->res[3].start = pci->irq;
adata->res[3].end = adata->res[3].start;
adata->acp5x_audio_mode = ACP5x_I2S_MODE;
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo[0].name = "acp5x_i2s_dma";
pdevinfo[0].id = 0;
pdevinfo[0].parent = &pci->dev;
pdevinfo[0].num_res = 4;
pdevinfo[0].res = &adata->res[0];
pdevinfo[0].data = &irqflags;
pdevinfo[0].size_data = sizeof(irqflags);
pdevinfo[1].name = "acp5x_i2s_playcap";
pdevinfo[1].id = 0;
pdevinfo[1].parent = &pci->dev;
pdevinfo[1].num_res = 1;
pdevinfo[1].res = &adata->res[1];
pdevinfo[2].name = "acp5x_i2s_playcap";
pdevinfo[2].id = 1;
pdevinfo[2].parent = &pci->dev;
pdevinfo[2].num_res = 1;
pdevinfo[2].res = &adata->res[2];
pdevinfo[3].name = "acp5x_mach";
pdevinfo[3].id = 0;
pdevinfo[3].parent = &pci->dev;
for (i = 0; i < ACP5x_DEVS; i++) {
adata->pdev[i] =
platform_device_register_full(&pdevinfo[i]);
if (IS_ERR(adata->pdev[i])) {
dev_err(&pci->dev, "cannot register %s device\n",
pdevinfo[i].name);
ret = PTR_ERR(adata->pdev[i]);
goto unregister_devs;
}
}
break;
default:
dev_info(&pci->dev, "ACP audio mode : %d\n", val);
}
pm_runtime_set_autosuspend_delay(&pci->dev, 2000);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return 0;
unregister_devs:
for (--i; i >= 0; i--)
platform_device_unregister(adata->pdev[i]);
de_init:
if (acp5x_deinit(adata->acp5x_base))
dev_err(&pci->dev, "ACP de-init failed\n");
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
}
static int __maybe_unused snd_acp5x_suspend(struct device *dev)
{
int ret;
struct acp5x_dev_data *adata;
adata = dev_get_drvdata(dev);
ret = acp5x_deinit(adata->acp5x_base);
if (ret)
dev_err(dev, "ACP de-init failed\n");
else
dev_dbg(dev, "ACP de-initialized\n");
return ret;
}
static int __maybe_unused snd_acp5x_resume(struct device *dev)
{
int ret;
struct acp5x_dev_data *adata;
adata = dev_get_drvdata(dev);
ret = acp5x_init(adata->acp5x_base);
if (ret) {
dev_err(dev, "ACP init failed\n");
return ret;
}
return 0;
}
static const struct dev_pm_ops acp5x_pm = {
SET_RUNTIME_PM_OPS(snd_acp5x_suspend,
snd_acp5x_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(snd_acp5x_suspend, snd_acp5x_resume)
};
static void snd_acp5x_remove(struct pci_dev *pci)
{
struct acp5x_dev_data *adata;
int i, ret;
adata = pci_get_drvdata(pci);
if (adata->acp5x_audio_mode == ACP5x_I2S_MODE) {
for (i = 0; i < ACP5x_DEVS; i++)
platform_device_unregister(adata->pdev[i]);
}
ret = acp5x_deinit(adata->acp5x_base);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
pci_release_regions(pci);
pci_disable_device(pci);
}
static const struct pci_device_id snd_acp5x_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_acp5x_ids);
static struct pci_driver acp5x_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_acp5x_ids,
.probe = snd_acp5x_probe,
.remove = snd_acp5x_remove,
.driver = {
.pm = &acp5x_pm,
}
};
module_pci_driver(acp5x_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD Vangogh ACP PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/vangogh/pci-acp5x.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD Renoir ACP PCI Driver
//
//Copyright 2020 Advanced Micro Devices, Inc.
#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include "rn_acp3x.h"
static int acp_power_gating;
module_param(acp_power_gating, int, 0644);
MODULE_PARM_DESC(acp_power_gating, "Enable acp power gating");
/*
* dmic_acpi_check = -1 - Use ACPI/DMI method to detect the DMIC hardware presence at runtime
* = 0 - Skip the DMIC device creation and return probe failure
* = 1 - Force DMIC support
*/
static int dmic_acpi_check = ACP_DMIC_AUTO;
module_param(dmic_acpi_check, bint, 0644);
MODULE_PARM_DESC(dmic_acpi_check, "Digital microphone presence (-1=auto, 0=none, 1=force)");
struct acp_dev_data {
void __iomem *acp_base;
struct resource *res;
struct platform_device *pdev[ACP_DEVS];
};
static int rn_acp_power_on(void __iomem *acp_base)
{
u32 val;
int timeout;
val = rn_readl(acp_base + ACP_PGFSM_STATUS);
if (val == 0)
return val;
if ((val & ACP_PGFSM_STATUS_MASK) !=
ACP_POWER_ON_IN_PROGRESS)
rn_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
acp_base + ACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
val = rn_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int rn_acp_power_off(void __iomem *acp_base)
{
u32 val;
int timeout;
rn_writel(ACP_PGFSM_CNTL_POWER_OFF_MASK,
acp_base + ACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
val = rn_readl(acp_base + ACP_PGFSM_STATUS);
if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_OFF)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int rn_acp_reset(void __iomem *acp_base)
{
u32 val;
int timeout;
rn_writel(1, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = rn_readl(acp_base + ACP_SOFT_RESET);
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
break;
cpu_relax();
}
rn_writel(0, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = rn_readl(acp_base + ACP_SOFT_RESET);
if (!val)
return 0;
cpu_relax();
}
return -ETIMEDOUT;
}
static void rn_acp_enable_interrupts(void __iomem *acp_base)
{
u32 ext_intr_ctrl;
rn_writel(0x01, acp_base + ACP_EXTERNAL_INTR_ENB);
ext_intr_ctrl = rn_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_intr_ctrl |= ACP_ERROR_MASK;
rn_writel(ext_intr_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
static void rn_acp_disable_interrupts(void __iomem *acp_base)
{
rn_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
ACP_EXTERNAL_INTR_STAT);
rn_writel(0x00, acp_base + ACP_EXTERNAL_INTR_ENB);
}
static int rn_acp_init(void __iomem *acp_base)
{
int ret;
/* power on */
ret = rn_acp_power_on(acp_base);
if (ret) {
pr_err("ACP power on failed\n");
return ret;
}
rn_writel(0x01, acp_base + ACP_CONTROL);
/* Reset */
ret = rn_acp_reset(acp_base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
rn_writel(0x03, acp_base + ACP_CLKMUX_SEL);
rn_acp_enable_interrupts(acp_base);
return 0;
}
static int rn_acp_deinit(void __iomem *acp_base)
{
int ret;
rn_acp_disable_interrupts(acp_base);
/* Reset */
ret = rn_acp_reset(acp_base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
rn_writel(0x00, acp_base + ACP_CLKMUX_SEL);
rn_writel(0x00, acp_base + ACP_CONTROL);
/* power off */
if (acp_power_gating) {
ret = rn_acp_power_off(acp_base);
if (ret) {
pr_err("ACP power off failed\n");
return ret;
}
}
return 0;
}
static const struct dmi_system_id rn_acp_quirk_table[] = {
{
/* Lenovo IdeaPad S340-14API */
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "81NB"),
}
},
{
/* Lenovo IdeaPad Flex 5 14ARE05 */
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "81X2"),
}
},
{
/* Lenovo IdeaPad 5 15ARE05 */
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "81YQ"),
}
},
{
/* Lenovo ThinkPad E14 Gen 2 */
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "20T6CTO1WW"),
}
},
{
/* Lenovo ThinkPad X395 */
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "20NLCTO1WW"),
}
},
{}
};
static int snd_rn_acp_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct acp_dev_data *adata;
struct platform_device_info pdevinfo[ACP_DEVS];
#if defined(CONFIG_ACPI)
acpi_handle handle;
acpi_integer dmic_status;
#endif
const struct dmi_system_id *dmi_id;
unsigned int irqflags, flag;
int ret, index;
u32 addr;
/* Return if acp config flag is defined */
flag = snd_amd_acp_find_config(pci);
if (flag)
return -ENODEV;
/* Renoir device check */
if (pci->revision != 0x01)
return -ENODEV;
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
return -ENODEV;
}
ret = pci_request_regions(pci, "AMD ACP3x audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
adata = devm_kzalloc(&pci->dev, sizeof(struct acp_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
goto release_regions;
}
/* check for msi interrupt support */
ret = pci_enable_msi(pci);
if (ret)
/* msi is not enabled */
irqflags = IRQF_SHARED;
else
/* msi is enabled */
irqflags = 0;
addr = pci_resource_start(pci, 0);
adata->acp_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
if (!adata->acp_base) {
ret = -ENOMEM;
goto disable_msi;
}
pci_set_master(pci);
pci_set_drvdata(pci, adata);
ret = rn_acp_init(adata->acp_base);
if (ret)
goto disable_msi;
if (!dmic_acpi_check) {
ret = -ENODEV;
goto de_init;
} else if (dmic_acpi_check == ACP_DMIC_AUTO) {
#if defined(CONFIG_ACPI)
handle = ACPI_HANDLE(&pci->dev);
ret = acpi_evaluate_integer(handle, "_WOV", NULL, &dmic_status);
if (ACPI_FAILURE(ret)) {
ret = -ENODEV;
goto de_init;
}
if (!dmic_status) {
ret = -ENODEV;
goto de_init;
}
#endif
dmi_id = dmi_first_match(rn_acp_quirk_table);
if (dmi_id && !dmi_id->driver_data) {
dev_info(&pci->dev, "ACPI settings override using DMI (ACP mic is not present)");
ret = -ENODEV;
goto de_init;
}
}
adata->res = devm_kzalloc(&pci->dev,
sizeof(struct resource) * 2,
GFP_KERNEL);
if (!adata->res) {
ret = -ENOMEM;
goto de_init;
}
adata->res[0].name = "acp_pdm_iomem";
adata->res[0].flags = IORESOURCE_MEM;
adata->res[0].start = addr;
adata->res[0].end = addr + (ACP_REG_END - ACP_REG_START);
adata->res[1].name = "acp_pdm_irq";
adata->res[1].flags = IORESOURCE_IRQ;
adata->res[1].start = pci->irq;
adata->res[1].end = pci->irq;
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo[0].name = "acp_rn_pdm_dma";
pdevinfo[0].id = 0;
pdevinfo[0].parent = &pci->dev;
pdevinfo[0].num_res = 2;
pdevinfo[0].res = adata->res;
pdevinfo[0].data = &irqflags;
pdevinfo[0].size_data = sizeof(irqflags);
pdevinfo[1].name = "dmic-codec";
pdevinfo[1].id = 0;
pdevinfo[1].parent = &pci->dev;
pdevinfo[2].name = "acp_pdm_mach";
pdevinfo[2].id = 0;
pdevinfo[2].parent = &pci->dev;
for (index = 0; index < ACP_DEVS; index++) {
adata->pdev[index] =
platform_device_register_full(&pdevinfo[index]);
if (IS_ERR(adata->pdev[index])) {
dev_err(&pci->dev, "cannot register %s device\n",
pdevinfo[index].name);
ret = PTR_ERR(adata->pdev[index]);
goto unregister_devs;
}
}
pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return 0;
unregister_devs:
for (index = 0; index < ACP_DEVS; index++)
platform_device_unregister(adata->pdev[index]);
de_init:
if (rn_acp_deinit(adata->acp_base))
dev_err(&pci->dev, "ACP de-init failed\n");
disable_msi:
pci_disable_msi(pci);
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
}
static int snd_rn_acp_suspend(struct device *dev)
{
int ret;
struct acp_dev_data *adata;
adata = dev_get_drvdata(dev);
ret = rn_acp_deinit(adata->acp_base);
if (ret)
dev_err(dev, "ACP de-init failed\n");
else
dev_dbg(dev, "ACP de-initialized\n");
return ret;
}
static int snd_rn_acp_resume(struct device *dev)
{
int ret;
struct acp_dev_data *adata;
adata = dev_get_drvdata(dev);
ret = rn_acp_init(adata->acp_base);
if (ret) {
dev_err(dev, "ACP init failed\n");
return ret;
}
return 0;
}
static const struct dev_pm_ops rn_acp_pm = {
.runtime_suspend = snd_rn_acp_suspend,
.runtime_resume = snd_rn_acp_resume,
.suspend = snd_rn_acp_suspend,
.resume = snd_rn_acp_resume,
.restore = snd_rn_acp_resume,
.poweroff = snd_rn_acp_suspend,
};
static void snd_rn_acp_remove(struct pci_dev *pci)
{
struct acp_dev_data *adata;
int ret, index;
adata = pci_get_drvdata(pci);
for (index = 0; index < ACP_DEVS; index++)
platform_device_unregister(adata->pdev[index]);
ret = rn_acp_deinit(adata->acp_base);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
pci_disable_msi(pci);
pci_release_regions(pci);
pci_disable_device(pci);
}
static const struct pci_device_id snd_rn_acp_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_rn_acp_ids);
static struct pci_driver rn_acp_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_rn_acp_ids,
.probe = snd_rn_acp_probe,
.remove = snd_rn_acp_remove,
.driver = {
.pm = &rn_acp_pm,
}
};
module_pci_driver(rn_acp_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP Renoir PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/renoir/rn-pci-acp3x.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD ALSA SoC PDM Driver
//
//Copyright 2020 Advanced Micro Devices, Inc.
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "rn_acp3x.h"
#define DRV_NAME "acp_rn_pdm_dma"
static int pdm_gain = 3;
module_param(pdm_gain, int, 0644);
MODULE_PARM_DESC(pdm_gain, "Gain control (0-3)");
static const struct snd_pcm_hardware acp_pdm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static irqreturn_t pdm_irq_handler(int irq, void *dev_id)
{
struct pdm_dev_data *rn_pdm_data;
u16 cap_flag;
u32 val;
rn_pdm_data = dev_id;
if (!rn_pdm_data)
return IRQ_NONE;
cap_flag = 0;
val = rn_readl(rn_pdm_data->acp_base + ACP_EXTERNAL_INTR_STAT);
if ((val & BIT(PDM_DMA_STAT)) && rn_pdm_data->capture_stream) {
rn_writel(BIT(PDM_DMA_STAT), rn_pdm_data->acp_base +
ACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(rn_pdm_data->capture_stream);
cap_flag = 1;
}
if (cap_flag)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void init_pdm_ring_buffer(u32 physical_addr,
u32 buffer_size,
u32 watermark_size,
void __iomem *acp_base)
{
rn_writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
rn_writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
rn_writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
rn_writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
}
static void enable_pdm_clock(void __iomem *acp_base)
{
u32 pdm_clk_enable, pdm_ctrl;
pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK;
rn_writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
pdm_ctrl = rn_readl(acp_base + ACP_WOV_MISC_CTRL);
pdm_ctrl &= ~ACP_WOV_GAIN_CONTROL;
pdm_ctrl |= FIELD_PREP(ACP_WOV_GAIN_CONTROL, clamp(pdm_gain, 0, 3));
rn_writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
}
static void enable_pdm_interrupts(void __iomem *acp_base)
{
u32 ext_int_ctrl;
ext_int_ctrl = rn_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl |= PDM_DMA_INTR_MASK;
rn_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
static void disable_pdm_interrupts(void __iomem *acp_base)
{
u32 ext_int_ctrl;
ext_int_ctrl = rn_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl |= ~PDM_DMA_INTR_MASK;
rn_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
static bool check_pdm_dma_status(void __iomem *acp_base)
{
bool pdm_dma_status;
u32 pdm_enable, pdm_dma_enable;
pdm_dma_status = false;
pdm_enable = rn_readl(acp_base + ACP_WOV_PDM_ENABLE);
pdm_dma_enable = rn_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable &
ACP_PDM_DMA_EN_STATUS))
pdm_dma_status = true;
return pdm_dma_status;
}
static int start_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable;
u32 pdm_dma_enable;
int timeout;
pdm_enable = 0x01;
pdm_dma_enable = 0x01;
enable_pdm_clock(acp_base);
rn_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
rn_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
pdm_dma_enable = rn_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS)
return 0;
udelay(DELAY_US);
}
return -ETIMEDOUT;
}
static int stop_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable, pdm_dma_enable;
int timeout;
pdm_enable = rn_readl(acp_base + ACP_WOV_PDM_ENABLE);
pdm_dma_enable = rn_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if (pdm_dma_enable & 0x01) {
pdm_dma_enable = 0x02;
rn_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
pdm_dma_enable = rn_readl(acp_base +
ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == 0x00)
break;
udelay(DELAY_US);
}
if (timeout == ACP_COUNTER)
return -ETIMEDOUT;
}
if (pdm_enable == ACP_PDM_ENABLE) {
pdm_enable = ACP_PDM_DISABLE;
rn_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
}
rn_writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
return 0;
}
static void config_acp_dma(struct pdm_stream_instance *rtd, int direction)
{
u16 page_idx;
u32 low, high, val;
dma_addr_t addr;
addr = rtd->dma_addr;
val = 0;
/* Group Enable */
rn_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp_base +
ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
rn_writel(PAGE_SIZE_4K_ENABLE, rtd->acp_base +
ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
rn_writel(low, rtd->acp_base + ACP_SCRATCH_REG_0 + val);
high |= BIT(31);
rn_writel(high, rtd->acp_base + ACP_SCRATCH_REG_0 + val + 4);
val += 8;
addr += PAGE_SIZE;
}
}
static int acp_pdm_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct pdm_dev_data *adata;
struct pdm_stream_instance *pdm_data;
int ret;
runtime = substream->runtime;
adata = dev_get_drvdata(component->dev);
pdm_data = kzalloc(sizeof(*pdm_data), GFP_KERNEL);
if (!pdm_data)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = acp_pdm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(pdm_data);
return ret;
}
enable_pdm_interrupts(adata->acp_base);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
adata->capture_stream = substream;
pdm_data->acp_base = adata->acp_base;
runtime->private_data = pdm_data;
return ret;
}
static int acp_pdm_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct pdm_stream_instance *rtd;
size_t size, period_bytes;
rtd = substream->runtime->private_data;
if (!rtd)
return -EINVAL;
size = params_buffer_bytes(params);
period_bytes = params_period_bytes(params);
rtd->dma_addr = substream->runtime->dma_addr;
rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
config_acp_dma(rtd, substream->stream);
init_pdm_ring_buffer(MEM_WINDOW_START, size, period_bytes,
rtd->acp_base);
return 0;
}
static u64 acp_pdm_get_byte_count(struct pdm_stream_instance *rtd,
int direction)
{
union acp_pdm_dma_count byte_count;
byte_count.bcount.high =
rn_readl(rtd->acp_base +
ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
byte_count.bcount.low =
rn_readl(rtd->acp_base +
ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
return byte_count.bytescount;
}
static snd_pcm_uframes_t acp_pdm_dma_pointer(struct snd_soc_component *comp,
struct snd_pcm_substream *stream)
{
struct pdm_stream_instance *rtd;
u32 pos, buffersize;
u64 bytescount;
rtd = stream->runtime->private_data;
buffersize = frames_to_bytes(stream->runtime,
stream->runtime->buffer_size);
bytescount = acp_pdm_get_byte_count(rtd, stream->stream);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(stream->runtime, pos);
}
static int acp_pdm_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, MIN_BUFFER, MAX_BUFFER);
return 0;
}
static int acp_pdm_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct pdm_dev_data *adata = dev_get_drvdata(component->dev);
disable_pdm_interrupts(adata->acp_base);
adata->capture_stream = NULL;
return 0;
}
static int acp_pdm_dai_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct pdm_stream_instance *rtd;
int ret;
bool pdm_status;
unsigned int ch_mask;
rtd = substream->runtime->private_data;
ret = 0;
switch (substream->runtime->channels) {
case TWO_CH:
ch_mask = 0x00;
break;
default:
return -EINVAL;
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
rn_writel(ch_mask, rtd->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
rn_writel(PDM_DECIMATION_FACTOR, rtd->acp_base +
ACP_WOV_PDM_DECIMATION_FACTOR);
rtd->bytescount = acp_pdm_get_byte_count(rtd,
substream->stream);
pdm_status = check_pdm_dma_status(rtd->acp_base);
if (!pdm_status)
ret = start_pdm_dma(rtd->acp_base);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
pdm_status = check_pdm_dma_status(rtd->acp_base);
if (pdm_status)
ret = stop_pdm_dma(rtd->acp_base);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct snd_soc_dai_ops acp_pdm_dai_ops = {
.trigger = acp_pdm_dai_trigger,
};
static struct snd_soc_dai_driver acp_pdm_dai_driver = {
.capture = {
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 48000,
.rate_max = 48000,
},
.ops = &acp_pdm_dai_ops,
};
static const struct snd_soc_component_driver acp_pdm_component = {
.name = DRV_NAME,
.open = acp_pdm_dma_open,
.close = acp_pdm_dma_close,
.hw_params = acp_pdm_dma_hw_params,
.pointer = acp_pdm_dma_pointer,
.pcm_construct = acp_pdm_dma_new,
.legacy_dai_naming = 1,
};
static int acp_pdm_audio_probe(struct platform_device *pdev)
{
struct resource *res;
struct pdm_dev_data *adata;
unsigned int irqflags;
int status;
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "platform_data not retrieved\n");
return -ENODEV;
}
irqflags = *((unsigned int *)(pdev->dev.platform_data));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
if (!adata)
return -ENOMEM;
adata->acp_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!adata->acp_base)
return -ENOMEM;
status = platform_get_irq(pdev, 0);
if (status < 0)
return status;
adata->pdm_irq = status;
adata->capture_stream = NULL;
dev_set_drvdata(&pdev->dev, adata);
status = devm_snd_soc_register_component(&pdev->dev,
&acp_pdm_component,
&acp_pdm_dai_driver, 1);
if (status) {
dev_err(&pdev->dev, "Fail to register acp pdm dai\n");
return -ENODEV;
}
status = devm_request_irq(&pdev->dev, adata->pdm_irq, pdm_irq_handler,
irqflags, "ACP_PDM_IRQ", adata);
if (status) {
dev_err(&pdev->dev, "ACP PDM IRQ request failed\n");
return -ENODEV;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void acp_pdm_audio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int acp_pdm_resume(struct device *dev)
{
struct pdm_dev_data *adata;
struct snd_pcm_runtime *runtime;
struct pdm_stream_instance *rtd;
u32 period_bytes, buffer_len;
adata = dev_get_drvdata(dev);
if (adata->capture_stream && adata->capture_stream->runtime) {
runtime = adata->capture_stream->runtime;
rtd = runtime->private_data;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
config_acp_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
init_pdm_ring_buffer(MEM_WINDOW_START, buffer_len, period_bytes,
adata->acp_base);
}
enable_pdm_interrupts(adata->acp_base);
return 0;
}
static int acp_pdm_runtime_suspend(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
disable_pdm_interrupts(adata->acp_base);
return 0;
}
static int acp_pdm_runtime_resume(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
enable_pdm_interrupts(adata->acp_base);
return 0;
}
static const struct dev_pm_ops acp_pdm_pm_ops = {
.runtime_suspend = acp_pdm_runtime_suspend,
.runtime_resume = acp_pdm_runtime_resume,
.resume = acp_pdm_resume,
};
static struct platform_driver acp_pdm_dma_driver = {
.probe = acp_pdm_audio_probe,
.remove_new = acp_pdm_audio_remove,
.driver = {
.name = "acp_rn_pdm_dma",
.pm = &acp_pdm_pm_ops,
},
};
module_platform_driver(acp_pdm_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP3x Renior PDM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/renoir/acp3x-pdm-dma.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Machine driver for AMD Renoir platform using DMIC
//
//Copyright 2020 Advanced Micro Devices, Inc.
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/io.h>
#include "rn_acp3x.h"
#define DRV_NAME "acp_pdm_mach"
SND_SOC_DAILINK_DEF(acp_pdm,
DAILINK_COMP_ARRAY(COMP_CPU("acp_rn_pdm_dma.0")));
SND_SOC_DAILINK_DEF(dmic_codec,
DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec.0",
"dmic-hifi")));
SND_SOC_DAILINK_DEF(platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_rn_pdm_dma.0")));
static struct snd_soc_dai_link acp_dai_pdm[] = {
{
.name = "acp3x-dmic-capture",
.stream_name = "DMIC capture",
.capture_only = 1,
SND_SOC_DAILINK_REG(acp_pdm, dmic_codec, platform),
},
};
static struct snd_soc_card acp_card = {
.name = "acp",
.owner = THIS_MODULE,
.dai_link = acp_dai_pdm,
.num_links = 1,
};
static int acp_probe(struct platform_device *pdev)
{
int ret;
struct acp_pdm *machine = NULL;
struct snd_soc_card *card;
card = &acp_card;
acp_card.dev = &pdev->dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
return dev_err_probe(&pdev->dev, ret,
"snd_soc_register_card(%s) failed\n",
card->name);
}
return 0;
}
static struct platform_driver acp_mach_driver = {
.driver = {
.name = "acp_pdm_mach",
.pm = &snd_soc_pm_ops,
},
.probe = acp_probe,
};
module_platform_driver(acp_mach_driver);
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/renoir/acp3x-rn.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD ALSA SoC PCM Driver
//
//Copyright 2016 Advanced Micro Devices, Inc.
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "acp3x.h"
#define DRV_NAME "acp3x_rv_i2s_dma"
static const struct snd_pcm_hardware acp3x_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp3x_pcm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
{
struct i2s_dev_data *rv_i2s_data;
u16 play_flag, cap_flag;
u32 val;
rv_i2s_data = dev_id;
if (!rv_i2s_data)
return IRQ_NONE;
play_flag = 0;
cap_flag = 0;
val = rv_readl(rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
if ((val & BIT(BT_TX_THRESHOLD)) && rv_i2s_data->play_stream) {
rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base +
mmACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(rv_i2s_data->play_stream);
play_flag = 1;
}
if ((val & BIT(I2S_TX_THRESHOLD)) &&
rv_i2s_data->i2ssp_play_stream) {
rv_writel(BIT(I2S_TX_THRESHOLD),
rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(rv_i2s_data->i2ssp_play_stream);
play_flag = 1;
}
if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) {
rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base +
mmACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(rv_i2s_data->capture_stream);
cap_flag = 1;
}
if ((val & BIT(I2S_RX_THRESHOLD)) &&
rv_i2s_data->i2ssp_capture_stream) {
rv_writel(BIT(I2S_RX_THRESHOLD),
rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
snd_pcm_period_elapsed(rv_i2s_data->i2ssp_capture_stream);
cap_flag = 1;
}
if (play_flag | cap_flag)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
{
u16 page_idx;
u32 low, high, val, acp_fifo_addr, reg_fifo_addr;
u32 reg_dma_size, reg_fifo_size;
dma_addr_t addr;
addr = rtd->dma_addr;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
val = ACP_SRAM_BT_PB_PTE_OFFSET;
break;
case I2S_SP_INSTANCE:
default:
val = ACP_SRAM_SP_PB_PTE_OFFSET;
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
val = ACP_SRAM_BT_CP_PTE_OFFSET;
break;
case I2S_SP_INSTANCE:
default:
val = ACP_SRAM_SP_CP_PTE_OFFSET;
}
}
/* Group Enable */
rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +
mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);
high |= BIT(31);
rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
+ 4);
/* Move to next physically contiguous page */
val += 8;
addr += PAGE_SIZE;
}
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_dma_size = mmACP_BT_TX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
BT_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = mmACP_BT_TX_FIFOADDR;
reg_fifo_size = mmACP_BT_TX_FIFOSIZE;
rv_writel(I2S_BT_TX_MEM_WINDOW_START,
rtd->acp3x_base + mmACP_BT_TX_RINGBUFADDR);
break;
case I2S_SP_INSTANCE:
default:
reg_dma_size = mmACP_I2S_TX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
SP_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = mmACP_I2S_TX_FIFOADDR;
reg_fifo_size = mmACP_I2S_TX_FIFOSIZE;
rv_writel(I2S_SP_TX_MEM_WINDOW_START,
rtd->acp3x_base + mmACP_I2S_TX_RINGBUFADDR);
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_dma_size = mmACP_BT_RX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
BT_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = mmACP_BT_RX_FIFOADDR;
reg_fifo_size = mmACP_BT_RX_FIFOSIZE;
rv_writel(I2S_BT_RX_MEM_WINDOW_START,
rtd->acp3x_base + mmACP_BT_RX_RINGBUFADDR);
break;
case I2S_SP_INSTANCE:
default:
reg_dma_size = mmACP_I2S_RX_DMA_SIZE;
acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
SP_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = mmACP_I2S_RX_FIFOADDR;
reg_fifo_size = mmACP_I2S_RX_FIFOSIZE;
rv_writel(I2S_SP_RX_MEM_WINDOW_START,
rtd->acp3x_base + mmACP_I2S_RX_RINGBUFADDR);
}
}
rv_writel(DMA_SIZE, rtd->acp3x_base + reg_dma_size);
rv_writel(acp_fifo_addr, rtd->acp3x_base + reg_fifo_addr);
rv_writel(FIFO_SIZE, rtd->acp3x_base + reg_fifo_size);
rv_writel(BIT(I2S_RX_THRESHOLD) | BIT(BT_RX_THRESHOLD)
| BIT(I2S_TX_THRESHOLD) | BIT(BT_TX_THRESHOLD),
rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
}
static int acp3x_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct snd_soc_pcm_runtime *prtd;
struct i2s_dev_data *adata;
struct i2s_stream_instance *i2s_data;
int ret;
runtime = substream->runtime;
prtd = asoc_substream_to_rtd(substream);
component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
adata = dev_get_drvdata(component->dev);
i2s_data = kzalloc(sizeof(*i2s_data), GFP_KERNEL);
if (!i2s_data)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = acp3x_pcm_hardware_playback;
else
runtime->hw = acp3x_pcm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(i2s_data);
return ret;
}
i2s_data->acp3x_base = adata->acp3x_base;
runtime->private_data = i2s_data;
return ret;
}
static int acp3x_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct i2s_stream_instance *rtd;
struct snd_soc_pcm_runtime *prtd;
struct snd_soc_card *card;
struct acp3x_platform_info *pinfo;
struct i2s_dev_data *adata;
u64 size;
prtd = asoc_substream_to_rtd(substream);
card = prtd->card;
pinfo = snd_soc_card_get_drvdata(card);
adata = dev_get_drvdata(component->dev);
rtd = substream->runtime->private_data;
if (!rtd)
return -EINVAL;
if (pinfo) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
rtd->i2s_instance = pinfo->play_i2s_instance;
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
adata->play_stream = substream;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_play_stream = substream;
}
} else {
rtd->i2s_instance = pinfo->cap_i2s_instance;
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
adata->capture_stream = substream;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_capture_stream = substream;
}
}
} else {
pr_err("pinfo failed\n");
}
size = params_buffer_bytes(params);
rtd->dma_addr = substream->runtime->dma_addr;
rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
config_acp3x_dma(rtd, substream->stream);
return 0;
}
static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct i2s_stream_instance *rtd;
u32 pos;
u32 buffersize;
u64 bytescount;
rtd = substream->runtime->private_data;
buffersize = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
bytescount = acp_get_byte_count(rtd, substream->stream);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(substream->runtime, pos);
}
static int acp3x_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, MIN_BUFFER, MAX_BUFFER);
return 0;
}
static int acp3x_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *prtd;
struct i2s_dev_data *adata;
struct i2s_stream_instance *ins;
prtd = asoc_substream_to_rtd(substream);
component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
adata = dev_get_drvdata(component->dev);
ins = substream->runtime->private_data;
if (!ins)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (ins->i2s_instance) {
case I2S_BT_INSTANCE:
adata->play_stream = NULL;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_play_stream = NULL;
}
} else {
switch (ins->i2s_instance) {
case I2S_BT_INSTANCE:
adata->capture_stream = NULL;
break;
case I2S_SP_INSTANCE:
default:
adata->i2ssp_capture_stream = NULL;
}
}
return 0;
}
static const struct snd_soc_component_driver acp3x_i2s_component = {
.name = DRV_NAME,
.open = acp3x_dma_open,
.close = acp3x_dma_close,
.hw_params = acp3x_dma_hw_params,
.pointer = acp3x_dma_pointer,
.pcm_construct = acp3x_dma_new,
};
static int acp3x_audio_probe(struct platform_device *pdev)
{
struct resource *res;
struct i2s_dev_data *adata;
unsigned int irqflags;
int status;
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "platform_data not retrieved\n");
return -ENODEV;
}
irqflags = *((unsigned int *)(pdev->dev.platform_data));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
if (!adata)
return -ENOMEM;
adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!adata->acp3x_base)
return -ENOMEM;
status = platform_get_irq(pdev, 0);
if (status < 0)
return status;
adata->i2s_irq = status;
dev_set_drvdata(&pdev->dev, adata);
status = devm_snd_soc_register_component(&pdev->dev,
&acp3x_i2s_component,
NULL, 0);
if (status) {
dev_err(&pdev->dev, "Fail to register acp i2s component\n");
return -ENODEV;
}
status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
irqflags, "ACP3x_I2S_IRQ", adata);
if (status) {
dev_err(&pdev->dev, "ACP3x I2S IRQ request failed\n");
return -ENODEV;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void acp3x_audio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int acp3x_resume(struct device *dev)
{
struct i2s_dev_data *adata;
u32 val, reg_val, frmt_val;
reg_val = 0;
frmt_val = 0;
adata = dev_get_drvdata(dev);
if (adata->play_stream && adata->play_stream->runtime) {
struct i2s_stream_instance *rtd =
adata->play_stream->runtime->private_data;
config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_val = mmACP_BTTDM_ITER;
frmt_val = mmACP_BTTDM_TXFRMT;
break;
case I2S_SP_INSTANCE:
default:
reg_val = mmACP_I2STDM_ITER;
frmt_val = mmACP_I2STDM_TXFRMT;
}
rv_writel((rtd->xfer_resolution << 3),
rtd->acp3x_base + reg_val);
}
if (adata->capture_stream && adata->capture_stream->runtime) {
struct i2s_stream_instance *rtd =
adata->capture_stream->runtime->private_data;
config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_val = mmACP_BTTDM_IRER;
frmt_val = mmACP_BTTDM_RXFRMT;
break;
case I2S_SP_INSTANCE:
default:
reg_val = mmACP_I2STDM_IRER;
frmt_val = mmACP_I2STDM_RXFRMT;
}
rv_writel((rtd->xfer_resolution << 3),
rtd->acp3x_base + reg_val);
}
if (adata->tdm_mode == TDM_ENABLE) {
rv_writel(adata->tdm_fmt, adata->acp3x_base + frmt_val);
val = rv_readl(adata->acp3x_base + reg_val);
rv_writel(val | 0x2, adata->acp3x_base + reg_val);
}
rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp3x_pcm_runtime_suspend(struct device *dev)
{
struct i2s_dev_data *adata;
adata = dev_get_drvdata(dev);
rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static int acp3x_pcm_runtime_resume(struct device *dev)
{
struct i2s_dev_data *adata;
adata = dev_get_drvdata(dev);
rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
return 0;
}
static const struct dev_pm_ops acp3x_pm_ops = {
.runtime_suspend = acp3x_pcm_runtime_suspend,
.runtime_resume = acp3x_pcm_runtime_resume,
.resume = acp3x_resume,
};
static struct platform_driver acp3x_dma_driver = {
.probe = acp3x_audio_probe,
.remove_new = acp3x_audio_remove,
.driver = {
.name = "acp3x_rv_i2s_dma",
.pm = &acp3x_pm_ops,
},
};
module_platform_driver(acp3x_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:"DRV_NAME);
| linux-master | sound/soc/amd/raven/acp3x-pcm-dma.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD ALSA SoC PCM Driver
//
//Copyright 2016 Advanced Micro Devices, Inc.
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
#include "acp3x.h"
#define DRV_NAME "acp3x_i2s_playcap"
static int acp3x_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct i2s_dev_data *adata;
int mode;
adata = snd_soc_dai_get_drvdata(cpu_dai);
mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
switch (mode) {
case SND_SOC_DAIFMT_I2S:
adata->tdm_mode = TDM_DISABLE;
break;
case SND_SOC_DAIFMT_DSP_A:
adata->tdm_mode = TDM_ENABLE;
break;
default:
return -EINVAL;
}
return 0;
}
static int acp3x_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
u32 tx_mask, u32 rx_mask, int slots, int slot_width)
{
struct i2s_dev_data *adata;
u32 frm_len;
u16 slot_len;
adata = snd_soc_dai_get_drvdata(cpu_dai);
/* These values are as per Hardware Spec */
switch (slot_width) {
case SLOT_WIDTH_8:
slot_len = 8;
break;
case SLOT_WIDTH_16:
slot_len = 16;
break;
case SLOT_WIDTH_24:
slot_len = 24;
break;
case SLOT_WIDTH_32:
slot_len = 0;
break;
default:
return -EINVAL;
}
frm_len = FRM_LEN | (slots << 15) | (slot_len << 18);
adata->tdm_fmt = frm_len;
return 0;
}
static int acp3x_i2s_hwparams(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct i2s_stream_instance *rtd;
struct snd_soc_pcm_runtime *prtd;
struct snd_soc_card *card;
struct acp3x_platform_info *pinfo;
struct i2s_dev_data *adata;
u32 val;
u32 reg_val, frmt_reg;
prtd = asoc_substream_to_rtd(substream);
rtd = substream->runtime->private_data;
card = prtd->card;
adata = snd_soc_dai_get_drvdata(dai);
pinfo = snd_soc_card_get_drvdata(card);
if (pinfo) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
rtd->i2s_instance = pinfo->play_i2s_instance;
else
rtd->i2s_instance = pinfo->cap_i2s_instance;
}
/* These values are as per Hardware Spec */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8:
case SNDRV_PCM_FORMAT_S8:
rtd->xfer_resolution = 0x0;
break;
case SNDRV_PCM_FORMAT_S16_LE:
rtd->xfer_resolution = 0x02;
break;
case SNDRV_PCM_FORMAT_S24_LE:
rtd->xfer_resolution = 0x04;
break;
case SNDRV_PCM_FORMAT_S32_LE:
rtd->xfer_resolution = 0x05;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_val = mmACP_BTTDM_ITER;
frmt_reg = mmACP_BTTDM_TXFRMT;
break;
case I2S_SP_INSTANCE:
default:
reg_val = mmACP_I2STDM_ITER;
frmt_reg = mmACP_I2STDM_TXFRMT;
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_val = mmACP_BTTDM_IRER;
frmt_reg = mmACP_BTTDM_RXFRMT;
break;
case I2S_SP_INSTANCE:
default:
reg_val = mmACP_I2STDM_IRER;
frmt_reg = mmACP_I2STDM_RXFRMT;
}
}
if (adata->tdm_mode) {
val = rv_readl(rtd->acp3x_base + reg_val);
rv_writel(val | 0x2, rtd->acp3x_base + reg_val);
rv_writel(adata->tdm_fmt, rtd->acp3x_base + frmt_reg);
}
val = rv_readl(rtd->acp3x_base + reg_val);
val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK;
val = val | (rtd->xfer_resolution << 3);
rv_writel(val, rtd->acp3x_base + reg_val);
return 0;
}
static int acp3x_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct i2s_stream_instance *rtd;
u32 ret, val, period_bytes, reg_val, ier_val, water_val;
u32 buf_size, buf_reg;
rtd = substream->runtime->private_data;
period_bytes = frames_to_bytes(substream->runtime,
substream->runtime->period_size);
buf_size = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
rtd->bytescount = acp_get_byte_count(rtd,
substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
water_val =
mmACP_BT_TX_INTR_WATERMARK_SIZE;
reg_val = mmACP_BTTDM_ITER;
ier_val = mmACP_BTTDM_IER;
buf_reg = mmACP_BT_TX_RINGBUFSIZE;
break;
case I2S_SP_INSTANCE:
default:
water_val =
mmACP_I2S_TX_INTR_WATERMARK_SIZE;
reg_val = mmACP_I2STDM_ITER;
ier_val = mmACP_I2STDM_IER;
buf_reg = mmACP_I2S_TX_RINGBUFSIZE;
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
water_val =
mmACP_BT_RX_INTR_WATERMARK_SIZE;
reg_val = mmACP_BTTDM_IRER;
ier_val = mmACP_BTTDM_IER;
buf_reg = mmACP_BT_RX_RINGBUFSIZE;
break;
case I2S_SP_INSTANCE:
default:
water_val =
mmACP_I2S_RX_INTR_WATERMARK_SIZE;
reg_val = mmACP_I2STDM_IRER;
ier_val = mmACP_I2STDM_IER;
buf_reg = mmACP_I2S_RX_RINGBUFSIZE;
}
}
rv_writel(period_bytes, rtd->acp3x_base + water_val);
rv_writel(buf_size, rtd->acp3x_base + buf_reg);
val = rv_readl(rtd->acp3x_base + reg_val);
val = val | BIT(0);
rv_writel(val, rtd->acp3x_base + reg_val);
rv_writel(1, rtd->acp3x_base + ier_val);
ret = 0;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_val = mmACP_BTTDM_ITER;
break;
case I2S_SP_INSTANCE:
default:
reg_val = mmACP_I2STDM_ITER;
}
} else {
switch (rtd->i2s_instance) {
case I2S_BT_INSTANCE:
reg_val = mmACP_BTTDM_IRER;
break;
case I2S_SP_INSTANCE:
default:
reg_val = mmACP_I2STDM_IRER;
}
}
val = rv_readl(rtd->acp3x_base + reg_val);
val = val & ~BIT(0);
rv_writel(val, rtd->acp3x_base + reg_val);
if (!(rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER) & BIT(0)) &&
!(rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER) & BIT(0)))
rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
if (!(rv_readl(rtd->acp3x_base + mmACP_I2STDM_ITER) & BIT(0)) &&
!(rv_readl(rtd->acp3x_base + mmACP_I2STDM_IRER) & BIT(0)))
rv_writel(0, rtd->acp3x_base + mmACP_I2STDM_IER);
ret = 0;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct snd_soc_dai_ops acp3x_i2s_dai_ops = {
.hw_params = acp3x_i2s_hwparams,
.trigger = acp3x_i2s_trigger,
.set_fmt = acp3x_i2s_set_fmt,
.set_tdm_slot = acp3x_i2s_set_tdm_slot,
};
static const struct snd_soc_component_driver acp3x_dai_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static struct snd_soc_dai_driver acp3x_i2s_dai = {
.playback = {
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &acp3x_i2s_dai_ops,
};
static int acp3x_dai_probe(struct platform_device *pdev)
{
struct resource *res;
struct i2s_dev_data *adata;
int ret;
adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
GFP_KERNEL);
if (!adata)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENOMEM;
}
adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!adata->acp3x_base)
return -ENOMEM;
adata->i2s_irq = res->start;
dev_set_drvdata(&pdev->dev, adata);
ret = devm_snd_soc_register_component(&pdev->dev,
&acp3x_dai_component, &acp3x_i2s_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
return -ENODEV;
}
return 0;
}
static struct platform_driver acp3x_dai_driver = {
.probe = acp3x_dai_probe,
.driver = {
.name = "acp3x_i2s_playcap",
},
};
module_platform_driver(acp3x_dai_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:"DRV_NAME);
| linux-master | sound/soc/amd/raven/acp3x-i2s.c |
// SPDX-License-Identifier: GPL-2.0+
//
// AMD ACP PCI Driver
//
//Copyright 2016 Advanced Micro Devices, Inc.
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include "acp3x.h"
struct acp3x_dev_data {
void __iomem *acp3x_base;
bool acp3x_audio_mode;
struct resource *res;
struct platform_device *pdev[ACP3x_DEVS];
u32 pme_en;
};
static int acp3x_power_on(struct acp3x_dev_data *adata)
{
void __iomem *acp3x_base = adata->acp3x_base;
u32 val;
int timeout;
val = rv_readl(acp3x_base + mmACP_PGFSM_STATUS);
if (val == 0)
return val;
if (!((val & ACP_PGFSM_STATUS_MASK) ==
ACP_POWER_ON_IN_PROGRESS))
rv_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
acp3x_base + mmACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
val = rv_readl(acp3x_base + mmACP_PGFSM_STATUS);
if (!val) {
/* ACP power On clears PME_EN.
* Restore the value to its prior state
*/
rv_writel(adata->pme_en, acp3x_base + mmACP_PME_EN);
return 0;
}
udelay(1);
}
return -ETIMEDOUT;
}
static int acp3x_reset(void __iomem *acp3x_base)
{
u32 val;
int timeout;
rv_writel(1, acp3x_base + mmACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = rv_readl(acp3x_base + mmACP_SOFT_RESET);
if (val & ACP3x_SOFT_RESET__SoftResetAudDone_MASK)
break;
cpu_relax();
}
rv_writel(0, acp3x_base + mmACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = rv_readl(acp3x_base + mmACP_SOFT_RESET);
if (!val)
return 0;
cpu_relax();
}
return -ETIMEDOUT;
}
static void acp3x_enable_interrupts(void __iomem *acp_base)
{
rv_writel(0x01, acp_base + mmACP_EXTERNAL_INTR_ENB);
}
static void acp3x_disable_interrupts(void __iomem *acp_base)
{
rv_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
mmACP_EXTERNAL_INTR_STAT);
rv_writel(0x00, acp_base + mmACP_EXTERNAL_INTR_CNTL);
rv_writel(0x00, acp_base + mmACP_EXTERNAL_INTR_ENB);
}
static int acp3x_init(struct acp3x_dev_data *adata)
{
void __iomem *acp3x_base = adata->acp3x_base;
int ret;
/* power on */
ret = acp3x_power_on(adata);
if (ret) {
pr_err("ACP3x power on failed\n");
return ret;
}
/* Reset */
ret = acp3x_reset(acp3x_base);
if (ret) {
pr_err("ACP3x reset failed\n");
return ret;
}
acp3x_enable_interrupts(acp3x_base);
return 0;
}
static int acp3x_deinit(void __iomem *acp3x_base)
{
int ret;
acp3x_disable_interrupts(acp3x_base);
/* Reset */
ret = acp3x_reset(acp3x_base);
if (ret) {
pr_err("ACP3x reset failed\n");
return ret;
}
return 0;
}
static int snd_acp3x_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct acp3x_dev_data *adata;
struct platform_device_info pdevinfo[ACP3x_DEVS];
unsigned int irqflags;
int ret, i;
u32 addr, val;
/* Raven device detection */
if (pci->revision != 0x00)
return -ENODEV;
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
return -ENODEV;
}
ret = pci_request_regions(pci, "AMD ACP3x audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
adata = devm_kzalloc(&pci->dev, sizeof(struct acp3x_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
goto release_regions;
}
irqflags = IRQF_SHARED;
addr = pci_resource_start(pci, 0);
adata->acp3x_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
if (!adata->acp3x_base) {
ret = -ENOMEM;
goto release_regions;
}
pci_set_master(pci);
pci_set_drvdata(pci, adata);
/* Save ACP_PME_EN state */
adata->pme_en = rv_readl(adata->acp3x_base + mmACP_PME_EN);
ret = acp3x_init(adata);
if (ret)
goto release_regions;
val = rv_readl(adata->acp3x_base + mmACP_I2S_PIN_CONFIG);
switch (val) {
case I2S_MODE:
adata->res = devm_kzalloc(&pci->dev,
sizeof(struct resource) * 4,
GFP_KERNEL);
if (!adata->res) {
ret = -ENOMEM;
goto de_init;
}
adata->res[0].name = "acp3x_i2s_iomem";
adata->res[0].flags = IORESOURCE_MEM;
adata->res[0].start = addr;
adata->res[0].end = addr + (ACP3x_REG_END - ACP3x_REG_START);
adata->res[1].name = "acp3x_i2s_sp";
adata->res[1].flags = IORESOURCE_MEM;
adata->res[1].start = addr + ACP3x_I2STDM_REG_START;
adata->res[1].end = addr + ACP3x_I2STDM_REG_END;
adata->res[2].name = "acp3x_i2s_bt";
adata->res[2].flags = IORESOURCE_MEM;
adata->res[2].start = addr + ACP3x_BT_TDM_REG_START;
adata->res[2].end = addr + ACP3x_BT_TDM_REG_END;
adata->res[3].name = "acp3x_i2s_irq";
adata->res[3].flags = IORESOURCE_IRQ;
adata->res[3].start = pci->irq;
adata->res[3].end = adata->res[3].start;
adata->acp3x_audio_mode = ACP3x_I2S_MODE;
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo[0].name = "acp3x_rv_i2s_dma";
pdevinfo[0].id = 0;
pdevinfo[0].parent = &pci->dev;
pdevinfo[0].num_res = 4;
pdevinfo[0].res = &adata->res[0];
pdevinfo[0].data = &irqflags;
pdevinfo[0].size_data = sizeof(irqflags);
pdevinfo[1].name = "acp3x_i2s_playcap";
pdevinfo[1].id = 0;
pdevinfo[1].parent = &pci->dev;
pdevinfo[1].num_res = 1;
pdevinfo[1].res = &adata->res[1];
pdevinfo[2].name = "acp3x_i2s_playcap";
pdevinfo[2].id = 1;
pdevinfo[2].parent = &pci->dev;
pdevinfo[2].num_res = 1;
pdevinfo[2].res = &adata->res[1];
pdevinfo[3].name = "acp3x_i2s_playcap";
pdevinfo[3].id = 2;
pdevinfo[3].parent = &pci->dev;
pdevinfo[3].num_res = 1;
pdevinfo[3].res = &adata->res[2];
for (i = 0; i < ACP3x_DEVS; i++) {
adata->pdev[i] =
platform_device_register_full(&pdevinfo[i]);
if (IS_ERR(adata->pdev[i])) {
dev_err(&pci->dev, "cannot register %s device\n",
pdevinfo[i].name);
ret = PTR_ERR(adata->pdev[i]);
goto unregister_devs;
}
}
break;
default:
dev_info(&pci->dev, "ACP audio mode : %d\n", val);
break;
}
pm_runtime_set_autosuspend_delay(&pci->dev, 2000);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return 0;
unregister_devs:
if (val == I2S_MODE)
for (i = 0; i < ACP3x_DEVS; i++)
platform_device_unregister(adata->pdev[i]);
de_init:
if (acp3x_deinit(adata->acp3x_base))
dev_err(&pci->dev, "ACP de-init failed\n");
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
}
static int snd_acp3x_suspend(struct device *dev)
{
int ret;
struct acp3x_dev_data *adata;
adata = dev_get_drvdata(dev);
ret = acp3x_deinit(adata->acp3x_base);
if (ret)
dev_err(dev, "ACP de-init failed\n");
else
dev_dbg(dev, "ACP de-initialized\n");
return 0;
}
static int snd_acp3x_resume(struct device *dev)
{
int ret;
struct acp3x_dev_data *adata;
adata = dev_get_drvdata(dev);
ret = acp3x_init(adata);
if (ret) {
dev_err(dev, "ACP init failed\n");
return ret;
}
return 0;
}
static const struct dev_pm_ops acp3x_pm = {
.runtime_suspend = snd_acp3x_suspend,
.runtime_resume = snd_acp3x_resume,
.resume = snd_acp3x_resume,
};
static void snd_acp3x_remove(struct pci_dev *pci)
{
struct acp3x_dev_data *adata;
int i, ret;
adata = pci_get_drvdata(pci);
if (adata->acp3x_audio_mode == ACP3x_I2S_MODE) {
for (i = 0; i < ACP3x_DEVS; i++)
platform_device_unregister(adata->pdev[i]);
}
ret = acp3x_deinit(adata->acp3x_base);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
pci_release_regions(pci);
pci_disable_device(pci);
}
static const struct pci_device_id snd_acp3x_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x15e2),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_acp3x_ids);
static struct pci_driver acp3x_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_acp3x_ids,
.probe = snd_acp3x_probe,
.remove = snd_acp3x_remove,
.driver = {
.pm = &acp3x_pm,
}
};
module_pci_driver(acp3x_driver);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP3x PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/raven/pci-acp3x.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Machine driver for AMD Pink Sardine platform using DMIC
*
* Copyright 2022 Advanced Micro Devices, Inc.
*/
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/io.h>
#include <linux/dmi.h>
#include "acp63.h"
#define DRV_NAME "acp_ps_mach"
SND_SOC_DAILINK_DEF(acp63_pdm,
DAILINK_COMP_ARRAY(COMP_CPU("acp_ps_pdm_dma.0")));
SND_SOC_DAILINK_DEF(dmic_codec,
DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec.0",
"dmic-hifi")));
SND_SOC_DAILINK_DEF(pdm_platform,
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_ps_pdm_dma.0")));
static struct snd_soc_dai_link acp63_dai_pdm[] = {
{
.name = "acp63-dmic-capture",
.stream_name = "DMIC capture",
.capture_only = 1,
SND_SOC_DAILINK_REG(acp63_pdm, dmic_codec, pdm_platform),
},
};
static struct snd_soc_card acp63_card = {
.name = "acp63",
.owner = THIS_MODULE,
.dai_link = acp63_dai_pdm,
.num_links = 1,
};
static int acp63_probe(struct platform_device *pdev)
{
struct acp63_pdm *machine = NULL;
struct snd_soc_card *card;
int ret;
platform_set_drvdata(pdev, &acp63_card);
card = platform_get_drvdata(pdev);
acp63_card.dev = &pdev->dev;
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
return dev_err_probe(&pdev->dev, ret,
"snd_soc_register_card(%s) failed\n",
card->name);
}
return 0;
}
static struct platform_driver acp63_mach_driver = {
.driver = {
.name = "acp_ps_mach",
.pm = &snd_soc_pm_ops,
},
.probe = acp63_probe,
};
module_platform_driver(acp63_mach_driver);
MODULE_AUTHOR("[email protected]");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/ps/ps-mach.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AMD ALSA SoC Pink Sardine SoundWire DMA Driver
*
* Copyright 2023 Advanced Micro Devices, Inc.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw_amd.h>
#include "acp63.h"
#define DRV_NAME "amd_ps_sdw_dma"
static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {
{ACP_AUDIO0_TX_DMA_SIZE, ACP_AUDIO0_TX_FIFOADDR, ACP_AUDIO0_TX_FIFOSIZE,
ACP_AUDIO0_TX_RINGBUFSIZE, ACP_AUDIO0_TX_RINGBUFADDR, ACP_AUDIO0_TX_INTR_WATERMARK_SIZE,
ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH},
{ACP_AUDIO1_TX_DMA_SIZE, ACP_AUDIO1_TX_FIFOADDR, ACP_AUDIO1_TX_FIFOSIZE,
ACP_AUDIO1_TX_RINGBUFSIZE, ACP_AUDIO1_TX_RINGBUFADDR, ACP_AUDIO1_TX_INTR_WATERMARK_SIZE,
ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH},
{ACP_AUDIO2_TX_DMA_SIZE, ACP_AUDIO2_TX_FIFOADDR, ACP_AUDIO2_TX_FIFOSIZE,
ACP_AUDIO2_TX_RINGBUFSIZE, ACP_AUDIO2_TX_RINGBUFADDR, ACP_AUDIO2_TX_INTR_WATERMARK_SIZE,
ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH},
{ACP_AUDIO0_RX_DMA_SIZE, ACP_AUDIO0_RX_FIFOADDR, ACP_AUDIO0_RX_FIFOSIZE,
ACP_AUDIO0_RX_RINGBUFSIZE, ACP_AUDIO0_RX_RINGBUFADDR, ACP_AUDIO0_RX_INTR_WATERMARK_SIZE,
ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH},
{ACP_AUDIO1_RX_DMA_SIZE, ACP_AUDIO1_RX_FIFOADDR, ACP_AUDIO1_RX_FIFOSIZE,
ACP_AUDIO1_RX_RINGBUFSIZE, ACP_AUDIO1_RX_RINGBUFADDR, ACP_AUDIO1_RX_INTR_WATERMARK_SIZE,
ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},
{ACP_AUDIO2_RX_DMA_SIZE, ACP_AUDIO2_RX_FIFOADDR, ACP_AUDIO2_RX_FIFOSIZE,
ACP_AUDIO2_RX_RINGBUFSIZE, ACP_AUDIO2_RX_RINGBUFADDR, ACP_AUDIO2_RX_INTR_WATERMARK_SIZE,
ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH}
};
/*
* SDW1 instance supports one TX stream and one RX stream.
* For TX/RX streams DMA registers programming for SDW1 instance, it uses ACP_P1_AUDIO1 register
* set as per hardware register documentation
*/
static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {
{ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE,
ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR,
ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE,
ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH},
{ACP_P1_AUDIO1_RX_DMA_SIZE, ACP_P1_AUDIO1_RX_FIFOADDR, ACP_P1_AUDIO1_RX_FIFOSIZE,
ACP_P1_AUDIO1_RX_RINGBUFSIZE, ACP_P1_AUDIO1_RX_RINGBUFADDR,
ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE,
ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},
};
static u32 sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {
ACP_SW0_AUDIO0_TX_EN,
ACP_SW0_AUDIO1_TX_EN,
ACP_SW0_AUDIO2_TX_EN,
ACP_SW0_AUDIO0_RX_EN,
ACP_SW0_AUDIO1_RX_EN,
ACP_SW0_AUDIO2_RX_EN,
};
/*
* SDW1 instance supports one TX stream and one RX stream.
* For TX/RX streams DMA enable register programming for SDW1 instance,
* it uses ACP_SW1_AUDIO1_TX_EN and ACP_SW1_AUDIO1_RX_EN registers
* as per hardware register documentation.
*/
static u32 sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {
ACP_SW1_AUDIO1_TX_EN,
ACP_SW1_AUDIO1_RX_EN,
};
static const struct snd_pcm_hardware acp63_sdw_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.buffer_bytes_max = SDW_PLAYBACK_MAX_NUM_PERIODS * SDW_PLAYBACK_MAX_PERIOD_SIZE,
.period_bytes_min = SDW_PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = SDW_PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = SDW_PLAYBACK_MIN_NUM_PERIODS,
.periods_max = SDW_PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp63_sdw_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.buffer_bytes_max = SDW_CAPTURE_MAX_NUM_PERIODS * SDW_CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = SDW_CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = SDW_CAPTURE_MAX_PERIOD_SIZE,
.periods_min = SDW_CAPTURE_MIN_NUM_PERIODS,
.periods_max = SDW_CAPTURE_MAX_NUM_PERIODS,
};
static void acp63_enable_disable_sdw_dma_interrupts(void __iomem *acp_base, bool enable)
{
u32 ext_intr_cntl, ext_intr_cntl1;
u32 irq_mask = ACP_SDW_DMA_IRQ_MASK;
u32 irq_mask1 = ACP_P1_SDW_DMA_IRQ_MASK;
if (enable) {
ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_intr_cntl |= irq_mask;
writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
ext_intr_cntl1 |= irq_mask1;
writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
} else {
ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_intr_cntl &= ~irq_mask;
writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
ext_intr_cntl1 &= ~irq_mask1;
writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
}
}
static void acp63_config_dma(struct acp_sdw_dma_stream *stream, void __iomem *acp_base,
u32 stream_id)
{
u16 page_idx;
u32 low, high, val;
u32 sdw_dma_pte_offset;
dma_addr_t addr;
addr = stream->dma_addr;
sdw_dma_pte_offset = SDW_PTE_OFFSET(stream->instance);
val = sdw_dma_pte_offset + (stream_id * ACP_SDW_PTE_OFFSET);
/* Group Enable */
writel(ACP_SDW_SRAM_PTE_OFFSET | BIT(31), acp_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2);
writel(PAGE_SIZE_4K_ENABLE, acp_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2);
for (page_idx = 0; page_idx < stream->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
writel(low, acp_base + ACP_SCRATCH_REG_0 + val);
high |= BIT(31);
writel(high, acp_base + ACP_SCRATCH_REG_0 + val + 4);
val += 8;
addr += PAGE_SIZE;
}
writel(0x1, acp_base + ACPAXI2AXI_ATU_CTRL);
}
static int acp63_configure_sdw_ringbuffer(void __iomem *acp_base, u32 stream_id, u32 size,
u32 manager_instance)
{
u32 reg_dma_size;
u32 reg_fifo_addr;
u32 reg_fifo_size;
u32 reg_ring_buf_size;
u32 reg_ring_buf_addr;
u32 sdw_fifo_addr;
u32 sdw_fifo_offset;
u32 sdw_ring_buf_addr;
u32 sdw_ring_buf_size;
u32 sdw_mem_window_offset;
switch (manager_instance) {
case ACP_SDW0:
reg_dma_size = sdw0_dma_ring_buf_reg[stream_id].reg_dma_size;
reg_fifo_addr = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_addr;
reg_fifo_size = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_size;
reg_ring_buf_size = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_size;
reg_ring_buf_addr = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_addr;
break;
case ACP_SDW1:
reg_dma_size = sdw1_dma_ring_buf_reg[stream_id].reg_dma_size;
reg_fifo_addr = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_addr;
reg_fifo_size = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_size;
reg_ring_buf_size = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_size;
reg_ring_buf_addr = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_addr;
break;
default:
return -EINVAL;
}
sdw_fifo_offset = ACP_SDW_FIFO_OFFSET(manager_instance);
sdw_mem_window_offset = SDW_MEM_WINDOW_START(manager_instance);
sdw_fifo_addr = sdw_fifo_offset + (stream_id * SDW_FIFO_OFFSET);
sdw_ring_buf_addr = sdw_mem_window_offset + (stream_id * ACP_SDW_RING_BUFF_ADDR_OFFSET);
sdw_ring_buf_size = size;
writel(sdw_ring_buf_size, acp_base + reg_ring_buf_size);
writel(sdw_ring_buf_addr, acp_base + reg_ring_buf_addr);
writel(sdw_fifo_addr, acp_base + reg_fifo_addr);
writel(SDW_DMA_SIZE, acp_base + reg_dma_size);
writel(SDW_FIFO_SIZE, acp_base + reg_fifo_size);
return 0;
}
static int acp63_sdw_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct acp_sdw_dma_stream *stream;
struct snd_soc_dai *cpu_dai;
struct amd_sdw_manager *amd_manager;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
int ret;
runtime = substream->runtime;
cpu_dai = asoc_rtd_to_cpu(prtd, 0);
amd_manager = snd_soc_dai_get_drvdata(cpu_dai);
stream = kzalloc(sizeof(*stream), GFP_KERNEL);
if (!stream)
return -ENOMEM;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = acp63_sdw_hardware_playback;
else
runtime->hw = acp63_sdw_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(stream);
return ret;
}
stream->stream_id = cpu_dai->id;
stream->instance = amd_manager->instance;
runtime->private_data = stream;
return ret;
}
static int acp63_sdw_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct acp_sdw_dma_stream *stream;
struct sdw_dma_dev_data *sdw_data;
u32 period_bytes;
u32 water_mark_size_reg;
u32 irq_mask, ext_intr_ctrl;
u64 size;
u32 stream_id;
u32 acp_ext_intr_cntl_reg;
int ret;
sdw_data = dev_get_drvdata(component->dev);
stream = substream->runtime->private_data;
if (!stream)
return -EINVAL;
stream_id = stream->stream_id;
switch (stream->instance) {
case ACP_SDW0:
sdw_data->sdw0_dma_stream[stream_id] = substream;
water_mark_size_reg = sdw0_dma_ring_buf_reg[stream_id].water_mark_size_reg;
acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
irq_mask = BIT(SDW0_DMA_TX_IRQ_MASK(stream_id));
else
irq_mask = BIT(SDW0_DMA_RX_IRQ_MASK(stream_id));
break;
case ACP_SDW1:
sdw_data->sdw1_dma_stream[stream_id] = substream;
acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL1;
water_mark_size_reg = sdw1_dma_ring_buf_reg[stream_id].water_mark_size_reg;
irq_mask = BIT(SDW1_DMA_IRQ_MASK(stream_id));
break;
default:
return -EINVAL;
}
size = params_buffer_bytes(params);
period_bytes = params_period_bytes(params);
stream->dma_addr = substream->runtime->dma_addr;
stream->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
acp63_config_dma(stream, sdw_data->acp_base, stream_id);
ret = acp63_configure_sdw_ringbuffer(sdw_data->acp_base, stream_id, size,
stream->instance);
if (ret) {
dev_err(component->dev, "Invalid DMA channel\n");
return -EINVAL;
}
ext_intr_ctrl = readl(sdw_data->acp_base + acp_ext_intr_cntl_reg);
ext_intr_ctrl |= irq_mask;
writel(ext_intr_ctrl, sdw_data->acp_base + acp_ext_intr_cntl_reg);
writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
return 0;
}
static u64 acp63_sdw_get_byte_count(struct acp_sdw_dma_stream *stream, void __iomem *acp_base)
{
union acp_sdw_dma_count byte_count;
u32 pos_low_reg, pos_high_reg;
byte_count.bytescount = 0;
switch (stream->instance) {
case ACP_SDW0:
pos_low_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_low_reg;
pos_high_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_high_reg;
break;
case ACP_SDW1:
pos_low_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_low_reg;
pos_high_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_high_reg;
break;
default:
goto POINTER_RETURN_BYTES;
}
if (pos_low_reg) {
byte_count.bcount.high = readl(acp_base + pos_high_reg);
byte_count.bcount.low = readl(acp_base + pos_low_reg);
}
POINTER_RETURN_BYTES:
return byte_count.bytescount;
}
static snd_pcm_uframes_t acp63_sdw_dma_pointer(struct snd_soc_component *comp,
struct snd_pcm_substream *substream)
{
struct sdw_dma_dev_data *sdw_data;
struct acp_sdw_dma_stream *stream;
u32 pos, buffersize;
u64 bytescount;
sdw_data = dev_get_drvdata(comp->dev);
stream = substream->runtime->private_data;
buffersize = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
bytescount = acp63_sdw_get_byte_count(stream, sdw_data->acp_base);
if (bytescount > stream->bytescount)
bytescount -= stream->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(substream->runtime, pos);
}
static int acp63_sdw_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, SDW_MIN_BUFFER, SDW_MAX_BUFFER);
return 0;
}
static int acp63_sdw_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct sdw_dma_dev_data *sdw_data;
struct acp_sdw_dma_stream *stream;
sdw_data = dev_get_drvdata(component->dev);
stream = substream->runtime->private_data;
if (!stream)
return -EINVAL;
switch (stream->instance) {
case ACP_SDW0:
sdw_data->sdw0_dma_stream[stream->stream_id] = NULL;
break;
case ACP_SDW1:
sdw_data->sdw1_dma_stream[stream->stream_id] = NULL;
break;
default:
return -EINVAL;
}
kfree(stream);
return 0;
}
static int acp63_sdw_dma_enable(struct snd_pcm_substream *substream,
void __iomem *acp_base, bool sdw_dma_enable)
{
struct acp_sdw_dma_stream *stream;
u32 stream_id;
u32 sdw_dma_en_reg;
u32 sdw_dma_en_stat_reg;
u32 sdw_dma_stat;
u32 dma_enable;
stream = substream->runtime->private_data;
stream_id = stream->stream_id;
switch (stream->instance) {
case ACP_SDW0:
sdw_dma_en_reg = sdw0_dma_enable_reg[stream_id];
break;
case ACP_SDW1:
sdw_dma_en_reg = sdw1_dma_enable_reg[stream_id];
break;
default:
return -EINVAL;
}
sdw_dma_en_stat_reg = sdw_dma_en_reg + 4;
dma_enable = sdw_dma_enable;
writel(dma_enable, acp_base + sdw_dma_en_reg);
return readl_poll_timeout(acp_base + sdw_dma_en_stat_reg, sdw_dma_stat,
(sdw_dma_stat == dma_enable), ACP_DELAY_US, ACP_COUNTER);
}
static int acp63_sdw_dma_trigger(struct snd_soc_component *comp,
struct snd_pcm_substream *substream,
int cmd)
{
struct sdw_dma_dev_data *sdw_data;
int ret;
sdw_data = dev_get_drvdata(comp->dev);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
ret = acp63_sdw_dma_enable(substream, sdw_data->acp_base, true);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
ret = acp63_sdw_dma_enable(substream, sdw_data->acp_base, false);
break;
default:
ret = -EINVAL;
}
if (ret)
dev_err(comp->dev, "trigger %d failed: %d", cmd, ret);
return ret;
}
static const struct snd_soc_component_driver acp63_sdw_component = {
.name = DRV_NAME,
.open = acp63_sdw_dma_open,
.close = acp63_sdw_dma_close,
.hw_params = acp63_sdw_dma_hw_params,
.trigger = acp63_sdw_dma_trigger,
.pointer = acp63_sdw_dma_pointer,
.pcm_construct = acp63_sdw_dma_new,
};
static int acp63_sdw_platform_probe(struct platform_device *pdev)
{
struct resource *res;
struct sdw_dma_dev_data *sdw_data;
struct acp63_dev_data *acp_data;
struct device *parent;
int status;
parent = pdev->dev.parent;
acp_data = dev_get_drvdata(parent);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
sdw_data = devm_kzalloc(&pdev->dev, sizeof(*sdw_data), GFP_KERNEL);
if (!sdw_data)
return -ENOMEM;
sdw_data->acp_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!sdw_data->acp_base)
return -ENOMEM;
sdw_data->acp_lock = &acp_data->acp_lock;
dev_set_drvdata(&pdev->dev, sdw_data);
status = devm_snd_soc_register_component(&pdev->dev,
&acp63_sdw_component,
NULL, 0);
if (status) {
dev_err(&pdev->dev, "Fail to register sdw dma component\n");
return status;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void acp63_sdw_platform_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int acp_restore_sdw_dma_config(struct sdw_dma_dev_data *sdw_data)
{
struct acp_sdw_dma_stream *stream;
struct snd_pcm_substream *substream;
struct snd_pcm_runtime *runtime;
u32 period_bytes, buf_size, water_mark_size_reg;
u32 stream_count;
int index, instance, ret;
for (instance = 0; instance < AMD_SDW_MAX_MANAGERS; instance++) {
if (instance == ACP_SDW0)
stream_count = ACP63_SDW0_DMA_MAX_STREAMS;
else
stream_count = ACP63_SDW1_DMA_MAX_STREAMS;
for (index = 0; index < stream_count; index++) {
if (instance == ACP_SDW0) {
substream = sdw_data->sdw0_dma_stream[index];
water_mark_size_reg =
sdw0_dma_ring_buf_reg[index].water_mark_size_reg;
} else {
substream = sdw_data->sdw1_dma_stream[index];
water_mark_size_reg =
sdw1_dma_ring_buf_reg[index].water_mark_size_reg;
}
if (substream && substream->runtime) {
runtime = substream->runtime;
stream = runtime->private_data;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
buf_size = frames_to_bytes(runtime, runtime->buffer_size);
acp63_config_dma(stream, sdw_data->acp_base, index);
ret = acp63_configure_sdw_ringbuffer(sdw_data->acp_base, index,
buf_size, instance);
if (ret)
return ret;
writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
}
}
}
acp63_enable_disable_sdw_dma_interrupts(sdw_data->acp_base, true);
return 0;
}
static int __maybe_unused acp63_sdw_pcm_resume(struct device *dev)
{
struct sdw_dma_dev_data *sdw_data;
sdw_data = dev_get_drvdata(dev);
return acp_restore_sdw_dma_config(sdw_data);
}
static const struct dev_pm_ops acp63_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(NULL, acp63_sdw_pcm_resume)
};
static struct platform_driver acp63_sdw_dma_driver = {
.probe = acp63_sdw_platform_probe,
.remove_new = acp63_sdw_platform_remove,
.driver = {
.name = "amd_ps_sdw_dma",
.pm = &acp63_pm_ops,
},
};
module_platform_driver(acp63_sdw_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP6.3 PS SDW DMA Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/ps/ps-sdw-dma.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AMD ALSA SoC Pink Sardine PDM Driver
*
* Copyright 2022 Advanced Micro Devices, Inc.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/pm_runtime.h>
#include "acp63.h"
#define DRV_NAME "acp_ps_pdm_dma"
static int pdm_gain = 3;
module_param(pdm_gain, int, 0644);
MODULE_PARM_DESC(pdm_gain, "Gain control (0-3)");
static const struct snd_pcm_hardware acp63_pdm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
static void acp63_init_pdm_ring_buffer(u32 physical_addr, u32 buffer_size,
u32 watermark_size, void __iomem *acp_base)
{
writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
}
static void acp63_enable_pdm_clock(void __iomem *acp_base)
{
u32 pdm_clk_enable, pdm_ctrl;
pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK;
pdm_ctrl = 0x00;
writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
pdm_ctrl = readl(acp_base + ACP_WOV_MISC_CTRL);
pdm_ctrl &= ~ACP_WOV_GAIN_CONTROL;
pdm_ctrl |= FIELD_PREP(ACP_WOV_GAIN_CONTROL, clamp(pdm_gain, 0, 3));
writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
}
static void acp63_enable_pdm_interrupts(struct pdm_dev_data *adata)
{
u32 ext_int_ctrl;
mutex_lock(adata->acp_lock);
ext_int_ctrl = readl(adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl |= PDM_DMA_INTR_MASK;
writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
mutex_unlock(adata->acp_lock);
}
static void acp63_disable_pdm_interrupts(struct pdm_dev_data *adata)
{
u32 ext_int_ctrl;
mutex_lock(adata->acp_lock);
ext_int_ctrl = readl(adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
ext_int_ctrl &= ~PDM_DMA_INTR_MASK;
writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
mutex_unlock(adata->acp_lock);
}
static bool acp63_check_pdm_dma_status(void __iomem *acp_base)
{
bool pdm_dma_status;
u32 pdm_enable, pdm_dma_enable;
pdm_dma_status = false;
pdm_enable = readl(acp_base + ACP_WOV_PDM_ENABLE);
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable & ACP_PDM_DMA_EN_STATUS))
pdm_dma_status = true;
return pdm_dma_status;
}
static int acp63_start_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable;
u32 pdm_dma_enable;
int timeout;
pdm_enable = 0x01;
pdm_dma_enable = 0x01;
acp63_enable_pdm_clock(acp_base);
writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS)
return 0;
udelay(DELAY_US);
}
return -ETIMEDOUT;
}
static int acp63_stop_pdm_dma(void __iomem *acp_base)
{
u32 pdm_enable, pdm_dma_enable;
int timeout;
pdm_enable = 0x00;
pdm_dma_enable = 0x00;
pdm_enable = readl(acp_base + ACP_WOV_PDM_ENABLE);
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if (pdm_dma_enable & 0x01) {
pdm_dma_enable = 0x02;
writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
timeout = 0;
while (++timeout < ACP_COUNTER) {
pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((pdm_dma_enable & 0x02) == 0x00)
break;
udelay(DELAY_US);
}
if (timeout == ACP_COUNTER)
return -ETIMEDOUT;
}
if (pdm_enable == ACP_PDM_ENABLE) {
pdm_enable = ACP_PDM_DISABLE;
writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
}
writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
return 0;
}
static void acp63_config_dma(struct pdm_stream_instance *rtd, int direction)
{
u16 page_idx;
u32 low, high, val;
dma_addr_t addr;
addr = rtd->dma_addr;
val = PDM_PTE_OFFSET;
/* Group Enable */
writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp63_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
writel(PAGE_SIZE_4K_ENABLE, rtd->acp63_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
writel(low, rtd->acp63_base + ACP_SCRATCH_REG_0 + val);
high |= BIT(31);
writel(high, rtd->acp63_base + ACP_SCRATCH_REG_0 + val + 4);
val += 8;
addr += PAGE_SIZE;
}
}
static int acp63_pdm_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime;
struct pdm_dev_data *adata;
struct pdm_stream_instance *pdm_data;
int ret;
runtime = substream->runtime;
adata = dev_get_drvdata(component->dev);
pdm_data = kzalloc(sizeof(*pdm_data), GFP_KERNEL);
if (!pdm_data)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = acp63_pdm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(pdm_data);
return ret;
}
acp63_enable_pdm_interrupts(adata);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
adata->capture_stream = substream;
pdm_data->acp63_base = adata->acp63_base;
runtime->private_data = pdm_data;
return ret;
}
static int acp63_pdm_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct pdm_stream_instance *rtd;
size_t size, period_bytes;
rtd = substream->runtime->private_data;
if (!rtd)
return -EINVAL;
size = params_buffer_bytes(params);
period_bytes = params_period_bytes(params);
rtd->dma_addr = substream->runtime->dma_addr;
rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
acp63_config_dma(rtd, substream->stream);
acp63_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, size,
period_bytes, rtd->acp63_base);
return 0;
}
static u64 acp63_pdm_get_byte_count(struct pdm_stream_instance *rtd,
int direction)
{
u32 high, low;
u64 byte_count;
high = readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
byte_count = high;
low = readl(rtd->acp63_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
byte_count = (byte_count << 32) | low;
return byte_count;
}
static snd_pcm_uframes_t acp63_pdm_dma_pointer(struct snd_soc_component *comp,
struct snd_pcm_substream *stream)
{
struct pdm_stream_instance *rtd;
u32 pos, buffersize;
u64 bytescount;
rtd = stream->runtime->private_data;
buffersize = frames_to_bytes(stream->runtime,
stream->runtime->buffer_size);
bytescount = acp63_pdm_get_byte_count(rtd, stream->stream);
if (bytescount > rtd->bytescount)
bytescount -= rtd->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(stream->runtime, pos);
}
static int acp63_pdm_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, MIN_BUFFER, MAX_BUFFER);
return 0;
}
static int acp63_pdm_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct pdm_dev_data *adata = dev_get_drvdata(component->dev);
struct snd_pcm_runtime *runtime = substream->runtime;
acp63_disable_pdm_interrupts(adata);
adata->capture_stream = NULL;
kfree(runtime->private_data);
return 0;
}
static int acp63_pdm_dai_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct pdm_stream_instance *rtd;
int ret;
bool pdm_status;
unsigned int ch_mask;
rtd = substream->runtime->private_data;
ret = 0;
switch (substream->runtime->channels) {
case TWO_CH:
ch_mask = 0x00;
break;
default:
return -EINVAL;
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
writel(ch_mask, rtd->acp63_base + ACP_WOV_PDM_NO_OF_CHANNELS);
writel(PDM_DECIMATION_FACTOR, rtd->acp63_base + ACP_WOV_PDM_DECIMATION_FACTOR);
rtd->bytescount = acp63_pdm_get_byte_count(rtd, substream->stream);
pdm_status = acp63_check_pdm_dma_status(rtd->acp63_base);
if (!pdm_status)
ret = acp63_start_pdm_dma(rtd->acp63_base);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
pdm_status = acp63_check_pdm_dma_status(rtd->acp63_base);
if (pdm_status)
ret = acp63_stop_pdm_dma(rtd->acp63_base);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct snd_soc_dai_ops acp63_pdm_dai_ops = {
.trigger = acp63_pdm_dai_trigger,
};
static struct snd_soc_dai_driver acp63_pdm_dai_driver = {
.name = "acp_ps_pdm_dma.0",
.capture = {
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 48000,
.rate_max = 48000,
},
.ops = &acp63_pdm_dai_ops,
};
static const struct snd_soc_component_driver acp63_pdm_component = {
.name = DRV_NAME,
.open = acp63_pdm_dma_open,
.close = acp63_pdm_dma_close,
.hw_params = acp63_pdm_dma_hw_params,
.pointer = acp63_pdm_dma_pointer,
.pcm_construct = acp63_pdm_dma_new,
};
static int acp63_pdm_audio_probe(struct platform_device *pdev)
{
struct resource *res;
struct pdm_dev_data *adata;
struct acp63_dev_data *acp_data;
struct device *parent;
int status;
parent = pdev->dev.parent;
acp_data = dev_get_drvdata(parent);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
if (!adata)
return -ENOMEM;
adata->acp63_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!adata->acp63_base)
return -ENOMEM;
adata->capture_stream = NULL;
adata->acp_lock = &acp_data->acp_lock;
dev_set_drvdata(&pdev->dev, adata);
status = devm_snd_soc_register_component(&pdev->dev,
&acp63_pdm_component,
&acp63_pdm_dai_driver, 1);
if (status) {
dev_err(&pdev->dev, "Fail to register acp pdm dai\n");
return -ENODEV;
}
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void acp63_pdm_audio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused acp63_pdm_resume(struct device *dev)
{
struct pdm_dev_data *adata;
struct snd_pcm_runtime *runtime;
struct pdm_stream_instance *rtd;
u32 period_bytes, buffer_len;
adata = dev_get_drvdata(dev);
if (adata->capture_stream && adata->capture_stream->runtime) {
runtime = adata->capture_stream->runtime;
rtd = runtime->private_data;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
acp63_config_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
acp63_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, buffer_len,
period_bytes, adata->acp63_base);
}
acp63_enable_pdm_interrupts(adata);
return 0;
}
static int __maybe_unused acp63_pdm_suspend(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
acp63_disable_pdm_interrupts(adata);
return 0;
}
static int __maybe_unused acp63_pdm_runtime_resume(struct device *dev)
{
struct pdm_dev_data *adata;
adata = dev_get_drvdata(dev);
acp63_enable_pdm_interrupts(adata);
return 0;
}
static const struct dev_pm_ops acp63_pdm_pm_ops = {
SET_RUNTIME_PM_OPS(acp63_pdm_suspend, acp63_pdm_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(acp63_pdm_suspend, acp63_pdm_resume)
};
static struct platform_driver acp63_pdm_dma_driver = {
.probe = acp63_pdm_audio_probe,
.remove_new = acp63_pdm_audio_remove,
.driver = {
.name = "acp_ps_pdm_dma",
.pm = &acp63_pdm_pm_ops,
},
};
module_platform_driver(acp63_pdm_dma_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD PINK SARDINE PDM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/ps/ps-pdm-dma.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AMD Pink Sardine ACP PCI Driver
*
* Copyright 2022 Advanced Micro Devices, Inc.
*/
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/acpi.h>
#include <linux/interrupt.h>
#include <sound/pcm_params.h>
#include <linux/pm_runtime.h>
#include <linux/iopoll.h>
#include <linux/soundwire/sdw_amd.h>
#include "acp63.h"
static int acp63_power_on(void __iomem *acp_base)
{
u32 val;
val = readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return val;
if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
return readl_poll_timeout(acp_base + ACP_PGFSM_STATUS, val, !val, DELAY_US, ACP_TIMEOUT);
}
static int acp63_reset(void __iomem *acp_base)
{
u32 val;
int ret;
writel(1, acp_base + ACP_SOFT_RESET);
ret = readl_poll_timeout(acp_base + ACP_SOFT_RESET, val,
val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK,
DELAY_US, ACP_TIMEOUT);
if (ret)
return ret;
writel(0, acp_base + ACP_SOFT_RESET);
return readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT);
}
static void acp63_enable_interrupts(void __iomem *acp_base)
{
writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL);
}
static void acp63_disable_interrupts(void __iomem *acp_base)
{
writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT);
writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
}
static int acp63_init(void __iomem *acp_base, struct device *dev)
{
int ret;
ret = acp63_power_on(acp_base);
if (ret) {
dev_err(dev, "ACP power on failed\n");
return ret;
}
writel(0x01, acp_base + ACP_CONTROL);
ret = acp63_reset(acp_base);
if (ret) {
dev_err(dev, "ACP reset failed\n");
return ret;
}
acp63_enable_interrupts(acp_base);
return 0;
}
static int acp63_deinit(void __iomem *acp_base, struct device *dev)
{
int ret;
acp63_disable_interrupts(acp_base);
ret = acp63_reset(acp_base);
if (ret) {
dev_err(dev, "ACP reset failed\n");
return ret;
}
writel(0, acp_base + ACP_CONTROL);
return 0;
}
static irqreturn_t acp63_irq_thread(int irq, void *context)
{
struct sdw_dma_dev_data *sdw_dma_data;
struct acp63_dev_data *adata = context;
u32 stream_index;
u16 pdev_index;
pdev_index = adata->sdw_dma_dev_index;
sdw_dma_data = dev_get_drvdata(&adata->pdev[pdev_index]->dev);
for (stream_index = 0; stream_index < ACP63_SDW0_DMA_MAX_STREAMS; stream_index++) {
if (adata->sdw0_dma_intr_stat[stream_index]) {
if (sdw_dma_data->sdw0_dma_stream[stream_index])
snd_pcm_period_elapsed(sdw_dma_data->sdw0_dma_stream[stream_index]);
adata->sdw0_dma_intr_stat[stream_index] = 0;
}
}
for (stream_index = 0; stream_index < ACP63_SDW1_DMA_MAX_STREAMS; stream_index++) {
if (adata->sdw1_dma_intr_stat[stream_index]) {
if (sdw_dma_data->sdw1_dma_stream[stream_index])
snd_pcm_period_elapsed(sdw_dma_data->sdw1_dma_stream[stream_index]);
adata->sdw1_dma_intr_stat[stream_index] = 0;
}
}
return IRQ_HANDLED;
}
static irqreturn_t acp63_irq_handler(int irq, void *dev_id)
{
struct acp63_dev_data *adata;
struct pdm_dev_data *ps_pdm_data;
struct amd_sdw_manager *amd_manager;
u32 ext_intr_stat, ext_intr_stat1;
u32 stream_id = 0;
u16 irq_flag = 0;
u16 sdw_dma_irq_flag = 0;
u16 pdev_index;
u16 index;
adata = dev_id;
if (!adata)
return IRQ_NONE;
/* ACP interrupts will be cleared by reading particular bit and writing
* same value to the status register. writing zero's doesn't have any
* effect.
* Bit by bit checking of IRQ field is implemented.
*/
ext_intr_stat = readl(adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
if (ext_intr_stat & ACP_SDW0_STAT) {
writel(ACP_SDW0_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
pdev_index = adata->sdw0_dev_index;
amd_manager = dev_get_drvdata(&adata->pdev[pdev_index]->dev);
if (amd_manager)
schedule_work(&amd_manager->amd_sdw_irq_thread);
irq_flag = 1;
}
ext_intr_stat1 = readl(adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
if (ext_intr_stat1 & ACP_SDW1_STAT) {
writel(ACP_SDW1_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
pdev_index = adata->sdw1_dev_index;
amd_manager = dev_get_drvdata(&adata->pdev[pdev_index]->dev);
if (amd_manager)
schedule_work(&amd_manager->amd_sdw_irq_thread);
irq_flag = 1;
}
if (ext_intr_stat & ACP_ERROR_IRQ) {
writel(ACP_ERROR_IRQ, adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
/* TODO: Report SoundWire Manager instance errors */
writel(0, adata->acp63_base + ACP_SW0_I2S_ERROR_REASON);
writel(0, adata->acp63_base + ACP_SW1_I2S_ERROR_REASON);
writel(0, adata->acp63_base + ACP_ERROR_STATUS);
irq_flag = 1;
}
if (ext_intr_stat & BIT(PDM_DMA_STAT)) {
pdev_index = adata->pdm_dev_index;
ps_pdm_data = dev_get_drvdata(&adata->pdev[pdev_index]->dev);
writel(BIT(PDM_DMA_STAT), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
if (ps_pdm_data->capture_stream)
snd_pcm_period_elapsed(ps_pdm_data->capture_stream);
irq_flag = 1;
}
if (ext_intr_stat & ACP_SDW_DMA_IRQ_MASK) {
for (index = ACP_AUDIO2_RX_THRESHOLD; index <= ACP_AUDIO0_TX_THRESHOLD; index++) {
if (ext_intr_stat & BIT(index)) {
writel(BIT(index), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
switch (index) {
case ACP_AUDIO0_TX_THRESHOLD:
stream_id = ACP_SDW0_AUDIO0_TX;
break;
case ACP_AUDIO1_TX_THRESHOLD:
stream_id = ACP_SDW0_AUDIO1_TX;
break;
case ACP_AUDIO2_TX_THRESHOLD:
stream_id = ACP_SDW0_AUDIO2_TX;
break;
case ACP_AUDIO0_RX_THRESHOLD:
stream_id = ACP_SDW0_AUDIO0_RX;
break;
case ACP_AUDIO1_RX_THRESHOLD:
stream_id = ACP_SDW0_AUDIO1_RX;
break;
case ACP_AUDIO2_RX_THRESHOLD:
stream_id = ACP_SDW0_AUDIO2_RX;
break;
}
adata->sdw0_dma_intr_stat[stream_id] = 1;
sdw_dma_irq_flag = 1;
}
}
}
if (ext_intr_stat1 & ACP_P1_AUDIO1_RX_THRESHOLD) {
writel(ACP_P1_AUDIO1_RX_THRESHOLD,
adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
adata->sdw1_dma_intr_stat[ACP_SDW1_AUDIO1_RX] = 1;
sdw_dma_irq_flag = 1;
}
if (ext_intr_stat1 & ACP_P1_AUDIO1_TX_THRESHOLD) {
writel(ACP_P1_AUDIO1_TX_THRESHOLD,
adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
adata->sdw1_dma_intr_stat[ACP_SDW1_AUDIO1_TX] = 1;
sdw_dma_irq_flag = 1;
}
if (sdw_dma_irq_flag)
return IRQ_WAKE_THREAD;
if (irq_flag)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static int sdw_amd_scan_controller(struct device *dev)
{
struct acp63_dev_data *acp_data;
struct fwnode_handle *link;
char name[32];
u32 sdw_manager_bitmap;
u8 count = 0;
u32 acp_sdw_power_mode = 0;
int index;
int ret;
acp_data = dev_get_drvdata(dev);
/*
* Current implementation is based on MIPI DisCo 2.0 spec.
* Found controller, find links supported.
*/
ret = fwnode_property_read_u32_array((acp_data->sdw_fw_node), "mipi-sdw-manager-list",
&sdw_manager_bitmap, 1);
if (ret) {
dev_dbg(dev, "Failed to read mipi-sdw-manager-list: %d\n", ret);
return -EINVAL;
}
count = hweight32(sdw_manager_bitmap);
/* Check count is within bounds */
if (count > AMD_SDW_MAX_MANAGERS) {
dev_err(dev, "Manager count %d exceeds max %d\n", count, AMD_SDW_MAX_MANAGERS);
return -EINVAL;
}
if (!count) {
dev_dbg(dev, "No SoundWire Managers detected\n");
return -EINVAL;
}
dev_dbg(dev, "ACPI reports %d SoundWire Manager devices\n", count);
acp_data->sdw_manager_count = count;
for (index = 0; index < count; index++) {
snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", index);
link = fwnode_get_named_child_node(acp_data->sdw_fw_node, name);
if (!link) {
dev_err(dev, "Manager node %s not found\n", name);
return -EIO;
}
ret = fwnode_property_read_u32(link, "amd-sdw-power-mode", &acp_sdw_power_mode);
if (ret)
return ret;
/*
* when SoundWire configuration is selected from acp pin config,
* based on manager instances count, acp init/de-init sequence should be
* executed as part of PM ops only when Bus reset is applied for the active
* SoundWire manager instances.
*/
if (acp_sdw_power_mode != AMD_SDW_POWER_OFF_MODE) {
acp_data->acp_reset = false;
return 0;
}
}
return 0;
}
static int get_acp63_device_config(u32 config, struct pci_dev *pci, struct acp63_dev_data *acp_data)
{
struct acpi_device *dmic_dev;
struct acpi_device *sdw_dev;
const union acpi_object *obj;
bool is_dmic_dev = false;
bool is_sdw_dev = false;
int ret;
dmic_dev = acpi_find_child_device(ACPI_COMPANION(&pci->dev), ACP63_DMIC_ADDR, 0);
if (dmic_dev) {
/* is_dmic_dev flag will be set when ACP PDM controller device exists */
if (!acpi_dev_get_property(dmic_dev, "acp-audio-device-type",
ACPI_TYPE_INTEGER, &obj) &&
obj->integer.value == ACP_DMIC_DEV)
is_dmic_dev = true;
}
sdw_dev = acpi_find_child_device(ACPI_COMPANION(&pci->dev), ACP63_SDW_ADDR, 0);
if (sdw_dev) {
acp_data->sdw_fw_node = acpi_fwnode_handle(sdw_dev);
ret = sdw_amd_scan_controller(&pci->dev);
/* is_sdw_dev flag will be set when SoundWire Manager device exists */
if (!ret)
is_sdw_dev = true;
}
if (!is_dmic_dev && !is_sdw_dev)
return -ENODEV;
dev_dbg(&pci->dev, "Audio Mode %d\n", config);
switch (config) {
case ACP_CONFIG_4:
case ACP_CONFIG_5:
case ACP_CONFIG_10:
case ACP_CONFIG_11:
if (is_dmic_dev) {
acp_data->pdev_config = ACP63_PDM_DEV_CONFIG;
acp_data->pdev_count = ACP63_PDM_MODE_DEVS;
}
break;
case ACP_CONFIG_2:
case ACP_CONFIG_3:
if (is_sdw_dev) {
switch (acp_data->sdw_manager_count) {
case 1:
acp_data->pdev_config = ACP63_SDW_DEV_CONFIG;
acp_data->pdev_count = ACP63_SDW0_MODE_DEVS;
break;
case 2:
acp_data->pdev_config = ACP63_SDW_DEV_CONFIG;
acp_data->pdev_count = ACP63_SDW0_SDW1_MODE_DEVS;
break;
default:
return -EINVAL;
}
}
break;
case ACP_CONFIG_6:
case ACP_CONFIG_7:
case ACP_CONFIG_12:
case ACP_CONFIG_8:
case ACP_CONFIG_13:
case ACP_CONFIG_14:
if (is_dmic_dev && is_sdw_dev) {
switch (acp_data->sdw_manager_count) {
case 1:
acp_data->pdev_config = ACP63_SDW_PDM_DEV_CONFIG;
acp_data->pdev_count = ACP63_SDW0_PDM_MODE_DEVS;
break;
case 2:
acp_data->pdev_config = ACP63_SDW_PDM_DEV_CONFIG;
acp_data->pdev_count = ACP63_SDW0_SDW1_PDM_MODE_DEVS;
break;
default:
return -EINVAL;
}
} else if (is_dmic_dev) {
acp_data->pdev_config = ACP63_PDM_DEV_CONFIG;
acp_data->pdev_count = ACP63_PDM_MODE_DEVS;
} else if (is_sdw_dev) {
switch (acp_data->sdw_manager_count) {
case 1:
acp_data->pdev_config = ACP63_SDW_DEV_CONFIG;
acp_data->pdev_count = ACP63_SDW0_MODE_DEVS;
break;
case 2:
acp_data->pdev_config = ACP63_SDW_DEV_CONFIG;
acp_data->pdev_count = ACP63_SDW0_SDW1_MODE_DEVS;
break;
default:
return -EINVAL;
}
}
break;
default:
break;
}
return 0;
}
static void acp63_fill_platform_dev_info(struct platform_device_info *pdevinfo,
struct device *parent,
struct fwnode_handle *fw_node,
char *name, unsigned int id,
const struct resource *res,
unsigned int num_res,
const void *data,
size_t size_data)
{
pdevinfo->name = name;
pdevinfo->id = id;
pdevinfo->parent = parent;
pdevinfo->num_res = num_res;
pdevinfo->res = res;
pdevinfo->data = data;
pdevinfo->size_data = size_data;
pdevinfo->fwnode = fw_node;
}
static int create_acp63_platform_devs(struct pci_dev *pci, struct acp63_dev_data *adata, u32 addr)
{
struct acp_sdw_pdata *sdw_pdata;
struct platform_device_info pdevinfo[ACP63_DEVS];
struct device *parent;
int index;
int ret;
parent = &pci->dev;
dev_dbg(&pci->dev,
"%s pdev_config:0x%x pdev_count:0x%x\n", __func__, adata->pdev_config,
adata->pdev_count);
if (adata->pdev_config) {
adata->res = devm_kzalloc(&pci->dev, sizeof(struct resource), GFP_KERNEL);
if (!adata->res) {
ret = -ENOMEM;
goto de_init;
}
adata->res->flags = IORESOURCE_MEM;
adata->res->start = addr;
adata->res->end = addr + (ACP63_REG_END - ACP63_REG_START);
memset(&pdevinfo, 0, sizeof(pdevinfo));
}
switch (adata->pdev_config) {
case ACP63_PDM_DEV_CONFIG:
adata->pdm_dev_index = 0;
acp63_fill_platform_dev_info(&pdevinfo[0], parent, NULL, "acp_ps_pdm_dma",
0, adata->res, 1, NULL, 0);
acp63_fill_platform_dev_info(&pdevinfo[1], parent, NULL, "dmic-codec",
0, NULL, 0, NULL, 0);
acp63_fill_platform_dev_info(&pdevinfo[2], parent, NULL, "acp_ps_mach",
0, NULL, 0, NULL, 0);
break;
case ACP63_SDW_DEV_CONFIG:
if (adata->pdev_count == ACP63_SDW0_MODE_DEVS) {
sdw_pdata = devm_kzalloc(&pci->dev, sizeof(struct acp_sdw_pdata),
GFP_KERNEL);
if (!sdw_pdata) {
ret = -ENOMEM;
goto de_init;
}
sdw_pdata->instance = 0;
sdw_pdata->acp_sdw_lock = &adata->acp_lock;
adata->sdw0_dev_index = 0;
adata->sdw_dma_dev_index = 1;
acp63_fill_platform_dev_info(&pdevinfo[0], parent, adata->sdw_fw_node,
"amd_sdw_manager", 0, adata->res, 1,
sdw_pdata, sizeof(struct acp_sdw_pdata));
acp63_fill_platform_dev_info(&pdevinfo[1], parent, NULL, "amd_ps_sdw_dma",
0, adata->res, 1, NULL, 0);
} else if (adata->pdev_count == ACP63_SDW0_SDW1_MODE_DEVS) {
sdw_pdata = devm_kzalloc(&pci->dev, sizeof(struct acp_sdw_pdata) * 2,
GFP_KERNEL);
if (!sdw_pdata) {
ret = -ENOMEM;
goto de_init;
}
sdw_pdata[0].instance = 0;
sdw_pdata[1].instance = 1;
sdw_pdata[0].acp_sdw_lock = &adata->acp_lock;
sdw_pdata[1].acp_sdw_lock = &adata->acp_lock;
sdw_pdata->acp_sdw_lock = &adata->acp_lock;
adata->sdw0_dev_index = 0;
adata->sdw1_dev_index = 1;
adata->sdw_dma_dev_index = 2;
acp63_fill_platform_dev_info(&pdevinfo[0], parent, adata->sdw_fw_node,
"amd_sdw_manager", 0, adata->res, 1,
&sdw_pdata[0], sizeof(struct acp_sdw_pdata));
acp63_fill_platform_dev_info(&pdevinfo[1], parent, adata->sdw_fw_node,
"amd_sdw_manager", 1, adata->res, 1,
&sdw_pdata[1], sizeof(struct acp_sdw_pdata));
acp63_fill_platform_dev_info(&pdevinfo[2], parent, NULL, "amd_ps_sdw_dma",
0, adata->res, 1, NULL, 0);
}
break;
case ACP63_SDW_PDM_DEV_CONFIG:
if (adata->pdev_count == ACP63_SDW0_PDM_MODE_DEVS) {
sdw_pdata = devm_kzalloc(&pci->dev, sizeof(struct acp_sdw_pdata),
GFP_KERNEL);
if (!sdw_pdata) {
ret = -ENOMEM;
goto de_init;
}
sdw_pdata->instance = 0;
sdw_pdata->acp_sdw_lock = &adata->acp_lock;
adata->pdm_dev_index = 0;
adata->sdw0_dev_index = 1;
adata->sdw_dma_dev_index = 2;
acp63_fill_platform_dev_info(&pdevinfo[0], parent, NULL, "acp_ps_pdm_dma",
0, adata->res, 1, NULL, 0);
acp63_fill_platform_dev_info(&pdevinfo[1], parent, adata->sdw_fw_node,
"amd_sdw_manager", 0, adata->res, 1,
sdw_pdata, sizeof(struct acp_sdw_pdata));
acp63_fill_platform_dev_info(&pdevinfo[2], parent, NULL, "amd_ps_sdw_dma",
0, adata->res, 1, NULL, 0);
acp63_fill_platform_dev_info(&pdevinfo[3], parent, NULL, "dmic-codec",
0, NULL, 0, NULL, 0);
} else if (adata->pdev_count == ACP63_SDW0_SDW1_PDM_MODE_DEVS) {
sdw_pdata = devm_kzalloc(&pci->dev, sizeof(struct acp_sdw_pdata) * 2,
GFP_KERNEL);
if (!sdw_pdata) {
ret = -ENOMEM;
goto de_init;
}
sdw_pdata[0].instance = 0;
sdw_pdata[1].instance = 1;
sdw_pdata[0].acp_sdw_lock = &adata->acp_lock;
sdw_pdata[1].acp_sdw_lock = &adata->acp_lock;
adata->pdm_dev_index = 0;
adata->sdw0_dev_index = 1;
adata->sdw1_dev_index = 2;
adata->sdw_dma_dev_index = 3;
acp63_fill_platform_dev_info(&pdevinfo[0], parent, NULL, "acp_ps_pdm_dma",
0, adata->res, 1, NULL, 0);
acp63_fill_platform_dev_info(&pdevinfo[1], parent, adata->sdw_fw_node,
"amd_sdw_manager", 0, adata->res, 1,
&sdw_pdata[0], sizeof(struct acp_sdw_pdata));
acp63_fill_platform_dev_info(&pdevinfo[2], parent, adata->sdw_fw_node,
"amd_sdw_manager", 1, adata->res, 1,
&sdw_pdata[1], sizeof(struct acp_sdw_pdata));
acp63_fill_platform_dev_info(&pdevinfo[3], parent, NULL, "amd_ps_sdw_dma",
0, adata->res, 1, NULL, 0);
acp63_fill_platform_dev_info(&pdevinfo[4], parent, NULL, "dmic-codec",
0, NULL, 0, NULL, 0);
}
break;
default:
dev_dbg(&pci->dev, "No PDM or SoundWire manager devices found\n");
return 0;
}
for (index = 0; index < adata->pdev_count; index++) {
adata->pdev[index] = platform_device_register_full(&pdevinfo[index]);
if (IS_ERR(adata->pdev[index])) {
dev_err(&pci->dev,
"cannot register %s device\n", pdevinfo[index].name);
ret = PTR_ERR(adata->pdev[index]);
goto unregister_devs;
}
}
return 0;
unregister_devs:
for (--index; index >= 0; index--)
platform_device_unregister(adata->pdev[index]);
de_init:
if (acp63_deinit(adata->acp63_base, &pci->dev))
dev_err(&pci->dev, "ACP de-init failed\n");
return ret;
}
static int snd_acp63_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct acp63_dev_data *adata;
u32 addr;
u32 irqflags, flag;
int val;
int ret;
irqflags = IRQF_SHARED;
/* Return if acp config flag is defined */
flag = snd_amd_acp_find_config(pci);
if (flag)
return -ENODEV;
/* Pink Sardine device check */
switch (pci->revision) {
case 0x63:
break;
default:
dev_dbg(&pci->dev, "acp63 pci device not found\n");
return -ENODEV;
}
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
return -ENODEV;
}
ret = pci_request_regions(pci, "AMD ACP6.2 audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
adata = devm_kzalloc(&pci->dev, sizeof(struct acp63_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
goto release_regions;
}
addr = pci_resource_start(pci, 0);
adata->acp63_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
if (!adata->acp63_base) {
ret = -ENOMEM;
goto release_regions;
}
/*
* By default acp_reset flag is set to true. i.e acp_deinit() and acp_init()
* will be invoked for all ACP configurations during suspend/resume callbacks.
* This flag should be set to false only when SoundWire manager power mode
* set to ClockStopMode.
*/
adata->acp_reset = true;
pci_set_master(pci);
pci_set_drvdata(pci, adata);
mutex_init(&adata->acp_lock);
ret = acp63_init(adata->acp63_base, &pci->dev);
if (ret)
goto release_regions;
ret = devm_request_threaded_irq(&pci->dev, pci->irq, acp63_irq_handler,
acp63_irq_thread, irqflags, "ACP_PCI_IRQ", adata);
if (ret) {
dev_err(&pci->dev, "ACP PCI IRQ request failed\n");
goto de_init;
}
val = readl(adata->acp63_base + ACP_PIN_CONFIG);
ret = get_acp63_device_config(val, pci, adata);
/* ACP PCI driver probe should be continued even PDM or SoundWire Devices are not found */
if (ret) {
dev_dbg(&pci->dev, "get acp device config failed:%d\n", ret);
goto skip_pdev_creation;
}
ret = create_acp63_platform_devs(pci, adata, addr);
if (ret < 0) {
dev_err(&pci->dev, "ACP platform devices creation failed\n");
goto de_init;
}
skip_pdev_creation:
pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return 0;
de_init:
if (acp63_deinit(adata->acp63_base, &pci->dev))
dev_err(&pci->dev, "ACP de-init failed\n");
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
}
static int __maybe_unused snd_acp63_suspend(struct device *dev)
{
struct acp63_dev_data *adata;
int ret = 0;
adata = dev_get_drvdata(dev);
if (adata->acp_reset) {
ret = acp63_deinit(adata->acp63_base, dev);
if (ret)
dev_err(dev, "ACP de-init failed\n");
}
return ret;
}
static int __maybe_unused snd_acp63_resume(struct device *dev)
{
struct acp63_dev_data *adata;
int ret = 0;
adata = dev_get_drvdata(dev);
if (adata->acp_reset) {
ret = acp63_init(adata->acp63_base, dev);
if (ret)
dev_err(dev, "ACP init failed\n");
}
return ret;
}
static const struct dev_pm_ops acp63_pm_ops = {
SET_RUNTIME_PM_OPS(snd_acp63_suspend, snd_acp63_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(snd_acp63_suspend, snd_acp63_resume)
};
static void snd_acp63_remove(struct pci_dev *pci)
{
struct acp63_dev_data *adata;
int ret, index;
adata = pci_get_drvdata(pci);
for (index = 0; index < adata->pdev_count; index++)
platform_device_unregister(adata->pdev[index]);
ret = acp63_deinit(adata->acp63_base, &pci->dev);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
pci_release_regions(pci);
pci_disable_device(pci);
}
static const struct pci_device_id snd_acp63_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_acp63_ids);
static struct pci_driver ps_acp63_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_acp63_ids,
.probe = snd_acp63_probe,
.remove = snd_acp63_remove,
.driver = {
.pm = &acp63_pm_ops,
}
};
module_pci_driver(ps_acp63_driver);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("AMD ACP Pink Sardine PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/ps/pci-ps.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* AMD RPL ACP PCI Driver
*
* Copyright 2022 Advanced Micro Devices, Inc.
*/
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include "rpl_acp6x.h"
struct rpl_dev_data {
void __iomem *acp6x_base;
};
static int rpl_power_on(void __iomem *acp_base)
{
u32 val;
int timeout;
val = rpl_acp_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return val;
if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
rpl_acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
timeout = 0;
while (++timeout < 500) {
val = rpl_acp_readl(acp_base + ACP_PGFSM_STATUS);
if (!val)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int rpl_reset(void __iomem *acp_base)
{
u32 val;
int timeout;
rpl_acp_writel(1, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = rpl_acp_readl(acp_base + ACP_SOFT_RESET);
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
break;
cpu_relax();
}
rpl_acp_writel(0, acp_base + ACP_SOFT_RESET);
timeout = 0;
while (++timeout < 500) {
val = rpl_acp_readl(acp_base + ACP_SOFT_RESET);
if (!val)
return 0;
cpu_relax();
}
return -ETIMEDOUT;
}
static int rpl_init(void __iomem *acp_base)
{
int ret;
/* power on */
ret = rpl_power_on(acp_base);
if (ret) {
pr_err("ACP power on failed\n");
return ret;
}
rpl_acp_writel(0x01, acp_base + ACP_CONTROL);
/* Reset */
ret = rpl_reset(acp_base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
rpl_acp_writel(0x03, acp_base + ACP_CLKMUX_SEL);
return 0;
}
static int rpl_deinit(void __iomem *acp_base)
{
int ret;
/* Reset */
ret = rpl_reset(acp_base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
rpl_acp_writel(0x00, acp_base + ACP_CLKMUX_SEL);
rpl_acp_writel(0x00, acp_base + ACP_CONTROL);
return 0;
}
static int snd_rpl_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
struct rpl_dev_data *adata;
u32 addr;
int ret;
/* RPL device check */
switch (pci->revision) {
case 0x62:
break;
default:
dev_dbg(&pci->dev, "acp6x pci device not found\n");
return -ENODEV;
}
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
return -ENODEV;
}
ret = pci_request_regions(pci, "AMD ACP6x audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
goto disable_pci;
}
adata = devm_kzalloc(&pci->dev, sizeof(struct rpl_dev_data),
GFP_KERNEL);
if (!adata) {
ret = -ENOMEM;
goto release_regions;
}
addr = pci_resource_start(pci, 0);
adata->acp6x_base = devm_ioremap(&pci->dev, addr,
pci_resource_len(pci, 0));
if (!adata->acp6x_base) {
ret = -ENOMEM;
goto release_regions;
}
pci_set_master(pci);
pci_set_drvdata(pci, adata);
ret = rpl_init(adata->acp6x_base);
if (ret)
goto release_regions;
pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return 0;
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
}
static int __maybe_unused snd_rpl_suspend(struct device *dev)
{
struct rpl_dev_data *adata;
int ret;
adata = dev_get_drvdata(dev);
ret = rpl_deinit(adata->acp6x_base);
if (ret)
dev_err(dev, "ACP de-init failed\n");
return ret;
}
static int __maybe_unused snd_rpl_resume(struct device *dev)
{
struct rpl_dev_data *adata;
int ret;
adata = dev_get_drvdata(dev);
ret = rpl_init(adata->acp6x_base);
if (ret)
dev_err(dev, "ACP init failed\n");
return ret;
}
static const struct dev_pm_ops rpl_pm = {
SET_RUNTIME_PM_OPS(snd_rpl_suspend, snd_rpl_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(snd_rpl_suspend, snd_rpl_resume)
};
static void snd_rpl_remove(struct pci_dev *pci)
{
struct rpl_dev_data *adata;
int ret;
adata = pci_get_drvdata(pci);
ret = rpl_deinit(adata->acp6x_base);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
pci_release_regions(pci);
pci_disable_device(pci);
}
static const struct pci_device_id snd_rpl_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
.class_mask = 0xffffff },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_rpl_ids);
static struct pci_driver rpl_acp6x_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_rpl_ids,
.probe = snd_rpl_probe,
.remove = snd_rpl_remove,
.driver = {
.pm = &rpl_pm,
}
};
module_pci_driver(rpl_acp6x_driver);
MODULE_DESCRIPTION("AMD ACP RPL PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/rpl/rpl-pci-acp6x.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Advanced Micro Devices, Inc. All rights reserved.
//
// Authors: Ajit Kumar Pandey <[email protected]>
/*
* Generic PCI interface for ACP device
*/
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include "amd.h"
#include "../mach-config.h"
#define DRV_NAME "acp_pci"
#define ACP3x_REG_START 0x1240000
#define ACP3x_REG_END 0x125C000
static struct platform_device *dmic_dev;
static struct platform_device *pdev;
static const struct resource acp_res[] = {
{
.start = 0,
.end = ACP3x_REG_END - ACP3x_REG_START,
.name = "acp_mem",
.flags = IORESOURCE_MEM,
},
{
.start = 0,
.end = 0,
.name = "acp_dai_irq",
.flags = IORESOURCE_IRQ,
},
};
static int acp_pci_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
{
struct platform_device_info pdevinfo;
struct device *dev = &pci->dev;
const struct resource *res_acp;
struct acp_chip_info *chip;
struct resource *res;
unsigned int flag, addr, num_res, i;
int ret;
flag = snd_amd_acp_find_config(pci);
if (flag != FLAG_AMD_LEGACY)
return -ENODEV;
chip = devm_kzalloc(&pci->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
if (pci_enable_device(pci))
return dev_err_probe(&pci->dev, -ENODEV,
"pci_enable_device failed\n");
ret = pci_request_regions(pci, "AMD ACP3x audio");
if (ret < 0) {
dev_err(&pci->dev, "pci_request_regions failed\n");
ret = -ENOMEM;
goto disable_pci;
}
pci_set_master(pci);
res_acp = acp_res;
num_res = ARRAY_SIZE(acp_res);
switch (pci->revision) {
case 0x01:
chip->name = "acp_asoc_renoir";
chip->acp_rev = ACP3X_DEV;
break;
case 0x6f:
chip->name = "acp_asoc_rembrandt";
chip->acp_rev = ACP6X_DEV;
break;
default:
dev_err(dev, "Unsupported device revision:0x%x\n", pci->revision);
ret = -EINVAL;
goto release_regions;
}
dmic_dev = platform_device_register_data(dev, "dmic-codec", PLATFORM_DEVID_NONE, NULL, 0);
if (IS_ERR(dmic_dev)) {
dev_err(dev, "failed to create DMIC device\n");
ret = PTR_ERR(dmic_dev);
goto release_regions;
}
addr = pci_resource_start(pci, 0);
chip->base = devm_ioremap(&pci->dev, addr, pci_resource_len(pci, 0));
if (!chip->base) {
ret = -ENOMEM;
goto unregister_dmic_dev;
}
acp_init(chip);
res = devm_kcalloc(&pci->dev, num_res, sizeof(struct resource), GFP_KERNEL);
if (!res) {
ret = -ENOMEM;
goto unregister_dmic_dev;
}
for (i = 0; i < num_res; i++, res_acp++) {
res[i].name = res_acp->name;
res[i].flags = res_acp->flags;
res[i].start = addr + res_acp->start;
res[i].end = addr + res_acp->end;
if (res_acp->flags == IORESOURCE_IRQ) {
res[i].start = pci->irq;
res[i].end = res[i].start;
}
}
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.name = chip->name;
pdevinfo.id = 0;
pdevinfo.parent = &pci->dev;
pdevinfo.num_res = num_res;
pdevinfo.res = &res[0];
pdevinfo.data = chip;
pdevinfo.size_data = sizeof(*chip);
pdev = platform_device_register_full(&pdevinfo);
if (IS_ERR(pdev)) {
dev_err(&pci->dev, "cannot register %s device\n", pdevinfo.name);
ret = PTR_ERR(pdev);
goto unregister_dmic_dev;
}
chip->chip_pdev = pdev;
dev_set_drvdata(&pci->dev, chip);
pm_runtime_set_autosuspend_delay(&pci->dev, 2000);
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_put_noidle(&pci->dev);
pm_runtime_allow(&pci->dev);
return ret;
unregister_dmic_dev:
platform_device_unregister(dmic_dev);
release_regions:
pci_release_regions(pci);
disable_pci:
pci_disable_device(pci);
return ret;
};
static int __maybe_unused snd_acp_suspend(struct device *dev)
{
struct acp_chip_info *chip;
int ret;
chip = dev_get_drvdata(dev);
ret = acp_deinit(chip->base);
if (ret)
dev_err(dev, "ACP de-init failed\n");
return ret;
}
static int __maybe_unused snd_acp_resume(struct device *dev)
{
struct acp_chip_info *chip;
struct acp_dev_data *adata;
struct device child;
int ret;
chip = dev_get_drvdata(dev);
ret = acp_init(chip);
if (ret)
dev_err(dev, "ACP init failed\n");
child = chip->chip_pdev->dev;
adata = dev_get_drvdata(&child);
if (adata)
acp_enable_interrupts(adata);
return ret;
}
static const struct dev_pm_ops acp_pm_ops = {
SET_RUNTIME_PM_OPS(snd_acp_suspend, snd_acp_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(snd_acp_suspend, snd_acp_resume)
};
static void acp_pci_remove(struct pci_dev *pci)
{
struct acp_chip_info *chip;
int ret;
chip = pci_get_drvdata(pci);
pm_runtime_forbid(&pci->dev);
pm_runtime_get_noresume(&pci->dev);
if (dmic_dev)
platform_device_unregister(dmic_dev);
if (pdev)
platform_device_unregister(pdev);
ret = acp_deinit(chip->base);
if (ret)
dev_err(&pci->dev, "ACP de-init failed\n");
}
/* PCI IDs */
static const struct pci_device_id acp_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_PCI_DEV_ID)},
{ 0, }
};
MODULE_DEVICE_TABLE(pci, acp_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_amd_acp_pci_driver = {
.name = KBUILD_MODNAME,
.id_table = acp_pci_ids,
.probe = acp_pci_probe,
.remove = acp_pci_remove,
.driver = {
.pm = &acp_pm_ops,
},
};
module_pci_driver(snd_amd_acp_pci_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_ACP_COMMON);
MODULE_ALIAS(DRV_NAME);
| linux-master | sound/soc/amd/acp/acp-pci.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
/*
* Generic interface for ACP audio blck PCM component
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
#include "amd.h"
#define DRV_NAME "acp_i2s_dma"
static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_96000,
.rate_min = 8000,
.rate_max = 96000,
.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
};
static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
};
int acp_machine_select(struct acp_dev_data *adata)
{
struct snd_soc_acpi_mach *mach;
int size;
size = sizeof(*adata->machines);
mach = snd_soc_acpi_find_machine(adata->machines);
if (!mach) {
dev_err(adata->dev, "warning: No matching ASoC machine driver found\n");
return -EINVAL;
}
adata->mach_dev = platform_device_register_data(adata->dev, mach->drv_name,
PLATFORM_DEVID_NONE, mach, size);
if (IS_ERR(adata->mach_dev))
dev_warn(adata->dev, "Unable to register Machine device\n");
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_machine_select, SND_SOC_ACP_COMMON);
static irqreturn_t i2s_irq_handler(int irq, void *data)
{
struct acp_dev_data *adata = data;
struct acp_resource *rsrc = adata->rsrc;
struct acp_stream *stream;
u16 i2s_flag = 0;
u32 ext_intr_stat, ext_intr_stat1;
if (!adata)
return IRQ_NONE;
if (adata->rsrc->no_of_ctrls == 2)
ext_intr_stat1 = readl(ACP_EXTERNAL_INTR_STAT(adata, (rsrc->irqp_used - 1)));
ext_intr_stat = readl(ACP_EXTERNAL_INTR_STAT(adata, rsrc->irqp_used));
spin_lock(&adata->acp_lock);
list_for_each_entry(stream, &adata->stream_list, list) {
if (ext_intr_stat & stream->irq_bit) {
writel(stream->irq_bit,
ACP_EXTERNAL_INTR_STAT(adata, rsrc->irqp_used));
snd_pcm_period_elapsed(stream->substream);
i2s_flag = 1;
}
if (adata->rsrc->no_of_ctrls == 2) {
if (ext_intr_stat1 & stream->irq_bit) {
writel(stream->irq_bit, ACP_EXTERNAL_INTR_STAT(adata,
(rsrc->irqp_used - 1)));
snd_pcm_period_elapsed(stream->substream);
i2s_flag = 1;
}
}
}
spin_unlock(&adata->acp_lock);
if (i2s_flag)
return IRQ_HANDLED;
return IRQ_NONE;
}
void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream)
{
struct acp_resource *rsrc = adata->rsrc;
u32 pte_reg, pte_size, reg_val;
/* Use ATU base Group5 */
pte_reg = ACPAXI2AXI_ATU_BASE_ADDR_GRP_5;
pte_size = ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5;
stream->reg_offset = 0x02000000;
/* Group Enable */
reg_val = rsrc->sram_pte_offset;
writel(reg_val | BIT(31), adata->acp_base + pte_reg);
writel(PAGE_SIZE_4K_ENABLE, adata->acp_base + pte_size);
writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
}
EXPORT_SYMBOL_NS_GPL(config_pte_for_stream, SND_SOC_ACP_COMMON);
void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size)
{
struct snd_pcm_substream *substream = stream->substream;
struct acp_resource *rsrc = adata->rsrc;
dma_addr_t addr = substream->dma_buffer.addr;
int num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
u32 low, high, val;
u16 page_idx;
val = stream->pte_offset;
for (page_idx = 0; page_idx < num_pages; page_idx++) {
/* Load the low address of page int ACP SRAM through SRBM */
low = lower_32_bits(addr);
high = upper_32_bits(addr);
writel(low, adata->acp_base + rsrc->scratch_reg_offset + val);
high |= BIT(31);
writel(high, adata->acp_base + rsrc->scratch_reg_offset + val + 4);
/* Move to next physically contiguous page */
val += 8;
addr += PAGE_SIZE;
}
}
EXPORT_SYMBOL_NS_GPL(config_acp_dma, SND_SOC_ACP_COMMON);
static int acp_dma_open(struct snd_soc_component *component, struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct device *dev = component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_stream *stream;
int ret;
stream = kzalloc(sizeof(*stream), GFP_KERNEL);
if (!stream)
return -ENOMEM;
stream->substream = substream;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = acp_pcm_hardware_playback;
else
runtime->hw = acp_pcm_hardware_capture;
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(component->dev, "set integer constraint failed\n");
kfree(stream);
return ret;
}
runtime->private_data = stream;
writel(1, ACP_EXTERNAL_INTR_ENB(adata));
spin_lock_irq(&adata->acp_lock);
list_add_tail(&stream->list, &adata->stream_list);
spin_unlock_irq(&adata->acp_lock);
return ret;
}
static int acp_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct acp_dev_data *adata = snd_soc_component_get_drvdata(component);
struct acp_stream *stream = substream->runtime->private_data;
u64 size = params_buffer_bytes(params);
/* Configure ACP DMA block with params */
config_pte_for_stream(adata, stream);
config_acp_dma(adata, stream, size);
return 0;
}
static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct device *dev = component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_stream *stream = substream->runtime->private_data;
u32 pos, buffersize;
u64 bytescount;
buffersize = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
bytescount = acp_get_byte_count(adata, stream->dai_id, substream->stream);
if (bytescount > stream->bytescount)
bytescount -= stream->bytescount;
pos = do_div(bytescount, buffersize);
return bytes_to_frames(substream->runtime, pos);
}
static int acp_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct device *parent = component->dev->parent;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
parent, MIN_BUFFER, MAX_BUFFER);
return 0;
}
static int acp_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct device *dev = component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_stream *stream = substream->runtime->private_data;
/* Remove entry from list */
spin_lock_irq(&adata->acp_lock);
list_del(&stream->list);
spin_unlock_irq(&adata->acp_lock);
kfree(stream);
return 0;
}
static const struct snd_soc_component_driver acp_pcm_component = {
.name = DRV_NAME,
.open = acp_dma_open,
.close = acp_dma_close,
.hw_params = acp_dma_hw_params,
.pointer = acp_dma_pointer,
.pcm_construct = acp_dma_new,
.legacy_dai_naming = 1,
};
int acp_platform_register(struct device *dev)
{
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct snd_soc_dai_driver;
unsigned int status;
status = devm_request_irq(dev, adata->i2s_irq, i2s_irq_handler,
IRQF_SHARED, "ACP_I2S_IRQ", adata);
if (status) {
dev_err(dev, "ACP I2S IRQ request failed\n");
return status;
}
status = devm_snd_soc_register_component(dev, &acp_pcm_component,
adata->dai_driver,
adata->num_dai);
if (status) {
dev_err(dev, "Fail to register acp i2s component\n");
return status;
}
INIT_LIST_HEAD(&adata->stream_list);
spin_lock_init(&adata->acp_lock);
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_platform_register, SND_SOC_ACP_COMMON);
int acp_platform_unregister(struct device *dev)
{
struct acp_dev_data *adata = dev_get_drvdata(dev);
if (adata->mach_dev)
platform_device_unregister(adata->mach_dev);
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_platform_unregister, SND_SOC_ACP_COMMON);
MODULE_DESCRIPTION("AMD ACP PCM Driver");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS(DRV_NAME);
| linux-master | sound/soc/amd/acp/acp-platform.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
//
/*
* Machine Driver Legacy Support for ACP HW block
*/
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc-acpi.h>
#include <sound/soc-dapm.h>
#include <linux/dmi.h>
#include <linux/module.h>
#include "acp-mach.h"
static struct acp_card_drvdata rt5682_rt1019_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682,
.amp_codec_id = RT1019,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata rt5682s_max_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682S,
.amp_codec_id = MAX98360A,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata rt5682s_rt1019_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682S,
.amp_codec_id = RT1019,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata max_nau8825_data = {
.hs_cpu_id = I2S_HS,
.amp_cpu_id = I2S_HS,
.dmic_cpu_id = DMIC,
.hs_codec_id = NAU8825,
.amp_codec_id = MAX98360A,
.dmic_codec_id = DMIC,
.soc_mclk = true,
.platform = REMBRANDT,
.tdm_mode = false,
};
static struct acp_card_drvdata rt5682s_rt1019_rmb_data = {
.hs_cpu_id = I2S_HS,
.amp_cpu_id = I2S_HS,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682S,
.amp_codec_id = RT1019,
.dmic_codec_id = DMIC,
.soc_mclk = true,
.platform = REMBRANDT,
.tdm_mode = false,
};
static int acp_asoc_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = NULL;
struct device *dev = &pdev->dev;
const struct dmi_system_id *dmi_id;
struct acp_card_drvdata *acp_card_drvdata;
int ret;
if (!pdev->id_entry)
return -EINVAL;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->dev = dev;
card->owner = THIS_MODULE;
card->name = pdev->id_entry->name;
card->drvdata = (struct acp_card_drvdata *)pdev->id_entry->driver_data;
/* Widgets and controls added per-codec in acp-mach-common.c */
acp_card_drvdata = card->drvdata;
dmi_id = dmi_first_match(acp_quirk_table);
if (dmi_id && dmi_id->driver_data)
acp_card_drvdata->tdm_mode = dmi_id->driver_data;
acp_legacy_dai_links_create(card);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
dev_err(&pdev->dev,
"devm_snd_soc_register_card(%s) failed: %d\n",
card->name, ret);
return ret;
}
return 0;
}
static const struct platform_device_id board_ids[] = {
{
.name = "acp3xalc56821019",
.driver_data = (kernel_ulong_t)&rt5682_rt1019_data,
},
{
.name = "acp3xalc5682sm98360",
.driver_data = (kernel_ulong_t)&rt5682s_max_data,
},
{
.name = "acp3xalc5682s1019",
.driver_data = (kernel_ulong_t)&rt5682s_rt1019_data,
},
{
.name = "rmb-nau8825-max",
.driver_data = (kernel_ulong_t)&max_nau8825_data,
},
{
.name = "rmb-rt5682s-rt1019",
.driver_data = (kernel_ulong_t)&rt5682s_rt1019_rmb_data,
},
{ }
};
static struct platform_driver acp_asoc_audio = {
.driver = {
.pm = &snd_soc_pm_ops,
.name = "acp_mach",
},
.probe = acp_asoc_probe,
.id_table = board_ids,
};
module_platform_driver(acp_asoc_audio);
MODULE_IMPORT_NS(SND_SOC_AMD_MACH);
MODULE_DESCRIPTION("ACP chrome audio support");
MODULE_ALIAS("platform:acp3xalc56821019");
MODULE_ALIAS("platform:acp3xalc5682sm98360");
MODULE_ALIAS("platform:acp3xalc5682s1019");
MODULE_ALIAS("platform:rmb-nau8825-max");
MODULE_ALIAS("platform:rmb-rt5682s-rt1019");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp/acp-legacy-mach.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2023 Advanced Micro Devices, Inc.
//
// Authors: Syed Saba Kareem <[email protected]>
//
/*
* Common file to be used by amd platforms
*/
#include "amd.h"
#include <linux/pci.h>
#include <linux/export.h>
void acp_enable_interrupts(struct acp_dev_data *adata)
{
struct acp_resource *rsrc = adata->rsrc;
u32 ext_intr_ctrl;
writel(0x01, ACP_EXTERNAL_INTR_ENB(adata));
ext_intr_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
ext_intr_ctrl |= ACP_ERROR_MASK;
writel(ext_intr_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
}
EXPORT_SYMBOL_NS_GPL(acp_enable_interrupts, SND_SOC_ACP_COMMON);
void acp_disable_interrupts(struct acp_dev_data *adata)
{
struct acp_resource *rsrc = adata->rsrc;
writel(ACP_EXT_INTR_STAT_CLEAR_MASK, ACP_EXTERNAL_INTR_STAT(adata, rsrc->irqp_used));
writel(0x00, ACP_EXTERNAL_INTR_ENB(adata));
}
EXPORT_SYMBOL_NS_GPL(acp_disable_interrupts, SND_SOC_ACP_COMMON);
static void set_acp_pdm_ring_buffer(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct acp_stream *stream = runtime->private_data;
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
u32 physical_addr, pdm_size, period_bytes;
period_bytes = frames_to_bytes(runtime, runtime->period_size);
pdm_size = frames_to_bytes(runtime, runtime->buffer_size);
physical_addr = stream->reg_offset + MEM_WINDOW_START;
/* Init ACP PDM Ring buffer */
writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);
writel(pdm_size, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);
writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
}
static void set_acp_pdm_clk(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
unsigned int pdm_ctrl;
/* Enable default ACP PDM clk */
writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);
pdm_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
pdm_ctrl |= PDM_MISC_CTRL_MASK;
writel(pdm_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);
set_acp_pdm_ring_buffer(substream, dai);
}
void restore_acp_pdm_params(struct snd_pcm_substream *substream,
struct acp_dev_data *adata)
{
struct snd_soc_dai *dai;
struct snd_soc_pcm_runtime *soc_runtime;
u32 ext_int_ctrl;
soc_runtime = asoc_substream_to_rtd(substream);
dai = asoc_rtd_to_cpu(soc_runtime, 0);
/* Programming channel mask and sampling rate */
writel(adata->ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);
/* Enabling ACP Pdm interuppts */
ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
ext_int_ctrl |= PDM_DMA_INTR_MASK;
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
set_acp_pdm_clk(substream, dai);
}
EXPORT_SYMBOL_NS_GPL(restore_acp_pdm_params, SND_SOC_ACP_COMMON);
static int set_acp_i2s_dma_fifo(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_resource *rsrc = adata->rsrc;
struct acp_stream *stream = substream->runtime->private_data;
u32 reg_dma_size, reg_fifo_size, reg_fifo_addr;
u32 phy_addr, acp_fifo_addr, ext_int_ctrl;
unsigned int dir = substream->stream;
switch (dai->driver->id) {
case I2S_SP_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
reg_dma_size = ACP_I2S_TX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
SP_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_I2S_TX_RINGBUFADDR);
} else {
reg_dma_size = ACP_I2S_RX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
SP_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_I2S_RX_RINGBUFADDR);
}
break;
case I2S_BT_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
reg_dma_size = ACP_BT_TX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
BT_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_BT_TX_FIFOADDR;
reg_fifo_size = ACP_BT_TX_FIFOSIZE;
phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_BT_TX_RINGBUFADDR);
} else {
reg_dma_size = ACP_BT_RX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
BT_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_BT_RX_FIFOADDR;
reg_fifo_size = ACP_BT_RX_FIFOSIZE;
phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_BT_RX_RINGBUFADDR);
}
break;
case I2S_HS_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
reg_dma_size = ACP_HS_TX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
HS_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_HS_TX_FIFOADDR;
reg_fifo_size = ACP_HS_TX_FIFOSIZE;
phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_HS_TX_RINGBUFADDR);
} else {
reg_dma_size = ACP_HS_RX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
HS_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_HS_RX_FIFOADDR;
reg_fifo_size = ACP_HS_RX_FIFOSIZE;
phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_HS_RX_RINGBUFADDR);
}
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
writel(DMA_SIZE, adata->acp_base + reg_dma_size);
writel(acp_fifo_addr, adata->acp_base + reg_fifo_addr);
writel(FIFO_SIZE, adata->acp_base + reg_fifo_size);
ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
ext_int_ctrl |= BIT(I2S_RX_THRESHOLD(rsrc->offset)) |
BIT(BT_RX_THRESHOLD(rsrc->offset)) |
BIT(I2S_TX_THRESHOLD(rsrc->offset)) |
BIT(BT_TX_THRESHOLD(rsrc->offset)) |
BIT(HS_RX_THRESHOLD(rsrc->offset)) |
BIT(HS_TX_THRESHOLD(rsrc->offset));
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
return 0;
}
int restore_acp_i2s_params(struct snd_pcm_substream *substream,
struct acp_dev_data *adata,
struct acp_stream *stream)
{
struct snd_soc_dai *dai;
struct snd_soc_pcm_runtime *soc_runtime;
u32 tdm_fmt, reg_val, fmt_reg, val;
soc_runtime = asoc_substream_to_rtd(substream);
dai = asoc_rtd_to_cpu(soc_runtime, 0);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
tdm_fmt = adata->tdm_tx_fmt[stream->dai_id - 1];
switch (stream->dai_id) {
case I2S_BT_INSTANCE:
reg_val = ACP_BTTDM_ITER;
fmt_reg = ACP_BTTDM_TXFRMT;
break;
case I2S_SP_INSTANCE:
reg_val = ACP_I2STDM_ITER;
fmt_reg = ACP_I2STDM_TXFRMT;
break;
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_ITER;
fmt_reg = ACP_HSTDM_TXFRMT;
break;
default:
pr_err("Invalid dai id %x\n", stream->dai_id);
return -EINVAL;
}
val = adata->xfer_tx_resolution[stream->dai_id - 1] << 3;
} else {
tdm_fmt = adata->tdm_rx_fmt[stream->dai_id - 1];
switch (stream->dai_id) {
case I2S_BT_INSTANCE:
reg_val = ACP_BTTDM_IRER;
fmt_reg = ACP_BTTDM_RXFRMT;
break;
case I2S_SP_INSTANCE:
reg_val = ACP_I2STDM_IRER;
fmt_reg = ACP_I2STDM_RXFRMT;
break;
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_IRER;
fmt_reg = ACP_HSTDM_RXFRMT;
break;
default:
pr_err("Invalid dai id %x\n", stream->dai_id);
return -EINVAL;
}
val = adata->xfer_rx_resolution[stream->dai_id - 1] << 3;
}
writel(val, adata->acp_base + reg_val);
if (adata->tdm_mode == TDM_ENABLE) {
writel(tdm_fmt, adata->acp_base + fmt_reg);
val = readl(adata->acp_base + reg_val);
writel(val | 0x2, adata->acp_base + reg_val);
}
return set_acp_i2s_dma_fifo(substream, dai);
}
EXPORT_SYMBOL_NS_GPL(restore_acp_i2s_params, SND_SOC_ACP_COMMON);
static int acp_power_on(struct acp_chip_info *chip)
{
u32 val, acp_pgfsm_stat_reg, acp_pgfsm_ctrl_reg;
void __iomem *base;
base = chip->base;
switch (chip->acp_rev) {
case ACP3X_DEV:
acp_pgfsm_stat_reg = ACP_PGFSM_STATUS;
acp_pgfsm_ctrl_reg = ACP_PGFSM_CONTROL;
break;
case ACP6X_DEV:
acp_pgfsm_stat_reg = ACP6X_PGFSM_STATUS;
acp_pgfsm_ctrl_reg = ACP6X_PGFSM_CONTROL;
break;
default:
return -EINVAL;
}
val = readl(base + acp_pgfsm_stat_reg);
if (val == ACP_POWERED_ON)
return 0;
if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
writel(ACP_PGFSM_CNTL_POWER_ON_MASK, base + acp_pgfsm_ctrl_reg);
return readl_poll_timeout(base + acp_pgfsm_stat_reg, val,
!val, DELAY_US, ACP_TIMEOUT);
}
static int acp_reset(void __iomem *base)
{
u32 val;
int ret;
writel(1, base + ACP_SOFT_RESET);
ret = readl_poll_timeout(base + ACP_SOFT_RESET, val, val & ACP_SOFT_RST_DONE_MASK,
DELAY_US, ACP_TIMEOUT);
if (ret)
return ret;
writel(0, base + ACP_SOFT_RESET);
return readl_poll_timeout(base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT);
}
int acp_init(struct acp_chip_info *chip)
{
int ret;
/* power on */
ret = acp_power_on(chip);
if (ret) {
pr_err("ACP power on failed\n");
return ret;
}
writel(0x01, chip->base + ACP_CONTROL);
/* Reset */
ret = acp_reset(chip->base);
if (ret) {
pr_err("ACP reset failed\n");
return ret;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_init, SND_SOC_ACP_COMMON);
int acp_deinit(void __iomem *base)
{
int ret;
/* Reset */
ret = acp_reset(base);
if (ret)
return ret;
writel(0, base + ACP_CONTROL);
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_deinit, SND_SOC_ACP_COMMON);
int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
{
pci_write_config_dword(dev, 0x60, smn_addr);
pci_write_config_dword(dev, 0x64, data);
return 0;
}
EXPORT_SYMBOL_NS_GPL(smn_write, SND_SOC_ACP_COMMON);
int smn_read(struct pci_dev *dev, u32 smn_addr)
{
u32 data;
pci_write_config_dword(dev, 0x60, smn_addr);
pci_read_config_dword(dev, 0x64, &data);
return data;
}
EXPORT_SYMBOL_NS_GPL(smn_read, SND_SOC_ACP_COMMON);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/amd/acp/acp-legacy-common.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
//
/*
* Generic Hardware interface for ACP Audio I2S controller
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
#include "amd.h"
#define DRV_NAME "acp_i2s_playcap"
static int acp_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct acp_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai);
int mode;
mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
switch (mode) {
case SND_SOC_DAIFMT_I2S:
adata->tdm_mode = TDM_DISABLE;
break;
case SND_SOC_DAIFMT_DSP_A:
adata->tdm_mode = TDM_ENABLE;
break;
default:
return -EINVAL;
}
return 0;
}
static int acp_i2s_set_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, u32 rx_mask,
int slots, int slot_width)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = snd_soc_dai_get_drvdata(dai);
struct acp_stream *stream;
int slot_len, no_of_slots;
switch (slot_width) {
case SLOT_WIDTH_8:
slot_len = 8;
break;
case SLOT_WIDTH_16:
slot_len = 16;
break;
case SLOT_WIDTH_24:
slot_len = 24;
break;
case SLOT_WIDTH_32:
slot_len = 0;
break;
default:
dev_err(dev, "Unsupported bitdepth %d\n", slot_width);
return -EINVAL;
}
switch (slots) {
case 1 ... 7:
no_of_slots = slots;
break;
case 8:
no_of_slots = 0;
break;
default:
dev_err(dev, "Unsupported slots %d\n", slots);
return -EINVAL;
}
slots = no_of_slots;
spin_lock_irq(&adata->acp_lock);
list_for_each_entry(stream, &adata->stream_list, list) {
if (tx_mask && stream->dir == SNDRV_PCM_STREAM_PLAYBACK)
adata->tdm_tx_fmt[stream->dai_id - 1] =
FRM_LEN | (slots << 15) | (slot_len << 18);
else if (rx_mask && stream->dir == SNDRV_PCM_STREAM_CAPTURE)
adata->tdm_rx_fmt[stream->dai_id - 1] =
FRM_LEN | (slots << 15) | (slot_len << 18);
}
spin_unlock_irq(&adata->acp_lock);
return 0;
}
static int acp_i2s_hwparams(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata;
struct acp_resource *rsrc;
u32 val;
u32 xfer_resolution;
u32 reg_val, fmt_reg, tdm_fmt;
u32 lrclk_div_val, bclk_div_val;
adata = snd_soc_dai_get_drvdata(dai);
rsrc = adata->rsrc;
/* These values are as per Hardware Spec */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U8:
case SNDRV_PCM_FORMAT_S8:
xfer_resolution = 0x0;
break;
case SNDRV_PCM_FORMAT_S16_LE:
xfer_resolution = 0x02;
break;
case SNDRV_PCM_FORMAT_S24_LE:
xfer_resolution = 0x04;
break;
case SNDRV_PCM_FORMAT_S32_LE:
xfer_resolution = 0x05;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (dai->driver->id) {
case I2S_BT_INSTANCE:
reg_val = ACP_BTTDM_ITER;
fmt_reg = ACP_BTTDM_TXFRMT;
break;
case I2S_SP_INSTANCE:
reg_val = ACP_I2STDM_ITER;
fmt_reg = ACP_I2STDM_TXFRMT;
break;
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_ITER;
fmt_reg = ACP_HSTDM_TXFRMT;
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
adata->xfer_tx_resolution[dai->driver->id - 1] = xfer_resolution;
} else {
switch (dai->driver->id) {
case I2S_BT_INSTANCE:
reg_val = ACP_BTTDM_IRER;
fmt_reg = ACP_BTTDM_RXFRMT;
break;
case I2S_SP_INSTANCE:
reg_val = ACP_I2STDM_IRER;
fmt_reg = ACP_I2STDM_RXFRMT;
break;
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_IRER;
fmt_reg = ACP_HSTDM_RXFRMT;
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
adata->xfer_rx_resolution[dai->driver->id - 1] = xfer_resolution;
}
val = readl(adata->acp_base + reg_val);
val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK;
val = val | (xfer_resolution << 3);
writel(val, adata->acp_base + reg_val);
if (adata->tdm_mode) {
val = readl(adata->acp_base + reg_val);
writel(val | BIT(1), adata->acp_base + reg_val);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tdm_fmt = adata->tdm_tx_fmt[dai->driver->id - 1];
else
tdm_fmt = adata->tdm_rx_fmt[dai->driver->id - 1];
writel(tdm_fmt, adata->acp_base + fmt_reg);
}
if (rsrc->soc_mclk) {
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
switch (params_rate(params)) {
case 8000:
bclk_div_val = 768;
break;
case 16000:
bclk_div_val = 384;
break;
case 24000:
bclk_div_val = 256;
break;
case 32000:
bclk_div_val = 192;
break;
case 44100:
case 48000:
bclk_div_val = 128;
break;
case 88200:
case 96000:
bclk_div_val = 64;
break;
case 192000:
bclk_div_val = 32;
break;
default:
return -EINVAL;
}
lrclk_div_val = 32;
break;
case SNDRV_PCM_FORMAT_S32_LE:
switch (params_rate(params)) {
case 8000:
bclk_div_val = 384;
break;
case 16000:
bclk_div_val = 192;
break;
case 24000:
bclk_div_val = 128;
break;
case 32000:
bclk_div_val = 96;
break;
case 44100:
case 48000:
bclk_div_val = 64;
break;
case 88200:
case 96000:
bclk_div_val = 32;
break;
case 192000:
bclk_div_val = 16;
break;
default:
return -EINVAL;
}
lrclk_div_val = 64;
break;
default:
return -EINVAL;
}
adata->lrclk_div = lrclk_div_val;
adata->bclk_div = bclk_div_val;
}
return 0;
}
static int acp_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
{
struct acp_stream *stream = substream->runtime->private_data;
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_resource *rsrc = adata->rsrc;
u32 val, period_bytes, reg_val, ier_val, water_val, buf_size, buf_reg;
period_bytes = frames_to_bytes(substream->runtime, substream->runtime->period_size);
buf_size = frames_to_bytes(substream->runtime, substream->runtime->buffer_size);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
stream->bytescount = acp_get_byte_count(adata, stream->dai_id, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (dai->driver->id) {
case I2S_BT_INSTANCE:
water_val = ACP_BT_TX_INTR_WATERMARK_SIZE;
reg_val = ACP_BTTDM_ITER;
ier_val = ACP_BTTDM_IER;
buf_reg = ACP_BT_TX_RINGBUFSIZE;
break;
case I2S_SP_INSTANCE:
water_val = ACP_I2S_TX_INTR_WATERMARK_SIZE;
reg_val = ACP_I2STDM_ITER;
ier_val = ACP_I2STDM_IER;
buf_reg = ACP_I2S_TX_RINGBUFSIZE;
break;
case I2S_HS_INSTANCE:
water_val = ACP_HS_TX_INTR_WATERMARK_SIZE;
reg_val = ACP_HSTDM_ITER;
ier_val = ACP_HSTDM_IER;
buf_reg = ACP_HS_TX_RINGBUFSIZE;
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
} else {
switch (dai->driver->id) {
case I2S_BT_INSTANCE:
water_val = ACP_BT_RX_INTR_WATERMARK_SIZE;
reg_val = ACP_BTTDM_IRER;
ier_val = ACP_BTTDM_IER;
buf_reg = ACP_BT_RX_RINGBUFSIZE;
break;
case I2S_SP_INSTANCE:
water_val = ACP_I2S_RX_INTR_WATERMARK_SIZE;
reg_val = ACP_I2STDM_IRER;
ier_val = ACP_I2STDM_IER;
buf_reg = ACP_I2S_RX_RINGBUFSIZE;
break;
case I2S_HS_INSTANCE:
water_val = ACP_HS_RX_INTR_WATERMARK_SIZE;
reg_val = ACP_HSTDM_IRER;
ier_val = ACP_HSTDM_IER;
buf_reg = ACP_HS_RX_RINGBUFSIZE;
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
}
writel(period_bytes, adata->acp_base + water_val);
writel(buf_size, adata->acp_base + buf_reg);
val = readl(adata->acp_base + reg_val);
val = val | BIT(0);
writel(val, adata->acp_base + reg_val);
writel(1, adata->acp_base + ier_val);
if (rsrc->soc_mclk)
acp_set_i2s_clk(adata, dai->driver->id);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (dai->driver->id) {
case I2S_BT_INSTANCE:
reg_val = ACP_BTTDM_ITER;
break;
case I2S_SP_INSTANCE:
reg_val = ACP_I2STDM_ITER;
break;
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_ITER;
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
} else {
switch (dai->driver->id) {
case I2S_BT_INSTANCE:
reg_val = ACP_BTTDM_IRER;
break;
case I2S_SP_INSTANCE:
reg_val = ACP_I2STDM_IRER;
break;
case I2S_HS_INSTANCE:
reg_val = ACP_HSTDM_IRER;
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
}
val = readl(adata->acp_base + reg_val);
val = val & ~BIT(0);
writel(val, adata->acp_base + reg_val);
if (!(readl(adata->acp_base + ACP_BTTDM_ITER) & BIT(0)) &&
!(readl(adata->acp_base + ACP_BTTDM_IRER) & BIT(0)))
writel(0, adata->acp_base + ACP_BTTDM_IER);
if (!(readl(adata->acp_base + ACP_I2STDM_ITER) & BIT(0)) &&
!(readl(adata->acp_base + ACP_I2STDM_IRER) & BIT(0)))
writel(0, adata->acp_base + ACP_I2STDM_IER);
if (!(readl(adata->acp_base + ACP_HSTDM_ITER) & BIT(0)) &&
!(readl(adata->acp_base + ACP_HSTDM_IRER) & BIT(0)))
writel(0, adata->acp_base + ACP_HSTDM_IER);
return 0;
default:
return -EINVAL;
}
return 0;
}
static int acp_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_resource *rsrc = adata->rsrc;
struct acp_stream *stream = substream->runtime->private_data;
u32 reg_dma_size = 0, reg_fifo_size = 0, reg_fifo_addr = 0;
u32 phy_addr = 0, acp_fifo_addr = 0, ext_int_ctrl;
unsigned int dir = substream->stream;
switch (dai->driver->id) {
case I2S_SP_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
reg_dma_size = ACP_I2S_TX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
SP_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_I2S_TX_RINGBUFADDR);
} else {
reg_dma_size = ACP_I2S_RX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
SP_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_I2S_RX_RINGBUFADDR);
}
break;
case I2S_BT_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
reg_dma_size = ACP_BT_TX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
BT_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_BT_TX_FIFOADDR;
reg_fifo_size = ACP_BT_TX_FIFOSIZE;
phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_BT_TX_RINGBUFADDR);
} else {
reg_dma_size = ACP_BT_RX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
BT_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_BT_RX_FIFOADDR;
reg_fifo_size = ACP_BT_RX_FIFOSIZE;
phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_BT_RX_RINGBUFADDR);
}
break;
case I2S_HS_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
reg_dma_size = ACP_HS_TX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
HS_PB_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_HS_TX_FIFOADDR;
reg_fifo_size = ACP_HS_TX_FIFOSIZE;
phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_HS_TX_RINGBUFADDR);
} else {
reg_dma_size = ACP_HS_RX_DMA_SIZE;
acp_fifo_addr = rsrc->sram_pte_offset +
HS_CAPT_FIFO_ADDR_OFFSET;
reg_fifo_addr = ACP_HS_RX_FIFOADDR;
reg_fifo_size = ACP_HS_RX_FIFOSIZE;
phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
writel(phy_addr, adata->acp_base + ACP_HS_RX_RINGBUFADDR);
}
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
writel(DMA_SIZE, adata->acp_base + reg_dma_size);
writel(acp_fifo_addr, adata->acp_base + reg_fifo_addr);
writel(FIFO_SIZE, adata->acp_base + reg_fifo_size);
ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
ext_int_ctrl |= BIT(I2S_RX_THRESHOLD(rsrc->offset)) |
BIT(BT_RX_THRESHOLD(rsrc->offset)) |
BIT(I2S_TX_THRESHOLD(rsrc->offset)) |
BIT(BT_TX_THRESHOLD(rsrc->offset)) |
BIT(HS_RX_THRESHOLD(rsrc->offset)) |
BIT(HS_TX_THRESHOLD(rsrc->offset));
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
return 0;
}
static int acp_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct acp_stream *stream = substream->runtime->private_data;
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_resource *rsrc = adata->rsrc;
unsigned int dir = substream->stream;
unsigned int irq_bit = 0;
switch (dai->driver->id) {
case I2S_SP_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
irq_bit = BIT(I2S_TX_THRESHOLD(rsrc->offset));
stream->pte_offset = ACP_SRAM_SP_PB_PTE_OFFSET;
stream->fifo_offset = SP_PB_FIFO_ADDR_OFFSET;
} else {
irq_bit = BIT(I2S_RX_THRESHOLD(rsrc->offset));
stream->pte_offset = ACP_SRAM_SP_CP_PTE_OFFSET;
stream->fifo_offset = SP_CAPT_FIFO_ADDR_OFFSET;
}
break;
case I2S_BT_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
irq_bit = BIT(BT_TX_THRESHOLD(rsrc->offset));
stream->pte_offset = ACP_SRAM_BT_PB_PTE_OFFSET;
stream->fifo_offset = BT_PB_FIFO_ADDR_OFFSET;
} else {
irq_bit = BIT(BT_RX_THRESHOLD(rsrc->offset));
stream->pte_offset = ACP_SRAM_BT_CP_PTE_OFFSET;
stream->fifo_offset = BT_CAPT_FIFO_ADDR_OFFSET;
}
break;
case I2S_HS_INSTANCE:
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
irq_bit = BIT(HS_TX_THRESHOLD(rsrc->offset));
stream->pte_offset = ACP_SRAM_HS_PB_PTE_OFFSET;
stream->fifo_offset = HS_PB_FIFO_ADDR_OFFSET;
} else {
irq_bit = BIT(HS_RX_THRESHOLD(rsrc->offset));
stream->pte_offset = ACP_SRAM_HS_CP_PTE_OFFSET;
stream->fifo_offset = HS_CAPT_FIFO_ADDR_OFFSET;
}
break;
default:
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
return -EINVAL;
}
/* Save runtime dai configuration in stream */
stream->id = dai->driver->id + dir;
stream->dai_id = dai->driver->id;
stream->irq_bit = irq_bit;
stream->dir = substream->stream;
return 0;
}
static int acp_i2s_probe(struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_resource *rsrc = adata->rsrc;
unsigned int val;
if (!adata->acp_base) {
dev_err(dev, "I2S base is NULL\n");
return -EINVAL;
}
val = readl(adata->acp_base + rsrc->i2s_pin_cfg_offset);
if (val != rsrc->i2s_mode) {
dev_err(dev, "I2S Mode not supported val %x\n", val);
return -EINVAL;
}
return 0;
}
const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops = {
.probe = acp_i2s_probe,
.startup = acp_i2s_startup,
.hw_params = acp_i2s_hwparams,
.prepare = acp_i2s_prepare,
.trigger = acp_i2s_trigger,
.set_fmt = acp_i2s_set_fmt,
.set_tdm_slot = acp_i2s_set_tdm_slot,
};
EXPORT_SYMBOL_NS_GPL(asoc_acp_cpu_dai_ops, SND_SOC_ACP_COMMON);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS(DRV_NAME);
| linux-master | sound/soc/amd/acp/acp-i2s.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
// Vijendar Mukunda <[email protected]>
//
/*
* Machine Driver Interface for ACP HW block
*/
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include <sound/soc.h>
#include <linux/input.h>
#include <linux/module.h>
#include "../../codecs/rt5682.h"
#include "../../codecs/rt1019.h"
#include "../../codecs/rt5682s.h"
#include "../../codecs/nau8825.h"
#include "../../codecs/nau8821.h"
#include "acp-mach.h"
#define PCO_PLAT_CLK 48000000
#define RT5682_PLL_FREQ (48000 * 512)
#define DUAL_CHANNEL 2
#define FOUR_CHANNEL 4
#define NAU8821_CODEC_DAI "nau8821-hifi"
#define NAU8821_BCLK 1536000
#define NAU8821_FREQ_OUT 12288000
#define MAX98388_CODEC_DAI "max98388-aif1"
#define TDM_MODE_ENABLE 1
const struct dmi_system_id acp_quirk_table[] = {
{
/* Google skyrim proto-0 */
.matches = {
DMI_EXACT_MATCH(DMI_PRODUCT_FAMILY, "Google_Skyrim"),
},
.driver_data = (void *)TDM_MODE_ENABLE,
},
{}
};
EXPORT_SYMBOL_GPL(acp_quirk_table);
static const unsigned int channels[] = {
DUAL_CHANNEL,
};
static const unsigned int rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
static int acp_clk_enable(struct acp_card_drvdata *drvdata,
unsigned int srate, unsigned int bclk_ratio)
{
clk_set_rate(drvdata->wclk, srate);
clk_set_rate(drvdata->bclk, srate * bclk_ratio);
return clk_prepare_enable(drvdata->wclk);
}
/* Declare RT5682 codec components */
SND_SOC_DAILINK_DEF(rt5682,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5682:00", "rt5682-aif1")));
static struct snd_soc_jack rt5682_jack;
static struct snd_soc_jack_pin rt5682_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_kcontrol_new rt5682_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget rt5682_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route rt5682_map[] = {
{ "Headphone Jack", NULL, "HPOL" },
{ "Headphone Jack", NULL, "HPOR" },
{ "IN1P", NULL, "Headset Mic" },
};
/* Define card ops for RT5682 CODEC */
static int acp_card_rt5682_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
int ret;
dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name);
if (drvdata->hs_codec_id != RT5682)
return -EINVAL;
drvdata->wclk = clk_get(component->dev, "rt5682-dai-wclk");
drvdata->bclk = clk_get(component->dev, "rt5682-dai-bclk");
ret = snd_soc_dapm_new_controls(&card->dapm, rt5682_widgets,
ARRAY_SIZE(rt5682_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, rt5682_controls,
ARRAY_SIZE(rt5682_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&rt5682_jack,
rt5682_jack_pins,
ARRAY_SIZE(rt5682_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(rt5682_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(rt5682_jack.jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(rt5682_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(rt5682_jack.jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ret = snd_soc_component_set_jack(component, &rt5682_jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return snd_soc_dapm_add_routes(&rtd->card->dapm, rt5682_map, ARRAY_SIZE(rt5682_map));
}
static int acp_card_hs_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
unsigned int fmt;
if (drvdata->tdm_mode)
fmt = SND_SOC_DAIFMT_DSP_A;
else
fmt = SND_SOC_DAIFMT_I2S;
if (drvdata->soc_mclk)
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(codec_dai, fmt);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return ret;
}
static void acp_card_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
if (!drvdata->soc_mclk)
clk_disable_unprepare(drvdata->wclk);
}
static int acp_card_rt5682_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
unsigned int fmt, srate, ch, format;
srate = params_rate(params);
ch = params_channels(params);
format = params_physical_width(params);
if (drvdata->tdm_mode)
fmt = SND_SOC_DAIFMT_DSP_A;
else
fmt = SND_SOC_DAIFMT_I2S;
if (drvdata->soc_mclk)
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_fmt(codec_dai, fmt);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
if (drvdata->tdm_mode) {
/**
* As codec supports slot 0 and slot 1 for playback and capture.
*/
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 8, 16);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "set TDM slot err: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x3, 0x3, 8, 16);
if (ret < 0) {
dev_warn(rtd->dev, "set TDM slot err:%d\n", ret);
return ret;
}
}
ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL2, RT5682_PLL2_S_MCLK,
PCO_PLAT_CLK, RT5682_PLL_FREQ);
if (ret < 0) {
dev_err(rtd->dev, "Failed to set codec PLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682_SCLK_S_PLL2,
RT5682_PLL_FREQ, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "Failed to set codec SYSCLK: %d\n", ret);
return ret;
}
/* Set tdm/i2s1 master bclk ratio */
ret = snd_soc_dai_set_bclk_ratio(codec_dai, ch * format);
if (ret < 0) {
dev_err(rtd->dev, "Failed to set rt5682 tdm bclk ratio: %d\n", ret);
return ret;
}
if (!drvdata->soc_mclk) {
ret = acp_clk_enable(drvdata, srate, ch * format);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to enable HS clk: %d\n", ret);
return ret;
}
}
return 0;
}
static const struct snd_soc_ops acp_card_rt5682_ops = {
.startup = acp_card_hs_startup,
.shutdown = acp_card_shutdown,
.hw_params = acp_card_rt5682_hw_params,
};
/* Define RT5682S CODEC component*/
SND_SOC_DAILINK_DEF(rt5682s,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-RTL5682:00", "rt5682s-aif1")));
static struct snd_soc_jack rt5682s_jack;
static struct snd_soc_jack_pin rt5682s_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_kcontrol_new rt5682s_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget rt5682s_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route rt5682s_map[] = {
{ "Headphone Jack", NULL, "HPOL" },
{ "Headphone Jack", NULL, "HPOR" },
{ "IN1P", NULL, "Headset Mic" },
};
static int acp_card_rt5682s_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
int ret;
dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name);
if (drvdata->hs_codec_id != RT5682S)
return -EINVAL;
if (!drvdata->soc_mclk) {
drvdata->wclk = clk_get(component->dev, "rt5682-dai-wclk");
drvdata->bclk = clk_get(component->dev, "rt5682-dai-bclk");
}
ret = snd_soc_dapm_new_controls(&card->dapm, rt5682s_widgets,
ARRAY_SIZE(rt5682s_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, rt5682s_controls,
ARRAY_SIZE(rt5682s_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&rt5682s_jack,
rt5682s_jack_pins,
ARRAY_SIZE(rt5682s_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(rt5682s_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(rt5682s_jack.jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(rt5682s_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(rt5682s_jack.jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ret = snd_soc_component_set_jack(component, &rt5682s_jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return snd_soc_dapm_add_routes(&rtd->card->dapm, rt5682s_map, ARRAY_SIZE(rt5682s_map));
}
static int acp_card_rt5682s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
unsigned int fmt, srate, ch, format;
srate = params_rate(params);
ch = params_channels(params);
format = params_physical_width(params);
if (drvdata->tdm_mode)
fmt = SND_SOC_DAIFMT_DSP_A;
else
fmt = SND_SOC_DAIFMT_I2S;
if (drvdata->soc_mclk)
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_fmt(codec_dai, fmt);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
if (drvdata->tdm_mode) {
/**
* As codec supports slot 0 and slot 1 for playback and capture.
*/
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 8, 16);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "set TDM slot err: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x3, 0x3, 8, 16);
if (ret < 0) {
dev_warn(rtd->dev, "set TDM slot err:%d\n", ret);
return ret;
}
}
ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
PCO_PLAT_CLK, RT5682_PLL_FREQ);
if (ret < 0) {
dev_err(rtd->dev, "Failed to set codec PLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL2,
RT5682_PLL_FREQ, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "Failed to set codec SYSCLK: %d\n", ret);
return ret;
}
/* Set tdm/i2s1 master bclk ratio */
ret = snd_soc_dai_set_bclk_ratio(codec_dai, ch * format);
if (ret < 0) {
dev_err(rtd->dev, "Failed to set rt5682 tdm bclk ratio: %d\n", ret);
return ret;
}
clk_set_rate(drvdata->wclk, srate);
clk_set_rate(drvdata->bclk, srate * ch * format);
return 0;
}
static const struct snd_soc_ops acp_card_rt5682s_ops = {
.startup = acp_card_hs_startup,
.hw_params = acp_card_rt5682s_hw_params,
};
static const unsigned int dmic_channels[] = {
DUAL_CHANNEL, FOUR_CHANNEL,
};
static const struct snd_pcm_hw_constraint_list dmic_constraints_channels = {
.count = ARRAY_SIZE(dmic_channels),
.list = dmic_channels,
.mask = 0,
};
static int acp_card_dmic_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&dmic_constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return 0;
}
static const struct snd_soc_ops acp_card_dmic_ops = {
.startup = acp_card_dmic_startup,
};
/* Declare RT1019 codec components */
SND_SOC_DAILINK_DEF(rt1019,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC1019:00", "rt1019-aif"),
COMP_CODEC("i2c-10EC1019:01", "rt1019-aif")));
static const struct snd_kcontrol_new rt1019_controls[] = {
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
};
static const struct snd_soc_dapm_widget rt1019_widgets[] = {
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
};
static const struct snd_soc_dapm_route rt1019_map_lr[] = {
{ "Left Spk", NULL, "Left SPO" },
{ "Right Spk", NULL, "Right SPO" },
};
static struct snd_soc_codec_conf rt1019_conf[] = {
{
.dlc = COMP_CODEC_CONF("i2c-10EC1019:01"),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF("i2c-10EC1019:00"),
.name_prefix = "Right",
},
};
static int acp_card_rt1019_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
int ret;
if (drvdata->amp_codec_id != RT1019)
return -EINVAL;
ret = snd_soc_dapm_new_controls(&card->dapm, rt1019_widgets,
ARRAY_SIZE(rt1019_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, rt1019_controls,
ARRAY_SIZE(rt1019_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
return snd_soc_dapm_add_routes(&rtd->card->dapm, rt1019_map_lr,
ARRAY_SIZE(rt1019_map_lr));
}
static int acp_card_rt1019_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int i, ret = 0;
unsigned int fmt, srate, ch, format;
srate = params_rate(params);
ch = params_channels(params);
format = params_physical_width(params);
if (drvdata->amp_codec_id != RT1019)
return -EINVAL;
if (drvdata->tdm_mode)
fmt = SND_SOC_DAIFMT_DSP_A;
else
fmt = SND_SOC_DAIFMT_I2S;
if (drvdata->soc_mclk)
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
if (drvdata->tdm_mode) {
/**
* As codec supports slot 2 and slot 3 for playback.
*/
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xC, 0, 8, 16);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "set TDM slot err: %d\n", ret);
return ret;
}
}
for_each_rtd_codec_dais(rtd, i, codec_dai) {
if (strcmp(codec_dai->name, "rt1019-aif"))
continue;
if (drvdata->tdm_mode)
ret = snd_soc_dai_set_pll(codec_dai, 0, RT1019_PLL_S_BCLK,
TDM_CHANNELS * format * srate, 256 * srate);
else
ret = snd_soc_dai_set_pll(codec_dai, 0, RT1019_PLL_S_BCLK,
ch * format * srate, 256 * srate);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(codec_dai, RT1019_SCLK_S_PLL,
256 * srate, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
if (drvdata->tdm_mode) {
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_NB_NF);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
/**
* As codec supports slot 2 for left channel playback.
*/
if (!strcmp(codec_dai->component->name, "i2c-10EC1019:00")) {
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x4, 0x4, 8, 16);
if (ret < 0)
break;
}
/**
* As codec supports slot 3 for right channel playback.
*/
if (!strcmp(codec_dai->component->name, "i2c-10EC1019:01")) {
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x8, 0x8, 8, 16);
if (ret < 0)
break;
}
}
}
if (!drvdata->soc_mclk) {
ret = acp_clk_enable(drvdata, srate, ch * format);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to enable AMP clk: %d\n", ret);
return ret;
}
}
return 0;
}
static int acp_card_amp_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
return 0;
}
static const struct snd_soc_ops acp_card_rt1019_ops = {
.startup = acp_card_amp_startup,
.shutdown = acp_card_shutdown,
.hw_params = acp_card_rt1019_hw_params,
};
/* Declare Maxim codec components */
SND_SOC_DAILINK_DEF(max98360a,
DAILINK_COMP_ARRAY(COMP_CODEC("MX98360A:00", "HiFi")));
static const struct snd_kcontrol_new max98360a_controls[] = {
SOC_DAPM_PIN_SWITCH("Spk"),
};
static const struct snd_soc_dapm_widget max98360a_widgets[] = {
SND_SOC_DAPM_SPK("Spk", NULL),
};
static const struct snd_soc_dapm_route max98360a_map[] = {
{"Spk", NULL, "Speaker"},
};
static int acp_card_maxim_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
int ret;
if (drvdata->amp_codec_id != MAX98360A)
return -EINVAL;
ret = snd_soc_dapm_new_controls(&card->dapm, max98360a_widgets,
ARRAY_SIZE(max98360a_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, max98360a_controls,
ARRAY_SIZE(max98360a_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
return snd_soc_dapm_add_routes(&rtd->card->dapm, max98360a_map,
ARRAY_SIZE(max98360a_map));
}
static int acp_card_maxim_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
unsigned int fmt, srate, ch, format;
int ret;
srate = params_rate(params);
ch = params_channels(params);
format = params_physical_width(params);
if (drvdata->tdm_mode)
fmt = SND_SOC_DAIFMT_DSP_A;
else
fmt = SND_SOC_DAIFMT_I2S;
if (drvdata->soc_mclk)
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
if (drvdata->tdm_mode) {
/**
* As codec supports slot 2 and slot 3 for playback.
*/
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xC, 0, 8, 16);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "set TDM slot err: %d\n", ret);
return ret;
}
}
if (!drvdata->soc_mclk) {
ret = acp_clk_enable(drvdata, srate, ch * format);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to enable AMP clk: %d\n", ret);
return ret;
}
}
return 0;
}
static const struct snd_soc_ops acp_card_maxim_ops = {
.startup = acp_card_amp_startup,
.shutdown = acp_card_shutdown,
.hw_params = acp_card_maxim_hw_params,
};
SND_SOC_DAILINK_DEF(max98388,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-ADS8388:00", "max98388-aif1"),
COMP_CODEC("i2c-ADS8388:01", "max98388-aif1")));
static const struct snd_kcontrol_new max98388_controls[] = {
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
};
static const struct snd_soc_dapm_widget max98388_widgets[] = {
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
};
static const struct snd_soc_dapm_route max98388_map[] = {
{ "Left Spk", NULL, "Left BE_OUT" },
{ "Right Spk", NULL, "Right BE_OUT" },
};
static struct snd_soc_codec_conf max98388_conf[] = {
{
.dlc = COMP_CODEC_CONF("i2c-ADS8388:00"),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF("i2c-ADS8388:01"),
.name_prefix = "Right",
},
};
static const unsigned int max98388_format[] = {16};
static struct snd_pcm_hw_constraint_list constraints_sample_bits_max = {
.list = max98388_format,
.count = ARRAY_SIZE(max98388_format),
};
static int acp_card_max98388_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
&constraints_sample_bits_max);
return 0;
}
static int acp_card_max98388_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
int ret;
if (drvdata->amp_codec_id != MAX98388)
return -EINVAL;
ret = snd_soc_dapm_new_controls(&card->dapm, max98388_widgets,
ARRAY_SIZE(max98388_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
/* Don't need to add routes if widget addition failed */
return ret;
}
ret = snd_soc_add_card_controls(card, max98388_controls,
ARRAY_SIZE(max98388_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
return snd_soc_dapm_add_routes(&rtd->card->dapm, max98388_map,
ARRAY_SIZE(max98388_map));
}
static int acp_max98388_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai =
snd_soc_card_get_codec_dai(card,
MAX98388_CODEC_DAI);
int ret;
ret = snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF);
if (ret < 0)
return ret;
return ret;
}
static const struct snd_soc_ops acp_max98388_ops = {
.startup = acp_card_max98388_startup,
.hw_params = acp_max98388_hw_params,
};
/* Declare nau8825 codec components */
SND_SOC_DAILINK_DEF(nau8825,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10508825:00", "nau8825-hifi")));
static struct snd_soc_jack nau8825_jack;
static struct snd_soc_jack_pin nau8825_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_kcontrol_new nau8825_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget nau8825_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route nau8825_map[] = {
{ "Headphone Jack", NULL, "HPOL" },
{ "Headphone Jack", NULL, "HPOR" },
};
static int acp_card_nau8825_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
int ret;
dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name);
if (drvdata->hs_codec_id != NAU8825)
return -EINVAL;
ret = snd_soc_dapm_new_controls(&card->dapm, nau8825_widgets,
ARRAY_SIZE(nau8825_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, nau8825_controls,
ARRAY_SIZE(nau8825_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&nau8825_jack,
nau8825_jack_pins,
ARRAY_SIZE(nau8825_jack_pins));
if (ret) {
dev_err(card->dev, "HP jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(nau8825_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(nau8825_jack.jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(nau8825_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(nau8825_jack.jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ret = snd_soc_component_set_jack(component, &nau8825_jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return snd_soc_dapm_add_routes(&rtd->card->dapm, nau8825_map, ARRAY_SIZE(nau8825_map));
}
static int acp_nau8825_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
unsigned int fmt;
ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_FS,
(48000 * 256), SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n", ret);
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, params_rate(params),
params_rate(params) * 256);
if (ret < 0) {
dev_err(rtd->dev, "can't set FLL: %d\n", ret);
return ret;
}
if (drvdata->tdm_mode)
fmt = SND_SOC_DAIFMT_DSP_A;
else
fmt = SND_SOC_DAIFMT_I2S;
if (drvdata->soc_mclk)
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_fmt(codec_dai, fmt);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
if (drvdata->tdm_mode) {
/**
* As codec supports slot 4 and slot 5 for playback and slot 6 for capture.
*/
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x30, 0xC0, 8, 16);
if (ret && ret != -ENOTSUPP) {
dev_err(rtd->dev, "set TDM slot err: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x40, 0x30, 8, 16);
if (ret < 0) {
dev_warn(rtd->dev, "set TDM slot err:%d\n", ret);
return ret;
}
}
return ret;
}
static int acp_nau8825_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
runtime->hw.channels_max = 2;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
return 0;
}
static const struct snd_soc_ops acp_card_nau8825_ops = {
.startup = acp_nau8825_startup,
.hw_params = acp_nau8825_hw_params,
};
static int platform_clock_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct snd_soc_card *card = dapm->card;
struct snd_soc_dai *codec_dai;
int ret = 0;
codec_dai = snd_soc_card_get_codec_dai(card, NAU8821_CODEC_DAI);
if (!codec_dai) {
dev_err(card->dev, "Codec dai not found\n");
return -EIO;
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
ret = snd_soc_dai_set_sysclk(codec_dai, NAU8821_CLK_INTERNAL,
0, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "set sysclk err = %d\n", ret);
return -EIO;
}
} else {
ret = snd_soc_dai_set_sysclk(codec_dai, NAU8821_CLK_FLL_BLK, 0,
SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(codec_dai->dev, "can't set FS clock %d\n", ret);
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, NAU8821_BCLK,
NAU8821_FREQ_OUT);
if (ret < 0)
dev_err(codec_dai->dev, "can't set FLL: %d\n", ret);
}
return ret;
}
static struct snd_soc_jack nau8821_jack;
static struct snd_soc_jack_pin nau8821_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_kcontrol_new nau8821_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget nau8821_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
platform_clock_control, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route nau8821_audio_route[] = {
/* HP jack connectors - unknown if we have jack detection */
{ "Headphone Jack", NULL, "HPOL" },
{ "Headphone Jack", NULL, "HPOR" },
{ "MICL", NULL, "Headset Mic" },
{ "MICR", NULL, "Headset Mic" },
{ "DMIC", NULL, "Int Mic" },
{ "Headphone Jack", NULL, "Platform Clock" },
{ "Headset Mic", NULL, "Platform Clock" },
{ "Int Mic", NULL, "Platform Clock" },
};
static const unsigned int nau8821_format[] = {16};
static struct snd_pcm_hw_constraint_list constraints_sample_bits = {
.list = nau8821_format,
.count = ARRAY_SIZE(nau8821_format),
};
static int acp_8821_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
int ret;
dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name);
ret = snd_soc_dapm_new_controls(&card->dapm, nau8821_widgets,
ARRAY_SIZE(nau8821_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add widget dapm controls, ret %d\n", ret);
// Don't need to add routes if widget addition failed
return ret;
}
ret = snd_soc_add_card_controls(card, nau8821_controls,
ARRAY_SIZE(nau8821_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&nau8821_jack,
nau8821_jack_pins,
ARRAY_SIZE(nau8821_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed %d\n", ret);
return ret;
}
snd_jack_set_key(nau8821_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(nau8821_jack.jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(nau8821_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(nau8821_jack.jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
nau8821_enable_jack_detect(component, &nau8821_jack);
return snd_soc_dapm_add_routes(&rtd->card->dapm, nau8821_audio_route,
ARRAY_SIZE(nau8821_audio_route));
}
static int acp_8821_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
runtime->hw.channels_max = DUAL_CHANNEL;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
&constraints_sample_bits);
return 0;
}
static int acp_nau8821_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct acp_card_drvdata *drvdata = card->drvdata;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
unsigned int fmt;
if (drvdata->soc_mclk)
fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBC_CFC;
else
fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBP_CFP;
ret = snd_soc_dai_set_fmt(codec_dai, fmt);
if (ret < 0) {
dev_err(rtd->card->dev, "Failed to set dai fmt: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, NAU8821_CLK_FLL_BLK, 0,
SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(card->dev, "can't set FS clock %d\n", ret);
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, snd_soc_params_to_bclk(params),
params_rate(params) * 256);
if (ret < 0)
dev_err(card->dev, "can't set FLL: %d\n", ret);
return ret;
}
static const struct snd_soc_ops acp_8821_ops = {
.startup = acp_8821_startup,
.hw_params = acp_nau8821_hw_params,
};
SND_SOC_DAILINK_DEF(nau8821,
DAILINK_COMP_ARRAY(COMP_CODEC("i2c-NVTN2020:00",
"nau8821-hifi")));
/* Declare DMIC codec components */
SND_SOC_DAILINK_DEF(dmic_codec,
DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec", "dmic-hifi")));
/* Declare ACP CPU components */
static struct snd_soc_dai_link_component platform_component[] = {
{
.name = "acp_asoc_renoir.0",
}
};
static struct snd_soc_dai_link_component platform_rmb_component[] = {
{
.name = "acp_asoc_rembrandt.0",
}
};
static struct snd_soc_dai_link_component sof_component[] = {
{
.name = "0000:04:00.5",
}
};
SND_SOC_DAILINK_DEF(i2s_sp,
DAILINK_COMP_ARRAY(COMP_CPU("acp-i2s-sp")));
SND_SOC_DAILINK_DEF(i2s_hs,
DAILINK_COMP_ARRAY(COMP_CPU("acp-i2s-hs")));
SND_SOC_DAILINK_DEF(sof_sp,
DAILINK_COMP_ARRAY(COMP_CPU("acp-sof-sp")));
SND_SOC_DAILINK_DEF(sof_sp_virtual,
DAILINK_COMP_ARRAY(COMP_CPU("acp-sof-sp-virtual")));
SND_SOC_DAILINK_DEF(sof_hs,
DAILINK_COMP_ARRAY(COMP_CPU("acp-sof-hs")));
SND_SOC_DAILINK_DEF(sof_hs_virtual,
DAILINK_COMP_ARRAY(COMP_CPU("acp-sof-hs-virtual")));
SND_SOC_DAILINK_DEF(sof_dmic,
DAILINK_COMP_ARRAY(COMP_CPU("acp-sof-dmic")));
SND_SOC_DAILINK_DEF(pdm_dmic,
DAILINK_COMP_ARRAY(COMP_CPU("acp-pdm-dmic")));
static int acp_rtk_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_component *component = dapm->component;
struct acp_card_drvdata *drvdata = card->drvdata;
int ret = 0;
if (!component)
return 0;
if (strncmp(component->name, "i2c-RTL5682", 11) &&
strncmp(component->name, "i2c-10EC1019", 12))
return 0;
/*
* For Realtek's codec and amplifier components,
* the lrck and bclk must be enabled brfore their all dapms be powered on,
* and must be disabled after their all dapms be powered down
* to avoid any pop.
*/
switch (level) {
case SND_SOC_BIAS_STANDBY:
if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
/* Increase bclk's enable_count */
ret = clk_prepare_enable(drvdata->bclk);
if (ret < 0)
dev_err(component->dev, "Failed to enable bclk %d\n", ret);
} else {
/*
* Decrease bclk's enable_count.
* While the enable_count is 0, the bclk would be closed.
*/
clk_disable_unprepare(drvdata->bclk);
}
break;
default:
break;
}
return ret;
}
int acp_sofdsp_dai_links_create(struct snd_soc_card *card)
{
struct snd_soc_dai_link *links;
struct device *dev = card->dev;
struct acp_card_drvdata *drv_data = card->drvdata;
int i = 0, num_links = 0;
if (drv_data->hs_cpu_id)
num_links++;
if (drv_data->amp_cpu_id)
num_links++;
if (drv_data->dmic_cpu_id)
num_links++;
links = devm_kcalloc(dev, num_links, sizeof(struct snd_soc_dai_link), GFP_KERNEL);
if (!links)
return -ENOMEM;
if (drv_data->hs_cpu_id == I2S_SP) {
links[i].name = "acp-headset-codec";
links[i].id = HEADSET_BE_ID;
links[i].cpus = sof_sp;
links[i].num_cpus = ARRAY_SIZE(sof_sp);
links[i].platforms = sof_component;
links[i].num_platforms = ARRAY_SIZE(sof_component);
links[i].dpcm_playback = 1;
links[i].dpcm_capture = 1;
links[i].nonatomic = true;
links[i].no_pcm = 1;
if (!drv_data->hs_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->hs_codec_id == RT5682) {
links[i].codecs = rt5682;
links[i].num_codecs = ARRAY_SIZE(rt5682);
links[i].init = acp_card_rt5682_init;
links[i].ops = &acp_card_rt5682_ops;
}
if (drv_data->hs_codec_id == RT5682S) {
links[i].codecs = rt5682s;
links[i].num_codecs = ARRAY_SIZE(rt5682s);
links[i].init = acp_card_rt5682s_init;
links[i].ops = &acp_card_rt5682s_ops;
}
if (drv_data->hs_codec_id == NAU8821) {
links[i].codecs = nau8821;
links[i].num_codecs = ARRAY_SIZE(nau8821);
links[i].init = acp_8821_init;
links[i].ops = &acp_8821_ops;
}
i++;
}
if (drv_data->hs_cpu_id == I2S_HS) {
links[i].name = "acp-headset-codec";
links[i].id = HEADSET_BE_ID;
links[i].cpus = sof_hs;
links[i].num_cpus = ARRAY_SIZE(sof_hs);
links[i].platforms = sof_component;
links[i].num_platforms = ARRAY_SIZE(sof_component);
links[i].dpcm_playback = 1;
links[i].dpcm_capture = 1;
links[i].nonatomic = true;
links[i].no_pcm = 1;
if (!drv_data->hs_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->hs_codec_id == NAU8825) {
links[i].codecs = nau8825;
links[i].num_codecs = ARRAY_SIZE(nau8825);
links[i].init = acp_card_nau8825_init;
links[i].ops = &acp_card_nau8825_ops;
}
if (drv_data->hs_codec_id == RT5682S) {
links[i].codecs = rt5682s;
links[i].num_codecs = ARRAY_SIZE(rt5682s);
links[i].init = acp_card_rt5682s_init;
links[i].ops = &acp_card_rt5682s_ops;
}
i++;
}
if (drv_data->amp_cpu_id == I2S_SP) {
links[i].name = "acp-amp-codec";
links[i].id = AMP_BE_ID;
links[i].cpus = sof_sp_virtual;
links[i].num_cpus = ARRAY_SIZE(sof_sp_virtual);
links[i].platforms = sof_component;
links[i].num_platforms = ARRAY_SIZE(sof_component);
links[i].dpcm_playback = 1;
links[i].nonatomic = true;
links[i].no_pcm = 1;
if (!drv_data->amp_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->amp_codec_id == RT1019) {
links[i].codecs = rt1019;
links[i].num_codecs = ARRAY_SIZE(rt1019);
links[i].ops = &acp_card_rt1019_ops;
links[i].init = acp_card_rt1019_init;
card->codec_conf = rt1019_conf;
card->num_configs = ARRAY_SIZE(rt1019_conf);
}
if (drv_data->amp_codec_id == MAX98360A) {
links[i].codecs = max98360a;
links[i].num_codecs = ARRAY_SIZE(max98360a);
links[i].ops = &acp_card_maxim_ops;
links[i].init = acp_card_maxim_init;
}
i++;
}
if (drv_data->amp_cpu_id == I2S_HS) {
links[i].name = "acp-amp-codec";
links[i].id = AMP_BE_ID;
links[i].cpus = sof_hs_virtual;
links[i].num_cpus = ARRAY_SIZE(sof_hs_virtual);
links[i].platforms = sof_component;
links[i].num_platforms = ARRAY_SIZE(sof_component);
links[i].dpcm_playback = 1;
links[i].nonatomic = true;
links[i].no_pcm = 1;
if (!drv_data->amp_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->amp_codec_id == MAX98360A) {
links[i].codecs = max98360a;
links[i].num_codecs = ARRAY_SIZE(max98360a);
links[i].ops = &acp_card_maxim_ops;
links[i].init = acp_card_maxim_init;
}
if (drv_data->amp_codec_id == MAX98388) {
links[i].codecs = max98388;
links[i].num_codecs = ARRAY_SIZE(max98388);
links[i].ops = &acp_max98388_ops;
links[i].init = acp_card_max98388_init;
card->codec_conf = max98388_conf;
card->num_configs = ARRAY_SIZE(max98388_conf);
}
if (drv_data->amp_codec_id == RT1019) {
links[i].codecs = rt1019;
links[i].num_codecs = ARRAY_SIZE(rt1019);
links[i].ops = &acp_card_rt1019_ops;
links[i].init = acp_card_rt1019_init;
card->codec_conf = rt1019_conf;
card->num_configs = ARRAY_SIZE(rt1019_conf);
}
i++;
}
if (drv_data->dmic_cpu_id == DMIC) {
links[i].name = "acp-dmic-codec";
links[i].id = DMIC_BE_ID;
links[i].codecs = dmic_codec;
links[i].num_codecs = ARRAY_SIZE(dmic_codec);
links[i].cpus = sof_dmic;
links[i].num_cpus = ARRAY_SIZE(sof_dmic);
links[i].platforms = sof_component;
links[i].num_platforms = ARRAY_SIZE(sof_component);
links[i].dpcm_capture = 1;
links[i].nonatomic = true;
links[i].no_pcm = 1;
}
card->dai_link = links;
card->num_links = num_links;
card->set_bias_level = acp_rtk_set_bias_level;
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_sofdsp_dai_links_create, SND_SOC_AMD_MACH);
int acp_legacy_dai_links_create(struct snd_soc_card *card)
{
struct snd_soc_dai_link *links;
struct device *dev = card->dev;
struct acp_card_drvdata *drv_data = card->drvdata;
int i = 0, num_links = 0;
if (drv_data->hs_cpu_id)
num_links++;
if (drv_data->amp_cpu_id)
num_links++;
if (drv_data->dmic_cpu_id)
num_links++;
links = devm_kcalloc(dev, num_links, sizeof(struct snd_soc_dai_link), GFP_KERNEL);
if (!links)
return -ENOMEM;
if (drv_data->hs_cpu_id == I2S_SP) {
links[i].name = "acp-headset-codec";
links[i].id = HEADSET_BE_ID;
links[i].cpus = i2s_sp;
links[i].num_cpus = ARRAY_SIZE(i2s_sp);
links[i].platforms = platform_component;
links[i].num_platforms = ARRAY_SIZE(platform_component);
links[i].dpcm_playback = 1;
links[i].dpcm_capture = 1;
if (!drv_data->hs_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->hs_codec_id == RT5682) {
links[i].codecs = rt5682;
links[i].num_codecs = ARRAY_SIZE(rt5682);
links[i].init = acp_card_rt5682_init;
links[i].ops = &acp_card_rt5682_ops;
}
if (drv_data->hs_codec_id == RT5682S) {
links[i].codecs = rt5682s;
links[i].num_codecs = ARRAY_SIZE(rt5682s);
links[i].init = acp_card_rt5682s_init;
links[i].ops = &acp_card_rt5682s_ops;
}
i++;
}
if (drv_data->hs_cpu_id == I2S_HS) {
links[i].name = "acp-headset-codec";
links[i].id = HEADSET_BE_ID;
links[i].cpus = i2s_hs;
links[i].num_cpus = ARRAY_SIZE(i2s_hs);
if (drv_data->platform == REMBRANDT) {
links[i].platforms = platform_rmb_component;
links[i].num_platforms = ARRAY_SIZE(platform_rmb_component);
} else {
links[i].platforms = platform_component;
links[i].num_platforms = ARRAY_SIZE(platform_component);
}
links[i].dpcm_playback = 1;
links[i].dpcm_capture = 1;
if (!drv_data->hs_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->hs_codec_id == NAU8825) {
links[i].codecs = nau8825;
links[i].num_codecs = ARRAY_SIZE(nau8825);
links[i].init = acp_card_nau8825_init;
links[i].ops = &acp_card_nau8825_ops;
}
if (drv_data->hs_codec_id == RT5682S) {
links[i].codecs = rt5682s;
links[i].num_codecs = ARRAY_SIZE(rt5682s);
links[i].init = acp_card_rt5682s_init;
links[i].ops = &acp_card_rt5682s_ops;
}
i++;
}
if (drv_data->amp_cpu_id == I2S_SP) {
links[i].name = "acp-amp-codec";
links[i].id = AMP_BE_ID;
links[i].cpus = i2s_sp;
links[i].num_cpus = ARRAY_SIZE(i2s_sp);
links[i].platforms = platform_component;
links[i].num_platforms = ARRAY_SIZE(platform_component);
links[i].dpcm_playback = 1;
if (!drv_data->amp_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->amp_codec_id == RT1019) {
links[i].codecs = rt1019;
links[i].num_codecs = ARRAY_SIZE(rt1019);
links[i].ops = &acp_card_rt1019_ops;
links[i].init = acp_card_rt1019_init;
card->codec_conf = rt1019_conf;
card->num_configs = ARRAY_SIZE(rt1019_conf);
}
if (drv_data->amp_codec_id == MAX98360A) {
links[i].codecs = max98360a;
links[i].num_codecs = ARRAY_SIZE(max98360a);
links[i].ops = &acp_card_maxim_ops;
links[i].init = acp_card_maxim_init;
}
i++;
}
if (drv_data->amp_cpu_id == I2S_HS) {
links[i].name = "acp-amp-codec";
links[i].id = AMP_BE_ID;
links[i].cpus = i2s_hs;
links[i].num_cpus = ARRAY_SIZE(i2s_hs);
if (drv_data->platform == REMBRANDT) {
links[i].platforms = platform_rmb_component;
links[i].num_platforms = ARRAY_SIZE(platform_rmb_component);
} else {
links[i].platforms = platform_component;
links[i].num_platforms = ARRAY_SIZE(platform_component);
}
links[i].dpcm_playback = 1;
if (!drv_data->amp_codec_id) {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
if (drv_data->amp_codec_id == MAX98360A) {
links[i].codecs = max98360a;
links[i].num_codecs = ARRAY_SIZE(max98360a);
links[i].ops = &acp_card_maxim_ops;
links[i].init = acp_card_maxim_init;
}
if (drv_data->amp_codec_id == RT1019) {
links[i].codecs = rt1019;
links[i].num_codecs = ARRAY_SIZE(rt1019);
links[i].ops = &acp_card_rt1019_ops;
links[i].init = acp_card_rt1019_init;
card->codec_conf = rt1019_conf;
card->num_configs = ARRAY_SIZE(rt1019_conf);
}
i++;
}
if (drv_data->dmic_cpu_id == DMIC) {
links[i].name = "acp-dmic-codec";
links[i].id = DMIC_BE_ID;
if (drv_data->dmic_codec_id == DMIC) {
links[i].codecs = dmic_codec;
links[i].num_codecs = ARRAY_SIZE(dmic_codec);
} else {
/* Use dummy codec if codec id not specified */
links[i].codecs = &asoc_dummy_dlc;
links[i].num_codecs = 1;
}
links[i].cpus = pdm_dmic;
links[i].num_cpus = ARRAY_SIZE(pdm_dmic);
if (drv_data->platform == REMBRANDT) {
links[i].platforms = platform_rmb_component;
links[i].num_platforms = ARRAY_SIZE(platform_rmb_component);
} else {
links[i].platforms = platform_component;
links[i].num_platforms = ARRAY_SIZE(platform_component);
}
links[i].ops = &acp_card_dmic_ops;
links[i].dpcm_capture = 1;
}
card->dai_link = links;
card->num_links = num_links;
card->set_bias_level = acp_rtk_set_bias_level;
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_legacy_dai_links_create, SND_SOC_AMD_MACH);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp/acp-mach-common.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
//
/*
* Hardware interface for Renoir ACP block
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
#include "amd.h"
#define DRV_NAME "acp_asoc_renoir"
static struct acp_resource rsrc = {
.offset = 20,
.no_of_ctrls = 1,
.irqp_used = 0,
.irq_reg_offset = 0x1800,
.i2s_pin_cfg_offset = 0x1400,
.i2s_mode = 0x04,
.scratch_reg_offset = 0x12800,
.sram_pte_offset = 0x02052800,
};
static struct snd_soc_acpi_codecs amp_rt1019 = {
.num_codecs = 1,
.codecs = {"10EC1019"}
};
static struct snd_soc_acpi_codecs amp_max = {
.num_codecs = 1,
.codecs = {"MX98360A"}
};
static struct snd_soc_acpi_mach snd_soc_acpi_amd_acp_machines[] = {
{
.id = "10EC5682",
.drv_name = "acp3xalc56821019",
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_rt1019,
},
{
.id = "RTL5682",
.drv_name = "acp3xalc5682sm98360",
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_max,
},
{
.id = "RTL5682",
.drv_name = "acp3xalc5682s1019",
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_rt1019,
},
{
.id = "AMDI1019",
.drv_name = "renoir-acp",
},
{},
};
static struct snd_soc_dai_driver acp_renoir_dai[] = {
{
.name = "acp-i2s-sp",
.id = I2S_SP_INSTANCE,
.playback = {
.stream_name = "I2S SP Playback",
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.stream_name = "I2S SP Capture",
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &asoc_acp_cpu_dai_ops,
},
{
.name = "acp-i2s-bt",
.id = I2S_BT_INSTANCE,
.playback = {
.stream_name = "I2S BT Playback",
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.stream_name = "I2S BT Capture",
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &asoc_acp_cpu_dai_ops,
},
{
.name = "acp-pdm-dmic",
.id = DMIC_INSTANCE,
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &acp_dmic_dai_ops,
},
};
static int renoir_audio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct acp_chip_info *chip;
struct acp_dev_data *adata;
struct resource *res;
int ret;
chip = dev_get_platdata(&pdev->dev);
if (!chip || !chip->base) {
dev_err(&pdev->dev, "ACP chip data is NULL\n");
return -ENODEV;
}
if (chip->acp_rev != ACP3X_DEV) {
dev_err(&pdev->dev, "Un-supported ACP Revision %d\n", chip->acp_rev);
return -ENODEV;
}
adata = devm_kzalloc(dev, sizeof(struct acp_dev_data), GFP_KERNEL);
if (!adata)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "acp_mem");
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata->acp_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!adata->acp_base)
return -ENOMEM;
ret = platform_get_irq_byname(pdev, "acp_dai_irq");
if (ret < 0)
return ret;
adata->i2s_irq = ret;
adata->dev = dev;
adata->dai_driver = acp_renoir_dai;
adata->num_dai = ARRAY_SIZE(acp_renoir_dai);
adata->rsrc = &rsrc;
adata->machines = snd_soc_acpi_amd_acp_machines;
acp_machine_select(adata);
dev_set_drvdata(dev, adata);
acp_enable_interrupts(adata);
acp_platform_register(dev);
return 0;
}
static void renoir_audio_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
acp_disable_interrupts(adata);
acp_platform_unregister(dev);
}
static struct platform_driver renoir_driver = {
.probe = renoir_audio_probe,
.remove_new = renoir_audio_remove,
.driver = {
.name = "acp_asoc_renoir",
},
};
module_platform_driver(renoir_driver);
MODULE_DESCRIPTION("AMD ACP Renoir Driver");
MODULE_IMPORT_NS(SND_SOC_ACP_COMMON);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/acp/acp-renoir.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
//
/*
* SOF Machine Driver Support for ACP HW block
*/
#include <sound/core.h>
#include <sound/pcm_params.h>
#include <sound/soc-acpi.h>
#include <sound/soc-dapm.h>
#include <linux/dmi.h>
#include <linux/module.h>
#include "acp-mach.h"
static struct acp_card_drvdata sof_rt5682_rt1019_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682,
.amp_codec_id = RT1019,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata sof_rt5682_max_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682,
.amp_codec_id = MAX98360A,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata sof_rt5682s_rt1019_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682S,
.amp_codec_id = RT1019,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata sof_rt5682s_max_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_SP,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682S,
.amp_codec_id = MAX98360A,
.dmic_codec_id = DMIC,
.tdm_mode = false,
};
static struct acp_card_drvdata sof_nau8825_data = {
.hs_cpu_id = I2S_HS,
.amp_cpu_id = I2S_HS,
.dmic_cpu_id = DMIC,
.hs_codec_id = NAU8825,
.amp_codec_id = MAX98360A,
.dmic_codec_id = DMIC,
.soc_mclk = true,
.tdm_mode = false,
};
static struct acp_card_drvdata sof_rt5682s_hs_rt1019_data = {
.hs_cpu_id = I2S_HS,
.amp_cpu_id = I2S_HS,
.dmic_cpu_id = DMIC,
.hs_codec_id = RT5682S,
.amp_codec_id = RT1019,
.dmic_codec_id = DMIC,
.soc_mclk = true,
.tdm_mode = false,
};
static struct acp_card_drvdata sof_nau8821_max98388_data = {
.hs_cpu_id = I2S_SP,
.amp_cpu_id = I2S_HS,
.dmic_cpu_id = NONE,
.hs_codec_id = NAU8821,
.amp_codec_id = MAX98388,
.dmic_codec_id = NONE,
.soc_mclk = true,
.tdm_mode = false,
};
static int acp_sof_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = NULL;
struct device *dev = &pdev->dev;
const struct dmi_system_id *dmi_id;
struct acp_card_drvdata *acp_card_drvdata;
int ret;
if (!pdev->id_entry)
return -EINVAL;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->dev = dev;
card->owner = THIS_MODULE;
card->name = pdev->id_entry->name;
card->drvdata = (struct acp_card_drvdata *)pdev->id_entry->driver_data;
/* Widgets and controls added per-codec in acp-mach-common.c */
acp_card_drvdata = card->drvdata;
dmi_id = dmi_first_match(acp_quirk_table);
if (dmi_id && dmi_id->driver_data)
acp_card_drvdata->tdm_mode = dmi_id->driver_data;
acp_sofdsp_dai_links_create(card);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
dev_err(&pdev->dev,
"devm_snd_soc_register_card(%s) failed: %d\n",
card->name, ret);
return ret;
}
return 0;
}
static const struct platform_device_id board_ids[] = {
{
.name = "rt5682-rt1019",
.driver_data = (kernel_ulong_t)&sof_rt5682_rt1019_data
},
{
.name = "rt5682-max",
.driver_data = (kernel_ulong_t)&sof_rt5682_max_data
},
{
.name = "rt5682s-max",
.driver_data = (kernel_ulong_t)&sof_rt5682s_max_data
},
{
.name = "rt5682s-rt1019",
.driver_data = (kernel_ulong_t)&sof_rt5682s_rt1019_data
},
{
.name = "nau8825-max",
.driver_data = (kernel_ulong_t)&sof_nau8825_data
},
{
.name = "rt5682s-hs-rt1019",
.driver_data = (kernel_ulong_t)&sof_rt5682s_hs_rt1019_data
},
{
.name = "nau8821-max",
.driver_data = (kernel_ulong_t)&sof_nau8821_max98388_data
},
{ }
};
static struct platform_driver acp_asoc_audio = {
.driver = {
.name = "sof_mach",
.pm = &snd_soc_pm_ops,
},
.probe = acp_sof_probe,
.id_table = board_ids,
};
module_platform_driver(acp_asoc_audio);
MODULE_IMPORT_NS(SND_SOC_AMD_MACH);
MODULE_DESCRIPTION("ACP chrome SOF audio support");
MODULE_ALIAS("platform:rt5682-rt1019");
MODULE_ALIAS("platform:rt5682-max");
MODULE_ALIAS("platform:rt5682s-max");
MODULE_ALIAS("platform:rt5682s-rt1019");
MODULE_ALIAS("platform:nau8825-max");
MODULE_ALIAS("platform:rt5682s-hs-rt1019");
MODULE_ALIAS("platform:nau8821-max");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/amd/acp/acp-sof-mach.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
// V sujith kumar Reddy <[email protected]>
/*
* Hardware interface for Renoir ACP block
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include "amd.h"
#define DRV_NAME "acp_asoc_rembrandt"
#define MP1_C2PMSG_69 0x3B10A14
#define MP1_C2PMSG_85 0x3B10A54
#define MP1_C2PMSG_93 0x3B10A74
#define HOST_BRIDGE_ID 0x14B5
static struct acp_resource rsrc = {
.offset = 0,
.no_of_ctrls = 2,
.irqp_used = 1,
.soc_mclk = true,
.irq_reg_offset = 0x1a00,
.i2s_pin_cfg_offset = 0x1440,
.i2s_mode = 0x0a,
.scratch_reg_offset = 0x12800,
.sram_pte_offset = 0x03802800,
};
static struct snd_soc_acpi_codecs amp_rt1019 = {
.num_codecs = 1,
.codecs = {"10EC1019"}
};
static struct snd_soc_acpi_codecs amp_max = {
.num_codecs = 1,
.codecs = {"MX98360A"}
};
static struct snd_soc_acpi_mach snd_soc_acpi_amd_rmb_acp_machines[] = {
{
.id = "10508825",
.drv_name = "rmb-nau8825-max",
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_max,
},
{
.id = "AMDI0007",
.drv_name = "rembrandt-acp",
},
{
.id = "RTL5682",
.drv_name = "rmb-rt5682s-rt1019",
.machine_quirk = snd_soc_acpi_codec_list,
.quirk_data = &_rt1019,
},
{},
};
static struct snd_soc_dai_driver acp_rmb_dai[] = {
{
.name = "acp-i2s-sp",
.id = I2S_SP_INSTANCE,
.playback = {
.stream_name = "I2S SP Playback",
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.stream_name = "I2S SP Capture",
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &asoc_acp_cpu_dai_ops,
},
{
.name = "acp-i2s-bt",
.id = I2S_BT_INSTANCE,
.playback = {
.stream_name = "I2S BT Playback",
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.stream_name = "I2S BT Capture",
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &asoc_acp_cpu_dai_ops,
},
{
.name = "acp-i2s-hs",
.id = I2S_HS_INSTANCE,
.playback = {
.stream_name = "I2S HS Playback",
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
},
.capture = {
.stream_name = "I2S HS Capture",
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &asoc_acp_cpu_dai_ops,
},
{
.name = "acp-pdm-dmic",
.id = DMIC_INSTANCE,
.capture = {
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &acp_dmic_dai_ops,
},
};
static int acp6x_master_clock_generate(struct device *dev)
{
int data = 0;
struct pci_dev *smn_dev;
smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, HOST_BRIDGE_ID, NULL);
if (!smn_dev) {
dev_err(dev, "Failed to get host bridge device\n");
return -ENODEV;
}
smn_write(smn_dev, MP1_C2PMSG_93, 0);
smn_write(smn_dev, MP1_C2PMSG_85, 0xC4);
smn_write(smn_dev, MP1_C2PMSG_69, 0x4);
read_poll_timeout(smn_read, data, data, DELAY_US,
ACP_TIMEOUT, false, smn_dev, MP1_C2PMSG_93);
return 0;
}
static int rembrandt_audio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct acp_chip_info *chip;
struct acp_dev_data *adata;
struct resource *res;
chip = dev_get_platdata(&pdev->dev);
if (!chip || !chip->base) {
dev_err(&pdev->dev, "ACP chip data is NULL\n");
return -ENODEV;
}
if (chip->acp_rev != ACP6X_DEV) {
dev_err(&pdev->dev, "Un-supported ACP Revision %d\n", chip->acp_rev);
return -ENODEV;
}
adata = devm_kzalloc(dev, sizeof(struct acp_dev_data), GFP_KERNEL);
if (!adata)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "acp_mem");
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
return -ENODEV;
}
adata->acp_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!adata->acp_base)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "acp_dai_irq");
if (!res) {
dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
return -ENODEV;
}
adata->i2s_irq = res->start;
adata->dev = dev;
adata->dai_driver = acp_rmb_dai;
adata->num_dai = ARRAY_SIZE(acp_rmb_dai);
adata->rsrc = &rsrc;
adata->machines = snd_soc_acpi_amd_rmb_acp_machines;
acp_machine_select(adata);
dev_set_drvdata(dev, adata);
acp6x_master_clock_generate(dev);
acp_enable_interrupts(adata);
acp_platform_register(dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static void rembrandt_audio_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
acp_disable_interrupts(adata);
acp_platform_unregister(dev);
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused rmb_pcm_resume(struct device *dev)
{
struct acp_dev_data *adata = dev_get_drvdata(dev);
struct acp_stream *stream;
struct snd_pcm_substream *substream;
snd_pcm_uframes_t buf_in_frames;
u64 buf_size;
acp6x_master_clock_generate(dev);
spin_lock(&adata->acp_lock);
list_for_each_entry(stream, &adata->stream_list, list) {
substream = stream->substream;
if (substream && substream->runtime) {
buf_in_frames = (substream->runtime->buffer_size);
buf_size = frames_to_bytes(substream->runtime, buf_in_frames);
config_pte_for_stream(adata, stream);
config_acp_dma(adata, stream, buf_size);
if (stream->dai_id)
restore_acp_i2s_params(substream, adata, stream);
else
restore_acp_pdm_params(substream, adata);
}
}
spin_unlock(&adata->acp_lock);
return 0;
}
static const struct dev_pm_ops rmb_dma_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(NULL, rmb_pcm_resume)
};
static struct platform_driver rembrandt_driver = {
.probe = rembrandt_audio_probe,
.remove_new = rembrandt_audio_remove,
.driver = {
.name = "acp_asoc_rembrandt",
.pm = &rmb_dma_pm_ops,
},
};
module_platform_driver(rembrandt_driver);
MODULE_DESCRIPTION("AMD ACP Rembrandt Driver");
MODULE_IMPORT_NS(SND_SOC_ACP_COMMON);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/amd/acp/acp-rembrandt.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Advanced Micro Devices, Inc.
//
// Authors: Ajit Kumar Pandey <[email protected]>
// Vijendar Mukunda <[email protected]>
//
/*
* Generic Hardware interface for ACP Audio PDM controller
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "amd.h"
#define DRV_NAME "acp-pdm"
static int acp_dmic_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct acp_stream *stream = substream->runtime->private_data;
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
u32 physical_addr, size_dmic, period_bytes;
unsigned int dmic_ctrl;
/* Enable default DMIC clk */
writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);
dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
dmic_ctrl |= PDM_MISC_CTRL_MASK;
writel(dmic_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);
period_bytes = frames_to_bytes(substream->runtime,
substream->runtime->period_size);
size_dmic = frames_to_bytes(substream->runtime,
substream->runtime->buffer_size);
physical_addr = stream->reg_offset + MEM_WINDOW_START;
/* Init DMIC Ring buffer */
writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);
writel(size_dmic, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);
writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
return 0;
}
static int acp_dmic_dai_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
unsigned int dma_enable;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
if (!(dma_enable & DMA_EN_MASK)) {
writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
}
ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
dma_enable, (dma_enable & DMA_EN_MASK),
DELAY_US, PDM_TIMEOUT);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
if ((dma_enable & DMA_EN_MASK)) {
writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
}
ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
dma_enable, !(dma_enable & DMA_EN_MASK),
DELAY_US, PDM_TIMEOUT);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int acp_dmic_hwparams(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hwparams, struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
unsigned int channels, ch_mask;
channels = params_channels(hwparams);
switch (channels) {
case 2:
ch_mask = 0;
break;
case 4:
ch_mask = 1;
break;
case 6:
ch_mask = 2;
break;
default:
dev_err(dev, "Invalid channels %d\n", channels);
return -EINVAL;
}
adata->ch_mask = ch_mask;
if (params_format(hwparams) != SNDRV_PCM_FORMAT_S32_LE) {
dev_err(dai->dev, "Invalid format:%d\n", params_format(hwparams));
return -EINVAL;
}
writel(ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);
return 0;
}
static int acp_dmic_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct acp_stream *stream = substream->runtime->private_data;
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
u32 ext_int_ctrl;
stream->dai_id = DMIC_INSTANCE;
stream->irq_bit = BIT(PDM_DMA_STAT);
stream->pte_offset = ACP_SRAM_PDM_PTE_OFFSET;
stream->reg_offset = ACP_REGION2_OFFSET;
/* Enable DMIC Interrupts */
ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
ext_int_ctrl |= PDM_DMA_INTR_MASK;
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
return 0;
}
static void acp_dmic_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct device *dev = dai->component->dev;
struct acp_dev_data *adata = dev_get_drvdata(dev);
u32 ext_int_ctrl;
/* Disable DMIC interrupts */
ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
ext_int_ctrl &= ~PDM_DMA_INTR_MASK;
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));
}
const struct snd_soc_dai_ops acp_dmic_dai_ops = {
.prepare = acp_dmic_prepare,
.hw_params = acp_dmic_hwparams,
.trigger = acp_dmic_dai_trigger,
.startup = acp_dmic_dai_startup,
.shutdown = acp_dmic_dai_shutdown,
};
EXPORT_SYMBOL_NS_GPL(acp_dmic_dai_ops, SND_SOC_ACP_COMMON);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS(DRV_NAME);
| linux-master | sound/soc/amd/acp/acp-pdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// SH7760 ("camelot") DMABRG audio DMA unit support
//
// Copyright (C) 2007 Manuel Lauss <[email protected]>
//
// The SH7760 DMABRG provides 4 dma channels (2x rec, 2x play), which
// trigger an interrupt when one half of the programmed transfer size
// has been xmitted.
//
// FIXME: little-endian only for now
#include <linux/module.h>
#include <linux/gfp.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/dmabrg.h>
/* registers and bits */
#define BRGATXSAR 0x00
#define BRGARXDAR 0x04
#define BRGATXTCR 0x08
#define BRGARXTCR 0x0C
#define BRGACR 0x10
#define BRGATXTCNT 0x14
#define BRGARXTCNT 0x18
#define ACR_RAR (1 << 18)
#define ACR_RDS (1 << 17)
#define ACR_RDE (1 << 16)
#define ACR_TAR (1 << 2)
#define ACR_TDS (1 << 1)
#define ACR_TDE (1 << 0)
/* receiver/transmitter data alignment */
#define ACR_RAM_NONE (0 << 24)
#define ACR_RAM_4BYTE (1 << 24)
#define ACR_RAM_2WORD (2 << 24)
#define ACR_TAM_NONE (0 << 8)
#define ACR_TAM_4BYTE (1 << 8)
#define ACR_TAM_2WORD (2 << 8)
struct camelot_pcm {
unsigned long mmio; /* DMABRG audio channel control reg MMIO */
unsigned int txid; /* ID of first DMABRG IRQ for this unit */
struct snd_pcm_substream *tx_ss;
unsigned long tx_period_size;
unsigned int tx_period;
struct snd_pcm_substream *rx_ss;
unsigned long rx_period_size;
unsigned int rx_period;
} cam_pcm_data[2] = {
{
.mmio = 0xFE3C0040,
.txid = DMABRGIRQ_A0TXF,
},
{
.mmio = 0xFE3C0060,
.txid = DMABRGIRQ_A1TXF,
},
};
#define BRGREG(x) (*(unsigned long *)(cam->mmio + (x)))
/*
* set a minimum of 16kb per period, to avoid interrupt-"storm" and
* resulting skipping. In general, the bigger the minimum size, the
* better for overall system performance. (The SH7760 is a puny CPU
* with a slow SDRAM interface and poor internal bus bandwidth,
* *especially* when the LCDC is active). The minimum for the DMAC
* is 8 bytes; 16kbytes are enough to get skip-free playback of a
* 44kHz/16bit/stereo MP3 on a lightly loaded system, and maintain
* reasonable responsiveness in MPlayer.
*/
#define DMABRG_PERIOD_MIN 16 * 1024
#define DMABRG_PERIOD_MAX 0x03fffffc
#define DMABRG_PREALLOC_BUFFER 32 * 1024
#define DMABRG_PREALLOC_BUFFER_MAX 32 * 1024
static const struct snd_pcm_hardware camelot_pcm_hardware = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BATCH),
.buffer_bytes_max = DMABRG_PERIOD_MAX,
.period_bytes_min = DMABRG_PERIOD_MIN,
.period_bytes_max = DMABRG_PERIOD_MAX / 2,
.periods_min = 2,
.periods_max = 2,
.fifo_size = 128,
};
static void camelot_txdma(void *data)
{
struct camelot_pcm *cam = data;
cam->tx_period ^= 1;
snd_pcm_period_elapsed(cam->tx_ss);
}
static void camelot_rxdma(void *data)
{
struct camelot_pcm *cam = data;
cam->rx_period ^= 1;
snd_pcm_period_elapsed(cam->rx_ss);
}
static int camelot_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
int ret, dmairq;
snd_soc_set_runtime_hwparams(substream, &camelot_pcm_hardware);
/* DMABRG buffer half/full events */
dmairq = (recv) ? cam->txid + 2 : cam->txid;
if (recv) {
cam->rx_ss = substream;
ret = dmabrg_request_irq(dmairq, camelot_rxdma, cam);
if (unlikely(ret)) {
pr_debug("audio unit %d irqs already taken!\n",
asoc_rtd_to_cpu(rtd, 0)->id);
return -EBUSY;
}
(void)dmabrg_request_irq(dmairq + 1,camelot_rxdma, cam);
} else {
cam->tx_ss = substream;
ret = dmabrg_request_irq(dmairq, camelot_txdma, cam);
if (unlikely(ret)) {
pr_debug("audio unit %d irqs already taken!\n",
asoc_rtd_to_cpu(rtd, 0)->id);
return -EBUSY;
}
(void)dmabrg_request_irq(dmairq + 1, camelot_txdma, cam);
}
return 0;
}
static int camelot_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
int dmairq;
dmairq = (recv) ? cam->txid + 2 : cam->txid;
if (recv)
cam->rx_ss = NULL;
else
cam->tx_ss = NULL;
dmabrg_free_irq(dmairq + 1);
dmabrg_free_irq(dmairq);
return 0;
}
static int camelot_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
if (recv) {
cam->rx_period_size = params_period_bytes(hw_params);
cam->rx_period = 0;
} else {
cam->tx_period_size = params_period_bytes(hw_params);
cam->tx_period = 0;
}
return 0;
}
static int camelot_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
pr_debug("PCM data: addr 0x%08lx len %d\n",
(u32)runtime->dma_addr, runtime->dma_bytes);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
BRGREG(BRGATXSAR) = (unsigned long)runtime->dma_area;
BRGREG(BRGATXTCR) = runtime->dma_bytes;
} else {
BRGREG(BRGARXDAR) = (unsigned long)runtime->dma_area;
BRGREG(BRGARXTCR) = runtime->dma_bytes;
}
return 0;
}
static inline void dmabrg_play_dma_start(struct camelot_pcm *cam)
{
unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
/* start DMABRG engine: XFER start, auto-addr-reload */
BRGREG(BRGACR) = acr | ACR_TDE | ACR_TAR | ACR_TAM_2WORD;
}
static inline void dmabrg_play_dma_stop(struct camelot_pcm *cam)
{
unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
/* forcibly terminate data transmission */
BRGREG(BRGACR) = acr | ACR_TDS;
}
static inline void dmabrg_rec_dma_start(struct camelot_pcm *cam)
{
unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
/* start DMABRG engine: recv start, auto-reload */
BRGREG(BRGACR) = acr | ACR_RDE | ACR_RAR | ACR_RAM_2WORD;
}
static inline void dmabrg_rec_dma_stop(struct camelot_pcm *cam)
{
unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
/* forcibly terminate data receiver */
BRGREG(BRGACR) = acr | ACR_RDS;
}
static int camelot_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
if (recv)
dmabrg_rec_dma_start(cam);
else
dmabrg_play_dma_start(cam);
break;
case SNDRV_PCM_TRIGGER_STOP:
if (recv)
dmabrg_rec_dma_stop(cam);
else
dmabrg_play_dma_stop(cam);
break;
default:
return -EINVAL;
}
return 0;
}
static snd_pcm_uframes_t camelot_pos(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
unsigned long pos;
/* cannot use the DMABRG pointer register: under load, by the
* time ALSA comes around to read the register, it is already
* far ahead (or worse, already done with the fragment) of the
* position at the time the IRQ was triggered, which results in
* fast-playback sound in my test application (ScummVM)
*/
if (recv)
pos = cam->rx_period ? cam->rx_period_size : 0;
else
pos = cam->tx_period ? cam->tx_period_size : 0;
return bytes_to_frames(runtime, pos);
}
static int camelot_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
/* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
* in MMAP mode (i.e. aplay -M)
*/
snd_pcm_set_managed_buffer_all(pcm,
SNDRV_DMA_TYPE_CONTINUOUS,
NULL,
DMABRG_PREALLOC_BUFFER, DMABRG_PREALLOC_BUFFER_MAX);
return 0;
}
static const struct snd_soc_component_driver sh7760_soc_component = {
.open = camelot_pcm_open,
.close = camelot_pcm_close,
.hw_params = camelot_hw_params,
.prepare = camelot_prepare,
.trigger = camelot_trigger,
.pointer = camelot_pos,
.pcm_construct = camelot_pcm_new,
};
static int sh7760_soc_platform_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev, &sh7760_soc_component,
NULL, 0);
}
static struct platform_driver sh7760_pcm_driver = {
.driver = {
.name = "sh7760-pcm-audio",
},
.probe = sh7760_soc_platform_probe,
};
module_platform_driver(sh7760_pcm_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("SH7760 Audio DMA (DMABRG) driver");
MODULE_AUTHOR("Manuel Lauss <[email protected]>");
| linux-master | sound/soc/sh/dma-sh7760.c |
// SPDX-License-Identifier: GPL-2.0+
//
// siu_dai.c - ALSA SoC driver for Renesas SH7343, SH7722 SIU peripheral.
//
// Copyright (C) 2009-2010 Guennadi Liakhovetski <[email protected]>
// Copyright (C) 2006 Carlos Munoz <[email protected]>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <asm/clock.h>
#include <asm/siu.h>
#include <sound/control.h>
#include <sound/soc.h>
#include "siu.h"
/* Board specifics */
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
# define SIU_MAX_VOLUME 0x1000
#else
# define SIU_MAX_VOLUME 0x7fff
#endif
#define PRAM_SIZE 0x2000
#define XRAM_SIZE 0x800
#define YRAM_SIZE 0x800
#define XRAM_OFFSET 0x4000
#define YRAM_OFFSET 0x6000
#define REG_OFFSET 0xc000
#define PLAYBACK_ENABLED 1
#define CAPTURE_ENABLED 2
#define VOLUME_CAPTURE 0
#define VOLUME_PLAYBACK 1
#define DFLT_VOLUME_LEVEL 0x08000800
/*
* SPDIF is only available on port A and on some SIU implementations it is only
* available for input. Due to the lack of hardware to test it, SPDIF is left
* disabled in this driver version
*/
struct format_flag {
u32 i2s;
u32 pcm;
u32 spdif;
u32 mask;
};
struct port_flag {
struct format_flag playback;
struct format_flag capture;
};
struct siu_info *siu_i2s_data;
static struct port_flag siu_flags[SIU_PORT_NUM] = {
[SIU_PORT_A] = {
.playback = {
.i2s = 0x50000000,
.pcm = 0x40000000,
.spdif = 0x80000000, /* not on all SIU versions */
.mask = 0xd0000000,
},
.capture = {
.i2s = 0x05000000,
.pcm = 0x04000000,
.spdif = 0x08000000,
.mask = 0x0d000000,
},
},
[SIU_PORT_B] = {
.playback = {
.i2s = 0x00500000,
.pcm = 0x00400000,
.spdif = 0, /* impossible - turn off */
.mask = 0x00500000,
},
.capture = {
.i2s = 0x00050000,
.pcm = 0x00040000,
.spdif = 0, /* impossible - turn off */
.mask = 0x00050000,
},
},
};
static void siu_dai_start(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
dev_dbg(port_info->pcm->card->dev, "%s\n", __func__);
/* Issue software reset to siu */
siu_write32(base + SIU_SRCTL, 0);
/* Wait for the reset to take effect */
udelay(1);
port_info->stfifo = 0;
port_info->trdat = 0;
/* portA, portB, SIU operate */
siu_write32(base + SIU_SRCTL, 0x301);
/* portA=256fs, portB=256fs */
siu_write32(base + SIU_CKCTL, 0x40400000);
/* portA's BRG does not divide SIUCKA */
siu_write32(base + SIU_BRGASEL, 0);
siu_write32(base + SIU_BRRA, 0);
/* portB's BRG divides SIUCKB by half */
siu_write32(base + SIU_BRGBSEL, 1);
siu_write32(base + SIU_BRRB, 0);
siu_write32(base + SIU_IFCTL, 0x44440000);
/* portA: 32 bit/fs, master; portB: 32 bit/fs, master */
siu_write32(base + SIU_SFORM, 0x0c0c0000);
/*
* Volume levels: looks like the DSP firmware implements volume controls
* differently from what's described in the datasheet
*/
siu_write32(base + SIU_SBDVCA, port_info->playback.volume);
siu_write32(base + SIU_SBDVCB, port_info->capture.volume);
}
static void siu_dai_stop(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
/* SIU software reset */
siu_write32(base + SIU_SRCTL, 0);
}
static void siu_dai_spbAselect(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
struct siu_firmware *fw = &info->fw;
u32 *ydef = fw->yram0;
u32 idx;
/* path A use */
if (!info->port_id)
idx = 1; /* portA */
else
idx = 2; /* portB */
ydef[0] = (fw->spbpar[idx].ab1a << 16) |
(fw->spbpar[idx].ab0a << 8) |
(fw->spbpar[idx].dir << 7) | 3;
ydef[1] = fw->yram0[1]; /* 0x03000300 */
ydef[2] = (16 / 2) << 24;
ydef[3] = fw->yram0[3]; /* 0 */
ydef[4] = fw->yram0[4]; /* 0 */
ydef[7] = fw->spbpar[idx].event;
port_info->stfifo |= fw->spbpar[idx].stfifo;
port_info->trdat |= fw->spbpar[idx].trdat;
}
static void siu_dai_spbBselect(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
struct siu_firmware *fw = &info->fw;
u32 *ydef = fw->yram0;
u32 idx;
/* path B use */
if (!info->port_id)
idx = 7; /* portA */
else
idx = 8; /* portB */
ydef[5] = (fw->spbpar[idx].ab1a << 16) |
(fw->spbpar[idx].ab0a << 8) | 1;
ydef[6] = fw->spbpar[idx].event;
port_info->stfifo |= fw->spbpar[idx].stfifo;
port_info->trdat |= fw->spbpar[idx].trdat;
}
static void siu_dai_open(struct siu_stream *siu_stream)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
u32 srctl, ifctl;
srctl = siu_read32(base + SIU_SRCTL);
ifctl = siu_read32(base + SIU_IFCTL);
switch (info->port_id) {
case SIU_PORT_A:
/* portA operates */
srctl |= 0x200;
ifctl &= ~0xc2;
break;
case SIU_PORT_B:
/* portB operates */
srctl |= 0x100;
ifctl &= ~0x31;
break;
}
siu_write32(base + SIU_SRCTL, srctl);
/* Unmute and configure portA */
siu_write32(base + SIU_IFCTL, ifctl);
}
/*
* At the moment only fixed Left-upper, Left-lower, Right-upper, Right-lower
* packing is supported
*/
static void siu_dai_pcmdatapack(struct siu_stream *siu_stream)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
u32 dpak;
dpak = siu_read32(base + SIU_DPAK);
switch (info->port_id) {
case SIU_PORT_A:
dpak &= ~0xc0000000;
break;
case SIU_PORT_B:
dpak &= ~0x00c00000;
break;
}
siu_write32(base + SIU_DPAK, dpak);
}
static int siu_dai_spbstart(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
struct siu_firmware *fw = &info->fw;
u32 *ydef = fw->yram0;
int cnt;
u32 __iomem *add;
u32 *ptr;
/* Load SPB Program in PRAM */
ptr = fw->pram0;
add = info->pram;
for (cnt = 0; cnt < PRAM0_SIZE; cnt++, add++, ptr++)
siu_write32(add, *ptr);
ptr = fw->pram1;
add = info->pram + (0x0100 / sizeof(u32));
for (cnt = 0; cnt < PRAM1_SIZE; cnt++, add++, ptr++)
siu_write32(add, *ptr);
/* XRAM initialization */
add = info->xram;
for (cnt = 0; cnt < XRAM0_SIZE + XRAM1_SIZE + XRAM2_SIZE; cnt++, add++)
siu_write32(add, 0);
/* YRAM variable area initialization */
add = info->yram;
for (cnt = 0; cnt < YRAM_DEF_SIZE; cnt++, add++)
siu_write32(add, ydef[cnt]);
/* YRAM FIR coefficient area initialization */
add = info->yram + (0x0200 / sizeof(u32));
for (cnt = 0; cnt < YRAM_FIR_SIZE; cnt++, add++)
siu_write32(add, fw->yram_fir_coeff[cnt]);
/* YRAM IIR coefficient area initialization */
add = info->yram + (0x0600 / sizeof(u32));
for (cnt = 0; cnt < YRAM_IIR_SIZE; cnt++, add++)
siu_write32(add, 0);
siu_write32(base + SIU_TRDAT, port_info->trdat);
port_info->trdat = 0x0;
/* SPB start condition: software */
siu_write32(base + SIU_SBACTIV, 0);
/* Start SPB */
siu_write32(base + SIU_SBCTL, 0xc0000000);
/* Wait for program to halt */
cnt = 0x10000;
while (--cnt && siu_read32(base + SIU_SBCTL) != 0x80000000)
cpu_relax();
if (!cnt)
return -EBUSY;
/* SPB program start address setting */
siu_write32(base + SIU_SBPSET, 0x00400000);
/* SPB hardware start(FIFOCTL source) */
siu_write32(base + SIU_SBACTIV, 0xc0000000);
return 0;
}
static void siu_dai_spbstop(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
siu_write32(base + SIU_SBACTIV, 0);
/* SPB stop */
siu_write32(base + SIU_SBCTL, 0);
port_info->stfifo = 0;
}
/* API functions */
/* Playback and capture hardware properties are identical */
static const struct snd_pcm_hardware siu_dai_pcm_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED,
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = SIU_BUFFER_BYTES_MAX,
.period_bytes_min = SIU_PERIOD_BYTES_MIN,
.period_bytes_max = SIU_PERIOD_BYTES_MAX,
.periods_min = SIU_PERIODS_MIN,
.periods_max = SIU_PERIODS_MAX,
};
static int siu_dai_info_volume(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_info *uinfo)
{
struct siu_port *port_info = snd_kcontrol_chip(kctrl);
dev_dbg(port_info->pcm->card->dev, "%s\n", __func__);
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = SIU_MAX_VOLUME;
return 0;
}
static int siu_dai_get_volume(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_value *ucontrol)
{
struct siu_port *port_info = snd_kcontrol_chip(kctrl);
struct device *dev = port_info->pcm->card->dev;
u32 vol;
dev_dbg(dev, "%s\n", __func__);
switch (kctrl->private_value) {
case VOLUME_PLAYBACK:
/* Playback is always on port 0 */
vol = port_info->playback.volume;
ucontrol->value.integer.value[0] = vol & 0xffff;
ucontrol->value.integer.value[1] = vol >> 16 & 0xffff;
break;
case VOLUME_CAPTURE:
/* Capture is always on port 1 */
vol = port_info->capture.volume;
ucontrol->value.integer.value[0] = vol & 0xffff;
ucontrol->value.integer.value[1] = vol >> 16 & 0xffff;
break;
default:
dev_err(dev, "%s() invalid private_value=%ld\n",
__func__, kctrl->private_value);
return -EINVAL;
}
return 0;
}
static int siu_dai_put_volume(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_value *ucontrol)
{
struct siu_port *port_info = snd_kcontrol_chip(kctrl);
struct device *dev = port_info->pcm->card->dev;
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
u32 new_vol;
u32 cur_vol;
dev_dbg(dev, "%s\n", __func__);
if (ucontrol->value.integer.value[0] < 0 ||
ucontrol->value.integer.value[0] > SIU_MAX_VOLUME ||
ucontrol->value.integer.value[1] < 0 ||
ucontrol->value.integer.value[1] > SIU_MAX_VOLUME)
return -EINVAL;
new_vol = ucontrol->value.integer.value[0] |
ucontrol->value.integer.value[1] << 16;
/* See comment above - DSP firmware implementation */
switch (kctrl->private_value) {
case VOLUME_PLAYBACK:
/* Playback is always on port 0 */
cur_vol = port_info->playback.volume;
siu_write32(base + SIU_SBDVCA, new_vol);
port_info->playback.volume = new_vol;
break;
case VOLUME_CAPTURE:
/* Capture is always on port 1 */
cur_vol = port_info->capture.volume;
siu_write32(base + SIU_SBDVCB, new_vol);
port_info->capture.volume = new_vol;
break;
default:
dev_err(dev, "%s() invalid private_value=%ld\n",
__func__, kctrl->private_value);
return -EINVAL;
}
if (cur_vol != new_vol)
return 1;
return 0;
}
static const struct snd_kcontrol_new playback_controls = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "PCM Playback Volume",
.index = 0,
.info = siu_dai_info_volume,
.get = siu_dai_get_volume,
.put = siu_dai_put_volume,
.private_value = VOLUME_PLAYBACK,
};
static const struct snd_kcontrol_new capture_controls = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "PCM Capture Volume",
.index = 0,
.info = siu_dai_info_volume,
.get = siu_dai_get_volume,
.put = siu_dai_put_volume,
.private_value = VOLUME_CAPTURE,
};
int siu_init_port(int port, struct siu_port **port_info, struct snd_card *card)
{
struct device *dev = card->dev;
struct snd_kcontrol *kctrl;
int ret;
*port_info = kzalloc(sizeof(**port_info), GFP_KERNEL);
if (!*port_info)
return -ENOMEM;
dev_dbg(dev, "%s: port #%d@%p\n", __func__, port, *port_info);
(*port_info)->playback.volume = DFLT_VOLUME_LEVEL;
(*port_info)->capture.volume = DFLT_VOLUME_LEVEL;
/*
* Add mixer support. The SPB is used to change the volume. Both
* ports use the same SPB. Therefore, we only register one
* control instance since it will be used by both channels.
* In error case we continue without controls.
*/
kctrl = snd_ctl_new1(&playback_controls, *port_info);
ret = snd_ctl_add(card, kctrl);
if (ret < 0)
dev_err(dev,
"failed to add playback controls %p port=%d err=%d\n",
kctrl, port, ret);
kctrl = snd_ctl_new1(&capture_controls, *port_info);
ret = snd_ctl_add(card, kctrl);
if (ret < 0)
dev_err(dev,
"failed to add capture controls %p port=%d err=%d\n",
kctrl, port, ret);
return 0;
}
void siu_free_port(struct siu_port *port_info)
{
kfree(port_info);
}
static int siu_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct siu_info *info = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *rt = substream->runtime;
struct siu_port *port_info = siu_port_info(substream);
int ret;
dev_dbg(substream->pcm->card->dev, "%s: port=%d@%p\n", __func__,
info->port_id, port_info);
snd_soc_set_runtime_hwparams(substream, &siu_dai_pcm_hw);
ret = snd_pcm_hw_constraint_integer(rt, SNDRV_PCM_HW_PARAM_PERIODS);
if (unlikely(ret < 0))
return ret;
siu_dai_start(port_info);
return 0;
}
static void siu_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct siu_info *info = snd_soc_dai_get_drvdata(dai);
struct siu_port *port_info = siu_port_info(substream);
dev_dbg(substream->pcm->card->dev, "%s: port=%d@%p\n", __func__,
info->port_id, port_info);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
port_info->play_cap &= ~PLAYBACK_ENABLED;
else
port_info->play_cap &= ~CAPTURE_ENABLED;
/* Stop the siu if the other stream is not using it */
if (!port_info->play_cap) {
/* during stmread or stmwrite ? */
if (WARN_ON(port_info->playback.rw_flg || port_info->capture.rw_flg))
return;
siu_dai_spbstop(port_info);
siu_dai_stop(port_info);
}
}
/* PCM part of siu_dai_playback_prepare() / siu_dai_capture_prepare() */
static int siu_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct siu_info *info = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *rt = substream->runtime;
struct siu_port *port_info = siu_port_info(substream);
struct siu_stream *siu_stream;
int self, ret;
dev_dbg(substream->pcm->card->dev,
"%s: port %d, active streams %lx, %d channels\n",
__func__, info->port_id, port_info->play_cap, rt->channels);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
self = PLAYBACK_ENABLED;
siu_stream = &port_info->playback;
} else {
self = CAPTURE_ENABLED;
siu_stream = &port_info->capture;
}
/* Set up the siu if not already done */
if (!port_info->play_cap) {
siu_stream->rw_flg = 0; /* stream-data transfer flag */
siu_dai_spbAselect(port_info);
siu_dai_spbBselect(port_info);
siu_dai_open(siu_stream);
siu_dai_pcmdatapack(siu_stream);
ret = siu_dai_spbstart(port_info);
if (ret < 0)
goto fail;
} else {
ret = 0;
}
port_info->play_cap |= self;
fail:
return ret;
}
/*
* SIU can set bus format to I2S / PCM / SPDIF independently for playback and
* capture, however, the current API sets the bus format globally for a DAI.
*/
static int siu_dai_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct siu_info *info = snd_soc_dai_get_drvdata(dai);
u32 __iomem *base = info->reg;
u32 ifctl;
dev_dbg(dai->dev, "%s: fmt 0x%x on port %d\n",
__func__, fmt, info->port_id);
if (info->port_id < 0)
return -ENODEV;
/* Here select between I2S / PCM / SPDIF */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ifctl = siu_flags[info->port_id].playback.i2s |
siu_flags[info->port_id].capture.i2s;
break;
case SND_SOC_DAIFMT_LEFT_J:
ifctl = siu_flags[info->port_id].playback.pcm |
siu_flags[info->port_id].capture.pcm;
break;
/* SPDIF disabled - see comment at the top */
default:
return -EINVAL;
}
ifctl |= ~(siu_flags[info->port_id].playback.mask |
siu_flags[info->port_id].capture.mask) &
siu_read32(base + SIU_IFCTL);
siu_write32(base + SIU_IFCTL, ifctl);
return 0;
}
static int siu_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct clk *siu_clk, *parent_clk;
char *siu_name, *parent_name;
int ret;
if (dir != SND_SOC_CLOCK_IN)
return -EINVAL;
dev_dbg(dai->dev, "%s: using clock %d\n", __func__, clk_id);
switch (clk_id) {
case SIU_CLKA_PLL:
siu_name = "siua_clk";
parent_name = "pll_clk";
break;
case SIU_CLKA_EXT:
siu_name = "siua_clk";
parent_name = "siumcka_clk";
break;
case SIU_CLKB_PLL:
siu_name = "siub_clk";
parent_name = "pll_clk";
break;
case SIU_CLKB_EXT:
siu_name = "siub_clk";
parent_name = "siumckb_clk";
break;
default:
return -EINVAL;
}
siu_clk = clk_get(dai->dev, siu_name);
if (IS_ERR(siu_clk)) {
dev_err(dai->dev, "%s: cannot get a SIU clock: %ld\n", __func__,
PTR_ERR(siu_clk));
return PTR_ERR(siu_clk);
}
parent_clk = clk_get(dai->dev, parent_name);
if (IS_ERR(parent_clk)) {
ret = PTR_ERR(parent_clk);
dev_err(dai->dev, "cannot get a SIU clock parent: %d\n", ret);
goto epclkget;
}
ret = clk_set_parent(siu_clk, parent_clk);
if (ret < 0) {
dev_err(dai->dev, "cannot reparent the SIU clock: %d\n", ret);
goto eclksetp;
}
ret = clk_set_rate(siu_clk, freq);
if (ret < 0)
dev_err(dai->dev, "cannot set SIU clock rate: %d\n", ret);
/* TODO: when clkdev gets reference counting we'll move these to siu_dai_shutdown() */
eclksetp:
clk_put(parent_clk);
epclkget:
clk_put(siu_clk);
return ret;
}
static const struct snd_soc_dai_ops siu_dai_ops = {
.startup = siu_dai_startup,
.shutdown = siu_dai_shutdown,
.prepare = siu_dai_prepare,
.set_sysclk = siu_dai_set_sysclk,
.set_fmt = siu_dai_set_fmt,
};
static struct snd_soc_dai_driver siu_i2s_dai = {
.name = "siu-i2s-dai",
.playback = {
.channels_min = 2,
.channels_max = 2,
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_8000_48000,
},
.capture = {
.channels_min = 2,
.channels_max = 2,
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_8000_48000,
},
.ops = &siu_dai_ops,
};
static int siu_probe(struct platform_device *pdev)
{
const struct firmware *fw_entry;
struct resource *res, *region;
struct siu_info *info;
int ret;
info = devm_kmalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
siu_i2s_data = info;
info->dev = &pdev->dev;
ret = request_firmware(&fw_entry, "siu_spb.bin", &pdev->dev);
if (ret)
return ret;
/*
* Loaded firmware is "const" - read only, but we have to modify it in
* snd_siu_sh7343_spbAselect() and snd_siu_sh7343_spbBselect()
*/
memcpy(&info->fw, fw_entry->data, fw_entry->size);
release_firmware(fw_entry);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
region = devm_request_mem_region(&pdev->dev, res->start,
resource_size(res), pdev->name);
if (!region) {
dev_err(&pdev->dev, "SIU region already claimed\n");
return -EBUSY;
}
info->pram = devm_ioremap(&pdev->dev, res->start, PRAM_SIZE);
if (!info->pram)
return -ENOMEM;
info->xram = devm_ioremap(&pdev->dev, res->start + XRAM_OFFSET,
XRAM_SIZE);
if (!info->xram)
return -ENOMEM;
info->yram = devm_ioremap(&pdev->dev, res->start + YRAM_OFFSET,
YRAM_SIZE);
if (!info->yram)
return -ENOMEM;
info->reg = devm_ioremap(&pdev->dev, res->start + REG_OFFSET,
resource_size(res) - REG_OFFSET);
if (!info->reg)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, info);
/* register using ARRAY version so we can keep dai name */
ret = devm_snd_soc_register_component(&pdev->dev, &siu_component,
&siu_i2s_dai, 1);
if (ret < 0)
return ret;
pm_runtime_enable(&pdev->dev);
return 0;
}
static void siu_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static struct platform_driver siu_driver = {
.driver = {
.name = "siu-pcm-audio",
},
.probe = siu_probe,
.remove_new = siu_remove,
};
module_platform_driver(siu_driver);
MODULE_AUTHOR("Carlos Munoz <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC SH7722 SIU driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("siu_spb.bin");
| linux-master | sound/soc/sh/siu_dai.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
//
// Copyright (C) 2021 Renesas Electronics Corp.
// Copyright (C) 2019 Chris Brandt.
//
#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/soc.h>
/* REGISTER OFFSET */
#define SSICR 0x000
#define SSISR 0x004
#define SSIFCR 0x010
#define SSIFSR 0x014
#define SSIFTDR 0x018
#define SSIFRDR 0x01c
#define SSIOFR 0x020
#define SSISCR 0x024
/* SSI REGISTER BITS */
#define SSICR_DWL(x) (((x) & 0x7) << 19)
#define SSICR_SWL(x) (((x) & 0x7) << 16)
#define SSICR_CKS BIT(30)
#define SSICR_TUIEN BIT(29)
#define SSICR_TOIEN BIT(28)
#define SSICR_RUIEN BIT(27)
#define SSICR_ROIEN BIT(26)
#define SSICR_MST BIT(14)
#define SSICR_BCKP BIT(13)
#define SSICR_LRCKP BIT(12)
#define SSICR_CKDV(x) (((x) & 0xf) << 4)
#define SSICR_TEN BIT(1)
#define SSICR_REN BIT(0)
#define SSISR_TUIRQ BIT(29)
#define SSISR_TOIRQ BIT(28)
#define SSISR_RUIRQ BIT(27)
#define SSISR_ROIRQ BIT(26)
#define SSISR_IIRQ BIT(25)
#define SSIFCR_AUCKE BIT(31)
#define SSIFCR_SSIRST BIT(16)
#define SSIFCR_TIE BIT(3)
#define SSIFCR_RIE BIT(2)
#define SSIFCR_TFRST BIT(1)
#define SSIFCR_RFRST BIT(0)
#define SSIFSR_TDC_MASK 0x3f
#define SSIFSR_TDC_SHIFT 24
#define SSIFSR_RDC_MASK 0x3f
#define SSIFSR_RDC_SHIFT 8
#define SSIFSR_TDE BIT(16)
#define SSIFSR_RDF BIT(0)
#define SSIOFR_LRCONT BIT(8)
#define SSISCR_TDES(x) (((x) & 0x1f) << 8)
#define SSISCR_RDFS(x) (((x) & 0x1f) << 0)
/* Pre allocated buffers sizes */
#define PREALLOC_BUFFER (SZ_32K)
#define PREALLOC_BUFFER_MAX (SZ_32K)
#define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */
#define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE
#define SSI_CHAN_MIN 2
#define SSI_CHAN_MAX 2
#define SSI_FIFO_DEPTH 32
struct rz_ssi_priv;
struct rz_ssi_stream {
struct rz_ssi_priv *priv;
struct snd_pcm_substream *substream;
int fifo_sample_size; /* sample capacity of SSI FIFO */
int dma_buffer_pos; /* The address for the next DMA descriptor */
int period_counter; /* for keeping track of periods transferred */
int sample_width;
int buffer_pos; /* current frame position in the buffer */
int running; /* 0=stopped, 1=running */
int uerr_num;
int oerr_num;
struct dma_chan *dma_ch;
int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
};
struct rz_ssi_priv {
void __iomem *base;
struct platform_device *pdev;
struct reset_control *rstc;
struct device *dev;
struct clk *sfr_clk;
struct clk *clk;
phys_addr_t phys;
int irq_int;
int irq_tx;
int irq_rx;
int irq_rt;
spinlock_t lock;
/*
* The SSI supports full-duplex transmission and reception.
* However, if an error occurs, channel reset (both transmission
* and reception reset) is required.
* So it is better to use as half-duplex (playing and recording
* should be done on separate channels).
*/
struct rz_ssi_stream playback;
struct rz_ssi_stream capture;
/* clock */
unsigned long audio_mck;
unsigned long audio_clk_1;
unsigned long audio_clk_2;
bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
bool dma_rt;
};
static void rz_ssi_dma_complete(void *data);
static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
{
writel(data, (priv->base + reg));
}
static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
{
return readl(priv->base + reg);
}
static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
u32 bclr, u32 bset)
{
u32 val;
val = readl(priv->base + reg);
val = (val & ~bclr) | bset;
writel(val, (priv->base + reg));
}
static inline struct snd_soc_dai *
rz_ssi_get_dai(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
return asoc_rtd_to_cpu(rtd, 0);
}
static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi,
struct snd_pcm_substream *substream)
{
return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
}
static inline struct rz_ssi_stream *
rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
{
struct rz_ssi_stream *stream = &ssi->playback;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
stream = &ssi->capture;
return stream;
}
static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
{
return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
}
static void rz_ssi_set_substream(struct rz_ssi_stream *strm,
struct snd_pcm_substream *substream)
{
struct rz_ssi_priv *ssi = strm->priv;
unsigned long flags;
spin_lock_irqsave(&ssi->lock, flags);
strm->substream = substream;
spin_unlock_irqrestore(&ssi->lock, flags);
}
static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
struct rz_ssi_stream *strm)
{
unsigned long flags;
bool ret;
spin_lock_irqsave(&ssi->lock, flags);
ret = strm->substream && strm->substream->runtime;
spin_unlock_irqrestore(&ssi->lock, flags);
return ret;
}
static void rz_ssi_stream_init(struct rz_ssi_stream *strm,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
rz_ssi_set_substream(strm, substream);
strm->sample_width = samples_to_bytes(runtime, 1);
strm->dma_buffer_pos = 0;
strm->period_counter = 0;
strm->buffer_pos = 0;
strm->oerr_num = 0;
strm->uerr_num = 0;
strm->running = 0;
/* fifo init */
strm->fifo_sample_size = SSI_FIFO_DEPTH;
}
static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
struct rz_ssi_stream *strm)
{
struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream);
rz_ssi_set_substream(strm, NULL);
if (strm->oerr_num > 0)
dev_info(dai->dev, "overrun = %d\n", strm->oerr_num);
if (strm->uerr_num > 0)
dev_info(dai->dev, "underrun = %d\n", strm->uerr_num);
}
static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
unsigned int channels)
{
static s8 ckdv[16] = { 1, 2, 4, 8, 16, 32, 64, 128,
6, 12, 24, 48, 96, -1, -1, -1 };
unsigned int channel_bits = 32; /* System Word Length */
unsigned long bclk_rate = rate * channels * channel_bits;
unsigned int div;
unsigned int i;
u32 ssicr = 0;
u32 clk_ckdv;
/* Clear AUCKE so we can set MST */
rz_ssi_reg_writel(ssi, SSIFCR, 0);
/* Continue to output LRCK pin even when idle */
rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
if (ssi->audio_clk_1 && ssi->audio_clk_2) {
if (ssi->audio_clk_1 % bclk_rate)
ssi->audio_mck = ssi->audio_clk_2;
else
ssi->audio_mck = ssi->audio_clk_1;
}
/* Clock setting */
ssicr |= SSICR_MST;
if (ssi->audio_mck == ssi->audio_clk_1)
ssicr |= SSICR_CKS;
if (ssi->bckp_rise)
ssicr |= SSICR_BCKP;
if (ssi->lrckp_fsync_fall)
ssicr |= SSICR_LRCKP;
/* Determine the clock divider */
clk_ckdv = 0;
div = ssi->audio_mck / bclk_rate;
/* try to find an match */
for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
if (ckdv[i] == div) {
clk_ckdv = i;
break;
}
}
if (i == ARRAY_SIZE(ckdv)) {
dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
return -EINVAL;
}
/*
* DWL: Data Word Length = 16 bits
* SWL: System Word Length = 32 bits
*/
ssicr |= SSICR_CKDV(clk_ckdv);
ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
rz_ssi_reg_writel(ssi, SSICR, ssicr);
rz_ssi_reg_writel(ssi, SSIFCR,
(SSIFCR_AUCKE | SSIFCR_TFRST | SSIFCR_RFRST));
return 0;
}
static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
{
bool is_play = rz_ssi_stream_is_play(ssi, strm->substream);
u32 ssicr, ssifcr;
ssicr = rz_ssi_reg_readl(ssi, SSICR);
ssifcr = rz_ssi_reg_readl(ssi, SSIFCR) & ~0xF;
/* FIFO interrupt thresholds */
if (rz_ssi_is_dma_enabled(ssi))
rz_ssi_reg_writel(ssi, SSISCR, 0);
else
rz_ssi_reg_writel(ssi, SSISCR,
SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
SSISCR_RDFS(0));
/* enable IRQ */
if (is_play) {
ssicr |= SSICR_TUIEN | SSICR_TOIEN;
ssifcr |= SSIFCR_TIE | SSIFCR_RFRST;
} else {
ssicr |= SSICR_RUIEN | SSICR_ROIEN;
ssifcr |= SSIFCR_RIE | SSIFCR_TFRST;
}
rz_ssi_reg_writel(ssi, SSICR, ssicr);
rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
/* Clear all error flags */
rz_ssi_reg_mask_setl(ssi, SSISR,
(SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
SSISR_RUIRQ), 0);
strm->running = 1;
ssicr |= is_play ? SSICR_TEN : SSICR_REN;
rz_ssi_reg_writel(ssi, SSICR, ssicr);
return 0;
}
static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
{
int timeout;
strm->running = 0;
/* Disable TX/RX */
rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
/* Cancel all remaining DMA transactions */
if (rz_ssi_is_dma_enabled(ssi))
dmaengine_terminate_async(strm->dma_ch);
/* Disable irqs */
rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
SSICR_RUIEN | SSICR_ROIEN, 0);
rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
/* Clear all error flags */
rz_ssi_reg_mask_setl(ssi, SSISR,
(SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
SSISR_RUIRQ), 0);
/* Wait for idle */
timeout = 100;
while (--timeout) {
if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ)
break;
udelay(1);
}
if (!timeout)
dev_info(ssi->dev, "timeout waiting for SSI idle\n");
/* Hold FIFOs in reset */
rz_ssi_reg_mask_setl(ssi, SSIFCR, 0,
SSIFCR_TFRST | SSIFCR_RFRST);
return 0;
}
static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
{
struct snd_pcm_substream *substream = strm->substream;
struct snd_pcm_runtime *runtime;
int current_period;
if (!strm->running || !substream || !substream->runtime)
return;
runtime = substream->runtime;
strm->buffer_pos += frames;
WARN_ON(strm->buffer_pos > runtime->buffer_size);
/* ring buffer */
if (strm->buffer_pos == runtime->buffer_size)
strm->buffer_pos = 0;
current_period = strm->buffer_pos / runtime->period_size;
if (strm->period_counter != current_period) {
snd_pcm_period_elapsed(strm->substream);
strm->period_counter = current_period;
}
}
static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
{
struct snd_pcm_substream *substream = strm->substream;
struct snd_pcm_runtime *runtime;
u16 *buf;
int fifo_samples;
int frames_left;
int samples;
int i;
if (!rz_ssi_stream_is_valid(ssi, strm))
return -EINVAL;
runtime = substream->runtime;
do {
/* frames left in this period */
frames_left = runtime->period_size -
(strm->buffer_pos % runtime->period_size);
if (!frames_left)
frames_left = runtime->period_size;
/* Samples in RX FIFO */
fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
/* Only read full frames at a time */
samples = 0;
while (frames_left && (fifo_samples >= runtime->channels)) {
samples += runtime->channels;
fifo_samples -= runtime->channels;
frames_left--;
}
/* not enough samples yet */
if (!samples)
break;
/* calculate new buffer index */
buf = (u16 *)runtime->dma_area;
buf += strm->buffer_pos * runtime->channels;
/* Note, only supports 16-bit samples */
for (i = 0; i < samples; i++)
*buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
rz_ssi_pointer_update(strm, samples / runtime->channels);
} while (!frames_left && fifo_samples >= runtime->channels);
return 0;
}
static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
{
struct snd_pcm_substream *substream = strm->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
int sample_space;
int samples = 0;
int frames_left;
int i;
u32 ssifsr;
u16 *buf;
if (!rz_ssi_stream_is_valid(ssi, strm))
return -EINVAL;
/* frames left in this period */
frames_left = runtime->period_size - (strm->buffer_pos %
runtime->period_size);
if (frames_left == 0)
frames_left = runtime->period_size;
sample_space = strm->fifo_sample_size;
ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
/* Only add full frames at a time */
while (frames_left && (sample_space >= runtime->channels)) {
samples += runtime->channels;
sample_space -= runtime->channels;
frames_left--;
}
/* no space to send anything right now */
if (samples == 0)
return 0;
/* calculate new buffer index */
buf = (u16 *)(runtime->dma_area);
buf += strm->buffer_pos * runtime->channels;
/* Note, only supports 16-bit samples */
for (i = 0; i < samples; i++)
rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
rz_ssi_pointer_update(strm, samples / runtime->channels);
return 0;
}
static irqreturn_t rz_ssi_interrupt(int irq, void *data)
{
struct rz_ssi_stream *strm = NULL;
struct rz_ssi_priv *ssi = data;
u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
if (ssi->playback.substream)
strm = &ssi->playback;
else if (ssi->capture.substream)
strm = &ssi->capture;
else
return IRQ_HANDLED; /* Left over TX/RX interrupt */
if (irq == ssi->irq_int) { /* error or idle */
if (ssisr & SSISR_TUIRQ)
strm->uerr_num++;
if (ssisr & SSISR_TOIRQ)
strm->oerr_num++;
if (ssisr & SSISR_RUIRQ)
strm->uerr_num++;
if (ssisr & SSISR_ROIRQ)
strm->oerr_num++;
if (ssisr & (SSISR_TUIRQ | SSISR_TOIRQ | SSISR_RUIRQ |
SSISR_ROIRQ)) {
/* Error handling */
/* You must reset (stop/restart) after each interrupt */
rz_ssi_stop(ssi, strm);
/* Clear all flags */
rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ |
SSISR_TUIRQ | SSISR_ROIRQ |
SSISR_RUIRQ, 0);
/* Add/remove more data */
strm->transfer(ssi, strm);
/* Resume */
rz_ssi_start(ssi, strm);
}
}
if (!strm->running)
return IRQ_HANDLED;
/* tx data empty */
if (irq == ssi->irq_tx)
strm->transfer(ssi, &ssi->playback);
/* rx data full */
if (irq == ssi->irq_rx) {
strm->transfer(ssi, &ssi->capture);
rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
}
if (irq == ssi->irq_rt) {
struct snd_pcm_substream *substream = strm->substream;
if (rz_ssi_stream_is_play(ssi, substream)) {
strm->transfer(ssi, &ssi->playback);
} else {
strm->transfer(ssi, &ssi->capture);
rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
}
}
return IRQ_HANDLED;
}
static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
struct dma_chan *dma_ch, bool is_play)
{
struct dma_slave_config cfg;
memset(&cfg, 0, sizeof(cfg));
cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
cfg.dst_addr = ssi->phys + SSIFTDR;
cfg.src_addr = ssi->phys + SSIFRDR;
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
return dmaengine_slave_config(dma_ch, &cfg);
}
static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
struct rz_ssi_stream *strm)
{
struct snd_pcm_substream *substream = strm->substream;
struct dma_async_tx_descriptor *desc;
struct snd_pcm_runtime *runtime;
enum dma_transfer_direction dir;
u32 dma_paddr, dma_size;
int amount;
if (!rz_ssi_stream_is_valid(ssi, strm))
return -EINVAL;
runtime = substream->runtime;
if (runtime->state == SNDRV_PCM_STATE_DRAINING)
/*
* Stream is ending, so do not queue up any more DMA
* transfers otherwise we play partial sound clips
* because we can't shut off the DMA quick enough.
*/
return 0;
dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
/* Always transfer 1 period */
amount = runtime->period_size;
/* DMA physical address and size */
dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
strm->dma_buffer_pos);
dma_size = frames_to_bytes(runtime, amount);
desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
dir,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
return -ENOMEM;
}
desc->callback = rz_ssi_dma_complete;
desc->callback_param = strm;
if (dmaengine_submit(desc) < 0) {
dev_err(ssi->dev, "dmaengine_submit() fail\n");
return -EIO;
}
/* Update DMA pointer */
strm->dma_buffer_pos += amount;
if (strm->dma_buffer_pos >= runtime->buffer_size)
strm->dma_buffer_pos = 0;
/* Start DMA */
dma_async_issue_pending(strm->dma_ch);
return 0;
}
static void rz_ssi_dma_complete(void *data)
{
struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
if (!strm->running || !strm->substream || !strm->substream->runtime)
return;
/* Note that next DMA transaction has probably already started */
rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
/* Queue up another DMA transaction */
rz_ssi_dma_transfer(strm->priv, strm);
}
static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
{
if (ssi->playback.dma_ch) {
dma_release_channel(ssi->playback.dma_ch);
ssi->playback.dma_ch = NULL;
if (ssi->dma_rt)
ssi->dma_rt = false;
}
if (ssi->capture.dma_ch) {
dma_release_channel(ssi->capture.dma_ch);
ssi->capture.dma_ch = NULL;
}
}
static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
{
ssi->playback.dma_ch = dma_request_chan(dev, "tx");
if (IS_ERR(ssi->playback.dma_ch))
ssi->playback.dma_ch = NULL;
ssi->capture.dma_ch = dma_request_chan(dev, "rx");
if (IS_ERR(ssi->capture.dma_ch))
ssi->capture.dma_ch = NULL;
if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
ssi->playback.dma_ch = dma_request_chan(dev, "rt");
if (IS_ERR(ssi->playback.dma_ch)) {
ssi->playback.dma_ch = NULL;
goto no_dma;
}
ssi->dma_rt = true;
}
if (!rz_ssi_is_dma_enabled(ssi))
goto no_dma;
if (ssi->playback.dma_ch &&
(rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
goto no_dma;
if (ssi->capture.dma_ch &&
(rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0))
goto no_dma;
return 0;
no_dma:
rz_ssi_release_dma_channels(ssi);
return -ENODEV;
}
static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
int ret = 0, i, num_transfer = 1;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
/* Soft Reset */
rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
udelay(5);
rz_ssi_stream_init(strm, substream);
if (ssi->dma_rt) {
bool is_playback;
is_playback = rz_ssi_stream_is_play(ssi, substream);
ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
is_playback);
/* Fallback to pio */
if (ret < 0) {
ssi->playback.transfer = rz_ssi_pio_send;
ssi->capture.transfer = rz_ssi_pio_recv;
rz_ssi_release_dma_channels(ssi);
}
}
/* For DMA, queue up multiple DMA descriptors */
if (rz_ssi_is_dma_enabled(ssi))
num_transfer = 4;
for (i = 0; i < num_transfer; i++) {
ret = strm->transfer(ssi, strm);
if (ret)
goto done;
}
ret = rz_ssi_start(ssi, strm);
break;
case SNDRV_PCM_TRIGGER_STOP:
rz_ssi_stop(ssi, strm);
rz_ssi_stream_quit(ssi, strm);
break;
}
done:
return ret;
}
static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
break;
default:
dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
return -EINVAL;
}
/*
* set clock polarity
*
* "normal" BCLK = Signal is available at rising edge of BCLK
* "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
ssi->bckp_rise = false;
ssi->lrckp_fsync_fall = false;
break;
case SND_SOC_DAIFMT_NB_IF:
ssi->bckp_rise = false;
ssi->lrckp_fsync_fall = true;
break;
case SND_SOC_DAIFMT_IB_NF:
ssi->bckp_rise = true;
ssi->lrckp_fsync_fall = false;
break;
case SND_SOC_DAIFMT_IB_IF:
ssi->bckp_rise = true;
ssi->lrckp_fsync_fall = true;
break;
default:
return -EINVAL;
}
/* only i2s support */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
default:
dev_err(ssi->dev, "Only I2S mode is supported.\n");
return -EINVAL;
}
return 0;
}
static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
unsigned int sample_bits = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
unsigned int channels = params_channels(params);
if (sample_bits != 16) {
dev_err(ssi->dev, "Unsupported sample width: %d\n",
sample_bits);
return -EINVAL;
}
if (channels != 2) {
dev_err(ssi->dev, "Number of channels not matched: %d\n",
channels);
return -EINVAL;
}
return rz_ssi_clk_setup(ssi, params_rate(params),
params_channels(params));
}
static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
.trigger = rz_ssi_dai_trigger,
.set_fmt = rz_ssi_dai_set_fmt,
.hw_params = rz_ssi_dai_hw_params,
};
static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID,
.buffer_bytes_max = PREALLOC_BUFFER,
.period_bytes_min = 32,
.period_bytes_max = 8192,
.channels_min = SSI_CHAN_MIN,
.channels_max = SSI_CHAN_MAX,
.periods_min = 1,
.periods_max = 32,
.fifo_size = 32 * 2,
};
static int rz_ssi_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
return snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
}
static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_dai *dai = rz_ssi_get_dai(substream);
struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
return strm->buffer_pos;
}
static int rz_ssi_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
rtd->card->snd_card->dev,
PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
return 0;
}
static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
{
.name = "rz-ssi-dai",
.playback = {
.rates = SSI_RATES,
.formats = SSI_FMTS,
.channels_min = SSI_CHAN_MIN,
.channels_max = SSI_CHAN_MAX,
},
.capture = {
.rates = SSI_RATES,
.formats = SSI_FMTS,
.channels_min = SSI_CHAN_MIN,
.channels_max = SSI_CHAN_MAX,
},
.ops = &rz_ssi_dai_ops,
},
};
static const struct snd_soc_component_driver rz_ssi_soc_component = {
.name = "rz-ssi",
.open = rz_ssi_pcm_open,
.pointer = rz_ssi_pcm_pointer,
.pcm_construct = rz_ssi_pcm_new,
.legacy_dai_naming = 1,
};
static int rz_ssi_probe(struct platform_device *pdev)
{
struct rz_ssi_priv *ssi;
struct clk *audio_clk;
struct resource *res;
int ret;
ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
if (!ssi)
return -ENOMEM;
ssi->pdev = pdev;
ssi->dev = &pdev->dev;
ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(ssi->base))
return PTR_ERR(ssi->base);
ssi->phys = res->start;
ssi->clk = devm_clk_get(&pdev->dev, "ssi");
if (IS_ERR(ssi->clk))
return PTR_ERR(ssi->clk);
ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr");
if (IS_ERR(ssi->sfr_clk))
return PTR_ERR(ssi->sfr_clk);
audio_clk = devm_clk_get(&pdev->dev, "audio_clk1");
if (IS_ERR(audio_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
"no audio clk1");
ssi->audio_clk_1 = clk_get_rate(audio_clk);
audio_clk = devm_clk_get(&pdev->dev, "audio_clk2");
if (IS_ERR(audio_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
"no audio clk2");
ssi->audio_clk_2 = clk_get_rate(audio_clk);
if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
return dev_err_probe(&pdev->dev, -EINVAL,
"no audio clk1 or audio clk2");
ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
/* Detect DMA support */
ret = rz_ssi_dma_request(ssi, &pdev->dev);
if (ret < 0) {
dev_warn(&pdev->dev, "DMA not available, using PIO\n");
ssi->playback.transfer = rz_ssi_pio_send;
ssi->capture.transfer = rz_ssi_pio_recv;
} else {
dev_info(&pdev->dev, "DMA enabled");
ssi->playback.transfer = rz_ssi_dma_transfer;
ssi->capture.transfer = rz_ssi_dma_transfer;
}
ssi->playback.priv = ssi;
ssi->capture.priv = ssi;
spin_lock_init(&ssi->lock);
dev_set_drvdata(&pdev->dev, ssi);
/* Error Interrupt */
ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
if (ssi->irq_int < 0) {
rz_ssi_release_dma_channels(ssi);
return ssi->irq_int;
}
ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
0, dev_name(&pdev->dev), ssi);
if (ret < 0) {
rz_ssi_release_dma_channels(ssi);
return dev_err_probe(&pdev->dev, ret,
"irq request error (int_req)\n");
}
if (!rz_ssi_is_dma_enabled(ssi)) {
/* Tx and Rx interrupts (pio only) */
ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
if (ssi->irq_rt < 0)
return ssi->irq_rt;
ret = devm_request_irq(&pdev->dev, ssi->irq_rt,
&rz_ssi_interrupt, 0,
dev_name(&pdev->dev), ssi);
if (ret < 0)
return dev_err_probe(&pdev->dev, ret,
"irq request error (dma_tx)\n");
} else {
if (ssi->irq_tx < 0)
return ssi->irq_tx;
if (ssi->irq_rx < 0)
return ssi->irq_rx;
ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
&rz_ssi_interrupt, 0,
dev_name(&pdev->dev), ssi);
if (ret < 0)
return dev_err_probe(&pdev->dev, ret,
"irq request error (dma_tx)\n");
ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
&rz_ssi_interrupt, 0,
dev_name(&pdev->dev), ssi);
if (ret < 0)
return dev_err_probe(&pdev->dev, ret,
"irq request error (dma_rx)\n");
}
}
ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(ssi->rstc)) {
ret = PTR_ERR(ssi->rstc);
goto err_reset;
}
reset_control_deassert(ssi->rstc);
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n");
goto err_pm;
}
ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component,
rz_ssi_soc_dai,
ARRAY_SIZE(rz_ssi_soc_dai));
if (ret < 0) {
dev_err(&pdev->dev, "failed to register snd component\n");
goto err_snd_soc;
}
return 0;
err_snd_soc:
pm_runtime_put(ssi->dev);
err_pm:
pm_runtime_disable(ssi->dev);
reset_control_assert(ssi->rstc);
err_reset:
rz_ssi_release_dma_channels(ssi);
return ret;
}
static void rz_ssi_remove(struct platform_device *pdev)
{
struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
rz_ssi_release_dma_channels(ssi);
pm_runtime_put(ssi->dev);
pm_runtime_disable(ssi->dev);
reset_control_assert(ssi->rstc);
}
static const struct of_device_id rz_ssi_of_match[] = {
{ .compatible = "renesas,rz-ssi", },
{/* Sentinel */},
};
MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
static struct platform_driver rz_ssi_driver = {
.driver = {
.name = "rz-ssi-pcm-audio",
.of_match_table = rz_ssi_of_match,
},
.probe = rz_ssi_probe,
.remove_new = rz_ssi_remove,
};
module_platform_driver(rz_ssi_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
MODULE_AUTHOR("Biju Das <[email protected]>");
| linux-master | sound/soc/sh/rz-ssi.c |
// SPDX-License-Identifier: GPL-2.0
//
// Hitachi Audio Controller (AC97) support for SH7760/SH7780
//
// Copyright (c) 2007 Manuel Lauss <[email protected]>
//
// dont forget to set IPSEL/OMSEL register bits (in your board code) to
// enable HAC output pins!
/* BIG FAT FIXME: although the SH7760 has 2 independent AC97 units, only
* the FIRST can be used since ASoC does not pass any information to the
* ac97_read/write() functions regarding WHICH unit to use. You'll have
* to edit the code a bit to use the other AC97 unit. --mlau
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
/* regs and bits */
#define HACCR 0x08
#define HACCSAR 0x20
#define HACCSDR 0x24
#define HACPCML 0x28
#define HACPCMR 0x2C
#define HACTIER 0x50
#define HACTSR 0x54
#define HACRIER 0x58
#define HACRSR 0x5C
#define HACACR 0x60
#define CR_CR (1 << 15) /* "codec-ready" indicator */
#define CR_CDRT (1 << 11) /* cold reset */
#define CR_WMRT (1 << 10) /* warm reset */
#define CR_B9 (1 << 9) /* the mysterious "bit 9" */
#define CR_ST (1 << 5) /* AC97 link start bit */
#define CSAR_RD (1 << 19) /* AC97 data read bit */
#define CSAR_WR (0)
#define TSR_CMDAMT (1 << 31)
#define TSR_CMDDMT (1 << 30)
#define RSR_STARY (1 << 22)
#define RSR_STDRY (1 << 21)
#define ACR_DMARX16 (1 << 30)
#define ACR_DMATX16 (1 << 29)
#define ACR_TX12ATOM (1 << 26)
#define ACR_DMARX20 ((1 << 24) | (1 << 22))
#define ACR_DMATX20 ((1 << 23) | (1 << 21))
#define CSDR_SHIFT 4
#define CSDR_MASK (0xffff << CSDR_SHIFT)
#define CSAR_SHIFT 12
#define CSAR_MASK (0x7f << CSAR_SHIFT)
#define AC97_WRITE_RETRY 1
#define AC97_READ_RETRY 5
/* manual-suggested AC97 codec access timeouts (us) */
#define TMO_E1 500 /* 21 < E1 < 1000 */
#define TMO_E2 13 /* 13 < E2 */
#define TMO_E3 21 /* 21 < E3 */
#define TMO_E4 500 /* 21 < E4 < 1000 */
struct hac_priv {
unsigned long mmio; /* HAC base address */
} hac_cpu_data[] = {
#if defined(CONFIG_CPU_SUBTYPE_SH7760)
{
.mmio = 0xFE240000,
},
{
.mmio = 0xFE250000,
},
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
{
.mmio = 0xFFE40000,
},
#else
#error "Unsupported SuperH SoC"
#endif
};
#define HACREG(reg) (*(unsigned long *)(hac->mmio + (reg)))
/*
* AC97 read/write flow as outlined in the SH7760 manual (pages 903-906)
*/
static int hac_get_codec_data(struct hac_priv *hac, unsigned short r,
unsigned short *v)
{
unsigned int to1, to2, i;
unsigned short adr;
for (i = AC97_READ_RETRY; i; i--) {
*v = 0;
/* wait for HAC to receive something from the codec */
for (to1 = TMO_E4;
to1 && !(HACREG(HACRSR) & RSR_STARY);
--to1)
udelay(1);
for (to2 = TMO_E4;
to2 && !(HACREG(HACRSR) & RSR_STDRY);
--to2)
udelay(1);
if (!to1 && !to2)
return 0; /* codec comm is down */
adr = ((HACREG(HACCSAR) & CSAR_MASK) >> CSAR_SHIFT);
*v = ((HACREG(HACCSDR) & CSDR_MASK) >> CSDR_SHIFT);
HACREG(HACRSR) &= ~(RSR_STDRY | RSR_STARY);
if (r == adr)
break;
/* manual says: wait at least 21 usec before retrying */
udelay(21);
}
HACREG(HACRSR) &= ~(RSR_STDRY | RSR_STARY);
return i;
}
static unsigned short hac_read_codec_aux(struct hac_priv *hac,
unsigned short reg)
{
unsigned short val;
unsigned int i, to;
for (i = AC97_READ_RETRY; i; i--) {
/* send_read_request */
local_irq_disable();
HACREG(HACTSR) &= ~(TSR_CMDAMT);
HACREG(HACCSAR) = (reg << CSAR_SHIFT) | CSAR_RD;
local_irq_enable();
for (to = TMO_E3;
to && !(HACREG(HACTSR) & TSR_CMDAMT);
--to)
udelay(1);
HACREG(HACTSR) &= ~TSR_CMDAMT;
val = 0;
if (hac_get_codec_data(hac, reg, &val) != 0)
break;
}
return i ? val : ~0;
}
static void hac_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
unsigned short val)
{
int unit_id = 0 /* ac97->private_data */;
struct hac_priv *hac = &hac_cpu_data[unit_id];
unsigned int i, to;
/* write_codec_aux */
for (i = AC97_WRITE_RETRY; i; i--) {
/* send_write_request */
local_irq_disable();
HACREG(HACTSR) &= ~(TSR_CMDDMT | TSR_CMDAMT);
HACREG(HACCSDR) = (val << CSDR_SHIFT);
HACREG(HACCSAR) = (reg << CSAR_SHIFT) & (~CSAR_RD);
local_irq_enable();
/* poll-wait for CMDAMT and CMDDMT */
for (to = TMO_E1;
to && !(HACREG(HACTSR) & (TSR_CMDAMT|TSR_CMDDMT));
--to)
udelay(1);
HACREG(HACTSR) &= ~(TSR_CMDAMT | TSR_CMDDMT);
if (to)
break;
/* timeout, try again */
}
}
static unsigned short hac_ac97_read(struct snd_ac97 *ac97,
unsigned short reg)
{
int unit_id = 0 /* ac97->private_data */;
struct hac_priv *hac = &hac_cpu_data[unit_id];
return hac_read_codec_aux(hac, reg);
}
static void hac_ac97_warmrst(struct snd_ac97 *ac97)
{
int unit_id = 0 /* ac97->private_data */;
struct hac_priv *hac = &hac_cpu_data[unit_id];
unsigned int tmo;
HACREG(HACCR) = CR_WMRT | CR_ST | CR_B9;
msleep(10);
HACREG(HACCR) = CR_ST | CR_B9;
for (tmo = 1000; (tmo > 0) && !(HACREG(HACCR) & CR_CR); tmo--)
udelay(1);
if (!tmo)
printk(KERN_INFO "hac: reset: AC97 link down!\n");
/* settings this bit lets us have a conversation with codec */
HACREG(HACACR) |= ACR_TX12ATOM;
}
static void hac_ac97_coldrst(struct snd_ac97 *ac97)
{
int unit_id = 0 /* ac97->private_data */;
struct hac_priv *hac;
hac = &hac_cpu_data[unit_id];
HACREG(HACCR) = 0;
HACREG(HACCR) = CR_CDRT | CR_ST | CR_B9;
msleep(10);
hac_ac97_warmrst(ac97);
}
static struct snd_ac97_bus_ops hac_ac97_ops = {
.read = hac_ac97_read,
.write = hac_ac97_write,
.reset = hac_ac97_coldrst,
.warm_reset = hac_ac97_warmrst,
};
static int hac_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct hac_priv *hac = &hac_cpu_data[dai->id];
int d = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
switch (params->msbits) {
case 16:
HACREG(HACACR) |= d ? ACR_DMARX16 : ACR_DMATX16;
HACREG(HACACR) &= d ? ~ACR_DMARX20 : ~ACR_DMATX20;
break;
case 20:
HACREG(HACACR) &= d ? ~ACR_DMARX16 : ~ACR_DMATX16;
HACREG(HACACR) |= d ? ACR_DMARX20 : ACR_DMATX20;
break;
default:
pr_debug("hac: invalid depth %d bit\n", params->msbits);
return -EINVAL;
break;
}
return 0;
}
#define AC97_RATES \
SNDRV_PCM_RATE_8000_192000
#define AC97_FMTS \
SNDRV_PCM_FMTBIT_S16_LE
static const struct snd_soc_dai_ops hac_dai_ops = {
.hw_params = hac_hw_params,
};
static struct snd_soc_dai_driver sh4_hac_dai[] = {
{
.name = "hac-dai.0",
.playback = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &hac_dai_ops,
},
#ifdef CONFIG_CPU_SUBTYPE_SH7760
{
.name = "hac-dai.1",
.id = 1,
.playback = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &hac_dai_ops,
},
#endif
};
static const struct snd_soc_component_driver sh4_hac_component = {
.name = "sh4-hac",
.legacy_dai_naming = 1,
};
static int hac_soc_platform_probe(struct platform_device *pdev)
{
int ret;
ret = snd_soc_set_ac97_ops(&hac_ac97_ops);
if (ret != 0)
return ret;
return devm_snd_soc_register_component(&pdev->dev, &sh4_hac_component,
sh4_hac_dai, ARRAY_SIZE(sh4_hac_dai));
}
static void hac_soc_platform_remove(struct platform_device *pdev)
{
snd_soc_set_ac97_ops(NULL);
}
static struct platform_driver hac_pcm_driver = {
.driver = {
.name = "hac-pcm-audio",
},
.probe = hac_soc_platform_probe,
.remove_new = hac_soc_platform_remove,
};
module_platform_driver(hac_pcm_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("SuperH onchip HAC (AC97) audio driver");
MODULE_AUTHOR("Manuel Lauss <[email protected]>");
| linux-master | sound/soc/sh/hac.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC driver for Migo-R
//
// Copyright (C) 2009-2010 Guennadi Liakhovetski <[email protected]>
#include <linux/clkdev.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/module.h>
#include <asm/clock.h>
#include <cpu/sh7722.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include "../codecs/wm8978.h"
#include "siu.h"
/* Default 8000Hz sampling frequency */
static unsigned long codec_freq = 8000 * 512;
static unsigned int use_count;
/* External clock, sourced from the codec at the SIUMCKB pin */
static unsigned long siumckb_recalc(struct clk *clk)
{
return codec_freq;
}
static struct sh_clk_ops siumckb_clk_ops = {
.recalc = siumckb_recalc,
};
static struct clk siumckb_clk = {
.ops = &siumckb_clk_ops,
.rate = 0, /* initialised at run-time */
};
static struct clk_lookup *siumckb_lookup;
static int migor_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
unsigned int rate = params_rate(params);
ret = snd_soc_dai_set_sysclk(codec_dai, WM8978_PLL, 13000000,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_clkdiv(codec_dai, WM8978_OPCLKRATE, rate * 512);
if (ret < 0)
return ret;
codec_freq = rate * 512;
/*
* This propagates the parent frequency change to children and
* recalculates the frequency table
*/
clk_set_rate(&siumckb_clk, codec_freq);
dev_dbg(codec_dai->dev, "%s: configure %luHz\n", __func__, codec_freq);
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), SIU_CLKB_EXT,
codec_freq / 2, SND_SOC_CLOCK_IN);
if (!ret)
use_count++;
return ret;
}
static int migor_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
if (use_count) {
use_count--;
if (!use_count)
snd_soc_dai_set_sysclk(codec_dai, WM8978_PLL, 0,
SND_SOC_CLOCK_IN);
} else {
dev_dbg(codec_dai->dev, "Unbalanced hw_free!\n");
}
return 0;
}
static const struct snd_soc_ops migor_dai_ops = {
.hw_params = migor_hw_params,
.hw_free = migor_hw_free,
};
static const struct snd_soc_dapm_widget migor_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Onboard Microphone", NULL),
SND_SOC_DAPM_MIC("External Microphone", NULL),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* Headphone output connected to LHP/RHP, enable OUT4 for VMID */
{ "Headphone", NULL, "OUT4 VMID" },
{ "OUT4 VMID", NULL, "LHP" },
{ "OUT4 VMID", NULL, "RHP" },
/* On-board microphone */
{ "RMICN", NULL, "Mic Bias" },
{ "RMICP", NULL, "Mic Bias" },
{ "Mic Bias", NULL, "Onboard Microphone" },
/* External microphone */
{ "LMICN", NULL, "Mic Bias" },
{ "LMICP", NULL, "Mic Bias" },
{ "Mic Bias", NULL, "External Microphone" },
};
/* migor digital audio interface glue - connects codec <--> CPU */
SND_SOC_DAILINK_DEFS(wm8978,
DAILINK_COMP_ARRAY(COMP_CPU("siu-pcm-audio")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8978.0-001a", "wm8978-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("siu-pcm-audio")));
static struct snd_soc_dai_link migor_dai = {
.name = "wm8978",
.stream_name = "WM8978",
.dai_fmt = SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &migor_dai_ops,
SND_SOC_DAILINK_REG(wm8978),
};
/* migor audio machine driver */
static struct snd_soc_card snd_soc_migor = {
.name = "Migo-R",
.owner = THIS_MODULE,
.dai_link = &migor_dai,
.num_links = 1,
.dapm_widgets = migor_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(migor_dapm_widgets),
.dapm_routes = audio_map,
.num_dapm_routes = ARRAY_SIZE(audio_map),
};
static struct platform_device *migor_snd_device;
static int __init migor_init(void)
{
int ret;
ret = clk_register(&siumckb_clk);
if (ret < 0)
return ret;
siumckb_lookup = clkdev_create(&siumckb_clk, "siumckb_clk", NULL);
if (!siumckb_lookup) {
ret = -ENOMEM;
goto eclkdevalloc;
}
/* Port number used on this machine: port B */
migor_snd_device = platform_device_alloc("soc-audio", 1);
if (!migor_snd_device) {
ret = -ENOMEM;
goto epdevalloc;
}
platform_set_drvdata(migor_snd_device, &snd_soc_migor);
ret = platform_device_add(migor_snd_device);
if (ret)
goto epdevadd;
return 0;
epdevadd:
platform_device_put(migor_snd_device);
epdevalloc:
clkdev_drop(siumckb_lookup);
eclkdevalloc:
clk_unregister(&siumckb_clk);
return ret;
}
static void __exit migor_exit(void)
{
clkdev_drop(siumckb_lookup);
clk_unregister(&siumckb_clk);
platform_device_unregister(migor_snd_device);
}
module_init(migor_init);
module_exit(migor_exit);
MODULE_AUTHOR("Guennadi Liakhovetski <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC Migor");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/sh/migor.c |
// SPDX-License-Identifier: GPL-2.0
//
// Serial Sound Interface (I2S) support for SH7760/SH7780
//
// Copyright (c) 2007 Manuel Lauss <[email protected]>
//
// dont forget to set IPSEL/OMSEL register bits (in your board code) to
// enable SSI output pins!
/*
* LIMITATIONS:
* The SSI unit has only one physical data line, so full duplex is
* impossible. This can be remedied on the SH7760 by using the
* other SSI unit for recording; however the SH7780 has only 1 SSI
* unit, and its pins are shared with the AC97 unit, among others.
*
* FEATURES:
* The SSI features "compressed mode": in this mode it continuously
* streams PCM data over the I2S lines and uses LRCK as a handshake
* signal. Can be used to send compressed data (AC3/DTS) to a DSP.
* The number of bits sent over the wire in a frame can be adjusted
* and can be independent from the actual sample bit depth. This is
* useful to support TDM mode codecs like the AD1939 which have a
* fixed TDM slot size, regardless of sample resolution.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/io.h>
#define SSICR 0x00
#define SSISR 0x04
#define CR_DMAEN (1 << 28)
#define CR_CHNL_SHIFT 22
#define CR_CHNL_MASK (3 << CR_CHNL_SHIFT)
#define CR_DWL_SHIFT 19
#define CR_DWL_MASK (7 << CR_DWL_SHIFT)
#define CR_SWL_SHIFT 16
#define CR_SWL_MASK (7 << CR_SWL_SHIFT)
#define CR_SCK_MASTER (1 << 15) /* bitclock master bit */
#define CR_SWS_MASTER (1 << 14) /* wordselect master bit */
#define CR_SCKP (1 << 13) /* I2Sclock polarity */
#define CR_SWSP (1 << 12) /* LRCK polarity */
#define CR_SPDP (1 << 11)
#define CR_SDTA (1 << 10) /* i2s alignment (msb/lsb) */
#define CR_PDTA (1 << 9) /* fifo data alignment */
#define CR_DEL (1 << 8) /* delay data by 1 i2sclk */
#define CR_BREN (1 << 7) /* clock gating in burst mode */
#define CR_CKDIV_SHIFT 4
#define CR_CKDIV_MASK (7 << CR_CKDIV_SHIFT) /* bitclock divider */
#define CR_MUTE (1 << 3) /* SSI mute */
#define CR_CPEN (1 << 2) /* compressed mode */
#define CR_TRMD (1 << 1) /* transmit/receive select */
#define CR_EN (1 << 0) /* enable SSI */
#define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg)))
struct ssi_priv {
unsigned long mmio;
unsigned long sysclk;
int inuse;
} ssi_cpu_data[] = {
#if defined(CONFIG_CPU_SUBTYPE_SH7760)
{
.mmio = 0xFE680000,
},
{
.mmio = 0xFE690000,
},
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
{
.mmio = 0xFFE70000,
},
#else
#error "Unsupported SuperH SoC"
#endif
};
/*
* track usage of the SSI; it is simplex-only so prevent attempts of
* concurrent playback + capture. FIXME: any locking required?
*/
static int ssi_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
if (ssi->inuse) {
pr_debug("ssi: already in use!\n");
return -EBUSY;
} else
ssi->inuse = 1;
return 0;
}
static void ssi_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
ssi->inuse = 0;
}
static int ssi_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
SSIREG(SSICR) |= CR_DMAEN | CR_EN;
break;
case SNDRV_PCM_TRIGGER_STOP:
SSIREG(SSICR) &= ~(CR_DMAEN | CR_EN);
break;
default:
return -EINVAL;
}
return 0;
}
static int ssi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
unsigned long ssicr = SSIREG(SSICR);
unsigned int bits, channels, swl, recv, i;
channels = params_channels(params);
bits = params->msbits;
recv = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 0 : 1;
pr_debug("ssi_hw_params() enter\nssicr was %08lx\n", ssicr);
pr_debug("bits: %u channels: %u\n", bits, channels);
ssicr &= ~(CR_TRMD | CR_CHNL_MASK | CR_DWL_MASK | CR_PDTA |
CR_SWL_MASK);
/* direction (send/receive) */
if (!recv)
ssicr |= CR_TRMD; /* transmit */
/* channels */
if ((channels < 2) || (channels > 8) || (channels & 1)) {
pr_debug("ssi: invalid number of channels\n");
return -EINVAL;
}
ssicr |= ((channels >> 1) - 1) << CR_CHNL_SHIFT;
/* DATA WORD LENGTH (DWL): databits in audio sample */
i = 0;
switch (bits) {
case 32: ++i;
case 24: ++i;
case 22: ++i;
case 20: ++i;
case 18: ++i;
case 16: ++i;
ssicr |= i << CR_DWL_SHIFT;
case 8: break;
default:
pr_debug("ssi: invalid sample width\n");
return -EINVAL;
}
/*
* SYSTEM WORD LENGTH: size in bits of half a frame over the I2S
* wires. This is usually bits_per_sample x channels/2; i.e. in
* Stereo mode the SWL equals DWL. SWL can be bigger than the
* product of (channels_per_slot x samplebits), e.g. for codecs
* like the AD1939 which only accept 32bit wide TDM slots. For
* "standard" I2S operation we set SWL = chans / 2 * DWL here.
* Waiting for ASoC to get TDM support ;-)
*/
if ((bits > 16) && (bits <= 24)) {
bits = 24; /* these are padded by the SSI */
/*ssicr |= CR_PDTA;*/ /* cpu/data endianness ? */
}
i = 0;
swl = (bits * channels) / 2;
switch (swl) {
case 256: ++i;
case 128: ++i;
case 64: ++i;
case 48: ++i;
case 32: ++i;
case 16: ++i;
ssicr |= i << CR_SWL_SHIFT;
case 8: break;
default:
pr_debug("ssi: invalid system word length computed\n");
return -EINVAL;
}
SSIREG(SSICR) = ssicr;
pr_debug("ssi_hw_params() leave\nssicr is now %08lx\n", ssicr);
return 0;
}
static int ssi_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
unsigned int freq, int dir)
{
struct ssi_priv *ssi = &ssi_cpu_data[cpu_dai->id];
ssi->sysclk = freq;
return 0;
}
/*
* This divider is used to generate the SSI_SCK (I2S bitclock) from the
* clock at the HAC_BIT_CLK ("oversampling clock") pin.
*/
static int ssi_set_clkdiv(struct snd_soc_dai *dai, int did, int div)
{
struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
unsigned long ssicr;
int i;
i = 0;
ssicr = SSIREG(SSICR) & ~CR_CKDIV_MASK;
switch (div) {
case 16: ++i;
case 8: ++i;
case 4: ++i;
case 2: ++i;
SSIREG(SSICR) = ssicr | (i << CR_CKDIV_SHIFT);
case 1: break;
default:
pr_debug("ssi: invalid sck divider %d\n", div);
return -EINVAL;
}
return 0;
}
static int ssi_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
unsigned long ssicr = SSIREG(SSICR);
pr_debug("ssi_set_fmt()\nssicr was 0x%08lx\n", ssicr);
ssicr &= ~(CR_DEL | CR_PDTA | CR_BREN | CR_SWSP | CR_SCKP |
CR_SWS_MASTER | CR_SCK_MASTER);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_RIGHT_J:
ssicr |= CR_DEL | CR_PDTA;
break;
case SND_SOC_DAIFMT_LEFT_J:
ssicr |= CR_DEL;
break;
default:
pr_debug("ssi: unsupported format\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
case SND_SOC_DAIFMT_CONT:
break;
case SND_SOC_DAIFMT_GATED:
ssicr |= CR_BREN;
break;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
ssicr |= CR_SCKP; /* sample data at low clkedge */
break;
case SND_SOC_DAIFMT_NB_IF:
ssicr |= CR_SCKP | CR_SWSP;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
ssicr |= CR_SWSP; /* word select starts low */
break;
default:
pr_debug("ssi: invalid inversion\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
break;
case SND_SOC_DAIFMT_BP_FC:
ssicr |= CR_SCK_MASTER;
break;
case SND_SOC_DAIFMT_BC_FP:
ssicr |= CR_SWS_MASTER;
break;
case SND_SOC_DAIFMT_BP_FP:
ssicr |= CR_SWS_MASTER | CR_SCK_MASTER;
break;
default:
pr_debug("ssi: invalid master/secondary configuration\n");
return -EINVAL;
}
SSIREG(SSICR) = ssicr;
pr_debug("ssi_set_fmt() leave\nssicr is now 0x%08lx\n", ssicr);
return 0;
}
/* the SSI depends on an external clocksource (at HAC_BIT_CLK) even in
* Master mode, so really this is board specific; the SSI can do any
* rate with the right bitclk and divider settings.
*/
#define SSI_RATES \
SNDRV_PCM_RATE_8000_192000
/* the SSI can do 8-32 bit samples, with 8 possible channels */
#define SSI_FMTS \
(SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE | \
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
static const struct snd_soc_dai_ops ssi_dai_ops = {
.startup = ssi_startup,
.shutdown = ssi_shutdown,
.trigger = ssi_trigger,
.hw_params = ssi_hw_params,
.set_sysclk = ssi_set_sysclk,
.set_clkdiv = ssi_set_clkdiv,
.set_fmt = ssi_set_fmt,
};
static struct snd_soc_dai_driver sh4_ssi_dai[] = {
{
.name = "ssi-dai.0",
.playback = {
.rates = SSI_RATES,
.formats = SSI_FMTS,
.channels_min = 2,
.channels_max = 8,
},
.capture = {
.rates = SSI_RATES,
.formats = SSI_FMTS,
.channels_min = 2,
.channels_max = 8,
},
.ops = &ssi_dai_ops,
},
#ifdef CONFIG_CPU_SUBTYPE_SH7760
{
.name = "ssi-dai.1",
.playback = {
.rates = SSI_RATES,
.formats = SSI_FMTS,
.channels_min = 2,
.channels_max = 8,
},
.capture = {
.rates = SSI_RATES,
.formats = SSI_FMTS,
.channels_min = 2,
.channels_max = 8,
},
.ops = &ssi_dai_ops,
},
#endif
};
static const struct snd_soc_component_driver sh4_ssi_component = {
.name = "sh4-ssi",
.legacy_dai_naming = 1,
};
static int sh4_soc_dai_probe(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev, &sh4_ssi_component,
sh4_ssi_dai,
ARRAY_SIZE(sh4_ssi_dai));
}
static struct platform_driver sh4_ssi_driver = {
.driver = {
.name = "sh4-ssi-dai",
},
.probe = sh4_soc_dai_probe,
};
module_platform_driver(sh4_ssi_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("SuperH onchip SSI (I2S) audio driver");
MODULE_AUTHOR("Manuel Lauss <[email protected]>");
| linux-master | sound/soc/sh/ssi.c |
// SPDX-License-Identifier: GPL-2.0
//
// Fifo-attached Serial Interface (FSI) support for SH7724
//
// Copyright (C) 2009 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
//
// Based on ssi.c
// Copyright (c) 2007 Manuel Lauss <[email protected]>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm_runtime.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/scatterlist.h>
#include <linux/sh_dma.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/workqueue.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <sound/sh_fsi.h>
/* PortA/PortB register */
#define REG_DO_FMT 0x0000
#define REG_DOFF_CTL 0x0004
#define REG_DOFF_ST 0x0008
#define REG_DI_FMT 0x000C
#define REG_DIFF_CTL 0x0010
#define REG_DIFF_ST 0x0014
#define REG_CKG1 0x0018
#define REG_CKG2 0x001C
#define REG_DIDT 0x0020
#define REG_DODT 0x0024
#define REG_MUTE_ST 0x0028
#define REG_OUT_DMAC 0x002C
#define REG_OUT_SEL 0x0030
#define REG_IN_DMAC 0x0038
/* master register */
#define MST_CLK_RST 0x0210
#define MST_SOFT_RST 0x0214
#define MST_FIFO_SZ 0x0218
/* core register (depend on FSI version) */
#define A_MST_CTLR 0x0180
#define B_MST_CTLR 0x01A0
#define CPU_INT_ST 0x01F4
#define CPU_IEMSK 0x01F8
#define CPU_IMSK 0x01FC
#define INT_ST 0x0200
#define IEMSK 0x0204
#define IMSK 0x0208
/* DO_FMT */
/* DI_FMT */
#define CR_BWS_MASK (0x3 << 20) /* FSI2 */
#define CR_BWS_24 (0x0 << 20) /* FSI2 */
#define CR_BWS_16 (0x1 << 20) /* FSI2 */
#define CR_BWS_20 (0x2 << 20) /* FSI2 */
#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
#define CR_MONO (0x0 << 4)
#define CR_MONO_D (0x1 << 4)
#define CR_PCM (0x2 << 4)
#define CR_I2S (0x3 << 4)
#define CR_TDM (0x4 << 4)
#define CR_TDM_D (0x5 << 4)
/* OUT_DMAC */
/* IN_DMAC */
#define VDMD_MASK (0x3 << 4)
#define VDMD_FRONT (0x0 << 4) /* Package in front */
#define VDMD_BACK (0x1 << 4) /* Package in back */
#define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
#define DMA_ON (0x1 << 0)
/* DOFF_CTL */
/* DIFF_CTL */
#define IRQ_HALF 0x00100000
#define FIFO_CLR 0x00000001
/* DOFF_ST */
#define ERR_OVER 0x00000010
#define ERR_UNDER 0x00000001
#define ST_ERR (ERR_OVER | ERR_UNDER)
/* CKG1 */
#define ACKMD_MASK 0x00007000
#define BPFMD_MASK 0x00000700
#define DIMD (1 << 4)
#define DOMD (1 << 0)
/* A/B MST_CTLR */
#define BP (1 << 4) /* Fix the signal of Biphase output */
#define SE (1 << 0) /* Fix the master clock */
/* CLK_RST */
#define CRB (1 << 4)
#define CRA (1 << 0)
/* IO SHIFT / MACRO */
#define BI_SHIFT 12
#define BO_SHIFT 8
#define AI_SHIFT 4
#define AO_SHIFT 0
#define AB_IO(param, shift) (param << shift)
/* SOFT_RST */
#define PBSR (1 << 12) /* Port B Software Reset */
#define PASR (1 << 8) /* Port A Software Reset */
#define IR (1 << 4) /* Interrupt Reset */
#define FSISR (1 << 0) /* Software Reset */
/* OUT_SEL (FSI2) */
#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
/* 1: Biphase and serial */
/* FIFO_SZ */
#define FIFO_SZ_MASK 0x7
#define FSI_RATES SNDRV_PCM_RATE_8000_96000
#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
/*
* bus options
*
* 0x000000BA
*
* A : sample widtht 16bit setting
* B : sample widtht 24bit setting
*/
#define SHIFT_16DATA 0
#define SHIFT_24DATA 4
#define PACKAGE_24BITBUS_BACK 0
#define PACKAGE_24BITBUS_FRONT 1
#define PACKAGE_16BITBUS_STREAM 2
#define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
#define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
/*
* FSI driver use below type name for variable
*
* xxx_num : number of data
* xxx_pos : position of data
* xxx_capa : capacity of data
*/
/*
* period/frame/sample image
*
* ex) PCM (2ch)
*
* period pos period pos
* [n] [n + 1]
* |<-------------------- period--------------------->|
* ==|============================================ ... =|==
* | |
* ||<----- frame ----->|<------ frame ----->| ... |
* |+--------------------+--------------------+- ... |
* ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
* |+--------------------+--------------------+- ... |
* ==|============================================ ... =|==
*/
/*
* FSI FIFO image
*
* | |
* | |
* | [ sample ] |
* | [ sample ] |
* | [ sample ] |
* | [ sample ] |
* --> go to codecs
*/
/*
* FSI clock
*
* FSIxCLK [CPG] (ick) -------> |
* |-> FSI_DIV (div)-> FSI2
* FSIxCK [external] (xck) ---> |
*/
/*
* struct
*/
struct fsi_stream_handler;
struct fsi_stream {
/*
* these are initialized by fsi_stream_init()
*/
struct snd_pcm_substream *substream;
int fifo_sample_capa; /* sample capacity of FSI FIFO */
int buff_sample_capa; /* sample capacity of ALSA buffer */
int buff_sample_pos; /* sample position of ALSA buffer */
int period_samples; /* sample number / 1 period */
int period_pos; /* current period position */
int sample_width; /* sample width */
int uerr_num;
int oerr_num;
/*
* bus options
*/
u32 bus_option;
/*
* these are initialized by fsi_handler_init()
*/
struct fsi_stream_handler *handler;
struct fsi_priv *priv;
/*
* these are for DMAEngine
*/
struct dma_chan *chan;
int dma_id;
};
struct fsi_clk {
/* see [FSI clock] */
struct clk *own;
struct clk *xck;
struct clk *ick;
struct clk *div;
int (*set_rate)(struct device *dev,
struct fsi_priv *fsi);
unsigned long rate;
unsigned int count;
};
struct fsi_priv {
void __iomem *base;
phys_addr_t phys;
struct fsi_master *master;
struct fsi_stream playback;
struct fsi_stream capture;
struct fsi_clk clock;
u32 fmt;
int chan_num:16;
unsigned int clk_master:1;
unsigned int clk_cpg:1;
unsigned int spdif:1;
unsigned int enable_stream:1;
unsigned int bit_clk_inv:1;
unsigned int lr_clk_inv:1;
};
struct fsi_stream_handler {
int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
int enable);
};
#define fsi_stream_handler_call(io, func, args...) \
(!(io) ? -ENODEV : \
!((io)->handler->func) ? 0 : \
(io)->handler->func(args))
struct fsi_core {
int ver;
u32 int_st;
u32 iemsk;
u32 imsk;
u32 a_mclk;
u32 b_mclk;
};
struct fsi_master {
void __iomem *base;
struct fsi_priv fsia;
struct fsi_priv fsib;
const struct fsi_core *core;
spinlock_t lock;
};
static inline int fsi_stream_is_play(struct fsi_priv *fsi,
struct fsi_stream *io)
{
return &fsi->playback == io;
}
/*
* basic read write function
*/
static void __fsi_reg_write(u32 __iomem *reg, u32 data)
{
/* valid data area is 24bit */
data &= 0x00ffffff;
__raw_writel(data, reg);
}
static u32 __fsi_reg_read(u32 __iomem *reg)
{
return __raw_readl(reg);
}
static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
{
u32 val = __fsi_reg_read(reg);
val &= ~mask;
val |= data & mask;
__fsi_reg_write(reg, val);
}
#define fsi_reg_write(p, r, d)\
__fsi_reg_write((p->base + REG_##r), d)
#define fsi_reg_read(p, r)\
__fsi_reg_read((p->base + REG_##r))
#define fsi_reg_mask_set(p, r, m, d)\
__fsi_reg_mask_set((p->base + REG_##r), m, d)
#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
{
u32 ret;
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
ret = __fsi_reg_read(master->base + reg);
spin_unlock_irqrestore(&master->lock, flags);
return ret;
}
#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
static void _fsi_master_mask_set(struct fsi_master *master,
u32 reg, u32 mask, u32 data)
{
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
__fsi_reg_mask_set(master->base + reg, mask, data);
spin_unlock_irqrestore(&master->lock, flags);
}
/*
* basic function
*/
static int fsi_version(struct fsi_master *master)
{
return master->core->ver;
}
static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
{
return fsi->master;
}
static int fsi_is_clk_master(struct fsi_priv *fsi)
{
return fsi->clk_master;
}
static int fsi_is_port_a(struct fsi_priv *fsi)
{
return fsi->master->base == fsi->base;
}
static int fsi_is_spdif(struct fsi_priv *fsi)
{
return fsi->spdif;
}
static int fsi_is_enable_stream(struct fsi_priv *fsi)
{
return fsi->enable_stream;
}
static int fsi_is_play(struct snd_pcm_substream *substream)
{
return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
}
static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
return asoc_rtd_to_cpu(rtd, 0);
}
static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
{
struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
if (dai->id == 0)
return &master->fsia;
else
return &master->fsib;
}
static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
{
return fsi_get_priv_frm_dai(fsi_get_dai(substream));
}
static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
{
int is_play = fsi_stream_is_play(fsi, io);
int is_porta = fsi_is_port_a(fsi);
u32 shift;
if (is_porta)
shift = is_play ? AO_SHIFT : AI_SHIFT;
else
shift = is_play ? BO_SHIFT : BI_SHIFT;
return shift;
}
static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
{
return frames * fsi->chan_num;
}
static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
{
return samples / fsi->chan_num;
}
static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
struct fsi_stream *io)
{
int is_play = fsi_stream_is_play(fsi, io);
u32 status;
int frames;
status = is_play ?
fsi_reg_read(fsi, DOFF_ST) :
fsi_reg_read(fsi, DIFF_ST);
frames = 0x1ff & (status >> 8);
return fsi_frame2sample(fsi, frames);
}
static void fsi_count_fifo_err(struct fsi_priv *fsi)
{
u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
u32 istatus = fsi_reg_read(fsi, DIFF_ST);
if (ostatus & ERR_OVER)
fsi->playback.oerr_num++;
if (ostatus & ERR_UNDER)
fsi->playback.uerr_num++;
if (istatus & ERR_OVER)
fsi->capture.oerr_num++;
if (istatus & ERR_UNDER)
fsi->capture.uerr_num++;
fsi_reg_write(fsi, DOFF_ST, 0);
fsi_reg_write(fsi, DIFF_ST, 0);
}
/*
* fsi_stream_xx() function
*/
static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
struct snd_pcm_substream *substream)
{
return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
}
static int fsi_stream_is_working(struct fsi_priv *fsi,
struct fsi_stream *io)
{
struct fsi_master *master = fsi_get_master(fsi);
unsigned long flags;
int ret;
spin_lock_irqsave(&master->lock, flags);
ret = !!(io->substream && io->substream->runtime);
spin_unlock_irqrestore(&master->lock, flags);
return ret;
}
static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
{
return io->priv;
}
static void fsi_stream_init(struct fsi_priv *fsi,
struct fsi_stream *io,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsi_master *master = fsi_get_master(fsi);
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
io->substream = substream;
io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
io->buff_sample_pos = 0;
io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
io->period_pos = 0;
io->sample_width = samples_to_bytes(runtime, 1);
io->bus_option = 0;
io->oerr_num = -1; /* ignore 1st err */
io->uerr_num = -1; /* ignore 1st err */
fsi_stream_handler_call(io, init, fsi, io);
spin_unlock_irqrestore(&master->lock, flags);
}
static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_soc_dai *dai = fsi_get_dai(io->substream);
struct fsi_master *master = fsi_get_master(fsi);
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
if (io->oerr_num > 0)
dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
if (io->uerr_num > 0)
dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
fsi_stream_handler_call(io, quit, fsi, io);
io->substream = NULL;
io->buff_sample_capa = 0;
io->buff_sample_pos = 0;
io->period_samples = 0;
io->period_pos = 0;
io->sample_width = 0;
io->bus_option = 0;
io->oerr_num = 0;
io->uerr_num = 0;
spin_unlock_irqrestore(&master->lock, flags);
}
static int fsi_stream_transfer(struct fsi_stream *io)
{
struct fsi_priv *fsi = fsi_stream_to_priv(io);
if (!fsi)
return -EIO;
return fsi_stream_handler_call(io, transfer, fsi, io);
}
#define fsi_stream_start(fsi, io)\
fsi_stream_handler_call(io, start_stop, fsi, io, 1)
#define fsi_stream_stop(fsi, io)\
fsi_stream_handler_call(io, start_stop, fsi, io, 0)
static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
{
struct fsi_stream *io;
int ret1, ret2;
io = &fsi->playback;
ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
io = &fsi->capture;
ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
if (ret1 < 0)
return ret1;
if (ret2 < 0)
return ret2;
return 0;
}
static int fsi_stream_remove(struct fsi_priv *fsi)
{
struct fsi_stream *io;
int ret1, ret2;
io = &fsi->playback;
ret1 = fsi_stream_handler_call(io, remove, fsi, io);
io = &fsi->capture;
ret2 = fsi_stream_handler_call(io, remove, fsi, io);
if (ret1 < 0)
return ret1;
if (ret2 < 0)
return ret2;
return 0;
}
/*
* format/bus/dma setting
*/
static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
u32 bus, struct device *dev)
{
struct fsi_master *master = fsi_get_master(fsi);
int is_play = fsi_stream_is_play(fsi, io);
u32 fmt = fsi->fmt;
if (fsi_version(master) >= 2) {
u32 dma = 0;
/*
* FSI2 needs DMA/Bus setting
*/
switch (bus) {
case PACKAGE_24BITBUS_FRONT:
fmt |= CR_BWS_24;
dma |= VDMD_FRONT;
dev_dbg(dev, "24bit bus / package in front\n");
break;
case PACKAGE_16BITBUS_STREAM:
fmt |= CR_BWS_16;
dma |= VDMD_STREAM;
dev_dbg(dev, "16bit bus / stream mode\n");
break;
case PACKAGE_24BITBUS_BACK:
default:
fmt |= CR_BWS_24;
dma |= VDMD_BACK;
dev_dbg(dev, "24bit bus / package in back\n");
break;
}
if (is_play)
fsi_reg_write(fsi, OUT_DMAC, dma);
else
fsi_reg_write(fsi, IN_DMAC, dma);
}
if (is_play)
fsi_reg_write(fsi, DO_FMT, fmt);
else
fsi_reg_write(fsi, DI_FMT, fmt);
}
/*
* irq function
*/
static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
{
u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
struct fsi_master *master = fsi_get_master(fsi);
fsi_core_mask_set(master, imsk, data, data);
fsi_core_mask_set(master, iemsk, data, data);
}
static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
{
u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
struct fsi_master *master = fsi_get_master(fsi);
fsi_core_mask_set(master, imsk, data, 0);
fsi_core_mask_set(master, iemsk, data, 0);
}
static u32 fsi_irq_get_status(struct fsi_master *master)
{
return fsi_core_read(master, int_st);
}
static void fsi_irq_clear_status(struct fsi_priv *fsi)
{
u32 data = 0;
struct fsi_master *master = fsi_get_master(fsi);
data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
/* clear interrupt factor */
fsi_core_mask_set(master, int_st, data, 0);
}
/*
* SPDIF master clock function
*
* These functions are used later FSI2
*/
static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
{
struct fsi_master *master = fsi_get_master(fsi);
u32 mask, val;
mask = BP | SE;
val = enable ? mask : 0;
fsi_is_port_a(fsi) ?
fsi_core_mask_set(master, a_mclk, mask, val) :
fsi_core_mask_set(master, b_mclk, mask, val);
}
/*
* clock function
*/
static int fsi_clk_init(struct device *dev,
struct fsi_priv *fsi,
int xck,
int ick,
int div,
int (*set_rate)(struct device *dev,
struct fsi_priv *fsi))
{
struct fsi_clk *clock = &fsi->clock;
int is_porta = fsi_is_port_a(fsi);
clock->xck = NULL;
clock->ick = NULL;
clock->div = NULL;
clock->rate = 0;
clock->count = 0;
clock->set_rate = set_rate;
clock->own = devm_clk_get(dev, NULL);
if (IS_ERR(clock->own))
return -EINVAL;
/* external clock */
if (xck) {
clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
if (IS_ERR(clock->xck)) {
dev_err(dev, "can't get xck clock\n");
return -EINVAL;
}
if (clock->xck == clock->own) {
dev_err(dev, "cpu doesn't support xck clock\n");
return -EINVAL;
}
}
/* FSIACLK/FSIBCLK */
if (ick) {
clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
if (IS_ERR(clock->ick)) {
dev_err(dev, "can't get ick clock\n");
return -EINVAL;
}
if (clock->ick == clock->own) {
dev_err(dev, "cpu doesn't support ick clock\n");
return -EINVAL;
}
}
/* FSI-DIV */
if (div) {
clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
if (IS_ERR(clock->div)) {
dev_err(dev, "can't get div clock\n");
return -EINVAL;
}
if (clock->div == clock->own) {
dev_err(dev, "cpu doesn't support div clock\n");
return -EINVAL;
}
}
return 0;
}
#define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
{
fsi->clock.rate = rate;
}
static int fsi_clk_is_valid(struct fsi_priv *fsi)
{
return fsi->clock.set_rate &&
fsi->clock.rate;
}
static int fsi_clk_enable(struct device *dev,
struct fsi_priv *fsi)
{
struct fsi_clk *clock = &fsi->clock;
int ret = -EINVAL;
if (!fsi_clk_is_valid(fsi))
return ret;
if (0 == clock->count) {
ret = clock->set_rate(dev, fsi);
if (ret < 0) {
fsi_clk_invalid(fsi);
return ret;
}
ret = clk_enable(clock->xck);
if (ret)
goto err;
ret = clk_enable(clock->ick);
if (ret)
goto disable_xck;
ret = clk_enable(clock->div);
if (ret)
goto disable_ick;
clock->count++;
}
return ret;
disable_ick:
clk_disable(clock->ick);
disable_xck:
clk_disable(clock->xck);
err:
return ret;
}
static int fsi_clk_disable(struct device *dev,
struct fsi_priv *fsi)
{
struct fsi_clk *clock = &fsi->clock;
if (!fsi_clk_is_valid(fsi))
return -EINVAL;
if (1 == clock->count--) {
clk_disable(clock->xck);
clk_disable(clock->ick);
clk_disable(clock->div);
}
return 0;
}
static int fsi_clk_set_ackbpf(struct device *dev,
struct fsi_priv *fsi,
int ackmd, int bpfmd)
{
u32 data = 0;
/* check ackmd/bpfmd relationship */
if (bpfmd > ackmd) {
dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
return -EINVAL;
}
/* ACKMD */
switch (ackmd) {
case 512:
data |= (0x0 << 12);
break;
case 256:
data |= (0x1 << 12);
break;
case 128:
data |= (0x2 << 12);
break;
case 64:
data |= (0x3 << 12);
break;
case 32:
data |= (0x4 << 12);
break;
default:
dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
return -EINVAL;
}
/* BPFMD */
switch (bpfmd) {
case 32:
data |= (0x0 << 8);
break;
case 64:
data |= (0x1 << 8);
break;
case 128:
data |= (0x2 << 8);
break;
case 256:
data |= (0x3 << 8);
break;
case 512:
data |= (0x4 << 8);
break;
case 16:
data |= (0x7 << 8);
break;
default:
dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
return -EINVAL;
}
dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
udelay(10);
return 0;
}
static int fsi_clk_set_rate_external(struct device *dev,
struct fsi_priv *fsi)
{
struct clk *xck = fsi->clock.xck;
struct clk *ick = fsi->clock.ick;
unsigned long rate = fsi->clock.rate;
unsigned long xrate;
int ackmd, bpfmd;
int ret = 0;
/* check clock rate */
xrate = clk_get_rate(xck);
if (xrate % rate) {
dev_err(dev, "unsupported clock rate\n");
return -EINVAL;
}
clk_set_parent(ick, xck);
clk_set_rate(ick, xrate);
bpfmd = fsi->chan_num * 32;
ackmd = xrate / rate;
dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
if (ret < 0)
dev_err(dev, "%s failed", __func__);
return ret;
}
static int fsi_clk_set_rate_cpg(struct device *dev,
struct fsi_priv *fsi)
{
struct clk *ick = fsi->clock.ick;
struct clk *div = fsi->clock.div;
unsigned long rate = fsi->clock.rate;
unsigned long target = 0; /* 12288000 or 11289600 */
unsigned long actual, cout;
unsigned long diff, min;
unsigned long best_cout, best_act;
int adj;
int ackmd, bpfmd;
int ret = -EINVAL;
if (!(12288000 % rate))
target = 12288000;
if (!(11289600 % rate))
target = 11289600;
if (!target) {
dev_err(dev, "unsupported rate\n");
return ret;
}
bpfmd = fsi->chan_num * 32;
ackmd = target / rate;
ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
if (ret < 0) {
dev_err(dev, "%s failed", __func__);
return ret;
}
/*
* The clock flow is
*
* [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
*
* But, it needs to find best match of CPG and FSI_DIV
* combination, since it is difficult to generate correct
* frequency of audio clock from ick clock only.
* Because ick is created from its parent clock.
*
* target = rate x [512/256/128/64]fs
* cout = round(target x adjustment)
* actual = cout / adjustment (by FSI-DIV) ~= target
* audio = actual
*/
min = ~0;
best_cout = 0;
best_act = 0;
for (adj = 1; adj < 0xffff; adj++) {
cout = target * adj;
if (cout > 100000000) /* max clock = 100MHz */
break;
/* cout/actual audio clock */
cout = clk_round_rate(ick, cout);
actual = cout / adj;
/* find best frequency */
diff = abs(actual - target);
if (diff < min) {
min = diff;
best_cout = cout;
best_act = actual;
}
}
ret = clk_set_rate(ick, best_cout);
if (ret < 0) {
dev_err(dev, "ick clock failed\n");
return -EIO;
}
ret = clk_set_rate(div, clk_round_rate(div, best_act));
if (ret < 0) {
dev_err(dev, "div clock failed\n");
return -EIO;
}
dev_dbg(dev, "ick/div = %ld/%ld\n",
clk_get_rate(ick), clk_get_rate(div));
return ret;
}
static void fsi_pointer_update(struct fsi_stream *io, int size)
{
io->buff_sample_pos += size;
if (io->buff_sample_pos >=
io->period_samples * (io->period_pos + 1)) {
struct snd_pcm_substream *substream = io->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
io->period_pos++;
if (io->period_pos >= runtime->periods) {
io->buff_sample_pos = 0;
io->period_pos = 0;
}
snd_pcm_period_elapsed(substream);
}
}
/*
* pio data transfer handler
*/
static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
{
int i;
if (fsi_is_enable_stream(fsi)) {
/*
* stream mode
* see
* fsi_pio_push_init()
*/
u32 *buf = (u32 *)_buf;
for (i = 0; i < samples / 2; i++)
fsi_reg_write(fsi, DODT, buf[i]);
} else {
/* normal mode */
u16 *buf = (u16 *)_buf;
for (i = 0; i < samples; i++)
fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
}
}
static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
{
u16 *buf = (u16 *)_buf;
int i;
for (i = 0; i < samples; i++)
*(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
}
static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
{
u32 *buf = (u32 *)_buf;
int i;
for (i = 0; i < samples; i++)
fsi_reg_write(fsi, DODT, *(buf + i));
}
static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
{
u32 *buf = (u32 *)_buf;
int i;
for (i = 0; i < samples; i++)
*(buf + i) = fsi_reg_read(fsi, DIDT);
}
static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_pcm_runtime *runtime = io->substream->runtime;
return runtime->dma_area +
samples_to_bytes(runtime, io->buff_sample_pos);
}
static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
int samples)
{
u8 *buf;
if (!fsi_stream_is_working(fsi, io))
return -EINVAL;
buf = fsi_pio_get_area(fsi, io);
switch (io->sample_width) {
case 2:
run16(fsi, buf, samples);
break;
case 4:
run32(fsi, buf, samples);
break;
default:
return -EINVAL;
}
fsi_pointer_update(io, samples);
return 0;
}
static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
{
int sample_residues; /* samples in FSI fifo */
int sample_space; /* ALSA free samples space */
int samples;
sample_residues = fsi_get_current_fifo_samples(fsi, io);
sample_space = io->buff_sample_capa - io->buff_sample_pos;
samples = min(sample_residues, sample_space);
return fsi_pio_transfer(fsi, io,
fsi_pio_pop16,
fsi_pio_pop32,
samples);
}
static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
{
int sample_residues; /* ALSA residue samples */
int sample_space; /* FSI fifo free samples space */
int samples;
sample_residues = io->buff_sample_capa - io->buff_sample_pos;
sample_space = io->fifo_sample_capa -
fsi_get_current_fifo_samples(fsi, io);
samples = min(sample_residues, sample_space);
return fsi_pio_transfer(fsi, io,
fsi_pio_push16,
fsi_pio_push32,
samples);
}
static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
int enable)
{
struct fsi_master *master = fsi_get_master(fsi);
u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
if (enable)
fsi_irq_enable(fsi, io);
else
fsi_irq_disable(fsi, io);
if (fsi_is_clk_master(fsi))
fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
return 0;
}
static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
{
/*
* we can use 16bit stream mode
* when "playback" and "16bit data"
* and platform allows "stream mode"
* see
* fsi_pio_push16()
*/
if (fsi_is_enable_stream(fsi))
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
else
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
return 0;
}
static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
{
/*
* always 24bit bus, package back when "capture"
*/
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
return 0;
}
static struct fsi_stream_handler fsi_pio_push_handler = {
.init = fsi_pio_push_init,
.transfer = fsi_pio_push,
.start_stop = fsi_pio_start_stop,
};
static struct fsi_stream_handler fsi_pio_pop_handler = {
.init = fsi_pio_pop_init,
.transfer = fsi_pio_pop,
.start_stop = fsi_pio_start_stop,
};
static irqreturn_t fsi_interrupt(int irq, void *data)
{
struct fsi_master *master = data;
u32 int_st = fsi_irq_get_status(master);
/* clear irq status */
fsi_master_mask_set(master, SOFT_RST, IR, 0);
fsi_master_mask_set(master, SOFT_RST, IR, IR);
if (int_st & AB_IO(1, AO_SHIFT))
fsi_stream_transfer(&master->fsia.playback);
if (int_st & AB_IO(1, BO_SHIFT))
fsi_stream_transfer(&master->fsib.playback);
if (int_st & AB_IO(1, AI_SHIFT))
fsi_stream_transfer(&master->fsia.capture);
if (int_st & AB_IO(1, BI_SHIFT))
fsi_stream_transfer(&master->fsib.capture);
fsi_count_fifo_err(&master->fsia);
fsi_count_fifo_err(&master->fsib);
fsi_irq_clear_status(&master->fsia);
fsi_irq_clear_status(&master->fsib);
return IRQ_HANDLED;
}
/*
* dma data transfer handler
*/
static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
{
/*
* 24bit data : 24bit bus / package in back
* 16bit data : 16bit bus / stream mode
*/
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
return 0;
}
static void fsi_dma_complete(void *data)
{
struct fsi_stream *io = (struct fsi_stream *)data;
struct fsi_priv *fsi = fsi_stream_to_priv(io);
fsi_pointer_update(io, io->period_samples);
fsi_count_fifo_err(fsi);
}
static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_soc_dai *dai = fsi_get_dai(io->substream);
struct snd_pcm_substream *substream = io->substream;
struct dma_async_tx_descriptor *desc;
int is_play = fsi_stream_is_play(fsi, io);
enum dma_transfer_direction dir;
int ret = -EIO;
if (is_play)
dir = DMA_MEM_TO_DEV;
else
dir = DMA_DEV_TO_MEM;
desc = dmaengine_prep_dma_cyclic(io->chan,
substream->runtime->dma_addr,
snd_pcm_lib_buffer_bytes(substream),
snd_pcm_lib_period_bytes(substream),
dir,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
goto fsi_dma_transfer_err;
}
desc->callback = fsi_dma_complete;
desc->callback_param = io;
if (dmaengine_submit(desc) < 0) {
dev_err(dai->dev, "tx_submit() fail\n");
goto fsi_dma_transfer_err;
}
dma_async_issue_pending(io->chan);
/*
* FIXME
*
* In DMAEngine case, codec and FSI cannot be started simultaneously
* since FSI is using the scheduler work queue.
* Therefore, in capture case, probably FSI FIFO will have got
* overflow error in this point.
* in that case, DMA cannot start transfer until error was cleared.
*/
if (!is_play) {
if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
fsi_reg_write(fsi, DIFF_ST, 0);
}
}
ret = 0;
fsi_dma_transfer_err:
return ret;
}
static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
int start)
{
struct fsi_master *master = fsi_get_master(fsi);
u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
u32 enable = start ? DMA_ON : 0;
fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
dmaengine_terminate_all(io->chan);
if (fsi_is_clk_master(fsi))
fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
return 0;
}
static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
{
int is_play = fsi_stream_is_play(fsi, io);
#ifdef CONFIG_SUPERH
dma_cap_mask_t mask;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
io->chan = dma_request_channel(mask, shdma_chan_filter,
(void *)io->dma_id);
#else
io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx");
#endif
if (io->chan) {
struct dma_slave_config cfg = {};
int ret;
if (is_play) {
cfg.dst_addr = fsi->phys + REG_DODT;
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
cfg.direction = DMA_MEM_TO_DEV;
} else {
cfg.src_addr = fsi->phys + REG_DIDT;
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
cfg.direction = DMA_DEV_TO_MEM;
}
ret = dmaengine_slave_config(io->chan, &cfg);
if (ret < 0) {
dma_release_channel(io->chan);
io->chan = NULL;
}
}
if (!io->chan) {
/* switch to PIO handler */
if (is_play)
fsi->playback.handler = &fsi_pio_push_handler;
else
fsi->capture.handler = &fsi_pio_pop_handler;
dev_info(dev, "switch handler (dma => pio)\n");
/* probe again */
return fsi_stream_probe(fsi, dev);
}
return 0;
}
static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
{
fsi_stream_stop(fsi, io);
if (io->chan)
dma_release_channel(io->chan);
io->chan = NULL;
return 0;
}
static struct fsi_stream_handler fsi_dma_push_handler = {
.init = fsi_dma_init,
.probe = fsi_dma_probe,
.transfer = fsi_dma_transfer,
.remove = fsi_dma_remove,
.start_stop = fsi_dma_push_start_stop,
};
/*
* dai ops
*/
static void fsi_fifo_init(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
struct fsi_master *master = fsi_get_master(fsi);
int is_play = fsi_stream_is_play(fsi, io);
u32 shift, i;
int frame_capa;
/* get on-chip RAM capacity */
shift = fsi_master_read(master, FIFO_SZ);
shift >>= fsi_get_port_shift(fsi, io);
shift &= FIFO_SZ_MASK;
frame_capa = 256 << shift;
dev_dbg(dev, "fifo = %d words\n", frame_capa);
/*
* The maximum number of sample data varies depending
* on the number of channels selected for the format.
*
* FIFOs are used in 4-channel units in 3-channel mode
* and in 8-channel units in 5- to 7-channel mode
* meaning that more FIFOs than the required size of DPRAM
* are used.
*
* ex) if 256 words of DP-RAM is connected
* 1 channel: 256 (256 x 1 = 256)
* 2 channels: 128 (128 x 2 = 256)
* 3 channels: 64 ( 64 x 3 = 192)
* 4 channels: 64 ( 64 x 4 = 256)
* 5 channels: 32 ( 32 x 5 = 160)
* 6 channels: 32 ( 32 x 6 = 192)
* 7 channels: 32 ( 32 x 7 = 224)
* 8 channels: 32 ( 32 x 8 = 256)
*/
for (i = 1; i < fsi->chan_num; i <<= 1)
frame_capa >>= 1;
dev_dbg(dev, "%d channel %d store\n",
fsi->chan_num, frame_capa);
io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
/*
* set interrupt generation factor
* clear FIFO
*/
if (is_play) {
fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
} else {
fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
}
}
static int fsi_hw_startup(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
u32 data = 0;
/* clock setting */
if (fsi_is_clk_master(fsi))
data = DIMD | DOMD;
fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
/* clock inversion (CKG2) */
data = 0;
if (fsi->bit_clk_inv)
data |= (1 << 0);
if (fsi->lr_clk_inv)
data |= (1 << 4);
if (fsi_is_clk_master(fsi))
data <<= 8;
fsi_reg_write(fsi, CKG2, data);
/* spdif ? */
if (fsi_is_spdif(fsi)) {
fsi_spdif_clk_ctrl(fsi, 1);
fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
}
/*
* get bus settings
*/
data = 0;
switch (io->sample_width) {
case 2:
data = BUSOP_GET(16, io->bus_option);
break;
case 4:
data = BUSOP_GET(24, io->bus_option);
break;
}
fsi_format_bus_setup(fsi, io, data, dev);
/* irq clear */
fsi_irq_disable(fsi, io);
fsi_irq_clear_status(fsi);
/* fifo init */
fsi_fifo_init(fsi, io, dev);
/* start master clock */
if (fsi_is_clk_master(fsi))
return fsi_clk_enable(dev, fsi);
return 0;
}
static int fsi_hw_shutdown(struct fsi_priv *fsi,
struct device *dev)
{
/* stop master clock */
if (fsi_is_clk_master(fsi))
return fsi_clk_disable(dev, fsi);
return 0;
}
static int fsi_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
fsi_clk_invalid(fsi);
return 0;
}
static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
fsi_clk_invalid(fsi);
}
static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
struct fsi_stream *io = fsi_stream_get(fsi, substream);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
fsi_stream_init(fsi, io, substream);
if (!ret)
ret = fsi_hw_startup(fsi, io, dai->dev);
if (!ret)
ret = fsi_stream_start(fsi, io);
if (!ret)
ret = fsi_stream_transfer(io);
break;
case SNDRV_PCM_TRIGGER_STOP:
if (!ret)
ret = fsi_hw_shutdown(fsi, dai->dev);
fsi_stream_stop(fsi, io);
fsi_stream_quit(fsi, io);
break;
}
return ret;
}
static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
{
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
fsi->fmt = CR_I2S;
fsi->chan_num = 2;
break;
case SND_SOC_DAIFMT_LEFT_J:
fsi->fmt = CR_PCM;
fsi->chan_num = 2;
break;
default:
return -EINVAL;
}
return 0;
}
static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
{
struct fsi_master *master = fsi_get_master(fsi);
if (fsi_version(master) < 2)
return -EINVAL;
fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
fsi->chan_num = 2;
return 0;
}
static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
int ret;
/* set clock master audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
break;
case SND_SOC_DAIFMT_BP_FP:
fsi->clk_master = 1; /* cpu is master */
break;
default:
return -EINVAL;
}
/* set clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
fsi->bit_clk_inv = 0;
fsi->lr_clk_inv = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
fsi->bit_clk_inv = 1;
fsi->lr_clk_inv = 0;
break;
case SND_SOC_DAIFMT_IB_IF:
fsi->bit_clk_inv = 1;
fsi->lr_clk_inv = 1;
break;
case SND_SOC_DAIFMT_NB_NF:
default:
fsi->bit_clk_inv = 0;
fsi->lr_clk_inv = 0;
break;
}
if (fsi_is_clk_master(fsi)) {
if (fsi->clk_cpg)
fsi_clk_init(dai->dev, fsi, 0, 1, 1,
fsi_clk_set_rate_cpg);
else
fsi_clk_init(dai->dev, fsi, 1, 1, 0,
fsi_clk_set_rate_external);
}
/* set format */
if (fsi_is_spdif(fsi))
ret = fsi_set_fmt_spdif(fsi);
else
ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return ret;
}
static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
if (fsi_is_clk_master(fsi))
fsi_clk_valid(fsi, params_rate(params));
return 0;
}
/*
* Select below from Sound Card, not auto
* SND_SOC_DAIFMT_CBC_CFC
* SND_SOC_DAIFMT_CBP_CFP
*/
static u64 fsi_dai_formats =
SND_SOC_POSSIBLE_DAIFMT_I2S |
SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
SND_SOC_POSSIBLE_DAIFMT_NB_NF |
SND_SOC_POSSIBLE_DAIFMT_NB_IF |
SND_SOC_POSSIBLE_DAIFMT_IB_NF |
SND_SOC_POSSIBLE_DAIFMT_IB_IF;
static const struct snd_soc_dai_ops fsi_dai_ops = {
.startup = fsi_dai_startup,
.shutdown = fsi_dai_shutdown,
.trigger = fsi_dai_trigger,
.set_fmt = fsi_dai_set_fmt,
.hw_params = fsi_dai_hw_params,
.auto_selectable_formats = &fsi_dai_formats,
.num_auto_selectable_formats = 1,
};
/*
* pcm ops
*/
static const struct snd_pcm_hardware fsi_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID,
.buffer_bytes_max = 64 * 1024,
.period_bytes_min = 32,
.period_bytes_max = 8192,
.periods_min = 1,
.periods_max = 32,
.fifo_size = 256,
};
static int fsi_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
int ret = 0;
snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
return ret;
}
static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
struct fsi_stream *io = fsi_stream_get(fsi, substream);
return fsi_sample2frame(fsi, io->buff_sample_pos);
}
/*
* snd_soc_component
*/
#define PREALLOC_BUFFER (32 * 1024)
#define PREALLOC_BUFFER_MAX (32 * 1024)
static int fsi_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
snd_pcm_set_managed_buffer_all(
rtd->pcm,
SNDRV_DMA_TYPE_DEV,
rtd->card->snd_card->dev,
PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
return 0;
}
/*
* alsa struct
*/
static struct snd_soc_dai_driver fsi_soc_dai[] = {
{
.name = "fsia-dai",
.playback = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &fsi_dai_ops,
},
{
.name = "fsib-dai",
.playback = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &fsi_dai_ops,
},
};
static const struct snd_soc_component_driver fsi_soc_component = {
.name = "fsi",
.open = fsi_pcm_open,
.pointer = fsi_pointer,
.pcm_construct = fsi_pcm_new,
};
/*
* platform function
*/
static void fsi_of_parse(char *name,
struct device_node *np,
struct sh_fsi_port_info *info,
struct device *dev)
{
int i;
char prop[128];
unsigned long flags = 0;
struct {
char *name;
unsigned int val;
} of_parse_property[] = {
{ "spdif-connection", SH_FSI_FMT_SPDIF },
{ "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
{ "use-internal-clock", SH_FSI_CLK_CPG },
};
for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
sprintf(prop, "%s,%s", name, of_parse_property[i].name);
if (of_property_present(np, prop))
flags |= of_parse_property[i].val;
}
info->flags = flags;
dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
}
static void fsi_port_info_init(struct fsi_priv *fsi,
struct sh_fsi_port_info *info)
{
if (info->flags & SH_FSI_FMT_SPDIF)
fsi->spdif = 1;
if (info->flags & SH_FSI_CLK_CPG)
fsi->clk_cpg = 1;
if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
fsi->enable_stream = 1;
}
static void fsi_handler_init(struct fsi_priv *fsi,
struct sh_fsi_port_info *info)
{
fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
fsi->playback.priv = fsi;
fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
fsi->capture.priv = fsi;
if (info->tx_id) {
fsi->playback.dma_id = info->tx_id;
fsi->playback.handler = &fsi_dma_push_handler;
}
}
static const struct fsi_core fsi1_core = {
.ver = 1,
/* Interrupt */
.int_st = INT_ST,
.iemsk = IEMSK,
.imsk = IMSK,
};
static const struct fsi_core fsi2_core = {
.ver = 2,
/* Interrupt */
.int_st = CPU_INT_ST,
.iemsk = CPU_IEMSK,
.imsk = CPU_IMSK,
.a_mclk = A_MST_CTLR,
.b_mclk = B_MST_CTLR,
};
static const struct of_device_id fsi_of_match[] = {
{ .compatible = "renesas,sh_fsi", .data = &fsi1_core},
{ .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
{},
};
MODULE_DEVICE_TABLE(of, fsi_of_match);
static const struct platform_device_id fsi_id_table[] = {
{ "sh_fsi", (kernel_ulong_t)&fsi1_core },
{},
};
MODULE_DEVICE_TABLE(platform, fsi_id_table);
static int fsi_probe(struct platform_device *pdev)
{
struct fsi_master *master;
struct device_node *np = pdev->dev.of_node;
struct sh_fsi_platform_info info;
const struct fsi_core *core;
struct fsi_priv *fsi;
struct resource *res;
unsigned int irq;
int ret;
memset(&info, 0, sizeof(info));
core = NULL;
if (np) {
core = of_device_get_match_data(&pdev->dev);
fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
} else {
const struct platform_device_id *id_entry = pdev->id_entry;
if (id_entry)
core = (struct fsi_core *)id_entry->driver_data;
if (pdev->dev.platform_data)
memcpy(&info, pdev->dev.platform_data, sizeof(info));
}
if (!core) {
dev_err(&pdev->dev, "unknown fsi device\n");
return -ENODEV;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (!res || (int)irq <= 0) {
dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
return -ENODEV;
}
master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
if (!master)
return -ENOMEM;
master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!master->base) {
dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
return -ENXIO;
}
/* master setting */
master->core = core;
spin_lock_init(&master->lock);
/* FSI A setting */
fsi = &master->fsia;
fsi->base = master->base;
fsi->phys = res->start;
fsi->master = master;
fsi_port_info_init(fsi, &info.port_a);
fsi_handler_init(fsi, &info.port_a);
ret = fsi_stream_probe(fsi, &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "FSIA stream probe failed\n");
return ret;
}
/* FSI B setting */
fsi = &master->fsib;
fsi->base = master->base + 0x40;
fsi->phys = res->start + 0x40;
fsi->master = master;
fsi_port_info_init(fsi, &info.port_b);
fsi_handler_init(fsi, &info.port_b);
ret = fsi_stream_probe(fsi, &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "FSIB stream probe failed\n");
goto exit_fsia;
}
pm_runtime_enable(&pdev->dev);
dev_set_drvdata(&pdev->dev, master);
ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
dev_name(&pdev->dev), master);
if (ret) {
dev_err(&pdev->dev, "irq request err\n");
goto exit_fsib;
}
ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component,
fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
if (ret < 0) {
dev_err(&pdev->dev, "cannot snd component register\n");
goto exit_fsib;
}
return ret;
exit_fsib:
pm_runtime_disable(&pdev->dev);
fsi_stream_remove(&master->fsib);
exit_fsia:
fsi_stream_remove(&master->fsia);
return ret;
}
static void fsi_remove(struct platform_device *pdev)
{
struct fsi_master *master;
master = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
fsi_stream_remove(&master->fsia);
fsi_stream_remove(&master->fsib);
}
static void __fsi_suspend(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
if (!fsi_stream_is_working(fsi, io))
return;
fsi_stream_stop(fsi, io);
fsi_hw_shutdown(fsi, dev);
}
static void __fsi_resume(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
if (!fsi_stream_is_working(fsi, io))
return;
fsi_hw_startup(fsi, io, dev);
fsi_stream_start(fsi, io);
}
static int fsi_suspend(struct device *dev)
{
struct fsi_master *master = dev_get_drvdata(dev);
struct fsi_priv *fsia = &master->fsia;
struct fsi_priv *fsib = &master->fsib;
__fsi_suspend(fsia, &fsia->playback, dev);
__fsi_suspend(fsia, &fsia->capture, dev);
__fsi_suspend(fsib, &fsib->playback, dev);
__fsi_suspend(fsib, &fsib->capture, dev);
return 0;
}
static int fsi_resume(struct device *dev)
{
struct fsi_master *master = dev_get_drvdata(dev);
struct fsi_priv *fsia = &master->fsia;
struct fsi_priv *fsib = &master->fsib;
__fsi_resume(fsia, &fsia->playback, dev);
__fsi_resume(fsia, &fsia->capture, dev);
__fsi_resume(fsib, &fsib->playback, dev);
__fsi_resume(fsib, &fsib->capture, dev);
return 0;
}
static const struct dev_pm_ops fsi_pm_ops = {
.suspend = fsi_suspend,
.resume = fsi_resume,
};
static struct platform_driver fsi_driver = {
.driver = {
.name = "fsi-pcm-audio",
.pm = &fsi_pm_ops,
.of_match_table = fsi_of_match,
},
.probe = fsi_probe,
.remove_new = fsi_remove,
.id_table = fsi_id_table,
};
module_platform_driver(fsi_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
MODULE_ALIAS("platform:fsi-pcm-audio");
| linux-master | sound/soc/sh/fsi.c |
// SPDX-License-Identifier: GPL-2.0
//
// Generic AC97 sound support for SH7760
//
// (c) 2007 Manuel Lauss
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <asm/io.h>
#define IPSEL 0xFE400034
SND_SOC_DAILINK_DEFS(ac97,
DAILINK_COMP_ARRAY(COMP_CPU("hac-dai.0")), /* HAC0 */
DAILINK_COMP_ARRAY(COMP_CODEC("ac97-codec", "ac97-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("sh7760-pcm-audio")));
static struct snd_soc_dai_link sh7760_ac97_dai = {
.name = "AC97",
.stream_name = "AC97 HiFi",
SND_SOC_DAILINK_REG(ac97),
};
static struct snd_soc_card sh7760_ac97_soc_machine = {
.name = "SH7760 AC97",
.owner = THIS_MODULE,
.dai_link = &sh7760_ac97_dai,
.num_links = 1,
};
static struct platform_device *sh7760_ac97_snd_device;
static int __init sh7760_ac97_init(void)
{
int ret;
unsigned short ipsel;
/* enable both AC97 controllers in pinmux reg */
ipsel = __raw_readw(IPSEL);
__raw_writew(ipsel | (3 << 10), IPSEL);
ret = -ENOMEM;
sh7760_ac97_snd_device = platform_device_alloc("soc-audio", -1);
if (!sh7760_ac97_snd_device)
goto out;
platform_set_drvdata(sh7760_ac97_snd_device,
&sh7760_ac97_soc_machine);
ret = platform_device_add(sh7760_ac97_snd_device);
if (ret)
platform_device_put(sh7760_ac97_snd_device);
out:
return ret;
}
static void __exit sh7760_ac97_exit(void)
{
platform_device_unregister(sh7760_ac97_snd_device);
}
module_init(sh7760_ac97_init);
module_exit(sh7760_ac97_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Generic SH7760 AC97 sound machine");
MODULE_AUTHOR("Manuel Lauss <[email protected]>");
| linux-master | sound/soc/sh/sh7760-ac97.c |
// SPDX-License-Identifier: GPL-2.0+
//
// siu_pcm.c - ALSA driver for Renesas SH7343, SH7722 SIU peripheral.
//
// Copyright (C) 2009-2010 Guennadi Liakhovetski <[email protected]>
// Copyright (C) 2006 Carlos Munoz <[email protected]>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/control.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/siu.h>
#include "siu.h"
#define DRV_NAME "siu-i2s"
#define GET_MAX_PERIODS(buf_bytes, period_bytes) \
((buf_bytes) / (period_bytes))
#define PERIOD_OFFSET(buf_addr, period_num, period_bytes) \
((buf_addr) + ((period_num) * (period_bytes)))
#define RWF_STM_RD 0x01 /* Read in progress */
#define RWF_STM_WT 0x02 /* Write in progress */
struct siu_port *siu_ports[SIU_PORT_NUM];
/* transfersize is number of u32 dma transfers per period */
static int siu_pcm_stmwrite_stop(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
struct siu_stream *siu_stream = &port_info->playback;
u32 stfifo;
if (!siu_stream->rw_flg)
return -EPERM;
/* output FIFO disable */
stfifo = siu_read32(base + SIU_STFIFO);
siu_write32(base + SIU_STFIFO, stfifo & ~0x0c180c18);
pr_debug("%s: STFIFO %x -> %x\n", __func__,
stfifo, stfifo & ~0x0c180c18);
/* during stmwrite clear */
siu_stream->rw_flg = 0;
return 0;
}
static int siu_pcm_stmwrite_start(struct siu_port *port_info)
{
struct siu_stream *siu_stream = &port_info->playback;
if (siu_stream->rw_flg)
return -EPERM;
/* Current period in buffer */
port_info->playback.cur_period = 0;
/* during stmwrite flag set */
siu_stream->rw_flg = RWF_STM_WT;
/* DMA transfer start */
queue_work(system_highpri_wq, &siu_stream->work);
return 0;
}
static void siu_dma_tx_complete(void *arg)
{
struct siu_stream *siu_stream = arg;
if (!siu_stream->rw_flg)
return;
/* Update completed period count */
if (++siu_stream->cur_period >=
GET_MAX_PERIODS(siu_stream->buf_bytes,
siu_stream->period_bytes))
siu_stream->cur_period = 0;
pr_debug("%s: done period #%d (%u/%u bytes), cookie %d\n",
__func__, siu_stream->cur_period,
siu_stream->cur_period * siu_stream->period_bytes,
siu_stream->buf_bytes, siu_stream->cookie);
queue_work(system_highpri_wq, &siu_stream->work);
/* Notify alsa: a period is done */
snd_pcm_period_elapsed(siu_stream->substream);
}
static int siu_pcm_wr_set(struct siu_port *port_info,
dma_addr_t buff, u32 size)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
struct siu_stream *siu_stream = &port_info->playback;
struct snd_pcm_substream *substream = siu_stream->substream;
struct device *dev = substream->pcm->card->dev;
struct dma_async_tx_descriptor *desc;
dma_cookie_t cookie;
struct scatterlist sg;
u32 stfifo;
sg_init_table(&sg, 1);
sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
size, offset_in_page(buff));
sg_dma_len(&sg) = size;
sg_dma_address(&sg) = buff;
desc = dmaengine_prep_slave_sg(siu_stream->chan,
&sg, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(dev, "Failed to allocate a dma descriptor\n");
return -ENOMEM;
}
desc->callback = siu_dma_tx_complete;
desc->callback_param = siu_stream;
cookie = dmaengine_submit(desc);
if (cookie < 0) {
dev_err(dev, "Failed to submit a dma transfer\n");
return cookie;
}
siu_stream->tx_desc = desc;
siu_stream->cookie = cookie;
dma_async_issue_pending(siu_stream->chan);
/* only output FIFO enable */
stfifo = siu_read32(base + SIU_STFIFO);
siu_write32(base + SIU_STFIFO, stfifo | (port_info->stfifo & 0x0c180c18));
dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
stfifo, stfifo | (port_info->stfifo & 0x0c180c18));
return 0;
}
static int siu_pcm_rd_set(struct siu_port *port_info,
dma_addr_t buff, size_t size)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
struct siu_stream *siu_stream = &port_info->capture;
struct snd_pcm_substream *substream = siu_stream->substream;
struct device *dev = substream->pcm->card->dev;
struct dma_async_tx_descriptor *desc;
dma_cookie_t cookie;
struct scatterlist sg;
u32 stfifo;
dev_dbg(dev, "%s: %u@%llx\n", __func__, size, (unsigned long long)buff);
sg_init_table(&sg, 1);
sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
size, offset_in_page(buff));
sg_dma_len(&sg) = size;
sg_dma_address(&sg) = buff;
desc = dmaengine_prep_slave_sg(siu_stream->chan,
&sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(dev, "Failed to allocate dma descriptor\n");
return -ENOMEM;
}
desc->callback = siu_dma_tx_complete;
desc->callback_param = siu_stream;
cookie = dmaengine_submit(desc);
if (cookie < 0) {
dev_err(dev, "Failed to submit dma descriptor\n");
return cookie;
}
siu_stream->tx_desc = desc;
siu_stream->cookie = cookie;
dma_async_issue_pending(siu_stream->chan);
/* only input FIFO enable */
stfifo = siu_read32(base + SIU_STFIFO);
siu_write32(base + SIU_STFIFO, siu_read32(base + SIU_STFIFO) |
(port_info->stfifo & 0x13071307));
dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
stfifo, stfifo | (port_info->stfifo & 0x13071307));
return 0;
}
static void siu_io_work(struct work_struct *work)
{
struct siu_stream *siu_stream = container_of(work, struct siu_stream,
work);
struct snd_pcm_substream *substream = siu_stream->substream;
struct device *dev = substream->pcm->card->dev;
struct snd_pcm_runtime *rt = substream->runtime;
struct siu_port *port_info = siu_port_info(substream);
dev_dbg(dev, "%s: flags %x\n", __func__, siu_stream->rw_flg);
if (!siu_stream->rw_flg) {
dev_dbg(dev, "%s: stream inactive\n", __func__);
return;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
dma_addr_t buff;
size_t count;
buff = (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
siu_stream->cur_period,
siu_stream->period_bytes);
count = siu_stream->period_bytes;
/* DMA transfer start */
siu_pcm_rd_set(port_info, buff, count);
} else {
siu_pcm_wr_set(port_info,
(dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
siu_stream->cur_period,
siu_stream->period_bytes),
siu_stream->period_bytes);
}
}
/* Capture */
static int siu_pcm_stmread_start(struct siu_port *port_info)
{
struct siu_stream *siu_stream = &port_info->capture;
if (siu_stream->xfer_cnt > 0x1000000)
return -EINVAL;
if (siu_stream->rw_flg)
return -EPERM;
/* Current period in buffer */
siu_stream->cur_period = 0;
/* during stmread flag set */
siu_stream->rw_flg = RWF_STM_RD;
queue_work(system_highpri_wq, &siu_stream->work);
return 0;
}
static int siu_pcm_stmread_stop(struct siu_port *port_info)
{
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
struct siu_stream *siu_stream = &port_info->capture;
struct device *dev = siu_stream->substream->pcm->card->dev;
u32 stfifo;
if (!siu_stream->rw_flg)
return -EPERM;
/* input FIFO disable */
stfifo = siu_read32(base + SIU_STFIFO);
siu_write32(base + SIU_STFIFO, stfifo & ~0x13071307);
dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
stfifo, stfifo & ~0x13071307);
/* during stmread flag clear */
siu_stream->rw_flg = 0;
return 0;
}
static bool filter(struct dma_chan *chan, void *secondary)
{
struct sh_dmae_slave *param = secondary;
pr_debug("%s: secondary ID %d\n", __func__, param->shdma_slave.slave_id);
chan->private = ¶m->shdma_slave;
return true;
}
static int siu_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
/* Playback / Capture */
struct siu_platform *pdata = component->dev->platform_data;
struct siu_info *info = siu_i2s_data;
struct siu_port *port_info = siu_port_info(ss);
struct siu_stream *siu_stream;
u32 port = info->port_id;
struct device *dev = ss->pcm->card->dev;
dma_cap_mask_t mask;
struct sh_dmae_slave *param;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
dev_dbg(dev, "%s, port=%d@%p\n", __func__, port, port_info);
if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) {
siu_stream = &port_info->playback;
param = &siu_stream->param;
param->shdma_slave.slave_id = port ? pdata->dma_slave_tx_b :
pdata->dma_slave_tx_a;
} else {
siu_stream = &port_info->capture;
param = &siu_stream->param;
param->shdma_slave.slave_id = port ? pdata->dma_slave_rx_b :
pdata->dma_slave_rx_a;
}
/* Get DMA channel */
siu_stream->chan = dma_request_channel(mask, filter, param);
if (!siu_stream->chan) {
dev_err(dev, "DMA channel allocation failed!\n");
return -EBUSY;
}
siu_stream->substream = ss;
return 0;
}
static int siu_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct siu_info *info = siu_i2s_data;
struct device *dev = ss->pcm->card->dev;
struct siu_port *port_info = siu_port_info(ss);
struct siu_stream *siu_stream;
dev_dbg(dev, "%s: port=%d\n", __func__, info->port_id);
if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
siu_stream = &port_info->playback;
else
siu_stream = &port_info->capture;
dma_release_channel(siu_stream->chan);
siu_stream->chan = NULL;
siu_stream->substream = NULL;
return 0;
}
static int siu_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct siu_info *info = siu_i2s_data;
struct siu_port *port_info = siu_port_info(ss);
struct device *dev = ss->pcm->card->dev;
struct snd_pcm_runtime *rt;
struct siu_stream *siu_stream;
snd_pcm_sframes_t xfer_cnt;
if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
siu_stream = &port_info->playback;
else
siu_stream = &port_info->capture;
rt = siu_stream->substream->runtime;
siu_stream->buf_bytes = snd_pcm_lib_buffer_bytes(ss);
siu_stream->period_bytes = snd_pcm_lib_period_bytes(ss);
dev_dbg(dev, "%s: port=%d, %d channels, period=%u bytes\n", __func__,
info->port_id, rt->channels, siu_stream->period_bytes);
/* We only support buffers that are multiples of the period */
if (siu_stream->buf_bytes % siu_stream->period_bytes) {
dev_err(dev, "%s() - buffer=%d not multiple of period=%d\n",
__func__, siu_stream->buf_bytes,
siu_stream->period_bytes);
return -EINVAL;
}
xfer_cnt = bytes_to_frames(rt, siu_stream->period_bytes);
if (!xfer_cnt || xfer_cnt > 0x1000000)
return -EINVAL;
siu_stream->format = rt->format;
siu_stream->xfer_cnt = xfer_cnt;
dev_dbg(dev, "port=%d buf=%lx buf_bytes=%d period_bytes=%d "
"format=%d channels=%d xfer_cnt=%d\n", info->port_id,
(unsigned long)rt->dma_addr, siu_stream->buf_bytes,
siu_stream->period_bytes,
siu_stream->format, rt->channels, (int)xfer_cnt);
return 0;
}
static int siu_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *ss, int cmd)
{
struct siu_info *info = siu_i2s_data;
struct device *dev = ss->pcm->card->dev;
struct siu_port *port_info = siu_port_info(ss);
int ret;
dev_dbg(dev, "%s: port=%d@%p, cmd=%d\n", __func__,
info->port_id, port_info, cmd);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = siu_pcm_stmwrite_start(port_info);
else
ret = siu_pcm_stmread_start(port_info);
if (ret < 0)
dev_warn(dev, "%s: start failed on port=%d\n",
__func__, info->port_id);
break;
case SNDRV_PCM_TRIGGER_STOP:
if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
siu_pcm_stmwrite_stop(port_info);
else
siu_pcm_stmread_stop(port_info);
ret = 0;
break;
default:
dev_err(dev, "%s() unsupported cmd=%d\n", __func__, cmd);
ret = -EINVAL;
}
return ret;
}
/*
* So far only resolution of one period is supported, subject to extending the
* dmangine API
*/
static snd_pcm_uframes_t
siu_pcm_pointer_dma(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct device *dev = ss->pcm->card->dev;
struct siu_info *info = siu_i2s_data;
u32 __iomem *base = info->reg;
struct siu_port *port_info = siu_port_info(ss);
struct snd_pcm_runtime *rt = ss->runtime;
size_t ptr;
struct siu_stream *siu_stream;
if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
siu_stream = &port_info->playback;
else
siu_stream = &port_info->capture;
/*
* ptr is the offset into the buffer where the dma is currently at. We
* check if the dma buffer has just wrapped.
*/
ptr = PERIOD_OFFSET(rt->dma_addr,
siu_stream->cur_period,
siu_stream->period_bytes) - rt->dma_addr;
dev_dbg(dev,
"%s: port=%d, events %x, FSTS %x, xferred %u/%u, cookie %d\n",
__func__, info->port_id, siu_read32(base + SIU_EVNTC),
siu_read32(base + SIU_SBFSTS), ptr, siu_stream->buf_bytes,
siu_stream->cookie);
if (ptr >= siu_stream->buf_bytes)
ptr = 0;
return bytes_to_frames(ss->runtime, ptr);
}
static int siu_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
/* card->dev == socdev->dev, see snd_soc_new_pcms() */
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
struct siu_info *info = siu_i2s_data;
struct platform_device *pdev = to_platform_device(card->dev);
int ret;
int i;
/* pdev->id selects between SIUA and SIUB */
if (pdev->id < 0 || pdev->id >= SIU_PORT_NUM)
return -EINVAL;
info->port_id = pdev->id;
/*
* While the siu has 2 ports, only one port can be on at a time (only 1
* SPB). So far all the boards using the siu had only one of the ports
* wired to a codec. To simplify things, we only register one port with
* alsa. In case both ports are needed, it should be changed here
*/
for (i = pdev->id; i < pdev->id + 1; i++) {
struct siu_port **port_info = &siu_ports[i];
ret = siu_init_port(i, port_info, card);
if (ret < 0)
return ret;
snd_pcm_set_managed_buffer_all(pcm,
SNDRV_DMA_TYPE_DEV, card->dev,
SIU_BUFFER_BYTES_MAX, SIU_BUFFER_BYTES_MAX);
(*port_info)->pcm = pcm;
/* IO works */
INIT_WORK(&(*port_info)->playback.work, siu_io_work);
INIT_WORK(&(*port_info)->capture.work, siu_io_work);
}
dev_info(card->dev, "SuperH SIU driver initialized.\n");
return 0;
}
static void siu_pcm_free(struct snd_soc_component *component,
struct snd_pcm *pcm)
{
struct platform_device *pdev = to_platform_device(pcm->card->dev);
struct siu_port *port_info = siu_ports[pdev->id];
cancel_work_sync(&port_info->capture.work);
cancel_work_sync(&port_info->playback.work);
siu_free_port(port_info);
dev_dbg(pcm->card->dev, "%s\n", __func__);
}
const struct snd_soc_component_driver siu_component = {
.name = DRV_NAME,
.open = siu_pcm_open,
.close = siu_pcm_close,
.prepare = siu_pcm_prepare,
.trigger = siu_pcm_trigger,
.pointer = siu_pcm_pointer_dma,
.pcm_construct = siu_pcm_new,
.pcm_destruct = siu_pcm_free,
.legacy_dai_naming = 1,
};
EXPORT_SYMBOL_GPL(siu_component);
| linux-master | sound/soc/sh/siu_pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// ctu.c
//
// Copyright (c) 2015 Kuninori Morimoto <[email protected]>
#include "rsnd.h"
#define CTU_NAME_SIZE 16
#define CTU_NAME "ctu"
/*
* User needs to setup CTU by amixer, and its settings are
* based on below registers
*
* CTUn_CPMDR : amixser set "CTU Pass"
* CTUn_SV0xR : amixser set "CTU SV0"
* CTUn_SV1xR : amixser set "CTU SV1"
* CTUn_SV2xR : amixser set "CTU SV2"
* CTUn_SV3xR : amixser set "CTU SV3"
*
* [CTU Pass]
* 0000: default
* 0001: Connect input data of channel 0
* 0010: Connect input data of channel 1
* 0011: Connect input data of channel 2
* 0100: Connect input data of channel 3
* 0101: Connect input data of channel 4
* 0110: Connect input data of channel 5
* 0111: Connect input data of channel 6
* 1000: Connect input data of channel 7
* 1001: Connect calculated data by scale values of matrix row 0
* 1010: Connect calculated data by scale values of matrix row 1
* 1011: Connect calculated data by scale values of matrix row 2
* 1100: Connect calculated data by scale values of matrix row 3
*
* [CTU SVx]
* [Output0] = [SV00, SV01, SV02, SV03, SV04, SV05, SV06, SV07]
* [Output1] = [SV10, SV11, SV12, SV13, SV14, SV15, SV16, SV17]
* [Output2] = [SV20, SV21, SV22, SV23, SV24, SV25, SV26, SV27]
* [Output3] = [SV30, SV31, SV32, SV33, SV34, SV35, SV36, SV37]
* [Output4] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
* [Output5] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
* [Output6] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
* [Output7] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
*
* [SVxx]
* Plus Minus
* value time dB value time dB
* -----------------------------------------------------------------------
* H'7F_FFFF 2 6 H'80_0000 2 6
* ...
* H'40_0000 1 0 H'C0_0000 1 0
* ...
* H'00_0001 2.38 x 10^-7 -132
* H'00_0000 0 Mute H'FF_FFFF 2.38 x 10^-7 -132
*
*
* Ex) Input ch -> Output ch
* 1ch -> 0ch
* 0ch -> 1ch
*
* amixer set "CTU Reset" on
* amixer set "CTU Pass" 9,10
* amixer set "CTU SV0" 0,4194304
* amixer set "CTU SV1" 4194304,0
* or
* amixer set "CTU Reset" on
* amixer set "CTU Pass" 2,1
*/
struct rsnd_ctu {
struct rsnd_mod mod;
struct rsnd_kctrl_cfg_m pass;
struct rsnd_kctrl_cfg_m sv[4];
struct rsnd_kctrl_cfg_s reset;
int channels;
u32 flags;
};
#define KCTRL_INITIALIZED (1 << 0)
#define rsnd_ctu_nr(priv) ((priv)->ctu_nr)
#define for_each_rsnd_ctu(pos, priv, i) \
for ((i) = 0; \
((i) < rsnd_ctu_nr(priv)) && \
((pos) = (struct rsnd_ctu *)(priv)->ctu + i); \
i++)
#define rsnd_mod_to_ctu(_mod) \
container_of((_mod), struct rsnd_ctu, mod)
#define rsnd_ctu_get(priv, id) ((struct rsnd_ctu *)(priv->ctu) + id)
static void rsnd_ctu_activation(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, CTU_SWRSR, 0);
rsnd_mod_write(mod, CTU_SWRSR, 1);
}
static void rsnd_ctu_halt(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, CTU_CTUIR, 1);
rsnd_mod_write(mod, CTU_SWRSR, 0);
}
static int rsnd_ctu_probe_(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
return rsnd_cmd_attach(io, rsnd_mod_id(mod));
}
static void rsnd_ctu_value_init(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
u32 cpmdr = 0;
u32 scmdr = 0;
int i, j;
for (i = 0; i < RSND_MAX_CHANNELS; i++) {
u32 val = rsnd_kctrl_valm(ctu->pass, i);
cpmdr |= val << (28 - (i * 4));
if ((val > 0x8) && (scmdr < (val - 0x8)))
scmdr = val - 0x8;
}
rsnd_mod_write(mod, CTU_CTUIR, 1);
rsnd_mod_write(mod, CTU_ADINR, rsnd_runtime_channel_original(io));
rsnd_mod_write(mod, CTU_CPMDR, cpmdr);
rsnd_mod_write(mod, CTU_SCMDR, scmdr);
for (i = 0; i < 4; i++) {
if (i >= scmdr)
break;
for (j = 0; j < RSND_MAX_CHANNELS; j++)
rsnd_mod_write(mod, CTU_SVxxR(i, j), rsnd_kctrl_valm(ctu->sv[i], j));
}
rsnd_mod_write(mod, CTU_CTUIR, 0);
}
static void rsnd_ctu_value_reset(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
int i;
if (!rsnd_kctrl_vals(ctu->reset))
return;
for (i = 0; i < RSND_MAX_CHANNELS; i++) {
rsnd_kctrl_valm(ctu->pass, i) = 0;
rsnd_kctrl_valm(ctu->sv[0], i) = 0;
rsnd_kctrl_valm(ctu->sv[1], i) = 0;
rsnd_kctrl_valm(ctu->sv[2], i) = 0;
rsnd_kctrl_valm(ctu->sv[3], i) = 0;
}
rsnd_kctrl_vals(ctu->reset) = 0;
}
static int rsnd_ctu_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
int ret;
ret = rsnd_mod_power_on(mod);
if (ret < 0)
return ret;
rsnd_ctu_activation(mod);
rsnd_ctu_value_init(io, mod);
return 0;
}
static int rsnd_ctu_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_ctu_halt(mod);
rsnd_mod_power_off(mod);
return 0;
}
static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd)
{
struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
int ret;
if (rsnd_flags_has(ctu, KCTRL_INITIALIZED))
return 0;
/* CTU Pass */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU Pass",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->pass, RSND_MAX_CHANNELS,
0xC);
if (ret < 0)
return ret;
/* ROW0 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV0",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[0], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* ROW1 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV1",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[1], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* ROW2 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV2",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[2], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* ROW3 */
ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV3",
rsnd_kctrl_accept_anytime,
NULL,
&ctu->sv[3], RSND_MAX_CHANNELS,
0x00FFFFFF);
if (ret < 0)
return ret;
/* Reset */
ret = rsnd_kctrl_new_s(mod, io, rtd, "CTU Reset",
rsnd_kctrl_accept_anytime,
rsnd_ctu_value_reset,
&ctu->reset, 1);
rsnd_flags_set(ctu, KCTRL_INITIALIZED);
return ret;
}
static int rsnd_ctu_id(struct rsnd_mod *mod)
{
/*
* ctu00: -> 0, ctu01: -> 0, ctu02: -> 0, ctu03: -> 0
* ctu10: -> 1, ctu11: -> 1, ctu12: -> 1, ctu13: -> 1
*/
return mod->id / 4;
}
static int rsnd_ctu_id_sub(struct rsnd_mod *mod)
{
/*
* ctu00: -> 0, ctu01: -> 1, ctu02: -> 2, ctu03: -> 3
* ctu10: -> 0, ctu11: -> 1, ctu12: -> 2, ctu13: -> 3
*/
return mod->id % 4;
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_ctu_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
0x500 + rsnd_mod_id_raw(mod) * 0x100, 0x100);
}
#define DEBUG_INFO .debug_info = rsnd_ctu_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_ctu_ops = {
.name = CTU_NAME,
.probe = rsnd_ctu_probe_,
.init = rsnd_ctu_init,
.quit = rsnd_ctu_quit,
.pcm_new = rsnd_ctu_pcm_new,
.get_status = rsnd_mod_get_status,
.id = rsnd_ctu_id,
.id_sub = rsnd_ctu_id_sub,
.id_cmd = rsnd_mod_id_raw,
DEBUG_INFO
};
struct rsnd_mod *rsnd_ctu_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_ctu_nr(priv)))
id = 0;
return rsnd_mod_get(rsnd_ctu_get(priv, id));
}
int rsnd_ctu_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_ctu *ctu;
struct clk *clk;
char name[CTU_NAME_SIZE];
int i, nr, ret;
/* This driver doesn't support Gen1 at this point */
if (rsnd_is_gen1(priv))
return 0;
node = rsnd_ctu_of_node(priv);
if (!node)
return 0; /* not used is not error */
nr = of_get_child_count(node);
if (!nr) {
ret = -EINVAL;
goto rsnd_ctu_probe_done;
}
ctu = devm_kcalloc(dev, nr, sizeof(*ctu), GFP_KERNEL);
if (!ctu) {
ret = -ENOMEM;
goto rsnd_ctu_probe_done;
}
priv->ctu_nr = nr;
priv->ctu = ctu;
i = 0;
ret = 0;
for_each_child_of_node(node, np) {
ctu = rsnd_ctu_get(priv, i);
/*
* CTU00, CTU01, CTU02, CTU03 => CTU0
* CTU10, CTU11, CTU12, CTU13 => CTU1
*/
snprintf(name, CTU_NAME_SIZE, "%s.%d",
CTU_NAME, i / 4);
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_ctu_probe_done;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(ctu), &rsnd_ctu_ops,
clk, RSND_MOD_CTU, i);
if (ret) {
of_node_put(np);
goto rsnd_ctu_probe_done;
}
i++;
}
rsnd_ctu_probe_done:
of_node_put(node);
return ret;
}
void rsnd_ctu_remove(struct rsnd_priv *priv)
{
struct rsnd_ctu *ctu;
int i;
for_each_rsnd_ctu(ctu, priv, i) {
rsnd_mod_quit(rsnd_mod_get(ctu));
}
}
| linux-master | sound/soc/sh/rcar/ctu.c |
// SPDX-License-Identifier: GPL-2.0
//
// // Renesas R-Car debugfs support
//
// Copyright (c) 2021 Kuninori Morimoto <[email protected]>
//
// > mount -t debugfs none /sys/kernel/debug
// > cd /sys/kernel/debug/asoc/rcar-sound/ec500000.sound/rdai{N}/
// > cat playback/xxx
// > cat capture/xxx
//
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include "rsnd.h"
static int rsnd_debugfs_show(struct seq_file *m, void *v)
{
struct rsnd_dai_stream *io = m->private;
struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
int i;
/* adg is out of mods */
rsnd_adg_clk_dbg_info(priv, m);
for_each_rsnd_mod(i, mod, io) {
u32 *status = mod->ops->get_status(mod, io, mod->type);
seq_printf(m, "name: %s\n", rsnd_mod_name(mod));
seq_printf(m, "status: %08x\n", *status);
if (mod->ops->debug_info)
mod->ops->debug_info(m, io, mod);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(rsnd_debugfs);
void rsnd_debugfs_reg_show(struct seq_file *m, phys_addr_t _addr,
void __iomem *base, int offset, int size)
{
int i, j;
for (i = 0; i < size; i += 0x10) {
phys_addr_t addr = _addr + offset + i;
seq_printf(m, "%pa:", &addr);
for (j = 0; j < 0x10; j += 0x4)
seq_printf(m, " %08x", __raw_readl(base + offset + i + j));
seq_puts(m, "\n");
}
}
void rsnd_debugfs_mod_reg_show(struct seq_file *m, struct rsnd_mod *mod,
int reg_id, int offset, int size)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
rsnd_debugfs_reg_show(m,
rsnd_gen_get_phy_addr(priv, reg_id),
rsnd_gen_get_base_addr(priv, reg_id),
offset, size);
}
int rsnd_debugfs_probe(struct snd_soc_component *component)
{
struct rsnd_priv *priv = dev_get_drvdata(component->dev);
struct rsnd_dai *rdai;
struct dentry *dir;
char name[64];
int i;
/* Gen1 is not supported */
if (rsnd_is_gen1(priv))
return 0;
for_each_rsnd_dai(rdai, priv, i) {
/*
* created debugfs will be automatically
* removed, nothing to do for _remove.
* see
* soc_cleanup_component_debugfs()
*/
snprintf(name, sizeof(name), "rdai%d", i);
dir = debugfs_create_dir(name, component->debugfs_root);
debugfs_create_file("playback", 0444, dir, &rdai->playback, &rsnd_debugfs_fops);
debugfs_create_file("capture", 0444, dir, &rdai->capture, &rsnd_debugfs_fops);
}
return 0;
}
#endif /* CONFIG_DEBUG_FS */
| linux-master | sound/soc/sh/rcar/debugfs.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car CMD support
//
// Copyright (C) 2015 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
#include "rsnd.h"
struct rsnd_cmd {
struct rsnd_mod mod;
};
#define CMD_NAME "cmd"
#define rsnd_cmd_nr(priv) ((priv)->cmd_nr)
#define for_each_rsnd_cmd(pos, priv, i) \
for ((i) = 0; \
((i) < rsnd_cmd_nr(priv)) && \
((pos) = (struct rsnd_cmd *)(priv)->cmd + i); \
i++)
static int rsnd_cmd_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io);
struct rsnd_mod *mix = rsnd_io_to_mod_mix(io);
struct device *dev = rsnd_priv_to_dev(priv);
u32 data;
static const u32 path[] = {
[1] = 1 << 0,
[5] = 1 << 8,
[6] = 1 << 12,
[9] = 1 << 15,
};
if (!mix && !dvc)
return 0;
if (ARRAY_SIZE(path) < rsnd_mod_id(mod) + 1)
return -ENXIO;
if (mix) {
struct rsnd_dai *rdai;
int i;
/*
* it is assuming that integrater is well understanding about
* data path. Here doesn't check impossible connection,
* like src2 + src5
*/
data = 0;
for_each_rsnd_dai(rdai, priv, i) {
struct rsnd_dai_stream *tio = &rdai->playback;
struct rsnd_mod *src = rsnd_io_to_mod_src(tio);
if (mix == rsnd_io_to_mod_mix(tio))
data |= path[rsnd_mod_id(src)];
tio = &rdai->capture;
src = rsnd_io_to_mod_src(tio);
if (mix == rsnd_io_to_mod_mix(tio))
data |= path[rsnd_mod_id(src)];
}
} else {
struct rsnd_mod *src = rsnd_io_to_mod_src(io);
static const u8 cmd_case[] = {
[0] = 0x3,
[1] = 0x3,
[2] = 0x4,
[3] = 0x1,
[4] = 0x2,
[5] = 0x4,
[6] = 0x1,
[9] = 0x2,
};
if (unlikely(!src))
return -EIO;
data = path[rsnd_mod_id(src)] |
cmd_case[rsnd_mod_id(src)] << 16;
}
dev_dbg(dev, "ctu/mix path = 0x%08x\n", data);
rsnd_mod_write(mod, CMD_ROUTE_SLCT, data);
rsnd_mod_write(mod, CMD_BUSIF_MODE, rsnd_get_busif_shift(io, mod) | 1);
rsnd_mod_write(mod, CMD_BUSIF_DALIGN, rsnd_get_dalign(mod, io));
rsnd_adg_set_cmd_timsel_gen2(mod, io);
return 0;
}
static int rsnd_cmd_start(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_mod_write(mod, CMD_CTRL, 0x10);
return 0;
}
static int rsnd_cmd_stop(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_mod_write(mod, CMD_CTRL, 0);
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_cmd_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
0x180 + rsnd_mod_id_raw(mod) * 0x20, 0x30);
}
#define DEBUG_INFO .debug_info = rsnd_cmd_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_cmd_ops = {
.name = CMD_NAME,
.init = rsnd_cmd_init,
.start = rsnd_cmd_start,
.stop = rsnd_cmd_stop,
.get_status = rsnd_mod_get_status,
DEBUG_INFO
};
static struct rsnd_mod *rsnd_cmd_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_cmd_nr(priv)))
id = 0;
return rsnd_mod_get((struct rsnd_cmd *)(priv->cmd) + id);
}
int rsnd_cmd_attach(struct rsnd_dai_stream *io, int id)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct rsnd_mod *mod = rsnd_cmd_mod_get(priv, id);
return rsnd_dai_connect(mod, io, mod->type);
}
int rsnd_cmd_probe(struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_cmd *cmd;
int i, nr;
/* This driver doesn't support Gen1 at this point */
if (rsnd_is_gen1(priv))
return 0;
/* same number as DVC */
nr = priv->dvc_nr;
if (!nr)
return 0;
cmd = devm_kcalloc(dev, nr, sizeof(*cmd), GFP_KERNEL);
if (!cmd)
return -ENOMEM;
priv->cmd_nr = nr;
priv->cmd = cmd;
for_each_rsnd_cmd(cmd, priv, i) {
int ret = rsnd_mod_init(priv, rsnd_mod_get(cmd),
&rsnd_cmd_ops, NULL,
RSND_MOD_CMD, i);
if (ret)
return ret;
}
return 0;
}
void rsnd_cmd_remove(struct rsnd_priv *priv)
{
struct rsnd_cmd *cmd;
int i;
for_each_rsnd_cmd(cmd, priv, i) {
rsnd_mod_quit(rsnd_mod_get(cmd));
}
}
| linux-master | sound/soc/sh/rcar/cmd.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car SRU/SCU/SSIU/SSI support
//
// Copyright (C) 2013 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
//
// Based on fsi.c
// Kuninori Morimoto <[email protected]>
/*
* Renesas R-Car sound device structure
*
* Gen1
*
* SRU : Sound Routing Unit
* - SRC : Sampling Rate Converter
* - CMD
* - CTU : Channel Count Conversion Unit
* - MIX : Mixer
* - DVC : Digital Volume and Mute Function
* - SSI : Serial Sound Interface
*
* Gen2
*
* SCU : Sampling Rate Converter Unit
* - SRC : Sampling Rate Converter
* - CMD
* - CTU : Channel Count Conversion Unit
* - MIX : Mixer
* - DVC : Digital Volume and Mute Function
* SSIU : Serial Sound Interface Unit
* - SSI : Serial Sound Interface
*/
/*
* driver data Image
*
* rsnd_priv
* |
* | ** this depends on Gen1/Gen2
* |
* +- gen
* |
* | ** these depend on data path
* | ** gen and platform data control it
* |
* +- rdai[0]
* | | sru ssiu ssi
* | +- playback -> [mod] -> [mod] -> [mod] -> ...
* | |
* | | sru ssiu ssi
* | +- capture -> [mod] -> [mod] -> [mod] -> ...
* |
* +- rdai[1]
* | | sru ssiu ssi
* | +- playback -> [mod] -> [mod] -> [mod] -> ...
* | |
* | | sru ssiu ssi
* | +- capture -> [mod] -> [mod] -> [mod] -> ...
* ...
* |
* | ** these control ssi
* |
* +- ssi
* | |
* | +- ssi[0]
* | +- ssi[1]
* | +- ssi[2]
* | ...
* |
* | ** these control src
* |
* +- src
* |
* +- src[0]
* +- src[1]
* +- src[2]
* ...
*
*
* for_each_rsnd_dai(xx, priv, xx)
* rdai[0] => rdai[1] => rdai[2] => ...
*
* for_each_rsnd_mod(xx, rdai, xx)
* [mod] => [mod] => [mod] => ...
*
* rsnd_dai_call(xxx, fn )
* [mod]->fn() -> [mod]->fn() -> [mod]->fn()...
*
*/
#include <linux/pm_runtime.h>
#include "rsnd.h"
#define RSND_RATES SNDRV_PCM_RATE_8000_192000
#define RSND_FMTS (SNDRV_PCM_FMTBIT_S8 |\
SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static const struct of_device_id rsnd_of_match[] = {
{ .compatible = "renesas,rcar_sound-gen1", .data = (void *)RSND_GEN1 },
{ .compatible = "renesas,rcar_sound-gen2", .data = (void *)RSND_GEN2 },
{ .compatible = "renesas,rcar_sound-gen3", .data = (void *)RSND_GEN3 },
{ .compatible = "renesas,rcar_sound-gen4", .data = (void *)RSND_GEN4 },
/* Special Handling */
{ .compatible = "renesas,rcar_sound-r8a77990", .data = (void *)(RSND_GEN3 | RSND_SOC_E) },
{},
};
MODULE_DEVICE_TABLE(of, rsnd_of_match);
/*
* rsnd_mod functions
*/
void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type)
{
if (mod->type != type) {
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
dev_warn(dev, "%s is not your expected module\n",
rsnd_mod_name(mod));
}
}
struct dma_chan *rsnd_mod_dma_req(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
if (!mod || !mod->ops || !mod->ops->dma_req)
return NULL;
return mod->ops->dma_req(io, mod);
}
#define MOD_NAME_NUM 5
#define MOD_NAME_SIZE 16
char *rsnd_mod_name(struct rsnd_mod *mod)
{
static char names[MOD_NAME_NUM][MOD_NAME_SIZE];
static int num;
char *name = names[num];
num++;
if (num >= MOD_NAME_NUM)
num = 0;
/*
* Let's use same char to avoid pointlessness memory
* Thus, rsnd_mod_name() should be used immediately
* Don't keep pointer
*/
if ((mod)->ops->id_sub) {
snprintf(name, MOD_NAME_SIZE, "%s[%d%d]",
mod->ops->name,
rsnd_mod_id(mod),
rsnd_mod_id_sub(mod));
} else {
snprintf(name, MOD_NAME_SIZE, "%s[%d]",
mod->ops->name,
rsnd_mod_id(mod));
}
return name;
}
u32 *rsnd_mod_get_status(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
enum rsnd_mod_type type)
{
return &mod->status;
}
int rsnd_mod_id_raw(struct rsnd_mod *mod)
{
return mod->id;
}
int rsnd_mod_id(struct rsnd_mod *mod)
{
if ((mod)->ops->id)
return (mod)->ops->id(mod);
return rsnd_mod_id_raw(mod);
}
int rsnd_mod_id_sub(struct rsnd_mod *mod)
{
if ((mod)->ops->id_sub)
return (mod)->ops->id_sub(mod);
return 0;
}
int rsnd_mod_init(struct rsnd_priv *priv,
struct rsnd_mod *mod,
struct rsnd_mod_ops *ops,
struct clk *clk,
enum rsnd_mod_type type,
int id)
{
int ret = clk_prepare(clk);
if (ret)
return ret;
mod->id = id;
mod->ops = ops;
mod->type = type;
mod->clk = clk;
mod->priv = priv;
return 0;
}
void rsnd_mod_quit(struct rsnd_mod *mod)
{
clk_unprepare(mod->clk);
mod->clk = NULL;
}
void rsnd_mod_interrupt(struct rsnd_mod *mod,
void (*callback)(struct rsnd_mod *mod,
struct rsnd_dai_stream *io))
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct rsnd_dai *rdai;
int i;
for_each_rsnd_dai(rdai, priv, i) {
struct rsnd_dai_stream *io = &rdai->playback;
if (mod == io->mod[mod->type])
callback(mod, io);
io = &rdai->capture;
if (mod == io->mod[mod->type])
callback(mod, io);
}
}
int rsnd_io_is_working(struct rsnd_dai_stream *io)
{
/* see rsnd_dai_stream_init/quit() */
if (io->substream)
return snd_pcm_running(io->substream);
return 0;
}
int rsnd_runtime_channel_original_with_params(struct rsnd_dai_stream *io,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
/*
* params will be added when refine
* see
* __rsnd_soc_hw_rule_rate()
* __rsnd_soc_hw_rule_channels()
*/
if (params)
return params_channels(params);
else if (runtime)
return runtime->channels;
return 0;
}
int rsnd_runtime_channel_after_ctu_with_params(struct rsnd_dai_stream *io,
struct snd_pcm_hw_params *params)
{
int chan = rsnd_runtime_channel_original_with_params(io, params);
struct rsnd_mod *ctu_mod = rsnd_io_to_mod_ctu(io);
if (ctu_mod) {
u32 converted_chan = rsnd_io_converted_chan(io);
/*
* !! Note !!
*
* converted_chan will be used for CTU,
* or TDM Split mode.
* User shouldn't use CTU with TDM Split mode.
*/
if (rsnd_runtime_is_tdm_split(io)) {
struct device *dev = rsnd_priv_to_dev(rsnd_io_to_priv(io));
dev_err(dev, "CTU and TDM Split should be used\n");
}
if (converted_chan)
return converted_chan;
}
return chan;
}
int rsnd_channel_normalization(int chan)
{
if (WARN_ON((chan > 8) || (chan < 0)))
return 0;
/* TDM Extend Mode needs 8ch */
if (chan == 6)
chan = 8;
return chan;
}
int rsnd_runtime_channel_for_ssi_with_params(struct rsnd_dai_stream *io,
struct snd_pcm_hw_params *params)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
int chan = rsnd_io_is_play(io) ?
rsnd_runtime_channel_after_ctu_with_params(io, params) :
rsnd_runtime_channel_original_with_params(io, params);
/* Use Multi SSI */
if (rsnd_runtime_is_multi_ssi(io))
chan /= rsnd_rdai_ssi_lane_get(rdai);
return rsnd_channel_normalization(chan);
}
int rsnd_runtime_is_multi_ssi(struct rsnd_dai_stream *io)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
int lane = rsnd_rdai_ssi_lane_get(rdai);
int chan = rsnd_io_is_play(io) ?
rsnd_runtime_channel_after_ctu(io) :
rsnd_runtime_channel_original(io);
return (chan > 2) && (lane > 1);
}
int rsnd_runtime_is_tdm(struct rsnd_dai_stream *io)
{
return rsnd_runtime_channel_for_ssi(io) >= 6;
}
int rsnd_runtime_is_tdm_split(struct rsnd_dai_stream *io)
{
return !!rsnd_flags_has(io, RSND_STREAM_TDM_SPLIT);
}
/*
* ADINR function
*/
u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct device *dev = rsnd_priv_to_dev(priv);
switch (snd_pcm_format_width(runtime->format)) {
case 8:
return 16 << 16;
case 16:
return 8 << 16;
case 24:
return 0 << 16;
}
dev_warn(dev, "not supported sample bits\n");
return 0;
}
/*
* DALIGN function
*/
u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io)
{
static const u32 dalign_values[8] = {
0x76543210, 0x00000032, 0x00007654, 0x00000076,
0xfedcba98, 0x000000ba, 0x0000fedc, 0x000000fe,
};
int id = 0;
struct rsnd_mod *ssiu = rsnd_io_to_mod_ssiu(io);
struct rsnd_mod *target;
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
u32 dalign;
/*
* *Hardware* L/R and *Software* L/R are inverted for 16bit data.
* 31..16 15...0
* HW: [L ch] [R ch]
* SW: [R ch] [L ch]
* We need to care about inversion timing to control
* Playback/Capture correctly.
* The point is [DVC] needs *Hardware* L/R, [MEM] needs *Software* L/R
*
* sL/R : software L/R
* hL/R : hardware L/R
* (*) : conversion timing
*
* Playback
* sL/R (*) hL/R hL/R hL/R hL/R hL/R
* [MEM] -> [SRC] -> [DVC] -> [CMD] -> [SSIU] -> [SSI] -> codec
*
* Capture
* hL/R hL/R hL/R hL/R hL/R (*) sL/R
* codec -> [SSI] -> [SSIU] -> [SRC] -> [DVC] -> [CMD] -> [MEM]
*/
if (rsnd_io_is_play(io)) {
struct rsnd_mod *src = rsnd_io_to_mod_src(io);
target = src ? src : ssiu;
} else {
struct rsnd_mod *cmd = rsnd_io_to_mod_cmd(io);
target = cmd ? cmd : ssiu;
}
if (mod == ssiu)
id = rsnd_mod_id_sub(mod);
dalign = dalign_values[id];
if (mod == target && snd_pcm_format_width(runtime->format) == 16) {
/* Target mod needs inverted DALIGN when 16bit */
dalign = (dalign & 0xf0f0f0f0) >> 4 |
(dalign & 0x0f0f0f0f) << 4;
}
return dalign;
}
u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, struct rsnd_mod *mod)
{
static const enum rsnd_mod_type playback_mods[] = {
RSND_MOD_SRC,
RSND_MOD_CMD,
RSND_MOD_SSIU,
};
static const enum rsnd_mod_type capture_mods[] = {
RSND_MOD_CMD,
RSND_MOD_SRC,
RSND_MOD_SSIU,
};
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_mod *tmod = NULL;
const enum rsnd_mod_type *mods =
rsnd_io_is_play(io) ?
playback_mods : capture_mods;
int i;
/*
* This is needed for 24bit data
* We need to shift 8bit
*
* Linux 24bit data is located as 0x00******
* HW 24bit data is located as 0x******00
*
*/
if (snd_pcm_format_width(runtime->format) != 24)
return 0;
for (i = 0; i < ARRAY_SIZE(playback_mods); i++) {
tmod = rsnd_io_to_mod(io, mods[i]);
if (tmod)
break;
}
if (tmod != mod)
return 0;
if (rsnd_io_is_play(io))
return (0 << 20) | /* shift to Left */
(8 << 16); /* 8bit */
else
return (1 << 20) | /* shift to Right */
(8 << 16); /* 8bit */
}
/*
* rsnd_dai functions
*/
struct rsnd_mod *rsnd_mod_next(int *iterator,
struct rsnd_dai_stream *io,
enum rsnd_mod_type *array,
int array_size)
{
int max = array ? array_size : RSND_MOD_MAX;
for (; *iterator < max; (*iterator)++) {
enum rsnd_mod_type type = (array) ? array[*iterator] : *iterator;
struct rsnd_mod *mod = rsnd_io_to_mod(io, type);
if (mod)
return mod;
}
return NULL;
}
static enum rsnd_mod_type rsnd_mod_sequence[][RSND_MOD_MAX] = {
{
/* CAPTURE */
RSND_MOD_AUDMAPP,
RSND_MOD_AUDMA,
RSND_MOD_DVC,
RSND_MOD_MIX,
RSND_MOD_CTU,
RSND_MOD_CMD,
RSND_MOD_SRC,
RSND_MOD_SSIU,
RSND_MOD_SSIM3,
RSND_MOD_SSIM2,
RSND_MOD_SSIM1,
RSND_MOD_SSIP,
RSND_MOD_SSI,
}, {
/* PLAYBACK */
RSND_MOD_AUDMAPP,
RSND_MOD_AUDMA,
RSND_MOD_SSIM3,
RSND_MOD_SSIM2,
RSND_MOD_SSIM1,
RSND_MOD_SSIP,
RSND_MOD_SSI,
RSND_MOD_SSIU,
RSND_MOD_DVC,
RSND_MOD_MIX,
RSND_MOD_CTU,
RSND_MOD_CMD,
RSND_MOD_SRC,
},
};
static int rsnd_status_update(struct rsnd_dai_stream *io,
struct rsnd_mod *mod, enum rsnd_mod_type type,
int shift, int add, int timing)
{
u32 *status = mod->ops->get_status(mod, io, type);
u32 mask = 0xF << shift;
u8 val = (*status >> shift) & 0xF;
u8 next_val = (val + add) & 0xF;
int func_call = (val == timing);
/* no status update */
if (add == 0 || shift == 28)
return 1;
if (next_val == 0xF) /* underflow case */
func_call = -1;
else
*status = (*status & ~mask) + (next_val << shift);
return func_call;
}
#define rsnd_dai_call(fn, io, param...) \
({ \
struct device *dev = rsnd_priv_to_dev(rsnd_io_to_priv(io)); \
struct rsnd_mod *mod; \
int is_play = rsnd_io_is_play(io); \
int ret = 0, i; \
enum rsnd_mod_type *types = rsnd_mod_sequence[is_play]; \
for_each_rsnd_mod_arrays(i, mod, io, types, RSND_MOD_MAX) { \
int tmp = 0; \
int func_call = rsnd_status_update(io, mod, types[i], \
__rsnd_mod_shift_##fn, \
__rsnd_mod_add_##fn, \
__rsnd_mod_call_##fn); \
if (func_call > 0 && (mod)->ops->fn) \
tmp = (mod)->ops->fn(mod, io, param); \
if (unlikely(func_call < 0) || \
unlikely(tmp && (tmp != -EPROBE_DEFER))) \
dev_err(dev, "%s : %s error (%d, %d)\n", \
rsnd_mod_name(mod), #fn, tmp, func_call);\
ret |= tmp; \
} \
ret; \
})
int rsnd_dai_connect(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
enum rsnd_mod_type type)
{
struct rsnd_priv *priv;
struct device *dev;
if (!mod)
return -EIO;
if (io->mod[type] == mod)
return 0;
if (io->mod[type])
return -EINVAL;
priv = rsnd_mod_to_priv(mod);
dev = rsnd_priv_to_dev(priv);
io->mod[type] = mod;
dev_dbg(dev, "%s is connected to io (%s)\n",
rsnd_mod_name(mod),
rsnd_io_is_play(io) ? "Playback" : "Capture");
return 0;
}
static void rsnd_dai_disconnect(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
enum rsnd_mod_type type)
{
io->mod[type] = NULL;
}
int rsnd_rdai_channels_ctrl(struct rsnd_dai *rdai,
int max_channels)
{
if (max_channels > 0)
rdai->max_channels = max_channels;
return rdai->max_channels;
}
int rsnd_rdai_ssi_lane_ctrl(struct rsnd_dai *rdai,
int ssi_lane)
{
if (ssi_lane > 0)
rdai->ssi_lane = ssi_lane;
return rdai->ssi_lane;
}
int rsnd_rdai_width_ctrl(struct rsnd_dai *rdai, int width)
{
if (width > 0)
rdai->chan_width = width;
return rdai->chan_width;
}
struct rsnd_dai *rsnd_rdai_get(struct rsnd_priv *priv, int id)
{
if ((id < 0) || (id >= rsnd_rdai_nr(priv)))
return NULL;
return priv->rdai + id;
}
static struct snd_soc_dai_driver
*rsnd_daidrv_get(struct rsnd_priv *priv, int id)
{
if ((id < 0) || (id >= rsnd_rdai_nr(priv)))
return NULL;
return priv->daidrv + id;
}
#define rsnd_dai_to_priv(dai) snd_soc_dai_get_drvdata(dai)
static struct rsnd_dai *rsnd_dai_to_rdai(struct snd_soc_dai *dai)
{
struct rsnd_priv *priv = rsnd_dai_to_priv(dai);
return rsnd_rdai_get(priv, dai->id);
}
/*
* rsnd_soc_dai functions
*/
void rsnd_dai_period_elapsed(struct rsnd_dai_stream *io)
{
struct snd_pcm_substream *substream = io->substream;
/*
* this function should be called...
*
* - if rsnd_dai_pointer_update() returns true
* - without spin lock
*/
snd_pcm_period_elapsed(substream);
}
static void rsnd_dai_stream_init(struct rsnd_dai_stream *io,
struct snd_pcm_substream *substream)
{
io->substream = substream;
}
static void rsnd_dai_stream_quit(struct rsnd_dai_stream *io)
{
io->substream = NULL;
}
static
struct snd_soc_dai *rsnd_substream_to_dai(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
return asoc_rtd_to_cpu(rtd, 0);
}
static
struct rsnd_dai_stream *rsnd_rdai_to_io(struct rsnd_dai *rdai,
struct snd_pcm_substream *substream)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return &rdai->playback;
else
return &rdai->capture;
}
static int rsnd_soc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct rsnd_priv *priv = rsnd_dai_to_priv(dai);
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
int ret;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
ret = rsnd_dai_call(init, io, priv);
if (ret < 0)
goto dai_trigger_end;
ret = rsnd_dai_call(start, io, priv);
if (ret < 0)
goto dai_trigger_end;
ret = rsnd_dai_call(irq, io, priv, 1);
if (ret < 0)
goto dai_trigger_end;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
ret = rsnd_dai_call(irq, io, priv, 0);
ret |= rsnd_dai_call(stop, io, priv);
ret |= rsnd_dai_call(quit, io, priv);
break;
default:
ret = -EINVAL;
}
dai_trigger_end:
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
static int rsnd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
/* set clock master for audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
rdai->clk_master = 0;
break;
case SND_SOC_DAIFMT_BP_FP:
rdai->clk_master = 1; /* cpu is master */
break;
default:
return -EINVAL;
}
/* set format */
rdai->bit_clk_inv = 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
rdai->sys_delay = 0;
rdai->data_alignment = 0;
rdai->frm_clk_inv = 0;
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_DSP_B:
rdai->sys_delay = 1;
rdai->data_alignment = 0;
rdai->frm_clk_inv = 1;
break;
case SND_SOC_DAIFMT_RIGHT_J:
rdai->sys_delay = 1;
rdai->data_alignment = 1;
rdai->frm_clk_inv = 1;
break;
case SND_SOC_DAIFMT_DSP_A:
rdai->sys_delay = 0;
rdai->data_alignment = 0;
rdai->frm_clk_inv = 1;
break;
}
/* set clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
rdai->frm_clk_inv = !rdai->frm_clk_inv;
break;
case SND_SOC_DAIFMT_IB_NF:
rdai->bit_clk_inv = !rdai->bit_clk_inv;
break;
case SND_SOC_DAIFMT_IB_IF:
rdai->bit_clk_inv = !rdai->bit_clk_inv;
rdai->frm_clk_inv = !rdai->frm_clk_inv;
break;
case SND_SOC_DAIFMT_NB_NF:
default:
break;
}
return 0;
}
static int rsnd_soc_set_dai_tdm_slot(struct snd_soc_dai *dai,
u32 tx_mask, u32 rx_mask,
int slots, int slot_width)
{
struct rsnd_priv *priv = rsnd_dai_to_priv(dai);
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct device *dev = rsnd_priv_to_dev(priv);
switch (slot_width) {
case 16:
case 24:
case 32:
break;
default:
/* use default */
/*
* Indicate warning if DT has "dai-tdm-slot-width"
* but the value was not expected.
*/
if (slot_width)
dev_warn(dev, "unsupported TDM slot width (%d), force to use default 32\n",
slot_width);
slot_width = 32;
}
switch (slots) {
case 2:
/* TDM Split Mode */
case 6:
case 8:
/* TDM Extend Mode */
rsnd_rdai_channels_set(rdai, slots);
rsnd_rdai_ssi_lane_set(rdai, 1);
rsnd_rdai_width_set(rdai, slot_width);
break;
default:
dev_err(dev, "unsupported TDM slots (%d)\n", slots);
return -EINVAL;
}
return 0;
}
static unsigned int rsnd_soc_hw_channels_list[] = {
2, 6, 8,
};
static unsigned int rsnd_soc_hw_rate_list[] = {
8000,
11025,
16000,
22050,
32000,
44100,
48000,
64000,
88200,
96000,
176400,
192000,
};
static int rsnd_soc_hw_rule(struct rsnd_dai *rdai,
unsigned int *list, int list_num,
struct snd_interval *baseline, struct snd_interval *iv,
struct rsnd_dai_stream *io, char *unit)
{
struct snd_interval p;
unsigned int rate;
int i;
snd_interval_any(&p);
p.min = UINT_MAX;
p.max = 0;
for (i = 0; i < list_num; i++) {
if (!snd_interval_test(iv, list[i]))
continue;
rate = rsnd_ssi_clk_query(rdai,
baseline->min, list[i], NULL);
if (rate > 0) {
p.min = min(p.min, list[i]);
p.max = max(p.max, list[i]);
}
rate = rsnd_ssi_clk_query(rdai,
baseline->max, list[i], NULL);
if (rate > 0) {
p.min = min(p.min, list[i]);
p.max = max(p.max, list[i]);
}
}
/* Indicate error once if it can't handle */
if (!rsnd_flags_has(io, RSND_HW_RULE_ERR) && (p.min > p.max)) {
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct device *dev = rsnd_priv_to_dev(priv);
dev_warn(dev, "It can't handle %d %s <-> %d %s\n",
baseline->min, unit, baseline->max, unit);
rsnd_flags_set(io, RSND_HW_RULE_ERR);
}
return snd_interval_refine(iv, &p);
}
static int rsnd_soc_hw_rule_rate(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_interval *ic_ = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_interval *ir = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval ic;
struct rsnd_dai_stream *io = rule->private;
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
/*
* possible sampling rate limitation is same as
* 2ch if it supports multi ssi
* and same as 8ch if TDM 6ch (see rsnd_ssi_config_init())
*/
ic = *ic_;
ic.min =
ic.max = rsnd_runtime_channel_for_ssi_with_params(io, params);
return rsnd_soc_hw_rule(rdai, rsnd_soc_hw_rate_list,
ARRAY_SIZE(rsnd_soc_hw_rate_list),
&ic, ir, io, "ch");
}
static int rsnd_soc_hw_rule_channels(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct snd_interval *ic_ = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_interval *ir = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval ic;
struct rsnd_dai_stream *io = rule->private;
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
/*
* possible sampling rate limitation is same as
* 2ch if it supports multi ssi
* and same as 8ch if TDM 6ch (see rsnd_ssi_config_init())
*/
ic = *ic_;
ic.min =
ic.max = rsnd_runtime_channel_for_ssi_with_params(io, params);
return rsnd_soc_hw_rule(rdai, rsnd_soc_hw_channels_list,
ARRAY_SIZE(rsnd_soc_hw_channels_list),
ir, &ic, io, "Hz");
}
static const struct snd_pcm_hardware rsnd_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID,
.buffer_bytes_max = 64 * 1024,
.period_bytes_min = 32,
.period_bytes_max = 8192,
.periods_min = 1,
.periods_max = 32,
.fifo_size = 256,
};
static int rsnd_soc_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
struct snd_pcm_hw_constraint_list *constraint = &rdai->constraint;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned int max_channels = rsnd_rdai_channels_get(rdai);
int i;
rsnd_flags_del(io, RSND_HW_RULE_ERR);
rsnd_dai_stream_init(io, substream);
/*
* Channel Limitation
* It depends on Platform design
*/
constraint->list = rsnd_soc_hw_channels_list;
constraint->count = 0;
constraint->mask = 0;
for (i = 0; i < ARRAY_SIZE(rsnd_soc_hw_channels_list); i++) {
if (rsnd_soc_hw_channels_list[i] > max_channels)
break;
constraint->count = i + 1;
}
snd_soc_set_runtime_hwparams(substream, &rsnd_pcm_hardware);
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS, constraint);
snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
/*
* Sampling Rate / Channel Limitation
* It depends on Clock Master Mode
*/
if (rsnd_rdai_is_clk_master(rdai)) {
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
rsnd_soc_hw_rule_rate,
is_play ? &rdai->playback : &rdai->capture,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
rsnd_soc_hw_rule_channels,
is_play ? &rdai->playback : &rdai->capture,
SNDRV_PCM_HW_PARAM_RATE, -1);
}
return 0;
}
static void rsnd_soc_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
/*
* call rsnd_dai_call without spinlock
*/
rsnd_dai_call(cleanup, io, priv);
rsnd_dai_stream_quit(io);
}
static int rsnd_soc_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct rsnd_priv *priv = rsnd_dai_to_priv(dai);
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
return rsnd_dai_call(prepare, io, priv);
}
static u64 rsnd_soc_dai_formats[] = {
/*
* 1st Priority
*
* Well tested formats.
* Select below from Sound Card, not auto
* SND_SOC_DAIFMT_CBC_CFC
* SND_SOC_DAIFMT_CBP_CFP
*/
SND_SOC_POSSIBLE_DAIFMT_I2S |
SND_SOC_POSSIBLE_DAIFMT_RIGHT_J |
SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
SND_SOC_POSSIBLE_DAIFMT_NB_NF |
SND_SOC_POSSIBLE_DAIFMT_NB_IF |
SND_SOC_POSSIBLE_DAIFMT_IB_NF |
SND_SOC_POSSIBLE_DAIFMT_IB_IF,
/*
* 2nd Priority
*
* Supported, but not well tested
*/
SND_SOC_POSSIBLE_DAIFMT_DSP_A |
SND_SOC_POSSIBLE_DAIFMT_DSP_B,
};
static void rsnd_parse_tdm_split_mode(struct rsnd_priv *priv,
struct rsnd_dai_stream *io,
struct device_node *dai_np)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *ssiu_np = rsnd_ssiu_of_node(priv);
struct device_node *np;
int is_play = rsnd_io_is_play(io);
int i;
if (!ssiu_np)
return;
/*
* This driver assumes that it is TDM Split mode
* if it includes ssiu node
*/
for (i = 0;; i++) {
struct device_node *node = is_play ?
of_parse_phandle(dai_np, "playback", i) :
of_parse_phandle(dai_np, "capture", i);
if (!node)
break;
for_each_child_of_node(ssiu_np, np) {
if (np == node) {
rsnd_flags_set(io, RSND_STREAM_TDM_SPLIT);
dev_dbg(dev, "%s is part of TDM Split\n", io->name);
}
}
of_node_put(node);
}
of_node_put(ssiu_np);
}
static void rsnd_parse_connect_simple(struct rsnd_priv *priv,
struct rsnd_dai_stream *io,
struct device_node *dai_np)
{
if (!rsnd_io_to_mod_ssi(io))
return;
rsnd_parse_tdm_split_mode(priv, io, dai_np);
}
static void rsnd_parse_connect_graph(struct rsnd_priv *priv,
struct rsnd_dai_stream *io,
struct device_node *endpoint)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *remote_node;
if (!rsnd_io_to_mod_ssi(io))
return;
remote_node = of_graph_get_remote_port_parent(endpoint);
/* HDMI0 */
if (strstr(remote_node->full_name, "hdmi@fead0000")) {
rsnd_flags_set(io, RSND_STREAM_HDMI0);
dev_dbg(dev, "%s connected to HDMI0\n", io->name);
}
/* HDMI1 */
if (strstr(remote_node->full_name, "hdmi@feae0000")) {
rsnd_flags_set(io, RSND_STREAM_HDMI1);
dev_dbg(dev, "%s connected to HDMI1\n", io->name);
}
rsnd_parse_tdm_split_mode(priv, io, endpoint);
of_node_put(remote_node);
}
void rsnd_parse_connect_common(struct rsnd_dai *rdai, char *name,
struct rsnd_mod* (*mod_get)(struct rsnd_priv *priv, int id),
struct device_node *node,
struct device_node *playback,
struct device_node *capture)
{
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np;
int i;
if (!node)
return;
i = 0;
for_each_child_of_node(node, np) {
struct rsnd_mod *mod;
i = rsnd_node_fixed_index(dev, np, name, i);
if (i < 0) {
of_node_put(np);
break;
}
mod = mod_get(priv, i);
if (np == playback)
rsnd_dai_connect(mod, &rdai->playback, mod->type);
if (np == capture)
rsnd_dai_connect(mod, &rdai->capture, mod->type);
i++;
}
of_node_put(node);
}
int rsnd_node_fixed_index(struct device *dev, struct device_node *node, char *name, int idx)
{
char node_name[16];
/*
* rsnd is assuming each device nodes are sequential numbering,
* but some of them are not.
* This function adjusts index for it.
*
* ex)
* Normal case, special case
* ssi-0
* ssi-1
* ssi-2
* ssi-3 ssi-3
* ssi-4 ssi-4
* ...
*
* assume Max 64 node
*/
for (; idx < 64; idx++) {
snprintf(node_name, sizeof(node_name), "%s-%d", name, idx);
if (strncmp(node_name, of_node_full_name(node), sizeof(node_name)) == 0)
return idx;
}
dev_err(dev, "strange node numbering (%s)",
of_node_full_name(node));
return -EINVAL;
}
int rsnd_node_count(struct rsnd_priv *priv, struct device_node *node, char *name)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np;
int i;
i = 0;
for_each_child_of_node(node, np) {
i = rsnd_node_fixed_index(dev, np, name, i);
if (i < 0) {
of_node_put(np);
return 0;
}
i++;
}
return i;
}
static int rsnd_dai_of_node(struct rsnd_priv *priv, int *is_graph)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np = dev->of_node;
struct device_node *ports, *node;
int nr = 0;
int i = 0;
*is_graph = 0;
/*
* parse both previous dai (= rcar_sound,dai), and
* graph dai (= ports/port)
*/
/*
* Simple-Card
*/
node = of_get_child_by_name(np, RSND_NODE_DAI);
if (!node)
goto audio_graph;
of_node_put(node);
for_each_child_of_node(np, node) {
if (!of_node_name_eq(node, RSND_NODE_DAI))
continue;
priv->component_dais[i] = of_get_child_count(node);
nr += priv->component_dais[i];
i++;
if (i >= RSND_MAX_COMPONENT) {
dev_info(dev, "reach to max component\n");
of_node_put(node);
break;
}
}
return nr;
audio_graph:
/*
* Audio-Graph-Card
*/
for_each_child_of_node(np, ports) {
if (!of_node_name_eq(ports, "ports") &&
!of_node_name_eq(ports, "port"))
continue;
priv->component_dais[i] = of_graph_get_endpoint_count(ports);
nr += priv->component_dais[i];
i++;
if (i >= RSND_MAX_COMPONENT) {
dev_info(dev, "reach to max component\n");
of_node_put(node);
of_node_put(ports);
break;
}
}
*is_graph = 1;
return nr;
}
#define PREALLOC_BUFFER (32 * 1024)
#define PREALLOC_BUFFER_MAX (32 * 1024)
static int rsnd_preallocate_pages(struct snd_soc_pcm_runtime *rtd,
struct rsnd_dai_stream *io,
int stream)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct device *dev = rsnd_priv_to_dev(priv);
struct snd_pcm_substream *substream;
/*
* use Audio-DMAC dev if we can use IPMMU
* see
* rsnd_dmaen_attach()
*/
if (io->dmac_dev)
dev = io->dmac_dev;
for (substream = rtd->pcm->streams[stream].substream;
substream;
substream = substream->next) {
snd_pcm_set_managed_buffer(substream,
SNDRV_DMA_TYPE_DEV,
dev,
PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
}
return 0;
}
static int rsnd_soc_dai_pcm_new(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai)
{
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
int ret;
ret = rsnd_dai_call(pcm_new, &rdai->playback, rtd);
if (ret)
return ret;
ret = rsnd_dai_call(pcm_new, &rdai->capture, rtd);
if (ret)
return ret;
ret = rsnd_preallocate_pages(rtd, &rdai->playback,
SNDRV_PCM_STREAM_PLAYBACK);
if (ret)
return ret;
ret = rsnd_preallocate_pages(rtd, &rdai->capture,
SNDRV_PCM_STREAM_CAPTURE);
if (ret)
return ret;
return 0;
}
static const struct snd_soc_dai_ops rsnd_soc_dai_ops = {
.pcm_new = rsnd_soc_dai_pcm_new,
.startup = rsnd_soc_dai_startup,
.shutdown = rsnd_soc_dai_shutdown,
.trigger = rsnd_soc_dai_trigger,
.set_fmt = rsnd_soc_dai_set_fmt,
.set_tdm_slot = rsnd_soc_set_dai_tdm_slot,
.prepare = rsnd_soc_dai_prepare,
.auto_selectable_formats = rsnd_soc_dai_formats,
.num_auto_selectable_formats = ARRAY_SIZE(rsnd_soc_dai_formats),
};
static void __rsnd_dai_probe(struct rsnd_priv *priv,
struct device_node *dai_np,
struct device_node *node_np,
uint32_t node_arg,
int dai_i)
{
struct rsnd_dai_stream *io_playback;
struct rsnd_dai_stream *io_capture;
struct snd_soc_dai_driver *drv;
struct rsnd_dai *rdai;
struct device *dev = rsnd_priv_to_dev(priv);
int playback_exist = 0, capture_exist = 0;
int io_i;
rdai = rsnd_rdai_get(priv, dai_i);
drv = rsnd_daidrv_get(priv, dai_i);
io_playback = &rdai->playback;
io_capture = &rdai->capture;
snprintf(rdai->name, RSND_DAI_NAME_SIZE, "rsnd-dai.%d", dai_i);
/* for multi Component */
rdai->dai_args.np = node_np;
rdai->dai_args.args_count = 1;
rdai->dai_args.args[0] = node_arg;
rdai->priv = priv;
drv->name = rdai->name;
drv->ops = &rsnd_soc_dai_ops;
drv->id = dai_i;
drv->dai_args = &rdai->dai_args;
io_playback->rdai = rdai;
io_capture->rdai = rdai;
rsnd_rdai_channels_set(rdai, 2); /* default 2ch */
rsnd_rdai_ssi_lane_set(rdai, 1); /* default 1lane */
rsnd_rdai_width_set(rdai, 32); /* default 32bit width */
for (io_i = 0;; io_i++) {
struct device_node *playback = of_parse_phandle(dai_np, "playback", io_i);
struct device_node *capture = of_parse_phandle(dai_np, "capture", io_i);
if (!playback && !capture)
break;
if (io_i == 0) {
/* check whether playback/capture property exists */
if (playback)
playback_exist = 1;
if (capture)
capture_exist = 1;
}
rsnd_parse_connect_ssi(rdai, playback, capture);
rsnd_parse_connect_ssiu(rdai, playback, capture);
rsnd_parse_connect_src(rdai, playback, capture);
rsnd_parse_connect_ctu(rdai, playback, capture);
rsnd_parse_connect_mix(rdai, playback, capture);
rsnd_parse_connect_dvc(rdai, playback, capture);
of_node_put(playback);
of_node_put(capture);
}
if (playback_exist) {
snprintf(io_playback->name, RSND_DAI_NAME_SIZE, "DAI%d Playback", dai_i);
drv->playback.rates = RSND_RATES;
drv->playback.formats = RSND_FMTS;
drv->playback.channels_min = 2;
drv->playback.channels_max = 8;
drv->playback.stream_name = io_playback->name;
}
if (capture_exist) {
snprintf(io_capture->name, RSND_DAI_NAME_SIZE, "DAI%d Capture", dai_i);
drv->capture.rates = RSND_RATES;
drv->capture.formats = RSND_FMTS;
drv->capture.channels_min = 2;
drv->capture.channels_max = 8;
drv->capture.stream_name = io_capture->name;
}
if (rsnd_ssi_is_pin_sharing(io_capture) ||
rsnd_ssi_is_pin_sharing(io_playback)) {
/* should have symmetric_rate if pin sharing */
drv->symmetric_rate = 1;
}
dev_dbg(dev, "%s (%s/%s)\n", rdai->name,
rsnd_io_to_mod_ssi(io_playback) ? "play" : " -- ",
rsnd_io_to_mod_ssi(io_capture) ? "capture" : " -- ");
}
static int rsnd_dai_probe(struct rsnd_priv *priv)
{
struct snd_soc_dai_driver *rdrv;
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np = dev->of_node;
struct rsnd_dai *rdai;
int nr = 0;
int is_graph;
int dai_i;
nr = rsnd_dai_of_node(priv, &is_graph);
if (!nr)
return -EINVAL;
rdrv = devm_kcalloc(dev, nr, sizeof(*rdrv), GFP_KERNEL);
rdai = devm_kcalloc(dev, nr, sizeof(*rdai), GFP_KERNEL);
if (!rdrv || !rdai)
return -ENOMEM;
priv->rdai_nr = nr;
priv->daidrv = rdrv;
priv->rdai = rdai;
/*
* parse all dai
*/
dai_i = 0;
if (is_graph) {
struct device_node *ports;
struct device_node *dai_np;
for_each_child_of_node(np, ports) {
if (!of_node_name_eq(ports, "ports") &&
!of_node_name_eq(ports, "port"))
continue;
for_each_endpoint_of_node(ports, dai_np) {
__rsnd_dai_probe(priv, dai_np, dai_np, 0, dai_i);
if (rsnd_is_gen3(priv) || rsnd_is_gen4(priv)) {
rdai = rsnd_rdai_get(priv, dai_i);
rsnd_parse_connect_graph(priv, &rdai->playback, dai_np);
rsnd_parse_connect_graph(priv, &rdai->capture, dai_np);
}
dai_i++;
}
}
} else {
struct device_node *node;
struct device_node *dai_np;
for_each_child_of_node(np, node) {
if (!of_node_name_eq(node, RSND_NODE_DAI))
continue;
for_each_child_of_node(node, dai_np) {
__rsnd_dai_probe(priv, dai_np, np, dai_i, dai_i);
if (rsnd_is_gen3(priv) || rsnd_is_gen4(priv)) {
rdai = rsnd_rdai_get(priv, dai_i);
rsnd_parse_connect_simple(priv, &rdai->playback, dai_np);
rsnd_parse_connect_simple(priv, &rdai->capture, dai_np);
}
dai_i++;
}
}
}
return 0;
}
/*
* pcm ops
*/
static int rsnd_hw_update(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_soc_dai *dai = rsnd_substream_to_dai(substream);
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
struct rsnd_priv *priv = rsnd_io_to_priv(io);
unsigned long flags;
int ret;
spin_lock_irqsave(&priv->lock, flags);
if (hw_params)
ret = rsnd_dai_call(hw_params, io, substream, hw_params);
else
ret = rsnd_dai_call(hw_free, io, substream);
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
static int rsnd_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_soc_dai *dai = rsnd_substream_to_dai(substream);
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
struct snd_soc_pcm_runtime *fe = asoc_substream_to_rtd(substream);
/*
* rsnd assumes that it might be used under DPCM if user want to use
* channel / rate convert. Then, rsnd should be FE.
* And then, this function will be called *after* BE settings.
* this means, each BE already has fixuped hw_params.
* see
* dpcm_fe_dai_hw_params()
* dpcm_be_dai_hw_params()
*/
io->converted_rate = 0;
io->converted_chan = 0;
if (fe->dai_link->dynamic) {
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct device *dev = rsnd_priv_to_dev(priv);
struct snd_soc_dpcm *dpcm;
int stream = substream->stream;
for_each_dpcm_be(fe, stream, dpcm) {
struct snd_soc_pcm_runtime *be = dpcm->be;
struct snd_pcm_hw_params *be_params = &be->dpcm[stream].hw_params;
if (params_channels(hw_params) != params_channels(be_params))
io->converted_chan = params_channels(be_params);
if (params_rate(hw_params) != params_rate(be_params))
io->converted_rate = params_rate(be_params);
}
if (io->converted_chan)
dev_dbg(dev, "convert channels = %d\n", io->converted_chan);
if (io->converted_rate) {
/*
* SRC supports convert rates from params_rate(hw_params)/k_down
* to params_rate(hw_params)*k_up, where k_up is always 6, and
* k_down depends on number of channels and SRC unit.
* So all SRC units can upsample audio up to 6 times regardless
* its number of channels. And all SRC units can downsample
* 2 channel audio up to 6 times too.
*/
int k_up = 6;
int k_down = 6;
int channel;
struct rsnd_mod *src_mod = rsnd_io_to_mod_src(io);
dev_dbg(dev, "convert rate = %d\n", io->converted_rate);
channel = io->converted_chan ? io->converted_chan :
params_channels(hw_params);
switch (rsnd_mod_id(src_mod)) {
/*
* SRC0 can downsample 4, 6 and 8 channel audio up to 4 times.
* SRC1, SRC3 and SRC4 can downsample 4 channel audio
* up to 4 times.
* SRC1, SRC3 and SRC4 can downsample 6 and 8 channel audio
* no more than twice.
*/
case 1:
case 3:
case 4:
if (channel > 4) {
k_down = 2;
break;
}
fallthrough;
case 0:
if (channel > 2)
k_down = 4;
break;
/* Other SRC units do not support more than 2 channels */
default:
if (channel > 2)
return -EINVAL;
}
if (params_rate(hw_params) > io->converted_rate * k_down) {
hw_param_interval(hw_params, SNDRV_PCM_HW_PARAM_RATE)->min =
io->converted_rate * k_down;
hw_param_interval(hw_params, SNDRV_PCM_HW_PARAM_RATE)->max =
io->converted_rate * k_down;
hw_params->cmask |= SNDRV_PCM_HW_PARAM_RATE;
} else if (params_rate(hw_params) * k_up < io->converted_rate) {
hw_param_interval(hw_params, SNDRV_PCM_HW_PARAM_RATE)->min =
DIV_ROUND_UP(io->converted_rate, k_up);
hw_param_interval(hw_params, SNDRV_PCM_HW_PARAM_RATE)->max =
DIV_ROUND_UP(io->converted_rate, k_up);
hw_params->cmask |= SNDRV_PCM_HW_PARAM_RATE;
}
/*
* TBD: Max SRC input and output rates also depend on number
* of channels and SRC unit:
* SRC1, SRC3 and SRC4 do not support more than 128kHz
* for 6 channel and 96kHz for 8 channel audio.
* Perhaps this function should return EINVAL if the input or
* the output rate exceeds the limitation.
*/
}
}
return rsnd_hw_update(substream, hw_params);
}
static int rsnd_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
return rsnd_hw_update(substream, NULL);
}
static snd_pcm_uframes_t rsnd_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_dai *dai = rsnd_substream_to_dai(substream);
struct rsnd_dai *rdai = rsnd_dai_to_rdai(dai);
struct rsnd_dai_stream *io = rsnd_rdai_to_io(rdai, substream);
snd_pcm_uframes_t pointer = 0;
rsnd_dai_call(pointer, io, &pointer);
return pointer;
}
/*
* snd_kcontrol
*/
static int rsnd_kctrl_info(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_info *uinfo)
{
struct rsnd_kctrl_cfg *cfg = snd_kcontrol_chip(kctrl);
if (cfg->texts) {
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = cfg->size;
uinfo->value.enumerated.items = cfg->max;
if (uinfo->value.enumerated.item >= cfg->max)
uinfo->value.enumerated.item = cfg->max - 1;
strscpy(uinfo->value.enumerated.name,
cfg->texts[uinfo->value.enumerated.item],
sizeof(uinfo->value.enumerated.name));
} else {
uinfo->count = cfg->size;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = cfg->max;
uinfo->type = (cfg->max == 1) ?
SNDRV_CTL_ELEM_TYPE_BOOLEAN :
SNDRV_CTL_ELEM_TYPE_INTEGER;
}
return 0;
}
static int rsnd_kctrl_get(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_value *uc)
{
struct rsnd_kctrl_cfg *cfg = snd_kcontrol_chip(kctrl);
int i;
for (i = 0; i < cfg->size; i++)
if (cfg->texts)
uc->value.enumerated.item[i] = cfg->val[i];
else
uc->value.integer.value[i] = cfg->val[i];
return 0;
}
static int rsnd_kctrl_put(struct snd_kcontrol *kctrl,
struct snd_ctl_elem_value *uc)
{
struct rsnd_kctrl_cfg *cfg = snd_kcontrol_chip(kctrl);
int i, change = 0;
if (!cfg->accept(cfg->io))
return 0;
for (i = 0; i < cfg->size; i++) {
if (cfg->texts) {
change |= (uc->value.enumerated.item[i] != cfg->val[i]);
cfg->val[i] = uc->value.enumerated.item[i];
} else {
change |= (uc->value.integer.value[i] != cfg->val[i]);
cfg->val[i] = uc->value.integer.value[i];
}
}
if (change && cfg->update)
cfg->update(cfg->io, cfg->mod);
return change;
}
int rsnd_kctrl_accept_anytime(struct rsnd_dai_stream *io)
{
return 1;
}
int rsnd_kctrl_accept_runtime(struct rsnd_dai_stream *io)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct device *dev = rsnd_priv_to_dev(priv);
if (!runtime) {
dev_warn(dev, "Can't update kctrl when idle\n");
return 0;
}
return 1;
}
struct rsnd_kctrl_cfg *rsnd_kctrl_init_m(struct rsnd_kctrl_cfg_m *cfg)
{
cfg->cfg.val = cfg->val;
return &cfg->cfg;
}
struct rsnd_kctrl_cfg *rsnd_kctrl_init_s(struct rsnd_kctrl_cfg_s *cfg)
{
cfg->cfg.val = &cfg->val;
return &cfg->cfg;
}
const char * const volume_ramp_rate[] = {
"128 dB/1 step", /* 00000 */
"64 dB/1 step", /* 00001 */
"32 dB/1 step", /* 00010 */
"16 dB/1 step", /* 00011 */
"8 dB/1 step", /* 00100 */
"4 dB/1 step", /* 00101 */
"2 dB/1 step", /* 00110 */
"1 dB/1 step", /* 00111 */
"0.5 dB/1 step", /* 01000 */
"0.25 dB/1 step", /* 01001 */
"0.125 dB/1 step", /* 01010 = VOLUME_RAMP_MAX_MIX */
"0.125 dB/2 steps", /* 01011 */
"0.125 dB/4 steps", /* 01100 */
"0.125 dB/8 steps", /* 01101 */
"0.125 dB/16 steps", /* 01110 */
"0.125 dB/32 steps", /* 01111 */
"0.125 dB/64 steps", /* 10000 */
"0.125 dB/128 steps", /* 10001 */
"0.125 dB/256 steps", /* 10010 */
"0.125 dB/512 steps", /* 10011 */
"0.125 dB/1024 steps", /* 10100 */
"0.125 dB/2048 steps", /* 10101 */
"0.125 dB/4096 steps", /* 10110 */
"0.125 dB/8192 steps", /* 10111 = VOLUME_RAMP_MAX_DVC */
};
int rsnd_kctrl_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd,
const unsigned char *name,
int (*accept)(struct rsnd_dai_stream *io),
void (*update)(struct rsnd_dai_stream *io,
struct rsnd_mod *mod),
struct rsnd_kctrl_cfg *cfg,
const char * const *texts,
int size,
u32 max)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_kcontrol *kctrl;
struct snd_kcontrol_new knew = {
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = name,
.info = rsnd_kctrl_info,
.index = rtd->num,
.get = rsnd_kctrl_get,
.put = rsnd_kctrl_put,
};
int ret;
/*
* 1) Avoid duplicate register for DVC with MIX case
* 2) Allow duplicate register for MIX
* 3) re-register if card was rebinded
*/
list_for_each_entry(kctrl, &card->controls, list) {
struct rsnd_kctrl_cfg *c = kctrl->private_data;
if (c == cfg)
return 0;
}
if (size > RSND_MAX_CHANNELS)
return -EINVAL;
kctrl = snd_ctl_new1(&knew, cfg);
if (!kctrl)
return -ENOMEM;
ret = snd_ctl_add(card, kctrl);
if (ret < 0)
return ret;
cfg->texts = texts;
cfg->max = max;
cfg->size = size;
cfg->accept = accept;
cfg->update = update;
cfg->card = card;
cfg->kctrl = kctrl;
cfg->io = io;
cfg->mod = mod;
return 0;
}
/*
* snd_soc_component
*/
static const struct snd_soc_component_driver rsnd_soc_component = {
.name = "rsnd",
.probe = rsnd_debugfs_probe,
.hw_params = rsnd_hw_params,
.hw_free = rsnd_hw_free,
.pointer = rsnd_pointer,
.legacy_dai_naming = 1,
};
static int rsnd_rdai_continuance_probe(struct rsnd_priv *priv,
struct rsnd_dai_stream *io)
{
int ret;
ret = rsnd_dai_call(probe, io, priv);
if (ret == -EAGAIN) {
struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
struct rsnd_mod *mod;
int i;
/*
* Fallback to PIO mode
*/
/*
* call "remove" for SSI/SRC/DVC
* SSI will be switch to PIO mode if it was DMA mode
* see
* rsnd_dma_init()
* rsnd_ssi_fallback()
*/
rsnd_dai_call(remove, io, priv);
/*
* remove all mod from io
* and, re connect ssi
*/
for_each_rsnd_mod(i, mod, io)
rsnd_dai_disconnect(mod, io, i);
rsnd_dai_connect(ssi_mod, io, RSND_MOD_SSI);
/*
* fallback
*/
rsnd_dai_call(fallback, io, priv);
/*
* retry to "probe".
* DAI has SSI which is PIO mode only now.
*/
ret = rsnd_dai_call(probe, io, priv);
}
return ret;
}
/*
* rsnd probe
*/
static int rsnd_probe(struct platform_device *pdev)
{
struct rsnd_priv *priv;
struct device *dev = &pdev->dev;
struct rsnd_dai *rdai;
int (*probe_func[])(struct rsnd_priv *priv) = {
rsnd_gen_probe,
rsnd_dma_probe,
rsnd_ssi_probe,
rsnd_ssiu_probe,
rsnd_src_probe,
rsnd_ctu_probe,
rsnd_mix_probe,
rsnd_dvc_probe,
rsnd_cmd_probe,
rsnd_adg_probe,
rsnd_dai_probe,
};
int ret, i;
int ci;
/*
* init priv data
*/
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENODEV;
priv->pdev = pdev;
priv->flags = (unsigned long)of_device_get_match_data(dev);
spin_lock_init(&priv->lock);
/*
* init each module
*/
for (i = 0; i < ARRAY_SIZE(probe_func); i++) {
ret = probe_func[i](priv);
if (ret)
return ret;
}
for_each_rsnd_dai(rdai, priv, i) {
ret = rsnd_rdai_continuance_probe(priv, &rdai->playback);
if (ret)
goto exit_snd_probe;
ret = rsnd_rdai_continuance_probe(priv, &rdai->capture);
if (ret)
goto exit_snd_probe;
}
dev_set_drvdata(dev, priv);
/*
* asoc register
*/
ci = 0;
for (i = 0; priv->component_dais[i] > 0; i++) {
int nr = priv->component_dais[i];
ret = devm_snd_soc_register_component(dev, &rsnd_soc_component,
priv->daidrv + ci, nr);
if (ret < 0) {
dev_err(dev, "cannot snd component register\n");
goto exit_snd_probe;
}
ci += nr;
}
pm_runtime_enable(dev);
dev_info(dev, "probed\n");
return ret;
exit_snd_probe:
for_each_rsnd_dai(rdai, priv, i) {
rsnd_dai_call(remove, &rdai->playback, priv);
rsnd_dai_call(remove, &rdai->capture, priv);
}
/*
* adg is very special mod which can't use rsnd_dai_call(remove),
* and it registers ADG clock on probe.
* It should be unregister if probe failed.
* Mainly it is assuming -EPROBE_DEFER case
*/
rsnd_adg_remove(priv);
return ret;
}
static void rsnd_remove(struct platform_device *pdev)
{
struct rsnd_priv *priv = dev_get_drvdata(&pdev->dev);
struct rsnd_dai *rdai;
void (*remove_func[])(struct rsnd_priv *priv) = {
rsnd_ssi_remove,
rsnd_ssiu_remove,
rsnd_src_remove,
rsnd_ctu_remove,
rsnd_mix_remove,
rsnd_dvc_remove,
rsnd_cmd_remove,
rsnd_adg_remove,
};
int i;
pm_runtime_disable(&pdev->dev);
for_each_rsnd_dai(rdai, priv, i) {
int ret;
ret = rsnd_dai_call(remove, &rdai->playback, priv);
if (ret)
dev_warn(&pdev->dev, "Failed to remove playback dai #%d\n", i);
ret = rsnd_dai_call(remove, &rdai->capture, priv);
if (ret)
dev_warn(&pdev->dev, "Failed to remove capture dai #%d\n", i);
}
for (i = 0; i < ARRAY_SIZE(remove_func); i++)
remove_func[i](priv);
}
static int __maybe_unused rsnd_suspend(struct device *dev)
{
struct rsnd_priv *priv = dev_get_drvdata(dev);
rsnd_adg_clk_disable(priv);
return 0;
}
static int __maybe_unused rsnd_resume(struct device *dev)
{
struct rsnd_priv *priv = dev_get_drvdata(dev);
rsnd_adg_clk_enable(priv);
return 0;
}
static const struct dev_pm_ops rsnd_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(rsnd_suspend, rsnd_resume)
};
static struct platform_driver rsnd_driver = {
.driver = {
.name = "rcar_sound",
.pm = &rsnd_pm_ops,
.of_match_table = rsnd_of_match,
},
.probe = rsnd_probe,
.remove_new = rsnd_remove,
};
module_platform_driver(rsnd_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas R-Car audio driver");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
MODULE_ALIAS("platform:rcar-pcm-audio");
| linux-master | sound/soc/sh/rcar/core.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car Audio DMAC support
//
// Copyright (C) 2015 Renesas Electronics Corp.
// Copyright (c) 2015 Kuninori Morimoto <[email protected]>
#include <linux/delay.h>
#include <linux/of_dma.h>
#include "rsnd.h"
/*
* Audio DMAC peri peri register
*/
#define PDMASAR 0x00
#define PDMADAR 0x04
#define PDMACHCR 0x0c
/* PDMACHCR */
#define PDMACHCR_DE (1 << 0)
struct rsnd_dmaen {
struct dma_chan *chan;
dma_cookie_t cookie;
unsigned int dma_len;
};
struct rsnd_dmapp {
int dmapp_id;
u32 chcr;
};
struct rsnd_dma {
struct rsnd_mod mod;
struct rsnd_mod *mod_from;
struct rsnd_mod *mod_to;
dma_addr_t src_addr;
dma_addr_t dst_addr;
union {
struct rsnd_dmaen en;
struct rsnd_dmapp pp;
} dma;
};
struct rsnd_dma_ctrl {
void __iomem *ppbase;
phys_addr_t ppres;
int dmaen_num;
int dmapp_num;
};
#define rsnd_priv_to_dmac(p) ((struct rsnd_dma_ctrl *)(p)->dma)
#define rsnd_mod_to_dma(_mod) container_of((_mod), struct rsnd_dma, mod)
#define rsnd_dma_to_dmaen(dma) (&(dma)->dma.en)
#define rsnd_dma_to_dmapp(dma) (&(dma)->dma.pp)
/* for DEBUG */
static struct rsnd_mod_ops mem_ops = {
.name = "mem",
};
static struct rsnd_mod mem = {
};
/*
* Audio DMAC
*/
static void __rsnd_dmaen_complete(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
if (rsnd_io_is_working(io))
rsnd_dai_period_elapsed(io);
}
static void rsnd_dmaen_complete(void *data)
{
struct rsnd_mod *mod = data;
rsnd_mod_interrupt(mod, __rsnd_dmaen_complete);
}
static struct dma_chan *rsnd_dmaen_request_channel(struct rsnd_dai_stream *io,
struct rsnd_mod *mod_from,
struct rsnd_mod *mod_to)
{
if ((!mod_from && !mod_to) ||
(mod_from && mod_to))
return NULL;
if (mod_from)
return rsnd_mod_dma_req(io, mod_from);
else
return rsnd_mod_dma_req(io, mod_to);
}
static int rsnd_dmaen_stop(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
if (dmaen->chan)
dmaengine_terminate_async(dmaen->chan);
return 0;
}
static int rsnd_dmaen_cleanup(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
/*
* DMAEngine release uses mutex lock.
* Thus, it shouldn't be called under spinlock.
* Let's call it under prepare
*/
if (dmaen->chan)
dma_release_channel(dmaen->chan);
dmaen->chan = NULL;
return 0;
}
static int rsnd_dmaen_prepare(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
struct device *dev = rsnd_priv_to_dev(priv);
/* maybe suspended */
if (dmaen->chan)
return 0;
/*
* DMAEngine request uses mutex lock.
* Thus, it shouldn't be called under spinlock.
* Let's call it under prepare
*/
dmaen->chan = rsnd_dmaen_request_channel(io,
dma->mod_from,
dma->mod_to);
if (IS_ERR_OR_NULL(dmaen->chan)) {
dmaen->chan = NULL;
dev_err(dev, "can't get dma channel\n");
return -EIO;
}
return 0;
}
static int rsnd_dmaen_start(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
struct snd_pcm_substream *substream = io->substream;
struct device *dev = rsnd_priv_to_dev(priv);
struct dma_async_tx_descriptor *desc;
struct dma_slave_config cfg = {};
enum dma_slave_buswidth buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
int is_play = rsnd_io_is_play(io);
int ret;
/*
* in case of monaural data writing or reading through Audio-DMAC
* data is always in Left Justified format, so both src and dst
* DMA Bus width need to be set equal to physical data width.
*/
if (rsnd_runtime_channel_original(io) == 1) {
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
int bits = snd_pcm_format_physical_width(runtime->format);
switch (bits) {
case 8:
buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
break;
case 16:
buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
case 32:
buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
break;
default:
dev_err(dev, "invalid format width %d\n", bits);
return -EINVAL;
}
}
cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
cfg.src_addr = dma->src_addr;
cfg.dst_addr = dma->dst_addr;
cfg.src_addr_width = buswidth;
cfg.dst_addr_width = buswidth;
dev_dbg(dev, "%s %pad -> %pad\n",
rsnd_mod_name(mod),
&cfg.src_addr, &cfg.dst_addr);
ret = dmaengine_slave_config(dmaen->chan, &cfg);
if (ret < 0)
return ret;
desc = dmaengine_prep_dma_cyclic(dmaen->chan,
substream->runtime->dma_addr,
snd_pcm_lib_buffer_bytes(substream),
snd_pcm_lib_period_bytes(substream),
is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(dev, "dmaengine_prep_slave_sg() fail\n");
return -EIO;
}
desc->callback = rsnd_dmaen_complete;
desc->callback_param = rsnd_mod_get(dma);
dmaen->dma_len = snd_pcm_lib_buffer_bytes(substream);
dmaen->cookie = dmaengine_submit(desc);
if (dmaen->cookie < 0) {
dev_err(dev, "dmaengine_submit() fail\n");
return -EIO;
}
dma_async_issue_pending(dmaen->chan);
return 0;
}
struct dma_chan *rsnd_dma_request_channel(struct device_node *of_node, char *name,
struct rsnd_mod *mod, char *x)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct dma_chan *chan = NULL;
struct device_node *np;
int i = 0;
for_each_child_of_node(of_node, np) {
i = rsnd_node_fixed_index(dev, np, name, i);
if (i < 0) {
chan = NULL;
of_node_put(np);
break;
}
if (i == rsnd_mod_id_raw(mod) && (!chan))
chan = of_dma_request_slave_channel(np, x);
i++;
}
/* It should call of_node_put(), since, it is rsnd_xxx_of_node() */
of_node_put(of_node);
return chan;
}
static int rsnd_dmaen_attach(struct rsnd_dai_stream *io,
struct rsnd_dma *dma,
struct rsnd_mod *mod_from, struct rsnd_mod *mod_to)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
struct dma_chan *chan;
/* try to get DMAEngine channel */
chan = rsnd_dmaen_request_channel(io, mod_from, mod_to);
if (IS_ERR_OR_NULL(chan)) {
/* Let's follow when -EPROBE_DEFER case */
if (PTR_ERR(chan) == -EPROBE_DEFER)
return PTR_ERR(chan);
/*
* DMA failed. try to PIO mode
* see
* rsnd_ssi_fallback()
* rsnd_rdai_continuance_probe()
*/
return -EAGAIN;
}
/*
* use it for IPMMU if needed
* see
* rsnd_preallocate_pages()
*/
io->dmac_dev = chan->device->dev;
dma_release_channel(chan);
dmac->dmaen_num++;
return 0;
}
static int rsnd_dmaen_pointer(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
snd_pcm_uframes_t *pointer)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmaen *dmaen = rsnd_dma_to_dmaen(dma);
struct dma_tx_state state;
enum dma_status status;
unsigned int pos = 0;
status = dmaengine_tx_status(dmaen->chan, dmaen->cookie, &state);
if (status == DMA_IN_PROGRESS || status == DMA_PAUSED) {
if (state.residue > 0 && state.residue <= dmaen->dma_len)
pos = dmaen->dma_len - state.residue;
}
*pointer = bytes_to_frames(runtime, pos);
return 0;
}
static struct rsnd_mod_ops rsnd_dmaen_ops = {
.name = "audmac",
.prepare = rsnd_dmaen_prepare,
.cleanup = rsnd_dmaen_cleanup,
.start = rsnd_dmaen_start,
.stop = rsnd_dmaen_stop,
.pointer = rsnd_dmaen_pointer,
.get_status = rsnd_mod_get_status,
};
/*
* Audio DMAC peri peri
*/
static const u8 gen2_id_table_ssiu[] = {
/* SSI00 ~ SSI07 */
0x00, 0x01, 0x02, 0x03, 0x39, 0x3a, 0x3b, 0x3c,
/* SSI10 ~ SSI17 */
0x04, 0x05, 0x06, 0x07, 0x3d, 0x3e, 0x3f, 0x40,
/* SSI20 ~ SSI27 */
0x08, 0x09, 0x0a, 0x0b, 0x41, 0x42, 0x43, 0x44,
/* SSI30 ~ SSI37 */
0x0c, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b,
/* SSI40 ~ SSI47 */
0x0d, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52,
/* SSI5 */
0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* SSI6 */
0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* SSI7 */
0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* SSI8 */
0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* SSI90 ~ SSI97 */
0x12, 0x13, 0x14, 0x15, 0x53, 0x54, 0x55, 0x56,
};
static const u8 gen2_id_table_scu[] = {
0x2d, /* SCU_SRCI0 */
0x2e, /* SCU_SRCI1 */
0x2f, /* SCU_SRCI2 */
0x30, /* SCU_SRCI3 */
0x31, /* SCU_SRCI4 */
0x32, /* SCU_SRCI5 */
0x33, /* SCU_SRCI6 */
0x34, /* SCU_SRCI7 */
0x35, /* SCU_SRCI8 */
0x36, /* SCU_SRCI9 */
};
static const u8 gen2_id_table_cmd[] = {
0x37, /* SCU_CMD0 */
0x38, /* SCU_CMD1 */
};
static u32 rsnd_dmapp_get_id(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_mod *ssi = rsnd_io_to_mod_ssi(io);
struct rsnd_mod *ssiu = rsnd_io_to_mod_ssiu(io);
struct rsnd_mod *src = rsnd_io_to_mod_src(io);
struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io);
const u8 *entry = NULL;
int id = 255;
int size = 0;
if ((mod == ssi) ||
(mod == ssiu)) {
int busif = rsnd_mod_id_sub(ssiu);
entry = gen2_id_table_ssiu;
size = ARRAY_SIZE(gen2_id_table_ssiu);
id = (rsnd_mod_id(mod) * 8) + busif;
} else if (mod == src) {
entry = gen2_id_table_scu;
size = ARRAY_SIZE(gen2_id_table_scu);
id = rsnd_mod_id(mod);
} else if (mod == dvc) {
entry = gen2_id_table_cmd;
size = ARRAY_SIZE(gen2_id_table_cmd);
id = rsnd_mod_id(mod);
}
if ((!entry) || (size <= id)) {
struct device *dev = rsnd_priv_to_dev(rsnd_io_to_priv(io));
dev_err(dev, "unknown connection (%s)\n", rsnd_mod_name(mod));
/* use non-prohibited SRS number as error */
return 0x00; /* SSI00 */
}
return entry[id];
}
static u32 rsnd_dmapp_get_chcr(struct rsnd_dai_stream *io,
struct rsnd_mod *mod_from,
struct rsnd_mod *mod_to)
{
return (rsnd_dmapp_get_id(io, mod_from) << 24) +
(rsnd_dmapp_get_id(io, mod_to) << 16);
}
#define rsnd_dmapp_addr(dmac, dma, reg) \
(dmac->ppbase + 0x20 + reg + \
(0x10 * rsnd_dma_to_dmapp(dma)->dmapp_id))
static void rsnd_dmapp_write(struct rsnd_dma *dma, u32 data, u32 reg)
{
struct rsnd_mod *mod = rsnd_mod_get(dma);
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
struct device *dev = rsnd_priv_to_dev(priv);
dev_dbg(dev, "w 0x%px : %08x\n", rsnd_dmapp_addr(dmac, dma, reg), data);
iowrite32(data, rsnd_dmapp_addr(dmac, dma, reg));
}
static u32 rsnd_dmapp_read(struct rsnd_dma *dma, u32 reg)
{
struct rsnd_mod *mod = rsnd_mod_get(dma);
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
return ioread32(rsnd_dmapp_addr(dmac, dma, reg));
}
static void rsnd_dmapp_bset(struct rsnd_dma *dma, u32 data, u32 mask, u32 reg)
{
struct rsnd_mod *mod = rsnd_mod_get(dma);
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
void __iomem *addr = rsnd_dmapp_addr(dmac, dma, reg);
u32 val = ioread32(addr);
val &= ~mask;
val |= (data & mask);
iowrite32(val, addr);
}
static int rsnd_dmapp_stop(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
int i;
rsnd_dmapp_bset(dma, 0, PDMACHCR_DE, PDMACHCR);
for (i = 0; i < 1024; i++) {
if (0 == (rsnd_dmapp_read(dma, PDMACHCR) & PDMACHCR_DE))
return 0;
udelay(1);
}
return -EIO;
}
static int rsnd_dmapp_start(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmapp *dmapp = rsnd_dma_to_dmapp(dma);
rsnd_dmapp_write(dma, dma->src_addr, PDMASAR);
rsnd_dmapp_write(dma, dma->dst_addr, PDMADAR);
rsnd_dmapp_write(dma, dmapp->chcr, PDMACHCR);
return 0;
}
static int rsnd_dmapp_attach(struct rsnd_dai_stream *io,
struct rsnd_dma *dma,
struct rsnd_mod *mod_from, struct rsnd_mod *mod_to)
{
struct rsnd_dmapp *dmapp = rsnd_dma_to_dmapp(dma);
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
struct device *dev = rsnd_priv_to_dev(priv);
dmapp->dmapp_id = dmac->dmapp_num;
dmapp->chcr = rsnd_dmapp_get_chcr(io, mod_from, mod_to) | PDMACHCR_DE;
dmac->dmapp_num++;
dev_dbg(dev, "id/src/dst/chcr = %d/%pad/%pad/%08x\n",
dmapp->dmapp_id, &dma->src_addr, &dma->dst_addr, dmapp->chcr);
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_dmapp_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
struct rsnd_dma *dma = rsnd_mod_to_dma(mod);
struct rsnd_dmapp *dmapp = rsnd_dma_to_dmapp(dma);
rsnd_debugfs_reg_show(m, dmac->ppres, dmac->ppbase,
0x20 + 0x10 * dmapp->dmapp_id, 0x10);
}
#define DEBUG_INFO .debug_info = rsnd_dmapp_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_dmapp_ops = {
.name = "audmac-pp",
.start = rsnd_dmapp_start,
.stop = rsnd_dmapp_stop,
.quit = rsnd_dmapp_stop,
.get_status = rsnd_mod_get_status,
DEBUG_INFO
};
/*
* Common DMAC Interface
*/
/*
* DMA read/write register offset
*
* RSND_xxx_I_N for Audio DMAC input
* RSND_xxx_O_N for Audio DMAC output
* RSND_xxx_I_P for Audio DMAC peri peri input
* RSND_xxx_O_P for Audio DMAC peri peri output
*
* ex) R-Car H2 case
* mod / DMAC in / DMAC out / DMAC PP in / DMAC pp out
* SSI : 0xec541000 / 0xec241008 / 0xec24100c
* SSIU: 0xec541000 / 0xec100000 / 0xec100000 / 0xec400000 / 0xec400000
* SCU : 0xec500000 / 0xec000000 / 0xec004000 / 0xec300000 / 0xec304000
* CMD : 0xec500000 / / 0xec008000 0xec308000
*/
#define RDMA_SSI_I_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0x8)
#define RDMA_SSI_O_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0xc)
#define RDMA_SSIU_I_N(addr, i, j) (addr ##_reg - 0x00441000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4)))
#define RDMA_SSIU_O_N(addr, i, j) RDMA_SSIU_I_N(addr, i, j)
#define RDMA_SSIU_I_P(addr, i, j) (addr ##_reg - 0x00141000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4)))
#define RDMA_SSIU_O_P(addr, i, j) RDMA_SSIU_I_P(addr, i, j)
#define RDMA_SRC_I_N(addr, i) (addr ##_reg - 0x00500000 + (0x400 * i))
#define RDMA_SRC_O_N(addr, i) (addr ##_reg - 0x004fc000 + (0x400 * i))
#define RDMA_SRC_I_P(addr, i) (addr ##_reg - 0x00200000 + (0x400 * i))
#define RDMA_SRC_O_P(addr, i) (addr ##_reg - 0x001fc000 + (0x400 * i))
#define RDMA_CMD_O_N(addr, i) (addr ##_reg - 0x004f8000 + (0x400 * i))
#define RDMA_CMD_O_P(addr, i) (addr ##_reg - 0x001f8000 + (0x400 * i))
static dma_addr_t
rsnd_gen2_dma_addr(struct rsnd_dai_stream *io,
struct rsnd_mod *mod,
int is_play, int is_from)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct device *dev = rsnd_priv_to_dev(priv);
phys_addr_t ssi_reg = rsnd_gen_get_phy_addr(priv, RSND_GEN2_SSI);
phys_addr_t src_reg = rsnd_gen_get_phy_addr(priv, RSND_GEN2_SCU);
int is_ssi = !!(rsnd_io_to_mod_ssi(io) == mod) ||
!!(rsnd_io_to_mod_ssiu(io) == mod);
int use_src = !!rsnd_io_to_mod_src(io);
int use_cmd = !!rsnd_io_to_mod_dvc(io) ||
!!rsnd_io_to_mod_mix(io) ||
!!rsnd_io_to_mod_ctu(io);
int id = rsnd_mod_id(mod);
int busif = rsnd_mod_id_sub(rsnd_io_to_mod_ssiu(io));
struct dma_addr {
dma_addr_t out_addr;
dma_addr_t in_addr;
} dma_addrs[3][2][3] = {
/* SRC */
/* Capture */
{{{ 0, 0 },
{ RDMA_SRC_O_N(src, id), RDMA_SRC_I_P(src, id) },
{ RDMA_CMD_O_N(src, id), RDMA_SRC_I_P(src, id) } },
/* Playback */
{{ 0, 0, },
{ RDMA_SRC_O_P(src, id), RDMA_SRC_I_N(src, id) },
{ RDMA_CMD_O_P(src, id), RDMA_SRC_I_N(src, id) } }
},
/* SSI */
/* Capture */
{{{ RDMA_SSI_O_N(ssi, id), 0 },
{ RDMA_SSIU_O_P(ssi, id, busif), 0 },
{ RDMA_SSIU_O_P(ssi, id, busif), 0 } },
/* Playback */
{{ 0, RDMA_SSI_I_N(ssi, id) },
{ 0, RDMA_SSIU_I_P(ssi, id, busif) },
{ 0, RDMA_SSIU_I_P(ssi, id, busif) } }
},
/* SSIU */
/* Capture */
{{{ RDMA_SSIU_O_N(ssi, id, busif), 0 },
{ RDMA_SSIU_O_P(ssi, id, busif), 0 },
{ RDMA_SSIU_O_P(ssi, id, busif), 0 } },
/* Playback */
{{ 0, RDMA_SSIU_I_N(ssi, id, busif) },
{ 0, RDMA_SSIU_I_P(ssi, id, busif) },
{ 0, RDMA_SSIU_I_P(ssi, id, busif) } } },
};
/*
* FIXME
*
* We can't support SSI9-4/5/6/7, because its address is
* out of calculation rule
*/
if ((id == 9) && (busif >= 4))
dev_err(dev, "This driver doesn't support SSI%d-%d, so far",
id, busif);
/* it shouldn't happen */
if (use_cmd && !use_src)
dev_err(dev, "DVC is selected without SRC\n");
/* use SSIU or SSI ? */
if (is_ssi && rsnd_ssi_use_busif(io))
is_ssi++;
return (is_from) ?
dma_addrs[is_ssi][is_play][use_src + use_cmd].out_addr :
dma_addrs[is_ssi][is_play][use_src + use_cmd].in_addr;
}
/*
* Gen4 DMA read/write register offset
*
* ex) R-Car V4H case
* mod / SYS-DMAC in / SYS-DMAC out
* SSI_SDMC: 0xec400000 / 0xec400000 / 0xec400000
*/
#define RDMA_SSI_SDMC(addr, i) (addr + (0x8000 * i))
static dma_addr_t
rsnd_gen4_dma_addr(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
int is_play, int is_from)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
phys_addr_t addr = rsnd_gen_get_phy_addr(priv, RSND_GEN4_SDMC);
int id = rsnd_mod_id(mod);
int busif = rsnd_mod_id_sub(mod);
/*
* SSI0 only is supported
*/
if (id != 0) {
struct device *dev = rsnd_priv_to_dev(priv);
dev_err(dev, "This driver doesn't support non SSI0");
return -EINVAL;
}
return RDMA_SSI_SDMC(addr, busif);
}
static dma_addr_t rsnd_dma_addr(struct rsnd_dai_stream *io,
struct rsnd_mod *mod,
int is_play, int is_from)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
if (!mod)
return 0;
/*
* gen1 uses default DMA addr
*/
if (rsnd_is_gen1(priv))
return 0;
else if (rsnd_is_gen4(priv))
return rsnd_gen4_dma_addr(io, mod, is_play, is_from);
else
return rsnd_gen2_dma_addr(io, mod, is_play, is_from);
}
#define MOD_MAX (RSND_MOD_MAX + 1) /* +Memory */
static void rsnd_dma_of_path(struct rsnd_mod *this,
struct rsnd_dai_stream *io,
int is_play,
struct rsnd_mod **mod_from,
struct rsnd_mod **mod_to)
{
struct rsnd_mod *ssi;
struct rsnd_mod *src = rsnd_io_to_mod_src(io);
struct rsnd_mod *ctu = rsnd_io_to_mod_ctu(io);
struct rsnd_mod *mix = rsnd_io_to_mod_mix(io);
struct rsnd_mod *dvc = rsnd_io_to_mod_dvc(io);
struct rsnd_mod *mod[MOD_MAX];
struct rsnd_mod *mod_start, *mod_end;
struct rsnd_priv *priv = rsnd_mod_to_priv(this);
struct device *dev = rsnd_priv_to_dev(priv);
int nr, i, idx;
/*
* It should use "rcar_sound,ssiu" on DT.
* But, we need to keep compatibility for old version.
*
* If it has "rcar_sound.ssiu", it will be used.
* If not, "rcar_sound.ssi" will be used.
* see
* rsnd_ssiu_dma_req()
* rsnd_ssi_dma_req()
*/
if (rsnd_ssiu_of_node(priv)) {
struct rsnd_mod *ssiu = rsnd_io_to_mod_ssiu(io);
/* use SSIU */
ssi = ssiu;
if (this == rsnd_io_to_mod_ssi(io))
this = ssiu;
} else {
/* keep compatible, use SSI */
ssi = rsnd_io_to_mod_ssi(io);
}
if (!ssi)
return;
nr = 0;
for (i = 0; i < MOD_MAX; i++) {
mod[i] = NULL;
nr += !!rsnd_io_to_mod(io, i);
}
/*
* [S] -*-> [E]
* [S] -*-> SRC -o-> [E]
* [S] -*-> SRC -> DVC -o-> [E]
* [S] -*-> SRC -> CTU -> MIX -> DVC -o-> [E]
*
* playback [S] = mem
* [E] = SSI
*
* capture [S] = SSI
* [E] = mem
*
* -*-> Audio DMAC
* -o-> Audio DMAC peri peri
*/
mod_start = (is_play) ? NULL : ssi;
mod_end = (is_play) ? ssi : NULL;
idx = 0;
mod[idx++] = mod_start;
for (i = 1; i < nr; i++) {
if (src) {
mod[idx++] = src;
src = NULL;
} else if (ctu) {
mod[idx++] = ctu;
ctu = NULL;
} else if (mix) {
mod[idx++] = mix;
mix = NULL;
} else if (dvc) {
mod[idx++] = dvc;
dvc = NULL;
}
}
mod[idx] = mod_end;
/*
* | SSI | SRC |
* -------------+-----+-----+
* is_play | o | * |
* !is_play | * | o |
*/
if ((this == ssi) == (is_play)) {
*mod_from = mod[idx - 1];
*mod_to = mod[idx];
} else {
*mod_from = mod[0];
*mod_to = mod[1];
}
dev_dbg(dev, "module connection (this is %s)\n", rsnd_mod_name(this));
for (i = 0; i <= idx; i++) {
dev_dbg(dev, " %s%s\n",
rsnd_mod_name(mod[i] ? mod[i] : &mem),
(mod[i] == *mod_from) ? " from" :
(mod[i] == *mod_to) ? " to" : "");
}
}
static int rsnd_dma_alloc(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
struct rsnd_mod **dma_mod)
{
struct rsnd_mod *mod_from = NULL;
struct rsnd_mod *mod_to = NULL;
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct rsnd_dma_ctrl *dmac = rsnd_priv_to_dmac(priv);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_dma *dma;
struct rsnd_mod_ops *ops;
enum rsnd_mod_type type;
int (*attach)(struct rsnd_dai_stream *io, struct rsnd_dma *dma,
struct rsnd_mod *mod_from, struct rsnd_mod *mod_to);
int is_play = rsnd_io_is_play(io);
int ret, dma_id;
/*
* DMA failed. try to PIO mode
* see
* rsnd_ssi_fallback()
* rsnd_rdai_continuance_probe()
*/
if (!dmac)
return -EAGAIN;
rsnd_dma_of_path(mod, io, is_play, &mod_from, &mod_to);
/* for Gen2 or later */
if (mod_from && mod_to) {
ops = &rsnd_dmapp_ops;
attach = rsnd_dmapp_attach;
dma_id = dmac->dmapp_num;
type = RSND_MOD_AUDMAPP;
} else {
ops = &rsnd_dmaen_ops;
attach = rsnd_dmaen_attach;
dma_id = dmac->dmaen_num;
type = RSND_MOD_AUDMA;
}
/* for Gen1, overwrite */
if (rsnd_is_gen1(priv)) {
ops = &rsnd_dmaen_ops;
attach = rsnd_dmaen_attach;
dma_id = dmac->dmaen_num;
type = RSND_MOD_AUDMA;
}
dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
if (!dma)
return -ENOMEM;
*dma_mod = rsnd_mod_get(dma);
ret = rsnd_mod_init(priv, *dma_mod, ops, NULL,
type, dma_id);
if (ret < 0)
return ret;
dev_dbg(dev, "%s %s -> %s\n",
rsnd_mod_name(*dma_mod),
rsnd_mod_name(mod_from ? mod_from : &mem),
rsnd_mod_name(mod_to ? mod_to : &mem));
ret = attach(io, dma, mod_from, mod_to);
if (ret < 0)
return ret;
dma->src_addr = rsnd_dma_addr(io, mod_from, is_play, 1);
dma->dst_addr = rsnd_dma_addr(io, mod_to, is_play, 0);
dma->mod_from = mod_from;
dma->mod_to = mod_to;
return 0;
}
int rsnd_dma_attach(struct rsnd_dai_stream *io, struct rsnd_mod *mod,
struct rsnd_mod **dma_mod)
{
if (!(*dma_mod)) {
int ret = rsnd_dma_alloc(io, mod, dma_mod);
if (ret < 0)
return ret;
}
return rsnd_dai_connect(*dma_mod, io, (*dma_mod)->type);
}
int rsnd_dma_probe(struct rsnd_priv *priv)
{
struct platform_device *pdev = rsnd_priv_to_pdev(priv);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_dma_ctrl *dmac;
struct resource *res;
/*
* for Gen1
*/
if (rsnd_is_gen1(priv))
return 0;
/*
* for Gen2 or later
*/
dmac = devm_kzalloc(dev, sizeof(*dmac), GFP_KERNEL);
if (!dmac) {
dev_err(dev, "dma allocate failed\n");
return 0; /* it will be PIO mode */
}
/* for Gen4 doesn't have DMA-pp */
if (rsnd_is_gen4(priv))
goto audmapp_end;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audmapp");
if (!res) {
dev_err(dev, "lack of audmapp in DT\n");
return 0; /* it will be PIO mode */
}
dmac->dmapp_num = 0;
dmac->ppres = res->start;
dmac->ppbase = devm_ioremap_resource(dev, res);
if (IS_ERR(dmac->ppbase))
return PTR_ERR(dmac->ppbase);
audmapp_end:
priv->dma = dmac;
/* dummy mem mod for debug */
return rsnd_mod_init(NULL, &mem, &mem_ops, NULL, 0, 0);
}
| linux-master | sound/soc/sh/rcar/dma.c |
// SPDX-License-Identifier: GPL-2.0
//
// Helper routines for R-Car sound ADG.
//
// Copyright (C) 2013 Kuninori Morimoto <[email protected]>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include "rsnd.h"
#define CLKA 0
#define CLKB 1
#define CLKC 2
#define CLKI 3
#define CLKINMAX 4
#define CLKOUT 0
#define CLKOUT1 1
#define CLKOUT2 2
#define CLKOUT3 3
#define CLKOUTMAX 4
#define BRRx_MASK(x) (0x3FF & x)
static struct rsnd_mod_ops adg_ops = {
.name = "adg",
};
#define ADG_HZ_441 0
#define ADG_HZ_48 1
#define ADG_HZ_SIZE 2
struct rsnd_adg {
struct clk *clkin[CLKINMAX];
struct clk *clkout[CLKOUTMAX];
struct clk *null_clk;
struct clk_onecell_data onecell;
struct rsnd_mod mod;
int clkin_rate[CLKINMAX];
int clkin_size;
int clkout_size;
u32 ckr;
u32 brga;
u32 brgb;
int brg_rate[ADG_HZ_SIZE]; /* BRGA / BRGB */
};
#define for_each_rsnd_clkin(pos, adg, i) \
for (i = 0; \
(i < adg->clkin_size) && \
((pos) = adg->clkin[i]); \
i++)
#define for_each_rsnd_clkout(pos, adg, i) \
for (i = 0; \
(i < adg->clkout_size) && \
((pos) = adg->clkout[i]); \
i++)
#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
static const char * const clkin_name_gen4[] = {
[CLKA] = "clkin",
};
static const char * const clkin_name_gen2[] = {
[CLKA] = "clk_a",
[CLKB] = "clk_b",
[CLKC] = "clk_c",
[CLKI] = "clk_i",
};
static const char * const clkout_name_gen2[] = {
[CLKOUT] = "audio_clkout",
[CLKOUT1] = "audio_clkout1",
[CLKOUT2] = "audio_clkout2",
[CLKOUT3] = "audio_clkout3",
};
static u32 rsnd_adg_calculate_brgx(unsigned long div)
{
int i;
if (!div)
return 0;
for (i = 3; i >= 0; i--) {
int ratio = 2 << (i * 2);
if (0 == (div % ratio))
return (u32)((i << 8) | ((div / ratio) - 1));
}
return ~0;
}
static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
{
struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
int id = rsnd_mod_id(ssi_mod);
int ws = id;
if (rsnd_ssi_is_pin_sharing(io)) {
switch (id) {
case 1:
case 2:
case 9:
ws = 0;
break;
case 4:
ws = 3;
break;
case 8:
ws = 7;
break;
}
}
return (0x6 + ws) << 8;
}
static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
struct rsnd_dai_stream *io,
unsigned int target_rate,
unsigned int *target_val,
unsigned int *target_en)
{
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct device *dev = rsnd_priv_to_dev(priv);
int sel;
unsigned int val, en;
unsigned int min, diff;
unsigned int sel_rate[] = {
adg->clkin_rate[CLKA], /* 0000: CLKA */
adg->clkin_rate[CLKB], /* 0001: CLKB */
adg->clkin_rate[CLKC], /* 0010: CLKC */
adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */
adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */
};
min = ~0;
val = 0;
en = 0;
for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
int idx = 0;
int step = 2;
int div;
if (!sel_rate[sel])
continue;
for (div = 2; div <= 98304; div += step) {
diff = abs(target_rate - sel_rate[sel] / div);
if (min > diff) {
val = (sel << 8) | idx;
min = diff;
en = 1 << (sel + 1); /* fixme */
}
/*
* step of 0_0000 / 0_0001 / 0_1101
* are out of order
*/
if ((idx > 2) && (idx % 2))
step *= 2;
if (idx == 0x1c) {
div += step;
step *= 2;
}
idx++;
}
}
if (min == ~0) {
dev_err(dev, "no Input clock\n");
return;
}
*target_val = val;
if (target_en)
*target_en = en;
}
static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
struct rsnd_dai_stream *io,
unsigned int in_rate,
unsigned int out_rate,
u32 *in, u32 *out, u32 *en)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
unsigned int target_rate;
u32 *target_val;
u32 _in;
u32 _out;
u32 _en;
/* default = SSI WS */
_in =
_out = rsnd_adg_ssi_ws_timing_gen2(io);
target_rate = 0;
target_val = NULL;
_en = 0;
if (runtime->rate != in_rate) {
target_rate = out_rate;
target_val = &_out;
} else if (runtime->rate != out_rate) {
target_rate = in_rate;
target_val = &_in;
}
if (target_rate)
__rsnd_adg_get_timesel_ratio(priv, io,
target_rate,
target_val, &_en);
if (in)
*in = _in;
if (out)
*out = _out;
if (en)
*en = _en;
}
int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
struct rsnd_dai_stream *io)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
int id = rsnd_mod_id(cmd_mod);
int shift = (id % 2) ? 16 : 0;
u32 mask, val;
rsnd_adg_get_timesel_ratio(priv, io,
rsnd_src_get_in_rate(priv, io),
rsnd_src_get_out_rate(priv, io),
NULL, &val, NULL);
val = val << shift;
mask = 0x0f1f << shift;
rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
return 0;
}
int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
struct rsnd_dai_stream *io,
unsigned int in_rate,
unsigned int out_rate)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
u32 in, out;
u32 mask, en;
int id = rsnd_mod_id(src_mod);
int shift = (id % 2) ? 16 : 0;
rsnd_mod_confirm_src(src_mod);
rsnd_adg_get_timesel_ratio(priv, io,
in_rate, out_rate,
&in, &out, &en);
in = in << shift;
out = out << shift;
mask = 0x0f1f << shift;
rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
if (en)
rsnd_mod_bset(adg_mod, DIV_EN, en, en);
return 0;
}
static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
struct device *dev = rsnd_priv_to_dev(priv);
int id = rsnd_mod_id(ssi_mod);
int shift = (id % 4) * 8;
u32 mask = 0xFF << shift;
rsnd_mod_confirm_ssi(ssi_mod);
val = val << shift;
/*
* SSI 8 is not connected to ADG.
* it works with SSI 7
*/
if (id == 8)
return;
rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
}
int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
{
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct clk *clk;
int i;
int sel_table[] = {
[CLKA] = 0x1,
[CLKB] = 0x2,
[CLKC] = 0x3,
[CLKI] = 0x0,
};
/*
* find suitable clock from
* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
*/
for_each_rsnd_clkin(clk, adg, i)
if (rate == adg->clkin_rate[i])
return sel_table[i];
/*
* find divided clock from BRGA/BRGB
*/
if (rate == adg->brg_rate[ADG_HZ_441])
return 0x10;
if (rate == adg->brg_rate[ADG_HZ_48])
return 0x20;
return -EIO;
}
int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
{
rsnd_adg_set_ssi_clk(ssi_mod, 0);
return 0;
}
int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
int data;
u32 ckr = 0;
data = rsnd_adg_clk_query(priv, rate);
if (data < 0)
return data;
rsnd_adg_set_ssi_clk(ssi_mod, data);
if (0 == (rate % 8000))
ckr = 0x80000000; /* BRGB output = 48kHz */
rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
(ckr) ? 'B' : 'A',
(ckr) ? adg->brg_rate[ADG_HZ_48] :
adg->brg_rate[ADG_HZ_441]);
return 0;
}
void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
{
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
struct clk *clk;
int i;
if (enable) {
rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr);
rsnd_mod_write(adg_mod, BRRA, adg->brga);
rsnd_mod_write(adg_mod, BRRB, adg->brgb);
}
for_each_rsnd_clkin(clk, adg, i) {
if (enable) {
clk_prepare_enable(clk);
/*
* We shouldn't use clk_get_rate() under
* atomic context. Let's keep it when
* rsnd_adg_clk_enable() was called
*/
adg->clkin_rate[i] = clk_get_rate(clk);
} else {
clk_disable_unprepare(clk);
}
}
}
static struct clk *rsnd_adg_create_null_clk(struct rsnd_priv *priv,
const char * const name,
const char *parent)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct clk *clk;
clk = clk_register_fixed_rate(dev, name, parent, 0, 0);
if (IS_ERR_OR_NULL(clk)) {
dev_err(dev, "create null clk error\n");
return ERR_CAST(clk);
}
return clk;
}
static struct clk *rsnd_adg_null_clk_get(struct rsnd_priv *priv)
{
struct rsnd_adg *adg = priv->adg;
if (!adg->null_clk) {
static const char * const name = "rsnd_adg_null";
adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL);
}
return adg->null_clk;
}
static void rsnd_adg_null_clk_clean(struct rsnd_priv *priv)
{
struct rsnd_adg *adg = priv->adg;
if (adg->null_clk)
clk_unregister_fixed_rate(adg->null_clk);
}
static int rsnd_adg_get_clkin(struct rsnd_priv *priv)
{
struct rsnd_adg *adg = priv->adg;
struct device *dev = rsnd_priv_to_dev(priv);
struct clk *clk;
const char * const *clkin_name;
int clkin_size;
int i;
clkin_name = clkin_name_gen2;
clkin_size = ARRAY_SIZE(clkin_name_gen2);
if (rsnd_is_gen4(priv)) {
clkin_name = clkin_name_gen4;
clkin_size = ARRAY_SIZE(clkin_name_gen4);
}
for (i = 0; i < clkin_size; i++) {
clk = devm_clk_get(dev, clkin_name[i]);
if (IS_ERR_OR_NULL(clk))
clk = rsnd_adg_null_clk_get(priv);
if (IS_ERR_OR_NULL(clk))
goto err;
adg->clkin[i] = clk;
}
adg->clkin_size = clkin_size;
return 0;
err:
dev_err(dev, "adg clock IN get failed\n");
rsnd_adg_null_clk_clean(priv);
return -EIO;
}
static void rsnd_adg_unregister_clkout(struct rsnd_priv *priv)
{
struct rsnd_adg *adg = priv->adg;
struct clk *clk;
int i;
for_each_rsnd_clkout(clk, adg, i)
clk_unregister_fixed_rate(clk);
}
static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
{
struct rsnd_adg *adg = priv->adg;
struct clk *clk;
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np = dev->of_node;
struct property *prop;
u32 ckr, brgx, brga, brgb;
u32 req_rate[ADG_HZ_SIZE] = {};
uint32_t count = 0;
unsigned long req_Hz[ADG_HZ_SIZE];
int clkout_size;
int i, req_size;
int approximate = 0;
const char *parent_clk_name = NULL;
const char * const *clkout_name;
int brg_table[] = {
[CLKA] = 0x0,
[CLKB] = 0x1,
[CLKC] = 0x4,
[CLKI] = 0x2,
};
ckr = 0;
brga = 0xff; /* default */
brgb = 0xff; /* default */
/*
* ADG supports BRRA/BRRB output only
* this means all clkout0/1/2/3 will be same rate
*/
prop = of_find_property(np, "clock-frequency", NULL);
if (!prop)
goto rsnd_adg_get_clkout_end;
req_size = prop->length / sizeof(u32);
if (req_size > ADG_HZ_SIZE) {
dev_err(dev, "too many clock-frequency\n");
return -EINVAL;
}
of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
req_Hz[ADG_HZ_48] = 0;
req_Hz[ADG_HZ_441] = 0;
for (i = 0; i < req_size; i++) {
if (0 == (req_rate[i] % 44100))
req_Hz[ADG_HZ_441] = req_rate[i];
if (0 == (req_rate[i] % 48000))
req_Hz[ADG_HZ_48] = req_rate[i];
}
/*
* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
* have 44.1kHz or 48kHz base clocks for now.
*
* SSI itself can divide parent clock by 1/1 - 1/16
* see
* rsnd_adg_ssi_clk_try_start()
* rsnd_ssi_master_clk_start()
*/
/*
* [APPROXIMATE]
*
* clk_i (internal clock) can't create accurate rate, it will be approximate rate.
*
* <Note>
*
* clk_i needs x2 of required maximum rate.
* see
* - Minimum division of BRRA/BRRB
* - rsnd_ssi_clk_query()
*
* Sample Settings for TDM 8ch, 32bit width
*
* 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200
* 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000
*
* clock-frequency = <22579200 24576000>;
*/
for_each_rsnd_clkin(clk, adg, i) {
u32 rate, div;
rate = clk_get_rate(clk);
if (0 == rate) /* not used */
continue;
/* BRGA */
if (i == CLKI)
/* see [APPROXIMATE] */
rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441];
if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) {
div = rate / req_Hz[ADG_HZ_441];
brgx = rsnd_adg_calculate_brgx(div);
if (BRRx_MASK(brgx) == brgx) {
brga = brgx;
adg->brg_rate[ADG_HZ_441] = rate / div;
ckr |= brg_table[i] << 20;
if (req_Hz[ADG_HZ_441])
parent_clk_name = __clk_get_name(clk);
if (i == CLKI)
approximate = 1;
}
}
/* BRGB */
if (i == CLKI)
/* see [APPROXIMATE] */
rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48];
if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) {
div = rate / req_Hz[ADG_HZ_48];
brgx = rsnd_adg_calculate_brgx(div);
if (BRRx_MASK(brgx) == brgx) {
brgb = brgx;
adg->brg_rate[ADG_HZ_48] = rate / div;
ckr |= brg_table[i] << 16;
if (req_Hz[ADG_HZ_48])
parent_clk_name = __clk_get_name(clk);
if (i == CLKI)
approximate = 1;
}
}
}
if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) &&
!(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441]))
goto rsnd_adg_get_clkout_end;
if (approximate)
dev_info(dev, "It uses CLK_I as approximate rate");
clkout_name = clkout_name_gen2;
clkout_size = ARRAY_SIZE(clkout_name_gen2);
if (rsnd_is_gen4(priv))
clkout_size = 1; /* reuse clkout_name_gen2[] */
/*
* ADG supports BRRA/BRRB output only.
* this means all clkout0/1/2/3 will be * same rate
*/
of_property_read_u32(np, "#clock-cells", &count);
/*
* for clkout
*/
if (!count) {
clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
parent_clk_name, 0, req_rate[0]);
if (IS_ERR_OR_NULL(clk))
goto err;
adg->clkout[CLKOUT] = clk;
adg->clkout_size = 1;
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
/*
* for clkout0/1/2/3
*/
else {
for (i = 0; i < clkout_size; i++) {
clk = clk_register_fixed_rate(dev, clkout_name[i],
parent_clk_name, 0,
req_rate[0]);
if (IS_ERR_OR_NULL(clk))
goto err;
adg->clkout[i] = clk;
}
adg->onecell.clks = adg->clkout;
adg->onecell.clk_num = clkout_size;
adg->clkout_size = clkout_size;
of_clk_add_provider(np, of_clk_src_onecell_get,
&adg->onecell);
}
rsnd_adg_get_clkout_end:
adg->ckr = ckr;
adg->brga = brga;
adg->brgb = brgb;
return 0;
err:
dev_err(dev, "adg clock OUT get failed\n");
rsnd_adg_unregister_clkout(priv);
return -EIO;
}
#if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
__printf(3, 4)
static void dbg_msg(struct device *dev, struct seq_file *m,
const char *fmt, ...)
{
char msg[128];
va_list args;
va_start(args, fmt);
vsnprintf(msg, sizeof(msg), fmt, args);
va_end(args);
if (m)
seq_puts(m, msg);
else
dev_dbg(dev, "%s", msg);
}
void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct seq_file *m)
{
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
struct device *dev = rsnd_priv_to_dev(priv);
struct clk *clk;
int i;
for_each_rsnd_clkin(clk, adg, i)
dbg_msg(dev, m, "%-18s : %pa : %ld\n",
__clk_get_name(clk), clk, clk_get_rate(clk));
dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
adg->ckr, adg->brga, adg->brgb);
dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]);
dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]);
/*
* Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
* by BRGCKR::BRGCKR_31
*/
for_each_rsnd_clkout(clk, adg, i)
dbg_msg(dev, m, "%-18s : %pa : %ld\n",
__clk_get_name(clk), clk, clk_get_rate(clk));
}
#else
#define rsnd_adg_clk_dbg_info(priv, m)
#endif
int rsnd_adg_probe(struct rsnd_priv *priv)
{
struct rsnd_adg *adg;
struct device *dev = rsnd_priv_to_dev(priv);
int ret;
adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
if (!adg)
return -ENOMEM;
ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
NULL, 0, 0);
if (ret)
return ret;
priv->adg = adg;
ret = rsnd_adg_get_clkin(priv);
if (ret)
return ret;
ret = rsnd_adg_get_clkout(priv);
if (ret)
return ret;
rsnd_adg_clk_enable(priv);
rsnd_adg_clk_dbg_info(priv, NULL);
return 0;
}
void rsnd_adg_remove(struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np = dev->of_node;
rsnd_adg_unregister_clkout(priv);
of_clk_del_provider(np);
rsnd_adg_clk_disable(priv);
/* It should be called after rsnd_adg_clk_disable() */
rsnd_adg_null_clk_clean(priv);
}
| linux-master | sound/soc/sh/rcar/adg.c |
// SPDX-License-Identifier: GPL-2.0
//
// mix.c
//
// Copyright (c) 2015 Kuninori Morimoto <[email protected]>
/*
* CTUn MIXn
* +------+ +------+
* [SRC3 / SRC6] -> |CTU n0| -> [MIX n0| ->
* [SRC4 / SRC9] -> |CTU n1| -> [MIX n1| ->
* [SRC0 / SRC1] -> |CTU n2| -> [MIX n2| ->
* [SRC2 / SRC5] -> |CTU n3| -> [MIX n3| ->
* +------+ +------+
*
* ex)
* DAI0 : playback = <&src0 &ctu02 &mix0 &dvc0 &ssi0>;
* DAI1 : playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>;
*
* MIX Volume
* amixer set "MIX",0 100% // DAI0 Volume
* amixer set "MIX",1 100% // DAI1 Volume
*
* Volume Ramp
* amixer set "MIX Ramp Up Rate" "0.125 dB/1 step"
* amixer set "MIX Ramp Down Rate" "4 dB/1 step"
* amixer set "MIX Ramp" on
* aplay xxx.wav &
* amixer set "MIX",0 80% // DAI0 Volume Down
* amixer set "MIX",1 100% // DAI1 Volume Up
*/
#include "rsnd.h"
#define MIX_NAME_SIZE 16
#define MIX_NAME "mix"
struct rsnd_mix {
struct rsnd_mod mod;
struct rsnd_kctrl_cfg_s volumeA; /* MDBAR */
struct rsnd_kctrl_cfg_s volumeB; /* MDBBR */
struct rsnd_kctrl_cfg_s volumeC; /* MDBCR */
struct rsnd_kctrl_cfg_s volumeD; /* MDBDR */
struct rsnd_kctrl_cfg_s ren; /* Ramp Enable */
struct rsnd_kctrl_cfg_s rup; /* Ramp Rate Up */
struct rsnd_kctrl_cfg_s rdw; /* Ramp Rate Down */
u32 flags;
};
#define ONCE_KCTRL_INITIALIZED (1 << 0)
#define HAS_VOLA (1 << 1)
#define HAS_VOLB (1 << 2)
#define HAS_VOLC (1 << 3)
#define HAS_VOLD (1 << 4)
#define VOL_MAX 0x3ff
#define rsnd_mod_to_mix(_mod) \
container_of((_mod), struct rsnd_mix, mod)
#define rsnd_mix_get(priv, id) ((struct rsnd_mix *)(priv->mix) + id)
#define rsnd_mix_nr(priv) ((priv)->mix_nr)
#define for_each_rsnd_mix(pos, priv, i) \
for ((i) = 0; \
((i) < rsnd_mix_nr(priv)) && \
((pos) = (struct rsnd_mix *)(priv)->mix + i); \
i++)
static void rsnd_mix_activation(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, MIX_SWRSR, 0);
rsnd_mod_write(mod, MIX_SWRSR, 1);
}
static void rsnd_mix_halt(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, MIX_MIXIR, 1);
rsnd_mod_write(mod, MIX_SWRSR, 0);
}
#define rsnd_mix_get_vol(mix, X) \
rsnd_flags_has(mix, HAS_VOL##X) ? \
(VOL_MAX - rsnd_kctrl_vals(mix->volume##X)) : 0
static void rsnd_mix_volume_parameter(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mix *mix = rsnd_mod_to_mix(mod);
u32 volA = rsnd_mix_get_vol(mix, A);
u32 volB = rsnd_mix_get_vol(mix, B);
u32 volC = rsnd_mix_get_vol(mix, C);
u32 volD = rsnd_mix_get_vol(mix, D);
dev_dbg(dev, "MIX A/B/C/D = %02x/%02x/%02x/%02x\n",
volA, volB, volC, volD);
rsnd_mod_write(mod, MIX_MDBAR, volA);
rsnd_mod_write(mod, MIX_MDBBR, volB);
rsnd_mod_write(mod, MIX_MDBCR, volC);
rsnd_mod_write(mod, MIX_MDBDR, volD);
}
static void rsnd_mix_volume_init(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_mix *mix = rsnd_mod_to_mix(mod);
rsnd_mod_write(mod, MIX_MIXIR, 1);
/* General Information */
rsnd_mod_write(mod, MIX_ADINR, rsnd_runtime_channel_after_ctu(io));
/* volume step */
rsnd_mod_write(mod, MIX_MIXMR, rsnd_kctrl_vals(mix->ren));
rsnd_mod_write(mod, MIX_MVPDR, rsnd_kctrl_vals(mix->rup) << 8 |
rsnd_kctrl_vals(mix->rdw));
/* common volume parameter */
rsnd_mix_volume_parameter(io, mod);
rsnd_mod_write(mod, MIX_MIXIR, 0);
}
static void rsnd_mix_volume_update(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
/* Disable MIX dB setting */
rsnd_mod_write(mod, MIX_MDBER, 0);
/* common volume parameter */
rsnd_mix_volume_parameter(io, mod);
/* Enable MIX dB setting */
rsnd_mod_write(mod, MIX_MDBER, 1);
}
static int rsnd_mix_probe_(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
return rsnd_cmd_attach(io, rsnd_mod_id(mod));
}
static int rsnd_mix_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
int ret;
ret = rsnd_mod_power_on(mod);
if (ret < 0)
return ret;
rsnd_mix_activation(mod);
rsnd_mix_volume_init(io, mod);
rsnd_mix_volume_update(io, mod);
return 0;
}
static int rsnd_mix_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_mix_halt(mod);
rsnd_mod_power_off(mod);
return 0;
}
static int rsnd_mix_pcm_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mix *mix = rsnd_mod_to_mix(mod);
struct rsnd_mod *src_mod = rsnd_io_to_mod_src(io);
struct rsnd_kctrl_cfg_s *volume;
int ret;
switch (rsnd_mod_id(src_mod)) {
case 3:
case 6: /* MDBAR */
volume = &mix->volumeA;
rsnd_flags_set(mix, HAS_VOLA);
break;
case 4:
case 9: /* MDBBR */
volume = &mix->volumeB;
rsnd_flags_set(mix, HAS_VOLB);
break;
case 0:
case 1: /* MDBCR */
volume = &mix->volumeC;
rsnd_flags_set(mix, HAS_VOLC);
break;
case 2:
case 5: /* MDBDR */
volume = &mix->volumeD;
rsnd_flags_set(mix, HAS_VOLD);
break;
default:
dev_err(dev, "unknown SRC is connected\n");
return -EINVAL;
}
/* Volume */
ret = rsnd_kctrl_new_s(mod, io, rtd,
"MIX Playback Volume",
rsnd_kctrl_accept_anytime,
rsnd_mix_volume_update,
volume, VOL_MAX);
if (ret < 0)
return ret;
rsnd_kctrl_vals(*volume) = VOL_MAX;
if (rsnd_flags_has(mix, ONCE_KCTRL_INITIALIZED))
return ret;
/* Ramp */
ret = rsnd_kctrl_new_s(mod, io, rtd,
"MIX Ramp Switch",
rsnd_kctrl_accept_anytime,
rsnd_mix_volume_update,
&mix->ren, 1);
if (ret < 0)
return ret;
ret = rsnd_kctrl_new_e(mod, io, rtd,
"MIX Ramp Up Rate",
rsnd_kctrl_accept_anytime,
rsnd_mix_volume_update,
&mix->rup,
volume_ramp_rate,
VOLUME_RAMP_MAX_MIX);
if (ret < 0)
return ret;
ret = rsnd_kctrl_new_e(mod, io, rtd,
"MIX Ramp Down Rate",
rsnd_kctrl_accept_anytime,
rsnd_mix_volume_update,
&mix->rdw,
volume_ramp_rate,
VOLUME_RAMP_MAX_MIX);
rsnd_flags_set(mix, ONCE_KCTRL_INITIALIZED);
return ret;
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_mix_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
0xd00 + rsnd_mod_id(mod) * 0x40, 0x30);
}
#define DEBUG_INFO .debug_info = rsnd_mix_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_mix_ops = {
.name = MIX_NAME,
.probe = rsnd_mix_probe_,
.init = rsnd_mix_init,
.quit = rsnd_mix_quit,
.pcm_new = rsnd_mix_pcm_new,
.get_status = rsnd_mod_get_status,
DEBUG_INFO
};
struct rsnd_mod *rsnd_mix_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_mix_nr(priv)))
id = 0;
return rsnd_mod_get(rsnd_mix_get(priv, id));
}
int rsnd_mix_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mix *mix;
struct clk *clk;
char name[MIX_NAME_SIZE];
int i, nr, ret;
/* This driver doesn't support Gen1 at this point */
if (rsnd_is_gen1(priv))
return 0;
node = rsnd_mix_of_node(priv);
if (!node)
return 0; /* not used is not error */
nr = of_get_child_count(node);
if (!nr) {
ret = -EINVAL;
goto rsnd_mix_probe_done;
}
mix = devm_kcalloc(dev, nr, sizeof(*mix), GFP_KERNEL);
if (!mix) {
ret = -ENOMEM;
goto rsnd_mix_probe_done;
}
priv->mix_nr = nr;
priv->mix = mix;
i = 0;
ret = 0;
for_each_child_of_node(node, np) {
mix = rsnd_mix_get(priv, i);
snprintf(name, MIX_NAME_SIZE, "%s.%d",
MIX_NAME, i);
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_mix_probe_done;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(mix), &rsnd_mix_ops,
clk, RSND_MOD_MIX, i);
if (ret) {
of_node_put(np);
goto rsnd_mix_probe_done;
}
i++;
}
rsnd_mix_probe_done:
of_node_put(node);
return ret;
}
void rsnd_mix_remove(struct rsnd_priv *priv)
{
struct rsnd_mix *mix;
int i;
for_each_rsnd_mix(mix, priv, i) {
rsnd_mod_quit(rsnd_mod_get(mix));
}
}
| linux-master | sound/soc/sh/rcar/mix.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car SSIU support
//
// Copyright (c) 2015 Kuninori Morimoto <[email protected]>
#include "rsnd.h"
#define SSIU_NAME "ssiu"
struct rsnd_ssiu {
struct rsnd_mod mod;
u32 busif_status[8]; /* for BUSIF0 - BUSIF7 */
unsigned int usrcnt;
int id;
int id_sub;
};
/* SSI_MODE */
#define TDM_EXT (1 << 0)
#define TDM_SPLIT (1 << 8)
#define rsnd_ssiu_nr(priv) ((priv)->ssiu_nr)
#define rsnd_mod_to_ssiu(_mod) container_of((_mod), struct rsnd_ssiu, mod)
#define for_each_rsnd_ssiu(pos, priv, i) \
for (i = 0; \
(i < rsnd_ssiu_nr(priv)) && \
((pos) = ((struct rsnd_ssiu *)(priv)->ssiu + i)); \
i++)
/*
* SSI Gen2 Gen3 Gen4
* 0 BUSIF0-3 BUSIF0-7 BUSIF0-7
* 1 BUSIF0-3 BUSIF0-7
* 2 BUSIF0-3 BUSIF0-7
* 3 BUSIF0 BUSIF0-7
* 4 BUSIF0 BUSIF0-7
* 5 BUSIF0 BUSIF0
* 6 BUSIF0 BUSIF0
* 7 BUSIF0 BUSIF0
* 8 BUSIF0 BUSIF0
* 9 BUSIF0-3 BUSIF0-7
* total 22 52 8
*/
static const int gen2_id[] = { 0, 4, 8, 12, 13, 14, 15, 16, 17, 18 };
static const int gen3_id[] = { 0, 8, 16, 24, 32, 40, 41, 42, 43, 44 };
static const int gen4_id[] = { 0 };
/* enable busif buffer over/under run interrupt. */
#define rsnd_ssiu_busif_err_irq_enable(mod) rsnd_ssiu_busif_err_irq_ctrl(mod, 1)
#define rsnd_ssiu_busif_err_irq_disable(mod) rsnd_ssiu_busif_err_irq_ctrl(mod, 0)
static void rsnd_ssiu_busif_err_irq_ctrl(struct rsnd_mod *mod, int enable)
{
int id = rsnd_mod_id(mod);
int shift, offset;
int i;
switch (id) {
case 0:
case 1:
case 2:
case 3:
case 4:
shift = id;
offset = 0;
break;
case 9:
shift = 1;
offset = 1;
break;
default:
return;
}
for (i = 0; i < 4; i++) {
enum rsnd_reg reg = SSI_SYS_INT_ENABLE((i * 2) + offset);
u32 val = 0xf << (shift * 4);
u32 sys_int_enable = rsnd_mod_read(mod, reg);
if (enable)
sys_int_enable |= val;
else
sys_int_enable &= ~val;
rsnd_mod_write(mod, reg, sys_int_enable);
}
}
bool rsnd_ssiu_busif_err_status_clear(struct rsnd_mod *mod)
{
bool error = false;
int id = rsnd_mod_id(mod);
int shift, offset;
int i;
switch (id) {
case 0:
case 1:
case 2:
case 3:
case 4:
shift = id;
offset = 0;
break;
case 9:
shift = 1;
offset = 1;
break;
default:
goto out;
}
for (i = 0; i < 4; i++) {
u32 reg = SSI_SYS_STATUS(i * 2) + offset;
u32 status = rsnd_mod_read(mod, reg);
u32 val = 0xf << (shift * 4);
status &= val;
if (status) {
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
rsnd_print_irq_status(dev, "%s err status : 0x%08x\n",
rsnd_mod_name(mod), status);
error = true;
}
rsnd_mod_write(mod, reg, val);
}
out:
return error;
}
static u32 *rsnd_ssiu_get_status(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
enum rsnd_mod_type type)
{
struct rsnd_ssiu *ssiu = rsnd_mod_to_ssiu(mod);
int busif = rsnd_mod_id_sub(mod);
return &ssiu->busif_status[busif];
}
static int rsnd_ssiu_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
u32 ssis = rsnd_ssi_multi_secondaries_runtime(io);
int use_busif = rsnd_ssi_use_busif(io);
int id = rsnd_mod_id(mod);
int is_clk_master = rsnd_rdai_is_clk_master(rdai);
u32 val1, val2;
/* clear status */
rsnd_ssiu_busif_err_status_clear(mod);
/* Gen4 doesn't have SSI_MODE */
if (rsnd_is_gen4(priv))
goto ssi_mode_setting_end;
/*
* SSI_MODE0
*/
rsnd_mod_bset(mod, SSI_MODE0, (1 << id), !use_busif << id);
/*
* SSI_MODE1 / SSI_MODE2
*
* FIXME
* sharing/multi with SSI0 are mainly supported
*/
val1 = rsnd_mod_read(mod, SSI_MODE1);
val2 = rsnd_mod_read(mod, SSI_MODE2);
if (rsnd_ssi_is_pin_sharing(io)) {
ssis |= (1 << id);
} else if (ssis) {
/*
* Multi SSI
*
* set synchronized bit here
*/
/* SSI4 is synchronized with SSI3 */
if (ssis & (1 << 4))
val1 |= (1 << 20);
/* SSI012 are synchronized */
if (ssis == 0x0006)
val1 |= (1 << 4);
/* SSI0129 are synchronized */
if (ssis == 0x0206)
val2 |= (1 << 4);
}
/* SSI1 is sharing pin with SSI0 */
if (ssis & (1 << 1))
val1 |= is_clk_master ? 0x2 : 0x1;
/* SSI2 is sharing pin with SSI0 */
if (ssis & (1 << 2))
val1 |= is_clk_master ? 0x2 << 2 :
0x1 << 2;
/* SSI4 is sharing pin with SSI3 */
if (ssis & (1 << 4))
val1 |= is_clk_master ? 0x2 << 16 :
0x1 << 16;
/* SSI9 is sharing pin with SSI0 */
if (ssis & (1 << 9))
val2 |= is_clk_master ? 0x2 : 0x1;
rsnd_mod_bset(mod, SSI_MODE1, 0x0013001f, val1);
rsnd_mod_bset(mod, SSI_MODE2, 0x00000017, val2);
ssi_mode_setting_end:
/*
* Enable busif buffer over/under run interrupt.
* It will be handled from ssi.c
* see
* __rsnd_ssi_interrupt()
*/
rsnd_ssiu_busif_err_irq_enable(mod);
return 0;
}
static int rsnd_ssiu_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
/* disable busif buffer over/under run interrupt. */
rsnd_ssiu_busif_err_irq_disable(mod);
return 0;
}
static struct rsnd_mod_ops rsnd_ssiu_ops_gen1 = {
.name = SSIU_NAME,
.init = rsnd_ssiu_init,
.quit = rsnd_ssiu_quit,
.get_status = rsnd_ssiu_get_status,
};
static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssiu *ssiu = rsnd_mod_to_ssiu(mod);
u32 has_hdmi0 = rsnd_flags_has(io, RSND_STREAM_HDMI0);
u32 has_hdmi1 = rsnd_flags_has(io, RSND_STREAM_HDMI1);
int ret;
u32 mode = 0;
ret = rsnd_ssiu_init(mod, io, priv);
if (ret < 0)
return ret;
ssiu->usrcnt++;
/*
* TDM Extend/Split Mode
* see
* rsnd_ssi_config_init()
*/
if (rsnd_runtime_is_tdm(io))
mode = TDM_EXT;
else if (rsnd_runtime_is_tdm_split(io))
mode = TDM_SPLIT;
rsnd_mod_write(mod, SSI_MODE, mode);
if (rsnd_ssi_use_busif(io)) {
int id = rsnd_mod_id(mod);
int busif = rsnd_mod_id_sub(mod);
enum rsnd_reg adinr_reg, mode_reg, dalign_reg;
if ((id == 9) && (busif >= 4)) {
adinr_reg = SSI9_BUSIF_ADINR(busif);
mode_reg = SSI9_BUSIF_MODE(busif);
dalign_reg = SSI9_BUSIF_DALIGN(busif);
} else {
adinr_reg = SSI_BUSIF_ADINR(busif);
mode_reg = SSI_BUSIF_MODE(busif);
dalign_reg = SSI_BUSIF_DALIGN(busif);
}
rsnd_mod_write(mod, adinr_reg,
rsnd_get_adinr_bit(mod, io) |
(rsnd_io_is_play(io) ?
rsnd_runtime_channel_after_ctu(io) :
rsnd_runtime_channel_original(io)));
rsnd_mod_write(mod, mode_reg,
rsnd_get_busif_shift(io, mod) | 1);
rsnd_mod_write(mod, dalign_reg,
rsnd_get_dalign(mod, io));
}
if (has_hdmi0 || has_hdmi1) {
enum rsnd_mod_type rsnd_ssi_array[] = {
RSND_MOD_SSIM1,
RSND_MOD_SSIM2,
RSND_MOD_SSIM3,
};
struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
struct rsnd_mod *pos;
u32 val;
int i;
i = rsnd_mod_id(ssi_mod);
/* output all same SSI as default */
val = i << 16 |
i << 20 |
i << 24 |
i << 28 |
i;
for_each_rsnd_mod_array(i, pos, io, rsnd_ssi_array) {
int shift = (i * 4) + 20;
val = (val & ~(0xF << shift)) |
rsnd_mod_id(pos) << shift;
}
if (has_hdmi0)
rsnd_mod_write(mod, HDMI0_SEL, val);
if (has_hdmi1)
rsnd_mod_write(mod, HDMI1_SEL, val);
}
return 0;
}
static int rsnd_ssiu_start_gen2(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
int busif = rsnd_mod_id_sub(mod);
if (!rsnd_ssi_use_busif(io))
return 0;
rsnd_mod_bset(mod, SSI_CTRL, 1 << (busif * 4), 1 << (busif * 4));
if (rsnd_ssi_multi_secondaries_runtime(io))
rsnd_mod_write(mod, SSI_CONTROL, 0x1);
return 0;
}
static int rsnd_ssiu_stop_gen2(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssiu *ssiu = rsnd_mod_to_ssiu(mod);
int busif = rsnd_mod_id_sub(mod);
if (!rsnd_ssi_use_busif(io))
return 0;
rsnd_mod_bset(mod, SSI_CTRL, 1 << (busif * 4), 0);
if (--ssiu->usrcnt)
return 0;
if (rsnd_ssi_multi_secondaries_runtime(io))
rsnd_mod_write(mod, SSI_CONTROL, 0);
return 0;
}
static int rsnd_ssiu_id(struct rsnd_mod *mod)
{
struct rsnd_ssiu *ssiu = rsnd_mod_to_ssiu(mod);
/* see rsnd_ssiu_probe() */
return ssiu->id;
}
static int rsnd_ssiu_id_sub(struct rsnd_mod *mod)
{
struct rsnd_ssiu *ssiu = rsnd_mod_to_ssiu(mod);
/* see rsnd_ssiu_probe() */
return ssiu->id_sub;
}
static struct dma_chan *rsnd_ssiu_dma_req(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
int is_play = rsnd_io_is_play(io);
char *name;
/*
* It should use "rcar_sound,ssiu" on DT.
* But, we need to keep compatibility for old version.
*
* If it has "rcar_sound.ssiu", it will be used.
* If not, "rcar_sound.ssi" will be used.
* see
* rsnd_ssi_dma_req()
* rsnd_dma_of_path()
*/
name = is_play ? "rx" : "tx";
return rsnd_dma_request_channel(rsnd_ssiu_of_node(priv),
SSIU_NAME, mod, name);
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_ssiu_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SSIU,
rsnd_mod_id(mod) * 0x80, 0x80);
}
#define DEBUG_INFO .debug_info = rsnd_ssiu_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_ssiu_ops_gen2 = {
.name = SSIU_NAME,
.dma_req = rsnd_ssiu_dma_req,
.init = rsnd_ssiu_init_gen2,
.quit = rsnd_ssiu_quit,
.start = rsnd_ssiu_start_gen2,
.stop = rsnd_ssiu_stop_gen2,
.get_status = rsnd_ssiu_get_status,
DEBUG_INFO
};
static struct rsnd_mod *rsnd_ssiu_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_ssiu_nr(priv)))
id = 0;
return rsnd_mod_get((struct rsnd_ssiu *)(priv->ssiu) + id);
}
static void rsnd_parse_connect_ssiu_compatible(struct rsnd_priv *priv,
struct rsnd_dai_stream *io)
{
struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
struct rsnd_ssiu *ssiu;
int is_dma_mode;
int i;
if (!ssi_mod)
return;
is_dma_mode = rsnd_ssi_is_dma_mode(ssi_mod);
/* select BUSIF0 */
for_each_rsnd_ssiu(ssiu, priv, i) {
struct rsnd_mod *mod = rsnd_mod_get(ssiu);
if (is_dma_mode &&
(rsnd_mod_id(ssi_mod) == rsnd_mod_id(mod)) &&
(rsnd_mod_id_sub(mod) == 0)) {
rsnd_dai_connect(mod, io, mod->type);
return;
}
}
}
void rsnd_parse_connect_ssiu(struct rsnd_dai *rdai,
struct device_node *playback,
struct device_node *capture)
{
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *node = rsnd_ssiu_of_node(priv);
struct rsnd_dai_stream *io_p = &rdai->playback;
struct rsnd_dai_stream *io_c = &rdai->capture;
/* use rcar_sound,ssiu if exist */
if (node) {
struct device_node *np;
int i = 0;
for_each_child_of_node(node, np) {
struct rsnd_mod *mod;
i = rsnd_node_fixed_index(dev, np, SSIU_NAME, i);
if (i < 0) {
of_node_put(np);
break;
}
mod = rsnd_ssiu_mod_get(priv, i);
if (np == playback)
rsnd_dai_connect(mod, io_p, mod->type);
if (np == capture)
rsnd_dai_connect(mod, io_c, mod->type);
i++;
}
of_node_put(node);
}
/* Keep DT compatibility */
if (!rsnd_io_to_mod_ssiu(io_p))
rsnd_parse_connect_ssiu_compatible(priv, io_p);
if (!rsnd_io_to_mod_ssiu(io_c))
rsnd_parse_connect_ssiu_compatible(priv, io_c);
}
int rsnd_ssiu_probe(struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *node;
struct rsnd_ssiu *ssiu;
struct rsnd_mod_ops *ops;
const int *list = NULL;
int i, nr;
/*
* Keep DT compatibility.
* if it has "rcar_sound,ssiu", use it.
* if not, use "rcar_sound,ssi"
* see
* rsnd_ssiu_bufsif_to_id()
*/
node = rsnd_ssiu_of_node(priv);
if (node)
nr = rsnd_node_count(priv, node, SSIU_NAME);
else
nr = priv->ssi_nr;
if (!nr)
return -EINVAL;
ssiu = devm_kcalloc(dev, nr, sizeof(*ssiu), GFP_KERNEL);
if (!ssiu)
return -ENOMEM;
priv->ssiu = ssiu;
priv->ssiu_nr = nr;
if (rsnd_is_gen1(priv))
ops = &rsnd_ssiu_ops_gen1;
else
ops = &rsnd_ssiu_ops_gen2;
/* Keep compatibility */
nr = 0;
if ((node) &&
(ops == &rsnd_ssiu_ops_gen2)) {
ops->id = rsnd_ssiu_id;
ops->id_sub = rsnd_ssiu_id_sub;
if (rsnd_is_gen2(priv)) {
list = gen2_id;
nr = ARRAY_SIZE(gen2_id);
} else if (rsnd_is_gen3(priv)) {
list = gen3_id;
nr = ARRAY_SIZE(gen3_id);
} else if (rsnd_is_gen4(priv)) {
list = gen4_id;
nr = ARRAY_SIZE(gen4_id);
} else {
dev_err(dev, "unknown SSIU\n");
return -ENODEV;
}
}
for_each_rsnd_ssiu(ssiu, priv, i) {
int ret;
if (node) {
int j;
/*
* see
* rsnd_ssiu_get_id()
* rsnd_ssiu_get_id_sub()
*/
for (j = 0; j < nr; j++) {
if (list[j] > i)
break;
ssiu->id = j;
ssiu->id_sub = i - list[ssiu->id];
}
} else {
ssiu->id = i;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(ssiu),
ops, NULL, RSND_MOD_SSIU, i);
if (ret)
return ret;
}
return 0;
}
void rsnd_ssiu_remove(struct rsnd_priv *priv)
{
struct rsnd_ssiu *ssiu;
int i;
for_each_rsnd_ssiu(ssiu, priv, i) {
rsnd_mod_quit(rsnd_mod_get(ssiu));
}
}
| linux-master | sound/soc/sh/rcar/ssiu.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car SSIU/SSI support
//
// Copyright (C) 2013 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
//
// Based on fsi.c
// Kuninori Morimoto <[email protected]>
/*
* you can enable below define if you don't need
* SSI interrupt status debug message when debugging
* see rsnd_print_irq_status()
*
* #define RSND_DEBUG_NO_IRQ_STATUS 1
*/
#include <sound/simple_card_utils.h>
#include <linux/delay.h>
#include "rsnd.h"
#define RSND_SSI_NAME_SIZE 16
/*
* SSICR
*/
#define FORCE (1u << 31) /* Fixed */
#define DMEN (1u << 28) /* DMA Enable */
#define UIEN (1u << 27) /* Underflow Interrupt Enable */
#define OIEN (1u << 26) /* Overflow Interrupt Enable */
#define IIEN (1u << 25) /* Idle Mode Interrupt Enable */
#define DIEN (1u << 24) /* Data Interrupt Enable */
#define CHNL_4 (1u << 22) /* Channels */
#define CHNL_6 (2u << 22) /* Channels */
#define CHNL_8 (3u << 22) /* Channels */
#define DWL_MASK (7u << 19) /* Data Word Length mask */
#define DWL_8 (0u << 19) /* Data Word Length */
#define DWL_16 (1u << 19) /* Data Word Length */
#define DWL_18 (2u << 19) /* Data Word Length */
#define DWL_20 (3u << 19) /* Data Word Length */
#define DWL_22 (4u << 19) /* Data Word Length */
#define DWL_24 (5u << 19) /* Data Word Length */
#define DWL_32 (6u << 19) /* Data Word Length */
/*
* System word length
*/
#define SWL_16 (1 << 16) /* R/W System Word Length */
#define SWL_24 (2 << 16) /* R/W System Word Length */
#define SWL_32 (3 << 16) /* R/W System Word Length */
#define SCKD (1 << 15) /* Serial Bit Clock Direction */
#define SWSD (1 << 14) /* Serial WS Direction */
#define SCKP (1 << 13) /* Serial Bit Clock Polarity */
#define SWSP (1 << 12) /* Serial WS Polarity */
#define SDTA (1 << 10) /* Serial Data Alignment */
#define PDTA (1 << 9) /* Parallel Data Alignment */
#define DEL (1 << 8) /* Serial Data Delay */
#define CKDV(v) (v << 4) /* Serial Clock Division Ratio */
#define TRMD (1 << 1) /* Transmit/Receive Mode Select */
#define EN (1 << 0) /* SSI Module Enable */
/*
* SSISR
*/
#define UIRQ (1 << 27) /* Underflow Error Interrupt Status */
#define OIRQ (1 << 26) /* Overflow Error Interrupt Status */
#define IIRQ (1 << 25) /* Idle Mode Interrupt Status */
#define DIRQ (1 << 24) /* Data Interrupt Status Flag */
/*
* SSIWSR
*/
#define CONT (1 << 8) /* WS Continue Function */
#define WS_MODE (1 << 0) /* WS Mode */
#define SSI_NAME "ssi"
struct rsnd_ssi {
struct rsnd_mod mod;
u32 flags;
u32 cr_own;
u32 cr_clk;
u32 cr_mode;
u32 cr_en;
u32 wsr;
int chan;
int rate;
int irq;
unsigned int usrcnt;
/* for PIO */
int byte_pos;
int byte_per_period;
int next_period_byte;
};
/* flags */
#define RSND_SSI_CLK_PIN_SHARE (1 << 0)
#define RSND_SSI_NO_BUSIF (1 << 1) /* SSI+DMA without BUSIF */
#define RSND_SSI_PROBED (1 << 2)
#define for_each_rsnd_ssi(pos, priv, i) \
for (i = 0; \
(i < rsnd_ssi_nr(priv)) && \
((pos) = ((struct rsnd_ssi *)(priv)->ssi + i)); \
i++)
#define rsnd_ssi_get(priv, id) ((struct rsnd_ssi *)(priv->ssi) + id)
#define rsnd_ssi_nr(priv) ((priv)->ssi_nr)
#define rsnd_mod_to_ssi(_mod) container_of((_mod), struct rsnd_ssi, mod)
#define rsnd_ssi_is_parent(ssi, io) ((ssi) == rsnd_io_to_mod_ssip(io))
#define rsnd_ssi_is_multi_secondary(mod, io) \
(rsnd_ssi_multi_secondaries(io) & (1 << rsnd_mod_id(mod)))
#define rsnd_ssi_is_run_mods(mod, io) \
(rsnd_ssi_run_mods(io) & (1 << rsnd_mod_id(mod)))
#define rsnd_ssi_can_output_clk(mod) (!__rsnd_ssi_is_pin_sharing(mod))
int rsnd_ssi_use_busif(struct rsnd_dai_stream *io)
{
struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
int use_busif = 0;
if (!rsnd_ssi_is_dma_mode(mod))
return 0;
if (!(rsnd_flags_has(ssi, RSND_SSI_NO_BUSIF)))
use_busif = 1;
if (rsnd_io_to_mod_src(io))
use_busif = 1;
return use_busif;
}
static void rsnd_ssi_status_clear(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, SSISR, 0);
}
static u32 rsnd_ssi_status_get(struct rsnd_mod *mod)
{
return rsnd_mod_read(mod, SSISR);
}
static void rsnd_ssi_status_check(struct rsnd_mod *mod,
u32 bit)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
u32 status;
int i;
for (i = 0; i < 1024; i++) {
status = rsnd_ssi_status_get(mod);
if (status & bit)
return;
udelay(5);
}
dev_warn(dev, "%s status check failed\n", rsnd_mod_name(mod));
}
static u32 rsnd_ssi_multi_secondaries(struct rsnd_dai_stream *io)
{
static const enum rsnd_mod_type types[] = {
RSND_MOD_SSIM1,
RSND_MOD_SSIM2,
RSND_MOD_SSIM3,
};
int i, mask;
mask = 0;
for (i = 0; i < ARRAY_SIZE(types); i++) {
struct rsnd_mod *mod = rsnd_io_to_mod(io, types[i]);
if (!mod)
continue;
mask |= 1 << rsnd_mod_id(mod);
}
return mask;
}
static u32 rsnd_ssi_run_mods(struct rsnd_dai_stream *io)
{
struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
struct rsnd_mod *ssi_parent_mod = rsnd_io_to_mod_ssip(io);
u32 mods;
mods = rsnd_ssi_multi_secondaries_runtime(io) |
1 << rsnd_mod_id(ssi_mod);
if (ssi_parent_mod)
mods |= 1 << rsnd_mod_id(ssi_parent_mod);
return mods;
}
u32 rsnd_ssi_multi_secondaries_runtime(struct rsnd_dai_stream *io)
{
if (rsnd_runtime_is_multi_ssi(io))
return rsnd_ssi_multi_secondaries(io);
return 0;
}
static u32 rsnd_rdai_width_to_swl(struct rsnd_dai *rdai)
{
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct device *dev = rsnd_priv_to_dev(priv);
int width = rsnd_rdai_width_get(rdai);
switch (width) {
case 32: return SWL_32;
case 24: return SWL_24;
case 16: return SWL_16;
}
dev_err(dev, "unsupported slot width value: %d\n", width);
return 0;
}
unsigned int rsnd_ssi_clk_query(struct rsnd_dai *rdai,
int param1, int param2, int *idx)
{
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
static const int ssi_clk_mul_table[] = {
1, 2, 4, 8, 16, 6, 12,
};
int j, ret;
unsigned int main_rate;
int width = rsnd_rdai_width_get(rdai);
for (j = 0; j < ARRAY_SIZE(ssi_clk_mul_table); j++) {
/*
* It will set SSIWSR.CONT here, but SSICR.CKDV = 000
* with it is not allowed. (SSIWSR.WS_MODE with
* SSICR.CKDV = 000 is not allowed either).
* Skip it. See SSICR.CKDV
*/
if (j == 0)
continue;
main_rate = width * param1 * param2 * ssi_clk_mul_table[j];
ret = rsnd_adg_clk_query(priv, main_rate);
if (ret < 0)
continue;
if (idx)
*idx = j;
return main_rate;
}
return 0;
}
static int rsnd_ssi_master_clk_start(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
int chan = rsnd_runtime_channel_for_ssi(io);
int idx, ret;
unsigned int main_rate;
unsigned int rate = rsnd_io_is_play(io) ?
rsnd_src_get_out_rate(priv, io) :
rsnd_src_get_in_rate(priv, io);
if (!rsnd_rdai_is_clk_master(rdai))
return 0;
if (!rsnd_ssi_can_output_clk(mod))
return 0;
if (rsnd_ssi_is_multi_secondary(mod, io))
return 0;
if (rsnd_runtime_is_tdm_split(io))
chan = rsnd_io_converted_chan(io);
chan = rsnd_channel_normalization(chan);
if (ssi->usrcnt > 0) {
if (ssi->rate != rate) {
dev_err(dev, "SSI parent/child should use same rate\n");
return -EINVAL;
}
if (ssi->chan != chan) {
dev_err(dev, "SSI parent/child should use same chan\n");
return -EINVAL;
}
return 0;
}
ret = -EIO;
main_rate = rsnd_ssi_clk_query(rdai, rate, chan, &idx);
if (!main_rate)
goto rate_err;
ret = rsnd_adg_ssi_clk_try_start(mod, main_rate);
if (ret < 0)
goto rate_err;
/*
* SSI clock will be output contiguously
* by below settings.
* This means, rsnd_ssi_master_clk_start()
* and rsnd_ssi_register_setup() are necessary
* for SSI parent
*
* SSICR : FORCE, SCKD, SWSD
* SSIWSR : CONT
*/
ssi->cr_clk = FORCE | rsnd_rdai_width_to_swl(rdai) |
SCKD | SWSD | CKDV(idx);
ssi->wsr = CONT;
ssi->rate = rate;
ssi->chan = chan;
dev_dbg(dev, "%s outputs %d chan %u Hz\n",
rsnd_mod_name(mod), chan, rate);
return 0;
rate_err:
dev_err(dev, "unsupported clock rate\n");
return ret;
}
static void rsnd_ssi_master_clk_stop(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
if (!rsnd_rdai_is_clk_master(rdai))
return;
if (!rsnd_ssi_can_output_clk(mod))
return;
if (ssi->usrcnt > 1)
return;
ssi->cr_clk = 0;
ssi->rate = 0;
ssi->chan = 0;
rsnd_adg_ssi_clk_stop(mod);
}
static void rsnd_ssi_config_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct device *dev = rsnd_priv_to_dev(priv);
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
u32 cr_own = ssi->cr_own;
u32 cr_mode = ssi->cr_mode;
u32 wsr = ssi->wsr;
int width;
int is_tdm, is_tdm_split;
is_tdm = rsnd_runtime_is_tdm(io);
is_tdm_split = rsnd_runtime_is_tdm_split(io);
if (is_tdm)
dev_dbg(dev, "TDM mode\n");
if (is_tdm_split)
dev_dbg(dev, "TDM Split mode\n");
cr_own |= FORCE | rsnd_rdai_width_to_swl(rdai);
if (rdai->bit_clk_inv)
cr_own |= SCKP;
if (rdai->frm_clk_inv && !is_tdm)
cr_own |= SWSP;
if (rdai->data_alignment)
cr_own |= SDTA;
if (rdai->sys_delay)
cr_own |= DEL;
/*
* TDM Mode
* see
* rsnd_ssiu_init_gen2()
*/
if (is_tdm || is_tdm_split) {
wsr |= WS_MODE;
cr_own |= CHNL_8;
}
/*
* We shouldn't exchange SWSP after running.
* This means, parent needs to care it.
*/
if (rsnd_ssi_is_parent(mod, io))
goto init_end;
if (rsnd_io_is_play(io))
cr_own |= TRMD;
cr_own &= ~DWL_MASK;
width = snd_pcm_format_width(runtime->format);
if (is_tdm_split) {
/*
* The SWL and DWL bits in SSICR should be fixed at 32-bit
* setting when TDM split mode.
* see datasheet
* Operation :: TDM Format Split Function (TDM Split Mode)
*/
width = 32;
}
switch (width) {
case 8:
cr_own |= DWL_8;
break;
case 16:
cr_own |= DWL_16;
break;
case 24:
cr_own |= DWL_24;
break;
case 32:
cr_own |= DWL_32;
break;
}
if (rsnd_ssi_is_dma_mode(mod)) {
cr_mode = UIEN | OIEN | /* over/under run */
DMEN; /* DMA : enable DMA */
} else {
cr_mode = DIEN; /* PIO : enable Data interrupt */
}
init_end:
ssi->cr_own = cr_own;
ssi->cr_mode = cr_mode;
ssi->wsr = wsr;
}
static void rsnd_ssi_register_setup(struct rsnd_mod *mod)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
rsnd_mod_write(mod, SSIWSR, ssi->wsr);
rsnd_mod_write(mod, SSICR, ssi->cr_own |
ssi->cr_clk |
ssi->cr_mode |
ssi->cr_en);
}
/*
* SSI mod common functions
*/
static int rsnd_ssi_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
int ret;
if (!rsnd_ssi_is_run_mods(mod, io))
return 0;
ret = rsnd_ssi_master_clk_start(mod, io);
if (ret < 0)
return ret;
ssi->usrcnt++;
ret = rsnd_mod_power_on(mod);
if (ret < 0)
return ret;
rsnd_ssi_config_init(mod, io);
rsnd_ssi_register_setup(mod);
/* clear error status */
rsnd_ssi_status_clear(mod);
return 0;
}
static int rsnd_ssi_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
struct device *dev = rsnd_priv_to_dev(priv);
if (!rsnd_ssi_is_run_mods(mod, io))
return 0;
if (!ssi->usrcnt) {
dev_err(dev, "%s usrcnt error\n", rsnd_mod_name(mod));
return -EIO;
}
rsnd_ssi_master_clk_stop(mod, io);
rsnd_mod_power_off(mod);
ssi->usrcnt--;
if (!ssi->usrcnt) {
ssi->cr_own = 0;
ssi->cr_mode = 0;
ssi->wsr = 0;
}
return 0;
}
static int rsnd_ssi_hw_params(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
unsigned int fmt_width = snd_pcm_format_width(params_format(params));
if (fmt_width > rdai->chan_width) {
struct rsnd_priv *priv = rsnd_io_to_priv(io);
struct device *dev = rsnd_priv_to_dev(priv);
dev_err(dev, "invalid combination of slot-width and format-data-width\n");
return -EINVAL;
}
return 0;
}
static int rsnd_ssi_start(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
if (!rsnd_ssi_is_run_mods(mod, io))
return 0;
/*
* EN will be set via SSIU :: SSI_CONTROL
* if Multi channel mode
*/
if (rsnd_ssi_multi_secondaries_runtime(io))
return 0;
/*
* EN is for data output.
* SSI parent EN is not needed.
*/
if (rsnd_ssi_is_parent(mod, io))
return 0;
ssi->cr_en = EN;
rsnd_mod_write(mod, SSICR, ssi->cr_own |
ssi->cr_clk |
ssi->cr_mode |
ssi->cr_en);
return 0;
}
static int rsnd_ssi_stop(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
u32 cr;
if (!rsnd_ssi_is_run_mods(mod, io))
return 0;
if (rsnd_ssi_is_parent(mod, io))
return 0;
cr = ssi->cr_own |
ssi->cr_clk;
/*
* disable all IRQ,
* Playback: Wait all data was sent
* Capture: It might not receave data. Do nothing
*/
if (rsnd_io_is_play(io)) {
rsnd_mod_write(mod, SSICR, cr | ssi->cr_en);
rsnd_ssi_status_check(mod, DIRQ);
}
/* In multi-SSI mode, stop is performed by setting ssi0129 in
* SSI_CONTROL to 0 (in rsnd_ssio_stop_gen2). Do nothing here.
*/
if (rsnd_ssi_multi_secondaries_runtime(io))
return 0;
/*
* disable SSI,
* and, wait idle state
*/
rsnd_mod_write(mod, SSICR, cr); /* disabled all */
rsnd_ssi_status_check(mod, IIRQ);
ssi->cr_en = 0;
return 0;
}
static int rsnd_ssi_irq(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv,
int enable)
{
u32 val = 0;
int is_tdm, is_tdm_split;
int id = rsnd_mod_id(mod);
is_tdm = rsnd_runtime_is_tdm(io);
is_tdm_split = rsnd_runtime_is_tdm_split(io);
if (rsnd_is_gen1(priv))
return 0;
if (rsnd_ssi_is_parent(mod, io))
return 0;
if (!rsnd_ssi_is_run_mods(mod, io))
return 0;
if (enable)
val = rsnd_ssi_is_dma_mode(mod) ? 0x0e000000 : 0x0f000000;
if (is_tdm || is_tdm_split) {
switch (id) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 9:
val |= 0x0000ff00;
break;
}
}
rsnd_mod_write(mod, SSI_INT_ENABLE, val);
return 0;
}
static bool rsnd_ssi_pio_interrupt(struct rsnd_mod *mod,
struct rsnd_dai_stream *io);
static void __rsnd_ssi_interrupt(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
int is_dma = rsnd_ssi_is_dma_mode(mod);
u32 status;
bool elapsed = false;
bool stop = false;
spin_lock(&priv->lock);
/* ignore all cases if not working */
if (!rsnd_io_is_working(io))
goto rsnd_ssi_interrupt_out;
status = rsnd_ssi_status_get(mod);
/* PIO only */
if (!is_dma && (status & DIRQ))
elapsed = rsnd_ssi_pio_interrupt(mod, io);
/* DMA only */
if (is_dma && (status & (UIRQ | OIRQ))) {
rsnd_print_irq_status(dev, "%s err status : 0x%08x\n",
rsnd_mod_name(mod), status);
stop = true;
}
stop |= rsnd_ssiu_busif_err_status_clear(mod);
rsnd_ssi_status_clear(mod);
rsnd_ssi_interrupt_out:
spin_unlock(&priv->lock);
if (elapsed)
rsnd_dai_period_elapsed(io);
if (stop)
snd_pcm_stop_xrun(io->substream);
}
static irqreturn_t rsnd_ssi_interrupt(int irq, void *data)
{
struct rsnd_mod *mod = data;
rsnd_mod_interrupt(mod, __rsnd_ssi_interrupt);
return IRQ_HANDLED;
}
static u32 *rsnd_ssi_get_status(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
enum rsnd_mod_type type)
{
/*
* SSIP (= SSI parent) needs to be special, otherwise,
* 2nd SSI might doesn't start. see also rsnd_mod_call()
*
* We can't include parent SSI status on SSI, because we don't know
* how many SSI requests parent SSI. Thus, it is localed on "io" now.
* ex) trouble case
* Playback: SSI0
* Capture : SSI1 (needs SSI0)
*
* 1) start Capture -> SSI0/SSI1 are started.
* 2) start Playback -> SSI0 doesn't work, because it is already
* marked as "started" on 1)
*
* OTOH, using each mod's status is good for MUX case.
* It doesn't need to start in 2nd start
* ex)
* IO-0: SRC0 -> CTU1 -+-> MUX -> DVC -> SSIU -> SSI0
* |
* IO-1: SRC1 -> CTU2 -+
*
* 1) start IO-0 -> start SSI0
* 2) start IO-1 -> SSI0 doesn't need to start, because it is
* already started on 1)
*/
if (type == RSND_MOD_SSIP)
return &io->parent_ssi_status;
return rsnd_mod_get_status(mod, io, type);
}
/*
* SSI PIO
*/
static void rsnd_ssi_parent_attach(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
if (!__rsnd_ssi_is_pin_sharing(mod))
return;
if (!rsnd_rdai_is_clk_master(rdai))
return;
if (rsnd_ssi_is_multi_secondary(mod, io))
return;
switch (rsnd_mod_id(mod)) {
case 1:
case 2:
case 9:
rsnd_dai_connect(rsnd_ssi_mod_get(priv, 0), io, RSND_MOD_SSIP);
break;
case 4:
rsnd_dai_connect(rsnd_ssi_mod_get(priv, 3), io, RSND_MOD_SSIP);
break;
case 8:
rsnd_dai_connect(rsnd_ssi_mod_get(priv, 7), io, RSND_MOD_SSIP);
break;
}
}
static int rsnd_ssi_pcm_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd)
{
/*
* rsnd_rdai_is_clk_master() will be enabled after set_fmt,
* and, pcm_new will be called after it.
* This function reuse pcm_new at this point.
*/
rsnd_ssi_parent_attach(mod, io);
return 0;
}
static int rsnd_ssi_common_probe(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
int ret = 0;
/*
* SSIP/SSIU/IRQ are not needed on
* SSI Multi secondaries
*/
if (rsnd_ssi_is_multi_secondary(mod, io))
return 0;
/*
* It can't judge ssi parent at this point
* see rsnd_ssi_pcm_new()
*/
/*
* SSI might be called again as PIO fallback
* It is easy to manual handling for IRQ request/free
*
* OTOH, this function might be called many times if platform is
* using MIX. It needs xxx_attach() many times on xxx_probe().
* Because of it, we can't control .probe/.remove calling count by
* mod->status.
* But it don't need to call request_irq() many times.
* Let's control it by RSND_SSI_PROBED flag.
*/
if (!rsnd_flags_has(ssi, RSND_SSI_PROBED)) {
ret = request_irq(ssi->irq,
rsnd_ssi_interrupt,
IRQF_SHARED,
dev_name(dev), mod);
rsnd_flags_set(ssi, RSND_SSI_PROBED);
}
return ret;
}
static int rsnd_ssi_common_remove(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
struct rsnd_mod *pure_ssi_mod = rsnd_io_to_mod_ssi(io);
/* Do nothing if non SSI (= SSI parent, multi SSI) mod */
if (pure_ssi_mod != mod)
return 0;
/* PIO will request IRQ again */
if (rsnd_flags_has(ssi, RSND_SSI_PROBED)) {
free_irq(ssi->irq, mod);
rsnd_flags_del(ssi, RSND_SSI_PROBED);
}
return 0;
}
/*
* SSI PIO functions
*/
static bool rsnd_ssi_pio_interrupt(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
u32 *buf = (u32 *)(runtime->dma_area + ssi->byte_pos);
int shift = 0;
int byte_pos;
bool elapsed = false;
if (snd_pcm_format_width(runtime->format) == 24)
shift = 8;
/*
* 8/16/32 data can be assesse to TDR/RDR register
* directly as 32bit data
* see rsnd_ssi_init()
*/
if (rsnd_io_is_play(io))
rsnd_mod_write(mod, SSITDR, (*buf) << shift);
else
*buf = (rsnd_mod_read(mod, SSIRDR) >> shift);
byte_pos = ssi->byte_pos + sizeof(*buf);
if (byte_pos >= ssi->next_period_byte) {
int period_pos = byte_pos / ssi->byte_per_period;
if (period_pos >= runtime->periods) {
byte_pos = 0;
period_pos = 0;
}
ssi->next_period_byte = (period_pos + 1) * ssi->byte_per_period;
elapsed = true;
}
WRITE_ONCE(ssi->byte_pos, byte_pos);
return elapsed;
}
static int rsnd_ssi_pio_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
if (!rsnd_ssi_is_parent(mod, io)) {
ssi->byte_pos = 0;
ssi->byte_per_period = runtime->period_size *
runtime->channels *
samples_to_bytes(runtime, 1);
ssi->next_period_byte = ssi->byte_per_period;
}
return rsnd_ssi_init(mod, io, priv);
}
static int rsnd_ssi_pio_pointer(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
snd_pcm_uframes_t *pointer)
{
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
*pointer = bytes_to_frames(runtime, READ_ONCE(ssi->byte_pos));
return 0;
}
static struct rsnd_mod_ops rsnd_ssi_pio_ops = {
.name = SSI_NAME,
.probe = rsnd_ssi_common_probe,
.remove = rsnd_ssi_common_remove,
.init = rsnd_ssi_pio_init,
.quit = rsnd_ssi_quit,
.start = rsnd_ssi_start,
.stop = rsnd_ssi_stop,
.irq = rsnd_ssi_irq,
.pointer = rsnd_ssi_pio_pointer,
.pcm_new = rsnd_ssi_pcm_new,
.hw_params = rsnd_ssi_hw_params,
.get_status = rsnd_ssi_get_status,
};
static int rsnd_ssi_dma_probe(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
int ret;
/*
* SSIP/SSIU/IRQ/DMA are not needed on
* SSI Multi secondaries
*/
if (rsnd_ssi_is_multi_secondary(mod, io))
return 0;
ret = rsnd_ssi_common_probe(mod, io, priv);
if (ret)
return ret;
/* SSI probe might be called many times in MUX multi path */
ret = rsnd_dma_attach(io, mod, &io->dma);
return ret;
}
static int rsnd_ssi_fallback(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
/*
* fallback to PIO
*
* SSI .probe might be called again.
* see
* rsnd_rdai_continuance_probe()
*/
mod->ops = &rsnd_ssi_pio_ops;
dev_info(dev, "%s fallback to PIO mode\n", rsnd_mod_name(mod));
return 0;
}
static struct dma_chan *rsnd_ssi_dma_req(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
int is_play = rsnd_io_is_play(io);
char *name;
/*
* It should use "rcar_sound,ssiu" on DT.
* But, we need to keep compatibility for old version.
*
* If it has "rcar_sound.ssiu", it will be used.
* If not, "rcar_sound.ssi" will be used.
* see
* rsnd_ssiu_dma_req()
* rsnd_dma_of_path()
*/
if (rsnd_ssi_use_busif(io))
name = is_play ? "rxu" : "txu";
else
name = is_play ? "rx" : "tx";
return rsnd_dma_request_channel(rsnd_ssi_of_node(priv),
SSI_NAME, mod, name);
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_ssi_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
seq_printf(m, "clock: %s\n", rsnd_rdai_is_clk_master(rdai) ?
"provider" : "consumer");
seq_printf(m, "bit_clk_inv: %d\n", rdai->bit_clk_inv);
seq_printf(m, "frm_clk_inv: %d\n", rdai->frm_clk_inv);
seq_printf(m, "pin share: %d\n", __rsnd_ssi_is_pin_sharing(mod));
seq_printf(m, "can out clk: %d\n", rsnd_ssi_can_output_clk(mod));
seq_printf(m, "multi secondary: %d\n", rsnd_ssi_is_multi_secondary(mod, io));
seq_printf(m, "tdm: %d, %d\n", rsnd_runtime_is_tdm(io),
rsnd_runtime_is_tdm_split(io));
seq_printf(m, "chan: %d\n", ssi->chan);
seq_printf(m, "user: %d\n", ssi->usrcnt);
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SSI,
rsnd_mod_id(mod) * 0x40, 0x40);
}
#define DEBUG_INFO .debug_info = rsnd_ssi_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_ssi_dma_ops = {
.name = SSI_NAME,
.dma_req = rsnd_ssi_dma_req,
.probe = rsnd_ssi_dma_probe,
.remove = rsnd_ssi_common_remove,
.init = rsnd_ssi_init,
.quit = rsnd_ssi_quit,
.start = rsnd_ssi_start,
.stop = rsnd_ssi_stop,
.irq = rsnd_ssi_irq,
.pcm_new = rsnd_ssi_pcm_new,
.fallback = rsnd_ssi_fallback,
.hw_params = rsnd_ssi_hw_params,
.get_status = rsnd_ssi_get_status,
DEBUG_INFO
};
int rsnd_ssi_is_dma_mode(struct rsnd_mod *mod)
{
return mod->ops == &rsnd_ssi_dma_ops;
}
/*
* ssi mod function
*/
static void rsnd_ssi_connect(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
static const enum rsnd_mod_type types[] = {
RSND_MOD_SSI,
RSND_MOD_SSIM1,
RSND_MOD_SSIM2,
RSND_MOD_SSIM3,
};
enum rsnd_mod_type type;
int i;
/* try SSI -> SSIM1 -> SSIM2 -> SSIM3 */
for (i = 0; i < ARRAY_SIZE(types); i++) {
type = types[i];
if (!rsnd_io_to_mod(io, type)) {
rsnd_dai_connect(mod, io, type);
rsnd_rdai_channels_set(rdai, (i + 1) * 2);
rsnd_rdai_ssi_lane_set(rdai, (i + 1));
return;
}
}
}
void rsnd_parse_connect_ssi(struct rsnd_dai *rdai,
struct device_node *playback,
struct device_node *capture)
{
struct rsnd_priv *priv = rsnd_rdai_to_priv(rdai);
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *node;
struct device_node *np;
int i;
node = rsnd_ssi_of_node(priv);
if (!node)
return;
i = 0;
for_each_child_of_node(node, np) {
struct rsnd_mod *mod;
i = rsnd_node_fixed_index(dev, np, SSI_NAME, i);
if (i < 0) {
of_node_put(np);
break;
}
mod = rsnd_ssi_mod_get(priv, i);
if (np == playback)
rsnd_ssi_connect(mod, &rdai->playback);
if (np == capture)
rsnd_ssi_connect(mod, &rdai->capture);
i++;
}
of_node_put(node);
}
struct rsnd_mod *rsnd_ssi_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_ssi_nr(priv)))
id = 0;
return rsnd_mod_get(rsnd_ssi_get(priv, id));
}
int __rsnd_ssi_is_pin_sharing(struct rsnd_mod *mod)
{
if (!mod)
return 0;
return !!(rsnd_flags_has(rsnd_mod_to_ssi(mod), RSND_SSI_CLK_PIN_SHARE));
}
int rsnd_ssi_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mod_ops *ops;
struct clk *clk;
struct rsnd_ssi *ssi;
char name[RSND_SSI_NAME_SIZE];
int i, nr, ret;
node = rsnd_ssi_of_node(priv);
if (!node)
return -EINVAL;
nr = rsnd_node_count(priv, node, SSI_NAME);
if (!nr) {
ret = -EINVAL;
goto rsnd_ssi_probe_done;
}
ssi = devm_kcalloc(dev, nr, sizeof(*ssi), GFP_KERNEL);
if (!ssi) {
ret = -ENOMEM;
goto rsnd_ssi_probe_done;
}
priv->ssi = ssi;
priv->ssi_nr = nr;
i = 0;
for_each_child_of_node(node, np) {
if (!of_device_is_available(np))
goto skip;
i = rsnd_node_fixed_index(dev, np, SSI_NAME, i);
if (i < 0) {
ret = -EINVAL;
of_node_put(np);
goto rsnd_ssi_probe_done;
}
ssi = rsnd_ssi_get(priv, i);
snprintf(name, RSND_SSI_NAME_SIZE, "%s.%d",
SSI_NAME, i);
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_ssi_probe_done;
}
if (of_property_read_bool(np, "shared-pin"))
rsnd_flags_set(ssi, RSND_SSI_CLK_PIN_SHARE);
if (of_property_read_bool(np, "no-busif"))
rsnd_flags_set(ssi, RSND_SSI_NO_BUSIF);
ssi->irq = irq_of_parse_and_map(np, 0);
if (!ssi->irq) {
ret = -EINVAL;
of_node_put(np);
goto rsnd_ssi_probe_done;
}
if (of_property_read_bool(np, "pio-transfer"))
ops = &rsnd_ssi_pio_ops;
else
ops = &rsnd_ssi_dma_ops;
ret = rsnd_mod_init(priv, rsnd_mod_get(ssi), ops, clk,
RSND_MOD_SSI, i);
if (ret) {
of_node_put(np);
goto rsnd_ssi_probe_done;
}
skip:
i++;
}
ret = 0;
rsnd_ssi_probe_done:
of_node_put(node);
return ret;
}
void rsnd_ssi_remove(struct rsnd_priv *priv)
{
struct rsnd_ssi *ssi;
int i;
for_each_rsnd_ssi(ssi, priv, i) {
rsnd_mod_quit(rsnd_mod_get(ssi));
}
}
| linux-master | sound/soc/sh/rcar/ssi.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car Gen1 SRU/SSI support
//
// Copyright (C) 2013 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
/*
* #define DEBUG
*
* you can also add below in
* ${LINUX}/drivers/base/regmap/regmap.c
* for regmap debug
*
* #define LOG_DEVICE "xxxx.rcar_sound"
*/
#include "rsnd.h"
struct rsnd_gen {
struct rsnd_gen_ops *ops;
/* RSND_BASE_MAX base */
void __iomem *base[RSND_BASE_MAX];
phys_addr_t res[RSND_BASE_MAX];
struct regmap *regmap[RSND_BASE_MAX];
/* RSND_REG_MAX base */
struct regmap_field *regs[REG_MAX];
const char *reg_name[REG_MAX];
};
#define rsnd_priv_to_gen(p) ((struct rsnd_gen *)(p)->gen)
#define rsnd_reg_name(gen, id) ((gen)->reg_name[id])
struct rsnd_regmap_field_conf {
int idx;
unsigned int reg_offset;
unsigned int id_offset;
const char *reg_name;
};
#define RSND_REG_SET(id, offset, _id_offset, n) \
{ \
.idx = id, \
.reg_offset = offset, \
.id_offset = _id_offset, \
.reg_name = n, \
}
/* single address mapping */
#define RSND_GEN_S_REG(id, offset) \
RSND_REG_SET(id, offset, 0, #id)
/* multi address mapping */
#define RSND_GEN_M_REG(id, offset, _id_offset) \
RSND_REG_SET(id, offset, _id_offset, #id)
/*
* basic function
*/
static int rsnd_is_accessible_reg(struct rsnd_priv *priv,
struct rsnd_gen *gen, enum rsnd_reg reg)
{
if (!gen->regs[reg]) {
struct device *dev = rsnd_priv_to_dev(priv);
dev_err(dev, "unsupported register access %x\n", reg);
return 0;
}
return 1;
}
static int rsnd_mod_id_cmd(struct rsnd_mod *mod)
{
if (mod->ops->id_cmd)
return mod->ops->id_cmd(mod);
return rsnd_mod_id(mod);
}
u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
u32 val;
if (!rsnd_is_accessible_reg(priv, gen, reg))
return 0;
regmap_fields_read(gen->regs[reg], rsnd_mod_id_cmd(mod), &val);
dev_dbg(dev, "r %s - %-18s (%4d) : %08x\n",
rsnd_mod_name(mod),
rsnd_reg_name(gen, reg), reg, val);
return val;
}
void rsnd_mod_write(struct rsnd_mod *mod,
enum rsnd_reg reg, u32 data)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
if (!rsnd_is_accessible_reg(priv, gen, reg))
return;
regmap_fields_force_write(gen->regs[reg], rsnd_mod_id_cmd(mod), data);
dev_dbg(dev, "w %s - %-18s (%4d) : %08x\n",
rsnd_mod_name(mod),
rsnd_reg_name(gen, reg), reg, data);
}
void rsnd_mod_bset(struct rsnd_mod *mod,
enum rsnd_reg reg, u32 mask, u32 data)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
if (!rsnd_is_accessible_reg(priv, gen, reg))
return;
regmap_fields_force_update_bits(gen->regs[reg],
rsnd_mod_id_cmd(mod), mask, data);
dev_dbg(dev, "b %s - %-18s (%4d) : %08x/%08x\n",
rsnd_mod_name(mod),
rsnd_reg_name(gen, reg), reg, data, mask);
}
phys_addr_t rsnd_gen_get_phy_addr(struct rsnd_priv *priv, int reg_id)
{
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
return gen->res[reg_id];
}
#ifdef CONFIG_DEBUG_FS
void __iomem *rsnd_gen_get_base_addr(struct rsnd_priv *priv, int reg_id)
{
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
return gen->base[reg_id];
}
#endif
#define rsnd_gen_regmap_init(priv, id_size, reg_id, name, conf) \
_rsnd_gen_regmap_init(priv, id_size, reg_id, name, conf, ARRAY_SIZE(conf))
static int _rsnd_gen_regmap_init(struct rsnd_priv *priv,
int id_size,
int reg_id,
const char *name,
const struct rsnd_regmap_field_conf *conf,
int conf_size)
{
struct platform_device *pdev = rsnd_priv_to_pdev(priv);
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
struct device *dev = rsnd_priv_to_dev(priv);
struct resource *res;
struct regmap_config regc;
struct regmap_field *regs;
struct regmap *regmap;
struct reg_field regf;
void __iomem *base;
int i;
memset(®c, 0, sizeof(regc));
regc.reg_bits = 32;
regc.val_bits = 32;
regc.reg_stride = 4;
regc.name = name;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
if (!res)
res = platform_get_resource(pdev, IORESOURCE_MEM, reg_id);
if (!res)
return -ENODEV;
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, ®c);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* RSND_BASE_MAX base */
gen->base[reg_id] = base;
gen->regmap[reg_id] = regmap;
gen->res[reg_id] = res->start;
for (i = 0; i < conf_size; i++) {
regf.reg = conf[i].reg_offset;
regf.id_offset = conf[i].id_offset;
regf.lsb = 0;
regf.msb = 31;
regf.id_size = id_size;
regs = devm_regmap_field_alloc(dev, regmap, regf);
if (IS_ERR(regs))
return PTR_ERR(regs);
/* RSND_REG_MAX base */
gen->regs[conf[i].idx] = regs;
gen->reg_name[conf[i].idx] = conf[i].reg_name;
}
return 0;
}
/*
* Gen4
*/
static int rsnd_gen4_probe(struct rsnd_priv *priv)
{
static const struct rsnd_regmap_field_conf conf_ssiu[] = {
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE6, 0x898),
RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
RSND_GEN_S_REG(SSI_SYS_STATUS4, 0x880),
RSND_GEN_S_REG(SSI_SYS_STATUS6, 0x888),
RSND_GEN_S_REG(SSI_BUSIF0_MODE, 0x0),
RSND_GEN_S_REG(SSI_BUSIF0_ADINR, 0x4),
RSND_GEN_S_REG(SSI_BUSIF0_DALIGN, 0x8),
RSND_GEN_S_REG(SSI_BUSIF1_MODE, 0x20),
RSND_GEN_S_REG(SSI_BUSIF1_ADINR, 0x24),
RSND_GEN_S_REG(SSI_BUSIF1_DALIGN, 0x28),
RSND_GEN_S_REG(SSI_BUSIF2_MODE, 0x40),
RSND_GEN_S_REG(SSI_BUSIF2_ADINR, 0x44),
RSND_GEN_S_REG(SSI_BUSIF2_DALIGN, 0x48),
RSND_GEN_S_REG(SSI_BUSIF3_MODE, 0x60),
RSND_GEN_S_REG(SSI_BUSIF3_ADINR, 0x64),
RSND_GEN_S_REG(SSI_BUSIF3_DALIGN, 0x68),
RSND_GEN_S_REG(SSI_BUSIF4_MODE, 0x500),
RSND_GEN_S_REG(SSI_BUSIF4_ADINR, 0x504),
RSND_GEN_S_REG(SSI_BUSIF4_DALIGN, 0x508),
RSND_GEN_S_REG(SSI_BUSIF5_MODE, 0x520),
RSND_GEN_S_REG(SSI_BUSIF5_ADINR, 0x524),
RSND_GEN_S_REG(SSI_BUSIF5_DALIGN, 0x528),
RSND_GEN_S_REG(SSI_BUSIF6_MODE, 0x540),
RSND_GEN_S_REG(SSI_BUSIF6_ADINR, 0x544),
RSND_GEN_S_REG(SSI_BUSIF6_DALIGN, 0x548),
RSND_GEN_S_REG(SSI_BUSIF7_MODE, 0x560),
RSND_GEN_S_REG(SSI_BUSIF7_ADINR, 0x564),
RSND_GEN_S_REG(SSI_BUSIF7_DALIGN, 0x568),
RSND_GEN_S_REG(SSI_CTRL, 0x010),
RSND_GEN_S_REG(SSI_INT_ENABLE, 0x018),
RSND_GEN_S_REG(SSI_MODE, 0x00c),
RSND_GEN_S_REG(SSI_MODE2, 0xa0c),
};
static const struct rsnd_regmap_field_conf conf_adg[] = {
RSND_GEN_S_REG(BRRA, 0x00),
RSND_GEN_S_REG(BRRB, 0x04),
RSND_GEN_S_REG(BRGCKR, 0x08),
RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
};
static const struct rsnd_regmap_field_conf conf_ssi[] = {
RSND_GEN_S_REG(SSICR, 0x00),
RSND_GEN_S_REG(SSISR, 0x04),
RSND_GEN_S_REG(SSITDR, 0x08),
RSND_GEN_S_REG(SSIRDR, 0x0c),
RSND_GEN_S_REG(SSIWSR, 0x20),
};
static const struct rsnd_regmap_field_conf conf_sdmc[] = {
RSND_GEN_M_REG(SSI_BUSIF, 0x0, 0x8000),
};
int ret_adg = rsnd_gen_regmap_init(priv, 10, RSND_GEN4_ADG, "adg", conf_adg);
int ret_ssiu = rsnd_gen_regmap_init(priv, 10, RSND_GEN4_SSIU, "ssiu", conf_ssiu);
int ret_ssi = rsnd_gen_regmap_init(priv, 10, RSND_GEN4_SSI, "ssi", conf_ssi);
int ret_sdmc = rsnd_gen_regmap_init(priv, 10, RSND_GEN4_SDMC, "sdmc", conf_sdmc);
return ret_adg | ret_ssiu | ret_ssi | ret_sdmc;
}
/*
* Gen2
*/
static int rsnd_gen2_probe(struct rsnd_priv *priv)
{
static const struct rsnd_regmap_field_conf conf_ssiu[] = {
RSND_GEN_S_REG(SSI_MODE0, 0x800),
RSND_GEN_S_REG(SSI_MODE1, 0x804),
RSND_GEN_S_REG(SSI_MODE2, 0x808),
RSND_GEN_S_REG(SSI_CONTROL, 0x810),
RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844),
RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c),
RSND_GEN_S_REG(SSI_SYS_STATUS4, 0x880),
RSND_GEN_S_REG(SSI_SYS_STATUS5, 0x884),
RSND_GEN_S_REG(SSI_SYS_STATUS6, 0x888),
RSND_GEN_S_REG(SSI_SYS_STATUS7, 0x88c),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE1, 0x854),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE3, 0x85c),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE5, 0x894),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE6, 0x898),
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE7, 0x89c),
RSND_GEN_S_REG(HDMI0_SEL, 0x9e0),
RSND_GEN_S_REG(HDMI1_SEL, 0x9e4),
/* FIXME: it needs SSI_MODE2/3 in the future */
RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80),
RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80),
RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80),
RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80),
RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80),
RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80),
RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80),
RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80),
RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80),
RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80),
RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80),
RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80),
RSND_GEN_M_REG(SSI_BUSIF4_MODE, 0x500, 0x80),
RSND_GEN_M_REG(SSI_BUSIF4_ADINR, 0x504, 0x80),
RSND_GEN_M_REG(SSI_BUSIF4_DALIGN, 0x508, 0x80),
RSND_GEN_M_REG(SSI_BUSIF5_MODE, 0x520, 0x80),
RSND_GEN_M_REG(SSI_BUSIF5_ADINR, 0x524, 0x80),
RSND_GEN_M_REG(SSI_BUSIF5_DALIGN, 0x528, 0x80),
RSND_GEN_M_REG(SSI_BUSIF6_MODE, 0x540, 0x80),
RSND_GEN_M_REG(SSI_BUSIF6_ADINR, 0x544, 0x80),
RSND_GEN_M_REG(SSI_BUSIF6_DALIGN, 0x548, 0x80),
RSND_GEN_M_REG(SSI_BUSIF7_MODE, 0x560, 0x80),
RSND_GEN_M_REG(SSI_BUSIF7_ADINR, 0x564, 0x80),
RSND_GEN_M_REG(SSI_BUSIF7_DALIGN, 0x568, 0x80),
RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80),
RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80),
RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80),
RSND_GEN_S_REG(SSI9_BUSIF0_MODE, 0x48c),
RSND_GEN_S_REG(SSI9_BUSIF0_ADINR, 0x484),
RSND_GEN_S_REG(SSI9_BUSIF0_DALIGN, 0x488),
RSND_GEN_S_REG(SSI9_BUSIF1_MODE, 0x4a0),
RSND_GEN_S_REG(SSI9_BUSIF1_ADINR, 0x4a4),
RSND_GEN_S_REG(SSI9_BUSIF1_DALIGN, 0x4a8),
RSND_GEN_S_REG(SSI9_BUSIF2_MODE, 0x4c0),
RSND_GEN_S_REG(SSI9_BUSIF2_ADINR, 0x4c4),
RSND_GEN_S_REG(SSI9_BUSIF2_DALIGN, 0x4c8),
RSND_GEN_S_REG(SSI9_BUSIF3_MODE, 0x4e0),
RSND_GEN_S_REG(SSI9_BUSIF3_ADINR, 0x4e4),
RSND_GEN_S_REG(SSI9_BUSIF3_DALIGN, 0x4e8),
RSND_GEN_S_REG(SSI9_BUSIF4_MODE, 0xd80),
RSND_GEN_S_REG(SSI9_BUSIF4_ADINR, 0xd84),
RSND_GEN_S_REG(SSI9_BUSIF4_DALIGN, 0xd88),
RSND_GEN_S_REG(SSI9_BUSIF5_MODE, 0xda0),
RSND_GEN_S_REG(SSI9_BUSIF5_ADINR, 0xda4),
RSND_GEN_S_REG(SSI9_BUSIF5_DALIGN, 0xda8),
RSND_GEN_S_REG(SSI9_BUSIF6_MODE, 0xdc0),
RSND_GEN_S_REG(SSI9_BUSIF6_ADINR, 0xdc4),
RSND_GEN_S_REG(SSI9_BUSIF6_DALIGN, 0xdc8),
RSND_GEN_S_REG(SSI9_BUSIF7_MODE, 0xde0),
RSND_GEN_S_REG(SSI9_BUSIF7_ADINR, 0xde4),
RSND_GEN_S_REG(SSI9_BUSIF7_DALIGN, 0xde8),
};
static const struct rsnd_regmap_field_conf conf_scu[] = {
RSND_GEN_M_REG(SRC_I_BUSIF_MODE,0x0, 0x20),
RSND_GEN_M_REG(SRC_O_BUSIF_MODE,0x4, 0x20),
RSND_GEN_M_REG(SRC_BUSIF_DALIGN,0x8, 0x20),
RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20),
RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20),
RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20),
RSND_GEN_M_REG(CMD_BUSIF_MODE, 0x184, 0x20),
RSND_GEN_M_REG(CMD_BUSIF_DALIGN,0x188, 0x20),
RSND_GEN_M_REG(CMD_ROUTE_SLCT, 0x18c, 0x20),
RSND_GEN_M_REG(CMD_CTRL, 0x190, 0x20),
RSND_GEN_S_REG(SCU_SYS_STATUS0, 0x1c8),
RSND_GEN_S_REG(SCU_SYS_INT_EN0, 0x1cc),
RSND_GEN_S_REG(SCU_SYS_STATUS1, 0x1d0),
RSND_GEN_S_REG(SCU_SYS_INT_EN1, 0x1d4),
RSND_GEN_M_REG(SRC_SWRSR, 0x200, 0x40),
RSND_GEN_M_REG(SRC_SRCIR, 0x204, 0x40),
RSND_GEN_M_REG(SRC_ADINR, 0x214, 0x40),
RSND_GEN_M_REG(SRC_IFSCR, 0x21c, 0x40),
RSND_GEN_M_REG(SRC_IFSVR, 0x220, 0x40),
RSND_GEN_M_REG(SRC_SRCCR, 0x224, 0x40),
RSND_GEN_M_REG(SRC_BSDSR, 0x22c, 0x40),
RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40),
RSND_GEN_M_REG(CTU_SWRSR, 0x500, 0x100),
RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100),
RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100),
RSND_GEN_M_REG(CTU_CPMDR, 0x510, 0x100),
RSND_GEN_M_REG(CTU_SCMDR, 0x514, 0x100),
RSND_GEN_M_REG(CTU_SV00R, 0x518, 0x100),
RSND_GEN_M_REG(CTU_SV01R, 0x51c, 0x100),
RSND_GEN_M_REG(CTU_SV02R, 0x520, 0x100),
RSND_GEN_M_REG(CTU_SV03R, 0x524, 0x100),
RSND_GEN_M_REG(CTU_SV04R, 0x528, 0x100),
RSND_GEN_M_REG(CTU_SV05R, 0x52c, 0x100),
RSND_GEN_M_REG(CTU_SV06R, 0x530, 0x100),
RSND_GEN_M_REG(CTU_SV07R, 0x534, 0x100),
RSND_GEN_M_REG(CTU_SV10R, 0x538, 0x100),
RSND_GEN_M_REG(CTU_SV11R, 0x53c, 0x100),
RSND_GEN_M_REG(CTU_SV12R, 0x540, 0x100),
RSND_GEN_M_REG(CTU_SV13R, 0x544, 0x100),
RSND_GEN_M_REG(CTU_SV14R, 0x548, 0x100),
RSND_GEN_M_REG(CTU_SV15R, 0x54c, 0x100),
RSND_GEN_M_REG(CTU_SV16R, 0x550, 0x100),
RSND_GEN_M_REG(CTU_SV17R, 0x554, 0x100),
RSND_GEN_M_REG(CTU_SV20R, 0x558, 0x100),
RSND_GEN_M_REG(CTU_SV21R, 0x55c, 0x100),
RSND_GEN_M_REG(CTU_SV22R, 0x560, 0x100),
RSND_GEN_M_REG(CTU_SV23R, 0x564, 0x100),
RSND_GEN_M_REG(CTU_SV24R, 0x568, 0x100),
RSND_GEN_M_REG(CTU_SV25R, 0x56c, 0x100),
RSND_GEN_M_REG(CTU_SV26R, 0x570, 0x100),
RSND_GEN_M_REG(CTU_SV27R, 0x574, 0x100),
RSND_GEN_M_REG(CTU_SV30R, 0x578, 0x100),
RSND_GEN_M_REG(CTU_SV31R, 0x57c, 0x100),
RSND_GEN_M_REG(CTU_SV32R, 0x580, 0x100),
RSND_GEN_M_REG(CTU_SV33R, 0x584, 0x100),
RSND_GEN_M_REG(CTU_SV34R, 0x588, 0x100),
RSND_GEN_M_REG(CTU_SV35R, 0x58c, 0x100),
RSND_GEN_M_REG(CTU_SV36R, 0x590, 0x100),
RSND_GEN_M_REG(CTU_SV37R, 0x594, 0x100),
RSND_GEN_M_REG(MIX_SWRSR, 0xd00, 0x40),
RSND_GEN_M_REG(MIX_MIXIR, 0xd04, 0x40),
RSND_GEN_M_REG(MIX_ADINR, 0xd08, 0x40),
RSND_GEN_M_REG(MIX_MIXMR, 0xd10, 0x40),
RSND_GEN_M_REG(MIX_MVPDR, 0xd14, 0x40),
RSND_GEN_M_REG(MIX_MDBAR, 0xd18, 0x40),
RSND_GEN_M_REG(MIX_MDBBR, 0xd1c, 0x40),
RSND_GEN_M_REG(MIX_MDBCR, 0xd20, 0x40),
RSND_GEN_M_REG(MIX_MDBDR, 0xd24, 0x40),
RSND_GEN_M_REG(MIX_MDBER, 0xd28, 0x40),
RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100),
RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100),
RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100),
RSND_GEN_M_REG(DVC_DVUCR, 0xe10, 0x100),
RSND_GEN_M_REG(DVC_ZCMCR, 0xe14, 0x100),
RSND_GEN_M_REG(DVC_VRCTR, 0xe18, 0x100),
RSND_GEN_M_REG(DVC_VRPDR, 0xe1c, 0x100),
RSND_GEN_M_REG(DVC_VRDBR, 0xe20, 0x100),
RSND_GEN_M_REG(DVC_VOL0R, 0xe28, 0x100),
RSND_GEN_M_REG(DVC_VOL1R, 0xe2c, 0x100),
RSND_GEN_M_REG(DVC_VOL2R, 0xe30, 0x100),
RSND_GEN_M_REG(DVC_VOL3R, 0xe34, 0x100),
RSND_GEN_M_REG(DVC_VOL4R, 0xe38, 0x100),
RSND_GEN_M_REG(DVC_VOL5R, 0xe3c, 0x100),
RSND_GEN_M_REG(DVC_VOL6R, 0xe40, 0x100),
RSND_GEN_M_REG(DVC_VOL7R, 0xe44, 0x100),
RSND_GEN_M_REG(DVC_DVUER, 0xe48, 0x100),
};
static const struct rsnd_regmap_field_conf conf_adg[] = {
RSND_GEN_S_REG(BRRA, 0x00),
RSND_GEN_S_REG(BRRB, 0x04),
RSND_GEN_S_REG(BRGCKR, 0x08),
RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10),
RSND_GEN_S_REG(AUDIO_CLK_SEL2, 0x14),
RSND_GEN_S_REG(DIV_EN, 0x30),
RSND_GEN_S_REG(SRCIN_TIMSEL0, 0x34),
RSND_GEN_S_REG(SRCIN_TIMSEL1, 0x38),
RSND_GEN_S_REG(SRCIN_TIMSEL2, 0x3c),
RSND_GEN_S_REG(SRCIN_TIMSEL3, 0x40),
RSND_GEN_S_REG(SRCIN_TIMSEL4, 0x44),
RSND_GEN_S_REG(SRCOUT_TIMSEL0, 0x48),
RSND_GEN_S_REG(SRCOUT_TIMSEL1, 0x4c),
RSND_GEN_S_REG(SRCOUT_TIMSEL2, 0x50),
RSND_GEN_S_REG(SRCOUT_TIMSEL3, 0x54),
RSND_GEN_S_REG(SRCOUT_TIMSEL4, 0x58),
RSND_GEN_S_REG(CMDOUT_TIMSEL, 0x5c),
};
static const struct rsnd_regmap_field_conf conf_ssi[] = {
RSND_GEN_M_REG(SSICR, 0x00, 0x40),
RSND_GEN_M_REG(SSISR, 0x04, 0x40),
RSND_GEN_M_REG(SSITDR, 0x08, 0x40),
RSND_GEN_M_REG(SSIRDR, 0x0c, 0x40),
RSND_GEN_M_REG(SSIWSR, 0x20, 0x40),
};
int ret_ssiu;
int ret_scu;
int ret_adg;
int ret_ssi;
ret_ssiu = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SSIU, "ssiu", conf_ssiu);
ret_scu = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SCU, "scu", conf_scu);
ret_adg = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_ADG, "adg", conf_adg);
ret_ssi = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SSI, "ssi", conf_ssi);
if (ret_ssiu < 0 ||
ret_scu < 0 ||
ret_adg < 0 ||
ret_ssi < 0)
return ret_ssiu | ret_scu | ret_adg | ret_ssi;
return 0;
}
/*
* Gen1
*/
static int rsnd_gen1_probe(struct rsnd_priv *priv)
{
static const struct rsnd_regmap_field_conf conf_adg[] = {
RSND_GEN_S_REG(BRRA, 0x00),
RSND_GEN_S_REG(BRRB, 0x04),
RSND_GEN_S_REG(BRGCKR, 0x08),
RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10),
};
static const struct rsnd_regmap_field_conf conf_ssi[] = {
RSND_GEN_M_REG(SSICR, 0x00, 0x40),
RSND_GEN_M_REG(SSISR, 0x04, 0x40),
RSND_GEN_M_REG(SSITDR, 0x08, 0x40),
RSND_GEN_M_REG(SSIRDR, 0x0c, 0x40),
RSND_GEN_M_REG(SSIWSR, 0x20, 0x40),
};
int ret_adg;
int ret_ssi;
ret_adg = rsnd_gen_regmap_init(priv, 9, RSND_GEN1_ADG, "adg", conf_adg);
ret_ssi = rsnd_gen_regmap_init(priv, 9, RSND_GEN1_SSI, "ssi", conf_ssi);
if (ret_adg < 0 ||
ret_ssi < 0)
return ret_adg | ret_ssi;
return 0;
}
/*
* Gen
*/
int rsnd_gen_probe(struct rsnd_priv *priv)
{
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_gen *gen;
int ret;
gen = devm_kzalloc(dev, sizeof(*gen), GFP_KERNEL);
if (!gen)
return -ENOMEM;
priv->gen = gen;
ret = -ENODEV;
if (rsnd_is_gen1(priv))
ret = rsnd_gen1_probe(priv);
else if (rsnd_is_gen2(priv) ||
rsnd_is_gen3(priv))
ret = rsnd_gen2_probe(priv);
else if (rsnd_is_gen4(priv))
ret = rsnd_gen4_probe(priv);
if (ret < 0)
dev_err(dev, "unknown generation R-Car sound device\n");
return ret;
}
| linux-master | sound/soc/sh/rcar/gen.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car DVC support
//
// Copyright (C) 2014 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
/*
* Playback Volume
* amixer set "DVC Out" 100%
*
* Capture Volume
* amixer set "DVC In" 100%
*
* Playback Mute
* amixer set "DVC Out Mute" on
*
* Capture Mute
* amixer set "DVC In Mute" on
*
* Volume Ramp
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
#include "rsnd.h"
#define RSND_DVC_NAME_SIZE 16
#define DVC_NAME "dvc"
struct rsnd_dvc {
struct rsnd_mod mod;
struct rsnd_kctrl_cfg_m volume;
struct rsnd_kctrl_cfg_m mute;
struct rsnd_kctrl_cfg_s ren; /* Ramp Enable */
struct rsnd_kctrl_cfg_s rup; /* Ramp Rate Up */
struct rsnd_kctrl_cfg_s rdown; /* Ramp Rate Down */
};
#define rsnd_dvc_get(priv, id) ((struct rsnd_dvc *)(priv->dvc) + id)
#define rsnd_dvc_nr(priv) ((priv)->dvc_nr)
#define rsnd_mod_to_dvc(_mod) \
container_of((_mod), struct rsnd_dvc, mod)
#define for_each_rsnd_dvc(pos, priv, i) \
for ((i) = 0; \
((i) < rsnd_dvc_nr(priv)) && \
((pos) = (struct rsnd_dvc *)(priv)->dvc + i); \
i++)
static void rsnd_dvc_activation(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, DVC_SWRSR, 0);
rsnd_mod_write(mod, DVC_SWRSR, 1);
}
static void rsnd_dvc_halt(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, DVC_DVUIR, 1);
rsnd_mod_write(mod, DVC_SWRSR, 0);
}
#define rsnd_dvc_get_vrpdr(dvc) (rsnd_kctrl_vals(dvc->rup) << 8 | \
rsnd_kctrl_vals(dvc->rdown))
#define rsnd_dvc_get_vrdbr(dvc) (0x3ff - (rsnd_kctrl_valm(dvc->volume, 0) >> 13))
static void rsnd_dvc_volume_parameter(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_dvc *dvc = rsnd_mod_to_dvc(mod);
u32 val[RSND_MAX_CHANNELS];
int i;
/* Enable Ramp */
if (rsnd_kctrl_vals(dvc->ren))
for (i = 0; i < RSND_MAX_CHANNELS; i++)
val[i] = rsnd_kctrl_max(dvc->volume);
else
for (i = 0; i < RSND_MAX_CHANNELS; i++)
val[i] = rsnd_kctrl_valm(dvc->volume, i);
/* Enable Digital Volume */
for (i = 0; i < RSND_MAX_CHANNELS; i++)
rsnd_mod_write(mod, DVC_VOLxR(i), val[i]);
}
static void rsnd_dvc_volume_init(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_dvc *dvc = rsnd_mod_to_dvc(mod);
u32 adinr = 0;
u32 dvucr = 0;
u32 vrctr = 0;
u32 vrpdr = 0;
u32 vrdbr = 0;
adinr = rsnd_get_adinr_bit(mod, io) |
rsnd_runtime_channel_after_ctu(io);
/* Enable Digital Volume, Zero Cross Mute Mode */
dvucr |= 0x101;
/* Enable Ramp */
if (rsnd_kctrl_vals(dvc->ren)) {
dvucr |= 0x10;
/*
* FIXME !!
* use scale-downed Digital Volume
* as Volume Ramp
* 7F FFFF -> 3FF
*/
vrctr = 0xff;
vrpdr = rsnd_dvc_get_vrpdr(dvc);
vrdbr = rsnd_dvc_get_vrdbr(dvc);
}
/* Initialize operation */
rsnd_mod_write(mod, DVC_DVUIR, 1);
/* General Information */
rsnd_mod_write(mod, DVC_ADINR, adinr);
rsnd_mod_write(mod, DVC_DVUCR, dvucr);
/* Volume Ramp Parameter */
rsnd_mod_write(mod, DVC_VRCTR, vrctr);
rsnd_mod_write(mod, DVC_VRPDR, vrpdr);
rsnd_mod_write(mod, DVC_VRDBR, vrdbr);
/* Digital Volume Function Parameter */
rsnd_dvc_volume_parameter(io, mod);
/* cancel operation */
rsnd_mod_write(mod, DVC_DVUIR, 0);
}
static void rsnd_dvc_volume_update(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_dvc *dvc = rsnd_mod_to_dvc(mod);
u32 zcmcr = 0;
u32 vrpdr = 0;
u32 vrdbr = 0;
int i;
for (i = 0; i < rsnd_kctrl_size(dvc->mute); i++)
zcmcr |= (!!rsnd_kctrl_valm(dvc->mute, i)) << i;
if (rsnd_kctrl_vals(dvc->ren)) {
vrpdr = rsnd_dvc_get_vrpdr(dvc);
vrdbr = rsnd_dvc_get_vrdbr(dvc);
}
/* Disable DVC Register access */
rsnd_mod_write(mod, DVC_DVUER, 0);
/* Zero Cross Mute Function */
rsnd_mod_write(mod, DVC_ZCMCR, zcmcr);
/* Volume Ramp Function */
rsnd_mod_write(mod, DVC_VRPDR, vrpdr);
rsnd_mod_write(mod, DVC_VRDBR, vrdbr);
/* add DVC_VRWTR here */
/* Digital Volume Function Parameter */
rsnd_dvc_volume_parameter(io, mod);
/* Enable DVC Register access */
rsnd_mod_write(mod, DVC_DVUER, 1);
}
static int rsnd_dvc_probe_(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
return rsnd_cmd_attach(io, rsnd_mod_id(mod));
}
static int rsnd_dvc_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
int ret;
ret = rsnd_mod_power_on(mod);
if (ret < 0)
return ret;
rsnd_dvc_activation(mod);
rsnd_dvc_volume_init(io, mod);
rsnd_dvc_volume_update(io, mod);
return 0;
}
static int rsnd_dvc_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_dvc_halt(mod);
rsnd_mod_power_off(mod);
return 0;
}
static int rsnd_dvc_pcm_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd)
{
struct rsnd_dvc *dvc = rsnd_mod_to_dvc(mod);
struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
int is_play = rsnd_io_is_play(io);
int channels = rsnd_rdai_channels_get(rdai);
int ret;
/* Volume */
ret = rsnd_kctrl_new_m(mod, io, rtd,
is_play ?
"DVC Out Playback Volume" : "DVC In Capture Volume",
rsnd_kctrl_accept_anytime,
rsnd_dvc_volume_update,
&dvc->volume, channels,
0x00800000 - 1);
if (ret < 0)
return ret;
/* Mute */
ret = rsnd_kctrl_new_m(mod, io, rtd,
is_play ?
"DVC Out Mute Switch" : "DVC In Mute Switch",
rsnd_kctrl_accept_anytime,
rsnd_dvc_volume_update,
&dvc->mute, channels,
1);
if (ret < 0)
return ret;
/* Ramp */
ret = rsnd_kctrl_new_s(mod, io, rtd,
is_play ?
"DVC Out Ramp Switch" : "DVC In Ramp Switch",
rsnd_kctrl_accept_anytime,
rsnd_dvc_volume_update,
&dvc->ren, 1);
if (ret < 0)
return ret;
ret = rsnd_kctrl_new_e(mod, io, rtd,
is_play ?
"DVC Out Ramp Up Rate" : "DVC In Ramp Up Rate",
rsnd_kctrl_accept_anytime,
rsnd_dvc_volume_update,
&dvc->rup,
volume_ramp_rate,
VOLUME_RAMP_MAX_DVC);
if (ret < 0)
return ret;
ret = rsnd_kctrl_new_e(mod, io, rtd,
is_play ?
"DVC Out Ramp Down Rate" : "DVC In Ramp Down Rate",
rsnd_kctrl_accept_anytime,
rsnd_dvc_volume_update,
&dvc->rdown,
volume_ramp_rate,
VOLUME_RAMP_MAX_DVC);
if (ret < 0)
return ret;
return 0;
}
static struct dma_chan *rsnd_dvc_dma_req(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
return rsnd_dma_request_channel(rsnd_dvc_of_node(priv),
DVC_NAME, mod, "tx");
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_dvc_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
0xe00 + rsnd_mod_id(mod) * 0x100, 0x60);
}
#define DEBUG_INFO .debug_info = rsnd_dvc_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_dvc_ops = {
.name = DVC_NAME,
.dma_req = rsnd_dvc_dma_req,
.probe = rsnd_dvc_probe_,
.init = rsnd_dvc_init,
.quit = rsnd_dvc_quit,
.pcm_new = rsnd_dvc_pcm_new,
.get_status = rsnd_mod_get_status,
DEBUG_INFO
};
struct rsnd_mod *rsnd_dvc_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_dvc_nr(priv)))
id = 0;
return rsnd_mod_get(rsnd_dvc_get(priv, id));
}
int rsnd_dvc_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_dvc *dvc;
struct clk *clk;
char name[RSND_DVC_NAME_SIZE];
int i, nr, ret;
/* This driver doesn't support Gen1 at this point */
if (rsnd_is_gen1(priv))
return 0;
node = rsnd_dvc_of_node(priv);
if (!node)
return 0; /* not used is not error */
nr = of_get_child_count(node);
if (!nr) {
ret = -EINVAL;
goto rsnd_dvc_probe_done;
}
dvc = devm_kcalloc(dev, nr, sizeof(*dvc), GFP_KERNEL);
if (!dvc) {
ret = -ENOMEM;
goto rsnd_dvc_probe_done;
}
priv->dvc_nr = nr;
priv->dvc = dvc;
i = 0;
ret = 0;
for_each_child_of_node(node, np) {
dvc = rsnd_dvc_get(priv, i);
snprintf(name, RSND_DVC_NAME_SIZE, "%s.%d",
DVC_NAME, i);
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_dvc_probe_done;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(dvc), &rsnd_dvc_ops,
clk, RSND_MOD_DVC, i);
if (ret) {
of_node_put(np);
goto rsnd_dvc_probe_done;
}
i++;
}
rsnd_dvc_probe_done:
of_node_put(node);
return ret;
}
void rsnd_dvc_remove(struct rsnd_priv *priv)
{
struct rsnd_dvc *dvc;
int i;
for_each_rsnd_dvc(dvc, priv, i) {
rsnd_mod_quit(rsnd_mod_get(dvc));
}
}
| linux-master | sound/soc/sh/rcar/dvc.c |
// SPDX-License-Identifier: GPL-2.0
//
// Renesas R-Car SRC support
//
// Copyright (C) 2013 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
/*
* You can use Synchronous Sampling Rate Convert (if no DVC)
*
* amixer set "SRC Out Rate" on
* aplay xxx.wav &
* amixer set "SRC Out Rate" 96000 // convert rate to 96000Hz
* amixer set "SRC Out Rate" 22050 // convert rate to 22050Hz
*/
/*
* you can enable below define if you don't need
* SSI interrupt status debug message when debugging
* see rsnd_print_irq_status()
*
* #define RSND_DEBUG_NO_IRQ_STATUS 1
*/
#include "rsnd.h"
#define SRC_NAME "src"
/* SCU_SYSTEM_STATUS0/1 */
#define OUF_SRC(id) ((1 << (id + 16)) | (1 << id))
struct rsnd_src {
struct rsnd_mod mod;
struct rsnd_mod *dma;
struct rsnd_kctrl_cfg_s sen; /* sync convert enable */
struct rsnd_kctrl_cfg_s sync; /* sync convert */
int irq;
};
#define RSND_SRC_NAME_SIZE 16
#define rsnd_src_get(priv, id) ((struct rsnd_src *)(priv->src) + id)
#define rsnd_src_nr(priv) ((priv)->src_nr)
#define rsnd_src_sync_is_enabled(mod) (rsnd_mod_to_src(mod)->sen.val)
#define rsnd_mod_to_src(_mod) \
container_of((_mod), struct rsnd_src, mod)
#define for_each_rsnd_src(pos, priv, i) \
for ((i) = 0; \
((i) < rsnd_src_nr(priv)) && \
((pos) = (struct rsnd_src *)(priv)->src + i); \
i++)
/*
* image of SRC (Sampling Rate Converter)
*
* 96kHz <-> +-----+ 48kHz +-----+ 48kHz +-------+
* 48kHz <-> | SRC | <------> | SSI | <-----> | codec |
* 44.1kHz <-> +-----+ +-----+ +-------+
* ...
*
*/
static void rsnd_src_activation(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, SRC_SWRSR, 0);
rsnd_mod_write(mod, SRC_SWRSR, 1);
}
static void rsnd_src_halt(struct rsnd_mod *mod)
{
rsnd_mod_write(mod, SRC_SRCIR, 1);
rsnd_mod_write(mod, SRC_SWRSR, 0);
}
static struct dma_chan *rsnd_src_dma_req(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
int is_play = rsnd_io_is_play(io);
return rsnd_dma_request_channel(rsnd_src_of_node(priv),
SRC_NAME, mod,
is_play ? "rx" : "tx");
}
static u32 rsnd_src_convert_rate(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
struct rsnd_src *src = rsnd_mod_to_src(mod);
u32 convert_rate;
if (!runtime)
return 0;
if (!rsnd_src_sync_is_enabled(mod))
return rsnd_io_converted_rate(io);
convert_rate = src->sync.val;
if (!convert_rate)
convert_rate = rsnd_io_converted_rate(io);
if (!convert_rate)
convert_rate = runtime->rate;
return convert_rate;
}
unsigned int rsnd_src_get_rate(struct rsnd_priv *priv,
struct rsnd_dai_stream *io,
int is_in)
{
struct rsnd_mod *src_mod = rsnd_io_to_mod_src(io);
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
unsigned int rate = 0;
int is_play = rsnd_io_is_play(io);
/*
* Playback
* runtime_rate -> [SRC] -> convert_rate
*
* Capture
* convert_rate -> [SRC] -> runtime_rate
*/
if (is_play == is_in)
return runtime->rate;
/*
* return convert rate if SRC is used,
* otherwise, return runtime->rate as usual
*/
if (src_mod)
rate = rsnd_src_convert_rate(io, src_mod);
if (!rate)
rate = runtime->rate;
return rate;
}
static const u32 bsdsr_table_pattern1[] = {
0x01800000, /* 6 - 1/6 */
0x01000000, /* 6 - 1/4 */
0x00c00000, /* 6 - 1/3 */
0x00800000, /* 6 - 1/2 */
0x00600000, /* 6 - 2/3 */
0x00400000, /* 6 - 1 */
};
static const u32 bsdsr_table_pattern2[] = {
0x02400000, /* 6 - 1/6 */
0x01800000, /* 6 - 1/4 */
0x01200000, /* 6 - 1/3 */
0x00c00000, /* 6 - 1/2 */
0x00900000, /* 6 - 2/3 */
0x00600000, /* 6 - 1 */
};
static const u32 bsisr_table[] = {
0x00100060, /* 6 - 1/6 */
0x00100040, /* 6 - 1/4 */
0x00100030, /* 6 - 1/3 */
0x00100020, /* 6 - 1/2 */
0x00100020, /* 6 - 2/3 */
0x00100020, /* 6 - 1 */
};
static const u32 chan288888[] = {
0x00000006, /* 1 to 2 */
0x000001fe, /* 1 to 8 */
0x000001fe, /* 1 to 8 */
0x000001fe, /* 1 to 8 */
0x000001fe, /* 1 to 8 */
0x000001fe, /* 1 to 8 */
};
static const u32 chan244888[] = {
0x00000006, /* 1 to 2 */
0x0000001e, /* 1 to 4 */
0x0000001e, /* 1 to 4 */
0x000001fe, /* 1 to 8 */
0x000001fe, /* 1 to 8 */
0x000001fe, /* 1 to 8 */
};
static const u32 chan222222[] = {
0x00000006, /* 1 to 2 */
0x00000006, /* 1 to 2 */
0x00000006, /* 1 to 2 */
0x00000006, /* 1 to 2 */
0x00000006, /* 1 to 2 */
0x00000006, /* 1 to 2 */
};
static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
int is_play = rsnd_io_is_play(io);
int use_src = 0;
u32 fin, fout;
u32 ifscr, fsrate, adinr;
u32 cr, route;
u32 i_busif, o_busif, tmp;
const u32 *bsdsr_table;
const u32 *chptn;
uint ratio;
int chan;
int idx;
if (!runtime)
return;
fin = rsnd_src_get_in_rate(priv, io);
fout = rsnd_src_get_out_rate(priv, io);
chan = rsnd_runtime_channel_original(io);
/* 6 - 1/6 are very enough ratio for SRC_BSDSR */
if (fin == fout)
ratio = 0;
else if (fin > fout)
ratio = 100 * fin / fout;
else
ratio = 100 * fout / fin;
if (ratio > 600) {
dev_err(dev, "FSO/FSI ratio error\n");
return;
}
use_src = (fin != fout) | rsnd_src_sync_is_enabled(mod);
/*
* SRC_ADINR
*/
adinr = rsnd_get_adinr_bit(mod, io) | chan;
/*
* SRC_IFSCR / SRC_IFSVR
*/
ifscr = 0;
fsrate = 0;
if (use_src) {
u64 n;
ifscr = 1;
n = (u64)0x0400000 * fin;
do_div(n, fout);
fsrate = n;
}
/*
* SRC_SRCCR / SRC_ROUTE_MODE0
*/
cr = 0x00011110;
route = 0x0;
if (use_src) {
route = 0x1;
if (rsnd_src_sync_is_enabled(mod)) {
cr |= 0x1;
route |= rsnd_io_is_play(io) ?
(0x1 << 24) : (0x1 << 25);
}
}
/*
* SRC_BSDSR / SRC_BSISR
*
* see
* Combination of Register Setting Related to
* FSO/FSI Ratio and Channel, Latency
*/
switch (rsnd_mod_id(mod)) {
case 0:
chptn = chan288888;
bsdsr_table = bsdsr_table_pattern1;
break;
case 1:
case 3:
case 4:
chptn = chan244888;
bsdsr_table = bsdsr_table_pattern1;
break;
case 2:
case 9:
chptn = chan222222;
bsdsr_table = bsdsr_table_pattern1;
break;
case 5:
case 6:
case 7:
case 8:
chptn = chan222222;
bsdsr_table = bsdsr_table_pattern2;
break;
default:
goto convert_rate_err;
}
/*
* E3 need to overwrite
*/
if (rsnd_is_e3(priv))
switch (rsnd_mod_id(mod)) {
case 0:
case 4:
chptn = chan222222;
}
for (idx = 0; idx < ARRAY_SIZE(chan222222); idx++)
if (chptn[idx] & (1 << chan))
break;
if (chan > 8 ||
idx >= ARRAY_SIZE(chan222222))
goto convert_rate_err;
/* BUSIF_MODE */
tmp = rsnd_get_busif_shift(io, mod);
i_busif = ( is_play ? tmp : 0) | 1;
o_busif = (!is_play ? tmp : 0) | 1;
rsnd_mod_write(mod, SRC_ROUTE_MODE0, route);
rsnd_mod_write(mod, SRC_SRCIR, 1); /* initialize */
rsnd_mod_write(mod, SRC_ADINR, adinr);
rsnd_mod_write(mod, SRC_IFSCR, ifscr);
rsnd_mod_write(mod, SRC_IFSVR, fsrate);
rsnd_mod_write(mod, SRC_SRCCR, cr);
rsnd_mod_write(mod, SRC_BSDSR, bsdsr_table[idx]);
rsnd_mod_write(mod, SRC_BSISR, bsisr_table[idx]);
rsnd_mod_write(mod, SRC_SRCIR, 0); /* cancel initialize */
rsnd_mod_write(mod, SRC_I_BUSIF_MODE, i_busif);
rsnd_mod_write(mod, SRC_O_BUSIF_MODE, o_busif);
rsnd_mod_write(mod, SRC_BUSIF_DALIGN, rsnd_get_dalign(mod, io));
rsnd_adg_set_src_timesel_gen2(mod, io, fin, fout);
return;
convert_rate_err:
dev_err(dev, "unknown BSDSR/BSDIR settings\n");
}
static int rsnd_src_irq(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv,
int enable)
{
struct rsnd_src *src = rsnd_mod_to_src(mod);
u32 sys_int_val, int_val, sys_int_mask;
int irq = src->irq;
int id = rsnd_mod_id(mod);
sys_int_val =
sys_int_mask = OUF_SRC(id);
int_val = 0x3300;
/*
* IRQ is not supported on non-DT
* see
* rsnd_src_probe_()
*/
if ((irq <= 0) || !enable) {
sys_int_val = 0;
int_val = 0;
}
/*
* WORKAROUND
*
* ignore over flow error when rsnd_src_sync_is_enabled()
*/
if (rsnd_src_sync_is_enabled(mod))
sys_int_val = sys_int_val & 0xffff;
rsnd_mod_write(mod, SRC_INT_ENABLE0, int_val);
rsnd_mod_bset(mod, SCU_SYS_INT_EN0, sys_int_mask, sys_int_val);
rsnd_mod_bset(mod, SCU_SYS_INT_EN1, sys_int_mask, sys_int_val);
return 0;
}
static void rsnd_src_status_clear(struct rsnd_mod *mod)
{
u32 val = OUF_SRC(rsnd_mod_id(mod));
rsnd_mod_write(mod, SCU_SYS_STATUS0, val);
rsnd_mod_write(mod, SCU_SYS_STATUS1, val);
}
static bool rsnd_src_error_occurred(struct rsnd_mod *mod)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
struct device *dev = rsnd_priv_to_dev(priv);
u32 val0, val1;
u32 status0, status1;
bool ret = false;
val0 = val1 = OUF_SRC(rsnd_mod_id(mod));
/*
* WORKAROUND
*
* ignore over flow error when rsnd_src_sync_is_enabled()
*/
if (rsnd_src_sync_is_enabled(mod))
val0 = val0 & 0xffff;
status0 = rsnd_mod_read(mod, SCU_SYS_STATUS0);
status1 = rsnd_mod_read(mod, SCU_SYS_STATUS1);
if ((status0 & val0) || (status1 & val1)) {
rsnd_print_irq_status(dev, "%s err status : 0x%08x, 0x%08x\n",
rsnd_mod_name(mod), status0, status1);
ret = true;
}
return ret;
}
static int rsnd_src_start(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
u32 val;
/*
* WORKAROUND
*
* Enable SRC output if you want to use sync convert together with DVC
*/
val = (rsnd_io_to_mod_dvc(io) && !rsnd_src_sync_is_enabled(mod)) ?
0x01 : 0x11;
rsnd_mod_write(mod, SRC_CTRL, val);
return 0;
}
static int rsnd_src_stop(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
rsnd_mod_write(mod, SRC_CTRL, 0);
return 0;
}
static int rsnd_src_init(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_src *src = rsnd_mod_to_src(mod);
int ret;
/* reset sync convert_rate */
src->sync.val = 0;
ret = rsnd_mod_power_on(mod);
if (ret < 0)
return ret;
rsnd_src_activation(mod);
rsnd_src_set_convert_rate(io, mod);
rsnd_src_status_clear(mod);
return 0;
}
static int rsnd_src_quit(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_src *src = rsnd_mod_to_src(mod);
rsnd_src_halt(mod);
rsnd_mod_power_off(mod);
/* reset sync convert_rate */
src->sync.val = 0;
return 0;
}
static void __rsnd_src_interrupt(struct rsnd_mod *mod,
struct rsnd_dai_stream *io)
{
struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
bool stop = false;
spin_lock(&priv->lock);
/* ignore all cases if not working */
if (!rsnd_io_is_working(io))
goto rsnd_src_interrupt_out;
if (rsnd_src_error_occurred(mod))
stop = true;
rsnd_src_status_clear(mod);
rsnd_src_interrupt_out:
spin_unlock(&priv->lock);
if (stop)
snd_pcm_stop_xrun(io->substream);
}
static irqreturn_t rsnd_src_interrupt(int irq, void *data)
{
struct rsnd_mod *mod = data;
rsnd_mod_interrupt(mod, __rsnd_src_interrupt);
return IRQ_HANDLED;
}
static int rsnd_src_probe_(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct rsnd_priv *priv)
{
struct rsnd_src *src = rsnd_mod_to_src(mod);
struct device *dev = rsnd_priv_to_dev(priv);
int irq = src->irq;
int ret;
if (irq > 0) {
/*
* IRQ is not supported on non-DT
* see
* rsnd_src_irq()
*/
ret = devm_request_irq(dev, irq,
rsnd_src_interrupt,
IRQF_SHARED,
dev_name(dev), mod);
if (ret)
return ret;
}
ret = rsnd_dma_attach(io, mod, &src->dma);
return ret;
}
static int rsnd_src_pcm_new(struct rsnd_mod *mod,
struct rsnd_dai_stream *io,
struct snd_soc_pcm_runtime *rtd)
{
struct rsnd_src *src = rsnd_mod_to_src(mod);
int ret;
/*
* enable SRC sync convert if possible
*/
/*
* It can't use SRC Synchronous convert
* when Capture if it uses CMD
*/
if (rsnd_io_to_mod_cmd(io) && !rsnd_io_is_play(io))
return 0;
/*
* enable sync convert
*/
ret = rsnd_kctrl_new_s(mod, io, rtd,
rsnd_io_is_play(io) ?
"SRC Out Rate Switch" :
"SRC In Rate Switch",
rsnd_kctrl_accept_anytime,
rsnd_src_set_convert_rate,
&src->sen, 1);
if (ret < 0)
return ret;
ret = rsnd_kctrl_new_s(mod, io, rtd,
rsnd_io_is_play(io) ?
"SRC Out Rate" :
"SRC In Rate",
rsnd_kctrl_accept_runtime,
rsnd_src_set_convert_rate,
&src->sync, 192000);
return ret;
}
#ifdef CONFIG_DEBUG_FS
static void rsnd_src_debug_info(struct seq_file *m,
struct rsnd_dai_stream *io,
struct rsnd_mod *mod)
{
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
rsnd_mod_id(mod) * 0x20, 0x20);
seq_puts(m, "\n");
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
0x1c0, 0x20);
seq_puts(m, "\n");
rsnd_debugfs_mod_reg_show(m, mod, RSND_GEN2_SCU,
0x200 + rsnd_mod_id(mod) * 0x40, 0x40);
}
#define DEBUG_INFO .debug_info = rsnd_src_debug_info
#else
#define DEBUG_INFO
#endif
static struct rsnd_mod_ops rsnd_src_ops = {
.name = SRC_NAME,
.dma_req = rsnd_src_dma_req,
.probe = rsnd_src_probe_,
.init = rsnd_src_init,
.quit = rsnd_src_quit,
.start = rsnd_src_start,
.stop = rsnd_src_stop,
.irq = rsnd_src_irq,
.pcm_new = rsnd_src_pcm_new,
.get_status = rsnd_mod_get_status,
DEBUG_INFO
};
struct rsnd_mod *rsnd_src_mod_get(struct rsnd_priv *priv, int id)
{
if (WARN_ON(id < 0 || id >= rsnd_src_nr(priv)))
id = 0;
return rsnd_mod_get(rsnd_src_get(priv, id));
}
int rsnd_src_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_src *src;
struct clk *clk;
char name[RSND_SRC_NAME_SIZE];
int i, nr, ret;
/* This driver doesn't support Gen1 at this point */
if (rsnd_is_gen1(priv))
return 0;
node = rsnd_src_of_node(priv);
if (!node)
return 0; /* not used is not error */
nr = rsnd_node_count(priv, node, SRC_NAME);
if (!nr) {
ret = -EINVAL;
goto rsnd_src_probe_done;
}
src = devm_kcalloc(dev, nr, sizeof(*src), GFP_KERNEL);
if (!src) {
ret = -ENOMEM;
goto rsnd_src_probe_done;
}
priv->src_nr = nr;
priv->src = src;
i = 0;
for_each_child_of_node(node, np) {
if (!of_device_is_available(np))
goto skip;
i = rsnd_node_fixed_index(dev, np, SRC_NAME, i);
if (i < 0) {
ret = -EINVAL;
of_node_put(np);
goto rsnd_src_probe_done;
}
src = rsnd_src_get(priv, i);
snprintf(name, RSND_SRC_NAME_SIZE, "%s.%d",
SRC_NAME, i);
src->irq = irq_of_parse_and_map(np, 0);
if (!src->irq) {
ret = -EINVAL;
of_node_put(np);
goto rsnd_src_probe_done;
}
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_src_probe_done;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(src),
&rsnd_src_ops, clk, RSND_MOD_SRC, i);
if (ret) {
of_node_put(np);
goto rsnd_src_probe_done;
}
skip:
i++;
}
ret = 0;
rsnd_src_probe_done:
of_node_put(node);
return ret;
}
void rsnd_src_remove(struct rsnd_priv *priv)
{
struct rsnd_src *src;
int i;
for_each_rsnd_src(src, priv, i) {
rsnd_mod_quit(rsnd_mod_get(src));
}
}
| linux-master | sound/soc/sh/rcar/src.c |
/*
* ALSA SoC Synopsys PIO PCM for I2S driver
*
* sound/soc/dwc/designware_pcm.c
*
* Copyright (C) 2016 Synopsys
* Jose Abreu <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/io.h>
#include <linux/rcupdate.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "local.h"
#define BUFFER_BYTES_MAX (3 * 2 * 8 * PERIOD_BYTES_MIN)
#define PERIOD_BYTES_MIN 4096
#define PERIODS_MIN 2
#define dw_pcm_tx_fn(sample_bits) \
static unsigned int dw_pcm_tx_##sample_bits(struct dw_i2s_dev *dev, \
struct snd_pcm_runtime *runtime, unsigned int tx_ptr, \
bool *period_elapsed) \
{ \
const u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
unsigned int period_pos = tx_ptr % runtime->period_size; \
int i; \
\
for (i = 0; i < dev->fifo_th; i++) { \
iowrite32(p[tx_ptr][0], dev->i2s_base + dev->l_reg); \
iowrite32(p[tx_ptr][1], dev->i2s_base + dev->r_reg); \
period_pos++; \
if (++tx_ptr >= runtime->buffer_size) \
tx_ptr = 0; \
} \
*period_elapsed = period_pos >= runtime->period_size; \
return tx_ptr; \
}
#define dw_pcm_rx_fn(sample_bits) \
static unsigned int dw_pcm_rx_##sample_bits(struct dw_i2s_dev *dev, \
struct snd_pcm_runtime *runtime, unsigned int rx_ptr, \
bool *period_elapsed) \
{ \
u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
unsigned int period_pos = rx_ptr % runtime->period_size; \
int i; \
\
for (i = 0; i < dev->fifo_th; i++) { \
p[rx_ptr][0] = ioread32(dev->i2s_base + dev->l_reg); \
p[rx_ptr][1] = ioread32(dev->i2s_base + dev->r_reg); \
period_pos++; \
if (++rx_ptr >= runtime->buffer_size) \
rx_ptr = 0; \
} \
*period_elapsed = period_pos >= runtime->period_size; \
return rx_ptr; \
}
dw_pcm_tx_fn(16);
dw_pcm_tx_fn(32);
dw_pcm_rx_fn(16);
dw_pcm_rx_fn(32);
#undef dw_pcm_tx_fn
#undef dw_pcm_rx_fn
static const struct snd_pcm_hardware dw_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BLOCK_TRANSFER,
.rates = SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000,
.rate_min = 32000,
.rate_max = 48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = BUFFER_BYTES_MAX,
.period_bytes_min = PERIOD_BYTES_MIN,
.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
.periods_min = PERIODS_MIN,
.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
.fifo_size = 16,
};
static void dw_pcm_transfer(struct dw_i2s_dev *dev, bool push)
{
struct snd_pcm_substream *substream;
bool active, period_elapsed;
rcu_read_lock();
if (push)
substream = rcu_dereference(dev->tx_substream);
else
substream = rcu_dereference(dev->rx_substream);
active = substream && snd_pcm_running(substream);
if (active) {
unsigned int ptr;
unsigned int new_ptr;
if (push) {
ptr = READ_ONCE(dev->tx_ptr);
new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
&period_elapsed);
cmpxchg(&dev->tx_ptr, ptr, new_ptr);
} else {
ptr = READ_ONCE(dev->rx_ptr);
new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
&period_elapsed);
cmpxchg(&dev->rx_ptr, ptr, new_ptr);
}
if (period_elapsed)
snd_pcm_period_elapsed(substream);
}
rcu_read_unlock();
}
void dw_pcm_push_tx(struct dw_i2s_dev *dev)
{
dw_pcm_transfer(dev, true);
}
void dw_pcm_pop_rx(struct dw_i2s_dev *dev)
{
dw_pcm_transfer(dev, false);
}
static int dw_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
snd_soc_set_runtime_hwparams(substream, &dw_pcm_hardware);
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
runtime->private_data = dev;
return 0;
}
static int dw_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
synchronize_rcu();
return 0;
}
static int dw_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct dw_i2s_dev *dev = runtime->private_data;
switch (params_channels(hw_params)) {
case 2:
break;
default:
dev_err(dev->dev, "invalid channels number\n");
return -EINVAL;
}
switch (params_format(hw_params)) {
case SNDRV_PCM_FORMAT_S16_LE:
dev->tx_fn = dw_pcm_tx_16;
dev->rx_fn = dw_pcm_rx_16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_S32_LE:
dev->tx_fn = dw_pcm_tx_32;
dev->rx_fn = dw_pcm_rx_32;
break;
default:
dev_err(dev->dev, "invalid format\n");
return -EINVAL;
}
return 0;
}
static int dw_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct dw_i2s_dev *dev = runtime->private_data;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
WRITE_ONCE(dev->tx_ptr, 0);
rcu_assign_pointer(dev->tx_substream, substream);
} else {
WRITE_ONCE(dev->rx_ptr, 0);
rcu_assign_pointer(dev->rx_substream, substream);
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
rcu_assign_pointer(dev->tx_substream, NULL);
else
rcu_assign_pointer(dev->rx_substream, NULL);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static snd_pcm_uframes_t dw_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct dw_i2s_dev *dev = runtime->private_data;
snd_pcm_uframes_t pos;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
pos = READ_ONCE(dev->tx_ptr);
else
pos = READ_ONCE(dev->rx_ptr);
return pos < runtime->buffer_size ? pos : 0;
}
static int dw_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
size_t size = dw_pcm_hardware.buffer_bytes_max;
snd_pcm_set_managed_buffer_all(rtd->pcm,
SNDRV_DMA_TYPE_CONTINUOUS,
NULL, size, size);
return 0;
}
static const struct snd_soc_component_driver dw_pcm_component = {
.open = dw_pcm_open,
.close = dw_pcm_close,
.hw_params = dw_pcm_hw_params,
.trigger = dw_pcm_trigger,
.pointer = dw_pcm_pointer,
.pcm_construct = dw_pcm_new,
};
int dw_pcm_register(struct platform_device *pdev)
{
return devm_snd_soc_register_component(&pdev->dev, &dw_pcm_component,
NULL, 0);
}
| linux-master | sound/soc/dwc/dwc-pcm.c |
/*
* ALSA SoC Synopsys I2S Audio Layer
*
* sound/soc/dwc/designware_i2s.c
*
* Copyright (C) 2010 ST Microelectronics
* Rajeev Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <sound/designware_i2s.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "local.h"
static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
{
writel(val, io_base + reg);
}
static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
{
return readl(io_base + reg);
}
static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
{
u32 i = 0;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < 4; i++)
i2s_write_reg(dev->i2s_base, TER(i), 0);
} else {
for (i = 0; i < 4; i++)
i2s_write_reg(dev->i2s_base, RER(i), 0);
}
}
static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
{
u32 i = 0;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < 4; i++)
i2s_read_reg(dev->i2s_base, TOR(i));
} else {
for (i = 0; i < 4; i++)
i2s_read_reg(dev->i2s_base, ROR(i));
}
}
static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
int chan_nr)
{
u32 i, irq;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
}
} else {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
}
}
}
static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
int chan_nr)
{
u32 i, irq;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
}
} else {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
}
}
}
static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
{
struct dw_i2s_dev *dev = dev_id;
bool irq_valid = false;
u32 isr[4];
int i;
for (i = 0; i < 4; i++)
isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
for (i = 0; i < 4; i++) {
/*
* Check if TX fifo is empty. If empty fill FIFO with samples
* NOTE: Only two channels supported
*/
if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
dw_pcm_push_tx(dev);
irq_valid = true;
}
/*
* Data available. Retrieve samples from FIFO
* NOTE: Only two channels supported
*/
if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
dw_pcm_pop_rx(dev);
irq_valid = true;
}
/* Error Handling: TX */
if (isr[i] & ISR_TXFO) {
dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);
irq_valid = true;
}
/* Error Handling: TX */
if (isr[i] & ISR_RXFO) {
dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);
irq_valid = true;
}
}
if (irq_valid)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream)
{
u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
/* Enable DMA handshake for stream */
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_reg |= I2S_DMAEN_TXBLOCK;
else
dma_reg |= I2S_DMAEN_RXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
}
static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream)
{
u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
/* Disable DMA handshake for stream */
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
dma_reg &= ~I2S_DMAEN_TXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1);
} else {
dma_reg &= ~I2S_DMAEN_RXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1);
}
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
}
static void i2s_start(struct dw_i2s_dev *dev,
struct snd_pcm_substream *substream)
{
struct i2s_clk_config_data *config = &dev->config;
u32 reg = IER_IEN;
if (dev->tdm_slots) {
reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT;
reg |= IER_INTF_TYPE;
reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT;
}
i2s_write_reg(dev->i2s_base, IER, reg);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_write_reg(dev->i2s_base, ITER, 1);
else
i2s_write_reg(dev->i2s_base, IRER, 1);
/* I2S needs to enable IRQ to make a handshake with DMAC on the JH7110 SoC */
if (dev->use_pio || dev->is_jh7110)
i2s_enable_irqs(dev, substream->stream, config->chan_nr);
else
i2s_enable_dma(dev, substream->stream);
i2s_write_reg(dev->i2s_base, CER, 1);
}
static void i2s_stop(struct dw_i2s_dev *dev,
struct snd_pcm_substream *substream)
{
i2s_clear_irqs(dev, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_write_reg(dev->i2s_base, ITER, 0);
else
i2s_write_reg(dev->i2s_base, IRER, 0);
if (dev->use_pio || dev->is_jh7110)
i2s_disable_irqs(dev, substream->stream, 8);
else
i2s_disable_dma(dev, substream->stream);
if (!dev->active) {
i2s_write_reg(dev->i2s_base, CER, 0);
i2s_write_reg(dev->i2s_base, IER, 0);
}
}
static int dw_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
if (dev->is_jh7110) {
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai_link *dai_link = rtd->dai_link;
dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC;
}
return 0;
}
static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
{
u32 ch_reg;
struct i2s_clk_config_data *config = &dev->config;
i2s_disable_channels(dev, stream);
for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
i2s_write_reg(dev->i2s_base, TCR(ch_reg),
dev->xfer_resolution);
i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
dev->fifo_th - 1);
i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
dev->tdm_mask << TER_TXSLOT_SHIFT);
} else {
i2s_write_reg(dev->i2s_base, RCR(ch_reg),
dev->xfer_resolution);
i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
dev->fifo_th - 1);
i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |
dev->tdm_mask << RER_RXSLOT_SHIFT);
}
}
}
static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
struct i2s_clk_config_data *config = &dev->config;
int ret;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
config->data_width = 16;
dev->ccr = 0x00;
dev->xfer_resolution = 0x02;
break;
case SNDRV_PCM_FORMAT_S24_LE:
config->data_width = 24;
dev->ccr = 0x08;
dev->xfer_resolution = 0x04;
break;
case SNDRV_PCM_FORMAT_S32_LE:
config->data_width = 32;
dev->ccr = 0x10;
dev->xfer_resolution = 0x05;
break;
default:
dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
return -EINVAL;
}
if (dev->tdm_slots)
config->data_width = 32;
config->chan_nr = params_channels(params);
switch (config->chan_nr) {
case EIGHT_CHANNEL_SUPPORT:
case SIX_CHANNEL_SUPPORT:
case FOUR_CHANNEL_SUPPORT:
case TWO_CHANNEL_SUPPORT:
break;
default:
dev_err(dev->dev, "channel not supported\n");
return -EINVAL;
}
dw_i2s_config(dev, substream->stream);
i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
config->sample_rate = params_rate(params);
if (dev->capability & DW_I2S_MASTER) {
if (dev->i2s_clk_cfg) {
ret = dev->i2s_clk_cfg(config);
if (ret < 0) {
dev_err(dev->dev, "runtime audio clk config fail\n");
return ret;
}
} else {
u32 bitclk = config->sample_rate *
config->data_width * 2;
ret = clk_set_rate(dev->clk, bitclk);
if (ret) {
dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
ret);
return ret;
}
}
}
return 0;
}
static int dw_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_write_reg(dev->i2s_base, TXFFR, 1);
else
i2s_write_reg(dev->i2s_base, RXFFR, 1);
return 0;
}
static int dw_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dev->active++;
i2s_start(dev, substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dev->active--;
i2s_stop(dev, substream);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
int ret = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
if (dev->capability & DW_I2S_SLAVE)
ret = 0;
else
ret = -EINVAL;
break;
case SND_SOC_DAIFMT_BP_FP:
if (dev->capability & DW_I2S_MASTER)
ret = 0;
else
ret = -EINVAL;
break;
case SND_SOC_DAIFMT_BC_FP:
case SND_SOC_DAIFMT_BP_FC:
ret = -EINVAL;
break;
default:
dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");
ret = -EINVAL;
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_DSP_A:
dev->frame_offset = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
dev->frame_offset = 0;
break;
default:
dev_err(dev->dev, "DAI format unsupported");
return -EINVAL;
}
return ret;
}
static int dw_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
if (slot_width != 32)
return -EINVAL;
if (slots < 0 || slots > 16)
return -EINVAL;
if (rx_mask != tx_mask)
return -EINVAL;
if (!rx_mask)
return -EINVAL;
dev->tdm_slots = slots;
dev->tdm_mask = rx_mask;
dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1);
dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1);
return 0;
}
static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
.probe = dw_i2s_dai_probe,
.startup = dw_i2s_startup,
.hw_params = dw_i2s_hw_params,
.prepare = dw_i2s_prepare,
.trigger = dw_i2s_trigger,
.set_fmt = dw_i2s_set_fmt,
.set_tdm_slot = dw_i2s_set_tdm_slot,
};
#ifdef CONFIG_PM
static int dw_i2s_runtime_suspend(struct device *dev)
{
struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
if (dw_dev->capability & DW_I2S_MASTER)
clk_disable(dw_dev->clk);
return 0;
}
static int dw_i2s_runtime_resume(struct device *dev)
{
struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
int ret;
if (dw_dev->capability & DW_I2S_MASTER) {
ret = clk_enable(dw_dev->clk);
if (ret)
return ret;
}
return 0;
}
static int dw_i2s_suspend(struct snd_soc_component *component)
{
struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
if (dev->capability & DW_I2S_MASTER)
clk_disable(dev->clk);
return 0;
}
static int dw_i2s_resume(struct snd_soc_component *component)
{
struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
struct snd_soc_dai *dai;
int stream, ret;
if (dev->capability & DW_I2S_MASTER) {
ret = clk_enable(dev->clk);
if (ret)
return ret;
}
for_each_component_dais(component, dai) {
for_each_pcm_streams(stream)
if (snd_soc_dai_stream_active(dai, stream))
dw_i2s_config(dev, stream);
}
return 0;
}
#else
#define dw_i2s_suspend NULL
#define dw_i2s_resume NULL
#endif
static const struct snd_soc_component_driver dw_i2s_component = {
.name = "dw-i2s",
.suspend = dw_i2s_suspend,
.resume = dw_i2s_resume,
.legacy_dai_naming = 1,
};
/*
* The following tables allow a direct lookup of various parameters
* defined in the I2S block's configuration in terms of sound system
* parameters. Each table is sized to the number of entries possible
* according to the number of configuration bits describing an I2S
* block parameter.
*/
/* Maximum bit resolution of a channel - not uniformly spaced */
static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
12, 16, 20, 24, 32, 0, 0, 0
};
/* Width of (DMA) bus */
static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
DMA_SLAVE_BUSWIDTH_1_BYTE,
DMA_SLAVE_BUSWIDTH_2_BYTES,
DMA_SLAVE_BUSWIDTH_4_BYTES,
DMA_SLAVE_BUSWIDTH_UNDEFINED
};
/* PCM format to support channel resolution */
static const u32 formats[COMP_MAX_WORDSIZE] = {
SNDRV_PCM_FMTBIT_S16_LE,
SNDRV_PCM_FMTBIT_S16_LE,
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0,
0,
0
};
static int dw_configure_dai(struct dw_i2s_dev *dev,
struct snd_soc_dai_driver *dw_i2s_dai,
unsigned int rates)
{
/*
* Read component parameter registers to extract
* the I2S block's configuration.
*/
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
u32 idx;
if (dev->capability & DWC_I2S_RECORD &&
dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
comp1 = comp1 & ~BIT(5);
if (dev->capability & DWC_I2S_PLAY &&
dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
comp1 = comp1 & ~BIT(6);
if (COMP1_TX_ENABLED(comp1)) {
dev_dbg(dev->dev, " designware: play supported\n");
idx = COMP1_TX_WORDSIZE_0(comp1);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
idx = 1;
dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->playback.channels_max =
1 << (COMP1_TX_CHANNELS(comp1) + 1);
dw_i2s_dai->playback.formats = formats[idx];
dw_i2s_dai->playback.rates = rates;
}
if (COMP1_RX_ENABLED(comp1)) {
dev_dbg(dev->dev, "designware: record supported\n");
idx = COMP2_RX_WORDSIZE_0(comp2);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
idx = 1;
dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->capture.channels_max =
1 << (COMP1_RX_CHANNELS(comp1) + 1);
dw_i2s_dai->capture.formats = formats[idx];
dw_i2s_dai->capture.rates = rates;
}
if (COMP1_MODE_EN(comp1)) {
dev_dbg(dev->dev, "designware: i2s master mode supported\n");
dev->capability |= DW_I2S_MASTER;
} else {
dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
dev->capability |= DW_I2S_SLAVE;
}
dev->fifo_th = fifo_depth / 2;
return 0;
}
static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
struct snd_soc_dai_driver *dw_i2s_dai,
struct resource *res,
const struct i2s_platform_data *pdata)
{
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
u32 idx = COMP1_APB_DATA_WIDTH(comp1);
int ret;
if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
return -EINVAL;
ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
if (ret < 0)
return ret;
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
idx = 1;
if (dev->is_jh7110) {
/* Use platform data and snd_dmaengine_dai_dma_data struct at the same time */
u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
u32 idx2;
if (COMP1_TX_ENABLED(comp1)) {
idx2 = COMP1_TX_WORDSIZE_0(comp1);
dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 *
(fifo_width[idx2]) >> 8;
dev->play_dma_data.dt.maxburst = 16;
}
if (COMP1_RX_ENABLED(comp1)) {
idx2 = COMP2_RX_WORDSIZE_0(comp2);
dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 *
(fifo_width[idx2] >> 8);
dev->capture_dma_data.dt.maxburst = 16;
}
} else {
/* Set DMA slaves info */
dev->play_dma_data.pd.data = pdata->play_dma_data;
dev->capture_dma_data.pd.data = pdata->capture_dma_data;
dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
dev->play_dma_data.pd.max_burst = 16;
dev->capture_dma_data.pd.max_burst = 16;
dev->play_dma_data.pd.addr_width = bus_widths[idx];
dev->capture_dma_data.pd.addr_width = bus_widths[idx];
dev->play_dma_data.pd.filter = pdata->filter;
dev->capture_dma_data.pd.filter = pdata->filter;
}
return 0;
}
static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
struct snd_soc_dai_driver *dw_i2s_dai,
struct resource *res)
{
u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
u32 idx2;
int ret;
ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
if (ret < 0)
return ret;
if (COMP1_TX_ENABLED(comp1)) {
idx2 = COMP1_TX_WORDSIZE_0(comp1);
dev->capability |= DWC_I2S_PLAY;
dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
dev->play_dma_data.dt.fifo_size = fifo_depth *
(fifo_width[idx2]) >> 8;
dev->play_dma_data.dt.maxburst = 16;
}
if (COMP1_RX_ENABLED(comp1)) {
idx2 = COMP2_RX_WORDSIZE_0(comp2);
dev->capability |= DWC_I2S_RECORD;
dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
dev->capture_dma_data.dt.fifo_size = fifo_depth *
(fifo_width[idx2] >> 8);
dev->capture_dma_data.dt.maxburst = 16;
}
return 0;
}
#ifdef CONFIG_OF
/* clocks initialization with master mode on JH7110 SoC */
static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev)
{
static struct clk_bulk_data clks[] = {
{ .id = "mclk" },
{ .id = "mclk_ext" },
{ .id = "mclk_inner" },
{ .id = "apb" },
{ .id = "i2sclk" },
};
struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);
int ret;
struct clk *pclk;
struct clk *bclk_mst;
struct clk *mclk;
struct clk *mclk_ext;
struct clk *mclk_inner;
if (IS_ERR(resets))
return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");
ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);
if (ret)
return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");
mclk = clks[0].clk;
mclk_ext = clks[1].clk;
mclk_inner = clks[2].clk;
pclk = clks[3].clk;
bclk_mst = clks[4].clk;
ret = clk_prepare_enable(pclk);
if (ret)
goto exit;
/* Use inner mclk first and avoid uninitialized gpio for external mclk */
ret = clk_set_parent(mclk, mclk_inner);
if (ret)
goto err_dis_pclk;
ret = clk_prepare_enable(bclk_mst);
if (ret)
goto err_dis_pclk;
/* deassert resets before set clock parent */
ret = reset_control_deassert(resets);
if (ret)
goto err_dis_all;
/* external clock (12.288MHz) for Audio */
ret = clk_set_parent(mclk, mclk_ext);
if (ret)
goto err_dis_all;
/* i2sclk will be got and enabled repeatedly later and should be disabled now. */
clk_disable_unprepare(bclk_mst);
clk_bulk_put(ARRAY_SIZE(clks), clks);
dev->is_jh7110 = true;
return 0;
err_dis_all:
clk_disable_unprepare(bclk_mst);
err_dis_pclk:
clk_disable_unprepare(pclk);
exit:
clk_bulk_put(ARRAY_SIZE(clks), clks);
return ret;
}
/* clocks initialization with slave mode on JH7110 SoC */
static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev)
{
static struct clk_bulk_data clks[] = {
{ .id = "mclk" },
{ .id = "mclk_ext" },
{ .id = "apb" },
{ .id = "bclk_ext" },
{ .id = "lrck_ext" },
{ .id = "bclk" },
{ .id = "lrck" },
{ .id = "mclk_inner" },
{ .id = "i2sclk" },
};
struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);
int ret;
struct clk *pclk;
struct clk *bclk_mst;
struct clk *bclk_ext;
struct clk *lrck_ext;
struct clk *bclk;
struct clk *lrck;
struct clk *mclk;
struct clk *mclk_ext;
struct clk *mclk_inner;
if (IS_ERR(resets))
return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");
ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);
if (ret)
return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");
mclk = clks[0].clk;
mclk_ext = clks[1].clk;
pclk = clks[2].clk;
bclk_ext = clks[3].clk;
lrck_ext = clks[4].clk;
bclk = clks[5].clk;
lrck = clks[6].clk;
mclk_inner = clks[7].clk;
bclk_mst = clks[8].clk;
ret = clk_prepare_enable(pclk);
if (ret)
goto exit;
ret = clk_set_parent(mclk, mclk_inner);
if (ret)
goto err_dis_pclk;
ret = clk_prepare_enable(bclk_mst);
if (ret)
goto err_dis_pclk;
ret = reset_control_deassert(resets);
if (ret)
goto err_dis_all;
/* The sources of BCLK and LRCK are the external codec. */
ret = clk_set_parent(bclk, bclk_ext);
if (ret)
goto err_dis_all;
ret = clk_set_parent(lrck, lrck_ext);
if (ret)
goto err_dis_all;
ret = clk_set_parent(mclk, mclk_ext);
if (ret)
goto err_dis_all;
/* The i2sclk will be got and enabled repeatedly later and should be disabled now. */
clk_disable_unprepare(bclk_mst);
clk_bulk_put(ARRAY_SIZE(clks), clks);
dev->is_jh7110 = true;
return 0;
err_dis_all:
clk_disable_unprepare(bclk_mst);
err_dis_pclk:
clk_disable_unprepare(pclk);
exit:
clk_bulk_put(ARRAY_SIZE(clks), clks);
return ret;
}
/* Special syscon initialization about RX channel with slave mode on JH7110 SoC */
static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev)
{
struct regmap *regmap;
unsigned int args[2];
regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node,
"starfive,syscon",
2, args);
if (IS_ERR(regmap))
return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n");
/* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */
regmap_update_bits(regmap, args[0], args[1], args[1]);
return jh7110_i2s_crg_slave_init(dev);
}
static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config)
{
struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config);
u32 bclk_rate = config->sample_rate * 64;
return clk_set_rate(dev->clk, bclk_rate);
}
#endif /* CONFIG_OF */
static int dw_i2s_probe(struct platform_device *pdev)
{
const struct i2s_platform_data *pdata = of_device_get_match_data(&pdev->dev);
struct dw_i2s_dev *dev;
struct resource *res;
int ret, irq;
struct snd_soc_dai_driver *dw_i2s_dai;
const char *clk_id;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
if (!dw_i2s_dai)
return -ENOMEM;
dw_i2s_dai->ops = &dw_i2s_dai_ops;
dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(dev->i2s_base))
return PTR_ERR(dev->i2s_base);
dev->dev = &pdev->dev;
dev->is_jh7110 = false;
if (pdata) {
if (pdata->i2s_pd_init) {
ret = pdata->i2s_pd_init(dev);
if (ret)
return ret;
}
}
if (!dev->is_jh7110) {
dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev);
if (IS_ERR(dev->reset))
return PTR_ERR(dev->reset);
ret = reset_control_deassert(dev->reset);
if (ret)
return ret;
}
irq = platform_get_irq_optional(pdev, 0);
if (irq >= 0) {
ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
pdev->name, dev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to request irq\n");
goto err_assert_reset;
}
}
dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
if (pdata) {
dev->capability = pdata->cap;
clk_id = NULL;
dev->quirks = pdata->quirks;
if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
}
ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
} else {
clk_id = "i2sclk";
ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
}
if (ret < 0)
goto err_assert_reset;
if (dev->capability & DW_I2S_MASTER) {
if (pdata) {
dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
if (!dev->i2s_clk_cfg) {
dev_err(&pdev->dev, "no clock configure method\n");
ret = -ENODEV;
goto err_assert_reset;
}
}
dev->clk = devm_clk_get(&pdev->dev, clk_id);
if (IS_ERR(dev->clk)) {
ret = PTR_ERR(dev->clk);
goto err_assert_reset;
}
ret = clk_prepare_enable(dev->clk);
if (ret < 0)
goto err_assert_reset;
}
dev_set_drvdata(&pdev->dev, dev);
ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
dw_i2s_dai, 1);
if (ret != 0) {
dev_err(&pdev->dev, "not able to register dai\n");
goto err_clk_disable;
}
if (!pdata || dev->is_jh7110) {
if (irq >= 0) {
ret = dw_pcm_register(pdev);
dev->use_pio = true;
dev->l_reg = LRBR_LTHR(0);
dev->r_reg = RRBR_RTHR(0);
} else {
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
0);
dev->use_pio = false;
}
if (ret) {
dev_err(&pdev->dev, "could not register pcm: %d\n",
ret);
goto err_clk_disable;
}
}
pm_runtime_enable(&pdev->dev);
return 0;
err_clk_disable:
if (dev->capability & DW_I2S_MASTER)
clk_disable_unprepare(dev->clk);
err_assert_reset:
reset_control_assert(dev->reset);
return ret;
}
static void dw_i2s_remove(struct platform_device *pdev)
{
struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
if (dev->capability & DW_I2S_MASTER)
clk_disable_unprepare(dev->clk);
reset_control_assert(dev->reset);
pm_runtime_disable(&pdev->dev);
}
#ifdef CONFIG_OF
static const struct i2s_platform_data jh7110_i2stx0_data = {
.cap = DWC_I2S_PLAY | DW_I2S_MASTER,
.channel = TWO_CHANNEL_SUPPORT,
.snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
.snd_rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000,
.i2s_clk_cfg = jh7110_i2stx0_clk_cfg,
.i2s_pd_init = jh7110_i2s_crg_master_init,
};
static const struct i2s_platform_data jh7110_i2stx1_data = {
.cap = DWC_I2S_PLAY | DW_I2S_SLAVE,
.channel = TWO_CHANNEL_SUPPORT,
.snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
.snd_rates = SNDRV_PCM_RATE_8000_192000,
.i2s_pd_init = jh7110_i2s_crg_slave_init,
};
static const struct i2s_platform_data jh7110_i2srx_data = {
.cap = DWC_I2S_RECORD | DW_I2S_SLAVE,
.channel = TWO_CHANNEL_SUPPORT,
.snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
.snd_rates = SNDRV_PCM_RATE_8000_192000,
.i2s_pd_init = jh7110_i2srx_crg_init,
};
static const struct of_device_id dw_i2s_of_match[] = {
{ .compatible = "snps,designware-i2s", },
{ .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, },
{ .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,},
{ .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,},
{},
};
MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
#endif
static const struct dev_pm_ops dwc_pm_ops = {
SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
};
static struct platform_driver dw_i2s_driver = {
.probe = dw_i2s_probe,
.remove_new = dw_i2s_remove,
.driver = {
.name = "designware-i2s",
.of_match_table = of_match_ptr(dw_i2s_of_match),
.pm = &dwc_pm_ops,
},
};
module_platform_driver(dw_i2s_driver);
MODULE_AUTHOR("Rajeev Kumar <[email protected]>");
MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:designware_i2s");
| linux-master | sound/soc/dwc/dwc-i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/meson-aiu.h>
#include "aiu.h"
#include "aiu-fifo.h"
#define AIU_I2S_MISC_958_SRC_SHIFT 3
static const char * const aiu_spdif_encode_sel_texts[] = {
"SPDIF", "I2S",
};
static SOC_ENUM_SINGLE_DECL(aiu_spdif_encode_sel_enum, AIU_I2S_MISC,
AIU_I2S_MISC_958_SRC_SHIFT,
aiu_spdif_encode_sel_texts);
static const struct snd_kcontrol_new aiu_spdif_encode_mux =
SOC_DAPM_ENUM("SPDIF Buffer Src", aiu_spdif_encode_sel_enum);
static const struct snd_soc_dapm_widget aiu_cpu_dapm_widgets[] = {
SND_SOC_DAPM_MUX("SPDIF SRC SEL", SND_SOC_NOPM, 0, 0,
&aiu_spdif_encode_mux),
};
static const struct snd_soc_dapm_route aiu_cpu_dapm_routes[] = {
{ "I2S Encoder Playback", NULL, "I2S FIFO Playback" },
{ "SPDIF SRC SEL", "SPDIF", "SPDIF FIFO Playback" },
{ "SPDIF SRC SEL", "I2S", "I2S FIFO Playback" },
{ "SPDIF Encoder Playback", NULL, "SPDIF SRC SEL" },
};
int aiu_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name,
unsigned int component_id)
{
struct snd_soc_dai *dai;
int id;
if (args->args_count != 2)
return -EINVAL;
if (args->args[0] != component_id)
return -EINVAL;
id = args->args[1];
if (id < 0 || id >= component->num_dai)
return -EINVAL;
for_each_component_dais(component, dai) {
if (id == 0)
break;
id--;
}
*dai_name = dai->driver->name;
return 0;
}
static int aiu_cpu_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
return aiu_of_xlate_dai_name(component, args, dai_name, AIU_CPU);
}
static int aiu_cpu_component_probe(struct snd_soc_component *component)
{
struct aiu *aiu = snd_soc_component_get_drvdata(component);
/* Required for the SPDIF Source control operation */
return clk_prepare_enable(aiu->i2s.clks[PCLK].clk);
}
static void aiu_cpu_component_remove(struct snd_soc_component *component)
{
struct aiu *aiu = snd_soc_component_get_drvdata(component);
clk_disable_unprepare(aiu->i2s.clks[PCLK].clk);
}
static const struct snd_soc_component_driver aiu_cpu_component = {
.name = "AIU CPU",
.dapm_widgets = aiu_cpu_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aiu_cpu_dapm_widgets),
.dapm_routes = aiu_cpu_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(aiu_cpu_dapm_routes),
.of_xlate_dai_name = aiu_cpu_of_xlate_dai_name,
.pointer = aiu_fifo_pointer,
.probe = aiu_cpu_component_probe,
.remove = aiu_cpu_component_remove,
#ifdef CONFIG_DEBUG_FS
.debugfs_prefix = "cpu",
#endif
};
static struct snd_soc_dai_driver aiu_cpu_dai_drv[] = {
[CPU_I2S_FIFO] = {
.name = "I2S FIFO",
.playback = {
.stream_name = "I2S FIFO Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 192000,
.formats = AIU_FORMATS,
},
.ops = &aiu_fifo_i2s_dai_ops,
},
[CPU_SPDIF_FIFO] = {
.name = "SPDIF FIFO",
.playback = {
.stream_name = "SPDIF FIFO Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 192000,
.formats = AIU_FORMATS,
},
.ops = &aiu_fifo_spdif_dai_ops,
},
[CPU_I2S_ENCODER] = {
.name = "I2S Encoder",
.playback = {
.stream_name = "I2S Encoder Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = AIU_FORMATS,
},
.ops = &aiu_encoder_i2s_dai_ops,
},
[CPU_SPDIF_ENCODER] = {
.name = "SPDIF Encoder",
.playback = {
.stream_name = "SPDIF Encoder Playback",
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000),
.formats = AIU_FORMATS,
},
.ops = &aiu_encoder_spdif_dai_ops,
}
};
static const struct regmap_config aiu_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x2ac,
};
static int aiu_clk_bulk_get(struct device *dev,
const char * const *ids,
unsigned int num,
struct aiu_interface *interface)
{
struct clk_bulk_data *clks;
int i, ret;
clks = devm_kcalloc(dev, num, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
for (i = 0; i < num; i++)
clks[i].id = ids[i];
ret = devm_clk_bulk_get(dev, num, clks);
if (ret < 0)
return ret;
interface->clks = clks;
interface->clk_num = num;
return 0;
}
static const char * const aiu_i2s_ids[] = {
[PCLK] = "i2s_pclk",
[AOCLK] = "i2s_aoclk",
[MCLK] = "i2s_mclk",
[MIXER] = "i2s_mixer",
};
static const char * const aiu_spdif_ids[] = {
[PCLK] = "spdif_pclk",
[AOCLK] = "spdif_aoclk",
[MCLK] = "spdif_mclk_sel"
};
static int aiu_clk_get(struct device *dev)
{
struct aiu *aiu = dev_get_drvdata(dev);
int ret;
aiu->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(aiu->pclk))
return dev_err_probe(dev, PTR_ERR(aiu->pclk), "Can't get the aiu pclk\n");
aiu->spdif_mclk = devm_clk_get(dev, "spdif_mclk");
if (IS_ERR(aiu->spdif_mclk))
return dev_err_probe(dev, PTR_ERR(aiu->spdif_mclk),
"Can't get the aiu spdif master clock\n");
ret = aiu_clk_bulk_get(dev, aiu_i2s_ids, ARRAY_SIZE(aiu_i2s_ids),
&aiu->i2s);
if (ret)
return dev_err_probe(dev, ret, "Can't get the i2s clocks\n");
ret = aiu_clk_bulk_get(dev, aiu_spdif_ids, ARRAY_SIZE(aiu_spdif_ids),
&aiu->spdif);
if (ret)
return dev_err_probe(dev, ret, "Can't get the spdif clocks\n");
ret = clk_prepare_enable(aiu->pclk);
if (ret) {
dev_err(dev, "peripheral clock enable failed\n");
return ret;
}
ret = devm_add_action_or_reset(dev,
(void(*)(void *))clk_disable_unprepare,
aiu->pclk);
if (ret)
dev_err(dev, "failed to add reset action on pclk");
return ret;
}
static int aiu_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
void __iomem *regs;
struct regmap *map;
struct aiu *aiu;
int ret;
aiu = devm_kzalloc(dev, sizeof(*aiu), GFP_KERNEL);
if (!aiu)
return -ENOMEM;
aiu->platform = device_get_match_data(dev);
if (!aiu->platform)
return -ENODEV;
platform_set_drvdata(pdev, aiu);
ret = device_reset(dev);
if (ret)
return dev_err_probe(dev, ret, "Failed to reset device\n");
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
map = devm_regmap_init_mmio(dev, regs, &aiu_regmap_cfg);
if (IS_ERR(map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(map));
return PTR_ERR(map);
}
aiu->i2s.irq = platform_get_irq_byname(pdev, "i2s");
if (aiu->i2s.irq < 0)
return aiu->i2s.irq;
aiu->spdif.irq = platform_get_irq_byname(pdev, "spdif");
if (aiu->spdif.irq < 0)
return aiu->spdif.irq;
ret = aiu_clk_get(dev);
if (ret)
return ret;
/* Register the cpu component of the aiu */
ret = snd_soc_register_component(dev, &aiu_cpu_component,
aiu_cpu_dai_drv,
ARRAY_SIZE(aiu_cpu_dai_drv));
if (ret) {
dev_err(dev, "Failed to register cpu component\n");
return ret;
}
/* Register the hdmi codec control component */
ret = aiu_hdmi_ctrl_register_component(dev);
if (ret) {
dev_err(dev, "Failed to register hdmi control component\n");
goto err;
}
/* Register the internal dac control component on gxl */
if (aiu->platform->has_acodec) {
ret = aiu_acodec_ctrl_register_component(dev);
if (ret) {
dev_err(dev,
"Failed to register acodec control component\n");
goto err;
}
}
return 0;
err:
snd_soc_unregister_component(dev);
return ret;
}
static void aiu_remove(struct platform_device *pdev)
{
snd_soc_unregister_component(&pdev->dev);
}
static const struct aiu_platform_data aiu_gxbb_pdata = {
.has_acodec = false,
.has_clk_ctrl_more_i2s_div = true,
};
static const struct aiu_platform_data aiu_gxl_pdata = {
.has_acodec = true,
.has_clk_ctrl_more_i2s_div = true,
};
static const struct aiu_platform_data aiu_meson8_pdata = {
.has_acodec = false,
.has_clk_ctrl_more_i2s_div = false,
};
static const struct of_device_id aiu_of_match[] = {
{ .compatible = "amlogic,aiu-gxbb", .data = &aiu_gxbb_pdata },
{ .compatible = "amlogic,aiu-gxl", .data = &aiu_gxl_pdata },
{ .compatible = "amlogic,aiu-meson8", .data = &aiu_meson8_pdata },
{ .compatible = "amlogic,aiu-meson8b", .data = &aiu_meson8_pdata },
{}
};
MODULE_DEVICE_TABLE(of, aiu_of_match);
static struct platform_driver aiu_pdrv = {
.probe = aiu_probe,
.remove_new = aiu_remove,
.driver = {
.name = "meson-aiu",
.of_match_table = aiu_of_match,
},
};
module_platform_driver(aiu_pdrv);
MODULE_DESCRIPTION("Meson AIU Driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/aiu.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "aiu.h"
#include "aiu-fifo.h"
#define AIU_IEC958_DCU_FF_CTRL_EN BIT(0)
#define AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE BIT(1)
#define AIU_IEC958_DCU_FF_CTRL_IRQ_MODE GENMASK(3, 2)
#define AIU_IEC958_DCU_FF_CTRL_IRQ_OUT_THD BIT(2)
#define AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ BIT(3)
#define AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN BIT(4)
#define AIU_IEC958_DCU_FF_CTRL_BYTE_SEEK BIT(5)
#define AIU_IEC958_DCU_FF_CTRL_CONTINUE BIT(6)
#define AIU_MEM_IEC958_CONTROL_ENDIAN GENMASK(5, 3)
#define AIU_MEM_IEC958_CONTROL_RD_DDR BIT(6)
#define AIU_MEM_IEC958_CONTROL_MODE_16BIT BIT(7)
#define AIU_MEM_IEC958_CONTROL_MODE_LINEAR BIT(8)
#define AIU_MEM_IEC958_BUF_CNTL_INIT BIT(0)
#define AIU_FIFO_SPDIF_BLOCK 8
static struct snd_pcm_hardware fifo_spdif_pcm = {
.info = (SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE),
.formats = AIU_FORMATS,
.rate_min = 5512,
.rate_max = 192000,
.channels_min = 2,
.channels_max = 2,
.period_bytes_min = AIU_FIFO_SPDIF_BLOCK,
.period_bytes_max = AIU_FIFO_SPDIF_BLOCK * USHRT_MAX,
.periods_min = 2,
.periods_max = UINT_MAX,
/* No real justification for this */
.buffer_bytes_max = 1 * 1024 * 1024,
};
static void fifo_spdif_dcu_enable(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
AIU_IEC958_DCU_FF_CTRL_EN,
enable ? AIU_IEC958_DCU_FF_CTRL_EN : 0);
}
static int fifo_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int ret;
ret = aiu_fifo_trigger(substream, cmd, dai);
if (ret)
return ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
fifo_spdif_dcu_enable(component, true);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
fifo_spdif_dcu_enable(component, false);
break;
default:
return -EINVAL;
}
return 0;
}
static int fifo_spdif_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int ret;
ret = aiu_fifo_prepare(substream, dai);
if (ret)
return ret;
snd_soc_component_update_bits(component,
AIU_MEM_IEC958_BUF_CNTL,
AIU_MEM_IEC958_BUF_CNTL_INIT,
AIU_MEM_IEC958_BUF_CNTL_INIT);
snd_soc_component_update_bits(component,
AIU_MEM_IEC958_BUF_CNTL,
AIU_MEM_IEC958_BUF_CNTL_INIT, 0);
return 0;
}
static int fifo_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
unsigned int val;
int ret;
ret = aiu_fifo_hw_params(substream, params, dai);
if (ret)
return ret;
val = AIU_MEM_IEC958_CONTROL_RD_DDR |
AIU_MEM_IEC958_CONTROL_MODE_LINEAR;
switch (params_physical_width(params)) {
case 16:
val |= AIU_MEM_IEC958_CONTROL_MODE_16BIT;
break;
case 32:
break;
default:
dev_err(dai->dev, "Unsupported physical width %u\n",
params_physical_width(params));
return -EINVAL;
}
snd_soc_component_update_bits(component, AIU_MEM_IEC958_CONTROL,
AIU_MEM_IEC958_CONTROL_ENDIAN |
AIU_MEM_IEC958_CONTROL_RD_DDR |
AIU_MEM_IEC958_CONTROL_MODE_LINEAR |
AIU_MEM_IEC958_CONTROL_MODE_16BIT,
val);
/* Number bytes read by the FIFO between each IRQ */
snd_soc_component_write(component, AIU_IEC958_BPF,
params_period_bytes(params));
/*
* AUTO_DISABLE and SYNC_HEAD are enabled by default but
* this should be disabled in PCM (uncompressed) mode
*/
snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE |
AIU_IEC958_DCU_FF_CTRL_IRQ_MODE |
AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN,
AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ);
return 0;
}
const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops = {
.pcm_new = aiu_fifo_pcm_new,
.probe = aiu_fifo_spdif_dai_probe,
.remove = aiu_fifo_dai_remove,
.trigger = fifo_spdif_trigger,
.prepare = fifo_spdif_prepare,
.hw_params = fifo_spdif_hw_params,
.startup = aiu_fifo_startup,
.shutdown = aiu_fifo_shutdown,
};
int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aiu *aiu = snd_soc_component_get_drvdata(component);
struct aiu_fifo *fifo;
int ret;
ret = aiu_fifo_dai_probe(dai);
if (ret)
return ret;
fifo = snd_soc_dai_dma_data_get_playback(dai);
fifo->pcm = &fifo_spdif_pcm;
fifo->mem_offset = AIU_MEM_IEC958_START;
fifo->fifo_block = 1;
fifo->pclk = aiu->spdif.clks[PCLK].clk;
fifo->irq = aiu->spdif.irq;
return 0;
}
| linux-master | sound/soc/meson/aiu-fifo-spdif.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/meson-aiu.h>
#include "aiu.h"
#include "meson-codec-glue.h"
#define CTRL_DIN_EN 15
#define CTRL_CLK_INV BIT(14)
#define CTRL_LRCLK_INV BIT(13)
#define CTRL_I2S_IN_BCLK_SRC BIT(11)
#define CTRL_DIN_LRCLK_SRC_SHIFT 6
#define CTRL_DIN_LRCLK_SRC (0x3 << CTRL_DIN_LRCLK_SRC_SHIFT)
#define CTRL_BCLK_MCLK_SRC GENMASK(5, 4)
#define CTRL_DIN_SKEW GENMASK(3, 2)
#define CTRL_I2S_OUT_LANE_SRC 0
#define AIU_ACODEC_OUT_CHMAX 2
static const char * const aiu_acodec_ctrl_mux_texts[] = {
"DISABLED", "I2S", "PCM",
};
static int aiu_acodec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mux, changed;
mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
changed = snd_soc_component_test_bits(component, e->reg,
CTRL_DIN_LRCLK_SRC,
FIELD_PREP(CTRL_DIN_LRCLK_SRC,
mux));
if (!changed)
return 0;
/* Force disconnect of the mux while updating */
snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
snd_soc_component_update_bits(component, e->reg,
CTRL_DIN_LRCLK_SRC |
CTRL_BCLK_MCLK_SRC,
FIELD_PREP(CTRL_DIN_LRCLK_SRC, mux) |
FIELD_PREP(CTRL_BCLK_MCLK_SRC, mux));
snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
return 1;
}
static SOC_ENUM_SINGLE_DECL(aiu_acodec_ctrl_mux_enum, AIU_ACODEC_CTRL,
CTRL_DIN_LRCLK_SRC_SHIFT,
aiu_acodec_ctrl_mux_texts);
static const struct snd_kcontrol_new aiu_acodec_ctrl_mux =
SOC_DAPM_ENUM_EXT("ACodec Source", aiu_acodec_ctrl_mux_enum,
snd_soc_dapm_get_enum_double,
aiu_acodec_ctrl_mux_put_enum);
static const struct snd_kcontrol_new aiu_acodec_ctrl_out_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", AIU_ACODEC_CTRL,
CTRL_DIN_EN, 1, 0);
static const struct snd_soc_dapm_widget aiu_acodec_ctrl_widgets[] = {
SND_SOC_DAPM_MUX("ACODEC SRC", SND_SOC_NOPM, 0, 0,
&aiu_acodec_ctrl_mux),
SND_SOC_DAPM_SWITCH("ACODEC OUT EN", SND_SOC_NOPM, 0, 0,
&aiu_acodec_ctrl_out_enable),
};
static int aiu_acodec_ctrl_input_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct meson_codec_glue_input *data;
int ret;
ret = meson_codec_glue_input_hw_params(substream, params, dai);
if (ret)
return ret;
/* The glue will provide 1 lane out of the 4 to the output */
data = meson_codec_glue_input_get_data(dai);
data->params.channels_min = min_t(unsigned int, AIU_ACODEC_OUT_CHMAX,
data->params.channels_min);
data->params.channels_max = min_t(unsigned int, AIU_ACODEC_OUT_CHMAX,
data->params.channels_max);
return 0;
}
static const struct snd_soc_dai_ops aiu_acodec_ctrl_input_ops = {
.probe = meson_codec_glue_input_dai_probe,
.remove = meson_codec_glue_input_dai_remove,
.hw_params = aiu_acodec_ctrl_input_hw_params,
.set_fmt = meson_codec_glue_input_set_fmt,
};
static const struct snd_soc_dai_ops aiu_acodec_ctrl_output_ops = {
.startup = meson_codec_glue_output_startup,
};
#define AIU_ACODEC_CTRL_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define AIU_ACODEC_STREAM(xname, xsuffix, xchmax) \
{ \
.stream_name = xname " " xsuffix, \
.channels_min = 1, \
.channels_max = (xchmax), \
.rate_min = 5512, \
.rate_max = 192000, \
.formats = AIU_ACODEC_CTRL_FORMATS, \
}
#define AIU_ACODEC_INPUT(xname) { \
.name = "ACODEC CTRL " xname, \
.playback = AIU_ACODEC_STREAM(xname, "Playback", 8), \
.ops = &aiu_acodec_ctrl_input_ops, \
}
#define AIU_ACODEC_OUTPUT(xname) { \
.name = "ACODEC CTRL " xname, \
.capture = AIU_ACODEC_STREAM(xname, "Capture", AIU_ACODEC_OUT_CHMAX), \
.ops = &aiu_acodec_ctrl_output_ops, \
}
static struct snd_soc_dai_driver aiu_acodec_ctrl_dai_drv[] = {
[CTRL_I2S] = AIU_ACODEC_INPUT("ACODEC I2S IN"),
[CTRL_PCM] = AIU_ACODEC_INPUT("ACODEC PCM IN"),
[CTRL_OUT] = AIU_ACODEC_OUTPUT("ACODEC OUT"),
};
static const struct snd_soc_dapm_route aiu_acodec_ctrl_routes[] = {
{ "ACODEC SRC", "I2S", "ACODEC I2S IN Playback" },
{ "ACODEC SRC", "PCM", "ACODEC PCM IN Playback" },
{ "ACODEC OUT EN", "Switch", "ACODEC SRC" },
{ "ACODEC OUT Capture", NULL, "ACODEC OUT EN" },
};
static const struct snd_kcontrol_new aiu_acodec_ctrl_controls[] = {
SOC_SINGLE("ACODEC I2S Lane Select", AIU_ACODEC_CTRL,
CTRL_I2S_OUT_LANE_SRC, 3, 0),
};
static int aiu_acodec_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
return aiu_of_xlate_dai_name(component, args, dai_name, AIU_ACODEC);
}
static int aiu_acodec_ctrl_component_probe(struct snd_soc_component *component)
{
/*
* NOTE: Din Skew setting
* According to the documentation, the following update adds one delay
* to the din line. Without this, the output saturates. This happens
* regardless of the link format (i2s or left_j) so it is not clear what
* it actually does but it seems to be required
*/
snd_soc_component_update_bits(component, AIU_ACODEC_CTRL,
CTRL_DIN_SKEW,
FIELD_PREP(CTRL_DIN_SKEW, 2));
return 0;
}
static const struct snd_soc_component_driver aiu_acodec_ctrl_component = {
.name = "AIU Internal DAC Codec Control",
.probe = aiu_acodec_ctrl_component_probe,
.controls = aiu_acodec_ctrl_controls,
.num_controls = ARRAY_SIZE(aiu_acodec_ctrl_controls),
.dapm_widgets = aiu_acodec_ctrl_widgets,
.num_dapm_widgets = ARRAY_SIZE(aiu_acodec_ctrl_widgets),
.dapm_routes = aiu_acodec_ctrl_routes,
.num_dapm_routes = ARRAY_SIZE(aiu_acodec_ctrl_routes),
.of_xlate_dai_name = aiu_acodec_of_xlate_dai_name,
.endianness = 1,
#ifdef CONFIG_DEBUG_FS
.debugfs_prefix = "acodec",
#endif
};
int aiu_acodec_ctrl_register_component(struct device *dev)
{
return snd_soc_register_component(dev, &aiu_acodec_ctrl_component,
aiu_acodec_ctrl_dai_drv,
ARRAY_SIZE(aiu_acodec_ctrl_dai_drv));
}
| linux-master | sound/soc/meson/aiu-acodec-ctrl.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/meson-aiu.h>
#include "aiu.h"
#include "meson-codec-glue.h"
#define CTRL_CLK_SEL GENMASK(1, 0)
#define CTRL_DATA_SEL_SHIFT 4
#define CTRL_DATA_SEL (0x3 << CTRL_DATA_SEL_SHIFT)
static const char * const aiu_codec_ctrl_mux_texts[] = {
"DISABLED", "PCM", "I2S",
};
static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mux, changed;
mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
changed = snd_soc_component_test_bits(component, e->reg,
CTRL_DATA_SEL,
FIELD_PREP(CTRL_DATA_SEL, mux));
if (!changed)
return 0;
/* Force disconnect of the mux while updating */
snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
/* Reset the source first */
snd_soc_component_update_bits(component, e->reg,
CTRL_CLK_SEL |
CTRL_DATA_SEL,
FIELD_PREP(CTRL_CLK_SEL, 0) |
FIELD_PREP(CTRL_DATA_SEL, 0));
/* Set the appropriate source */
snd_soc_component_update_bits(component, e->reg,
CTRL_CLK_SEL |
CTRL_DATA_SEL,
FIELD_PREP(CTRL_CLK_SEL, mux) |
FIELD_PREP(CTRL_DATA_SEL, mux));
snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
return 1;
}
static SOC_ENUM_SINGLE_DECL(aiu_hdmi_ctrl_mux_enum, AIU_HDMI_CLK_DATA_CTRL,
CTRL_DATA_SEL_SHIFT,
aiu_codec_ctrl_mux_texts);
static const struct snd_kcontrol_new aiu_hdmi_ctrl_mux =
SOC_DAPM_ENUM_EXT("HDMI Source", aiu_hdmi_ctrl_mux_enum,
snd_soc_dapm_get_enum_double,
aiu_codec_ctrl_mux_put_enum);
static const struct snd_soc_dapm_widget aiu_hdmi_ctrl_widgets[] = {
SND_SOC_DAPM_MUX("HDMI CTRL SRC", SND_SOC_NOPM, 0, 0,
&aiu_hdmi_ctrl_mux),
};
static const struct snd_soc_dai_ops aiu_codec_ctrl_input_ops = {
.probe = meson_codec_glue_input_dai_probe,
.remove = meson_codec_glue_input_dai_remove,
.hw_params = meson_codec_glue_input_hw_params,
.set_fmt = meson_codec_glue_input_set_fmt,
};
static const struct snd_soc_dai_ops aiu_codec_ctrl_output_ops = {
.startup = meson_codec_glue_output_startup,
};
#define AIU_CODEC_CTRL_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define AIU_CODEC_CTRL_STREAM(xname, xsuffix) \
{ \
.stream_name = xname " " xsuffix, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 5512, \
.rate_max = 192000, \
.formats = AIU_CODEC_CTRL_FORMATS, \
}
#define AIU_CODEC_CTRL_INPUT(xname) { \
.name = "CODEC CTRL " xname, \
.playback = AIU_CODEC_CTRL_STREAM(xname, "Playback"), \
.ops = &aiu_codec_ctrl_input_ops, \
}
#define AIU_CODEC_CTRL_OUTPUT(xname) { \
.name = "CODEC CTRL " xname, \
.capture = AIU_CODEC_CTRL_STREAM(xname, "Capture"), \
.ops = &aiu_codec_ctrl_output_ops, \
}
static struct snd_soc_dai_driver aiu_hdmi_ctrl_dai_drv[] = {
[CTRL_I2S] = AIU_CODEC_CTRL_INPUT("HDMI I2S IN"),
[CTRL_PCM] = AIU_CODEC_CTRL_INPUT("HDMI PCM IN"),
[CTRL_OUT] = AIU_CODEC_CTRL_OUTPUT("HDMI OUT"),
};
static const struct snd_soc_dapm_route aiu_hdmi_ctrl_routes[] = {
{ "HDMI CTRL SRC", "I2S", "HDMI I2S IN Playback" },
{ "HDMI CTRL SRC", "PCM", "HDMI PCM IN Playback" },
{ "HDMI OUT Capture", NULL, "HDMI CTRL SRC" },
};
static int aiu_hdmi_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
return aiu_of_xlate_dai_name(component, args, dai_name, AIU_HDMI);
}
static const struct snd_soc_component_driver aiu_hdmi_ctrl_component = {
.name = "AIU HDMI Codec Control",
.dapm_widgets = aiu_hdmi_ctrl_widgets,
.num_dapm_widgets = ARRAY_SIZE(aiu_hdmi_ctrl_widgets),
.dapm_routes = aiu_hdmi_ctrl_routes,
.num_dapm_routes = ARRAY_SIZE(aiu_hdmi_ctrl_routes),
.of_xlate_dai_name = aiu_hdmi_of_xlate_dai_name,
.endianness = 1,
#ifdef CONFIG_DEBUG_FS
.debugfs_prefix = "hdmi",
#endif
};
int aiu_hdmi_ctrl_register_component(struct device *dev)
{
return snd_soc_register_component(dev, &aiu_hdmi_ctrl_component,
aiu_hdmi_ctrl_dai_drv,
ARRAY_SIZE(aiu_hdmi_ctrl_dai_drv));
}
| linux-master | sound/soc/meson/aiu-codec-ctrl.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/pcm_params.h>
#include <sound/pcm_iec958.h>
/*
* NOTE:
* The meaning of bits SPDIFOUT_CTRL0_XXX_SEL is actually the opposite
* of what the documentation says. Manual control on V, U and C bits is
* applied when the related sel bits are cleared
*/
#define SPDIFOUT_STAT 0x00
#define SPDIFOUT_GAIN0 0x04
#define SPDIFOUT_GAIN1 0x08
#define SPDIFOUT_CTRL0 0x0c
#define SPDIFOUT_CTRL0_EN BIT(31)
#define SPDIFOUT_CTRL0_RST_OUT BIT(29)
#define SPDIFOUT_CTRL0_RST_IN BIT(28)
#define SPDIFOUT_CTRL0_USEL BIT(26)
#define SPDIFOUT_CTRL0_USET BIT(25)
#define SPDIFOUT_CTRL0_CHSTS_SEL BIT(24)
#define SPDIFOUT_CTRL0_DATA_SEL BIT(20)
#define SPDIFOUT_CTRL0_MSB_FIRST BIT(19)
#define SPDIFOUT_CTRL0_VSEL BIT(18)
#define SPDIFOUT_CTRL0_VSET BIT(17)
#define SPDIFOUT_CTRL0_MASK_MASK GENMASK(11, 4)
#define SPDIFOUT_CTRL0_MASK(x) ((x) << 4)
#define SPDIFOUT_CTRL1 0x10
#define SPDIFOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)
#define SPDIFOUT_CTRL1_MSB_POS(x) ((x) << 8)
#define SPDIFOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
#define SPDIFOUT_CTRL1_TYPE(x) ((x) << 4)
#define SPDIFOUT_PREAMB 0x14
#define SPDIFOUT_SWAP 0x18
#define SPDIFOUT_CHSTS0 0x1c
#define SPDIFOUT_CHSTS1 0x20
#define SPDIFOUT_CHSTS2 0x24
#define SPDIFOUT_CHSTS3 0x28
#define SPDIFOUT_CHSTS4 0x2c
#define SPDIFOUT_CHSTS5 0x30
#define SPDIFOUT_CHSTS6 0x34
#define SPDIFOUT_CHSTS7 0x38
#define SPDIFOUT_CHSTS8 0x3c
#define SPDIFOUT_CHSTS9 0x40
#define SPDIFOUT_CHSTSA 0x44
#define SPDIFOUT_CHSTSB 0x48
#define SPDIFOUT_MUTE_VAL 0x4c
struct axg_spdifout {
struct regmap *map;
struct clk *mclk;
struct clk *pclk;
};
static void axg_spdifout_enable(struct regmap *map)
{
/* Apply both reset */
regmap_update_bits(map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_RST_OUT | SPDIFOUT_CTRL0_RST_IN,
0);
/* Clear out reset before in reset */
regmap_update_bits(map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_RST_OUT, SPDIFOUT_CTRL0_RST_OUT);
regmap_update_bits(map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_RST_IN, SPDIFOUT_CTRL0_RST_IN);
/* Enable spdifout */
regmap_update_bits(map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_EN,
SPDIFOUT_CTRL0_EN);
}
static void axg_spdifout_disable(struct regmap *map)
{
regmap_update_bits(map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_EN, 0);
}
static int axg_spdifout_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
axg_spdifout_enable(priv->map);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
axg_spdifout_disable(priv->map);
return 0;
default:
return -EINVAL;
}
}
static int axg_spdifout_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
/* Use spdif valid bit to perform digital mute */
regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET,
mute ? SPDIFOUT_CTRL0_VSET : 0);
return 0;
}
static int axg_spdifout_sample_fmt(struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
unsigned int val;
/* Set the samples spdifout will pull from the FIFO */
switch (params_channels(params)) {
case 1:
val = SPDIFOUT_CTRL0_MASK(0x1);
break;
case 2:
val = SPDIFOUT_CTRL0_MASK(0x3);
break;
default:
dev_err(dai->dev, "too many channels for spdif dai: %u\n",
params_channels(params));
return -EINVAL;
}
regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_MASK_MASK, val);
/* FIFO data are arranged in chunks of 64bits */
switch (params_physical_width(params)) {
case 8:
/* 8 samples of 8 bits */
val = SPDIFOUT_CTRL1_TYPE(0);
break;
case 16:
/* 4 samples of 16 bits - right justified */
val = SPDIFOUT_CTRL1_TYPE(2);
break;
case 32:
/* 2 samples of 32 bits - right justified */
val = SPDIFOUT_CTRL1_TYPE(4);
break;
default:
dev_err(dai->dev, "Unsupported physical width: %u\n",
params_physical_width(params));
return -EINVAL;
}
/* Position of the MSB in FIFO samples */
val |= SPDIFOUT_CTRL1_MSB_POS(params_width(params) - 1);
regmap_update_bits(priv->map, SPDIFOUT_CTRL1,
SPDIFOUT_CTRL1_MSB_POS_MASK |
SPDIFOUT_CTRL1_TYPE_MASK, val);
regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_MSB_FIRST | SPDIFOUT_CTRL0_DATA_SEL,
0);
return 0;
}
static int axg_spdifout_set_chsts(struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
unsigned int offset;
int ret;
u8 cs[4];
u32 val;
ret = snd_pcm_create_iec958_consumer_hw_params(params, cs, 4);
if (ret < 0) {
dev_err(dai->dev, "Creating IEC958 channel status failed %d\n",
ret);
return ret;
}
val = cs[0] | cs[1] << 8 | cs[2] << 16 | cs[3] << 24;
/* Setup channel status A bits [31 - 0]*/
regmap_write(priv->map, SPDIFOUT_CHSTS0, val);
/* Clear channel status A bits [191 - 32] */
for (offset = SPDIFOUT_CHSTS1; offset <= SPDIFOUT_CHSTS5;
offset += regmap_get_reg_stride(priv->map))
regmap_write(priv->map, offset, 0);
/* Setup channel status B bits [31 - 0]*/
regmap_write(priv->map, SPDIFOUT_CHSTS6, val);
/* Clear channel status B bits [191 - 32] */
for (offset = SPDIFOUT_CHSTS7; offset <= SPDIFOUT_CHSTSB;
offset += regmap_get_reg_stride(priv->map))
regmap_write(priv->map, offset, 0);
return 0;
}
static int axg_spdifout_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
int ret;
/* 2 * 32bits per subframe * 2 channels = 128 */
ret = clk_set_rate(priv->mclk, rate * 128);
if (ret) {
dev_err(dai->dev, "failed to set spdif clock\n");
return ret;
}
ret = axg_spdifout_sample_fmt(params, dai);
if (ret) {
dev_err(dai->dev, "failed to setup sample format\n");
return ret;
}
ret = axg_spdifout_set_chsts(params, dai);
if (ret) {
dev_err(dai->dev, "failed to setup channel status words\n");
return ret;
}
return 0;
}
static int axg_spdifout_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
int ret;
/* Clock the spdif output block */
ret = clk_prepare_enable(priv->pclk);
if (ret) {
dev_err(dai->dev, "failed to enable pclk\n");
return ret;
}
/* Make sure the block is initially stopped */
axg_spdifout_disable(priv->map);
/* Insert data from bit 27 lsb first */
regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_MSB_FIRST | SPDIFOUT_CTRL0_DATA_SEL,
0);
/* Manual control of V, C and U, U = 0 */
regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
SPDIFOUT_CTRL0_CHSTS_SEL | SPDIFOUT_CTRL0_VSEL |
SPDIFOUT_CTRL0_USEL | SPDIFOUT_CTRL0_USET,
0);
/* Static SWAP configuration ATM */
regmap_write(priv->map, SPDIFOUT_SWAP, 0x10);
return 0;
}
static void axg_spdifout_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
clk_disable_unprepare(priv->pclk);
}
static const struct snd_soc_dai_ops axg_spdifout_ops = {
.trigger = axg_spdifout_trigger,
.mute_stream = axg_spdifout_mute,
.hw_params = axg_spdifout_hw_params,
.startup = axg_spdifout_startup,
.shutdown = axg_spdifout_shutdown,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver axg_spdifout_dai_drv[] = {
{
.name = "SPDIF Output",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000),
.formats = (SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_LE |
SNDRV_PCM_FMTBIT_S24_LE),
},
.ops = &axg_spdifout_ops,
},
};
static const char * const spdifout_sel_texts[] = {
"IN 0", "IN 1", "IN 2",
};
static SOC_ENUM_SINGLE_DECL(axg_spdifout_sel_enum, SPDIFOUT_CTRL1, 24,
spdifout_sel_texts);
static const struct snd_kcontrol_new axg_spdifout_in_mux =
SOC_DAPM_ENUM("Input Source", axg_spdifout_sel_enum);
static const struct snd_soc_dapm_widget axg_spdifout_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_spdifout_in_mux),
};
static const struct snd_soc_dapm_route axg_spdifout_dapm_routes[] = {
{ "SRC SEL", "IN 0", "IN 0" },
{ "SRC SEL", "IN 1", "IN 1" },
{ "SRC SEL", "IN 2", "IN 2" },
{ "Playback", NULL, "SRC SEL" },
};
static const struct snd_kcontrol_new axg_spdifout_controls[] = {
SOC_DOUBLE("Playback Volume", SPDIFOUT_GAIN0, 0, 8, 255, 0),
SOC_DOUBLE("Playback Switch", SPDIFOUT_CTRL0, 22, 21, 1, 1),
SOC_SINGLE("Playback Gain Enable Switch",
SPDIFOUT_CTRL1, 26, 1, 0),
SOC_SINGLE("Playback Channels Mix Switch",
SPDIFOUT_CTRL0, 23, 1, 0),
};
static int axg_spdifout_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct axg_spdifout *priv = snd_soc_component_get_drvdata(component);
enum snd_soc_bias_level now =
snd_soc_component_get_bias_level(component);
int ret = 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (now == SND_SOC_BIAS_STANDBY)
ret = clk_prepare_enable(priv->mclk);
break;
case SND_SOC_BIAS_STANDBY:
if (now == SND_SOC_BIAS_PREPARE)
clk_disable_unprepare(priv->mclk);
break;
case SND_SOC_BIAS_OFF:
case SND_SOC_BIAS_ON:
break;
}
return ret;
}
static const struct snd_soc_component_driver axg_spdifout_component_drv = {
.controls = axg_spdifout_controls,
.num_controls = ARRAY_SIZE(axg_spdifout_controls),
.dapm_widgets = axg_spdifout_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_spdifout_dapm_widgets),
.dapm_routes = axg_spdifout_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_spdifout_dapm_routes),
.set_bias_level = axg_spdifout_set_bias_level,
.legacy_dai_naming = 1,
};
static const struct regmap_config axg_spdifout_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = SPDIFOUT_MUTE_VAL,
};
static const struct of_device_id axg_spdifout_of_match[] = {
{ .compatible = "amlogic,axg-spdifout", },
{}
};
MODULE_DEVICE_TABLE(of, axg_spdifout_of_match);
static int axg_spdifout_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct axg_spdifout *priv;
void __iomem *regs;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifout_regmap_cfg);
if (IS_ERR(priv->map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(priv->map));
return PTR_ERR(priv->map);
}
priv->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(priv->pclk))
return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");
priv->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(priv->mclk))
return dev_err_probe(dev, PTR_ERR(priv->mclk), "failed to get mclk\n");
return devm_snd_soc_register_component(dev, &axg_spdifout_component_drv,
axg_spdifout_dai_drv, ARRAY_SIZE(axg_spdifout_dai_drv));
}
static struct platform_driver axg_spdifout_pdrv = {
.probe = axg_spdifout_probe,
.driver = {
.name = "axg-spdifout",
.of_match_table = axg_spdifout_of_match,
},
};
module_platform_driver(axg_spdifout_pdrv);
MODULE_DESCRIPTION("Amlogic AXG SPDIF Output driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-spdifout.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
/*
* This driver implements the frontend playback DAI of AXG and G12A based SoCs
*/
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-fifo.h"
#define CTRL0_FRDDR_PP_MODE BIT(30)
#define CTRL0_SEL1_EN_SHIFT 3
#define CTRL0_SEL2_SHIFT 4
#define CTRL0_SEL2_EN_SHIFT 7
#define CTRL0_SEL3_SHIFT 8
#define CTRL0_SEL3_EN_SHIFT 11
#define CTRL1_FRDDR_FORCE_FINISH BIT(12)
#define CTRL2_SEL1_SHIFT 0
#define CTRL2_SEL1_EN_SHIFT 4
#define CTRL2_SEL2_SHIFT 8
#define CTRL2_SEL2_EN_SHIFT 12
#define CTRL2_SEL3_SHIFT 16
#define CTRL2_SEL3_EN_SHIFT 20
static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
/* Reset the read pointer to the FIFO_INIT_ADDR */
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_FRDDR_FORCE_FINISH, 0);
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH);
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_FRDDR_FORCE_FINISH, 0);
return 0;
}
static int axg_frddr_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
unsigned int period, depth, val;
period = params_period_bytes(params);
/* Trim the FIFO depth if the period is small to improve latency */
depth = min(period, fifo->depth);
val = (depth / AXG_FIFO_BURST) - 1;
regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
CTRL1_FRDDR_DEPTH(val));
return 0;
}
static int axg_frddr_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
int ret;
/* Enable pclk to access registers and clock the fifo ip */
ret = clk_prepare_enable(fifo->pclk);
if (ret)
return ret;
/* Apply single buffer mode to the interface */
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
return 0;
}
static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
clk_disable_unprepare(fifo->pclk);
}
static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_dai *dai)
{
return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK);
}
static const struct snd_soc_dai_ops axg_frddr_ops = {
.hw_params = axg_frddr_dai_hw_params,
.startup = axg_frddr_dai_startup,
.shutdown = axg_frddr_dai_shutdown,
.pcm_new = axg_frddr_pcm_new,
};
static struct snd_soc_dai_driver axg_frddr_dai_drv = {
.name = "FRDDR",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
.rates = AXG_FIFO_RATES,
.formats = AXG_FIFO_FORMATS,
},
.ops = &axg_frddr_ops,
};
static const char * const axg_frddr_sel_texts[] = {
"OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4", "OUT 5", "OUT 6", "OUT 7",
};
static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
axg_frddr_sel_texts);
static const struct snd_kcontrol_new axg_frddr_out_demux =
SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum);
static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = {
SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0,
&axg_frddr_out_demux),
SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = {
{ "SINK SEL", NULL, "Playback" },
{ "OUT 0", "OUT 0", "SINK SEL" },
{ "OUT 1", "OUT 1", "SINK SEL" },
{ "OUT 2", "OUT 2", "SINK SEL" },
{ "OUT 3", "OUT 3", "SINK SEL" },
{ "OUT 4", "OUT 4", "SINK SEL" },
{ "OUT 5", "OUT 5", "SINK SEL" },
{ "OUT 6", "OUT 6", "SINK SEL" },
{ "OUT 7", "OUT 7", "SINK SEL" },
};
static const struct snd_soc_component_driver axg_frddr_component_drv = {
.dapm_widgets = axg_frddr_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets),
.dapm_routes = axg_frddr_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes),
.open = axg_fifo_pcm_open,
.close = axg_fifo_pcm_close,
.hw_params = axg_fifo_pcm_hw_params,
.hw_free = axg_fifo_pcm_hw_free,
.pointer = axg_fifo_pcm_pointer,
.trigger = axg_fifo_pcm_trigger,
.legacy_dai_naming = 1,
};
static const struct axg_fifo_match_data axg_frddr_match_data = {
.field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
.component_drv = &axg_frddr_component_drv,
.dai_drv = &axg_frddr_dai_drv
};
static const struct snd_soc_dai_ops g12a_frddr_ops = {
.prepare = g12a_frddr_dai_prepare,
.hw_params = axg_frddr_dai_hw_params,
.startup = axg_frddr_dai_startup,
.shutdown = axg_frddr_dai_shutdown,
.pcm_new = axg_frddr_pcm_new,
};
static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
.name = "FRDDR",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
.rates = AXG_FIFO_RATES,
.formats = AXG_FIFO_FORMATS,
},
.ops = &g12a_frddr_ops,
};
static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
axg_frddr_sel_texts);
static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT,
axg_frddr_sel_texts);
static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT,
axg_frddr_sel_texts);
static const struct snd_kcontrol_new g12a_frddr_out1_demux =
SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum);
static const struct snd_kcontrol_new g12a_frddr_out2_demux =
SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum);
static const struct snd_kcontrol_new g12a_frddr_out3_demux =
SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum);
static const struct snd_kcontrol_new g12a_frddr_out1_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
CTRL0_SEL1_EN_SHIFT, 1, 0);
static const struct snd_kcontrol_new g12a_frddr_out2_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
CTRL0_SEL2_EN_SHIFT, 1, 0);
static const struct snd_kcontrol_new g12a_frddr_out3_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
CTRL0_SEL3_EN_SHIFT, 1, 0);
static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
&g12a_frddr_out1_enable),
SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
&g12a_frddr_out2_enable),
SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
&g12a_frddr_out3_enable),
SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
&g12a_frddr_out1_demux),
SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
&g12a_frddr_out2_demux),
SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
&g12a_frddr_out3_demux),
SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = {
{ "SRC 1", NULL, "Playback" },
{ "SRC 2", NULL, "Playback" },
{ "SRC 3", NULL, "Playback" },
{ "SRC 1 EN", "Switch", "SRC 1" },
{ "SRC 2 EN", "Switch", "SRC 2" },
{ "SRC 3 EN", "Switch", "SRC 3" },
{ "SINK 1 SEL", NULL, "SRC 1 EN" },
{ "SINK 2 SEL", NULL, "SRC 2 EN" },
{ "SINK 3 SEL", NULL, "SRC 3 EN" },
{ "OUT 0", "OUT 0", "SINK 1 SEL" },
{ "OUT 1", "OUT 1", "SINK 1 SEL" },
{ "OUT 2", "OUT 2", "SINK 1 SEL" },
{ "OUT 3", "OUT 3", "SINK 1 SEL" },
{ "OUT 4", "OUT 4", "SINK 1 SEL" },
{ "OUT 5", "OUT 5", "SINK 1 SEL" },
{ "OUT 6", "OUT 6", "SINK 1 SEL" },
{ "OUT 7", "OUT 7", "SINK 1 SEL" },
{ "OUT 0", "OUT 0", "SINK 2 SEL" },
{ "OUT 1", "OUT 1", "SINK 2 SEL" },
{ "OUT 2", "OUT 2", "SINK 2 SEL" },
{ "OUT 3", "OUT 3", "SINK 2 SEL" },
{ "OUT 4", "OUT 4", "SINK 2 SEL" },
{ "OUT 5", "OUT 5", "SINK 2 SEL" },
{ "OUT 6", "OUT 6", "SINK 2 SEL" },
{ "OUT 7", "OUT 7", "SINK 2 SEL" },
{ "OUT 0", "OUT 0", "SINK 3 SEL" },
{ "OUT 1", "OUT 1", "SINK 3 SEL" },
{ "OUT 2", "OUT 2", "SINK 3 SEL" },
{ "OUT 3", "OUT 3", "SINK 3 SEL" },
{ "OUT 4", "OUT 4", "SINK 3 SEL" },
{ "OUT 5", "OUT 5", "SINK 3 SEL" },
{ "OUT 6", "OUT 6", "SINK 3 SEL" },
{ "OUT 7", "OUT 7", "SINK 3 SEL" },
};
static const struct snd_soc_component_driver g12a_frddr_component_drv = {
.dapm_widgets = g12a_frddr_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(g12a_frddr_dapm_widgets),
.dapm_routes = g12a_frddr_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
.open = axg_fifo_pcm_open,
.close = axg_fifo_pcm_close,
.hw_params = g12a_fifo_pcm_hw_params,
.hw_free = axg_fifo_pcm_hw_free,
.pointer = axg_fifo_pcm_pointer,
.trigger = axg_fifo_pcm_trigger,
.legacy_dai_naming = 1,
};
static const struct axg_fifo_match_data g12a_frddr_match_data = {
.field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
.component_drv = &g12a_frddr_component_drv,
.dai_drv = &g12a_frddr_dai_drv
};
/* On SM1, the output selection in on CTRL2 */
static const struct snd_kcontrol_new sm1_frddr_out1_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
CTRL2_SEL1_EN_SHIFT, 1, 0);
static const struct snd_kcontrol_new sm1_frddr_out2_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
CTRL2_SEL2_EN_SHIFT, 1, 0);
static const struct snd_kcontrol_new sm1_frddr_out3_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
CTRL2_SEL3_EN_SHIFT, 1, 0);
static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel1_enum, FIFO_CTRL2, CTRL2_SEL1_SHIFT,
axg_frddr_sel_texts);
static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel2_enum, FIFO_CTRL2, CTRL2_SEL2_SHIFT,
axg_frddr_sel_texts);
static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel3_enum, FIFO_CTRL2, CTRL2_SEL3_SHIFT,
axg_frddr_sel_texts);
static const struct snd_kcontrol_new sm1_frddr_out1_demux =
SOC_DAPM_ENUM("Output Src 1", sm1_frddr_sel1_enum);
static const struct snd_kcontrol_new sm1_frddr_out2_demux =
SOC_DAPM_ENUM("Output Src 2", sm1_frddr_sel2_enum);
static const struct snd_kcontrol_new sm1_frddr_out3_demux =
SOC_DAPM_ENUM("Output Src 3", sm1_frddr_sel3_enum);
static const struct snd_soc_dapm_widget sm1_frddr_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
&sm1_frddr_out1_enable),
SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
&sm1_frddr_out2_enable),
SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
&sm1_frddr_out3_enable),
SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
&sm1_frddr_out1_demux),
SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
&sm1_frddr_out2_demux),
SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
&sm1_frddr_out3_demux),
SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_component_driver sm1_frddr_component_drv = {
.dapm_widgets = sm1_frddr_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sm1_frddr_dapm_widgets),
.dapm_routes = g12a_frddr_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
.open = axg_fifo_pcm_open,
.close = axg_fifo_pcm_close,
.hw_params = g12a_fifo_pcm_hw_params,
.hw_free = axg_fifo_pcm_hw_free,
.pointer = axg_fifo_pcm_pointer,
.trigger = axg_fifo_pcm_trigger,
.legacy_dai_naming = 1,
};
static const struct axg_fifo_match_data sm1_frddr_match_data = {
.field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
.component_drv = &sm1_frddr_component_drv,
.dai_drv = &g12a_frddr_dai_drv
};
static const struct of_device_id axg_frddr_of_match[] = {
{
.compatible = "amlogic,axg-frddr",
.data = &axg_frddr_match_data,
}, {
.compatible = "amlogic,g12a-frddr",
.data = &g12a_frddr_match_data,
}, {
.compatible = "amlogic,sm1-frddr",
.data = &sm1_frddr_match_data,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_frddr_of_match);
static struct platform_driver axg_frddr_pdrv = {
.probe = axg_fifo_probe,
.driver = {
.name = "axg-frddr",
.of_match_table = axg_frddr_of_match,
},
};
module_platform_driver(axg_frddr_pdrv);
MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-frddr.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-tdm.h"
enum {
TDM_IFACE_PAD,
TDM_IFACE_LOOPBACK,
};
static unsigned int axg_tdm_slots_total(u32 *mask)
{
unsigned int slots = 0;
int i;
if (!mask)
return 0;
/* Count the total number of slots provided by all 4 lanes */
for (i = 0; i < AXG_TDM_NUM_LANES; i++)
slots += hweight32(mask[i]);
return slots;
}
int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
u32 *rx_mask, unsigned int slots,
unsigned int slot_width)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
struct axg_tdm_stream *tx = snd_soc_dai_dma_data_get_playback(dai);
struct axg_tdm_stream *rx = snd_soc_dai_dma_data_get_capture(dai);
unsigned int tx_slots, rx_slots;
unsigned int fmt = 0;
tx_slots = axg_tdm_slots_total(tx_mask);
rx_slots = axg_tdm_slots_total(rx_mask);
/* We should at least have a slot for a valid interface */
if (!tx_slots && !rx_slots) {
dev_err(dai->dev, "interface has no slot\n");
return -EINVAL;
}
iface->slots = slots;
switch (slot_width) {
case 0:
slot_width = 32;
fallthrough;
case 32:
fmt |= SNDRV_PCM_FMTBIT_S32_LE;
fallthrough;
case 24:
fmt |= SNDRV_PCM_FMTBIT_S24_LE;
fmt |= SNDRV_PCM_FMTBIT_S20_LE;
fallthrough;
case 16:
fmt |= SNDRV_PCM_FMTBIT_S16_LE;
fallthrough;
case 8:
fmt |= SNDRV_PCM_FMTBIT_S8;
break;
default:
dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
return -EINVAL;
}
iface->slot_width = slot_width;
/* Amend the dai driver and let dpcm merge do its job */
if (tx) {
tx->mask = tx_mask;
dai->driver->playback.channels_max = tx_slots;
dai->driver->playback.formats = fmt;
}
if (rx) {
rx->mask = rx_mask;
dai->driver->capture.channels_max = rx_slots;
dai->driver->capture.formats = fmt;
}
return 0;
}
EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
int ret = -ENOTSUPP;
if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
if (!iface->mclk) {
dev_warn(dai->dev, "master clock not provided\n");
} else {
ret = clk_set_rate(iface->mclk, freq);
if (!ret)
iface->mclk_rate = freq;
}
}
return ret;
}
static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
if (!iface->mclk) {
dev_err(dai->dev, "cpu clock master: mclk missing\n");
return -ENODEV;
}
break;
case SND_SOC_DAIFMT_BC_FC:
break;
case SND_SOC_DAIFMT_BP_FC:
case SND_SOC_DAIFMT_BC_FP:
dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
fallthrough;
default:
return -EINVAL;
}
iface->fmt = fmt;
return 0;
}
static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
struct axg_tdm_stream *ts =
snd_soc_dai_get_dma_data(dai, substream);
int ret;
if (!axg_tdm_slots_total(ts->mask)) {
dev_err(dai->dev, "interface has not slots\n");
return -EINVAL;
}
/* Apply component wide rate symmetry */
if (snd_soc_component_active(dai->component)) {
ret = snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
iface->rate);
if (ret < 0) {
dev_err(dai->dev,
"can't set iface rate constraint\n");
return ret;
}
}
return 0;
}
static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
unsigned int channels = params_channels(params);
unsigned int width = params_width(params);
/* Save rate and sample_bits for component symmetry */
iface->rate = params_rate(params);
/* Make sure this interface can cope with the stream */
if (axg_tdm_slots_total(ts->mask) < channels) {
dev_err(dai->dev, "not enough slots for channels\n");
return -EINVAL;
}
if (iface->slot_width < width) {
dev_err(dai->dev, "incompatible slots width for stream\n");
return -EINVAL;
}
/* Save the parameter for tdmout/tdmin widgets */
ts->physical_width = params_physical_width(params);
ts->width = params_width(params);
ts->channels = params_channels(params);
return 0;
}
static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
struct snd_pcm_hw_params *params)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
unsigned int ratio_num;
int ret;
ret = clk_set_rate(iface->lrclk, params_rate(params));
if (ret) {
dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
return ret;
}
switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
/* 50% duty cycle ratio */
ratio_num = 1;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
/*
* A zero duty cycle ratio will result in setting the mininum
* ratio possible which, for this clock, is 1 cycle of the
* parent bclk clock high and the rest low, This is exactly
* what we want here.
*/
ratio_num = 0;
break;
default:
return -EINVAL;
}
ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
if (ret) {
dev_err(dai->dev,
"setting sample clock duty cycle failed: %d\n", ret);
return ret;
}
/* Set sample clock inversion */
ret = clk_set_phase(iface->lrclk,
axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
if (ret) {
dev_err(dai->dev,
"setting sample clock phase failed: %d\n", ret);
return ret;
}
return 0;
}
static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
struct snd_pcm_hw_params *params)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
unsigned long srate;
int ret;
srate = iface->slots * iface->slot_width * params_rate(params);
if (!iface->mclk_rate) {
/* If no specific mclk is requested, default to bit clock * 4 */
clk_set_rate(iface->mclk, 4 * srate);
} else {
/* Check if we can actually get the bit clock from mclk */
if (iface->mclk_rate % srate) {
dev_err(dai->dev,
"can't derive sclk %lu from mclk %lu\n",
srate, iface->mclk_rate);
return -EINVAL;
}
}
ret = clk_set_rate(iface->sclk, srate);
if (ret) {
dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
return ret;
}
/* Set the bit clock inversion */
ret = clk_set_phase(iface->sclk,
axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
if (ret) {
dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
return ret;
}
return ret;
}
static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
int ret;
switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
if (iface->slots > 2) {
dev_err(dai->dev, "bad slot number for format: %d\n",
iface->slots);
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
break;
default:
dev_err(dai->dev, "unsupported dai format\n");
return -EINVAL;
}
ret = axg_tdm_iface_set_stream(substream, params, dai);
if (ret)
return ret;
if ((iface->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
SND_SOC_DAIFMT_BP_FP) {
ret = axg_tdm_iface_set_sclk(dai, params);
if (ret)
return ret;
ret = axg_tdm_iface_set_lrclk(dai, params);
if (ret)
return ret;
}
return 0;
}
static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
/* Stop all attached formatters */
axg_tdm_stream_stop(ts);
return 0;
}
static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
/* Force all attached formatters to update */
return axg_tdm_stream_reset(ts);
}
static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
{
int stream;
for_each_pcm_streams(stream) {
struct axg_tdm_stream *ts = snd_soc_dai_dma_data_get(dai, stream);
if (ts)
axg_tdm_stream_free(ts);
}
return 0;
}
static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
{
struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
int stream;
for_each_pcm_streams(stream) {
struct axg_tdm_stream *ts;
if (!snd_soc_dai_get_widget(dai, stream))
continue;
ts = axg_tdm_stream_alloc(iface);
if (!ts) {
axg_tdm_iface_remove_dai(dai);
return -ENOMEM;
}
snd_soc_dai_dma_data_set(dai, stream, ts);
}
return 0;
}
static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
.probe = axg_tdm_iface_probe_dai,
.remove = axg_tdm_iface_remove_dai,
.set_sysclk = axg_tdm_iface_set_sysclk,
.set_fmt = axg_tdm_iface_set_fmt,
.startup = axg_tdm_iface_startup,
.hw_params = axg_tdm_iface_hw_params,
.prepare = axg_tdm_iface_prepare,
.hw_free = axg_tdm_iface_hw_free,
};
/* TDM Backend DAIs */
static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
[TDM_IFACE_PAD] = {
.name = "TDM Pad",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = AXG_TDM_CHANNEL_MAX,
.rates = AXG_TDM_RATES,
.formats = AXG_TDM_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = AXG_TDM_CHANNEL_MAX,
.rates = AXG_TDM_RATES,
.formats = AXG_TDM_FORMATS,
},
.id = TDM_IFACE_PAD,
.ops = &axg_tdm_iface_ops,
},
[TDM_IFACE_LOOPBACK] = {
.name = "TDM Loopback",
.capture = {
.stream_name = "Loopback",
.channels_min = 1,
.channels_max = AXG_TDM_CHANNEL_MAX,
.rates = AXG_TDM_RATES,
.formats = AXG_TDM_FORMATS,
},
.id = TDM_IFACE_LOOPBACK,
.ops = &axg_tdm_iface_ops,
},
};
static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
enum snd_soc_bias_level now =
snd_soc_component_get_bias_level(component);
int ret = 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (now == SND_SOC_BIAS_STANDBY)
ret = clk_prepare_enable(iface->mclk);
break;
case SND_SOC_BIAS_STANDBY:
if (now == SND_SOC_BIAS_PREPARE)
clk_disable_unprepare(iface->mclk);
break;
case SND_SOC_BIAS_OFF:
case SND_SOC_BIAS_ON:
break;
}
return ret;
}
static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
SND_SOC_DAPM_SIGGEN("Playback Signal"),
};
static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
{ "Loopback", NULL, "Playback Signal" },
};
static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
.dapm_widgets = axg_tdm_iface_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
.dapm_routes = axg_tdm_iface_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
.set_bias_level = axg_tdm_iface_set_bias_level,
};
static const struct of_device_id axg_tdm_iface_of_match[] = {
{ .compatible = "amlogic,axg-tdm-iface", },
{}
};
MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
static int axg_tdm_iface_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct snd_soc_dai_driver *dai_drv;
struct axg_tdm_iface *iface;
int i;
iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
if (!iface)
return -ENOMEM;
platform_set_drvdata(pdev, iface);
/*
* Duplicate dai driver: depending on the slot masks configuration
* We'll change the number of channel provided by DAI stream, so dpcm
* channel merge can be done properly
*/
dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
sizeof(*dai_drv), GFP_KERNEL);
if (!dai_drv)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
sizeof(*dai_drv));
/* Bit clock provided on the pad */
iface->sclk = devm_clk_get(dev, "sclk");
if (IS_ERR(iface->sclk))
return dev_err_probe(dev, PTR_ERR(iface->sclk), "failed to get sclk\n");
/* Sample clock provided on the pad */
iface->lrclk = devm_clk_get(dev, "lrclk");
if (IS_ERR(iface->lrclk))
return dev_err_probe(dev, PTR_ERR(iface->lrclk), "failed to get lrclk\n");
/*
* mclk maybe be missing when the cpu dai is in slave mode and
* the codec does not require it to provide a master clock.
* At this point, ignore the error if mclk is missing. We'll
* throw an error if the cpu dai is master and mclk is missing
*/
iface->mclk = devm_clk_get_optional(dev, "mclk");
if (IS_ERR(iface->mclk))
return dev_err_probe(dev, PTR_ERR(iface->mclk), "failed to get mclk\n");
return devm_snd_soc_register_component(dev,
&axg_tdm_iface_component_drv, dai_drv,
ARRAY_SIZE(axg_tdm_iface_dai_drv));
}
static struct platform_driver axg_tdm_iface_pdrv = {
.probe = axg_tdm_iface_probe,
.driver = {
.name = "axg-tdm-iface",
.of_match_table = axg_tdm_iface_of_match,
},
};
module_platform_driver(axg_tdm_iface_pdrv);
MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-tdm-interface.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "aiu.h"
#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
#define AIU_RST_SOFT_I2S_FAST BIT(0)
#define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2)
#define AIU_CLK_CTRL_I2S_DIV_EN BIT(0)
#define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2)
#define AIU_CLK_CTRL_AOCLK_INVERT BIT(6)
#define AIU_CLK_CTRL_LRCLK_INVERT BIT(7)
#define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8)
#define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6)
#define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0)
#define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0)
static void aiu_encoder_i2s_divider_enable(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_update_bits(component, AIU_CLK_CTRL,
AIU_CLK_CTRL_I2S_DIV_EN,
enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
}
static int aiu_encoder_i2s_setup_desc(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
/* Always operate in split (classic interleaved) mode */
unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT;
/* Reset required to update the pipeline */
snd_soc_component_write(component, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
snd_soc_component_read(component, AIU_I2S_SYNC);
switch (params_physical_width(params)) {
case 16: /* Nothing to do */
break;
case 32:
desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT |
AIU_I2S_SOURCE_DESC_MODE_32BIT);
break;
default:
return -EINVAL;
}
switch (params_channels(params)) {
case 2: /* Nothing to do */
break;
case 8:
desc |= AIU_I2S_SOURCE_DESC_MODE_8CH;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC,
AIU_I2S_SOURCE_DESC_MODE_8CH |
AIU_I2S_SOURCE_DESC_MODE_24BIT |
AIU_I2S_SOURCE_DESC_MODE_32BIT |
AIU_I2S_SOURCE_DESC_MODE_SPLIT,
desc);
return 0;
}
static int aiu_encoder_i2s_set_legacy_div(struct snd_soc_component *component,
struct snd_pcm_hw_params *params,
unsigned int bs)
{
switch (bs) {
case 1:
case 2:
case 4:
case 8:
/* These are the only valid legacy dividers */
break;
default:
dev_err(component->dev, "Unsupported i2s divider: %u\n", bs);
return -EINVAL;
}
snd_soc_component_update_bits(component, AIU_CLK_CTRL,
AIU_CLK_CTRL_I2S_DIV,
FIELD_PREP(AIU_CLK_CTRL_I2S_DIV,
__ffs(bs)));
snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
AIU_CLK_CTRL_MORE_I2S_DIV,
FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
0));
return 0;
}
static int aiu_encoder_i2s_set_more_div(struct snd_soc_component *component,
struct snd_pcm_hw_params *params,
unsigned int bs)
{
/*
* NOTE: this HW is odd.
* In most configuration, the i2s divider is 'mclk / blck'.
* However, in 16 bits - 8ch mode, this factor needs to be
* increased by 50% to get the correct output rate.
* No idea why !
*/
if (params_width(params) == 16 && params_channels(params) == 8) {
if (bs % 2) {
dev_err(component->dev,
"Cannot increase i2s divider by 50%%\n");
return -EINVAL;
}
bs += bs / 2;
}
/* Use CLK_MORE for mclk to bclk divider */
snd_soc_component_update_bits(component, AIU_CLK_CTRL,
AIU_CLK_CTRL_I2S_DIV,
FIELD_PREP(AIU_CLK_CTRL_I2S_DIV, 0));
snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
AIU_CLK_CTRL_MORE_I2S_DIV,
FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
bs - 1));
return 0;
}
static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
struct aiu *aiu = snd_soc_component_get_drvdata(component);
unsigned int srate = params_rate(params);
unsigned int fs, bs;
int ret;
/* Get the oversampling factor */
fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate);
if (fs % 64)
return -EINVAL;
/* Send data MSB first */
snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG,
AIU_I2S_DAC_CFG_MSB_FIRST,
AIU_I2S_DAC_CFG_MSB_FIRST);
/* Set bclk to lrlck ratio */
snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL,
AIU_CODEC_DAC_LRCLK_CTRL_DIV,
FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV,
64 - 1));
bs = fs / 64;
if (aiu->platform->has_clk_ctrl_more_i2s_div)
ret = aiu_encoder_i2s_set_more_div(component, params, bs);
else
ret = aiu_encoder_i2s_set_legacy_div(component, params, bs);
if (ret)
return ret;
/* Make sure amclk is used for HDMI i2s as well */
snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
AIU_CLK_CTRL_MORE_HDMI_AMCLK,
AIU_CLK_CTRL_MORE_HDMI_AMCLK);
return 0;
}
static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int ret;
/* Disable the clock while changing the settings */
aiu_encoder_i2s_divider_enable(component, false);
ret = aiu_encoder_i2s_setup_desc(component, params);
if (ret) {
dev_err(dai->dev, "setting i2s desc failed\n");
return ret;
}
ret = aiu_encoder_i2s_set_clocks(component, params);
if (ret) {
dev_err(dai->dev, "setting i2s clocks failed\n");
return ret;
}
aiu_encoder_i2s_divider_enable(component, true);
return 0;
}
static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
aiu_encoder_i2s_divider_enable(component, false);
return 0;
}
static int aiu_encoder_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK;
unsigned int val = 0;
unsigned int skew;
/* Only CPU Master / Codec Slave supported ATM */
if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP)
return -EINVAL;
if (inv == SND_SOC_DAIFMT_NB_IF ||
inv == SND_SOC_DAIFMT_IB_IF)
val |= AIU_CLK_CTRL_LRCLK_INVERT;
if (inv == SND_SOC_DAIFMT_IB_NF ||
inv == SND_SOC_DAIFMT_IB_IF)
val |= AIU_CLK_CTRL_AOCLK_INVERT;
/* Signal skew */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* Invert sample clock for i2s */
val ^= AIU_CLK_CTRL_LRCLK_INVERT;
skew = 1;
break;
case SND_SOC_DAIFMT_LEFT_J:
skew = 0;
break;
default:
return -EINVAL;
}
val |= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew);
snd_soc_component_update_bits(component, AIU_CLK_CTRL,
AIU_CLK_CTRL_LRCLK_INVERT |
AIU_CLK_CTRL_AOCLK_INVERT |
AIU_CLK_CTRL_LRCLK_SKEW,
val);
return 0;
}
static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
int ret;
if (WARN_ON(clk_id != 0))
return -EINVAL;
if (dir == SND_SOC_CLOCK_IN)
return 0;
ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq);
if (ret)
dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
return ret;
}
static const unsigned int hw_channels[] = {2, 8};
static const struct snd_pcm_hw_constraint_list hw_channel_constraints = {
.list = hw_channels,
.count = ARRAY_SIZE(hw_channels),
.mask = 0,
};
static int aiu_encoder_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
int ret;
/* Make sure the encoder gets either 2 or 8 channels */
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&hw_channel_constraints);
if (ret) {
dev_err(dai->dev, "adding channels constraints failed\n");
return ret;
}
ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks);
if (ret)
dev_err(dai->dev, "failed to enable i2s clocks\n");
return ret;
}
static void aiu_encoder_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks);
}
const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops = {
.hw_params = aiu_encoder_i2s_hw_params,
.hw_free = aiu_encoder_i2s_hw_free,
.set_fmt = aiu_encoder_i2s_set_fmt,
.set_sysclk = aiu_encoder_i2s_set_sysclk,
.startup = aiu_encoder_i2s_startup,
.shutdown = aiu_encoder_i2s_shutdown,
};
| linux-master | sound/soc/meson/aiu-encoder-i2s.c |
Subsets and Splits