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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
/* This driver implements the frontend capture DAI of AXG based SoCs */
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-fifo.h"
#define CTRL0_TODDR_SEL_RESAMPLE BIT(30)
#define CTRL0_TODDR_EXT_SIGNED BIT(29)
#define CTRL0_TODDR_PP_MODE BIT(28)
#define CTRL0_TODDR_SYNC_CH BIT(27)
#define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
#define CTRL0_TODDR_TYPE(x) ((x) << 13)
#define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
#define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
#define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
#define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
#define CTRL1_TODDR_FORCE_FINISH BIT(25)
#define CTRL1_SEL_SHIFT 28
#define TODDR_MSB_POS 31
static int axg_toddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_dai *dai)
{
return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_CAPTURE);
}
static int g12a_toddr_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
/* Reset the write pointer to the FIFO_INIT_ADDR */
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_TODDR_FORCE_FINISH, 0);
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_TODDR_FORCE_FINISH, CTRL1_TODDR_FORCE_FINISH);
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_TODDR_FORCE_FINISH, 0);
return 0;
}
static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
unsigned int type, width;
switch (params_physical_width(params)) {
case 8:
type = 0; /* 8 samples of 8 bits */
break;
case 16:
type = 2; /* 4 samples of 16 bits - right justified */
break;
case 32:
type = 4; /* 2 samples of 32 bits - right justified */
break;
default:
return -EINVAL;
}
width = params_width(params);
regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_TODDR_TYPE_MASK |
CTRL0_TODDR_MSB_POS_MASK |
CTRL0_TODDR_LSB_POS_MASK,
CTRL0_TODDR_TYPE(type) |
CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
return 0;
}
static int axg_toddr_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
int ret;
/* Enable pclk to access registers and clock the fifo ip */
ret = clk_prepare_enable(fifo->pclk);
if (ret)
return ret;
/* Select orginal data - resampling not supported ATM */
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SEL_RESAMPLE, 0);
/* Only signed format are supported ATM */
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_EXT_SIGNED,
CTRL0_TODDR_EXT_SIGNED);
/* Apply single buffer mode to the interface */
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0);
return 0;
}
static void axg_toddr_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
clk_disable_unprepare(fifo->pclk);
}
static const struct snd_soc_dai_ops axg_toddr_ops = {
.hw_params = axg_toddr_dai_hw_params,
.startup = axg_toddr_dai_startup,
.shutdown = axg_toddr_dai_shutdown,
.pcm_new = axg_toddr_pcm_new,
};
static struct snd_soc_dai_driver axg_toddr_dai_drv = {
.name = "TODDR",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
.rates = AXG_FIFO_RATES,
.formats = AXG_FIFO_FORMATS,
},
.ops = &axg_toddr_ops,
};
static const char * const axg_toddr_sel_texts[] = {
"IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7"
};
static SOC_ENUM_SINGLE_DECL(axg_toddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
axg_toddr_sel_texts);
static const struct snd_kcontrol_new axg_toddr_in_mux =
SOC_DAPM_ENUM("Input Source", axg_toddr_sel_enum);
static const struct snd_soc_dapm_widget axg_toddr_dapm_widgets[] = {
SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_toddr_in_mux),
SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route axg_toddr_dapm_routes[] = {
{ "Capture", NULL, "SRC SEL" },
{ "SRC SEL", "IN 0", "IN 0" },
{ "SRC SEL", "IN 1", "IN 1" },
{ "SRC SEL", "IN 2", "IN 2" },
{ "SRC SEL", "IN 3", "IN 3" },
{ "SRC SEL", "IN 4", "IN 4" },
{ "SRC SEL", "IN 5", "IN 5" },
{ "SRC SEL", "IN 6", "IN 6" },
{ "SRC SEL", "IN 7", "IN 7" },
};
static const struct snd_soc_component_driver axg_toddr_component_drv = {
.dapm_widgets = axg_toddr_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
.dapm_routes = axg_toddr_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
.open = axg_fifo_pcm_open,
.close = axg_fifo_pcm_close,
.hw_params = axg_fifo_pcm_hw_params,
.hw_free = axg_fifo_pcm_hw_free,
.pointer = axg_fifo_pcm_pointer,
.trigger = axg_fifo_pcm_trigger,
.legacy_dai_naming = 1,
};
static const struct axg_fifo_match_data axg_toddr_match_data = {
.field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
.component_drv = &axg_toddr_component_drv,
.dai_drv = &axg_toddr_dai_drv
};
static int g12a_toddr_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
int ret;
ret = axg_toddr_dai_startup(substream, dai);
if (ret)
return ret;
/*
* Make sure the first channel ends up in the at beginning of the output
* As weird as it looks, without this the first channel may be misplaced
* in memory, with a random shift of 2 channels.
*/
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SYNC_CH,
CTRL0_TODDR_SYNC_CH);
return 0;
}
static const struct snd_soc_dai_ops g12a_toddr_ops = {
.prepare = g12a_toddr_dai_prepare,
.hw_params = axg_toddr_dai_hw_params,
.startup = g12a_toddr_dai_startup,
.shutdown = axg_toddr_dai_shutdown,
.pcm_new = axg_toddr_pcm_new,
};
static struct snd_soc_dai_driver g12a_toddr_dai_drv = {
.name = "TODDR",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
.rates = AXG_FIFO_RATES,
.formats = AXG_FIFO_FORMATS,
},
.ops = &g12a_toddr_ops,
};
static const struct snd_soc_component_driver g12a_toddr_component_drv = {
.dapm_widgets = axg_toddr_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
.dapm_routes = axg_toddr_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
.open = axg_fifo_pcm_open,
.close = axg_fifo_pcm_close,
.hw_params = g12a_fifo_pcm_hw_params,
.hw_free = axg_fifo_pcm_hw_free,
.pointer = axg_fifo_pcm_pointer,
.trigger = axg_fifo_pcm_trigger,
.legacy_dai_naming = 1,
};
static const struct axg_fifo_match_data g12a_toddr_match_data = {
.field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
.component_drv = &g12a_toddr_component_drv,
.dai_drv = &g12a_toddr_dai_drv
};
static const char * const sm1_toddr_sel_texts[] = {
"IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7",
"IN 8", "IN 9", "IN 10", "IN 11", "IN 12", "IN 13", "IN 14", "IN 15"
};
static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT,
sm1_toddr_sel_texts);
static const struct snd_kcontrol_new sm1_toddr_in_mux =
SOC_DAPM_ENUM("Input Source", sm1_toddr_sel_enum);
static const struct snd_soc_dapm_widget sm1_toddr_dapm_widgets[] = {
SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &sm1_toddr_in_mux),
SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 8", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 9", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 10", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 11", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 12", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 13", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 14", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 15", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route sm1_toddr_dapm_routes[] = {
{ "Capture", NULL, "SRC SEL" },
{ "SRC SEL", "IN 0", "IN 0" },
{ "SRC SEL", "IN 1", "IN 1" },
{ "SRC SEL", "IN 2", "IN 2" },
{ "SRC SEL", "IN 3", "IN 3" },
{ "SRC SEL", "IN 4", "IN 4" },
{ "SRC SEL", "IN 5", "IN 5" },
{ "SRC SEL", "IN 6", "IN 6" },
{ "SRC SEL", "IN 7", "IN 7" },
{ "SRC SEL", "IN 8", "IN 8" },
{ "SRC SEL", "IN 9", "IN 9" },
{ "SRC SEL", "IN 10", "IN 10" },
{ "SRC SEL", "IN 11", "IN 11" },
{ "SRC SEL", "IN 12", "IN 12" },
{ "SRC SEL", "IN 13", "IN 13" },
{ "SRC SEL", "IN 14", "IN 14" },
{ "SRC SEL", "IN 15", "IN 15" },
};
static const struct snd_soc_component_driver sm1_toddr_component_drv = {
.dapm_widgets = sm1_toddr_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sm1_toddr_dapm_widgets),
.dapm_routes = sm1_toddr_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sm1_toddr_dapm_routes),
.open = axg_fifo_pcm_open,
.close = axg_fifo_pcm_close,
.hw_params = g12a_fifo_pcm_hw_params,
.hw_free = axg_fifo_pcm_hw_free,
.pointer = axg_fifo_pcm_pointer,
.trigger = axg_fifo_pcm_trigger,
.legacy_dai_naming = 1,
};
static const struct axg_fifo_match_data sm1_toddr_match_data = {
.field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23),
.component_drv = &sm1_toddr_component_drv,
.dai_drv = &g12a_toddr_dai_drv
};
static const struct of_device_id axg_toddr_of_match[] = {
{
.compatible = "amlogic,axg-toddr",
.data = &axg_toddr_match_data,
}, {
.compatible = "amlogic,g12a-toddr",
.data = &g12a_toddr_match_data,
}, {
.compatible = "amlogic,sm1-toddr",
.data = &sm1_toddr_match_data,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_toddr_of_match);
static struct platform_driver axg_toddr_pdrv = {
.probe = axg_fifo_probe,
.driver = {
.name = "axg-toddr",
.of_match_table = axg_toddr_of_match,
},
};
module_platform_driver(axg_toddr_pdrv);
MODULE_DESCRIPTION("Amlogic AXG capture fifo driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-toddr.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-tdm-formatter.h"
#define TDMIN_CTRL 0x00
#define TDMIN_CTRL_ENABLE BIT(31)
#define TDMIN_CTRL_I2S_MODE BIT(30)
#define TDMIN_CTRL_RST_OUT BIT(29)
#define TDMIN_CTRL_RST_IN BIT(28)
#define TDMIN_CTRL_WS_INV BIT(25)
#define TDMIN_CTRL_SEL_SHIFT 20
#define TDMIN_CTRL_IN_BIT_SKEW_MASK GENMASK(18, 16)
#define TDMIN_CTRL_IN_BIT_SKEW(x) ((x) << 16)
#define TDMIN_CTRL_LSB_FIRST BIT(5)
#define TDMIN_CTRL_BITNUM_MASK GENMASK(4, 0)
#define TDMIN_CTRL_BITNUM(x) ((x) << 0)
#define TDMIN_SWAP 0x04
#define TDMIN_MASK0 0x08
#define TDMIN_MASK1 0x0c
#define TDMIN_MASK2 0x10
#define TDMIN_MASK3 0x14
#define TDMIN_STAT 0x18
#define TDMIN_MUTE_VAL 0x1c
#define TDMIN_MUTE0 0x20
#define TDMIN_MUTE1 0x24
#define TDMIN_MUTE2 0x28
#define TDMIN_MUTE3 0x2c
static const struct regmap_config axg_tdmin_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TDMIN_MUTE3,
};
static const char * const axg_tdmin_sel_texts[] = {
"IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7",
"IN 8", "IN 9", "IN 10", "IN 11", "IN 12", "IN 13", "IN 14", "IN 15",
};
/* Change to special mux control to reset dapm */
static SOC_ENUM_SINGLE_DECL(axg_tdmin_sel_enum, TDMIN_CTRL,
TDMIN_CTRL_SEL_SHIFT, axg_tdmin_sel_texts);
static const struct snd_kcontrol_new axg_tdmin_in_mux =
SOC_DAPM_ENUM("Input Source", axg_tdmin_sel_enum);
static struct snd_soc_dai *
axg_tdmin_get_be(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dapm_path *p;
struct snd_soc_dai *be;
snd_soc_dapm_widget_for_each_source_path(w, p) {
if (!p->connect)
continue;
if (p->source->id == snd_soc_dapm_dai_out)
return (struct snd_soc_dai *)p->source->priv;
be = axg_tdmin_get_be(p->source);
if (be)
return be;
}
return NULL;
}
static struct axg_tdm_stream *
axg_tdmin_get_tdm_stream(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dai *be = axg_tdmin_get_be(w);
if (!be)
return NULL;
return snd_soc_dai_dma_data_get_capture(be);
}
static void axg_tdmin_enable(struct regmap *map)
{
/* Apply both reset */
regmap_update_bits(map, TDMIN_CTRL,
TDMIN_CTRL_RST_OUT | TDMIN_CTRL_RST_IN, 0);
/* Clear out reset before in reset */
regmap_update_bits(map, TDMIN_CTRL,
TDMIN_CTRL_RST_OUT, TDMIN_CTRL_RST_OUT);
regmap_update_bits(map, TDMIN_CTRL,
TDMIN_CTRL_RST_IN, TDMIN_CTRL_RST_IN);
/* Actually enable tdmin */
regmap_update_bits(map, TDMIN_CTRL,
TDMIN_CTRL_ENABLE, TDMIN_CTRL_ENABLE);
}
static void axg_tdmin_disable(struct regmap *map)
{
regmap_update_bits(map, TDMIN_CTRL, TDMIN_CTRL_ENABLE, 0);
}
static int axg_tdmin_prepare(struct regmap *map,
const struct axg_tdm_formatter_hw *quirks,
struct axg_tdm_stream *ts)
{
unsigned int val, skew = quirks->skew_offset;
/* Set stream skew */
switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_DSP_A:
skew += 1;
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_DSP_B:
break;
default:
pr_err("Unsupported format: %u\n",
ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
val = TDMIN_CTRL_IN_BIT_SKEW(skew);
/* Set stream format mode */
switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
val |= TDMIN_CTRL_I2S_MODE;
break;
}
/* If the sample clock is inverted, invert it back for the formatter */
if (axg_tdm_lrclk_invert(ts->iface->fmt))
val |= TDMIN_CTRL_WS_INV;
/* Set the slot width */
val |= TDMIN_CTRL_BITNUM(ts->iface->slot_width - 1);
/*
* The following also reset LSB_FIRST which result in the formatter
* placing the first bit received at bit 31
*/
regmap_update_bits(map, TDMIN_CTRL,
(TDMIN_CTRL_IN_BIT_SKEW_MASK | TDMIN_CTRL_WS_INV |
TDMIN_CTRL_I2S_MODE | TDMIN_CTRL_LSB_FIRST |
TDMIN_CTRL_BITNUM_MASK), val);
/* Set static swap mask configuration */
regmap_write(map, TDMIN_SWAP, 0x76543210);
return axg_tdm_formatter_set_channel_masks(map, ts, TDMIN_MASK0);
}
static const struct snd_soc_dapm_widget axg_tdmin_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 8", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 9", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 10", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 11", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 12", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 13", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 14", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 15", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_tdmin_in_mux),
SND_SOC_DAPM_PGA_E("DEC", SND_SOC_NOPM, 0, 0, NULL, 0,
axg_tdm_formatter_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_AIF_OUT("OUT", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route axg_tdmin_dapm_routes[] = {
{ "SRC SEL", "IN 0", "IN 0" },
{ "SRC SEL", "IN 1", "IN 1" },
{ "SRC SEL", "IN 2", "IN 2" },
{ "SRC SEL", "IN 3", "IN 3" },
{ "SRC SEL", "IN 4", "IN 4" },
{ "SRC SEL", "IN 5", "IN 5" },
{ "SRC SEL", "IN 6", "IN 6" },
{ "SRC SEL", "IN 7", "IN 7" },
{ "SRC SEL", "IN 8", "IN 8" },
{ "SRC SEL", "IN 9", "IN 9" },
{ "SRC SEL", "IN 10", "IN 10" },
{ "SRC SEL", "IN 11", "IN 11" },
{ "SRC SEL", "IN 12", "IN 12" },
{ "SRC SEL", "IN 13", "IN 13" },
{ "SRC SEL", "IN 14", "IN 14" },
{ "SRC SEL", "IN 15", "IN 15" },
{ "DEC", NULL, "SRC SEL" },
{ "OUT", NULL, "DEC" },
};
static const struct snd_soc_component_driver axg_tdmin_component_drv = {
.dapm_widgets = axg_tdmin_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_tdmin_dapm_widgets),
.dapm_routes = axg_tdmin_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_tdmin_dapm_routes),
};
static const struct axg_tdm_formatter_ops axg_tdmin_ops = {
.get_stream = axg_tdmin_get_tdm_stream,
.prepare = axg_tdmin_prepare,
.enable = axg_tdmin_enable,
.disable = axg_tdmin_disable,
};
static const struct axg_tdm_formatter_driver axg_tdmin_drv = {
.component_drv = &axg_tdmin_component_drv,
.regmap_cfg = &axg_tdmin_regmap_cfg,
.ops = &axg_tdmin_ops,
.quirks = &(const struct axg_tdm_formatter_hw) {
.skew_offset = 3,
},
};
static const struct of_device_id axg_tdmin_of_match[] = {
{
.compatible = "amlogic,axg-tdmin",
.data = &axg_tdmin_drv,
}, {
.compatible = "amlogic,g12a-tdmin",
.data = &axg_tdmin_drv,
}, {
.compatible = "amlogic,sm1-tdmin",
.data = &axg_tdmin_drv,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_tdmin_of_match);
static struct platform_driver axg_tdmin_pdrv = {
.probe = axg_tdm_formatter_probe,
.driver = {
.name = "axg-tdmin",
.of_match_table = axg_tdmin_of_match,
},
};
module_platform_driver(axg_tdmin_pdrv);
MODULE_DESCRIPTION("Amlogic AXG TDM input formatter driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-tdmin.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "aiu-fifo.h"
#define AIU_MEM_START 0x00
#define AIU_MEM_RD 0x04
#define AIU_MEM_END 0x08
#define AIU_MEM_MASKS 0x0c
#define AIU_MEM_MASK_CH_RD GENMASK(7, 0)
#define AIU_MEM_MASK_CH_MEM GENMASK(15, 8)
#define AIU_MEM_CONTROL 0x10
#define AIU_MEM_CONTROL_INIT BIT(0)
#define AIU_MEM_CONTROL_FILL_EN BIT(1)
#define AIU_MEM_CONTROL_EMPTY_EN BIT(2)
static struct snd_soc_dai *aiu_fifo_dai(struct snd_pcm_substream *ss)
{
struct snd_soc_pcm_runtime *rtd = ss->private_data;
return asoc_rtd_to_cpu(rtd, 0);
}
snd_pcm_uframes_t aiu_fifo_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_dai *dai = aiu_fifo_dai(substream);
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned int addr;
addr = snd_soc_component_read(component, fifo->mem_offset + AIU_MEM_RD);
return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
}
static void aiu_fifo_enable(struct snd_soc_dai *dai, bool enable)
{
struct snd_soc_component *component = dai->component;
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
unsigned int en_mask = (AIU_MEM_CONTROL_FILL_EN |
AIU_MEM_CONTROL_EMPTY_EN);
snd_soc_component_update_bits(component,
fifo->mem_offset + AIU_MEM_CONTROL,
en_mask, enable ? en_mask : 0);
}
int aiu_fifo_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
aiu_fifo_enable(dai, true);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
aiu_fifo_enable(dai, false);
break;
default:
return -EINVAL;
}
return 0;
}
int aiu_fifo_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
snd_soc_component_update_bits(component,
fifo->mem_offset + AIU_MEM_CONTROL,
AIU_MEM_CONTROL_INIT,
AIU_MEM_CONTROL_INIT);
snd_soc_component_update_bits(component,
fifo->mem_offset + AIU_MEM_CONTROL,
AIU_MEM_CONTROL_INIT, 0);
return 0;
}
int aiu_fifo_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_component *component = dai->component;
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
dma_addr_t end;
/* Setup the fifo boundaries */
end = runtime->dma_addr + runtime->dma_bytes - fifo->fifo_block;
snd_soc_component_write(component, fifo->mem_offset + AIU_MEM_START,
runtime->dma_addr);
snd_soc_component_write(component, fifo->mem_offset + AIU_MEM_RD,
runtime->dma_addr);
snd_soc_component_write(component, fifo->mem_offset + AIU_MEM_END,
end);
/* Setup the fifo to read all the memory - no skip */
snd_soc_component_update_bits(component,
fifo->mem_offset + AIU_MEM_MASKS,
AIU_MEM_MASK_CH_RD | AIU_MEM_MASK_CH_MEM,
FIELD_PREP(AIU_MEM_MASK_CH_RD, 0xff) |
FIELD_PREP(AIU_MEM_MASK_CH_MEM, 0xff));
return 0;
}
static irqreturn_t aiu_fifo_isr(int irq, void *dev_id)
{
struct snd_pcm_substream *playback = dev_id;
snd_pcm_period_elapsed(playback);
return IRQ_HANDLED;
}
int aiu_fifo_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
int ret;
snd_soc_set_runtime_hwparams(substream, fifo->pcm);
/*
* Make sure the buffer and period size are multiple of the fifo burst
* size
*/
ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
fifo->fifo_block);
if (ret)
return ret;
ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
fifo->fifo_block);
if (ret)
return ret;
ret = clk_prepare_enable(fifo->pclk);
if (ret)
return ret;
ret = request_irq(fifo->irq, aiu_fifo_isr, 0, dev_name(dai->dev),
substream);
if (ret)
clk_disable_unprepare(fifo->pclk);
return ret;
}
void aiu_fifo_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
free_irq(fifo->irq, substream);
clk_disable_unprepare(fifo->pclk);
}
int aiu_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_dai *dai)
{
struct snd_card *card = rtd->card->snd_card;
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
size_t size = fifo->pcm->buffer_bytes_max;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
card->dev, size, size);
return 0;
}
int aiu_fifo_dai_probe(struct snd_soc_dai *dai)
{
struct aiu_fifo *fifo;
fifo = kzalloc(sizeof(*fifo), GFP_KERNEL);
if (!fifo)
return -ENOMEM;
snd_soc_dai_dma_data_set_playback(dai, fifo);
return 0;
}
int aiu_fifo_dai_remove(struct snd_soc_dai *dai)
{
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
kfree(fifo);
return 0;
}
| linux-master | sound/soc/meson/aiu-fifo.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "aiu.h"
#include "aiu-fifo.h"
#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
#define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)
#define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)
#define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)
#define AIU_RST_SOFT_I2S_FAST BIT(0)
#define AIU_I2S_MISC_HOLD_EN BIT(2)
#define AIU_I2S_MISC_FORCE_LEFT_RIGHT BIT(4)
#define AIU_FIFO_I2S_BLOCK 256
static struct snd_pcm_hardware fifo_i2s_pcm = {
.info = (SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE),
.formats = AIU_FORMATS,
.rate_min = 5512,
.rate_max = 192000,
.channels_min = 2,
.channels_max = 8,
.period_bytes_min = AIU_FIFO_I2S_BLOCK,
.period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
.periods_min = 2,
.periods_max = UINT_MAX,
/* No real justification for this */
.buffer_bytes_max = 1 * 1024 * 1024,
};
static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
snd_soc_component_write(component, AIU_RST_SOFT,
AIU_RST_SOFT_I2S_FAST);
snd_soc_component_read(component, AIU_I2S_SYNC);
break;
}
return aiu_fifo_trigger(substream, cmd, dai);
}
static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int ret;
ret = aiu_fifo_prepare(substream, dai);
if (ret)
return ret;
snd_soc_component_update_bits(component,
AIU_MEM_I2S_BUF_CNTL,
AIU_MEM_I2S_BUF_CNTL_INIT,
AIU_MEM_I2S_BUF_CNTL_INIT);
snd_soc_component_update_bits(component,
AIU_MEM_I2S_BUF_CNTL,
AIU_MEM_I2S_BUF_CNTL_INIT, 0);
return 0;
}
static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aiu_fifo *fifo = snd_soc_dai_dma_data_get_playback(dai);
unsigned int val;
int ret;
snd_soc_component_update_bits(component, AIU_I2S_MISC,
AIU_I2S_MISC_HOLD_EN,
AIU_I2S_MISC_HOLD_EN);
ret = aiu_fifo_hw_params(substream, params, dai);
if (ret)
return ret;
switch (params_physical_width(params)) {
case 16:
val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
break;
case 32:
val = 0;
break;
default:
dev_err(dai->dev, "Unsupported physical width %u\n",
params_physical_width(params));
return -EINVAL;
}
snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
AIU_MEM_I2S_CONTROL_MODE_16BIT,
val);
/* Setup the irq periodicity */
val = params_period_bytes(params) / fifo->fifo_block;
val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
/*
* Most (all?) supported SoCs have this bit set by default. The vendor
* driver however sets it manually (depending on the version either
* while un-setting AIU_I2S_MISC_HOLD_EN or right before that). Follow
* the same approach for consistency with the vendor driver.
*/
snd_soc_component_update_bits(component, AIU_I2S_MISC,
AIU_I2S_MISC_FORCE_LEFT_RIGHT,
AIU_I2S_MISC_FORCE_LEFT_RIGHT);
snd_soc_component_update_bits(component, AIU_I2S_MISC,
AIU_I2S_MISC_HOLD_EN, 0);
return 0;
}
const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
.pcm_new = aiu_fifo_pcm_new,
.probe = aiu_fifo_i2s_dai_probe,
.remove = aiu_fifo_dai_remove,
.trigger = aiu_fifo_i2s_trigger,
.prepare = aiu_fifo_i2s_prepare,
.hw_params = aiu_fifo_i2s_hw_params,
.startup = aiu_fifo_startup,
.shutdown = aiu_fifo_shutdown,
};
int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aiu *aiu = snd_soc_component_get_drvdata(component);
struct aiu_fifo *fifo;
int ret;
ret = aiu_fifo_dai_probe(dai);
if (ret)
return ret;
fifo = snd_soc_dai_dma_data_get_playback(dai);
fifo->pcm = &fifo_i2s_pcm;
fifo->mem_offset = AIU_MEM_I2S_START;
fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
fifo->pclk = aiu->i2s.clks[PCLK].clk;
fifo->irq = aiu->i2s.irq;
return 0;
}
| linux-master | sound/soc/meson/aiu-fifo-i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/soc.h>
#include "meson-card.h"
int meson_card_i2s_set_sysclk(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
unsigned int mclk_fs)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
unsigned int mclk;
int ret, i;
if (!mclk_fs)
return 0;
mclk = params_rate(params) * mclk_fs;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP)
return ret;
}
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret && ret != -ENOTSUPP)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(meson_card_i2s_set_sysclk);
int meson_card_reallocate_links(struct snd_soc_card *card,
unsigned int num_links)
{
struct meson_card *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_dai_link *links;
void **ldata;
links = krealloc(priv->card.dai_link,
num_links * sizeof(*priv->card.dai_link),
GFP_KERNEL | __GFP_ZERO);
if (!links)
goto err_links;
ldata = krealloc(priv->link_data,
num_links * sizeof(*priv->link_data),
GFP_KERNEL | __GFP_ZERO);
if (!ldata)
goto err_ldata;
priv->card.dai_link = links;
priv->link_data = ldata;
priv->card.num_links = num_links;
return 0;
err_ldata:
kfree(links);
err_links:
dev_err(priv->card.dev, "failed to allocate links\n");
return -ENOMEM;
}
EXPORT_SYMBOL_GPL(meson_card_reallocate_links);
int meson_card_parse_dai(struct snd_soc_card *card,
struct device_node *node,
struct snd_soc_dai_link_component *dlc)
{
int ret;
if (!dlc || !node)
return -EINVAL;
ret = snd_soc_of_get_dlc(node, NULL, dlc, 0);
if (ret)
return dev_err_probe(card->dev, ret, "can't parse dai\n");
return ret;
}
EXPORT_SYMBOL_GPL(meson_card_parse_dai);
static int meson_card_set_link_name(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node,
const char *prefix)
{
char *name = devm_kasprintf(card->dev, GFP_KERNEL, "%s.%s",
prefix, node->full_name);
if (!name)
return -ENOMEM;
link->name = name;
link->stream_name = name;
return 0;
}
unsigned int meson_card_parse_daifmt(struct device_node *node,
struct device_node *cpu_node)
{
struct device_node *bitclkmaster = NULL;
struct device_node *framemaster = NULL;
unsigned int daifmt;
daifmt = snd_soc_daifmt_parse_format(node, NULL);
snd_soc_daifmt_parse_clock_provider_as_phandle(node, NULL, &bitclkmaster, &framemaster);
/* If no master is provided, default to cpu master */
if (!bitclkmaster || bitclkmaster == cpu_node) {
daifmt |= (!framemaster || framemaster == cpu_node) ?
SND_SOC_DAIFMT_CBS_CFS : SND_SOC_DAIFMT_CBS_CFM;
} else {
daifmt |= (!framemaster || framemaster == cpu_node) ?
SND_SOC_DAIFMT_CBM_CFS : SND_SOC_DAIFMT_CBM_CFM;
}
of_node_put(bitclkmaster);
of_node_put(framemaster);
return daifmt;
}
EXPORT_SYMBOL_GPL(meson_card_parse_daifmt);
int meson_card_set_be_link(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node)
{
struct snd_soc_dai_link_component *codec;
struct device_node *np;
int ret, num_codecs;
num_codecs = of_get_child_count(node);
if (!num_codecs) {
dev_err(card->dev, "be link %s has no codec\n",
node->full_name);
return -EINVAL;
}
codec = devm_kcalloc(card->dev, num_codecs, sizeof(*codec), GFP_KERNEL);
if (!codec)
return -ENOMEM;
link->codecs = codec;
link->num_codecs = num_codecs;
for_each_child_of_node(node, np) {
ret = meson_card_parse_dai(card, np, codec);
if (ret) {
of_node_put(np);
return ret;
}
codec++;
}
ret = meson_card_set_link_name(card, link, node, "be");
if (ret)
dev_err(card->dev, "error setting %pOFn link name\n", np);
return ret;
}
EXPORT_SYMBOL_GPL(meson_card_set_be_link);
int meson_card_set_fe_link(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node,
bool is_playback)
{
link->codecs = &asoc_dummy_dlc;
link->num_codecs = 1;
link->dynamic = 1;
link->dpcm_merged_format = 1;
link->dpcm_merged_chan = 1;
link->dpcm_merged_rate = 1;
if (is_playback)
link->dpcm_playback = 1;
else
link->dpcm_capture = 1;
return meson_card_set_link_name(card, link, node, "fe");
}
EXPORT_SYMBOL_GPL(meson_card_set_fe_link);
static int meson_card_add_links(struct snd_soc_card *card)
{
struct meson_card *priv = snd_soc_card_get_drvdata(card);
struct device_node *node = card->dev->of_node;
struct device_node *np;
int num, i, ret;
num = of_get_child_count(node);
if (!num) {
dev_err(card->dev, "card has no links\n");
return -EINVAL;
}
ret = meson_card_reallocate_links(card, num);
if (ret)
return ret;
i = 0;
for_each_child_of_node(node, np) {
ret = priv->match_data->add_link(card, np, &i);
if (ret) {
of_node_put(np);
return ret;
}
i++;
}
return 0;
}
static int meson_card_parse_of_optional(struct snd_soc_card *card,
const char *propname,
int (*func)(struct snd_soc_card *c,
const char *p))
{
/* If property is not provided, don't fail ... */
if (!of_property_read_bool(card->dev->of_node, propname))
return 0;
/* ... but do fail if it is provided and the parsing fails */
return func(card, propname);
}
static void meson_card_clean_references(struct meson_card *priv)
{
struct snd_soc_card *card = &priv->card;
struct snd_soc_dai_link *link;
struct snd_soc_dai_link_component *codec;
struct snd_soc_aux_dev *aux;
int i, j;
if (card->dai_link) {
for_each_card_prelinks(card, i, link) {
if (link->cpus)
of_node_put(link->cpus->of_node);
for_each_link_codecs(link, j, codec)
of_node_put(codec->of_node);
}
}
if (card->aux_dev) {
for_each_card_pre_auxs(card, i, aux)
of_node_put(aux->dlc.of_node);
}
kfree(card->dai_link);
kfree(priv->link_data);
}
int meson_card_probe(struct platform_device *pdev)
{
const struct meson_card_match_data *data;
struct device *dev = &pdev->dev;
struct meson_card *priv;
int ret;
data = of_device_get_match_data(dev);
if (!data) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
snd_soc_card_set_drvdata(&priv->card, priv);
priv->card.owner = THIS_MODULE;
priv->card.dev = dev;
priv->card.driver_name = dev->driver->name;
priv->match_data = data;
ret = snd_soc_of_parse_card_name(&priv->card, "model");
if (ret < 0)
return ret;
ret = meson_card_parse_of_optional(&priv->card, "audio-routing",
snd_soc_of_parse_audio_routing);
if (ret) {
dev_err(dev, "error while parsing routing\n");
return ret;
}
ret = meson_card_parse_of_optional(&priv->card, "audio-widgets",
snd_soc_of_parse_audio_simple_widgets);
if (ret) {
dev_err(dev, "error while parsing widgets\n");
return ret;
}
ret = meson_card_add_links(&priv->card);
if (ret)
goto out_err;
ret = snd_soc_of_parse_aux_devs(&priv->card, "audio-aux-devs");
if (ret)
goto out_err;
ret = devm_snd_soc_register_card(dev, &priv->card);
if (ret)
goto out_err;
return 0;
out_err:
meson_card_clean_references(priv);
return ret;
}
EXPORT_SYMBOL_GPL(meson_card_probe);
int meson_card_remove(struct platform_device *pdev)
{
struct meson_card *priv = platform_get_drvdata(pdev);
meson_card_clean_references(priv);
return 0;
}
EXPORT_SYMBOL_GPL(meson_card_remove);
MODULE_DESCRIPTION("Amlogic Sound Card Utils");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/meson-card-utils.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include "axg-tdm-formatter.h"
struct axg_tdm_formatter {
struct list_head list;
struct axg_tdm_stream *stream;
const struct axg_tdm_formatter_driver *drv;
struct clk *pclk;
struct clk *sclk;
struct clk *lrclk;
struct clk *sclk_sel;
struct clk *lrclk_sel;
struct reset_control *reset;
bool enabled;
struct regmap *map;
};
int axg_tdm_formatter_set_channel_masks(struct regmap *map,
struct axg_tdm_stream *ts,
unsigned int offset)
{
unsigned int ch = ts->channels;
u32 val[AXG_TDM_NUM_LANES];
int i, j, k;
/*
* We need to mimick the slot distribution used by the HW to keep the
* channel placement consistent regardless of the number of channel
* in the stream. This is why the odd algorithm below is used.
*/
memset(val, 0, sizeof(*val) * AXG_TDM_NUM_LANES);
/*
* Distribute the channels of the stream over the available slots
* of each TDM lane. We need to go over the 32 slots ...
*/
for (i = 0; (i < 32) && ch; i += 2) {
/* ... of all the lanes ... */
for (j = 0; j < AXG_TDM_NUM_LANES; j++) {
/* ... then distribute the channels in pairs */
for (k = 0; k < 2; k++) {
if ((BIT(i + k) & ts->mask[j]) && ch) {
val[j] |= BIT(i + k);
ch -= 1;
}
}
}
}
/*
* If we still have channel left at the end of the process, it means
* the stream has more channels than we can accommodate and we should
* have caught this earlier.
*/
if (WARN_ON(ch != 0)) {
pr_err("channel mask error\n");
return -EINVAL;
}
for (i = 0; i < AXG_TDM_NUM_LANES; i++) {
regmap_write(map, offset, val[i]);
offset += regmap_get_reg_stride(map);
}
return 0;
}
EXPORT_SYMBOL_GPL(axg_tdm_formatter_set_channel_masks);
static int axg_tdm_formatter_enable(struct axg_tdm_formatter *formatter)
{
struct axg_tdm_stream *ts = formatter->stream;
bool invert;
int ret;
/* Do nothing if the formatter is already enabled */
if (formatter->enabled)
return 0;
/*
* On the g12a (and possibly other SoCs), when a stream using
* multiple lanes is restarted, it will sometimes not start
* from the first lane, but randomly from another used one.
* The result is an unexpected and random channel shift.
*
* The hypothesis is that an HW counter is not properly reset
* and the formatter simply starts on the lane it stopped
* before. Unfortunately, there does not seems to be a way to
* reset this through the registers of the block.
*
* However, the g12a has indenpendent reset lines for each audio
* devices. Using this reset before each start solves the issue.
*/
ret = reset_control_reset(formatter->reset);
if (ret)
return ret;
/*
* If sclk is inverted, it means the bit should latched on the
* rising edge which is what our HW expects. If not, we need to
* invert it before the formatter.
*/
invert = axg_tdm_sclk_invert(ts->iface->fmt);
ret = clk_set_phase(formatter->sclk, invert ? 0 : 180);
if (ret)
return ret;
/* Setup the stream parameter in the formatter */
ret = formatter->drv->ops->prepare(formatter->map,
formatter->drv->quirks,
formatter->stream);
if (ret)
return ret;
/* Enable the signal clocks feeding the formatter */
ret = clk_prepare_enable(formatter->sclk);
if (ret)
return ret;
ret = clk_prepare_enable(formatter->lrclk);
if (ret) {
clk_disable_unprepare(formatter->sclk);
return ret;
}
/* Finally, actually enable the formatter */
formatter->drv->ops->enable(formatter->map);
formatter->enabled = true;
return 0;
}
static void axg_tdm_formatter_disable(struct axg_tdm_formatter *formatter)
{
/* Do nothing if the formatter is already disabled */
if (!formatter->enabled)
return;
formatter->drv->ops->disable(formatter->map);
clk_disable_unprepare(formatter->lrclk);
clk_disable_unprepare(formatter->sclk);
formatter->enabled = false;
}
static int axg_tdm_formatter_attach(struct axg_tdm_formatter *formatter)
{
struct axg_tdm_stream *ts = formatter->stream;
int ret = 0;
mutex_lock(&ts->lock);
/* Catch up if the stream is already running when we attach */
if (ts->ready) {
ret = axg_tdm_formatter_enable(formatter);
if (ret) {
pr_err("failed to enable formatter\n");
goto out;
}
}
list_add_tail(&formatter->list, &ts->formatter_list);
out:
mutex_unlock(&ts->lock);
return ret;
}
static void axg_tdm_formatter_dettach(struct axg_tdm_formatter *formatter)
{
struct axg_tdm_stream *ts = formatter->stream;
mutex_lock(&ts->lock);
list_del(&formatter->list);
mutex_unlock(&ts->lock);
axg_tdm_formatter_disable(formatter);
}
static int axg_tdm_formatter_power_up(struct axg_tdm_formatter *formatter,
struct snd_soc_dapm_widget *w)
{
struct axg_tdm_stream *ts = formatter->drv->ops->get_stream(w);
int ret;
/*
* If we don't get a stream at this stage, it would mean that the
* widget is powering up but is not attached to any backend DAI.
* It should not happen, ever !
*/
if (WARN_ON(!ts))
return -ENODEV;
/* Clock our device */
ret = clk_prepare_enable(formatter->pclk);
if (ret)
return ret;
/* Reparent the bit clock to the TDM interface */
ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk);
if (ret)
goto disable_pclk;
/* Reparent the sample clock to the TDM interface */
ret = clk_set_parent(formatter->lrclk_sel, ts->iface->lrclk);
if (ret)
goto disable_pclk;
formatter->stream = ts;
ret = axg_tdm_formatter_attach(formatter);
if (ret)
goto disable_pclk;
return 0;
disable_pclk:
clk_disable_unprepare(formatter->pclk);
return ret;
}
static void axg_tdm_formatter_power_down(struct axg_tdm_formatter *formatter)
{
axg_tdm_formatter_dettach(formatter);
clk_disable_unprepare(formatter->pclk);
formatter->stream = NULL;
}
int axg_tdm_formatter_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *control,
int event)
{
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
struct axg_tdm_formatter *formatter = snd_soc_component_get_drvdata(c);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = axg_tdm_formatter_power_up(formatter, w);
break;
case SND_SOC_DAPM_PRE_PMD:
axg_tdm_formatter_power_down(formatter);
break;
default:
dev_err(c->dev, "Unexpected event %d\n", event);
return -EINVAL;
}
return ret;
}
EXPORT_SYMBOL_GPL(axg_tdm_formatter_event);
int axg_tdm_formatter_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct axg_tdm_formatter_driver *drv;
struct axg_tdm_formatter *formatter;
void __iomem *regs;
drv = of_device_get_match_data(dev);
if (!drv) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
formatter = devm_kzalloc(dev, sizeof(*formatter), GFP_KERNEL);
if (!formatter)
return -ENOMEM;
platform_set_drvdata(pdev, formatter);
formatter->drv = drv;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
formatter->map = devm_regmap_init_mmio(dev, regs, drv->regmap_cfg);
if (IS_ERR(formatter->map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(formatter->map));
return PTR_ERR(formatter->map);
}
/* Peripharal clock */
formatter->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(formatter->pclk))
return dev_err_probe(dev, PTR_ERR(formatter->pclk), "failed to get pclk\n");
/* Formatter bit clock */
formatter->sclk = devm_clk_get(dev, "sclk");
if (IS_ERR(formatter->sclk))
return dev_err_probe(dev, PTR_ERR(formatter->sclk), "failed to get sclk\n");
/* Formatter sample clock */
formatter->lrclk = devm_clk_get(dev, "lrclk");
if (IS_ERR(formatter->lrclk))
return dev_err_probe(dev, PTR_ERR(formatter->lrclk), "failed to get lrclk\n");
/* Formatter bit clock input multiplexer */
formatter->sclk_sel = devm_clk_get(dev, "sclk_sel");
if (IS_ERR(formatter->sclk_sel))
return dev_err_probe(dev, PTR_ERR(formatter->sclk_sel), "failed to get sclk_sel\n");
/* Formatter sample clock input multiplexer */
formatter->lrclk_sel = devm_clk_get(dev, "lrclk_sel");
if (IS_ERR(formatter->lrclk_sel))
return dev_err_probe(dev, PTR_ERR(formatter->lrclk_sel),
"failed to get lrclk_sel\n");
/* Formatter dedicated reset line */
formatter->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(formatter->reset))
return dev_err_probe(dev, PTR_ERR(formatter->reset), "failed to get reset\n");
return devm_snd_soc_register_component(dev, drv->component_drv,
NULL, 0);
}
EXPORT_SYMBOL_GPL(axg_tdm_formatter_probe);
int axg_tdm_stream_start(struct axg_tdm_stream *ts)
{
struct axg_tdm_formatter *formatter;
int ret = 0;
mutex_lock(&ts->lock);
ts->ready = true;
/* Start all the formatters attached to the stream */
list_for_each_entry(formatter, &ts->formatter_list, list) {
ret = axg_tdm_formatter_enable(formatter);
if (ret) {
pr_err("failed to start tdm stream\n");
goto out;
}
}
out:
mutex_unlock(&ts->lock);
return ret;
}
EXPORT_SYMBOL_GPL(axg_tdm_stream_start);
void axg_tdm_stream_stop(struct axg_tdm_stream *ts)
{
struct axg_tdm_formatter *formatter;
mutex_lock(&ts->lock);
ts->ready = false;
/* Stop all the formatters attached to the stream */
list_for_each_entry(formatter, &ts->formatter_list, list) {
axg_tdm_formatter_disable(formatter);
}
mutex_unlock(&ts->lock);
}
EXPORT_SYMBOL_GPL(axg_tdm_stream_stop);
struct axg_tdm_stream *axg_tdm_stream_alloc(struct axg_tdm_iface *iface)
{
struct axg_tdm_stream *ts;
ts = kzalloc(sizeof(*ts), GFP_KERNEL);
if (ts) {
INIT_LIST_HEAD(&ts->formatter_list);
mutex_init(&ts->lock);
ts->iface = iface;
}
return ts;
}
EXPORT_SYMBOL_GPL(axg_tdm_stream_alloc);
void axg_tdm_stream_free(struct axg_tdm_stream *ts)
{
/*
* If the list is not empty, it would mean that one of the formatter
* widget is still powered and attached to the interface while we
* are removing the TDM DAI. It should not be possible
*/
WARN_ON(!list_empty(&ts->formatter_list));
mutex_destroy(&ts->lock);
kfree(ts);
}
EXPORT_SYMBOL_GPL(axg_tdm_stream_free);
MODULE_DESCRIPTION("Amlogic AXG TDM formatter driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-tdm-formatter.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2019 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "meson-codec-glue.h"
static struct snd_soc_dapm_widget *
meson_codec_glue_get_input(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dapm_path *p;
struct snd_soc_dapm_widget *in;
snd_soc_dapm_widget_for_each_source_path(w, p) {
if (!p->connect)
continue;
/* Check that we still are in the same component */
if (snd_soc_dapm_to_component(w->dapm) !=
snd_soc_dapm_to_component(p->source->dapm))
continue;
if (p->source->id == snd_soc_dapm_dai_in)
return p->source;
in = meson_codec_glue_get_input(p->source);
if (in)
return in;
}
return NULL;
}
static void meson_codec_glue_input_set_data(struct snd_soc_dai *dai,
struct meson_codec_glue_input *data)
{
snd_soc_dai_dma_data_set_playback(dai, data);
}
struct meson_codec_glue_input *
meson_codec_glue_input_get_data(struct snd_soc_dai *dai)
{
return snd_soc_dai_dma_data_get_playback(dai);
}
EXPORT_SYMBOL_GPL(meson_codec_glue_input_get_data);
static struct meson_codec_glue_input *
meson_codec_glue_output_get_input_data(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dapm_widget *in =
meson_codec_glue_get_input(w);
struct snd_soc_dai *dai;
if (WARN_ON(!in))
return NULL;
dai = in->priv;
return meson_codec_glue_input_get_data(dai);
}
int meson_codec_glue_input_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct meson_codec_glue_input *data =
meson_codec_glue_input_get_data(dai);
data->params.rates = snd_pcm_rate_to_rate_bit(params_rate(params));
data->params.rate_min = params_rate(params);
data->params.rate_max = params_rate(params);
data->params.formats = 1ULL << (__force int) params_format(params);
data->params.channels_min = params_channels(params);
data->params.channels_max = params_channels(params);
data->params.sig_bits = dai->driver->playback.sig_bits;
return 0;
}
EXPORT_SYMBOL_GPL(meson_codec_glue_input_hw_params);
int meson_codec_glue_input_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct meson_codec_glue_input *data =
meson_codec_glue_input_get_data(dai);
/* Save the source stream format for the downstream link */
data->fmt = fmt;
return 0;
}
EXPORT_SYMBOL_GPL(meson_codec_glue_input_set_fmt);
int meson_codec_glue_output_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget_capture(dai);
struct meson_codec_glue_input *in_data = meson_codec_glue_output_get_input_data(w);
if (!in_data)
return -ENODEV;
if (WARN_ON(!rtd->dai_link->c2c_params)) {
dev_warn(dai->dev, "codec2codec link expected\n");
return -EINVAL;
}
/* Replace link params with the input params */
rtd->dai_link->c2c_params = &in_data->params;
rtd->dai_link->num_c2c_params = 1;
return snd_soc_runtime_set_dai_fmt(rtd, in_data->fmt);
}
EXPORT_SYMBOL_GPL(meson_codec_glue_output_startup);
int meson_codec_glue_input_dai_probe(struct snd_soc_dai *dai)
{
struct meson_codec_glue_input *data;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
meson_codec_glue_input_set_data(dai, data);
return 0;
}
EXPORT_SYMBOL_GPL(meson_codec_glue_input_dai_probe);
int meson_codec_glue_input_dai_remove(struct snd_soc_dai *dai)
{
struct meson_codec_glue_input *data =
meson_codec_glue_input_get_data(dai);
kfree(data);
return 0;
}
EXPORT_SYMBOL_GPL(meson_codec_glue_input_dai_remove);
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_DESCRIPTION("Amlogic Codec Glue Helpers");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/meson-codec-glue.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#define BLOCK_EN 0x00
#define LORN_EN 0
#define LORP_EN 1
#define LOLN_EN 2
#define LOLP_EN 3
#define DACR_EN 4
#define DACL_EN 5
#define DACR_INV 20
#define DACL_INV 21
#define DACR_SRC 22
#define DACL_SRC 23
#define REFP_BUF_EN BIT(12)
#define BIAS_CURRENT_EN BIT(13)
#define VMID_GEN_FAST BIT(14)
#define VMID_GEN_EN BIT(15)
#define I2S_MODE BIT(30)
#define VOL_CTRL0 0x04
#define GAIN_H 31
#define GAIN_L 23
#define VOL_CTRL1 0x08
#define DAC_MONO 8
#define RAMP_RATE 10
#define VC_RAMP_MODE 12
#define MUTE_MODE 13
#define UNMUTE_MODE 14
#define DAC_SOFT_MUTE 15
#define DACR_VC 16
#define DACL_VC 24
#define LINEOUT_CFG 0x0c
#define LORN_POL 0
#define LORP_POL 4
#define LOLN_POL 8
#define LOLP_POL 12
#define POWER_CFG 0x10
struct t9015 {
struct clk *pclk;
struct regulator *avdd;
};
static int t9015_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
unsigned int val;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
val = I2S_MODE;
break;
case SND_SOC_DAIFMT_CBS_CFS:
val = 0;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, BLOCK_EN, I2S_MODE, val);
if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S) &&
((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_LEFT_J))
return -EINVAL;
return 0;
}
static const struct snd_soc_dai_ops t9015_dai_ops = {
.set_fmt = t9015_dai_set_fmt,
};
static struct snd_soc_dai_driver t9015_dai = {
.name = "t9015-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = (SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_LE |
SNDRV_PCM_FMTBIT_S24_LE),
},
.ops = &t9015_dai_ops,
};
static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -9525, 0);
static const char * const ramp_rate_txt[] = { "Fast", "Slow" };
static SOC_ENUM_SINGLE_DECL(ramp_rate_enum, VOL_CTRL1, RAMP_RATE,
ramp_rate_txt);
static const char * const dacr_in_txt[] = { "Right", "Left" };
static SOC_ENUM_SINGLE_DECL(dacr_in_enum, BLOCK_EN, DACR_SRC, dacr_in_txt);
static const char * const dacl_in_txt[] = { "Left", "Right" };
static SOC_ENUM_SINGLE_DECL(dacl_in_enum, BLOCK_EN, DACL_SRC, dacl_in_txt);
static const char * const mono_txt[] = { "Stereo", "Mono"};
static SOC_ENUM_SINGLE_DECL(mono_enum, VOL_CTRL1, DAC_MONO, mono_txt);
static const struct snd_kcontrol_new t9015_snd_controls[] = {
/* Volume Controls */
SOC_ENUM("Playback Channel Mode", mono_enum),
SOC_SINGLE("Playback Switch", VOL_CTRL1, DAC_SOFT_MUTE, 1, 1),
SOC_DOUBLE_TLV("Playback Volume", VOL_CTRL1, DACL_VC, DACR_VC,
0xff, 0, dac_vol_tlv),
/* Ramp Controls */
SOC_ENUM("Ramp Rate", ramp_rate_enum),
SOC_SINGLE("Volume Ramp Switch", VOL_CTRL1, VC_RAMP_MODE, 1, 0),
SOC_SINGLE("Mute Ramp Switch", VOL_CTRL1, MUTE_MODE, 1, 0),
SOC_SINGLE("Unmute Ramp Switch", VOL_CTRL1, UNMUTE_MODE, 1, 0),
};
static const struct snd_kcontrol_new t9015_right_dac_mux =
SOC_DAPM_ENUM("Right DAC Source", dacr_in_enum);
static const struct snd_kcontrol_new t9015_left_dac_mux =
SOC_DAPM_ENUM("Left DAC Source", dacl_in_enum);
static const struct snd_soc_dapm_widget t9015_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("Right IN", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Left IN", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("Right DAC Sel", SND_SOC_NOPM, 0, 0,
&t9015_right_dac_mux),
SND_SOC_DAPM_MUX("Left DAC Sel", SND_SOC_NOPM, 0, 0,
&t9015_left_dac_mux),
SND_SOC_DAPM_DAC("Right DAC", NULL, BLOCK_EN, DACR_EN, 0),
SND_SOC_DAPM_DAC("Left DAC", NULL, BLOCK_EN, DACL_EN, 0),
SND_SOC_DAPM_OUT_DRV("Right- Driver", BLOCK_EN, LORN_EN, 0,
NULL, 0),
SND_SOC_DAPM_OUT_DRV("Right+ Driver", BLOCK_EN, LORP_EN, 0,
NULL, 0),
SND_SOC_DAPM_OUT_DRV("Left- Driver", BLOCK_EN, LOLN_EN, 0,
NULL, 0),
SND_SOC_DAPM_OUT_DRV("Left+ Driver", BLOCK_EN, LOLP_EN, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("LORN"),
SND_SOC_DAPM_OUTPUT("LORP"),
SND_SOC_DAPM_OUTPUT("LOLN"),
SND_SOC_DAPM_OUTPUT("LOLP"),
};
static const struct snd_soc_dapm_route t9015_dapm_routes[] = {
{ "Right IN", NULL, "Playback" },
{ "Left IN", NULL, "Playback" },
{ "Right DAC Sel", "Right", "Right IN" },
{ "Right DAC Sel", "Left", "Left IN" },
{ "Left DAC Sel", "Right", "Right IN" },
{ "Left DAC Sel", "Left", "Left IN" },
{ "Right DAC", NULL, "Right DAC Sel" },
{ "Left DAC", NULL, "Left DAC Sel" },
{ "Right- Driver", NULL, "Right DAC" },
{ "Right+ Driver", NULL, "Right DAC" },
{ "Left- Driver", NULL, "Left DAC" },
{ "Left+ Driver", NULL, "Left DAC" },
{ "LORN", NULL, "Right- Driver", },
{ "LORP", NULL, "Right+ Driver", },
{ "LOLN", NULL, "Left- Driver", },
{ "LOLP", NULL, "Left+ Driver", },
};
static int t9015_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct t9015 *priv = snd_soc_component_get_drvdata(component);
enum snd_soc_bias_level now =
snd_soc_component_get_bias_level(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_component_update_bits(component, BLOCK_EN,
BIAS_CURRENT_EN,
BIAS_CURRENT_EN);
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_component_update_bits(component, BLOCK_EN,
BIAS_CURRENT_EN,
0);
break;
case SND_SOC_BIAS_STANDBY:
ret = regulator_enable(priv->avdd);
if (ret) {
dev_err(component->dev, "AVDD enable failed\n");
return ret;
}
if (now == SND_SOC_BIAS_OFF) {
snd_soc_component_update_bits(component, BLOCK_EN,
VMID_GEN_EN | VMID_GEN_FAST | REFP_BUF_EN,
VMID_GEN_EN | VMID_GEN_FAST | REFP_BUF_EN);
mdelay(200);
snd_soc_component_update_bits(component, BLOCK_EN,
VMID_GEN_FAST,
0);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_component_update_bits(component, BLOCK_EN,
VMID_GEN_EN | VMID_GEN_FAST | REFP_BUF_EN,
0);
regulator_disable(priv->avdd);
break;
}
return 0;
}
static const struct snd_soc_component_driver t9015_codec_driver = {
.set_bias_level = t9015_set_bias_level,
.controls = t9015_snd_controls,
.num_controls = ARRAY_SIZE(t9015_snd_controls),
.dapm_widgets = t9015_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(t9015_dapm_widgets),
.dapm_routes = t9015_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(t9015_dapm_routes),
.suspend_bias_off = 1,
.endianness = 1,
};
static const struct regmap_config t9015_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = POWER_CFG,
};
static int t9015_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct t9015 *priv;
void __iomem *regs;
struct regmap *regmap;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(priv->pclk))
return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get core clock\n");
priv->avdd = devm_regulator_get(dev, "AVDD");
if (IS_ERR(priv->avdd))
return dev_err_probe(dev, PTR_ERR(priv->avdd), "failed to AVDD\n");
ret = clk_prepare_enable(priv->pclk);
if (ret) {
dev_err(dev, "core clock enable failed\n");
return ret;
}
ret = devm_add_action_or_reset(dev,
(void(*)(void *))clk_disable_unprepare,
priv->pclk);
if (ret)
return ret;
ret = device_reset(dev);
if (ret) {
dev_err(dev, "reset failed\n");
return ret;
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs)) {
dev_err(dev, "register map failed\n");
return PTR_ERR(regs);
}
regmap = devm_regmap_init_mmio(dev, regs, &t9015_regmap_config);
if (IS_ERR(regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(regmap);
}
/*
* Initialize output polarity:
* ATM the output polarity is fixed but in the future it might useful
* to add DT property to set this depending on the platform needs
*/
regmap_write(regmap, LINEOUT_CFG, 0x1111);
return devm_snd_soc_register_component(dev, &t9015_codec_driver,
&t9015_dai, 1);
}
static const struct of_device_id t9015_ids[] __maybe_unused = {
{ .compatible = "amlogic,t9015", },
{ }
};
MODULE_DEVICE_TABLE(of, t9015_ids);
static struct platform_driver t9015_driver = {
.driver = {
.name = "t9015-codec",
.of_match_table = of_match_ptr(t9015_ids),
},
.probe = t9015_probe,
};
module_platform_driver(t9015_driver);
MODULE_DESCRIPTION("ASoC Amlogic T9015 codec driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/meson/t9015.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-tdm-formatter.h"
#define TDMOUT_CTRL0 0x00
#define TDMOUT_CTRL0_BITNUM_MASK GENMASK(4, 0)
#define TDMOUT_CTRL0_BITNUM(x) ((x) << 0)
#define TDMOUT_CTRL0_SLOTNUM_MASK GENMASK(9, 5)
#define TDMOUT_CTRL0_SLOTNUM(x) ((x) << 5)
#define TDMOUT_CTRL0_INIT_BITNUM_MASK GENMASK(19, 15)
#define TDMOUT_CTRL0_INIT_BITNUM(x) ((x) << 15)
#define TDMOUT_CTRL0_ENABLE BIT(31)
#define TDMOUT_CTRL0_RST_OUT BIT(29)
#define TDMOUT_CTRL0_RST_IN BIT(28)
#define TDMOUT_CTRL1 0x04
#define TDMOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
#define TDMOUT_CTRL1_TYPE(x) ((x) << 4)
#define SM1_TDMOUT_CTRL1_GAIN_EN 7
#define TDMOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)
#define TDMOUT_CTRL1_MSB_POS(x) ((x) << 8)
#define TDMOUT_CTRL1_SEL_SHIFT 24
#define TDMOUT_CTRL1_GAIN_EN 26
#define TDMOUT_CTRL1_WS_INV BIT(28)
#define TDMOUT_SWAP 0x08
#define TDMOUT_MASK0 0x0c
#define TDMOUT_MASK1 0x10
#define TDMOUT_MASK2 0x14
#define TDMOUT_MASK3 0x18
#define TDMOUT_STAT 0x1c
#define TDMOUT_GAIN0 0x20
#define TDMOUT_GAIN1 0x24
#define TDMOUT_MUTE_VAL 0x28
#define TDMOUT_MUTE0 0x2c
#define TDMOUT_MUTE1 0x30
#define TDMOUT_MUTE2 0x34
#define TDMOUT_MUTE3 0x38
#define TDMOUT_MASK_VAL 0x3c
static const struct regmap_config axg_tdmout_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TDMOUT_MASK_VAL,
};
static struct snd_soc_dai *
axg_tdmout_get_be(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dapm_path *p;
struct snd_soc_dai *be;
snd_soc_dapm_widget_for_each_sink_path(w, p) {
if (!p->connect)
continue;
if (p->sink->id == snd_soc_dapm_dai_in)
return (struct snd_soc_dai *)p->sink->priv;
be = axg_tdmout_get_be(p->sink);
if (be)
return be;
}
return NULL;
}
static struct axg_tdm_stream *
axg_tdmout_get_tdm_stream(struct snd_soc_dapm_widget *w)
{
struct snd_soc_dai *be = axg_tdmout_get_be(w);
if (!be)
return NULL;
return snd_soc_dai_dma_data_get_playback(be);
}
static void axg_tdmout_enable(struct regmap *map)
{
/* Apply both reset */
regmap_update_bits(map, TDMOUT_CTRL0,
TDMOUT_CTRL0_RST_OUT | TDMOUT_CTRL0_RST_IN, 0);
/* Clear out reset before in reset */
regmap_update_bits(map, TDMOUT_CTRL0,
TDMOUT_CTRL0_RST_OUT, TDMOUT_CTRL0_RST_OUT);
regmap_update_bits(map, TDMOUT_CTRL0,
TDMOUT_CTRL0_RST_IN, TDMOUT_CTRL0_RST_IN);
/* Actually enable tdmout */
regmap_update_bits(map, TDMOUT_CTRL0,
TDMOUT_CTRL0_ENABLE, TDMOUT_CTRL0_ENABLE);
}
static void axg_tdmout_disable(struct regmap *map)
{
regmap_update_bits(map, TDMOUT_CTRL0, TDMOUT_CTRL0_ENABLE, 0);
}
static int axg_tdmout_prepare(struct regmap *map,
const struct axg_tdm_formatter_hw *quirks,
struct axg_tdm_stream *ts)
{
unsigned int val, skew = quirks->skew_offset;
/* Set the stream skew */
switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_DSP_A:
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_DSP_B:
skew += 1;
break;
default:
pr_err("Unsupported format: %u\n",
ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
val = TDMOUT_CTRL0_INIT_BITNUM(skew);
/* Set the slot width */
val |= TDMOUT_CTRL0_BITNUM(ts->iface->slot_width - 1);
/* Set the slot number */
val |= TDMOUT_CTRL0_SLOTNUM(ts->iface->slots - 1);
regmap_update_bits(map, TDMOUT_CTRL0,
TDMOUT_CTRL0_INIT_BITNUM_MASK |
TDMOUT_CTRL0_BITNUM_MASK |
TDMOUT_CTRL0_SLOTNUM_MASK, val);
/* Set the sample width */
val = TDMOUT_CTRL1_MSB_POS(ts->width - 1);
/* FIFO data are arranged in chunks of 64bits */
switch (ts->physical_width) {
case 8:
/* 8 samples of 8 bits */
val |= TDMOUT_CTRL1_TYPE(0);
break;
case 16:
/* 4 samples of 16 bits - right justified */
val |= TDMOUT_CTRL1_TYPE(2);
break;
case 32:
/* 2 samples of 32 bits - right justified */
val |= TDMOUT_CTRL1_TYPE(4);
break;
default:
pr_err("Unsupported physical width: %u\n",
ts->physical_width);
return -EINVAL;
}
/* If the sample clock is inverted, invert it back for the formatter */
if (axg_tdm_lrclk_invert(ts->iface->fmt))
val |= TDMOUT_CTRL1_WS_INV;
regmap_update_bits(map, TDMOUT_CTRL1,
(TDMOUT_CTRL1_TYPE_MASK | TDMOUT_CTRL1_MSB_POS_MASK |
TDMOUT_CTRL1_WS_INV), val);
/* Set static swap mask configuration */
regmap_write(map, TDMOUT_SWAP, 0x76543210);
return axg_tdm_formatter_set_channel_masks(map, ts, TDMOUT_MASK0);
}
static const struct snd_kcontrol_new axg_tdmout_controls[] = {
SOC_DOUBLE("Lane 0 Volume", TDMOUT_GAIN0, 0, 8, 255, 0),
SOC_DOUBLE("Lane 1 Volume", TDMOUT_GAIN0, 16, 24, 255, 0),
SOC_DOUBLE("Lane 2 Volume", TDMOUT_GAIN1, 0, 8, 255, 0),
SOC_DOUBLE("Lane 3 Volume", TDMOUT_GAIN1, 16, 24, 255, 0),
SOC_SINGLE("Gain Enable Switch", TDMOUT_CTRL1,
TDMOUT_CTRL1_GAIN_EN, 1, 0),
};
static const char * const axg_tdmout_sel_texts[] = {
"IN 0", "IN 1", "IN 2",
};
static SOC_ENUM_SINGLE_DECL(axg_tdmout_sel_enum, TDMOUT_CTRL1,
TDMOUT_CTRL1_SEL_SHIFT, axg_tdmout_sel_texts);
static const struct snd_kcontrol_new axg_tdmout_in_mux =
SOC_DAPM_ENUM("Input Source", axg_tdmout_sel_enum);
static const struct snd_soc_dapm_widget axg_tdmout_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_tdmout_in_mux),
SND_SOC_DAPM_PGA_E("ENC", SND_SOC_NOPM, 0, 0, NULL, 0,
axg_tdm_formatter_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_AIF_OUT("OUT", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route axg_tdmout_dapm_routes[] = {
{ "SRC SEL", "IN 0", "IN 0" },
{ "SRC SEL", "IN 1", "IN 1" },
{ "SRC SEL", "IN 2", "IN 2" },
{ "ENC", NULL, "SRC SEL" },
{ "OUT", NULL, "ENC" },
};
static const struct snd_soc_component_driver axg_tdmout_component_drv = {
.controls = axg_tdmout_controls,
.num_controls = ARRAY_SIZE(axg_tdmout_controls),
.dapm_widgets = axg_tdmout_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(axg_tdmout_dapm_widgets),
.dapm_routes = axg_tdmout_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(axg_tdmout_dapm_routes),
};
static const struct axg_tdm_formatter_ops axg_tdmout_ops = {
.get_stream = axg_tdmout_get_tdm_stream,
.prepare = axg_tdmout_prepare,
.enable = axg_tdmout_enable,
.disable = axg_tdmout_disable,
};
static const struct axg_tdm_formatter_driver axg_tdmout_drv = {
.component_drv = &axg_tdmout_component_drv,
.regmap_cfg = &axg_tdmout_regmap_cfg,
.ops = &axg_tdmout_ops,
.quirks = &(const struct axg_tdm_formatter_hw) {
.skew_offset = 1,
},
};
static const struct axg_tdm_formatter_driver g12a_tdmout_drv = {
.component_drv = &axg_tdmout_component_drv,
.regmap_cfg = &axg_tdmout_regmap_cfg,
.ops = &axg_tdmout_ops,
.quirks = &(const struct axg_tdm_formatter_hw) {
.skew_offset = 2,
},
};
static const struct snd_kcontrol_new sm1_tdmout_controls[] = {
SOC_DOUBLE("Lane 0 Volume", TDMOUT_GAIN0, 0, 8, 255, 0),
SOC_DOUBLE("Lane 1 Volume", TDMOUT_GAIN0, 16, 24, 255, 0),
SOC_DOUBLE("Lane 2 Volume", TDMOUT_GAIN1, 0, 8, 255, 0),
SOC_DOUBLE("Lane 3 Volume", TDMOUT_GAIN1, 16, 24, 255, 0),
SOC_SINGLE("Gain Enable Switch", TDMOUT_CTRL1,
SM1_TDMOUT_CTRL1_GAIN_EN, 1, 0),
};
static const char * const sm1_tdmout_sel_texts[] = {
"IN 0", "IN 1", "IN 2", "IN 3", "IN 4",
};
static SOC_ENUM_SINGLE_DECL(sm1_tdmout_sel_enum, TDMOUT_CTRL1,
TDMOUT_CTRL1_SEL_SHIFT, sm1_tdmout_sel_texts);
static const struct snd_kcontrol_new sm1_tdmout_in_mux =
SOC_DAPM_ENUM("Input Source", sm1_tdmout_sel_enum);
static const struct snd_soc_dapm_widget sm1_tdmout_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &sm1_tdmout_in_mux),
SND_SOC_DAPM_PGA_E("ENC", SND_SOC_NOPM, 0, 0, NULL, 0,
axg_tdm_formatter_event,
(SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD)),
SND_SOC_DAPM_AIF_OUT("OUT", NULL, 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route sm1_tdmout_dapm_routes[] = {
{ "SRC SEL", "IN 0", "IN 0" },
{ "SRC SEL", "IN 1", "IN 1" },
{ "SRC SEL", "IN 2", "IN 2" },
{ "SRC SEL", "IN 3", "IN 3" },
{ "SRC SEL", "IN 4", "IN 4" },
{ "ENC", NULL, "SRC SEL" },
{ "OUT", NULL, "ENC" },
};
static const struct snd_soc_component_driver sm1_tdmout_component_drv = {
.controls = sm1_tdmout_controls,
.num_controls = ARRAY_SIZE(sm1_tdmout_controls),
.dapm_widgets = sm1_tdmout_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sm1_tdmout_dapm_widgets),
.dapm_routes = sm1_tdmout_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sm1_tdmout_dapm_routes),
};
static const struct axg_tdm_formatter_driver sm1_tdmout_drv = {
.component_drv = &sm1_tdmout_component_drv,
.regmap_cfg = &axg_tdmout_regmap_cfg,
.ops = &axg_tdmout_ops,
.quirks = &(const struct axg_tdm_formatter_hw) {
.skew_offset = 2,
},
};
static const struct of_device_id axg_tdmout_of_match[] = {
{
.compatible = "amlogic,axg-tdmout",
.data = &axg_tdmout_drv,
}, {
.compatible = "amlogic,g12a-tdmout",
.data = &g12a_tdmout_drv,
}, {
.compatible = "amlogic,sm1-tdmout",
.data = &sm1_tdmout_drv,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_tdmout_of_match);
static struct platform_driver axg_tdmout_pdrv = {
.probe = axg_tdm_formatter_probe,
.driver = {
.name = "axg-tdmout",
.of_match_table = axg_tdmout_of_match,
},
};
module_platform_driver(axg_tdmout_pdrv);
MODULE_DESCRIPTION("Amlogic AXG TDM output formatter driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-tdmout.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/pcm_params.h>
#define PDM_CTRL 0x00
#define PDM_CTRL_EN BIT(31)
#define PDM_CTRL_OUT_MODE BIT(29)
#define PDM_CTRL_BYPASS_MODE BIT(28)
#define PDM_CTRL_RST_FIFO BIT(16)
#define PDM_CTRL_CHAN_RSTN_MASK GENMASK(15, 8)
#define PDM_CTRL_CHAN_RSTN(x) ((x) << 8)
#define PDM_CTRL_CHAN_EN_MASK GENMASK(7, 0)
#define PDM_CTRL_CHAN_EN(x) ((x) << 0)
#define PDM_HCIC_CTRL1 0x04
#define PDM_FILTER_EN BIT(31)
#define PDM_HCIC_CTRL1_GAIN_SFT_MASK GENMASK(29, 24)
#define PDM_HCIC_CTRL1_GAIN_SFT(x) ((x) << 24)
#define PDM_HCIC_CTRL1_GAIN_MULT_MASK GENMASK(23, 16)
#define PDM_HCIC_CTRL1_GAIN_MULT(x) ((x) << 16)
#define PDM_HCIC_CTRL1_DSR_MASK GENMASK(8, 4)
#define PDM_HCIC_CTRL1_DSR(x) ((x) << 4)
#define PDM_HCIC_CTRL1_STAGE_NUM_MASK GENMASK(3, 0)
#define PDM_HCIC_CTRL1_STAGE_NUM(x) ((x) << 0)
#define PDM_HCIC_CTRL2 0x08
#define PDM_F1_CTRL 0x0c
#define PDM_LPF_ROUND_MODE_MASK GENMASK(17, 16)
#define PDM_LPF_ROUND_MODE(x) ((x) << 16)
#define PDM_LPF_DSR_MASK GENMASK(15, 12)
#define PDM_LPF_DSR(x) ((x) << 12)
#define PDM_LPF_STAGE_NUM_MASK GENMASK(8, 0)
#define PDM_LPF_STAGE_NUM(x) ((x) << 0)
#define PDM_LPF_MAX_STAGE 336
#define PDM_LPF_NUM 3
#define PDM_F2_CTRL 0x10
#define PDM_F3_CTRL 0x14
#define PDM_HPF_CTRL 0x18
#define PDM_HPF_SFT_STEPS_MASK GENMASK(20, 16)
#define PDM_HPF_SFT_STEPS(x) ((x) << 16)
#define PDM_HPF_OUT_FACTOR_MASK GENMASK(15, 0)
#define PDM_HPF_OUT_FACTOR(x) ((x) << 0)
#define PDM_CHAN_CTRL 0x1c
#define PDM_CHAN_CTRL_POINTER_WIDTH 8
#define PDM_CHAN_CTRL_POINTER_MAX ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1)
#define PDM_CHAN_CTRL_NUM 4
#define PDM_CHAN_CTRL1 0x20
#define PDM_COEFF_ADDR 0x24
#define PDM_COEFF_DATA 0x28
#define PDM_CLKG_CTRL 0x2c
#define PDM_STS 0x30
struct axg_pdm_lpf {
unsigned int ds;
unsigned int round_mode;
const unsigned int *tap;
unsigned int tap_num;
};
struct axg_pdm_hcic {
unsigned int shift;
unsigned int mult;
unsigned int steps;
unsigned int ds;
};
struct axg_pdm_hpf {
unsigned int out_factor;
unsigned int steps;
};
struct axg_pdm_filters {
struct axg_pdm_hcic hcic;
struct axg_pdm_hpf hpf;
struct axg_pdm_lpf lpf[PDM_LPF_NUM];
};
struct axg_pdm_cfg {
const struct axg_pdm_filters *filters;
unsigned int sys_rate;
};
struct axg_pdm {
const struct axg_pdm_cfg *cfg;
struct regmap *map;
struct clk *dclk;
struct clk *sysclk;
struct clk *pclk;
};
static void axg_pdm_enable(struct regmap *map)
{
/* Reset AFIFO */
regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, PDM_CTRL_RST_FIFO);
regmap_update_bits(map, PDM_CTRL, PDM_CTRL_RST_FIFO, 0);
/* Enable PDM */
regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, PDM_CTRL_EN);
}
static void axg_pdm_disable(struct regmap *map)
{
regmap_update_bits(map, PDM_CTRL, PDM_CTRL_EN, 0);
}
static void axg_pdm_filters_enable(struct regmap *map, bool enable)
{
unsigned int val = enable ? PDM_FILTER_EN : 0;
regmap_update_bits(map, PDM_HCIC_CTRL1, PDM_FILTER_EN, val);
regmap_update_bits(map, PDM_F1_CTRL, PDM_FILTER_EN, val);
regmap_update_bits(map, PDM_F2_CTRL, PDM_FILTER_EN, val);
regmap_update_bits(map, PDM_F3_CTRL, PDM_FILTER_EN, val);
regmap_update_bits(map, PDM_HPF_CTRL, PDM_FILTER_EN, val);
}
static int axg_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
axg_pdm_enable(priv->map);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
axg_pdm_disable(priv->map);
return 0;
default:
return -EINVAL;
}
}
static unsigned int axg_pdm_get_os(struct axg_pdm *priv)
{
const struct axg_pdm_filters *filters = priv->cfg->filters;
unsigned int os = filters->hcic.ds;
int i;
/*
* The global oversampling factor is defined by the down sampling
* factor applied by each filter (HCIC and LPFs)
*/
for (i = 0; i < PDM_LPF_NUM; i++)
os *= filters->lpf[i].ds;
return os;
}
static int axg_pdm_set_sysclk(struct axg_pdm *priv, unsigned int os,
unsigned int rate)
{
unsigned int sys_rate = os * 2 * rate * PDM_CHAN_CTRL_POINTER_MAX;
/*
* Set the default system clock rate unless it is too fast for
* the requested sample rate. In this case, the sample pointer
* counter could overflow so set a lower system clock rate
*/
if (sys_rate < priv->cfg->sys_rate)
return clk_set_rate(priv->sysclk, sys_rate);
return clk_set_rate(priv->sysclk, priv->cfg->sys_rate);
}
static int axg_pdm_set_sample_pointer(struct axg_pdm *priv)
{
unsigned int spmax, sp, val;
int i;
/* Max sample counter value per half period of dclk */
spmax = DIV_ROUND_UP_ULL((u64)clk_get_rate(priv->sysclk),
clk_get_rate(priv->dclk) * 2);
/* Check if sysclk is not too fast - should not happen */
if (WARN_ON(spmax > PDM_CHAN_CTRL_POINTER_MAX))
return -EINVAL;
/* Capture the data when we are at 75% of the half period */
sp = spmax * 3 / 4;
for (i = 0, val = 0; i < PDM_CHAN_CTRL_NUM; i++)
val |= sp << (PDM_CHAN_CTRL_POINTER_WIDTH * i);
regmap_write(priv->map, PDM_CHAN_CTRL, val);
regmap_write(priv->map, PDM_CHAN_CTRL1, val);
return 0;
}
static void axg_pdm_set_channel_mask(struct axg_pdm *priv,
unsigned int channels)
{
unsigned int mask = GENMASK(channels - 1, 0);
/* Put all channel in reset */
regmap_update_bits(priv->map, PDM_CTRL,
PDM_CTRL_CHAN_RSTN_MASK, 0);
/* Take the necessary channels out of reset and enable them */
regmap_update_bits(priv->map, PDM_CTRL,
PDM_CTRL_CHAN_RSTN_MASK |
PDM_CTRL_CHAN_EN_MASK,
PDM_CTRL_CHAN_RSTN(mask) |
PDM_CTRL_CHAN_EN(mask));
}
static int axg_pdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
unsigned int os = axg_pdm_get_os(priv);
unsigned int rate = params_rate(params);
unsigned int val;
int ret;
switch (params_width(params)) {
case 24:
val = PDM_CTRL_OUT_MODE;
break;
case 32:
val = 0;
break;
default:
dev_err(dai->dev, "unsupported sample width\n");
return -EINVAL;
}
regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_OUT_MODE, val);
ret = axg_pdm_set_sysclk(priv, os, rate);
if (ret) {
dev_err(dai->dev, "failed to set system clock\n");
return ret;
}
ret = clk_set_rate(priv->dclk, rate * os);
if (ret) {
dev_err(dai->dev, "failed to set dclk\n");
return ret;
}
ret = axg_pdm_set_sample_pointer(priv);
if (ret) {
dev_err(dai->dev, "invalid clock setting\n");
return ret;
}
axg_pdm_set_channel_mask(priv, params_channels(params));
return 0;
}
static int axg_pdm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
int ret;
ret = clk_prepare_enable(priv->dclk);
if (ret) {
dev_err(dai->dev, "enabling dclk failed\n");
return ret;
}
/* Enable the filters */
axg_pdm_filters_enable(priv->map, true);
return ret;
}
static void axg_pdm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
axg_pdm_filters_enable(priv->map, false);
clk_disable_unprepare(priv->dclk);
}
static void axg_pdm_set_hcic_ctrl(struct axg_pdm *priv)
{
const struct axg_pdm_hcic *hcic = &priv->cfg->filters->hcic;
unsigned int val;
val = PDM_HCIC_CTRL1_STAGE_NUM(hcic->steps);
val |= PDM_HCIC_CTRL1_DSR(hcic->ds);
val |= PDM_HCIC_CTRL1_GAIN_MULT(hcic->mult);
val |= PDM_HCIC_CTRL1_GAIN_SFT(hcic->shift);
regmap_update_bits(priv->map, PDM_HCIC_CTRL1,
PDM_HCIC_CTRL1_STAGE_NUM_MASK |
PDM_HCIC_CTRL1_DSR_MASK |
PDM_HCIC_CTRL1_GAIN_MULT_MASK |
PDM_HCIC_CTRL1_GAIN_SFT_MASK,
val);
}
static void axg_pdm_set_lpf_ctrl(struct axg_pdm *priv, unsigned int index)
{
const struct axg_pdm_lpf *lpf = &priv->cfg->filters->lpf[index];
unsigned int offset = index * regmap_get_reg_stride(priv->map)
+ PDM_F1_CTRL;
unsigned int val;
val = PDM_LPF_STAGE_NUM(lpf->tap_num);
val |= PDM_LPF_DSR(lpf->ds);
val |= PDM_LPF_ROUND_MODE(lpf->round_mode);
regmap_update_bits(priv->map, offset,
PDM_LPF_STAGE_NUM_MASK |
PDM_LPF_DSR_MASK |
PDM_LPF_ROUND_MODE_MASK,
val);
}
static void axg_pdm_set_hpf_ctrl(struct axg_pdm *priv)
{
const struct axg_pdm_hpf *hpf = &priv->cfg->filters->hpf;
unsigned int val;
val = PDM_HPF_OUT_FACTOR(hpf->out_factor);
val |= PDM_HPF_SFT_STEPS(hpf->steps);
regmap_update_bits(priv->map, PDM_HPF_CTRL,
PDM_HPF_OUT_FACTOR_MASK |
PDM_HPF_SFT_STEPS_MASK,
val);
}
static int axg_pdm_set_lpf_filters(struct axg_pdm *priv)
{
const struct axg_pdm_lpf *lpf = priv->cfg->filters->lpf;
unsigned int count = 0;
int i, j;
for (i = 0; i < PDM_LPF_NUM; i++)
count += lpf[i].tap_num;
/* Make sure the coeffs fit in the memory */
if (count >= PDM_LPF_MAX_STAGE)
return -EINVAL;
/* Set the initial APB bus register address */
regmap_write(priv->map, PDM_COEFF_ADDR, 0);
/* Set the tap filter values of all 3 filters */
for (i = 0; i < PDM_LPF_NUM; i++) {
axg_pdm_set_lpf_ctrl(priv, i);
for (j = 0; j < lpf[i].tap_num; j++)
regmap_write(priv->map, PDM_COEFF_DATA, lpf[i].tap[j]);
}
return 0;
}
static int axg_pdm_dai_probe(struct snd_soc_dai *dai)
{
struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
int ret;
ret = clk_prepare_enable(priv->pclk);
if (ret) {
dev_err(dai->dev, "enabling pclk failed\n");
return ret;
}
/*
* sysclk must be set and enabled as well to access the pdm registers
* Accessing the register w/o it will give a bus error.
*/
ret = clk_set_rate(priv->sysclk, priv->cfg->sys_rate);
if (ret) {
dev_err(dai->dev, "setting sysclk failed\n");
goto err_pclk;
}
ret = clk_prepare_enable(priv->sysclk);
if (ret) {
dev_err(dai->dev, "enabling sysclk failed\n");
goto err_pclk;
}
/* Make sure the device is initially disabled */
axg_pdm_disable(priv->map);
/* Make sure filter bypass is disabled */
regmap_update_bits(priv->map, PDM_CTRL, PDM_CTRL_BYPASS_MODE, 0);
/* Load filter settings */
axg_pdm_set_hcic_ctrl(priv);
axg_pdm_set_hpf_ctrl(priv);
ret = axg_pdm_set_lpf_filters(priv);
if (ret) {
dev_err(dai->dev, "invalid filter configuration\n");
goto err_sysclk;
}
return 0;
err_sysclk:
clk_disable_unprepare(priv->sysclk);
err_pclk:
clk_disable_unprepare(priv->pclk);
return ret;
}
static int axg_pdm_dai_remove(struct snd_soc_dai *dai)
{
struct axg_pdm *priv = snd_soc_dai_get_drvdata(dai);
clk_disable_unprepare(priv->sysclk);
clk_disable_unprepare(priv->pclk);
return 0;
}
static const struct snd_soc_dai_ops axg_pdm_dai_ops = {
.probe = axg_pdm_dai_probe,
.remove = axg_pdm_dai_remove,
.trigger = axg_pdm_trigger,
.hw_params = axg_pdm_hw_params,
.startup = axg_pdm_startup,
.shutdown = axg_pdm_shutdown,
};
static struct snd_soc_dai_driver axg_pdm_dai_drv = {
.name = "PDM",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 5512,
.rate_max = 48000,
.formats = (SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE),
},
.ops = &axg_pdm_dai_ops,
};
static const struct snd_soc_component_driver axg_pdm_component_drv = {
.legacy_dai_naming = 1,
};
static const struct regmap_config axg_pdm_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = PDM_STS,
};
static const unsigned int lpf1_default_tap[] = {
0x000014, 0xffffb2, 0xfffed9, 0xfffdce, 0xfffd45,
0xfffe32, 0x000147, 0x000645, 0x000b86, 0x000e21,
0x000ae3, 0x000000, 0xffeece, 0xffdca8, 0xffd212,
0xffd7d1, 0xfff2a7, 0x001f4c, 0x0050c2, 0x0072aa,
0x006ff1, 0x003c32, 0xffdc4e, 0xff6a18, 0xff0fef,
0xfefbaf, 0xff4c40, 0x000000, 0x00ebc8, 0x01c077,
0x02209e, 0x01c1a4, 0x008e60, 0xfebe52, 0xfcd690,
0xfb8fa5, 0xfba498, 0xfd9812, 0x0181ce, 0x06f5f3,
0x0d112f, 0x12a958, 0x169686, 0x18000e, 0x169686,
0x12a958, 0x0d112f, 0x06f5f3, 0x0181ce, 0xfd9812,
0xfba498, 0xfb8fa5, 0xfcd690, 0xfebe52, 0x008e60,
0x01c1a4, 0x02209e, 0x01c077, 0x00ebc8, 0x000000,
0xff4c40, 0xfefbaf, 0xff0fef, 0xff6a18, 0xffdc4e,
0x003c32, 0x006ff1, 0x0072aa, 0x0050c2, 0x001f4c,
0xfff2a7, 0xffd7d1, 0xffd212, 0xffdca8, 0xffeece,
0x000000, 0x000ae3, 0x000e21, 0x000b86, 0x000645,
0x000147, 0xfffe32, 0xfffd45, 0xfffdce, 0xfffed9,
0xffffb2, 0x000014,
};
static const unsigned int lpf2_default_tap[] = {
0x00050a, 0xfff004, 0x0002c1, 0x003c12, 0xffa818,
0xffc87d, 0x010aef, 0xff5223, 0xfebd93, 0x028f41,
0xff5c0e, 0xfc63f8, 0x055f81, 0x000000, 0xf478a0,
0x11c5e3, 0x2ea74d, 0x11c5e3, 0xf478a0, 0x000000,
0x055f81, 0xfc63f8, 0xff5c0e, 0x028f41, 0xfebd93,
0xff5223, 0x010aef, 0xffc87d, 0xffa818, 0x003c12,
0x0002c1, 0xfff004, 0x00050a,
};
static const unsigned int lpf3_default_tap[] = {
0x000000, 0x000081, 0x000000, 0xfffedb, 0x000000,
0x00022d, 0x000000, 0xfffc46, 0x000000, 0x0005f7,
0x000000, 0xfff6eb, 0x000000, 0x000d4e, 0x000000,
0xffed1e, 0x000000, 0x001a1c, 0x000000, 0xffdcb0,
0x000000, 0x002ede, 0x000000, 0xffc2d1, 0x000000,
0x004ebe, 0x000000, 0xff9beb, 0x000000, 0x007dd7,
0x000000, 0xff633a, 0x000000, 0x00c1d2, 0x000000,
0xff11d5, 0x000000, 0x012368, 0x000000, 0xfe9c45,
0x000000, 0x01b252, 0x000000, 0xfdebf6, 0x000000,
0x0290b8, 0x000000, 0xfcca0d, 0x000000, 0x041d7c,
0x000000, 0xfa8152, 0x000000, 0x07e9c6, 0x000000,
0xf28fb5, 0x000000, 0x28b216, 0x3fffde, 0x28b216,
0x000000, 0xf28fb5, 0x000000, 0x07e9c6, 0x000000,
0xfa8152, 0x000000, 0x041d7c, 0x000000, 0xfcca0d,
0x000000, 0x0290b8, 0x000000, 0xfdebf6, 0x000000,
0x01b252, 0x000000, 0xfe9c45, 0x000000, 0x012368,
0x000000, 0xff11d5, 0x000000, 0x00c1d2, 0x000000,
0xff633a, 0x000000, 0x007dd7, 0x000000, 0xff9beb,
0x000000, 0x004ebe, 0x000000, 0xffc2d1, 0x000000,
0x002ede, 0x000000, 0xffdcb0, 0x000000, 0x001a1c,
0x000000, 0xffed1e, 0x000000, 0x000d4e, 0x000000,
0xfff6eb, 0x000000, 0x0005f7, 0x000000, 0xfffc46,
0x000000, 0x00022d, 0x000000, 0xfffedb, 0x000000,
0x000081, 0x000000,
};
/*
* These values are sane defaults for the axg platform:
* - OS = 64
* - Latency = 38700 (?)
*
* TODO: There is a lot of different HCIC, LPFs and HPF configurations possible.
* the configuration may depend on the dmic used by the platform, the
* expected tradeoff between latency and quality, etc ... If/When other
* settings are required, we should add a fw interface to this driver to
* load new filter settings.
*/
static const struct axg_pdm_filters axg_default_filters = {
.hcic = {
.shift = 0x15,
.mult = 0x80,
.steps = 7,
.ds = 8,
},
.hpf = {
.out_factor = 0x8000,
.steps = 13,
},
.lpf = {
[0] = {
.ds = 2,
.round_mode = 1,
.tap = lpf1_default_tap,
.tap_num = ARRAY_SIZE(lpf1_default_tap),
},
[1] = {
.ds = 2,
.round_mode = 0,
.tap = lpf2_default_tap,
.tap_num = ARRAY_SIZE(lpf2_default_tap),
},
[2] = {
.ds = 2,
.round_mode = 1,
.tap = lpf3_default_tap,
.tap_num = ARRAY_SIZE(lpf3_default_tap)
},
},
};
static const struct axg_pdm_cfg axg_pdm_config = {
.filters = &axg_default_filters,
.sys_rate = 250000000,
};
static const struct of_device_id axg_pdm_of_match[] = {
{
.compatible = "amlogic,axg-pdm",
.data = &axg_pdm_config,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_pdm_of_match);
static int axg_pdm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct axg_pdm *priv;
void __iomem *regs;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->cfg = of_device_get_match_data(dev);
if (!priv->cfg) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
priv->map = devm_regmap_init_mmio(dev, regs, &axg_pdm_regmap_cfg);
if (IS_ERR(priv->map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(priv->map));
return PTR_ERR(priv->map);
}
priv->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(priv->pclk))
return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");
priv->dclk = devm_clk_get(dev, "dclk");
if (IS_ERR(priv->dclk))
return dev_err_probe(dev, PTR_ERR(priv->dclk), "failed to get dclk\n");
priv->sysclk = devm_clk_get(dev, "sysclk");
if (IS_ERR(priv->sysclk))
return dev_err_probe(dev, PTR_ERR(priv->sysclk), "failed to get dclk\n");
return devm_snd_soc_register_component(dev, &axg_pdm_component_drv,
&axg_pdm_dai_drv, 1);
}
static struct platform_driver axg_pdm_pdrv = {
.probe = axg_pdm_probe,
.driver = {
.name = "axg-pdm",
.of_match_table = axg_pdm_of_match,
},
};
module_platform_driver(axg_pdm_pdrv);
MODULE_DESCRIPTION("Amlogic AXG PDM Input driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-pdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2019 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
#include "meson-codec-glue.h"
#define G12A_TOHDMITX_DRV_NAME "g12a-tohdmitx"
#define TOHDMITX_CTRL0 0x0
#define CTRL0_ENABLE_SHIFT 31
#define CTRL0_I2S_DAT_SEL_SHIFT 12
#define CTRL0_I2S_DAT_SEL (0x3 << CTRL0_I2S_DAT_SEL_SHIFT)
#define CTRL0_I2S_LRCLK_SEL GENMASK(9, 8)
#define CTRL0_I2S_BLK_CAP_INV BIT(7)
#define CTRL0_I2S_BCLK_O_INV BIT(6)
#define CTRL0_I2S_BCLK_SEL GENMASK(5, 4)
#define CTRL0_SPDIF_CLK_CAP_INV BIT(3)
#define CTRL0_SPDIF_CLK_O_INV BIT(2)
#define CTRL0_SPDIF_SEL_SHIFT 1
#define CTRL0_SPDIF_SEL (0x1 << CTRL0_SPDIF_SEL_SHIFT)
#define CTRL0_SPDIF_CLK_SEL BIT(0)
static const char * const g12a_tohdmitx_i2s_mux_texts[] = {
"I2S A", "I2S B", "I2S C",
};
static int g12a_tohdmitx_i2s_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mux, changed;
mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
changed = snd_soc_component_test_bits(component, e->reg,
CTRL0_I2S_DAT_SEL,
FIELD_PREP(CTRL0_I2S_DAT_SEL,
mux));
if (!changed)
return 0;
/* Force disconnect of the mux while updating */
snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
snd_soc_component_update_bits(component, e->reg,
CTRL0_I2S_DAT_SEL |
CTRL0_I2S_LRCLK_SEL |
CTRL0_I2S_BCLK_SEL,
FIELD_PREP(CTRL0_I2S_DAT_SEL, mux) |
FIELD_PREP(CTRL0_I2S_LRCLK_SEL, mux) |
FIELD_PREP(CTRL0_I2S_BCLK_SEL, mux));
snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
return 1;
}
static SOC_ENUM_SINGLE_DECL(g12a_tohdmitx_i2s_mux_enum, TOHDMITX_CTRL0,
CTRL0_I2S_DAT_SEL_SHIFT,
g12a_tohdmitx_i2s_mux_texts);
static const struct snd_kcontrol_new g12a_tohdmitx_i2s_mux =
SOC_DAPM_ENUM_EXT("I2S Source", g12a_tohdmitx_i2s_mux_enum,
snd_soc_dapm_get_enum_double,
g12a_tohdmitx_i2s_mux_put_enum);
static const char * const g12a_tohdmitx_spdif_mux_texts[] = {
"SPDIF A", "SPDIF B",
};
static int g12a_tohdmitx_spdif_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mux, changed;
mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
changed = snd_soc_component_test_bits(component, TOHDMITX_CTRL0,
CTRL0_SPDIF_SEL,
FIELD_PREP(CTRL0_SPDIF_SEL, mux));
if (!changed)
return 0;
/* Force disconnect of the mux while updating */
snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
snd_soc_component_update_bits(component, TOHDMITX_CTRL0,
CTRL0_SPDIF_SEL |
CTRL0_SPDIF_CLK_SEL,
FIELD_PREP(CTRL0_SPDIF_SEL, mux) |
FIELD_PREP(CTRL0_SPDIF_CLK_SEL, mux));
snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
return 0;
}
static SOC_ENUM_SINGLE_DECL(g12a_tohdmitx_spdif_mux_enum, TOHDMITX_CTRL0,
CTRL0_SPDIF_SEL_SHIFT,
g12a_tohdmitx_spdif_mux_texts);
static const struct snd_kcontrol_new g12a_tohdmitx_spdif_mux =
SOC_DAPM_ENUM_EXT("SPDIF Source", g12a_tohdmitx_spdif_mux_enum,
snd_soc_dapm_get_enum_double,
g12a_tohdmitx_spdif_mux_put_enum);
static const struct snd_kcontrol_new g12a_tohdmitx_out_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", TOHDMITX_CTRL0,
CTRL0_ENABLE_SHIFT, 1, 0);
static const struct snd_soc_dapm_widget g12a_tohdmitx_widgets[] = {
SND_SOC_DAPM_MUX("I2S SRC", SND_SOC_NOPM, 0, 0,
&g12a_tohdmitx_i2s_mux),
SND_SOC_DAPM_SWITCH("I2S OUT EN", SND_SOC_NOPM, 0, 0,
&g12a_tohdmitx_out_enable),
SND_SOC_DAPM_MUX("SPDIF SRC", SND_SOC_NOPM, 0, 0,
&g12a_tohdmitx_spdif_mux),
SND_SOC_DAPM_SWITCH("SPDIF OUT EN", SND_SOC_NOPM, 0, 0,
&g12a_tohdmitx_out_enable),
};
static const struct snd_soc_dai_ops g12a_tohdmitx_input_ops = {
.probe = meson_codec_glue_input_dai_probe,
.remove = meson_codec_glue_input_dai_remove,
.hw_params = meson_codec_glue_input_hw_params,
.set_fmt = meson_codec_glue_input_set_fmt,
};
static const struct snd_soc_dai_ops g12a_tohdmitx_output_ops = {
.startup = meson_codec_glue_output_startup,
};
#define TOHDMITX_SPDIF_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
#define TOHDMITX_I2S_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define TOHDMITX_STREAM(xname, xsuffix, xfmt, xchmax) \
{ \
.stream_name = xname " " xsuffix, \
.channels_min = 1, \
.channels_max = (xchmax), \
.rate_min = 8000, \
.rate_max = 192000, \
.formats = (xfmt), \
}
#define TOHDMITX_IN(xname, xid, xfmt, xchmax) { \
.name = xname, \
.id = (xid), \
.playback = TOHDMITX_STREAM(xname, "Playback", xfmt, xchmax), \
.ops = &g12a_tohdmitx_input_ops, \
}
#define TOHDMITX_OUT(xname, xid, xfmt, xchmax) { \
.name = xname, \
.id = (xid), \
.capture = TOHDMITX_STREAM(xname, "Capture", xfmt, xchmax), \
.ops = &g12a_tohdmitx_output_ops, \
}
static struct snd_soc_dai_driver g12a_tohdmitx_dai_drv[] = {
TOHDMITX_IN("I2S IN A", TOHDMITX_I2S_IN_A,
TOHDMITX_I2S_FORMATS, 8),
TOHDMITX_IN("I2S IN B", TOHDMITX_I2S_IN_B,
TOHDMITX_I2S_FORMATS, 8),
TOHDMITX_IN("I2S IN C", TOHDMITX_I2S_IN_C,
TOHDMITX_I2S_FORMATS, 8),
TOHDMITX_OUT("I2S OUT", TOHDMITX_I2S_OUT,
TOHDMITX_I2S_FORMATS, 8),
TOHDMITX_IN("SPDIF IN A", TOHDMITX_SPDIF_IN_A,
TOHDMITX_SPDIF_FORMATS, 2),
TOHDMITX_IN("SPDIF IN B", TOHDMITX_SPDIF_IN_B,
TOHDMITX_SPDIF_FORMATS, 2),
TOHDMITX_OUT("SPDIF OUT", TOHDMITX_SPDIF_OUT,
TOHDMITX_SPDIF_FORMATS, 2),
};
static int g12a_tohdmi_component_probe(struct snd_soc_component *c)
{
/* Initialize the static clock parameters */
return snd_soc_component_write(c, TOHDMITX_CTRL0,
CTRL0_I2S_BLK_CAP_INV | CTRL0_SPDIF_CLK_CAP_INV);
}
static const struct snd_soc_dapm_route g12a_tohdmitx_routes[] = {
{ "I2S SRC", "I2S A", "I2S IN A Playback" },
{ "I2S SRC", "I2S B", "I2S IN B Playback" },
{ "I2S SRC", "I2S C", "I2S IN C Playback" },
{ "I2S OUT EN", "Switch", "I2S SRC" },
{ "I2S OUT Capture", NULL, "I2S OUT EN" },
{ "SPDIF SRC", "SPDIF A", "SPDIF IN A Playback" },
{ "SPDIF SRC", "SPDIF B", "SPDIF IN B Playback" },
{ "SPDIF OUT EN", "Switch", "SPDIF SRC" },
{ "SPDIF OUT Capture", NULL, "SPDIF OUT EN" },
};
static const struct snd_soc_component_driver g12a_tohdmitx_component_drv = {
.probe = g12a_tohdmi_component_probe,
.dapm_widgets = g12a_tohdmitx_widgets,
.num_dapm_widgets = ARRAY_SIZE(g12a_tohdmitx_widgets),
.dapm_routes = g12a_tohdmitx_routes,
.num_dapm_routes = ARRAY_SIZE(g12a_tohdmitx_routes),
.endianness = 1,
};
static const struct regmap_config g12a_tohdmitx_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static const struct of_device_id g12a_tohdmitx_of_match[] = {
{ .compatible = "amlogic,g12a-tohdmitx", },
{}
};
MODULE_DEVICE_TABLE(of, g12a_tohdmitx_of_match);
static int g12a_tohdmitx_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
void __iomem *regs;
struct regmap *map;
int ret;
ret = device_reset(dev);
if (ret)
return ret;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
map = devm_regmap_init_mmio(dev, regs, &g12a_tohdmitx_regmap_cfg);
if (IS_ERR(map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(map));
return PTR_ERR(map);
}
return devm_snd_soc_register_component(dev,
&g12a_tohdmitx_component_drv, g12a_tohdmitx_dai_drv,
ARRAY_SIZE(g12a_tohdmitx_dai_drv));
}
static struct platform_driver g12a_tohdmitx_pdrv = {
.driver = {
.name = G12A_TOHDMITX_DRV_NAME,
.of_match_table = g12a_tohdmitx_of_match,
},
.probe = g12a_tohdmitx_probe,
};
module_platform_driver(g12a_tohdmitx_pdrv);
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_DESCRIPTION("Amlogic G12a To HDMI Tx Control Codec Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/g12a-tohdmitx.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-tdm.h"
#include "meson-card.h"
struct axg_dai_link_tdm_mask {
u32 tx;
u32 rx;
};
struct axg_dai_link_tdm_data {
unsigned int mclk_fs;
unsigned int slots;
unsigned int slot_width;
u32 *tx_mask;
u32 *rx_mask;
struct axg_dai_link_tdm_mask *codec_masks;
};
/*
* Base params for the codec to codec links
* Those will be over-written by the CPU side of the link
*/
static const struct snd_soc_pcm_stream codec_params = {
.formats = SNDRV_PCM_FMTBIT_S24_LE,
.rate_min = 5525,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 8,
};
static int axg_card_tdm_be_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct meson_card *priv = snd_soc_card_get_drvdata(rtd->card);
struct axg_dai_link_tdm_data *be =
(struct axg_dai_link_tdm_data *)priv->link_data[rtd->num];
return meson_card_i2s_set_sysclk(substream, params, be->mclk_fs);
}
static const struct snd_soc_ops axg_card_tdm_be_ops = {
.hw_params = axg_card_tdm_be_hw_params,
};
static int axg_card_tdm_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct meson_card *priv = snd_soc_card_get_drvdata(rtd->card);
struct axg_dai_link_tdm_data *be =
(struct axg_dai_link_tdm_data *)priv->link_data[rtd->num];
struct snd_soc_dai *codec_dai;
int ret, i;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_tdm_slot(codec_dai,
be->codec_masks[i].tx,
be->codec_masks[i].rx,
be->slots, be->slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(codec_dai->dev,
"setting tdm link slots failed\n");
return ret;
}
}
ret = axg_tdm_set_tdm_slots(asoc_rtd_to_cpu(rtd, 0), be->tx_mask, be->rx_mask,
be->slots, be->slot_width);
if (ret) {
dev_err(asoc_rtd_to_cpu(rtd, 0)->dev, "setting tdm link slots failed\n");
return ret;
}
return 0;
}
static int axg_card_tdm_dai_lb_init(struct snd_soc_pcm_runtime *rtd)
{
struct meson_card *priv = snd_soc_card_get_drvdata(rtd->card);
struct axg_dai_link_tdm_data *be =
(struct axg_dai_link_tdm_data *)priv->link_data[rtd->num];
int ret;
/* The loopback rx_mask is the pad tx_mask */
ret = axg_tdm_set_tdm_slots(asoc_rtd_to_cpu(rtd, 0), NULL, be->tx_mask,
be->slots, be->slot_width);
if (ret) {
dev_err(asoc_rtd_to_cpu(rtd, 0)->dev, "setting tdm link slots failed\n");
return ret;
}
return 0;
}
static int axg_card_add_tdm_loopback(struct snd_soc_card *card,
int *index)
{
struct meson_card *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_dai_link *pad = &card->dai_link[*index];
struct snd_soc_dai_link *lb;
struct snd_soc_dai_link_component *dlc;
int ret;
/* extend links */
ret = meson_card_reallocate_links(card, card->num_links + 1);
if (ret)
return ret;
lb = &card->dai_link[*index + 1];
lb->name = devm_kasprintf(card->dev, GFP_KERNEL, "%s-lb", pad->name);
if (!lb->name)
return -ENOMEM;
dlc = devm_kzalloc(card->dev, sizeof(*dlc), GFP_KERNEL);
if (!dlc)
return -ENOMEM;
lb->cpus = dlc;
lb->codecs = &asoc_dummy_dlc;
lb->num_cpus = 1;
lb->num_codecs = 1;
lb->stream_name = lb->name;
lb->cpus->of_node = pad->cpus->of_node;
lb->cpus->dai_name = "TDM Loopback";
lb->dpcm_capture = 1;
lb->no_pcm = 1;
lb->ops = &axg_card_tdm_be_ops;
lb->init = axg_card_tdm_dai_lb_init;
/* Provide the same link data to the loopback */
priv->link_data[*index + 1] = priv->link_data[*index];
/*
* axg_card_clean_references() will iterate over this link,
* make sure the node count is balanced
*/
of_node_get(lb->cpus->of_node);
/* Let add_links continue where it should */
*index += 1;
return 0;
}
static int axg_card_parse_cpu_tdm_slots(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node,
struct axg_dai_link_tdm_data *be)
{
char propname[32];
u32 tx, rx;
int i;
be->tx_mask = devm_kcalloc(card->dev, AXG_TDM_NUM_LANES,
sizeof(*be->tx_mask), GFP_KERNEL);
be->rx_mask = devm_kcalloc(card->dev, AXG_TDM_NUM_LANES,
sizeof(*be->rx_mask), GFP_KERNEL);
if (!be->tx_mask || !be->rx_mask)
return -ENOMEM;
for (i = 0, tx = 0; i < AXG_TDM_NUM_LANES; i++) {
snprintf(propname, 32, "dai-tdm-slot-tx-mask-%d", i);
snd_soc_of_get_slot_mask(node, propname, &be->tx_mask[i]);
tx = max(tx, be->tx_mask[i]);
}
/* Disable playback is the interface has no tx slots */
if (!tx)
link->dpcm_playback = 0;
for (i = 0, rx = 0; i < AXG_TDM_NUM_LANES; i++) {
snprintf(propname, 32, "dai-tdm-slot-rx-mask-%d", i);
snd_soc_of_get_slot_mask(node, propname, &be->rx_mask[i]);
rx = max(rx, be->rx_mask[i]);
}
/* Disable capture is the interface has no rx slots */
if (!rx)
link->dpcm_capture = 0;
/* ... but the interface should at least have one of them */
if (!tx && !rx) {
dev_err(card->dev, "tdm link has no cpu slots\n");
return -EINVAL;
}
of_property_read_u32(node, "dai-tdm-slot-num", &be->slots);
if (!be->slots) {
/*
* If the slot number is not provided, set it such as it
* accommodates the largest mask
*/
be->slots = fls(max(tx, rx));
} else if (be->slots < fls(max(tx, rx)) || be->slots > 32) {
/*
* Error if the slots can't accommodate the largest mask or
* if it is just too big
*/
dev_err(card->dev, "bad slot number\n");
return -EINVAL;
}
of_property_read_u32(node, "dai-tdm-slot-width", &be->slot_width);
return 0;
}
static int axg_card_parse_codecs_masks(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node,
struct axg_dai_link_tdm_data *be)
{
struct axg_dai_link_tdm_mask *codec_mask;
struct device_node *np;
codec_mask = devm_kcalloc(card->dev, link->num_codecs,
sizeof(*codec_mask), GFP_KERNEL);
if (!codec_mask)
return -ENOMEM;
be->codec_masks = codec_mask;
for_each_child_of_node(node, np) {
snd_soc_of_get_slot_mask(np, "dai-tdm-slot-rx-mask",
&codec_mask->rx);
snd_soc_of_get_slot_mask(np, "dai-tdm-slot-tx-mask",
&codec_mask->tx);
codec_mask++;
}
return 0;
}
static int axg_card_parse_tdm(struct snd_soc_card *card,
struct device_node *node,
int *index)
{
struct meson_card *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_dai_link *link = &card->dai_link[*index];
struct axg_dai_link_tdm_data *be;
int ret;
/* Allocate tdm link parameters */
be = devm_kzalloc(card->dev, sizeof(*be), GFP_KERNEL);
if (!be)
return -ENOMEM;
priv->link_data[*index] = be;
/* Setup tdm link */
link->ops = &axg_card_tdm_be_ops;
link->init = axg_card_tdm_dai_init;
link->dai_fmt = meson_card_parse_daifmt(node, link->cpus->of_node);
of_property_read_u32(node, "mclk-fs", &be->mclk_fs);
ret = axg_card_parse_cpu_tdm_slots(card, link, node, be);
if (ret) {
dev_err(card->dev, "error parsing tdm link slots\n");
return ret;
}
ret = axg_card_parse_codecs_masks(card, link, node, be);
if (ret)
return ret;
/* Add loopback if the pad dai has playback */
if (link->dpcm_playback) {
ret = axg_card_add_tdm_loopback(card, index);
if (ret)
return ret;
}
return 0;
}
static int axg_card_cpu_is_capture_fe(struct device_node *np)
{
return of_device_is_compatible(np, DT_PREFIX "axg-toddr");
}
static int axg_card_cpu_is_playback_fe(struct device_node *np)
{
return of_device_is_compatible(np, DT_PREFIX "axg-frddr");
}
static int axg_card_cpu_is_tdm_iface(struct device_node *np)
{
return of_device_is_compatible(np, DT_PREFIX "axg-tdm-iface");
}
static int axg_card_cpu_is_codec(struct device_node *np)
{
return of_device_is_compatible(np, DT_PREFIX "g12a-tohdmitx") ||
of_device_is_compatible(np, DT_PREFIX "g12a-toacodec");
}
static int axg_card_add_link(struct snd_soc_card *card, struct device_node *np,
int *index)
{
struct snd_soc_dai_link *dai_link = &card->dai_link[*index];
struct snd_soc_dai_link_component *cpu;
int ret;
cpu = devm_kzalloc(card->dev, sizeof(*cpu), GFP_KERNEL);
if (!cpu)
return -ENOMEM;
dai_link->cpus = cpu;
dai_link->num_cpus = 1;
ret = meson_card_parse_dai(card, np, dai_link->cpus);
if (ret)
return ret;
if (axg_card_cpu_is_playback_fe(dai_link->cpus->of_node))
return meson_card_set_fe_link(card, dai_link, np, true);
else if (axg_card_cpu_is_capture_fe(dai_link->cpus->of_node))
return meson_card_set_fe_link(card, dai_link, np, false);
ret = meson_card_set_be_link(card, dai_link, np);
if (ret)
return ret;
if (axg_card_cpu_is_codec(dai_link->cpus->of_node)) {
dai_link->c2c_params = &codec_params;
dai_link->num_c2c_params = 1;
} else {
dai_link->no_pcm = 1;
snd_soc_dai_link_set_capabilities(dai_link);
if (axg_card_cpu_is_tdm_iface(dai_link->cpus->of_node))
ret = axg_card_parse_tdm(card, np, index);
}
return ret;
}
static const struct meson_card_match_data axg_card_match_data = {
.add_link = axg_card_add_link,
};
static const struct of_device_id axg_card_of_match[] = {
{
.compatible = "amlogic,axg-sound-card",
.data = &axg_card_match_data,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_card_of_match);
static struct platform_driver axg_card_pdrv = {
.probe = meson_card_probe,
.remove = meson_card_remove,
.driver = {
.name = "axg-sound-card",
.of_match_table = axg_card_of_match,
},
};
module_platform_driver(axg_card_pdrv);
MODULE_DESCRIPTION("Amlogic AXG ALSA machine driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-card.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "meson-card.h"
struct gx_dai_link_i2s_data {
unsigned int mclk_fs;
};
/*
* Base params for the codec to codec links
* Those will be over-written by the CPU side of the link
*/
static const struct snd_soc_pcm_stream codec_params = {
.formats = SNDRV_PCM_FMTBIT_S24_LE,
.rate_min = 5525,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 8,
};
static int gx_card_i2s_be_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct meson_card *priv = snd_soc_card_get_drvdata(rtd->card);
struct gx_dai_link_i2s_data *be =
(struct gx_dai_link_i2s_data *)priv->link_data[rtd->num];
return meson_card_i2s_set_sysclk(substream, params, be->mclk_fs);
}
static const struct snd_soc_ops gx_card_i2s_be_ops = {
.hw_params = gx_card_i2s_be_hw_params,
};
static int gx_card_parse_i2s(struct snd_soc_card *card,
struct device_node *node,
int *index)
{
struct meson_card *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_dai_link *link = &card->dai_link[*index];
struct gx_dai_link_i2s_data *be;
/* Allocate i2s link parameters */
be = devm_kzalloc(card->dev, sizeof(*be), GFP_KERNEL);
if (!be)
return -ENOMEM;
priv->link_data[*index] = be;
/* Setup i2s link */
link->ops = &gx_card_i2s_be_ops;
link->dai_fmt = meson_card_parse_daifmt(node, link->cpus->of_node);
of_property_read_u32(node, "mclk-fs", &be->mclk_fs);
return 0;
}
static int gx_card_cpu_identify(struct snd_soc_dai_link_component *c,
char *match)
{
if (of_device_is_compatible(c->of_node, DT_PREFIX "aiu")) {
if (strstr(c->dai_name, match))
return 1;
}
/* dai not matched */
return 0;
}
static int gx_card_add_link(struct snd_soc_card *card, struct device_node *np,
int *index)
{
struct snd_soc_dai_link *dai_link = &card->dai_link[*index];
struct snd_soc_dai_link_component *cpu;
int ret;
cpu = devm_kzalloc(card->dev, sizeof(*cpu), GFP_KERNEL);
if (!cpu)
return -ENOMEM;
dai_link->cpus = cpu;
dai_link->num_cpus = 1;
ret = meson_card_parse_dai(card, np, dai_link->cpus);
if (ret)
return ret;
if (gx_card_cpu_identify(dai_link->cpus, "FIFO"))
return meson_card_set_fe_link(card, dai_link, np, true);
ret = meson_card_set_be_link(card, dai_link, np);
if (ret)
return ret;
/* Or apply codec to codec params if necessary */
if (gx_card_cpu_identify(dai_link->cpus, "CODEC CTRL")) {
dai_link->c2c_params = &codec_params;
dai_link->num_c2c_params = 1;
} else {
dai_link->no_pcm = 1;
snd_soc_dai_link_set_capabilities(dai_link);
/* Check if the cpu is the i2s encoder and parse i2s data */
if (gx_card_cpu_identify(dai_link->cpus, "I2S Encoder"))
ret = gx_card_parse_i2s(card, np, index);
}
return ret;
}
static const struct meson_card_match_data gx_card_match_data = {
.add_link = gx_card_add_link,
};
static const struct of_device_id gx_card_of_match[] = {
{
.compatible = "amlogic,gx-sound-card",
.data = &gx_card_match_data,
}, {}
};
MODULE_DEVICE_TABLE(of, gx_card_of_match);
static struct platform_driver gx_card_pdrv = {
.probe = meson_card_probe,
.remove = meson_card_remove,
.driver = {
.name = "gx-sound-card",
.of_match_table = gx_card_of_match,
},
};
module_platform_driver(gx_card_pdrv);
MODULE_DESCRIPTION("Amlogic GX ALSA machine driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/gx-card.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <sound/pcm_params.h>
#include <sound/pcm_iec958.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "aiu.h"
#define AIU_958_MISC_NON_PCM BIT(0)
#define AIU_958_MISC_MODE_16BITS BIT(1)
#define AIU_958_MISC_16BITS_ALIGN GENMASK(6, 5)
#define AIU_958_MISC_MODE_32BITS BIT(7)
#define AIU_958_MISC_U_FROM_STREAM BIT(12)
#define AIU_958_MISC_FORCE_LR BIT(13)
#define AIU_958_CTRL_HOLD_EN BIT(0)
#define AIU_CLK_CTRL_958_DIV_EN BIT(1)
#define AIU_CLK_CTRL_958_DIV GENMASK(5, 4)
#define AIU_CLK_CTRL_958_DIV_MORE BIT(12)
#define AIU_CS_WORD_LEN 4
#define AIU_958_INTERNAL_DIV 2
static void
aiu_encoder_spdif_divider_enable(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_update_bits(component, AIU_CLK_CTRL,
AIU_CLK_CTRL_958_DIV_EN,
enable ? AIU_CLK_CTRL_958_DIV_EN : 0);
}
static void aiu_encoder_spdif_hold(struct snd_soc_component *component,
bool enable)
{
snd_soc_component_update_bits(component, AIU_958_CTRL,
AIU_958_CTRL_HOLD_EN,
enable ? AIU_958_CTRL_HOLD_EN : 0);
}
static int
aiu_encoder_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
aiu_encoder_spdif_hold(component, false);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
aiu_encoder_spdif_hold(component, true);
return 0;
default:
return -EINVAL;
}
}
static int aiu_encoder_spdif_setup_cs_word(struct snd_soc_component *component,
struct snd_pcm_hw_params *params)
{
u8 cs[AIU_CS_WORD_LEN];
unsigned int val;
int ret;
ret = snd_pcm_create_iec958_consumer_hw_params(params, cs,
AIU_CS_WORD_LEN);
if (ret < 0)
return ret;
/* Write the 1st half word */
val = cs[1] | cs[0] << 8;
snd_soc_component_write(component, AIU_958_CHSTAT_L0, val);
snd_soc_component_write(component, AIU_958_CHSTAT_R0, val);
/* Write the 2nd half word */
val = cs[3] | cs[2] << 8;
snd_soc_component_write(component, AIU_958_CHSTAT_L1, val);
snd_soc_component_write(component, AIU_958_CHSTAT_R1, val);
return 0;
}
static int aiu_encoder_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct aiu *aiu = snd_soc_component_get_drvdata(component);
unsigned int val = 0, mrate;
int ret;
/* Disable the clock while changing the settings */
aiu_encoder_spdif_divider_enable(component, false);
switch (params_physical_width(params)) {
case 16:
val |= AIU_958_MISC_MODE_16BITS;
val |= FIELD_PREP(AIU_958_MISC_16BITS_ALIGN, 2);
break;
case 32:
val |= AIU_958_MISC_MODE_32BITS;
break;
default:
dev_err(dai->dev, "Unsupported physical width\n");
return -EINVAL;
}
snd_soc_component_update_bits(component, AIU_958_MISC,
AIU_958_MISC_NON_PCM |
AIU_958_MISC_MODE_16BITS |
AIU_958_MISC_16BITS_ALIGN |
AIU_958_MISC_MODE_32BITS |
AIU_958_MISC_FORCE_LR |
AIU_958_MISC_U_FROM_STREAM,
val);
/* Set the stream channel status word */
ret = aiu_encoder_spdif_setup_cs_word(component, params);
if (ret) {
dev_err(dai->dev, "failed to set channel status word\n");
return ret;
}
snd_soc_component_update_bits(component, AIU_CLK_CTRL,
AIU_CLK_CTRL_958_DIV |
AIU_CLK_CTRL_958_DIV_MORE,
FIELD_PREP(AIU_CLK_CTRL_958_DIV,
__ffs(AIU_958_INTERNAL_DIV)));
/* 2 * 32bits per subframe * 2 channels = 128 */
mrate = params_rate(params) * 128 * AIU_958_INTERNAL_DIV;
ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate);
if (ret) {
dev_err(dai->dev, "failed to set mclk rate\n");
return ret;
}
aiu_encoder_spdif_divider_enable(component, true);
return 0;
}
static int aiu_encoder_spdif_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
aiu_encoder_spdif_divider_enable(component, false);
return 0;
}
static int aiu_encoder_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
int ret;
/*
* NOTE: Make sure the spdif block is on its own divider.
*
* The spdif can be clocked by the i2s master clock or its own
* clock. We should (in theory) change the source depending on the
* origin of the data.
*
* However, considering the clocking scheme used on these platforms,
* the master clocks will pick the same PLL source when they are
* playing from the same FIFO. The clock should be in sync so, it
* should not be necessary to reparent the spdif master clock.
*/
ret = clk_set_parent(aiu->spdif.clks[MCLK].clk,
aiu->spdif_mclk);
if (ret)
return ret;
ret = clk_bulk_prepare_enable(aiu->spdif.clk_num, aiu->spdif.clks);
if (ret)
dev_err(dai->dev, "failed to enable spdif clocks\n");
return ret;
}
static void aiu_encoder_spdif_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
clk_bulk_disable_unprepare(aiu->spdif.clk_num, aiu->spdif.clks);
}
const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops = {
.trigger = aiu_encoder_spdif_trigger,
.hw_params = aiu_encoder_spdif_hw_params,
.hw_free = aiu_encoder_spdif_hw_free,
.startup = aiu_encoder_spdif_startup,
.shutdown = aiu_encoder_spdif_shutdown,
};
| linux-master | sound/soc/meson/aiu-encoder-spdif.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2020 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/meson-g12a-toacodec.h>
#include "axg-tdm.h"
#include "meson-codec-glue.h"
#define G12A_TOACODEC_DRV_NAME "g12a-toacodec"
#define TOACODEC_CTRL0 0x0
#define CTRL0_ENABLE_SHIFT 31
#define CTRL0_DAT_SEL_SM1_MSB 19
#define CTRL0_DAT_SEL_SM1_LSB 18
#define CTRL0_DAT_SEL_MSB 15
#define CTRL0_DAT_SEL_LSB 14
#define CTRL0_LANE_SEL_SM1 16
#define CTRL0_LANE_SEL 12
#define CTRL0_LRCLK_SEL_SM1_MSB 14
#define CTRL0_LRCLK_SEL_SM1_LSB 12
#define CTRL0_LRCLK_SEL_MSB 9
#define CTRL0_LRCLK_SEL_LSB 8
#define CTRL0_LRCLK_INV_SM1 BIT(10)
#define CTRL0_BLK_CAP_INV_SM1 BIT(9)
#define CTRL0_BLK_CAP_INV BIT(7)
#define CTRL0_BCLK_O_INV_SM1 BIT(8)
#define CTRL0_BCLK_O_INV BIT(6)
#define CTRL0_BCLK_SEL_SM1_MSB 6
#define CTRL0_BCLK_SEL_MSB 5
#define CTRL0_BCLK_SEL_LSB 4
#define CTRL0_MCLK_SEL GENMASK(2, 0)
#define TOACODEC_OUT_CHMAX 2
struct g12a_toacodec {
struct regmap_field *field_dat_sel;
struct regmap_field *field_lrclk_sel;
struct regmap_field *field_bclk_sel;
};
struct g12a_toacodec_match_data {
const struct snd_soc_component_driver *component_drv;
struct reg_field field_dat_sel;
struct reg_field field_lrclk_sel;
struct reg_field field_bclk_sel;
};
static const char * const g12a_toacodec_mux_texts[] = {
"I2S A", "I2S B", "I2S C",
};
static int g12a_toacodec_mux_put_enum(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_dapm_kcontrol_component(kcontrol);
struct g12a_toacodec *priv = snd_soc_component_get_drvdata(component);
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int mux, reg;
mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
regmap_field_read(priv->field_dat_sel, ®);
if (mux == reg)
return 0;
/* Force disconnect of the mux while updating */
snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
regmap_field_write(priv->field_dat_sel, mux);
regmap_field_write(priv->field_lrclk_sel, mux);
regmap_field_write(priv->field_bclk_sel, mux);
/*
* FIXME:
* On this soc, the glue gets the MCLK directly from the clock
* controller instead of going the through the TDM interface.
*
* Here we assume interface A uses clock A, etc ... While it is
* true for now, it could be different. Instead the glue should
* find out the clock used by the interface and select the same
* source. For that, we will need regmap backed clock mux which
* is a work in progress
*/
snd_soc_component_update_bits(component, e->reg,
CTRL0_MCLK_SEL,
FIELD_PREP(CTRL0_MCLK_SEL, mux));
snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
return 0;
}
static SOC_ENUM_SINGLE_DECL(g12a_toacodec_mux_enum, TOACODEC_CTRL0,
CTRL0_DAT_SEL_LSB,
g12a_toacodec_mux_texts);
static SOC_ENUM_SINGLE_DECL(sm1_toacodec_mux_enum, TOACODEC_CTRL0,
CTRL0_DAT_SEL_SM1_LSB,
g12a_toacodec_mux_texts);
static const struct snd_kcontrol_new g12a_toacodec_mux =
SOC_DAPM_ENUM_EXT("Source", g12a_toacodec_mux_enum,
snd_soc_dapm_get_enum_double,
g12a_toacodec_mux_put_enum);
static const struct snd_kcontrol_new sm1_toacodec_mux =
SOC_DAPM_ENUM_EXT("Source", sm1_toacodec_mux_enum,
snd_soc_dapm_get_enum_double,
g12a_toacodec_mux_put_enum);
static const struct snd_kcontrol_new g12a_toacodec_out_enable =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", TOACODEC_CTRL0,
CTRL0_ENABLE_SHIFT, 1, 0);
static const struct snd_soc_dapm_widget g12a_toacodec_widgets[] = {
SND_SOC_DAPM_MUX("SRC", SND_SOC_NOPM, 0, 0,
&g12a_toacodec_mux),
SND_SOC_DAPM_SWITCH("OUT EN", SND_SOC_NOPM, 0, 0,
&g12a_toacodec_out_enable),
};
static const struct snd_soc_dapm_widget sm1_toacodec_widgets[] = {
SND_SOC_DAPM_MUX("SRC", SND_SOC_NOPM, 0, 0,
&sm1_toacodec_mux),
SND_SOC_DAPM_SWITCH("OUT EN", SND_SOC_NOPM, 0, 0,
&g12a_toacodec_out_enable),
};
static int g12a_toacodec_input_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct meson_codec_glue_input *data;
int ret;
ret = meson_codec_glue_input_hw_params(substream, params, dai);
if (ret)
return ret;
/* The glue will provide 1 lane out of the 4 to the output */
data = meson_codec_glue_input_get_data(dai);
data->params.channels_min = min_t(unsigned int, TOACODEC_OUT_CHMAX,
data->params.channels_min);
data->params.channels_max = min_t(unsigned int, TOACODEC_OUT_CHMAX,
data->params.channels_max);
return 0;
}
static const struct snd_soc_dai_ops g12a_toacodec_input_ops = {
.probe = meson_codec_glue_input_dai_probe,
.remove = meson_codec_glue_input_dai_remove,
.hw_params = g12a_toacodec_input_hw_params,
.set_fmt = meson_codec_glue_input_set_fmt,
};
static const struct snd_soc_dai_ops g12a_toacodec_output_ops = {
.startup = meson_codec_glue_output_startup,
};
#define TOACODEC_STREAM(xname, xsuffix, xchmax) \
{ \
.stream_name = xname " " xsuffix, \
.channels_min = 1, \
.channels_max = (xchmax), \
.rate_min = 5512, \
.rate_max = 192000, \
.formats = AXG_TDM_FORMATS, \
}
#define TOACODEC_INPUT(xname, xid) { \
.name = xname, \
.id = (xid), \
.playback = TOACODEC_STREAM(xname, "Playback", 8), \
.ops = &g12a_toacodec_input_ops, \
}
#define TOACODEC_OUTPUT(xname, xid) { \
.name = xname, \
.id = (xid), \
.capture = TOACODEC_STREAM(xname, "Capture", TOACODEC_OUT_CHMAX), \
.ops = &g12a_toacodec_output_ops, \
}
static struct snd_soc_dai_driver g12a_toacodec_dai_drv[] = {
TOACODEC_INPUT("IN A", TOACODEC_IN_A),
TOACODEC_INPUT("IN B", TOACODEC_IN_B),
TOACODEC_INPUT("IN C", TOACODEC_IN_C),
TOACODEC_OUTPUT("OUT", TOACODEC_OUT),
};
static int g12a_toacodec_component_probe(struct snd_soc_component *c)
{
/* Initialize the static clock parameters */
return snd_soc_component_write(c, TOACODEC_CTRL0,
CTRL0_BLK_CAP_INV);
}
static int sm1_toacodec_component_probe(struct snd_soc_component *c)
{
/* Initialize the static clock parameters */
return snd_soc_component_write(c, TOACODEC_CTRL0,
CTRL0_BLK_CAP_INV_SM1);
}
static const struct snd_soc_dapm_route g12a_toacodec_routes[] = {
{ "SRC", "I2S A", "IN A Playback" },
{ "SRC", "I2S B", "IN B Playback" },
{ "SRC", "I2S C", "IN C Playback" },
{ "OUT EN", "Switch", "SRC" },
{ "OUT Capture", NULL, "OUT EN" },
};
static const struct snd_kcontrol_new g12a_toacodec_controls[] = {
SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL, 3, 0),
};
static const struct snd_kcontrol_new sm1_toacodec_controls[] = {
SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 3, 0),
};
static const struct snd_soc_component_driver g12a_toacodec_component_drv = {
.probe = g12a_toacodec_component_probe,
.controls = g12a_toacodec_controls,
.num_controls = ARRAY_SIZE(g12a_toacodec_controls),
.dapm_widgets = g12a_toacodec_widgets,
.num_dapm_widgets = ARRAY_SIZE(g12a_toacodec_widgets),
.dapm_routes = g12a_toacodec_routes,
.num_dapm_routes = ARRAY_SIZE(g12a_toacodec_routes),
.endianness = 1,
};
static const struct snd_soc_component_driver sm1_toacodec_component_drv = {
.probe = sm1_toacodec_component_probe,
.controls = sm1_toacodec_controls,
.num_controls = ARRAY_SIZE(sm1_toacodec_controls),
.dapm_widgets = sm1_toacodec_widgets,
.num_dapm_widgets = ARRAY_SIZE(sm1_toacodec_widgets),
.dapm_routes = g12a_toacodec_routes,
.num_dapm_routes = ARRAY_SIZE(g12a_toacodec_routes),
.endianness = 1,
};
static const struct regmap_config g12a_toacodec_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static const struct g12a_toacodec_match_data g12a_toacodec_match_data = {
.component_drv = &g12a_toacodec_component_drv,
.field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 14, 15),
.field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 8, 9),
.field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 5),
};
static const struct g12a_toacodec_match_data sm1_toacodec_match_data = {
.component_drv = &sm1_toacodec_component_drv,
.field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 18, 19),
.field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 12, 14),
.field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6),
};
static const struct of_device_id g12a_toacodec_of_match[] = {
{
.compatible = "amlogic,g12a-toacodec",
.data = &g12a_toacodec_match_data,
},
{
.compatible = "amlogic,sm1-toacodec",
.data = &sm1_toacodec_match_data,
},
{}
};
MODULE_DEVICE_TABLE(of, g12a_toacodec_of_match);
static int g12a_toacodec_probe(struct platform_device *pdev)
{
const struct g12a_toacodec_match_data *data;
struct device *dev = &pdev->dev;
struct g12a_toacodec *priv;
void __iomem *regs;
struct regmap *map;
int ret;
data = device_get_match_data(dev);
if (!data) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
ret = device_reset(dev);
if (ret)
return ret;
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
map = devm_regmap_init_mmio(dev, regs, &g12a_toacodec_regmap_cfg);
if (IS_ERR(map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(map));
return PTR_ERR(map);
}
priv->field_dat_sel = devm_regmap_field_alloc(dev, map, data->field_dat_sel);
if (IS_ERR(priv->field_dat_sel))
return PTR_ERR(priv->field_dat_sel);
priv->field_lrclk_sel = devm_regmap_field_alloc(dev, map, data->field_lrclk_sel);
if (IS_ERR(priv->field_lrclk_sel))
return PTR_ERR(priv->field_lrclk_sel);
priv->field_bclk_sel = devm_regmap_field_alloc(dev, map, data->field_bclk_sel);
if (IS_ERR(priv->field_bclk_sel))
return PTR_ERR(priv->field_bclk_sel);
return devm_snd_soc_register_component(dev,
data->component_drv, g12a_toacodec_dai_drv,
ARRAY_SIZE(g12a_toacodec_dai_drv));
}
static struct platform_driver g12a_toacodec_pdrv = {
.driver = {
.name = G12A_TOACODEC_DRV_NAME,
.of_match_table = g12a_toacodec_of_match,
},
.probe = g12a_toacodec_probe,
};
module_platform_driver(g12a_toacodec_pdrv);
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_DESCRIPTION("Amlogic G12a To Internal DAC Codec Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/g12a-toacodec.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/pcm_params.h>
#define SPDIFIN_CTRL0 0x00
#define SPDIFIN_CTRL0_EN BIT(31)
#define SPDIFIN_CTRL0_RST_OUT BIT(29)
#define SPDIFIN_CTRL0_RST_IN BIT(28)
#define SPDIFIN_CTRL0_WIDTH_SEL BIT(24)
#define SPDIFIN_CTRL0_STATUS_CH_SHIFT 11
#define SPDIFIN_CTRL0_STATUS_SEL GENMASK(10, 8)
#define SPDIFIN_CTRL0_SRC_SEL GENMASK(5, 4)
#define SPDIFIN_CTRL0_CHK_VALID BIT(3)
#define SPDIFIN_CTRL1 0x04
#define SPDIFIN_CTRL1_BASE_TIMER GENMASK(19, 0)
#define SPDIFIN_CTRL1_IRQ_MASK GENMASK(27, 20)
#define SPDIFIN_CTRL2 0x08
#define SPDIFIN_THRES_PER_REG 3
#define SPDIFIN_THRES_WIDTH 10
#define SPDIFIN_CTRL3 0x0c
#define SPDIFIN_CTRL4 0x10
#define SPDIFIN_TIMER_PER_REG 4
#define SPDIFIN_TIMER_WIDTH 8
#define SPDIFIN_CTRL5 0x14
#define SPDIFIN_CTRL6 0x18
#define SPDIFIN_STAT0 0x1c
#define SPDIFIN_STAT0_MODE GENMASK(30, 28)
#define SPDIFIN_STAT0_MAXW GENMASK(17, 8)
#define SPDIFIN_STAT0_IRQ GENMASK(7, 0)
#define SPDIFIN_IRQ_MODE_CHANGED BIT(2)
#define SPDIFIN_STAT1 0x20
#define SPDIFIN_STAT2 0x24
#define SPDIFIN_MUTE_VAL 0x28
#define SPDIFIN_MODE_NUM 7
struct axg_spdifin_cfg {
const unsigned int *mode_rates;
unsigned int ref_rate;
};
struct axg_spdifin {
const struct axg_spdifin_cfg *conf;
struct regmap *map;
struct clk *refclk;
struct clk *pclk;
};
/*
* TODO:
* It would have been nice to check the actual rate against the sample rate
* requested in hw_params(). Unfortunately, I was not able to make the mode
* detection and IRQ work reliably:
*
* 1. IRQs are generated on mode change only, so there is no notification
* on transition between no signal and mode 0 (32kHz).
* 2. Mode detection very often has glitches, and may detects the
* lowest or the highest mode before zeroing in on the actual mode.
*
* This makes calling snd_pcm_stop() difficult to get right. Even notifying
* the kcontrol would be very unreliable at this point.
* Let's keep things simple until the magic spell that makes this work is
* found.
*/
static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
{
unsigned int stat, mode, rate = 0;
regmap_read(priv->map, SPDIFIN_STAT0, &stat);
mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
/*
* If max width is zero, we are not capturing anything.
* Also Sometimes, when the capture is on but there is no data,
* mode is SPDIFIN_MODE_NUM, but not always ...
*/
if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
mode < SPDIFIN_MODE_NUM)
rate = priv->conf->mode_rates[mode];
return rate;
}
static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
/* Apply both reset */
regmap_update_bits(priv->map, SPDIFIN_CTRL0,
SPDIFIN_CTRL0_RST_OUT |
SPDIFIN_CTRL0_RST_IN,
0);
/* Clear out reset before in reset */
regmap_update_bits(priv->map, SPDIFIN_CTRL0,
SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
regmap_update_bits(priv->map, SPDIFIN_CTRL0,
SPDIFIN_CTRL0_RST_IN, SPDIFIN_CTRL0_RST_IN);
return 0;
}
static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
unsigned int val,
unsigned int num_per_reg,
unsigned int base_reg,
unsigned int width)
{
uint64_t offset = mode;
unsigned int reg, shift, rem;
rem = do_div(offset, num_per_reg);
reg = offset * regmap_get_reg_stride(map) + base_reg;
shift = width * (num_per_reg - 1 - rem);
regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
val << shift);
}
static void axg_spdifin_write_timer(struct regmap *map, int mode,
unsigned int val)
{
axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG,
SPDIFIN_CTRL4, SPDIFIN_TIMER_WIDTH);
}
static void axg_spdifin_write_threshold(struct regmap *map, int mode,
unsigned int val)
{
axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG,
SPDIFIN_CTRL2, SPDIFIN_THRES_WIDTH);
}
static unsigned int axg_spdifin_mode_timer(struct axg_spdifin *priv,
int mode,
unsigned int rate)
{
/*
* Number of period of the reference clock during a period of the
* input signal reference clock
*/
return rate / (128 * priv->conf->mode_rates[mode]);
}
static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
struct axg_spdifin *priv)
{
unsigned int rate, t_next;
int ret, i = SPDIFIN_MODE_NUM - 1;
/* Set spdif input reference clock */
ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
if (ret) {
dev_err(dai->dev, "reference clock rate set failed\n");
return ret;
}
/*
* The rate actually set might be slightly different, get
* the actual rate for the following mode calculation
*/
rate = clk_get_rate(priv->refclk);
/* HW will update mode every 1ms */
regmap_update_bits(priv->map, SPDIFIN_CTRL1,
SPDIFIN_CTRL1_BASE_TIMER,
FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
/* Threshold based on the minimum width between two edges */
regmap_update_bits(priv->map, SPDIFIN_CTRL0,
SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
/* Calculate the last timer which has no threshold */
t_next = axg_spdifin_mode_timer(priv, i, rate);
axg_spdifin_write_timer(priv->map, i, t_next);
do {
unsigned int t;
i -= 1;
/* Calculate the timer */
t = axg_spdifin_mode_timer(priv, i, rate);
/* Set the timer value */
axg_spdifin_write_timer(priv->map, i, t);
/* Set the threshold value */
axg_spdifin_write_threshold(priv->map, i, t + t_next);
/* Save the current timer for the next threshold calculation */
t_next = t;
} while (i > 0);
return 0;
}
static int axg_spdifin_dai_probe(struct snd_soc_dai *dai)
{
struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
int ret;
ret = clk_prepare_enable(priv->pclk);
if (ret) {
dev_err(dai->dev, "failed to enable pclk\n");
return ret;
}
ret = axg_spdifin_sample_mode_config(dai, priv);
if (ret) {
dev_err(dai->dev, "mode configuration failed\n");
goto pclk_err;
}
ret = clk_prepare_enable(priv->refclk);
if (ret) {
dev_err(dai->dev,
"failed to enable spdifin reference clock\n");
goto pclk_err;
}
regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
SPDIFIN_CTRL0_EN);
return 0;
pclk_err:
clk_disable_unprepare(priv->pclk);
return ret;
}
static int axg_spdifin_dai_remove(struct snd_soc_dai *dai)
{
struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
clk_disable_unprepare(priv->refclk);
clk_disable_unprepare(priv->pclk);
return 0;
}
static const struct snd_soc_dai_ops axg_spdifin_ops = {
.probe = axg_spdifin_dai_probe,
.remove = axg_spdifin_dai_remove,
.prepare = axg_spdifin_prepare,
};
static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int axg_spdifin_get_status_mask(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int i;
for (i = 0; i < 24; i++)
ucontrol->value.iec958.status[i] = 0xff;
return 0;
}
static int axg_spdifin_get_status(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
int i, j;
for (i = 0; i < 6; i++) {
unsigned int val;
regmap_update_bits(priv->map, SPDIFIN_CTRL0,
SPDIFIN_CTRL0_STATUS_SEL,
FIELD_PREP(SPDIFIN_CTRL0_STATUS_SEL, i));
regmap_read(priv->map, SPDIFIN_STAT1, &val);
for (j = 0; j < 4; j++) {
unsigned int offset = i * 4 + j;
ucontrol->value.iec958.status[offset] =
(val >> (j * 8)) & 0xff;
}
}
return 0;
}
#define AXG_SPDIFIN_IEC958_MASK \
{ \
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), \
.info = axg_spdifin_iec958_info, \
.get = axg_spdifin_get_status_mask, \
}
#define AXG_SPDIFIN_IEC958_STATUS \
{ \
.access = (SNDRV_CTL_ELEM_ACCESS_READ | \
SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE), \
.info = axg_spdifin_iec958_info, \
.get = axg_spdifin_get_status, \
}
static const char * const spdifin_chsts_src_texts[] = {
"A", "B",
};
static SOC_ENUM_SINGLE_DECL(axg_spdifin_chsts_src_enum, SPDIFIN_CTRL0,
SPDIFIN_CTRL0_STATUS_CH_SHIFT,
spdifin_chsts_src_texts);
static int axg_spdifin_rate_lock_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 192000;
return 0;
}
static int axg_spdifin_rate_lock_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);
return 0;
}
#define AXG_SPDIFIN_LOCK_RATE(xname) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
.access = (SNDRV_CTL_ELEM_ACCESS_READ | \
SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
.get = axg_spdifin_rate_lock_get, \
.info = axg_spdifin_rate_lock_info, \
.name = xname, \
}
static const struct snd_kcontrol_new axg_spdifin_controls[] = {
AXG_SPDIFIN_LOCK_RATE("Capture Rate Lock"),
SOC_DOUBLE("Capture Switch", SPDIFIN_CTRL0, 7, 6, 1, 1),
SOC_ENUM(SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Src",
axg_spdifin_chsts_src_enum),
AXG_SPDIFIN_IEC958_MASK,
AXG_SPDIFIN_IEC958_STATUS,
};
static const struct snd_soc_component_driver axg_spdifin_component_drv = {
.controls = axg_spdifin_controls,
.num_controls = ARRAY_SIZE(axg_spdifin_controls),
.legacy_dai_naming = 1,
};
static const struct regmap_config axg_spdifin_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = SPDIFIN_MUTE_VAL,
};
static const unsigned int axg_spdifin_mode_rates[SPDIFIN_MODE_NUM] = {
32000, 44100, 48000, 88200, 96000, 176400, 192000,
};
static const struct axg_spdifin_cfg axg_cfg = {
.mode_rates = axg_spdifin_mode_rates,
.ref_rate = 333333333,
};
static const struct of_device_id axg_spdifin_of_match[] = {
{
.compatible = "amlogic,axg-spdifin",
.data = &axg_cfg,
}, {}
};
MODULE_DEVICE_TABLE(of, axg_spdifin_of_match);
static struct snd_soc_dai_driver *
axg_spdifin_get_dai_drv(struct device *dev, struct axg_spdifin *priv)
{
struct snd_soc_dai_driver *drv;
int i;
drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return ERR_PTR(-ENOMEM);
drv->name = "SPDIF Input";
drv->ops = &axg_spdifin_ops;
drv->capture.stream_name = "Capture";
drv->capture.channels_min = 1;
drv->capture.channels_max = 2;
drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
for (i = 0; i < SPDIFIN_MODE_NUM; i++) {
unsigned int rb =
snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);
if (rb == SNDRV_PCM_RATE_KNOT)
return ERR_PTR(-EINVAL);
drv->capture.rates |= rb;
}
return drv;
}
static int axg_spdifin_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct axg_spdifin *priv;
struct snd_soc_dai_driver *dai_drv;
void __iomem *regs;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->conf = of_device_get_match_data(dev);
if (!priv->conf) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);
if (IS_ERR(priv->map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(priv->map));
return PTR_ERR(priv->map);
}
priv->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(priv->pclk))
return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");
priv->refclk = devm_clk_get(dev, "refclk");
if (IS_ERR(priv->refclk))
return dev_err_probe(dev, PTR_ERR(priv->refclk), "failed to get mclk\n");
dai_drv = axg_spdifin_get_dai_drv(dev, priv);
if (IS_ERR(dai_drv)) {
dev_err(dev, "failed to get dai driver: %ld\n",
PTR_ERR(dai_drv));
return PTR_ERR(dai_drv);
}
return devm_snd_soc_register_component(dev, &axg_spdifin_component_drv,
dai_drv, 1);
}
static struct platform_driver axg_spdifin_pdrv = {
.probe = axg_spdifin_probe,
.driver = {
.name = "axg-spdifin",
.of_match_table = axg_spdifin_of_match,
},
};
module_platform_driver(axg_spdifin_pdrv);
MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-spdifin.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <[email protected]>
#include <linux/clk.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "axg-fifo.h"
/*
* This file implements the platform operations common to the playback and
* capture frontend DAI. The logic behind this two types of fifo is very
* similar but some difference exist.
* These differences are handled in the respective DAI drivers
*/
static struct snd_pcm_hardware axg_fifo_hw = {
.info = (SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
.formats = AXG_FIFO_FORMATS,
.rate_min = 5512,
.rate_max = 192000,
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
.period_bytes_min = AXG_FIFO_BURST,
.period_bytes_max = UINT_MAX,
.periods_min = 2,
.periods_max = UINT_MAX,
/* No real justification for this */
.buffer_bytes_max = 1 * 1024 * 1024,
};
static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss)
{
struct snd_soc_pcm_runtime *rtd = ss->private_data;
return asoc_rtd_to_cpu(rtd, 0);
}
static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
{
struct snd_soc_dai *dai = axg_fifo_dai(ss);
return snd_soc_dai_get_drvdata(dai);
}
static struct device *axg_fifo_dev(struct snd_pcm_substream *ss)
{
struct snd_soc_dai *dai = axg_fifo_dai(ss);
return dai->dev;
}
static void __dma_enable(struct axg_fifo *fifo, bool enable)
{
regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
enable ? CTRL0_DMA_EN : 0);
}
int axg_fifo_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *ss, int cmd)
{
struct axg_fifo *fifo = axg_fifo_data(ss);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
__dma_enable(fifo, true);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
__dma_enable(fifo, false);
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_trigger);
snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct axg_fifo *fifo = axg_fifo_data(ss);
struct snd_pcm_runtime *runtime = ss->runtime;
unsigned int addr;
regmap_read(fifo->map, FIFO_STATUS2, &addr);
return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_pointer);
int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *ss,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = ss->runtime;
struct axg_fifo *fifo = axg_fifo_data(ss);
unsigned int burst_num, period, threshold, irq_en;
dma_addr_t end_ptr;
period = params_period_bytes(params);
/* Setup dma memory pointers */
end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
/* Setup interrupt periodicity */
burst_num = period / AXG_FIFO_BURST;
regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
/*
* Start the fifo request on the smallest of the following:
* - Half the fifo size
* - Half the period size
*/
threshold = min(period / 2, fifo->depth / 2);
/*
* With the threshold in bytes, register value is:
* V = (threshold / burst) - 1
*/
threshold /= AXG_FIFO_BURST;
regmap_field_write(fifo->field_threshold,
threshold ? threshold - 1 : 0);
/* Enable irq if necessary */
irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT;
regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
CTRL0_INT_EN(irq_en));
return 0;
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_params);
int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *ss,
struct snd_pcm_hw_params *params)
{
struct axg_fifo *fifo = axg_fifo_data(ss);
struct snd_pcm_runtime *runtime = ss->runtime;
int ret;
ret = axg_fifo_pcm_hw_params(component, ss, params);
if (ret)
return ret;
/* Set the initial memory address of the DMA */
regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
return 0;
}
EXPORT_SYMBOL_GPL(g12a_fifo_pcm_hw_params);
int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct axg_fifo *fifo = axg_fifo_data(ss);
/* Disable the block count irq */
regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
return 0;
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free);
static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
{
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_INT_CLR(FIFO_INT_MASK),
CTRL1_INT_CLR(mask));
/* Clear must also be cleared */
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_INT_CLR(FIFO_INT_MASK),
0);
}
static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
{
struct snd_pcm_substream *ss = dev_id;
struct axg_fifo *fifo = axg_fifo_data(ss);
unsigned int status;
regmap_read(fifo->map, FIFO_STATUS1, &status);
status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
if (status & FIFO_INT_COUNT_REPEAT)
snd_pcm_period_elapsed(ss);
else
dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
status);
/* Ack irqs */
axg_fifo_ack_irq(fifo, status);
return IRQ_RETVAL(status);
}
int axg_fifo_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct axg_fifo *fifo = axg_fifo_data(ss);
struct device *dev = axg_fifo_dev(ss);
int ret;
snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw);
/*
* Make sure the buffer and period size are multiple of the FIFO
* burst
*/
ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
AXG_FIFO_BURST);
if (ret)
return ret;
ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
AXG_FIFO_BURST);
if (ret)
return ret;
ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
dev_name(dev), ss);
if (ret)
return ret;
/* Enable pclk to access registers and clock the fifo ip */
ret = clk_prepare_enable(fifo->pclk);
if (ret)
goto free_irq;
/* Setup status2 so it reports the memory pointer */
regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_STATUS2_SEL_MASK,
CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
/* Make sure the dma is initially disabled */
__dma_enable(fifo, false);
/* Disable irqs until params are ready */
regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_INT_EN(FIFO_INT_MASK), 0);
/* Clear any pending interrupt */
axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
/* Take memory arbitror out of reset */
ret = reset_control_deassert(fifo->arb);
if (ret)
goto free_clk;
return 0;
free_clk:
clk_disable_unprepare(fifo->pclk);
free_irq:
free_irq(fifo->irq, ss);
return ret;
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_open);
int axg_fifo_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct axg_fifo *fifo = axg_fifo_data(ss);
int ret;
/* Put the memory arbitror back in reset */
ret = reset_control_assert(fifo->arb);
/* Disable fifo ip and register access */
clk_disable_unprepare(fifo->pclk);
/* remove IRQ */
free_irq(fifo->irq, ss);
return ret;
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_close);
int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
{
struct snd_card *card = rtd->card->snd_card;
size_t size = axg_fifo_hw.buffer_bytes_max;
snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream,
SNDRV_DMA_TYPE_DEV, card->dev,
size, size);
return 0;
}
EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
static const struct regmap_config axg_fifo_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = FIFO_CTRL2,
};
int axg_fifo_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct axg_fifo_match_data *data;
struct axg_fifo *fifo;
void __iomem *regs;
int ret;
data = of_device_get_match_data(dev);
if (!data) {
dev_err(dev, "failed to match device\n");
return -ENODEV;
}
fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
if (!fifo)
return -ENOMEM;
platform_set_drvdata(pdev, fifo);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
if (IS_ERR(fifo->map)) {
dev_err(dev, "failed to init regmap: %ld\n",
PTR_ERR(fifo->map));
return PTR_ERR(fifo->map);
}
fifo->pclk = devm_clk_get(dev, NULL);
if (IS_ERR(fifo->pclk))
return dev_err_probe(dev, PTR_ERR(fifo->pclk), "failed to get pclk\n");
fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(fifo->arb))
return dev_err_probe(dev, PTR_ERR(fifo->arb), "failed to get arb reset\n");
fifo->irq = of_irq_get(dev->of_node, 0);
if (fifo->irq <= 0) {
dev_err(dev, "failed to get irq: %d\n", fifo->irq);
return fifo->irq;
}
fifo->field_threshold =
devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
if (IS_ERR(fifo->field_threshold))
return PTR_ERR(fifo->field_threshold);
ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
&fifo->depth);
if (ret) {
/* Error out for anything but a missing property */
if (ret != -EINVAL)
return ret;
/*
* If the property is missing, it might be because of an old
* DT. In such case, assume the smallest known fifo depth
*/
fifo->depth = 256;
dev_warn(dev, "fifo depth not found, assume %u bytes\n",
fifo->depth);
}
return devm_snd_soc_register_component(dev, data->component_drv,
data->dai_drv, 1);
}
EXPORT_SYMBOL_GPL(axg_fifo_probe);
MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");
MODULE_AUTHOR("Jerome Brunet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/meson/axg-fifo.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This driver supports the digital controls for the internal codec
* found in Allwinner's A33 SoCs.
*
* (C) Copyright 2010-2016
* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
* huangxin <[email protected]>
* Mylène Josserand <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/log2.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#define SUN8I_SYSCLK_CTL 0x00c
#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8)
#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7
#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4)
#define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0)
#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0)
#define SUN8I_MOD_CLK_ENA 0x010
#define SUN8I_MOD_CLK_ENA_AIF1 15
#define SUN8I_MOD_CLK_ENA_AIF2 14
#define SUN8I_MOD_CLK_ENA_AIF3 13
#define SUN8I_MOD_CLK_ENA_ADC 3
#define SUN8I_MOD_CLK_ENA_DAC 2
#define SUN8I_MOD_RST_CTL 0x014
#define SUN8I_MOD_RST_CTL_AIF1 15
#define SUN8I_MOD_RST_CTL_AIF2 14
#define SUN8I_MOD_RST_CTL_AIF3 13
#define SUN8I_MOD_RST_CTL_ADC 3
#define SUN8I_MOD_RST_CTL_DAC 2
#define SUN8I_SYS_SR_CTRL 0x018
#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n)))
#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15
#define SUN8I_AIF_CLK_CTRL_CLK_INV 13
#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9
#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6
#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4
#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2
#define SUN8I_AIF1_ADCDAT_CTRL 0x044
#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15
#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14
#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10
#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8
#define SUN8I_AIF1_DACDAT_CTRL 0x048
#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10
#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8
#define SUN8I_AIF1_MXR_SRC 0x04c
#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15
#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14
#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13
#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12
#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11
#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10
#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9
#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8
#define SUN8I_AIF1_VOL_CTRL1 0x050
#define SUN8I_AIF1_VOL_CTRL1_AD0L_VOL 8
#define SUN8I_AIF1_VOL_CTRL1_AD0R_VOL 0
#define SUN8I_AIF1_VOL_CTRL3 0x058
#define SUN8I_AIF1_VOL_CTRL3_DA0L_VOL 8
#define SUN8I_AIF1_VOL_CTRL3_DA0R_VOL 0
#define SUN8I_AIF2_ADCDAT_CTRL 0x084
#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15
#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14
#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC 10
#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC 8
#define SUN8I_AIF2_DACDAT_CTRL 0x088
#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15
#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14
#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10
#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8
#define SUN8I_AIF2_MXR_SRC 0x08c
#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15
#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14
#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR 13
#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL 12
#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R 11
#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10
#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9
#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8
#define SUN8I_AIF2_VOL_CTRL1 0x090
#define SUN8I_AIF2_VOL_CTRL1_ADCL_VOL 8
#define SUN8I_AIF2_VOL_CTRL1_ADCR_VOL 0
#define SUN8I_AIF2_VOL_CTRL2 0x098
#define SUN8I_AIF2_VOL_CTRL2_DACL_VOL 8
#define SUN8I_AIF2_VOL_CTRL2_DACR_VOL 0
#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1 (0x0 << 0)
#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2 (0x1 << 0)
#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1CLK (0x2 << 0)
#define SUN8I_AIF3_PATH_CTRL 0x0cc
#define SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC 10
#define SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC 8
#define SUN8I_AIF3_PATH_CTRL_AIF3_PINS_TRI 7
#define SUN8I_ADC_DIG_CTRL 0x100
#define SUN8I_ADC_DIG_CTRL_ENAD 15
#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2
#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1
#define SUN8I_ADC_VOL_CTRL 0x104
#define SUN8I_ADC_VOL_CTRL_ADCL_VOL 8
#define SUN8I_ADC_VOL_CTRL_ADCR_VOL 0
#define SUN8I_DAC_DIG_CTRL 0x120
#define SUN8I_DAC_DIG_CTRL_ENDA 15
#define SUN8I_DAC_VOL_CTRL 0x124
#define SUN8I_DAC_VOL_CTRL_DACL_VOL 8
#define SUN8I_DAC_VOL_CTRL_DACR_VOL 0
#define SUN8I_DAC_MXR_SRC 0x130
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8)
#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13)
#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9)
#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6)
#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4)
#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)
#define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK GENMASK(1, 0)
#define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000
#define SUN8I_CODEC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\
SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S20_3LE|\
SNDRV_PCM_FMTBIT_S24_3LE)
#define SUN8I_CODEC_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000 |\
SNDRV_PCM_RATE_KNOT)
enum {
SUN8I_CODEC_AIF1,
SUN8I_CODEC_AIF2,
SUN8I_CODEC_AIF3,
SUN8I_CODEC_NAIFS
};
struct sun8i_codec_aif {
unsigned int lrck_div_order;
unsigned int sample_rate;
unsigned int slots;
unsigned int slot_width;
unsigned int active_streams : 2;
unsigned int open_streams : 2;
};
struct sun8i_codec_quirks {
bool legacy_widgets : 1;
bool lrck_inversion : 1;
};
struct sun8i_codec {
struct regmap *regmap;
struct clk *clk_module;
const struct sun8i_codec_quirks *quirks;
struct sun8i_codec_aif aifs[SUN8I_CODEC_NAIFS];
unsigned int sysclk_rate;
int sysclk_refcnt;
};
static struct snd_soc_dai_driver sun8i_codec_dais[];
static int sun8i_codec_runtime_resume(struct device *dev)
{
struct sun8i_codec *scodec = dev_get_drvdata(dev);
int ret;
regcache_cache_only(scodec->regmap, false);
ret = regcache_sync(scodec->regmap);
if (ret) {
dev_err(dev, "Failed to sync regmap cache\n");
return ret;
}
return 0;
}
static int sun8i_codec_runtime_suspend(struct device *dev)
{
struct sun8i_codec *scodec = dev_get_drvdata(dev);
regcache_cache_only(scodec->regmap, true);
regcache_mark_dirty(scodec->regmap);
return 0;
}
static int sun8i_codec_get_hw_rate(unsigned int sample_rate)
{
switch (sample_rate) {
case 7350:
case 8000:
return 0x0;
case 11025:
return 0x1;
case 12000:
return 0x2;
case 14700:
case 16000:
return 0x3;
case 22050:
return 0x4;
case 24000:
return 0x5;
case 29400:
case 32000:
return 0x6;
case 44100:
return 0x7;
case 48000:
return 0x8;
case 88200:
case 96000:
return 0x9;
case 176400:
case 192000:
return 0xa;
default:
return -EINVAL;
}
}
static int sun8i_codec_update_sample_rate(struct sun8i_codec *scodec)
{
unsigned int max_rate = 0;
int hw_rate, i;
for (i = SUN8I_CODEC_AIF1; i < SUN8I_CODEC_NAIFS; ++i) {
struct sun8i_codec_aif *aif = &scodec->aifs[i];
if (aif->active_streams)
max_rate = max(max_rate, aif->sample_rate);
}
/* Set the sample rate for ADC->DAC passthrough when no AIF is active. */
if (!max_rate)
max_rate = SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE;
hw_rate = sun8i_codec_get_hw_rate(max_rate);
if (hw_rate < 0)
return hw_rate;
regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
hw_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
return 0;
}
static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
u32 dsp_format, format, invert, value;
/* clock masters */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC: /* Codec slave, DAI master */
value = 0x1;
break;
case SND_SOC_DAIFMT_CBP_CFP: /* Codec Master, DAI slave */
value = 0x0;
break;
default:
return -EINVAL;
}
if (dai->id == SUN8I_CODEC_AIF3) {
/* AIF3 only supports master mode. */
if (value)
return -EINVAL;
/* Use the AIF2 BCLK and LRCK for AIF3. */
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK,
SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2);
} else {
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD),
value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
}
/* DAI format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = 0x0;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = 0x1;
break;
case SND_SOC_DAIFMT_RIGHT_J:
format = 0x2;
break;
case SND_SOC_DAIFMT_DSP_A:
format = 0x3;
dsp_format = 0x0; /* Set LRCK_INV to 0 */
break;
case SND_SOC_DAIFMT_DSP_B:
format = 0x3;
dsp_format = 0x1; /* Set LRCK_INV to 1 */
break;
default:
return -EINVAL;
}
if (dai->id == SUN8I_CODEC_AIF3) {
/* AIF3 only supports DSP mode. */
if (format != 3)
return -EINVAL;
} else {
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK,
format << SUN8I_AIF_CLK_CTRL_DATA_FMT);
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF: /* Normal */
invert = 0x0;
break;
case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */
invert = 0x1;
break;
case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */
invert = 0x2;
break;
case SND_SOC_DAIFMT_IB_IF: /* Both inverted */
invert = 0x3;
break;
default:
return -EINVAL;
}
if (format == 0x3) {
/* Inverted LRCK is not available in DSP mode. */
if (invert & BIT(0))
return -EINVAL;
/* Instead, the bit selects between DSP A/B formats. */
invert |= dsp_format;
} else {
/*
* It appears that the DAI and the codec in the A33 SoC don't
* share the same polarity for the LRCK signal when they mean
* 'normal' and 'inverted' in the datasheet.
*
* Since the DAI here is our regular i2s driver that have been
* tested with way more codecs than just this one, it means
* that the codec probably gets it backward, and we have to
* invert the value here.
*/
invert ^= scodec->quirks->lrck_inversion;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_CLK_INV_MASK,
invert << SUN8I_AIF_CLK_CTRL_CLK_INV);
return 0;
}
static int sun8i_codec_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];
if (slot_width && !is_power_of_2(slot_width))
return -EINVAL;
aif->slots = slots;
aif->slot_width = slot_width;
return 0;
}
static const unsigned int sun8i_codec_rates[] = {
7350, 8000, 11025, 12000, 14700, 16000, 22050, 24000,
29400, 32000, 44100, 48000, 88200, 96000, 176400, 192000,
};
static const struct snd_pcm_hw_constraint_list sun8i_codec_all_rates = {
.list = sun8i_codec_rates,
.count = ARRAY_SIZE(sun8i_codec_rates),
};
static const struct snd_pcm_hw_constraint_list sun8i_codec_22M_rates = {
.list = sun8i_codec_rates,
.count = ARRAY_SIZE(sun8i_codec_rates),
.mask = 0x5555,
};
static const struct snd_pcm_hw_constraint_list sun8i_codec_24M_rates = {
.list = sun8i_codec_rates,
.count = ARRAY_SIZE(sun8i_codec_rates),
.mask = 0xaaaa,
};
static int sun8i_codec_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
const struct snd_pcm_hw_constraint_list *list;
/* hw_constraints is not relevant for codec2codec DAIs. */
if (dai->id != SUN8I_CODEC_AIF1)
return 0;
if (!scodec->sysclk_refcnt)
list = &sun8i_codec_all_rates;
else if (scodec->sysclk_rate == 22579200)
list = &sun8i_codec_22M_rates;
else if (scodec->sysclk_rate == 24576000)
list = &sun8i_codec_24M_rates;
else
return -EINVAL;
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, list);
}
struct sun8i_codec_clk_div {
u8 div;
u8 val;
};
static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
{ .div = 1, .val = 0 },
{ .div = 2, .val = 1 },
{ .div = 4, .val = 2 },
{ .div = 6, .val = 3 },
{ .div = 8, .val = 4 },
{ .div = 12, .val = 5 },
{ .div = 16, .val = 6 },
{ .div = 24, .val = 7 },
{ .div = 32, .val = 8 },
{ .div = 48, .val = 9 },
{ .div = 64, .val = 10 },
{ .div = 96, .val = 11 },
{ .div = 128, .val = 12 },
{ .div = 192, .val = 13 },
};
static int sun8i_codec_get_bclk_div(unsigned int sysclk_rate,
unsigned int lrck_div_order,
unsigned int sample_rate)
{
unsigned int div = sysclk_rate / sample_rate >> lrck_div_order;
int i;
for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
if (bdiv->div == div)
return bdiv->val;
}
return -EINVAL;
}
static int sun8i_codec_get_lrck_div_order(unsigned int slots,
unsigned int slot_width)
{
unsigned int div = slots * slot_width;
if (div < 16 || div > 256)
return -EINVAL;
return order_base_2(div);
}
static unsigned int sun8i_codec_get_sysclk_rate(unsigned int sample_rate)
{
return (sample_rate % 4000) ? 22579200 : 24576000;
}
static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];
unsigned int sample_rate = params_rate(params);
unsigned int slots = aif->slots ?: params_channels(params);
unsigned int slot_width = aif->slot_width ?: params_width(params);
unsigned int sysclk_rate = sun8i_codec_get_sysclk_rate(sample_rate);
int bclk_div, lrck_div_order, ret, word_size;
u32 clk_reg;
/* word size */
switch (params_width(params)) {
case 8:
word_size = 0x0;
break;
case 16:
word_size = 0x1;
break;
case 20:
word_size = 0x2;
break;
case 24:
word_size = 0x3;
break;
default:
return -EINVAL;
}
regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id),
SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK,
word_size << SUN8I_AIF_CLK_CTRL_WORD_SIZ);
/* LRCK divider (BCLK/LRCK ratio) */
lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width);
if (lrck_div_order < 0)
return lrck_div_order;
if (dai->id == SUN8I_CODEC_AIF2 || dai->id == SUN8I_CODEC_AIF3) {
/* AIF2 and AIF3 share AIF2's BCLK and LRCK generation circuitry. */
int partner = (SUN8I_CODEC_AIF2 + SUN8I_CODEC_AIF3) - dai->id;
const struct sun8i_codec_aif *partner_aif = &scodec->aifs[partner];
const char *partner_name = sun8i_codec_dais[partner].name;
if (partner_aif->open_streams &&
(lrck_div_order != partner_aif->lrck_div_order ||
sample_rate != partner_aif->sample_rate)) {
dev_err(dai->dev,
"%s sample and bit rates must match %s when both are used\n",
dai->name, partner_name);
return -EBUSY;
}
clk_reg = SUN8I_AIF_CLK_CTRL(SUN8I_CODEC_AIF2);
} else {
clk_reg = SUN8I_AIF_CLK_CTRL(dai->id);
}
regmap_update_bits(scodec->regmap, clk_reg,
SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK,
(lrck_div_order - 4) << SUN8I_AIF_CLK_CTRL_LRCK_DIV);
/* BCLK divider (SYSCLK/BCLK ratio) */
bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate);
if (bclk_div < 0)
return bclk_div;
regmap_update_bits(scodec->regmap, clk_reg,
SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
/*
* SYSCLK rate
*
* Clock rate protection is reference counted; but hw_params may be
* called many times per substream, without matching calls to hw_free.
* Protect the clock rate once per AIF, on the first hw_params call
* for the first substream. clk_set_rate() will allow clock rate
* changes on subsequent calls if only one AIF has open streams.
*/
ret = (aif->open_streams ? clk_set_rate : clk_set_rate_exclusive)(scodec->clk_module,
sysclk_rate);
if (ret == -EBUSY)
dev_err(dai->dev,
"%s sample rate (%u Hz) conflicts with other audio streams\n",
dai->name, sample_rate);
if (ret < 0)
return ret;
if (!aif->open_streams)
scodec->sysclk_refcnt++;
scodec->sysclk_rate = sysclk_rate;
aif->lrck_div_order = lrck_div_order;
aif->sample_rate = sample_rate;
aif->open_streams |= BIT(substream->stream);
return sun8i_codec_update_sample_rate(scodec);
}
static int sun8i_codec_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];
/* Drop references when the last substream for the AIF is freed. */
if (aif->open_streams != BIT(substream->stream))
goto done;
clk_rate_exclusive_put(scodec->clk_module);
scodec->sysclk_refcnt--;
aif->lrck_div_order = 0;
aif->sample_rate = 0;
done:
aif->open_streams &= ~BIT(substream->stream);
return 0;
}
static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
.set_fmt = sun8i_codec_set_fmt,
.set_tdm_slot = sun8i_codec_set_tdm_slot,
.startup = sun8i_codec_startup,
.hw_params = sun8i_codec_hw_params,
.hw_free = sun8i_codec_hw_free,
};
static struct snd_soc_dai_driver sun8i_codec_dais[] = {
{
.name = "sun8i-codec-aif1",
.id = SUN8I_CODEC_AIF1,
.ops = &sun8i_codec_dai_ops,
/* capture capabilities */
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SUN8I_CODEC_PCM_RATES,
.formats = SUN8I_CODEC_PCM_FORMATS,
.sig_bits = 24,
},
/* playback capabilities */
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SUN8I_CODEC_PCM_RATES,
.formats = SUN8I_CODEC_PCM_FORMATS,
},
.symmetric_rate = true,
.symmetric_channels = true,
.symmetric_sample_bits = true,
},
{
.name = "sun8i-codec-aif2",
.id = SUN8I_CODEC_AIF2,
.ops = &sun8i_codec_dai_ops,
/* capture capabilities */
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SUN8I_CODEC_PCM_RATES,
.formats = SUN8I_CODEC_PCM_FORMATS,
.sig_bits = 24,
},
/* playback capabilities */
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SUN8I_CODEC_PCM_RATES,
.formats = SUN8I_CODEC_PCM_FORMATS,
},
.symmetric_rate = true,
.symmetric_channels = true,
.symmetric_sample_bits = true,
},
{
.name = "sun8i-codec-aif3",
.id = SUN8I_CODEC_AIF3,
.ops = &sun8i_codec_dai_ops,
/* capture capabilities */
.capture = {
.stream_name = "AIF3 Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SUN8I_CODEC_PCM_RATES,
.formats = SUN8I_CODEC_PCM_FORMATS,
.sig_bits = 24,
},
/* playback capabilities */
.playback = {
.stream_name = "AIF3 Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SUN8I_CODEC_PCM_RATES,
.formats = SUN8I_CODEC_PCM_FORMATS,
},
.symmetric_rate = true,
.symmetric_channels = true,
.symmetric_sample_bits = true,
},
};
static const DECLARE_TLV_DB_SCALE(sun8i_codec_vol_scale, -12000, 75, 1);
static const struct snd_kcontrol_new sun8i_codec_controls[] = {
SOC_DOUBLE_TLV("AIF1 AD0 Capture Volume",
SUN8I_AIF1_VOL_CTRL1,
SUN8I_AIF1_VOL_CTRL1_AD0L_VOL,
SUN8I_AIF1_VOL_CTRL1_AD0R_VOL,
0xc0, 0, sun8i_codec_vol_scale),
SOC_DOUBLE_TLV("AIF1 DA0 Playback Volume",
SUN8I_AIF1_VOL_CTRL3,
SUN8I_AIF1_VOL_CTRL3_DA0L_VOL,
SUN8I_AIF1_VOL_CTRL3_DA0R_VOL,
0xc0, 0, sun8i_codec_vol_scale),
SOC_DOUBLE_TLV("AIF2 ADC Capture Volume",
SUN8I_AIF2_VOL_CTRL1,
SUN8I_AIF2_VOL_CTRL1_ADCL_VOL,
SUN8I_AIF2_VOL_CTRL1_ADCR_VOL,
0xc0, 0, sun8i_codec_vol_scale),
SOC_DOUBLE_TLV("AIF2 DAC Playback Volume",
SUN8I_AIF2_VOL_CTRL2,
SUN8I_AIF2_VOL_CTRL2_DACL_VOL,
SUN8I_AIF2_VOL_CTRL2_DACR_VOL,
0xc0, 0, sun8i_codec_vol_scale),
SOC_DOUBLE_TLV("ADC Capture Volume",
SUN8I_ADC_VOL_CTRL,
SUN8I_ADC_VOL_CTRL_ADCL_VOL,
SUN8I_ADC_VOL_CTRL_ADCR_VOL,
0xc0, 0, sun8i_codec_vol_scale),
SOC_DOUBLE_TLV("DAC Playback Volume",
SUN8I_DAC_VOL_CTRL,
SUN8I_DAC_VOL_CTRL_DACL_VOL,
SUN8I_DAC_VOL_CTRL_DACR_VOL,
0xc0, 0, sun8i_codec_vol_scale),
};
static int sun8i_codec_aif_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
struct sun8i_codec_aif *aif = &scodec->aifs[w->sname[3] - '1'];
int stream = w->id == snd_soc_dapm_aif_out;
if (SND_SOC_DAPM_EVENT_ON(event))
aif->active_streams |= BIT(stream);
else
aif->active_streams &= ~BIT(stream);
return sun8i_codec_update_sample_rate(scodec);
}
static const char *const sun8i_aif_stereo_mux_enum_values[] = {
"Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono"
};
static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum,
SUN8I_AIF1_ADCDAT_CTRL,
SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC,
SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC,
sun8i_aif_stereo_mux_enum_values);
static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control =
SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route",
sun8i_aif1_ad0_stereo_mux_enum);
static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_adc_stereo_mux_enum,
SUN8I_AIF2_ADCDAT_CTRL,
SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC,
SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC,
sun8i_aif_stereo_mux_enum_values);
static const struct snd_kcontrol_new sun8i_aif2_adc_stereo_mux_control =
SOC_DAPM_ENUM("AIF2 ADC Stereo Capture Route",
sun8i_aif2_adc_stereo_mux_enum);
static const char *const sun8i_aif3_adc_mux_enum_values[] = {
"None", "AIF2 ADCL", "AIF2 ADCR"
};
static SOC_ENUM_SINGLE_DECL(sun8i_aif3_adc_mux_enum,
SUN8I_AIF3_PATH_CTRL,
SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC,
sun8i_aif3_adc_mux_enum_values);
static const struct snd_kcontrol_new sun8i_aif3_adc_mux_control =
SOC_DAPM_ENUM("AIF3 ADC Source Capture Route",
sun8i_aif3_adc_mux_enum);
static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = {
SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
SUN8I_AIF1_MXR_SRC,
SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L,
SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch",
SUN8I_AIF1_MXR_SRC,
SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL,
SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
SUN8I_AIF1_MXR_SRC,
SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL,
SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
SUN8I_AIF1_MXR_SRC,
SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR,
SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
};
static const struct snd_kcontrol_new sun8i_aif2_adc_mixer_controls[] = {
SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA0 Capture Switch",
SUN8I_AIF2_MXR_SRC,
SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L,
SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R, 1, 0),
SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA1 Capture Switch",
SUN8I_AIF2_MXR_SRC,
SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L,
SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R, 1, 0),
SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF2 DAC Rev Capture Switch",
SUN8I_AIF2_MXR_SRC,
SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR,
SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL, 1, 0),
SOC_DAPM_DOUBLE("AIF2 ADC Mixer ADC Capture Switch",
SUN8I_AIF2_MXR_SRC,
SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL,
SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR, 1, 0),
};
static const char *const sun8i_aif2_dac_mux_enum_values[] = {
"AIF2", "AIF3+2", "AIF2+3"
};
static SOC_ENUM_SINGLE_DECL(sun8i_aif2_dac_mux_enum,
SUN8I_AIF3_PATH_CTRL,
SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC,
sun8i_aif2_dac_mux_enum_values);
static const struct snd_kcontrol_new sun8i_aif2_dac_mux_control =
SOC_DAPM_ENUM("AIF2 DAC Source Playback Route",
sun8i_aif2_dac_mux_enum);
static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum,
SUN8I_AIF1_DACDAT_CTRL,
SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC,
SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC,
sun8i_aif_stereo_mux_enum_values);
static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control =
SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route",
sun8i_aif1_da0_stereo_mux_enum);
static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_dac_stereo_mux_enum,
SUN8I_AIF2_DACDAT_CTRL,
SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC,
SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC,
sun8i_aif_stereo_mux_enum_values);
static const struct snd_kcontrol_new sun8i_aif2_dac_stereo_mux_control =
SOC_DAPM_ENUM("AIF2 DAC Stereo Playback Route",
sun8i_aif2_dac_stereo_mux_enum);
static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
SUN8I_DAC_MXR_SRC,
SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
SUN8I_DAC_MXR_SRC,
SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
};
static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
/* System Clocks */
SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
SND_SOC_DAPM_SUPPLY("AIF1CLK",
SUN8I_SYSCLK_CTL,
SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("AIF2CLK",
SUN8I_SYSCLK_CTL,
SUN8I_SYSCLK_CTL_AIF2CLK_ENA, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("SYSCLK",
SUN8I_SYSCLK_CTL,
SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
/* Module Clocks */
SND_SOC_DAPM_SUPPLY("CLK AIF1",
SUN8I_MOD_CLK_ENA,
SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK AIF2",
SUN8I_MOD_CLK_ENA,
SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK AIF3",
SUN8I_MOD_CLK_ENA,
SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK ADC",
SUN8I_MOD_CLK_ENA,
SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CLK DAC",
SUN8I_MOD_CLK_ENA,
SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
/* Module Resets */
SND_SOC_DAPM_SUPPLY("RST AIF1",
SUN8I_MOD_RST_CTL,
SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RST AIF2",
SUN8I_MOD_RST_CTL,
SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RST AIF3",
SUN8I_MOD_RST_CTL,
SUN8I_MOD_RST_CTL_AIF3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RST ADC",
SUN8I_MOD_RST_CTL,
SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("RST DAC",
SUN8I_MOD_RST_CTL,
SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
/* Module Supplies */
SND_SOC_DAPM_SUPPLY("ADC",
SUN8I_ADC_DIG_CTRL,
SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC",
SUN8I_DAC_DIG_CTRL,
SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),
/* AIF "ADC" Outputs */
SND_SOC_DAPM_AIF_OUT_E("AIF1 AD0L", "AIF1 Capture", 0,
SUN8I_AIF1_ADCDAT_CTRL,
SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0,
sun8i_codec_aif_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "AIF1 Capture", 1,
SUN8I_AIF1_ADCDAT_CTRL,
SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),
SND_SOC_DAPM_AIF_OUT_E("AIF2 ADCL", "AIF2 Capture", 0,
SUN8I_AIF2_ADCDAT_CTRL,
SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA, 0,
sun8i_codec_aif_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_OUT("AIF2 ADCR", "AIF2 Capture", 1,
SUN8I_AIF2_ADCDAT_CTRL,
SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0),
SND_SOC_DAPM_AIF_OUT_E("AIF3 ADC", "AIF3 Capture", 0,
SND_SOC_NOPM, 0, 0,
sun8i_codec_aif_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* AIF "ADC" Mono/Stereo Muxes */
SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif1_ad0_stereo_mux_control),
SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif1_ad0_stereo_mux_control),
SND_SOC_DAPM_MUX("AIF2 ADCL Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif2_adc_stereo_mux_control),
SND_SOC_DAPM_MUX("AIF2 ADCR Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif2_adc_stereo_mux_control),
/* AIF "ADC" Output Muxes */
SND_SOC_DAPM_MUX("AIF3 ADC Source Capture Route", SND_SOC_NOPM, 0, 0,
&sun8i_aif3_adc_mux_control),
/* AIF "ADC" Mixers */
SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0,
sun8i_aif1_ad0_mixer_controls),
SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0,
sun8i_aif1_ad0_mixer_controls),
SOC_MIXER_ARRAY("AIF2 ADCL Mixer", SND_SOC_NOPM, 0, 0,
sun8i_aif2_adc_mixer_controls),
SOC_MIXER_ARRAY("AIF2 ADCR Mixer", SND_SOC_NOPM, 0, 0,
sun8i_aif2_adc_mixer_controls),
/* AIF "DAC" Input Muxes */
SND_SOC_DAPM_MUX("AIF2 DACL Source", SND_SOC_NOPM, 0, 0,
&sun8i_aif2_dac_mux_control),
SND_SOC_DAPM_MUX("AIF2 DACR Source", SND_SOC_NOPM, 0, 0,
&sun8i_aif2_dac_mux_control),
/* AIF "DAC" Mono/Stereo Muxes */
SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif1_da0_stereo_mux_control),
SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif1_da0_stereo_mux_control),
SND_SOC_DAPM_MUX("AIF2 DACL Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif2_dac_stereo_mux_control),
SND_SOC_DAPM_MUX("AIF2 DACR Stereo Mux", SND_SOC_NOPM, 0, 0,
&sun8i_aif2_dac_stereo_mux_control),
/* AIF "DAC" Inputs */
SND_SOC_DAPM_AIF_IN_E("AIF1 DA0L", "AIF1 Playback", 0,
SUN8I_AIF1_DACDAT_CTRL,
SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0,
sun8i_codec_aif_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "AIF1 Playback", 1,
SUN8I_AIF1_DACDAT_CTRL,
SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
SND_SOC_DAPM_AIF_IN_E("AIF2 DACL", "AIF2 Playback", 0,
SUN8I_AIF2_DACDAT_CTRL,
SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA, 0,
sun8i_codec_aif_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_AIF_IN("AIF2 DACR", "AIF2 Playback", 1,
SUN8I_AIF2_DACDAT_CTRL,
SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0),
SND_SOC_DAPM_AIF_IN_E("AIF3 DAC", "AIF3 Playback", 0,
SND_SOC_NOPM, 0, 0,
sun8i_codec_aif_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* ADC Inputs (connected to analog codec DAPM context) */
SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
/* DAC Outputs (connected to analog codec DAPM context) */
SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
/* DAC Mixers */
SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0,
sun8i_dac_mixer_controls),
SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0,
sun8i_dac_mixer_controls),
};
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
/* Clock Routes */
{ "AIF1CLK", NULL, "mod" },
{ "SYSCLK", NULL, "AIF1CLK" },
{ "CLK AIF1", NULL, "AIF1CLK" },
{ "CLK AIF1", NULL, "SYSCLK" },
{ "RST AIF1", NULL, "CLK AIF1" },
{ "AIF1 AD0L", NULL, "RST AIF1" },
{ "AIF1 AD0R", NULL, "RST AIF1" },
{ "AIF1 DA0L", NULL, "RST AIF1" },
{ "AIF1 DA0R", NULL, "RST AIF1" },
{ "CLK AIF2", NULL, "AIF2CLK" },
{ "CLK AIF2", NULL, "SYSCLK" },
{ "RST AIF2", NULL, "CLK AIF2" },
{ "AIF2 ADCL", NULL, "RST AIF2" },
{ "AIF2 ADCR", NULL, "RST AIF2" },
{ "AIF2 DACL", NULL, "RST AIF2" },
{ "AIF2 DACR", NULL, "RST AIF2" },
{ "CLK AIF3", NULL, "AIF1CLK" },
{ "CLK AIF3", NULL, "SYSCLK" },
{ "RST AIF3", NULL, "CLK AIF3" },
{ "AIF3 ADC", NULL, "RST AIF3" },
{ "AIF3 DAC", NULL, "RST AIF3" },
{ "CLK ADC", NULL, "SYSCLK" },
{ "RST ADC", NULL, "CLK ADC" },
{ "ADC", NULL, "RST ADC" },
{ "ADCL", NULL, "ADC" },
{ "ADCR", NULL, "ADC" },
{ "CLK DAC", NULL, "SYSCLK" },
{ "RST DAC", NULL, "CLK DAC" },
{ "DAC", NULL, "RST DAC" },
{ "DACL", NULL, "DAC" },
{ "DACR", NULL, "DAC" },
/* AIF "ADC" Output Routes */
{ "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" },
{ "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" },
{ "AIF2 ADCL", NULL, "AIF2 ADCL Stereo Mux" },
{ "AIF2 ADCR", NULL, "AIF2 ADCR Stereo Mux" },
{ "AIF3 ADC", NULL, "AIF3 ADC Source Capture Route" },
/* AIF "ADC" Mono/Stereo Mux Routes */
{ "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" },
{ "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" },
{ "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" },
{ "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" },
{ "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" },
{ "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" },
{ "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" },
{ "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" },
{ "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" },
{ "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" },
{ "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" },
{ "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" },
{ "AIF2 ADCL Stereo Mux", "Stereo", "AIF2 ADCL Mixer" },
{ "AIF2 ADCL Stereo Mux", "Reverse Stereo", "AIF2 ADCR Mixer" },
{ "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" },
{ "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" },
{ "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" },
{ "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" },
{ "AIF2 ADCR Stereo Mux", "Stereo", "AIF2 ADCR Mixer" },
{ "AIF2 ADCR Stereo Mux", "Reverse Stereo", "AIF2 ADCL Mixer" },
{ "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" },
{ "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" },
{ "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" },
{ "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" },
/* AIF "ADC" Output Mux Routes */
{ "AIF3 ADC Source Capture Route", "AIF2 ADCL", "AIF2 ADCL Mixer" },
{ "AIF3 ADC Source Capture Route", "AIF2 ADCR", "AIF2 ADCR Mixer" },
/* AIF "ADC" Mixer Routes */
{ "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" },
{ "AIF1 AD0L Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACL Source" },
{ "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" },
{ "AIF1 AD0L Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACR Source" },
{ "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" },
{ "AIF1 AD0R Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACR Source" },
{ "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" },
{ "AIF1 AD0R Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACL Source" },
{ "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0L Stereo Mux" },
{ "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACR Source" },
{ "AIF2 ADCL Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCL" },
{ "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0R Stereo Mux" },
{ "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACL Source" },
{ "AIF2 ADCR Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCR" },
/* AIF "DAC" Input Mux Routes */
{ "AIF2 DACL Source", "AIF2", "AIF2 DACL Stereo Mux" },
{ "AIF2 DACL Source", "AIF3+2", "AIF3 DAC" },
{ "AIF2 DACL Source", "AIF2+3", "AIF2 DACL Stereo Mux" },
{ "AIF2 DACR Source", "AIF2", "AIF2 DACR Stereo Mux" },
{ "AIF2 DACR Source", "AIF3+2", "AIF2 DACR Stereo Mux" },
{ "AIF2 DACR Source", "AIF2+3", "AIF3 DAC" },
/* AIF "DAC" Mono/Stereo Mux Routes */
{ "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" },
{ "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" },
{ "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" },
{ "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" },
{ "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" },
{ "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" },
{ "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" },
{ "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" },
{ "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" },
{ "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" },
{ "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" },
{ "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" },
{ "AIF2 DACL Stereo Mux", "Stereo", "AIF2 DACL" },
{ "AIF2 DACL Stereo Mux", "Reverse Stereo", "AIF2 DACR" },
{ "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACL" },
{ "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACR" },
{ "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACL" },
{ "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACR" },
{ "AIF2 DACR Stereo Mux", "Stereo", "AIF2 DACR" },
{ "AIF2 DACR Stereo Mux", "Reverse Stereo", "AIF2 DACL" },
{ "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACL" },
{ "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACR" },
{ "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACL" },
{ "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACR" },
/* DAC Output Routes */
{ "DACL", NULL, "DACL Mixer" },
{ "DACR", NULL, "DACR Mixer" },
/* DAC Mixer Routes */
{ "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" },
{ "DACL Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACL Source" },
{ "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" },
{ "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" },
{ "DACR Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACR Source" },
{ "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" },
};
static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = {
/* Legacy ADC Inputs (connected to analog codec DAPM context) */
SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0),
/* Legacy DAC Outputs (connected to analog codec DAPM context) */
SND_SOC_DAPM_DAC("AIF1 Slot 0 Left", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("AIF1 Slot 0 Right", NULL, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = {
/* Legacy ADC Routes */
{ "ADCL", NULL, "AIF1 Slot 0 Left ADC" },
{ "ADCR", NULL, "AIF1 Slot 0 Right ADC" },
/* Legacy DAC Routes */
{ "AIF1 Slot 0 Left", NULL, "DACL" },
{ "AIF1 Slot 0 Right", NULL, "DACR" },
};
static int sun8i_codec_component_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
int ret;
/* Add widgets for backward compatibility with old device trees. */
if (scodec->quirks->legacy_widgets) {
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets,
ARRAY_SIZE(sun8i_codec_legacy_widgets));
if (ret)
return ret;
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes,
ARRAY_SIZE(sun8i_codec_legacy_routes));
if (ret)
return ret;
}
/*
* AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod")
* and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also
* PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO
* directly to simplify the clock tree.
*/
regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL,
SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK |
SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK,
SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL |
SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL);
/* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */
regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL,
BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC),
SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK);
/* Program the default sample rate. */
sun8i_codec_update_sample_rate(scodec);
return 0;
}
static const struct snd_soc_component_driver sun8i_soc_component = {
.controls = sun8i_codec_controls,
.num_controls = ARRAY_SIZE(sun8i_codec_controls),
.dapm_widgets = sun8i_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
.dapm_routes = sun8i_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
.probe = sun8i_codec_component_probe,
.idle_bias_on = 1,
.endianness = 1,
};
static const struct regmap_config sun8i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN8I_DAC_MXR_SRC,
.cache_type = REGCACHE_FLAT,
};
static int sun8i_codec_probe(struct platform_device *pdev)
{
struct sun8i_codec *scodec;
void __iomem *base;
int ret;
scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
if (!scodec)
return -ENOMEM;
scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
if (IS_ERR(scodec->clk_module)) {
dev_err(&pdev->dev, "Failed to get the module clock\n");
return PTR_ERR(scodec->clk_module);
}
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
dev_err(&pdev->dev, "Failed to map the registers\n");
return PTR_ERR(base);
}
scodec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", base,
&sun8i_codec_regmap_config);
if (IS_ERR(scodec->regmap)) {
dev_err(&pdev->dev, "Failed to create our regmap\n");
return PTR_ERR(scodec->regmap);
}
scodec->quirks = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, scodec);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = sun8i_codec_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component,
sun8i_codec_dais,
ARRAY_SIZE(sun8i_codec_dais));
if (ret) {
dev_err(&pdev->dev, "Failed to register codec\n");
goto err_suspend;
}
return ret;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
sun8i_codec_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void sun8i_codec_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
sun8i_codec_runtime_suspend(&pdev->dev);
}
static const struct sun8i_codec_quirks sun8i_a33_quirks = {
.legacy_widgets = true,
.lrck_inversion = true,
};
static const struct sun8i_codec_quirks sun50i_a64_quirks = {
};
static const struct of_device_id sun8i_codec_of_match[] = {
{ .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks },
{ .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks },
{}
};
MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
static const struct dev_pm_ops sun8i_codec_pm_ops = {
SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
sun8i_codec_runtime_resume, NULL)
};
static struct platform_driver sun8i_codec_driver = {
.driver = {
.name = "sun8i-codec",
.of_match_table = sun8i_codec_of_match,
.pm = &sun8i_codec_pm_ops,
},
.probe = sun8i_codec_probe,
.remove_new = sun8i_codec_remove,
};
module_platform_driver(sun8i_codec_driver);
MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
MODULE_AUTHOR("Mylène Josserand <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sun8i-codec");
| linux-master | sound/soc/sunxi/sun8i-codec.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* This driver provides regmap to access to analog part of audio codec
* found on Allwinner A23, A31s, A33, H3 and A64 Socs
*
* Copyright 2016 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "sun8i-adda-pr-regmap.h"
/* Analog control register access bits */
#define ADDA_PR 0x0 /* PRCM base + 0x1c0 */
#define ADDA_PR_RESET BIT(28)
#define ADDA_PR_WRITE BIT(24)
#define ADDA_PR_ADDR_SHIFT 16
#define ADDA_PR_ADDR_MASK GENMASK(4, 0)
#define ADDA_PR_DATA_IN_SHIFT 8
#define ADDA_PR_DATA_IN_MASK GENMASK(7, 0)
#define ADDA_PR_DATA_OUT_SHIFT 0
#define ADDA_PR_DATA_OUT_MASK GENMASK(7, 0)
/* regmap access bits */
static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
{
void __iomem *base = (void __iomem *)context;
u32 tmp;
/* De-assert reset */
writel(readl(base) | ADDA_PR_RESET, base);
/* Clear write bit */
writel(readl(base) & ~ADDA_PR_WRITE, base);
/* Set register address */
tmp = readl(base);
tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
writel(tmp, base);
/* Read back value */
*val = readl(base) & ADDA_PR_DATA_OUT_MASK;
return 0;
}
static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
{
void __iomem *base = (void __iomem *)context;
u32 tmp;
/* De-assert reset */
writel(readl(base) | ADDA_PR_RESET, base);
/* Set register address */
tmp = readl(base);
tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
writel(tmp, base);
/* Set data to write */
tmp = readl(base);
tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
writel(tmp, base);
/* Set write bit to signal a write */
writel(readl(base) | ADDA_PR_WRITE, base);
/* Clear write bit */
writel(readl(base) & ~ADDA_PR_WRITE, base);
return 0;
}
static const struct regmap_config adda_pr_regmap_cfg = {
.name = "adda-pr",
.reg_bits = 5,
.reg_stride = 1,
.val_bits = 8,
.reg_read = adda_reg_read,
.reg_write = adda_reg_write,
.fast_io = true,
.max_register = 31,
};
struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,
void __iomem *base)
{
return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg);
}
EXPORT_SYMBOL_GPL(sun8i_adda_pr_regmap_init);
MODULE_DESCRIPTION("Allwinner analog audio codec regmap driver");
MODULE_AUTHOR("Vasily Khoruzhick <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sunxi-adda-pr");
| linux-master | sound/soc/sunxi/sun8i-adda-pr-regmap.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2014 Emilio López <[email protected]>
* Copyright 2014 Jon Smirl <[email protected]>
* Copyright 2015 Maxime Ripard <[email protected]>
* Copyright 2015 Adam Sampson <[email protected]>
* Copyright 2016 Chen-Yu Tsai <[email protected]>
*
* Based on the Allwinner SDK driver, released under the GPL.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/gpio/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include <sound/dmaengine_pcm.h>
/* Codec DAC digital controls and FIFO registers */
#define SUN4I_CODEC_DAC_DPC (0x00)
#define SUN4I_CODEC_DAC_DPC_EN_DA (31)
#define SUN4I_CODEC_DAC_DPC_DVOL (12)
#define SUN4I_CODEC_DAC_FIFOC (0x04)
#define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29)
#define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28)
#define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26)
#define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24)
#define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21)
#define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8)
#define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6)
#define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5)
#define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4)
#define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0)
#define SUN4I_CODEC_DAC_FIFOS (0x08)
#define SUN4I_CODEC_DAC_TXDATA (0x0c)
/* Codec DAC side analog signal controls */
#define SUN4I_CODEC_DAC_ACTL (0x10)
#define SUN4I_CODEC_DAC_ACTL_DACAENR (31)
#define SUN4I_CODEC_DAC_ACTL_DACAENL (30)
#define SUN4I_CODEC_DAC_ACTL_MIXEN (29)
#define SUN4I_CODEC_DAC_ACTL_LNG (26)
#define SUN4I_CODEC_DAC_ACTL_FMG (23)
#define SUN4I_CODEC_DAC_ACTL_MICG (20)
#define SUN4I_CODEC_DAC_ACTL_LLNS (19)
#define SUN4I_CODEC_DAC_ACTL_RLNS (18)
#define SUN4I_CODEC_DAC_ACTL_LFMS (17)
#define SUN4I_CODEC_DAC_ACTL_RFMS (16)
#define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15)
#define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14)
#define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13)
#define SUN4I_CODEC_DAC_ACTL_MIC1LS (12)
#define SUN4I_CODEC_DAC_ACTL_MIC1RS (11)
#define SUN4I_CODEC_DAC_ACTL_MIC2LS (10)
#define SUN4I_CODEC_DAC_ACTL_MIC2RS (9)
#define SUN4I_CODEC_DAC_ACTL_DACPAS (8)
#define SUN4I_CODEC_DAC_ACTL_MIXPAS (7)
#define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6)
#define SUN4I_CODEC_DAC_ACTL_PA_VOL (0)
#define SUN4I_CODEC_DAC_TUNE (0x14)
#define SUN4I_CODEC_DAC_DEBUG (0x18)
/* Codec ADC digital controls and FIFO registers */
#define SUN4I_CODEC_ADC_FIFOC (0x1c)
#define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29)
#define SUN4I_CODEC_ADC_FIFOC_EN_AD (28)
#define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24)
#define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8)
#define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7)
#define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6)
#define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4)
#define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0)
#define SUN4I_CODEC_ADC_FIFOS (0x20)
#define SUN4I_CODEC_ADC_RXDATA (0x24)
/* Codec ADC side analog signal controls */
#define SUN4I_CODEC_ADC_ACTL (0x28)
#define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31)
#define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30)
#define SUN4I_CODEC_ADC_ACTL_PREG1EN (29)
#define SUN4I_CODEC_ADC_ACTL_PREG2EN (28)
#define SUN4I_CODEC_ADC_ACTL_VMICEN (27)
#define SUN4I_CODEC_ADC_ACTL_PREG1 (25)
#define SUN4I_CODEC_ADC_ACTL_PREG2 (23)
#define SUN4I_CODEC_ADC_ACTL_VADCG (20)
#define SUN4I_CODEC_ADC_ACTL_ADCIS (17)
#define SUN4I_CODEC_ADC_ACTL_LNPREG (13)
#define SUN4I_CODEC_ADC_ACTL_PA_EN (4)
#define SUN4I_CODEC_ADC_ACTL_DDE (3)
#define SUN4I_CODEC_ADC_DEBUG (0x2c)
/* FIFO counters */
#define SUN4I_CODEC_DAC_TXCNT (0x30)
#define SUN4I_CODEC_ADC_RXCNT (0x34)
/* Calibration register (sun7i only) */
#define SUN7I_CODEC_AC_DAC_CAL (0x38)
/* Microphone controls (sun7i only) */
#define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c)
#define SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG1 (29)
#define SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2 (26)
/*
* sun6i specific registers
*
* sun6i shares the same digital control and FIFO registers as sun4i,
* but only the DAC digital controls are at the same offset. The others
* have been moved around to accommodate extra analog controls.
*/
/* Codec DAC digital controls and FIFO registers */
#define SUN6I_CODEC_ADC_FIFOC (0x10)
#define SUN6I_CODEC_ADC_FIFOC_EN_AD (28)
#define SUN6I_CODEC_ADC_FIFOS (0x14)
#define SUN6I_CODEC_ADC_RXDATA (0x18)
/* Output mixer and gain controls */
#define SUN6I_CODEC_OM_DACA_CTRL (0x20)
#define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31)
#define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18)
#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11)
#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10)
#define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9)
#define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8)
#define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7)
#define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6)
#define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0)
#define SUN6I_CODEC_OM_PA_CTRL (0x24)
#define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31)
#define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29)
#define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28)
#define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15)
#define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12)
#define SUN6I_CODEC_OM_PA_CTRL_LINEING (9)
#define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6)
#define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3)
#define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0)
/* Microphone, line out and phone out controls */
#define SUN6I_CODEC_MIC_CTRL (0x28)
#define SUN6I_CODEC_MIC_CTRL_HBIASEN (31)
#define SUN6I_CODEC_MIC_CTRL_MBIASEN (30)
#define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28)
#define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25)
#define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24)
#define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21)
#define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20)
#define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19)
#define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18)
#define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17)
#define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16)
#define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11)
#define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8)
/* ADC mixer controls */
#define SUN6I_CODEC_ADC_ACTL (0x2c)
#define SUN6I_CODEC_ADC_ACTL_ADCREN (31)
#define SUN6I_CODEC_ADC_ACTL_ADCLEN (30)
#define SUN6I_CODEC_ADC_ACTL_ADCRG (27)
#define SUN6I_CODEC_ADC_ACTL_ADCLG (24)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8)
#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1)
#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0)
/* Analog performance tuning controls */
#define SUN6I_CODEC_ADDA_TUNE (0x30)
/* Calibration controls */
#define SUN6I_CODEC_CALIBRATION (0x34)
/* FIFO counters */
#define SUN6I_CODEC_DAC_TXCNT (0x40)
#define SUN6I_CODEC_ADC_RXCNT (0x44)
/* headset jack detection and button support registers */
#define SUN6I_CODEC_HMIC_CTL (0x50)
#define SUN6I_CODEC_HMIC_DATA (0x54)
/* TODO sun6i DAP (Digital Audio Processing) bits */
/* FIFO counters moved on A23 */
#define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
#define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
/* TX FIFO moved on H3 */
#define SUN8I_H3_CODEC_DAC_TXDATA (0x20)
#define SUN8I_H3_CODEC_DAC_DBG (0x48)
#define SUN8I_H3_CODEC_ADC_DBG (0x4c)
/* TODO H3 DAP (Digital Audio Processing) bits */
struct sun4i_codec {
struct device *dev;
struct regmap *regmap;
struct clk *clk_apb;
struct clk *clk_module;
struct reset_control *rst;
struct gpio_desc *gpio_pa;
/* ADC_FIFOC register is at different offset on different SoCs */
struct regmap_field *reg_adc_fifoc;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct snd_dmaengine_dai_dma_data playback_dma_data;
};
static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
{
/* Flush TX FIFO */
regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
/* Enable DAC DRQ */
regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
}
static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
{
/* Disable DAC DRQ */
regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
}
static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
{
/* Enable ADC DRQ */
regmap_field_set_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
}
static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
{
/* Disable ADC DRQ */
regmap_field_clear_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
}
static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
sun4i_codec_start_playback(scodec);
else
sun4i_codec_start_capture(scodec);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
sun4i_codec_stop_playback(scodec);
else
sun4i_codec_stop_capture(scodec);
break;
default:
return -EINVAL;
}
return 0;
}
static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
/* Flush RX FIFO */
regmap_field_set_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH));
/* Set RX FIFO trigger level */
regmap_field_update_bits(scodec->reg_adc_fifoc,
0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
/*
* FIXME: Undocumented in the datasheet, but
* Allwinner's code mentions that it is
* related to microphone gain
*/
if (of_device_is_compatible(scodec->dev->of_node,
"allwinner,sun4i-a10-codec") ||
of_device_is_compatible(scodec->dev->of_node,
"allwinner,sun7i-a20-codec")) {
regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
0x3 << 25,
0x1 << 25);
}
if (of_device_is_compatible(scodec->dev->of_node,
"allwinner,sun7i-a20-codec"))
/* FIXME: Undocumented bits */
regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE,
0x3 << 8,
0x1 << 8);
return 0;
}
static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
u32 val;
/* Flush the TX FIFO */
regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
/* Set TX FIFO Empty Trigger Level */
regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
if (substream->runtime->rate > 32000)
/* Use 64 bits FIR filter */
val = 0;
else
/* Use 32 bits FIR filter */
val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
val);
/* Send zeros when we have an underrun */
regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
return 0;
};
static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return sun4i_codec_prepare_playback(substream, dai);
return sun4i_codec_prepare_capture(substream, dai);
}
static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
{
unsigned int rate = params_rate(params);
switch (rate) {
case 176400:
case 88200:
case 44100:
case 33075:
case 22050:
case 14700:
case 11025:
case 7350:
return 22579200;
case 192000:
case 96000:
case 48000:
case 32000:
case 24000:
case 16000:
case 12000:
case 8000:
return 24576000;
default:
return 0;
}
}
static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
{
unsigned int rate = params_rate(params);
switch (rate) {
case 192000:
case 176400:
return 6;
case 96000:
case 88200:
return 7;
case 48000:
case 44100:
return 0;
case 32000:
case 33075:
return 1;
case 24000:
case 22050:
return 2;
case 16000:
case 14700:
return 3;
case 12000:
case 11025:
return 4;
case 8000:
case 7350:
return 5;
default:
return -EINVAL;
}
}
static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
struct snd_pcm_hw_params *params,
unsigned int hwrate)
{
/* Set ADC sample rate */
regmap_field_update_bits(scodec->reg_adc_fifoc,
7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
/* Set the number of channels we want to use */
if (params_channels(params) == 1)
regmap_field_set_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
else
regmap_field_clear_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
/* Set the number of sample bits to either 16 or 24 bits */
if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
regmap_field_set_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
regmap_field_clear_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
} else {
regmap_field_clear_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
/* Fill most significant bits with valid data MSB */
regmap_field_set_bits(scodec->reg_adc_fifoc,
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
}
return 0;
}
static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
struct snd_pcm_hw_params *params,
unsigned int hwrate)
{
u32 val;
/* Set DAC sample rate */
regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
/* Set the number of channels we want to use */
if (params_channels(params) == 1)
val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
else
val = 0;
regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
val);
/* Set the number of sample bits to either 16 or 24 bits */
if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
/* Set TX FIFO mode to padding the LSBs with 0 */
regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
} else {
regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
/* Set TX FIFO mode to repeat the MSB */
regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
}
return 0;
}
static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
unsigned long clk_freq;
int ret, hwrate;
clk_freq = sun4i_codec_get_mod_freq(params);
if (!clk_freq)
return -EINVAL;
ret = clk_set_rate(scodec->clk_module, clk_freq);
if (ret)
return ret;
hwrate = sun4i_codec_get_hw_rate(params);
if (hwrate < 0)
return hwrate;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return sun4i_codec_hw_params_playback(scodec, params,
hwrate);
return sun4i_codec_hw_params_capture(scodec, params,
hwrate);
}
static unsigned int sun4i_codec_src_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000,
44100, 48000, 96000, 192000
};
static struct snd_pcm_hw_constraint_list sun4i_codec_constraints = {
.count = ARRAY_SIZE(sun4i_codec_src_rates),
.list = sun4i_codec_src_rates,
};
static int sun4i_codec_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &sun4i_codec_constraints);
/*
* Stop issuing DRQ when we have room for less than 16 samples
* in our TX FIFO
*/
regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
return clk_prepare_enable(scodec->clk_module);
}
static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
clk_disable_unprepare(scodec->clk_module);
}
static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
.startup = sun4i_codec_startup,
.shutdown = sun4i_codec_shutdown,
.trigger = sun4i_codec_trigger,
.hw_params = sun4i_codec_hw_params,
.prepare = sun4i_codec_prepare,
};
static struct snd_soc_dai_driver sun4i_codec_dai = {
.name = "Codec",
.ops = &sun4i_codec_dai_ops,
.playback = {
.stream_name = "Codec Playback",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.sig_bits = 24,
},
.capture = {
.stream_name = "Codec Capture",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.sig_bits = 24,
},
};
/*** sun4i Codec ***/
static const struct snd_kcontrol_new sun4i_codec_pa_mute =
SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
static DECLARE_TLV_DB_SCALE(sun4i_codec_linein_loopback_gain_scale, -150, 150,
0);
static DECLARE_TLV_DB_SCALE(sun4i_codec_linein_preamp_gain_scale, -1200, 300,
0);
static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150,
0);
static DECLARE_TLV_DB_SCALE(sun4i_codec_micin_loopback_gain_scale, -450, 150,
0);
static DECLARE_TLV_DB_RANGE(sun4i_codec_micin_preamp_gain_scale,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 7, TLV_DB_SCALE_ITEM(3500, 300, 0));
static DECLARE_TLV_DB_RANGE(sun7i_codec_micin_preamp_gain_scale,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0));
static const struct snd_kcontrol_new sun4i_codec_controls[] = {
SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
sun4i_codec_pa_volume_scale),
SOC_SINGLE_TLV("Line Playback Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_LNG, 1, 0,
sun4i_codec_linein_loopback_gain_scale),
SOC_SINGLE_TLV("Line Boost Volume", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_LNPREG, 7, 0,
sun4i_codec_linein_preamp_gain_scale),
SOC_SINGLE_TLV("FM Playback Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_FMG, 3, 0,
sun4i_codec_fmin_loopback_gain_scale),
SOC_SINGLE_TLV("Mic Playback Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MICG, 7, 0,
sun4i_codec_micin_loopback_gain_scale),
SOC_SINGLE_TLV("Mic1 Boost Volume", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PREG1, 3, 0,
sun4i_codec_micin_preamp_gain_scale),
SOC_SINGLE_TLV("Mic2 Boost Volume", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PREG2, 3, 0,
sun4i_codec_micin_preamp_gain_scale),
};
static const struct snd_kcontrol_new sun7i_codec_controls[] = {
SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
sun4i_codec_pa_volume_scale),
SOC_SINGLE_TLV("Line Playback Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_LNG, 1, 0,
sun4i_codec_linein_loopback_gain_scale),
SOC_SINGLE_TLV("Line Boost Volume", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_LNPREG, 7, 0,
sun4i_codec_linein_preamp_gain_scale),
SOC_SINGLE_TLV("FM Playback Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_FMG, 3, 0,
sun4i_codec_fmin_loopback_gain_scale),
SOC_SINGLE_TLV("Mic Playback Volume", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MICG, 7, 0,
sun4i_codec_micin_loopback_gain_scale),
SOC_SINGLE_TLV("Mic1 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG1, 7, 0,
sun7i_codec_micin_preamp_gain_scale),
SOC_SINGLE_TLV("Mic2 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2, 7, 0,
sun7i_codec_micin_preamp_gain_scale),
};
static const struct snd_kcontrol_new sun4i_codec_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Mixer Left DAC Playback Switch",
SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_LDACLMIXS,
1, 0),
SOC_DAPM_SINGLE("Right Mixer Right DAC Playback Switch",
SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_RDACRMIXS,
1, 0),
SOC_DAPM_SINGLE("Right Mixer Left DAC Playback Switch",
SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
SOC_DAPM_DOUBLE("Line Playback Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_LLNS,
SUN4I_CODEC_DAC_ACTL_RLNS, 1, 0),
SOC_DAPM_DOUBLE("FM Playback Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_LFMS,
SUN4I_CODEC_DAC_ACTL_RFMS, 1, 0),
SOC_DAPM_DOUBLE("Mic1 Playback Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MIC1LS,
SUN4I_CODEC_DAC_ACTL_MIC1RS, 1, 0),
SOC_DAPM_DOUBLE("Mic2 Playback Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MIC2LS,
SUN4I_CODEC_DAC_ACTL_MIC2RS, 1, 0),
};
static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
};
static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
/* Digital parts of the ADCs */
SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC,
SUN4I_CODEC_ADC_FIFOC_EN_AD, 0,
NULL, 0),
/* Digital parts of the DACs */
SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
SUN4I_CODEC_DAC_DPC_EN_DA, 0,
NULL, 0),
/* Analog parts of the ADCs */
SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0),
SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0),
/* Analog parts of the DACs */
SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
/* Mixers */
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
sun4i_codec_mixer_controls,
ARRAY_SIZE(sun4i_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
sun4i_codec_mixer_controls,
ARRAY_SIZE(sun4i_codec_mixer_controls)),
/* Global Mixer Enable */
SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
/* VMIC */
SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0),
/* Mic Pre-Amplifiers */
SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PREG2EN, 0, NULL, 0),
/* Power Amplifier */
SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
sun4i_codec_pa_mixer_controls,
ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0,
&sun4i_codec_pa_mute),
SND_SOC_DAPM_INPUT("Line Right"),
SND_SOC_DAPM_INPUT("Line Left"),
SND_SOC_DAPM_INPUT("FM Right"),
SND_SOC_DAPM_INPUT("FM Left"),
SND_SOC_DAPM_INPUT("Mic1"),
SND_SOC_DAPM_INPUT("Mic2"),
SND_SOC_DAPM_OUTPUT("HP Right"),
SND_SOC_DAPM_OUTPUT("HP Left"),
};
static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
/* Left ADC / DAC Routes */
{ "Left ADC", NULL, "ADC" },
{ "Left DAC", NULL, "DAC" },
/* Right ADC / DAC Routes */
{ "Right ADC", NULL, "ADC" },
{ "Right DAC", NULL, "DAC" },
/* Right Mixer Routes */
{ "Right Mixer", NULL, "Mixer Enable" },
{ "Right Mixer", "Right Mixer Left DAC Playback Switch", "Left DAC" },
{ "Right Mixer", "Right Mixer Right DAC Playback Switch", "Right DAC" },
{ "Right Mixer", "Line Playback Switch", "Line Right" },
{ "Right Mixer", "FM Playback Switch", "FM Right" },
{ "Right Mixer", "Mic1 Playback Switch", "MIC1 Pre-Amplifier" },
{ "Right Mixer", "Mic2 Playback Switch", "MIC2 Pre-Amplifier" },
/* Left Mixer Routes */
{ "Left Mixer", NULL, "Mixer Enable" },
{ "Left Mixer", "Left Mixer Left DAC Playback Switch", "Left DAC" },
{ "Left Mixer", "Line Playback Switch", "Line Left" },
{ "Left Mixer", "FM Playback Switch", "FM Left" },
{ "Left Mixer", "Mic1 Playback Switch", "MIC1 Pre-Amplifier" },
{ "Left Mixer", "Mic2 Playback Switch", "MIC2 Pre-Amplifier" },
/* Power Amplifier Routes */
{ "Power Amplifier", "Mixer Playback Switch", "Left Mixer" },
{ "Power Amplifier", "Mixer Playback Switch", "Right Mixer" },
{ "Power Amplifier", "DAC Playback Switch", "Left DAC" },
{ "Power Amplifier", "DAC Playback Switch", "Right DAC" },
/* Headphone Output Routes */
{ "Power Amplifier Mute", "Switch", "Power Amplifier" },
{ "HP Right", NULL, "Power Amplifier Mute" },
{ "HP Left", NULL, "Power Amplifier Mute" },
/* Mic1 Routes */
{ "Left ADC", NULL, "MIC1 Pre-Amplifier" },
{ "Right ADC", NULL, "MIC1 Pre-Amplifier" },
{ "MIC1 Pre-Amplifier", NULL, "Mic1"},
{ "Mic1", NULL, "VMIC" },
/* Mic2 Routes */
{ "Left ADC", NULL, "MIC2 Pre-Amplifier" },
{ "Right ADC", NULL, "MIC2 Pre-Amplifier" },
{ "MIC2 Pre-Amplifier", NULL, "Mic2"},
{ "Mic2", NULL, "VMIC" },
};
static const struct snd_soc_component_driver sun4i_codec_codec = {
.controls = sun4i_codec_controls,
.num_controls = ARRAY_SIZE(sun4i_codec_controls),
.dapm_widgets = sun4i_codec_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
.dapm_routes = sun4i_codec_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver sun7i_codec_codec = {
.controls = sun7i_codec_controls,
.num_controls = ARRAY_SIZE(sun7i_codec_controls),
.dapm_widgets = sun4i_codec_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
.dapm_routes = sun4i_codec_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/*** sun6i Codec ***/
/* mixer controls */
static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
SOC_DAPM_DOUBLE("DAC Playback Switch",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL,
SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0),
SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR,
SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0),
SOC_DAPM_DOUBLE("Line In Playback Switch",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL,
SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0),
SOC_DAPM_DOUBLE("Mic1 Playback Switch",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1,
SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0),
SOC_DAPM_DOUBLE("Mic2 Playback Switch",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2,
SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0),
};
/* ADC mixer controls */
static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = {
SOC_DAPM_DOUBLE("Mixer Capture Switch",
SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL,
SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0),
SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR,
SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0),
SOC_DAPM_DOUBLE("Line In Capture Switch",
SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL,
SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0),
SOC_DAPM_DOUBLE("Mic1 Capture Switch",
SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1,
SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0),
SOC_DAPM_DOUBLE("Mic2 Capture Switch",
SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2,
SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0),
};
/* headphone controls */
static const char * const sun6i_codec_hp_src_enum_text[] = {
"DAC", "Mixer",
};
static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
sun6i_codec_hp_src_enum_text);
static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
SOC_DAPM_ENUM("Headphone Source Playback Route",
sun6i_codec_hp_src_enum),
};
/* microphone controls */
static const char * const sun6i_codec_mic2_src_enum_text[] = {
"Mic2", "Mic3",
};
static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum,
SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MIC2SLT,
sun6i_codec_mic2_src_enum_text);
static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = {
SOC_DAPM_ENUM("Mic2 Amplifier Source Route",
sun6i_codec_mic2_src_enum),
};
/* line out controls */
static const char * const sun6i_codec_lineout_src_enum_text[] = {
"Stereo", "Mono Differential",
};
static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum,
SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC,
SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC,
sun6i_codec_lineout_src_enum_text);
static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = {
SOC_DAPM_ENUM("Line Out Source Playback Route",
sun6i_codec_lineout_src_enum),
};
/* volume / mute controls */
static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0);
static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1);
static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale,
-450, 150, 0);
static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale,
0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
);
static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
);
static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
sun6i_codec_dvol_scale),
SOC_SINGLE_TLV("Headphone Playback Volume",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0,
sun6i_codec_hp_vol_scale),
SOC_SINGLE_TLV("Line Out Playback Volume",
SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0,
sun6i_codec_lineout_vol_scale),
SOC_DOUBLE("Headphone Playback Switch",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE,
SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0),
SOC_DOUBLE("Line Out Playback Switch",
SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_LINEOUTLEN,
SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0),
/* Mixer pre-gains */
SOC_SINGLE_TLV("Line In Playback Volume",
SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING,
0x7, 0, sun6i_codec_out_mixer_pregain_scale),
SOC_SINGLE_TLV("Mic1 Playback Volume",
SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G,
0x7, 0, sun6i_codec_out_mixer_pregain_scale),
SOC_SINGLE_TLV("Mic2 Playback Volume",
SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G,
0x7, 0, sun6i_codec_out_mixer_pregain_scale),
/* Microphone Amp boost gains */
SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0,
sun6i_codec_mic_gain_scale),
SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0,
sun6i_codec_mic_gain_scale),
SOC_DOUBLE_TLV("ADC Capture Volume",
SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG,
SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0,
sun6i_codec_out_mixer_pregain_scale),
};
static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
/* Microphone inputs */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("MIC3"),
/* Microphone Bias */
SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0),
/* Mic input path */
SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route",
SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src),
SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL,
SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0),
/* Line In */
SND_SOC_DAPM_INPUT("LINEIN"),
/* Digital parts of the ADCs */
SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
SUN6I_CODEC_ADC_FIFOC_EN_AD, 0,
NULL, 0),
/* Analog parts of the ADCs */
SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_ADCLEN, 0),
SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
SUN6I_CODEC_ADC_ACTL_ADCREN, 0),
/* ADC Mixers */
SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
sun6i_codec_adc_mixer_controls),
SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
sun6i_codec_adc_mixer_controls),
/* Digital parts of the DACs */
SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
SUN4I_CODEC_DAC_DPC_EN_DA, 0,
NULL, 0),
/* Analog parts of the DACs */
SND_SOC_DAPM_DAC("Left DAC", "Codec Playback",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0),
SND_SOC_DAPM_DAC("Right DAC", "Codec Playback",
SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0),
/* Mixers */
SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0,
sun6i_codec_mixer_controls),
SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL,
SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0,
sun6i_codec_mixer_controls),
/* Headphone output path */
SND_SOC_DAPM_MUX("Headphone Source Playback Route",
SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL,
SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL,
SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL,
SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0),
SND_SOC_DAPM_OUTPUT("HP"),
/* Line Out path */
SND_SOC_DAPM_MUX("Line Out Source Playback Route",
SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
};
static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
/* DAC Routes */
{ "Left DAC", NULL, "DAC Enable" },
{ "Right DAC", NULL, "DAC Enable" },
/* Microphone Routes */
{ "Mic1 Amplifier", NULL, "MIC1"},
{ "Mic2 Amplifier Source Route", "Mic2", "MIC2" },
{ "Mic2 Amplifier Source Route", "Mic3", "MIC3" },
{ "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"},
/* Left Mixer Routes */
{ "Left Mixer", "DAC Playback Switch", "Left DAC" },
{ "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
{ "Left Mixer", "Line In Playback Switch", "LINEIN" },
{ "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
{ "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
/* Right Mixer Routes */
{ "Right Mixer", "DAC Playback Switch", "Right DAC" },
{ "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
{ "Right Mixer", "Line In Playback Switch", "LINEIN" },
{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
/* Left ADC Mixer Routes */
{ "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
{ "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
{ "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
{ "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
{ "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
/* Right ADC Mixer Routes */
{ "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
{ "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
{ "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
{ "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
{ "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
/* Headphone Routes */
{ "Headphone Source Playback Route", "DAC", "Left DAC" },
{ "Headphone Source Playback Route", "DAC", "Right DAC" },
{ "Headphone Source Playback Route", "Mixer", "Left Mixer" },
{ "Headphone Source Playback Route", "Mixer", "Right Mixer" },
{ "Headphone Amp", NULL, "Headphone Source Playback Route" },
{ "HP", NULL, "Headphone Amp" },
{ "HPCOM", NULL, "HPCOM Protection" },
/* Line Out Routes */
{ "Line Out Source Playback Route", "Stereo", "Left Mixer" },
{ "Line Out Source Playback Route", "Stereo", "Right Mixer" },
{ "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
{ "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
{ "LINEOUT", NULL, "Line Out Source Playback Route" },
/* ADC Routes */
{ "Left ADC", NULL, "ADC Enable" },
{ "Right ADC", NULL, "ADC Enable" },
{ "Left ADC", NULL, "Left ADC Mixer" },
{ "Right ADC", NULL, "Right ADC Mixer" },
};
static const struct snd_soc_component_driver sun6i_codec_codec = {
.controls = sun6i_codec_codec_widgets,
.num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets),
.dapm_widgets = sun6i_codec_codec_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets),
.dapm_routes = sun6i_codec_codec_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
/* sun8i A23 codec */
static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = {
SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
sun6i_codec_dvol_scale),
};
static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = {
/* Digital parts of the ADCs */
SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
/* Digital parts of the DACs */
SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
};
static const struct snd_soc_component_driver sun8i_a23_codec_codec = {
.controls = sun8i_a23_codec_codec_controls,
.num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls),
.dapm_widgets = sun8i_a23_codec_codec_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct snd_soc_component_driver sun4i_codec_component = {
.name = "sun4i-codec",
.legacy_dai_naming = 1,
#ifdef CONFIG_DEBUG_FS
.debugfs_prefix = "cpu",
#endif
};
#define SUN4I_CODEC_RATES SNDRV_PCM_RATE_CONTINUOUS
#define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
{
struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
&scodec->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops dummy_dai_ops = {
.probe = sun4i_codec_dai_probe,
};
static struct snd_soc_dai_driver dummy_cpu_dai = {
.name = "sun4i-codec-cpu-dai",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SUN4I_CODEC_RATES,
.formats = SUN4I_CODEC_FORMATS,
.sig_bits = 24,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SUN4I_CODEC_RATES,
.formats = SUN4I_CODEC_FORMATS,
.sig_bits = 24,
},
.ops = &dummy_dai_ops,
};
static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
int *num_links)
{
struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
GFP_KERNEL);
struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev,
3 * sizeof(*dlc), GFP_KERNEL);
if (!link || !dlc)
return NULL;
link->cpus = &dlc[0];
link->codecs = &dlc[1];
link->platforms = &dlc[2];
link->num_cpus = 1;
link->num_codecs = 1;
link->num_platforms = 1;
link->name = "cdc";
link->stream_name = "CDC PCM";
link->codecs->dai_name = "Codec";
link->cpus->dai_name = dev_name(dev);
link->codecs->name = dev_name(dev);
link->platforms->name = dev_name(dev);
link->dai_fmt = SND_SOC_DAIFMT_I2S;
*num_links = 1;
return link;
};
static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
gpiod_set_value_cansleep(scodec->gpio_pa,
!!SND_SOC_DAPM_EVENT_ON(event));
if (SND_SOC_DAPM_EVENT_ON(event)) {
/*
* Need a delay to wait for DAC to push the data. 700ms seems
* to be the best compromise not to feel this delay while
* playing a sound.
*/
msleep(700);
}
return 0;
}
static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = {
SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
};
static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = {
{ "Speaker", NULL, "HP Right" },
{ "Speaker", NULL, "HP Left" },
};
static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
{
struct snd_soc_card *card;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return ERR_PTR(-ENOMEM);
card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
if (!card->dai_link)
return ERR_PTR(-ENOMEM);
card->dev = dev;
card->owner = THIS_MODULE;
card->name = "sun4i-codec";
card->dapm_widgets = sun4i_codec_card_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets);
card->dapm_routes = sun4i_codec_card_dapm_routes;
card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes);
return card;
};
static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_LINE("Line In", NULL),
SND_SOC_DAPM_LINE("Line Out", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Mic", NULL),
SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
};
static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
{
struct snd_soc_card *card;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return ERR_PTR(-ENOMEM);
card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
if (!card->dai_link)
return ERR_PTR(-ENOMEM);
card->dev = dev;
card->owner = THIS_MODULE;
card->name = "A31 Audio Codec";
card->dapm_widgets = sun6i_codec_card_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
card->fully_routed = true;
ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
if (ret)
dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
return card;
};
/* Connect digital side enables to analog side widgets */
static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
/* ADC Routes */
{ "Left ADC", NULL, "ADC Enable" },
{ "Right ADC", NULL, "ADC Enable" },
{ "Codec Capture", NULL, "Left ADC" },
{ "Codec Capture", NULL, "Right ADC" },
/* DAC Routes */
{ "Left DAC", NULL, "DAC Enable" },
{ "Right DAC", NULL, "DAC Enable" },
{ "Left DAC", NULL, "Codec Playback" },
{ "Right DAC", NULL, "Codec Playback" },
};
static struct snd_soc_aux_dev aux_dev = {
.dlc = COMP_EMPTY(),
};
static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
{
struct snd_soc_card *card;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return ERR_PTR(-ENOMEM);
aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
"allwinner,codec-analog-controls",
0);
if (!aux_dev.dlc.of_node) {
dev_err(dev, "Can't find analog controls for codec.\n");
return ERR_PTR(-EINVAL);
}
card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
if (!card->dai_link)
return ERR_PTR(-ENOMEM);
card->dev = dev;
card->owner = THIS_MODULE;
card->name = "A23 Audio Codec";
card->dapm_widgets = sun6i_codec_card_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
card->dapm_routes = sun8i_codec_card_routes;
card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
card->aux_dev = &aux_dev;
card->num_aux_devs = 1;
card->fully_routed = true;
ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
if (ret)
dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
return card;
};
static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev)
{
struct snd_soc_card *card;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return ERR_PTR(-ENOMEM);
aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
"allwinner,codec-analog-controls",
0);
if (!aux_dev.dlc.of_node) {
dev_err(dev, "Can't find analog controls for codec.\n");
return ERR_PTR(-EINVAL);
}
card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
if (!card->dai_link)
return ERR_PTR(-ENOMEM);
card->dev = dev;
card->owner = THIS_MODULE;
card->name = "H3 Audio Codec";
card->dapm_widgets = sun6i_codec_card_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
card->dapm_routes = sun8i_codec_card_routes;
card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
card->aux_dev = &aux_dev;
card->num_aux_devs = 1;
card->fully_routed = true;
ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
if (ret)
dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
return card;
};
static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev)
{
struct snd_soc_card *card;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return ERR_PTR(-ENOMEM);
aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
"allwinner,codec-analog-controls",
0);
if (!aux_dev.dlc.of_node) {
dev_err(dev, "Can't find analog controls for codec.\n");
return ERR_PTR(-EINVAL);
}
card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
if (!card->dai_link)
return ERR_PTR(-ENOMEM);
card->dev = dev;
card->owner = THIS_MODULE;
card->name = "V3s Audio Codec";
card->dapm_widgets = sun6i_codec_card_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
card->dapm_routes = sun8i_codec_card_routes;
card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
card->aux_dev = &aux_dev;
card->num_aux_devs = 1;
card->fully_routed = true;
ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
if (ret)
dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
return card;
};
static const struct regmap_config sun4i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN4I_CODEC_ADC_RXCNT,
};
static const struct regmap_config sun6i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN6I_CODEC_HMIC_DATA,
};
static const struct regmap_config sun7i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
};
static const struct regmap_config sun8i_a23_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN8I_A23_CODEC_ADC_RXCNT,
};
static const struct regmap_config sun8i_h3_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN8I_H3_CODEC_ADC_DBG,
};
static const struct regmap_config sun8i_v3s_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN8I_H3_CODEC_ADC_DBG,
};
struct sun4i_codec_quirks {
const struct regmap_config *regmap_config;
const struct snd_soc_component_driver *codec;
struct snd_soc_card * (*create_card)(struct device *dev);
struct reg_field reg_adc_fifoc; /* used for regmap_field */
unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
bool has_reset;
};
static const struct sun4i_codec_quirks sun4i_codec_quirks = {
.regmap_config = &sun4i_codec_regmap_config,
.codec = &sun4i_codec_codec,
.create_card = sun4i_codec_create_card,
.reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
};
static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
.regmap_config = &sun6i_codec_regmap_config,
.codec = &sun6i_codec_codec,
.create_card = sun6i_codec_create_card,
.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
};
static const struct sun4i_codec_quirks sun7i_codec_quirks = {
.regmap_config = &sun7i_codec_regmap_config,
.codec = &sun7i_codec_codec,
.create_card = sun4i_codec_create_card,
.reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
};
static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
.regmap_config = &sun8i_a23_codec_regmap_config,
.codec = &sun8i_a23_codec_codec,
.create_card = sun8i_a23_codec_create_card,
.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
.reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
};
static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
.regmap_config = &sun8i_h3_codec_regmap_config,
/*
* TODO Share the codec structure with A23 for now.
* This should be split out when adding digital audio
* processing support for the H3.
*/
.codec = &sun8i_a23_codec_codec,
.create_card = sun8i_h3_codec_create_card,
.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
.reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
};
static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = {
.regmap_config = &sun8i_v3s_codec_regmap_config,
/*
* TODO The codec structure should be split out, like
* H3, when adding digital audio processing support.
*/
.codec = &sun8i_a23_codec_codec,
.create_card = sun8i_v3s_codec_create_card,
.reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
.reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
.reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
.has_reset = true,
};
static const struct of_device_id sun4i_codec_of_match[] = {
{
.compatible = "allwinner,sun4i-a10-codec",
.data = &sun4i_codec_quirks,
},
{
.compatible = "allwinner,sun6i-a31-codec",
.data = &sun6i_a31_codec_quirks,
},
{
.compatible = "allwinner,sun7i-a20-codec",
.data = &sun7i_codec_quirks,
},
{
.compatible = "allwinner,sun8i-a23-codec",
.data = &sun8i_a23_codec_quirks,
},
{
.compatible = "allwinner,sun8i-h3-codec",
.data = &sun8i_h3_codec_quirks,
},
{
.compatible = "allwinner,sun8i-v3s-codec",
.data = &sun8i_v3s_codec_quirks,
},
{}
};
MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
static int sun4i_codec_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sun4i_codec *scodec;
const struct sun4i_codec_quirks *quirks;
struct resource *res;
void __iomem *base;
int ret;
scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
if (!scodec)
return -ENOMEM;
scodec->dev = &pdev->dev;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
quirks = of_device_get_match_data(&pdev->dev);
if (quirks == NULL) {
dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
return -ENODEV;
}
scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
quirks->regmap_config);
if (IS_ERR(scodec->regmap)) {
dev_err(&pdev->dev, "Failed to create our regmap\n");
return PTR_ERR(scodec->regmap);
}
/* Get the clocks from the DT */
scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
if (IS_ERR(scodec->clk_apb)) {
dev_err(&pdev->dev, "Failed to get the APB clock\n");
return PTR_ERR(scodec->clk_apb);
}
scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
if (IS_ERR(scodec->clk_module)) {
dev_err(&pdev->dev, "Failed to get the module clock\n");
return PTR_ERR(scodec->clk_module);
}
if (quirks->has_reset) {
scodec->rst = devm_reset_control_get_exclusive(&pdev->dev,
NULL);
if (IS_ERR(scodec->rst)) {
dev_err(&pdev->dev, "Failed to get reset control\n");
return PTR_ERR(scodec->rst);
}
}
scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
GPIOD_OUT_LOW);
if (IS_ERR(scodec->gpio_pa)) {
ret = PTR_ERR(scodec->gpio_pa);
dev_err_probe(&pdev->dev, ret, "Failed to get pa gpio\n");
return ret;
}
/* reg_field setup */
scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev,
scodec->regmap,
quirks->reg_adc_fifoc);
if (IS_ERR(scodec->reg_adc_fifoc)) {
ret = PTR_ERR(scodec->reg_adc_fifoc);
dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
ret);
return ret;
}
/* Enable the bus clock */
if (clk_prepare_enable(scodec->clk_apb)) {
dev_err(&pdev->dev, "Failed to enable the APB clock\n");
return -EINVAL;
}
/* Deassert the reset control */
if (scodec->rst) {
ret = reset_control_deassert(scodec->rst);
if (ret) {
dev_err(&pdev->dev,
"Failed to deassert the reset control\n");
goto err_clk_disable;
}
}
/* DMA configuration for TX FIFO */
scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
scodec->playback_dma_data.maxburst = 8;
scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
/* DMA configuration for RX FIFO */
scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata;
scodec->capture_dma_data.maxburst = 8;
scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec,
&sun4i_codec_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Failed to register our codec\n");
goto err_assert_reset;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&sun4i_codec_component,
&dummy_cpu_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Failed to register our DAI\n");
goto err_assert_reset;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
goto err_assert_reset;
}
card = quirks->create_card(&pdev->dev);
if (IS_ERR(card)) {
ret = PTR_ERR(card);
dev_err(&pdev->dev, "Failed to create our card\n");
goto err_assert_reset;
}
snd_soc_card_set_drvdata(card, scodec);
ret = snd_soc_register_card(card);
if (ret) {
dev_err_probe(&pdev->dev, ret, "Failed to register our card\n");
goto err_assert_reset;
}
return 0;
err_assert_reset:
if (scodec->rst)
reset_control_assert(scodec->rst);
err_clk_disable:
clk_disable_unprepare(scodec->clk_apb);
return ret;
}
static void sun4i_codec_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
snd_soc_unregister_card(card);
if (scodec->rst)
reset_control_assert(scodec->rst);
clk_disable_unprepare(scodec->clk_apb);
}
static struct platform_driver sun4i_codec_driver = {
.driver = {
.name = "sun4i-codec",
.of_match_table = sun4i_codec_of_match,
},
.probe = sun4i_codec_probe,
.remove_new = sun4i_codec_remove,
};
module_platform_driver(sun4i_codec_driver);
MODULE_DESCRIPTION("Allwinner A10 codec driver");
MODULE_AUTHOR("Emilio López <[email protected]>");
MODULE_AUTHOR("Jon Smirl <[email protected]>");
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
MODULE_AUTHOR("Chen-Yu Tsai <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/sunxi/sun4i-codec.c |
// SPDX-License-Identifier: GPL-2.0-or-later
//
// This driver supports the DMIC in Allwinner's H6 SoCs.
//
// Copyright 2021 Ban Tao <[email protected]>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define SUN50I_DMIC_EN_CTL (0x00)
#define SUN50I_DMIC_EN_CTL_GLOBE BIT(8)
#define SUN50I_DMIC_EN_CTL_CHAN(v) ((v) << 0)
#define SUN50I_DMIC_EN_CTL_CHAN_MASK GENMASK(7, 0)
#define SUN50I_DMIC_SR (0x04)
#define SUN50I_DMIC_SR_SAMPLE_RATE(v) ((v) << 0)
#define SUN50I_DMIC_SR_SAMPLE_RATE_MASK GENMASK(2, 0)
#define SUN50I_DMIC_CTL (0x08)
#define SUN50I_DMIC_CTL_OVERSAMPLE_RATE BIT(0)
#define SUN50I_DMIC_DATA (0x10)
#define SUN50I_DMIC_INTC (0x14)
#define SUN50I_DMIC_FIFO_DRQ_EN BIT(2)
#define SUN50I_DMIC_INT_STA (0x18)
#define SUN50I_DMIC_INT_STA_OVERRUN_IRQ_PENDING BIT(1)
#define SUN50I_DMIC_INT_STA_DATA_IRQ_PENDING BIT(0)
#define SUN50I_DMIC_RXFIFO_CTL (0x1c)
#define SUN50I_DMIC_RXFIFO_CTL_FLUSH BIT(31)
#define SUN50I_DMIC_RXFIFO_CTL_MODE_MASK BIT(9)
#define SUN50I_DMIC_RXFIFO_CTL_MODE_LSB (0 << 9)
#define SUN50I_DMIC_RXFIFO_CTL_MODE_MSB (1 << 9)
#define SUN50I_DMIC_RXFIFO_CTL_SAMPLE_MASK BIT(8)
#define SUN50I_DMIC_RXFIFO_CTL_SAMPLE_16 (0 << 8)
#define SUN50I_DMIC_RXFIFO_CTL_SAMPLE_24 (1 << 8)
#define SUN50I_DMIC_CH_NUM (0x24)
#define SUN50I_DMIC_CH_NUM_N(v) ((v) << 0)
#define SUN50I_DMIC_CH_NUM_N_MASK GENMASK(2, 0)
#define SUN50I_DMIC_CNT (0x2c)
#define SUN50I_DMIC_CNT_N (1 << 0)
#define SUN50I_DMIC_HPF_CTRL (0x38)
#define SUN50I_DMIC_VERSION (0x50)
struct sun50i_dmic_dev {
struct clk *dmic_clk;
struct clk *bus_clk;
struct reset_control *rst;
struct regmap *regmap;
struct snd_dmaengine_dai_dma_data dma_params_rx;
};
struct dmic_rate {
unsigned int samplerate;
unsigned int rate_bit;
};
static const struct dmic_rate dmic_rate_s[] = {
{48000, 0x0},
{44100, 0x0},
{32000, 0x1},
{24000, 0x2},
{22050, 0x2},
{16000, 0x3},
{12000, 0x4},
{11025, 0x4},
{8000, 0x5},
};
static int sun50i_dmic_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
/* only support capture */
if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
return -EINVAL;
regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
SUN50I_DMIC_RXFIFO_CTL_FLUSH,
SUN50I_DMIC_RXFIFO_CTL_FLUSH);
regmap_write(host->regmap, SUN50I_DMIC_CNT, SUN50I_DMIC_CNT_N);
return 0;
}
static int sun50i_dmic_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
int i = 0;
unsigned long rate = params_rate(params);
unsigned int mclk = 0;
unsigned int channels = params_channels(params);
unsigned int chan_en = (1 << channels) - 1;
struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
/* DMIC num is N+1 */
regmap_update_bits(host->regmap, SUN50I_DMIC_CH_NUM,
SUN50I_DMIC_CH_NUM_N_MASK,
SUN50I_DMIC_CH_NUM_N(channels - 1));
regmap_write(host->regmap, SUN50I_DMIC_HPF_CTRL, chan_en);
regmap_update_bits(host->regmap, SUN50I_DMIC_EN_CTL,
SUN50I_DMIC_EN_CTL_CHAN_MASK,
SUN50I_DMIC_EN_CTL_CHAN(chan_en));
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
SUN50I_DMIC_RXFIFO_CTL_SAMPLE_MASK,
SUN50I_DMIC_RXFIFO_CTL_SAMPLE_16);
break;
case SNDRV_PCM_FORMAT_S24_LE:
regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
SUN50I_DMIC_RXFIFO_CTL_SAMPLE_MASK,
SUN50I_DMIC_RXFIFO_CTL_SAMPLE_24);
break;
default:
dev_err(cpu_dai->dev, "Invalid format!\n");
return -EINVAL;
}
/* The hardware supports FIFO mode 1 for 24-bit samples */
regmap_update_bits(host->regmap, SUN50I_DMIC_RXFIFO_CTL,
SUN50I_DMIC_RXFIFO_CTL_MODE_MASK,
SUN50I_DMIC_RXFIFO_CTL_MODE_MSB);
switch (rate) {
case 11025:
case 22050:
case 44100:
mclk = 22579200;
break;
case 8000:
case 12000:
case 16000:
case 24000:
case 32000:
case 48000:
mclk = 24576000;
break;
default:
dev_err(cpu_dai->dev, "Invalid rate!\n");
return -EINVAL;
}
if (clk_set_rate(host->dmic_clk, mclk)) {
dev_err(cpu_dai->dev, "mclk : %u not support\n", mclk);
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(dmic_rate_s); i++) {
if (dmic_rate_s[i].samplerate == rate) {
regmap_update_bits(host->regmap, SUN50I_DMIC_SR,
SUN50I_DMIC_SR_SAMPLE_RATE_MASK,
SUN50I_DMIC_SR_SAMPLE_RATE(dmic_rate_s[i].rate_bit));
break;
}
}
switch (params_physical_width(params)) {
case 16:
host->dma_params_rx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
case 32:
host->dma_params_rx.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
break;
default:
dev_err(cpu_dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
return -EINVAL;
}
/* oversamplerate adjust */
if (params_rate(params) >= 24000)
regmap_update_bits(host->regmap, SUN50I_DMIC_CTL,
SUN50I_DMIC_CTL_OVERSAMPLE_RATE,
SUN50I_DMIC_CTL_OVERSAMPLE_RATE);
else
regmap_update_bits(host->regmap, SUN50I_DMIC_CTL,
SUN50I_DMIC_CTL_OVERSAMPLE_RATE, 0);
return 0;
}
static int sun50i_dmic_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int ret = 0;
struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(dai);
if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
return -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/* DRQ ENABLE */
regmap_update_bits(host->regmap, SUN50I_DMIC_INTC,
SUN50I_DMIC_FIFO_DRQ_EN,
SUN50I_DMIC_FIFO_DRQ_EN);
/* Global enable */
regmap_update_bits(host->regmap, SUN50I_DMIC_EN_CTL,
SUN50I_DMIC_EN_CTL_GLOBE,
SUN50I_DMIC_EN_CTL_GLOBE);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* DRQ DISABLE */
regmap_update_bits(host->regmap, SUN50I_DMIC_INTC,
SUN50I_DMIC_FIFO_DRQ_EN, 0);
/* Global disable */
regmap_update_bits(host->regmap, SUN50I_DMIC_EN_CTL,
SUN50I_DMIC_EN_CTL_GLOBE, 0);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int sun50i_dmic_soc_dai_probe(struct snd_soc_dai *dai)
{
struct sun50i_dmic_dev *host = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, NULL, &host->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops sun50i_dmic_dai_ops = {
.probe = sun50i_dmic_soc_dai_probe,
.startup = sun50i_dmic_startup,
.trigger = sun50i_dmic_trigger,
.hw_params = sun50i_dmic_hw_params,
};
static const struct regmap_config sun50i_dmic_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN50I_DMIC_VERSION,
.cache_type = REGCACHE_NONE,
};
#define SUN50I_DMIC_RATES (SNDRV_PCM_RATE_8000_48000)
#define SUN50I_DMIC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver sun50i_dmic_dai = {
.capture = {
.channels_min = 1,
.channels_max = 8,
.rates = SUN50I_DMIC_RATES,
.formats = SUN50I_DMIC_FORMATS,
.sig_bits = 21,
},
.ops = &sun50i_dmic_dai_ops,
.name = "dmic",
};
static const struct of_device_id sun50i_dmic_of_match[] = {
{
.compatible = "allwinner,sun50i-h6-dmic",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun50i_dmic_of_match);
static const struct snd_soc_component_driver sun50i_dmic_component = {
.name = "sun50i-dmic",
};
static int sun50i_dmic_runtime_suspend(struct device *dev)
{
struct sun50i_dmic_dev *host = dev_get_drvdata(dev);
clk_disable_unprepare(host->dmic_clk);
clk_disable_unprepare(host->bus_clk);
return 0;
}
static int sun50i_dmic_runtime_resume(struct device *dev)
{
struct sun50i_dmic_dev *host = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(host->dmic_clk);
if (ret)
return ret;
ret = clk_prepare_enable(host->bus_clk);
if (ret) {
clk_disable_unprepare(host->dmic_clk);
return ret;
}
return 0;
}
static int sun50i_dmic_probe(struct platform_device *pdev)
{
struct sun50i_dmic_dev *host;
struct resource *res;
int ret;
void __iomem *base;
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
if (!host)
return -ENOMEM;
/* Get the addresses */
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return dev_err_probe(&pdev->dev, PTR_ERR(base),
"get resource failed.\n");
host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&sun50i_dmic_regmap_config);
/* Clocks */
host->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(host->bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(host->bus_clk),
"failed to get bus clock.\n");
host->dmic_clk = devm_clk_get(&pdev->dev, "mod");
if (IS_ERR(host->dmic_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(host->dmic_clk),
"failed to get dmic clock.\n");
host->dma_params_rx.addr = res->start + SUN50I_DMIC_DATA;
host->dma_params_rx.maxburst = 8;
platform_set_drvdata(pdev, host);
host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
if (IS_ERR(host->rst))
return dev_err_probe(&pdev->dev, PTR_ERR(host->rst),
"Failed to get reset.\n");
reset_control_deassert(host->rst);
ret = devm_snd_soc_register_component(&pdev->dev, &sun50i_dmic_component,
&sun50i_dmic_dai, 1);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"failed to register component.\n");
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = sun50i_dmic_runtime_resume(&pdev->dev);
if (ret)
goto err_disable_runtime_pm;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_suspend;
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
sun50i_dmic_runtime_suspend(&pdev->dev);
err_disable_runtime_pm:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void sun50i_dmic_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
sun50i_dmic_runtime_suspend(&pdev->dev);
}
static const struct dev_pm_ops sun50i_dmic_pm = {
SET_RUNTIME_PM_OPS(sun50i_dmic_runtime_suspend,
sun50i_dmic_runtime_resume, NULL)
};
static struct platform_driver sun50i_dmic_driver = {
.driver = {
.name = "sun50i-dmic",
.of_match_table = sun50i_dmic_of_match,
.pm = &sun50i_dmic_pm,
},
.probe = sun50i_dmic_probe,
.remove_new = sun50i_dmic_remove,
};
module_platform_driver(sun50i_dmic_driver);
MODULE_DESCRIPTION("Allwinner sun50i DMIC SoC Interface");
MODULE_AUTHOR("Ban Tao <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sun50i-dmic");
| linux-master | sound/soc/sunxi/sun50i-dmic.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* This driver supports the analog controls for the internal codec
* found in Allwinner's A64 SoC.
*
* Copyright (C) 2016 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2017 Marcus Cooper <[email protected]>
* Copyright (C) 2018 Vasily Khoruzhick <[email protected]>
*
* Based on sun8i-codec-analog.c
*
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "sun8i-adda-pr-regmap.h"
/* Codec analog control register offsets and bit fields */
#define SUN50I_ADDA_HP_CTRL 0x00
#define SUN50I_ADDA_HP_CTRL_PA_CLK_GATE 7
#define SUN50I_ADDA_HP_CTRL_HPPA_EN 6
#define SUN50I_ADDA_HP_CTRL_HPVOL 0
#define SUN50I_ADDA_OL_MIX_CTRL 0x01
#define SUN50I_ADDA_OL_MIX_CTRL_MIC1 6
#define SUN50I_ADDA_OL_MIX_CTRL_MIC2 5
#define SUN50I_ADDA_OL_MIX_CTRL_PHONE 4
#define SUN50I_ADDA_OL_MIX_CTRL_PHONEN 3
#define SUN50I_ADDA_OL_MIX_CTRL_LINEINL 2
#define SUN50I_ADDA_OL_MIX_CTRL_DACL 1
#define SUN50I_ADDA_OL_MIX_CTRL_DACR 0
#define SUN50I_ADDA_OR_MIX_CTRL 0x02
#define SUN50I_ADDA_OR_MIX_CTRL_MIC1 6
#define SUN50I_ADDA_OR_MIX_CTRL_MIC2 5
#define SUN50I_ADDA_OR_MIX_CTRL_PHONE 4
#define SUN50I_ADDA_OR_MIX_CTRL_PHONEP 3
#define SUN50I_ADDA_OR_MIX_CTRL_LINEINR 2
#define SUN50I_ADDA_OR_MIX_CTRL_DACR 1
#define SUN50I_ADDA_OR_MIX_CTRL_DACL 0
#define SUN50I_ADDA_EARPIECE_CTRL0 0x03
#define SUN50I_ADDA_EARPIECE_CTRL0_EAR_RAMP_TIME 4
#define SUN50I_ADDA_EARPIECE_CTRL0_ESPSR 0
#define SUN50I_ADDA_EARPIECE_CTRL1 0x04
#define SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_EN 7
#define SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_MUTE 6
#define SUN50I_ADDA_EARPIECE_CTRL1_ESP_VOL 0
#define SUN50I_ADDA_LINEOUT_CTRL0 0x05
#define SUN50I_ADDA_LINEOUT_CTRL0_LEN 7
#define SUN50I_ADDA_LINEOUT_CTRL0_REN 6
#define SUN50I_ADDA_LINEOUT_CTRL0_LSRC_SEL 5
#define SUN50I_ADDA_LINEOUT_CTRL0_RSRC_SEL 4
#define SUN50I_ADDA_LINEOUT_CTRL1 0x06
#define SUN50I_ADDA_LINEOUT_CTRL1_VOL 0
#define SUN50I_ADDA_MIC1_CTRL 0x07
#define SUN50I_ADDA_MIC1_CTRL_MIC1G 4
#define SUN50I_ADDA_MIC1_CTRL_MIC1AMPEN 3
#define SUN50I_ADDA_MIC1_CTRL_MIC1BOOST 0
#define SUN50I_ADDA_MIC2_CTRL 0x08
#define SUN50I_ADDA_MIC2_CTRL_MIC2G 4
#define SUN50I_ADDA_MIC2_CTRL_MIC2AMPEN 3
#define SUN50I_ADDA_MIC2_CTRL_MIC2BOOST 0
#define SUN50I_ADDA_LINEIN_CTRL 0x09
#define SUN50I_ADDA_LINEIN_CTRL_LINEING 0
#define SUN50I_ADDA_MIX_DAC_CTRL 0x0a
#define SUN50I_ADDA_MIX_DAC_CTRL_DACAREN 7
#define SUN50I_ADDA_MIX_DAC_CTRL_DACALEN 6
#define SUN50I_ADDA_MIX_DAC_CTRL_RMIXEN 5
#define SUN50I_ADDA_MIX_DAC_CTRL_LMIXEN 4
#define SUN50I_ADDA_MIX_DAC_CTRL_RHPPAMUTE 3
#define SUN50I_ADDA_MIX_DAC_CTRL_LHPPAMUTE 2
#define SUN50I_ADDA_MIX_DAC_CTRL_RHPIS 1
#define SUN50I_ADDA_MIX_DAC_CTRL_LHPIS 0
#define SUN50I_ADDA_L_ADCMIX_SRC 0x0b
#define SUN50I_ADDA_L_ADCMIX_SRC_MIC1 6
#define SUN50I_ADDA_L_ADCMIX_SRC_MIC2 5
#define SUN50I_ADDA_L_ADCMIX_SRC_PHONE 4
#define SUN50I_ADDA_L_ADCMIX_SRC_PHONEN 3
#define SUN50I_ADDA_L_ADCMIX_SRC_LINEINL 2
#define SUN50I_ADDA_L_ADCMIX_SRC_OMIXRL 1
#define SUN50I_ADDA_L_ADCMIX_SRC_OMIXRR 0
#define SUN50I_ADDA_R_ADCMIX_SRC 0x0c
#define SUN50I_ADDA_R_ADCMIX_SRC_MIC1 6
#define SUN50I_ADDA_R_ADCMIX_SRC_MIC2 5
#define SUN50I_ADDA_R_ADCMIX_SRC_PHONE 4
#define SUN50I_ADDA_R_ADCMIX_SRC_PHONEP 3
#define SUN50I_ADDA_R_ADCMIX_SRC_LINEINR 2
#define SUN50I_ADDA_R_ADCMIX_SRC_OMIXR 1
#define SUN50I_ADDA_R_ADCMIX_SRC_OMIXL 0
#define SUN50I_ADDA_ADC_CTRL 0x0d
#define SUN50I_ADDA_ADC_CTRL_ADCREN 7
#define SUN50I_ADDA_ADC_CTRL_ADCLEN 6
#define SUN50I_ADDA_ADC_CTRL_ADCG 0
#define SUN50I_ADDA_HS_MBIAS_CTRL 0x0e
#define SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN 7
#define SUN50I_ADDA_JACK_MIC_CTRL 0x1d
#define SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN 6
#define SUN50I_ADDA_JACK_MIC_CTRL_HMICBIASEN 5
/* mixer controls */
static const struct snd_kcontrol_new sun50i_a64_codec_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
SUN50I_ADDA_OL_MIX_CTRL,
SUN50I_ADDA_OR_MIX_CTRL,
SUN50I_ADDA_OL_MIX_CTRL_MIC1, 1, 0),
SOC_DAPM_DOUBLE_R("Mic2 Playback Switch",
SUN50I_ADDA_OL_MIX_CTRL,
SUN50I_ADDA_OR_MIX_CTRL,
SUN50I_ADDA_OL_MIX_CTRL_MIC2, 1, 0),
SOC_DAPM_DOUBLE_R("Line In Playback Switch",
SUN50I_ADDA_OL_MIX_CTRL,
SUN50I_ADDA_OR_MIX_CTRL,
SUN50I_ADDA_OL_MIX_CTRL_LINEINL, 1, 0),
SOC_DAPM_DOUBLE_R("DAC Playback Switch",
SUN50I_ADDA_OL_MIX_CTRL,
SUN50I_ADDA_OR_MIX_CTRL,
SUN50I_ADDA_OL_MIX_CTRL_DACL, 1, 0),
SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
SUN50I_ADDA_OL_MIX_CTRL,
SUN50I_ADDA_OR_MIX_CTRL,
SUN50I_ADDA_OL_MIX_CTRL_DACR, 1, 0),
};
/* ADC mixer controls */
static const struct snd_kcontrol_new sun50i_codec_adc_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
SUN50I_ADDA_L_ADCMIX_SRC,
SUN50I_ADDA_R_ADCMIX_SRC,
SUN50I_ADDA_L_ADCMIX_SRC_MIC1, 1, 0),
SOC_DAPM_DOUBLE_R("Mic2 Capture Switch",
SUN50I_ADDA_L_ADCMIX_SRC,
SUN50I_ADDA_R_ADCMIX_SRC,
SUN50I_ADDA_L_ADCMIX_SRC_MIC2, 1, 0),
SOC_DAPM_DOUBLE_R("Line In Capture Switch",
SUN50I_ADDA_L_ADCMIX_SRC,
SUN50I_ADDA_R_ADCMIX_SRC,
SUN50I_ADDA_L_ADCMIX_SRC_LINEINL, 1, 0),
SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
SUN50I_ADDA_L_ADCMIX_SRC,
SUN50I_ADDA_R_ADCMIX_SRC,
SUN50I_ADDA_L_ADCMIX_SRC_OMIXRL, 1, 0),
SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
SUN50I_ADDA_L_ADCMIX_SRC,
SUN50I_ADDA_R_ADCMIX_SRC,
SUN50I_ADDA_L_ADCMIX_SRC_OMIXRR, 1, 0),
};
static const DECLARE_TLV_DB_SCALE(sun50i_codec_out_mixer_pregain_scale,
-450, 150, 0);
static const DECLARE_TLV_DB_RANGE(sun50i_codec_mic_gain_scale,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
);
static const DECLARE_TLV_DB_SCALE(sun50i_codec_hp_vol_scale, -6300, 100, 1);
static const DECLARE_TLV_DB_RANGE(sun50i_codec_lineout_vol_scale,
0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
);
static const DECLARE_TLV_DB_RANGE(sun50i_codec_earpiece_vol_scale,
0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
);
/* volume / mute controls */
static const struct snd_kcontrol_new sun50i_a64_codec_controls[] = {
SOC_SINGLE_TLV("Headphone Playback Volume",
SUN50I_ADDA_HP_CTRL,
SUN50I_ADDA_HP_CTRL_HPVOL, 0x3f, 0,
sun50i_codec_hp_vol_scale),
/* Mixer pre-gain */
SOC_SINGLE_TLV("Mic1 Playback Volume", SUN50I_ADDA_MIC1_CTRL,
SUN50I_ADDA_MIC1_CTRL_MIC1G,
0x7, 0, sun50i_codec_out_mixer_pregain_scale),
/* Microphone Amp boost gain */
SOC_SINGLE_TLV("Mic1 Boost Volume", SUN50I_ADDA_MIC1_CTRL,
SUN50I_ADDA_MIC1_CTRL_MIC1BOOST, 0x7, 0,
sun50i_codec_mic_gain_scale),
/* Mixer pre-gain */
SOC_SINGLE_TLV("Mic2 Playback Volume",
SUN50I_ADDA_MIC2_CTRL, SUN50I_ADDA_MIC2_CTRL_MIC2G,
0x7, 0, sun50i_codec_out_mixer_pregain_scale),
/* Microphone Amp boost gain */
SOC_SINGLE_TLV("Mic2 Boost Volume", SUN50I_ADDA_MIC2_CTRL,
SUN50I_ADDA_MIC2_CTRL_MIC2BOOST, 0x7, 0,
sun50i_codec_mic_gain_scale),
/* ADC */
SOC_SINGLE_TLV("ADC Gain Capture Volume", SUN50I_ADDA_ADC_CTRL,
SUN50I_ADDA_ADC_CTRL_ADCG, 0x7, 0,
sun50i_codec_out_mixer_pregain_scale),
/* Mixer pre-gain */
SOC_SINGLE_TLV("Line In Playback Volume", SUN50I_ADDA_LINEIN_CTRL,
SUN50I_ADDA_LINEIN_CTRL_LINEING,
0x7, 0, sun50i_codec_out_mixer_pregain_scale),
SOC_SINGLE_TLV("Line Out Playback Volume",
SUN50I_ADDA_LINEOUT_CTRL1,
SUN50I_ADDA_LINEOUT_CTRL1_VOL, 0x1f, 0,
sun50i_codec_lineout_vol_scale),
SOC_SINGLE_TLV("Earpiece Playback Volume",
SUN50I_ADDA_EARPIECE_CTRL1,
SUN50I_ADDA_EARPIECE_CTRL1_ESP_VOL, 0x1f, 0,
sun50i_codec_earpiece_vol_scale),
};
static const char * const sun50i_codec_hp_src_enum_text[] = {
"DAC", "Mixer",
};
static SOC_ENUM_DOUBLE_DECL(sun50i_codec_hp_src_enum,
SUN50I_ADDA_MIX_DAC_CTRL,
SUN50I_ADDA_MIX_DAC_CTRL_LHPIS,
SUN50I_ADDA_MIX_DAC_CTRL_RHPIS,
sun50i_codec_hp_src_enum_text);
static const struct snd_kcontrol_new sun50i_codec_hp_src[] = {
SOC_DAPM_ENUM("Headphone Source Playback Route",
sun50i_codec_hp_src_enum),
};
static const struct snd_kcontrol_new sun50i_codec_hp_switch =
SOC_DAPM_DOUBLE("Headphone Playback Switch",
SUN50I_ADDA_MIX_DAC_CTRL,
SUN50I_ADDA_MIX_DAC_CTRL_LHPPAMUTE,
SUN50I_ADDA_MIX_DAC_CTRL_RHPPAMUTE, 1, 0);
static const char * const sun50i_codec_lineout_src_enum_text[] = {
"Stereo", "Mono Differential",
};
static SOC_ENUM_DOUBLE_DECL(sun50i_codec_lineout_src_enum,
SUN50I_ADDA_LINEOUT_CTRL0,
SUN50I_ADDA_LINEOUT_CTRL0_LSRC_SEL,
SUN50I_ADDA_LINEOUT_CTRL0_RSRC_SEL,
sun50i_codec_lineout_src_enum_text);
static const struct snd_kcontrol_new sun50i_codec_lineout_src[] = {
SOC_DAPM_ENUM("Line Out Source Playback Route",
sun50i_codec_lineout_src_enum),
};
static const struct snd_kcontrol_new sun50i_codec_lineout_switch =
SOC_DAPM_DOUBLE("Line Out Playback Switch",
SUN50I_ADDA_LINEOUT_CTRL0,
SUN50I_ADDA_LINEOUT_CTRL0_LEN,
SUN50I_ADDA_LINEOUT_CTRL0_REN, 1, 0);
static const char * const sun50i_codec_earpiece_src_enum_text[] = {
"DACR", "DACL", "Right Mixer", "Left Mixer",
};
static SOC_ENUM_SINGLE_DECL(sun50i_codec_earpiece_src_enum,
SUN50I_ADDA_EARPIECE_CTRL0,
SUN50I_ADDA_EARPIECE_CTRL0_ESPSR,
sun50i_codec_earpiece_src_enum_text);
static const struct snd_kcontrol_new sun50i_codec_earpiece_src[] = {
SOC_DAPM_ENUM("Earpiece Source Playback Route",
sun50i_codec_earpiece_src_enum),
};
static const struct snd_kcontrol_new sun50i_codec_earpiece_switch[] = {
SOC_DAPM_SINGLE("Earpiece Playback Switch",
SUN50I_ADDA_EARPIECE_CTRL1,
SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_MUTE, 1, 0),
};
static const struct snd_soc_dapm_widget sun50i_a64_codec_widgets[] = {
/* DAC */
SND_SOC_DAPM_DAC("Left DAC", NULL, SUN50I_ADDA_MIX_DAC_CTRL,
SUN50I_ADDA_MIX_DAC_CTRL_DACALEN, 0),
SND_SOC_DAPM_DAC("Right DAC", NULL, SUN50I_ADDA_MIX_DAC_CTRL,
SUN50I_ADDA_MIX_DAC_CTRL_DACAREN, 0),
/* ADC */
SND_SOC_DAPM_ADC("Left ADC", NULL, SUN50I_ADDA_ADC_CTRL,
SUN50I_ADDA_ADC_CTRL_ADCLEN, 0),
SND_SOC_DAPM_ADC("Right ADC", NULL, SUN50I_ADDA_ADC_CTRL,
SUN50I_ADDA_ADC_CTRL_ADCREN, 0),
/*
* Due to this component and the codec belonging to separate DAPM
* contexts, we need to manually link the above widgets to their
* stream widgets at the card level.
*/
SND_SOC_DAPM_REGULATOR_SUPPLY("cpvdd", 0, 0),
SND_SOC_DAPM_MUX("Left Headphone Source",
SND_SOC_NOPM, 0, 0, sun50i_codec_hp_src),
SND_SOC_DAPM_MUX("Right Headphone Source",
SND_SOC_NOPM, 0, 0, sun50i_codec_hp_src),
SND_SOC_DAPM_SWITCH("Left Headphone Switch",
SND_SOC_NOPM, 0, 0, &sun50i_codec_hp_switch),
SND_SOC_DAPM_SWITCH("Right Headphone Switch",
SND_SOC_NOPM, 0, 0, &sun50i_codec_hp_switch),
SND_SOC_DAPM_OUT_DRV("Left Headphone Amp",
SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUT_DRV("Right Headphone Amp",
SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Headphone Amp", SUN50I_ADDA_HP_CTRL,
SUN50I_ADDA_HP_CTRL_HPPA_EN, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_MUX("Left Line Out Source",
SND_SOC_NOPM, 0, 0, sun50i_codec_lineout_src),
SND_SOC_DAPM_MUX("Right Line Out Source",
SND_SOC_NOPM, 0, 0, sun50i_codec_lineout_src),
SND_SOC_DAPM_SWITCH("Left Line Out Switch",
SND_SOC_NOPM, 0, 0, &sun50i_codec_lineout_switch),
SND_SOC_DAPM_SWITCH("Right Line Out Switch",
SND_SOC_NOPM, 0, 0, &sun50i_codec_lineout_switch),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
SND_SOC_DAPM_MUX("Earpiece Source Playback Route",
SND_SOC_NOPM, 0, 0, sun50i_codec_earpiece_src),
SOC_MIXER_NAMED_CTL_ARRAY("Earpiece Switch",
SND_SOC_NOPM, 0, 0,
sun50i_codec_earpiece_switch),
SND_SOC_DAPM_OUT_DRV("Earpiece Amp", SUN50I_ADDA_EARPIECE_CTRL1,
SUN50I_ADDA_EARPIECE_CTRL1_ESPPA_EN, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("EARPIECE"),
/* Microphone inputs */
SND_SOC_DAPM_INPUT("MIC1"),
/* Microphone Bias */
SND_SOC_DAPM_SUPPLY("MBIAS", SUN50I_ADDA_HS_MBIAS_CTRL,
SUN50I_ADDA_HS_MBIAS_CTRL_MMICBIASEN,
0, NULL, 0),
/* Mic input path */
SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN50I_ADDA_MIC1_CTRL,
SUN50I_ADDA_MIC1_CTRL_MIC1AMPEN, 0, NULL, 0),
/* Microphone input */
SND_SOC_DAPM_INPUT("MIC2"),
/* Microphone Bias */
SND_SOC_DAPM_SUPPLY("HBIAS", SUN50I_ADDA_JACK_MIC_CTRL,
SUN50I_ADDA_JACK_MIC_CTRL_HMICBIASEN,
0, NULL, 0),
/* Mic input path */
SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN50I_ADDA_MIC2_CTRL,
SUN50I_ADDA_MIC2_CTRL_MIC2AMPEN, 0, NULL, 0),
/* Line input */
SND_SOC_DAPM_INPUT("LINEIN"),
/* Mixers */
SND_SOC_DAPM_MIXER("Left Mixer", SUN50I_ADDA_MIX_DAC_CTRL,
SUN50I_ADDA_MIX_DAC_CTRL_LMIXEN, 0,
sun50i_a64_codec_mixer_controls,
ARRAY_SIZE(sun50i_a64_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SUN50I_ADDA_MIX_DAC_CTRL,
SUN50I_ADDA_MIX_DAC_CTRL_RMIXEN, 0,
sun50i_a64_codec_mixer_controls,
ARRAY_SIZE(sun50i_a64_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
sun50i_codec_adc_mixer_controls,
ARRAY_SIZE(sun50i_codec_adc_mixer_controls)),
SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
sun50i_codec_adc_mixer_controls,
ARRAY_SIZE(sun50i_codec_adc_mixer_controls)),
};
static const struct snd_soc_dapm_route sun50i_a64_codec_routes[] = {
/* Left Mixer Routes */
{ "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
{ "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
{ "Left Mixer", "Line In Playback Switch", "LINEIN" },
{ "Left Mixer", "DAC Playback Switch", "Left DAC" },
{ "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
/* Right Mixer Routes */
{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
{ "Right Mixer", "Line In Playback Switch", "LINEIN" },
{ "Right Mixer", "DAC Playback Switch", "Right DAC" },
{ "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
/* Left ADC Mixer Routes */
{ "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
{ "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
{ "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
{ "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
{ "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
/* Right ADC Mixer Routes */
{ "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
{ "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
{ "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
{ "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
{ "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
/* ADC Routes */
{ "Left ADC", NULL, "Left ADC Mixer" },
{ "Right ADC", NULL, "Right ADC Mixer" },
/* Headphone Routes */
{ "Left Headphone Source", "DAC", "Left DAC" },
{ "Left Headphone Source", "Mixer", "Left Mixer" },
{ "Left Headphone Switch", "Headphone Playback Switch", "Left Headphone Source" },
{ "Left Headphone Amp", NULL, "Left Headphone Switch" },
{ "Left Headphone Amp", NULL, "Headphone Amp" },
{ "HP", NULL, "Left Headphone Amp" },
{ "Right Headphone Source", "DAC", "Right DAC" },
{ "Right Headphone Source", "Mixer", "Right Mixer" },
{ "Right Headphone Switch", "Headphone Playback Switch", "Right Headphone Source" },
{ "Right Headphone Amp", NULL, "Right Headphone Switch" },
{ "Right Headphone Amp", NULL, "Headphone Amp" },
{ "HP", NULL, "Right Headphone Amp" },
{ "Headphone Amp", NULL, "cpvdd" },
/* Microphone Routes */
{ "Mic1 Amplifier", NULL, "MIC1"},
/* Microphone Routes */
{ "Mic2 Amplifier", NULL, "MIC2"},
/* Line-out Routes */
{ "Left Line Out Source", "Stereo", "Left Mixer" },
{ "Left Line Out Source", "Mono Differential", "Left Mixer" },
{ "Left Line Out Source", "Mono Differential", "Right Mixer" },
{ "Left Line Out Switch", "Line Out Playback Switch", "Left Line Out Source" },
{ "LINEOUT", NULL, "Left Line Out Switch" },
{ "Right Line Out Switch", "Line Out Playback Switch", "Right Mixer" },
{ "Right Line Out Source", "Stereo", "Right Line Out Switch" },
{ "Right Line Out Source", "Mono Differential", "Left Line Out Switch" },
{ "LINEOUT", NULL, "Right Line Out Source" },
/* Earpiece Routes */
{ "Earpiece Source Playback Route", "DACL", "Left DAC" },
{ "Earpiece Source Playback Route", "DACR", "Right DAC" },
{ "Earpiece Source Playback Route", "Left Mixer", "Left Mixer" },
{ "Earpiece Source Playback Route", "Right Mixer", "Right Mixer" },
{ "Earpiece Switch", "Earpiece Playback Switch", "Earpiece Source Playback Route" },
{ "Earpiece Amp", NULL, "Earpiece Switch" },
{ "EARPIECE", NULL, "Earpiece Amp" },
};
static int sun50i_a64_codec_suspend(struct snd_soc_component *component)
{
return regmap_update_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE),
BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE));
}
static int sun50i_a64_codec_resume(struct snd_soc_component *component)
{
return regmap_update_bits(component->regmap, SUN50I_ADDA_HP_CTRL,
BIT(SUN50I_ADDA_HP_CTRL_PA_CLK_GATE), 0);
}
static const struct snd_soc_component_driver sun50i_codec_analog_cmpnt_drv = {
.controls = sun50i_a64_codec_controls,
.num_controls = ARRAY_SIZE(sun50i_a64_codec_controls),
.dapm_widgets = sun50i_a64_codec_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun50i_a64_codec_widgets),
.dapm_routes = sun50i_a64_codec_routes,
.num_dapm_routes = ARRAY_SIZE(sun50i_a64_codec_routes),
.suspend = sun50i_a64_codec_suspend,
.resume = sun50i_a64_codec_resume,
};
static const struct of_device_id sun50i_codec_analog_of_match[] = {
{
.compatible = "allwinner,sun50i-a64-codec-analog",
},
{}
};
MODULE_DEVICE_TABLE(of, sun50i_codec_analog_of_match);
static int sun50i_codec_analog_probe(struct platform_device *pdev)
{
struct regmap *regmap;
void __iomem *base;
bool enable;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
dev_err(&pdev->dev, "Failed to map the registers\n");
return PTR_ERR(base);
}
regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to create regmap\n");
return PTR_ERR(regmap);
}
enable = device_property_read_bool(&pdev->dev,
"allwinner,internal-bias-resistor");
regmap_update_bits(regmap, SUN50I_ADDA_JACK_MIC_CTRL,
BIT(SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN),
enable << SUN50I_ADDA_JACK_MIC_CTRL_INNERRESEN);
return devm_snd_soc_register_component(&pdev->dev,
&sun50i_codec_analog_cmpnt_drv,
NULL, 0);
}
static struct platform_driver sun50i_codec_analog_driver = {
.driver = {
.name = "sun50i-codec-analog",
.of_match_table = sun50i_codec_analog_of_match,
},
.probe = sun50i_codec_analog_probe,
};
module_platform_driver(sun50i_codec_analog_driver);
MODULE_DESCRIPTION("Allwinner internal codec analog controls driver for A64");
MODULE_AUTHOR("Vasily Khoruzhick <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sun50i-codec-analog");
| linux-master | sound/soc/sunxi/sun50i-codec-analog.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ALSA SoC SPDIF Audio Layer
*
* Copyright 2015 Andrea Venturi <[email protected]>
* Copyright 2015 Marcus Cooper <[email protected]>
*
* Based on the Allwinner SDK driver, released under the GPL.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/regmap.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include <sound/asoundef.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define SUN4I_SPDIF_CTL (0x00)
#define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
#define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
#define SUN4I_SPDIF_CTL_GEN BIT(1)
#define SUN4I_SPDIF_CTL_RESET BIT(0)
#define SUN4I_SPDIF_TXCFG (0x04)
#define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
#define SUN4I_SPDIF_TXCFG_ASS BIT(17)
#define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
#define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
#define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
#define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
#define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
#define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
#define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
#define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
#define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
#define SUN4I_SPDIF_RXCFG (0x08)
#define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
#define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
#define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
#define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
#define SUN4I_SPDIF_TXFIFO (0x0C)
#define SUN4I_SPDIF_RXFIFO (0x10)
#define SUN4I_SPDIF_FCTL (0x14)
#define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
#define SUN4I_SPDIF_FCTL_FTX BIT(17)
#define SUN4I_SPDIF_FCTL_FRX BIT(16)
#define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
#define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
#define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
#define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
#define SUN4I_SPDIF_FCTL_TXIM BIT(2)
#define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
#define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
#define SUN50I_H6_SPDIF_FCTL (0x14)
#define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
#define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
#define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
#define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
#define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
#define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
#define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
#define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
#define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
#define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
#define SUN4I_SPDIF_FSTA (0x18)
#define SUN4I_SPDIF_FSTA_TXE BIT(14)
#define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
#define SUN4I_SPDIF_FSTA_RXA BIT(6)
#define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
#define SUN4I_SPDIF_INT (0x1C)
#define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
#define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
#define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
#define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
#define SUN4I_SPDIF_INT_TXUIEN BIT(6)
#define SUN4I_SPDIF_INT_TXOIEN BIT(5)
#define SUN4I_SPDIF_INT_TXEIEN BIT(4)
#define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
#define SUN4I_SPDIF_INT_RXOIEN BIT(1)
#define SUN4I_SPDIF_INT_RXAIEN BIT(0)
#define SUN4I_SPDIF_ISTA (0x20)
#define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
#define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
#define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
#define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
#define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
#define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
#define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
#define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
#define SUN8I_SPDIF_TXFIFO (0x20)
#define SUN4I_SPDIF_TXCNT (0x24)
#define SUN4I_SPDIF_RXCNT (0x28)
#define SUN4I_SPDIF_TXCHSTA0 (0x2C)
#define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
#define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
#define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
#define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
#define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
#define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
#define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
#define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
#define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
#define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
#define SUN4I_SPDIF_TXCHSTA1 (0x30)
#define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
#define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
#define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
#define SUN4I_SPDIF_RXCHSTA0 (0x34)
#define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
#define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
#define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
#define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
#define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
#define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
#define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
#define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
#define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
#define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
#define SUN4I_SPDIF_RXCHSTA1 (0x38)
#define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
#define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
#define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
#define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
/* Defines for Sampling Frequency */
#define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
#define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
#define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
#define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
#define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
#define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
#define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
#define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
#define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
#define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
#define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
/**
* struct sun4i_spdif_quirks - Differences between SoC variants.
*
* @reg_dac_txdata: TX FIFO offset for DMA config.
* @has_reset: SoC needs reset deasserted.
* @val_fctl_ftx: TX FIFO flush bitmask.
*/
struct sun4i_spdif_quirks {
unsigned int reg_dac_txdata;
bool has_reset;
unsigned int val_fctl_ftx;
};
struct sun4i_spdif_dev {
struct platform_device *pdev;
struct clk *spdif_clk;
struct clk *apb_clk;
struct reset_control *rst;
struct snd_soc_dai_driver cpu_dai_drv;
struct regmap *regmap;
struct snd_dmaengine_dai_dma_data dma_params_tx;
const struct sun4i_spdif_quirks *quirks;
spinlock_t lock;
};
static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
{
const struct sun4i_spdif_quirks *quirks = host->quirks;
/* soft reset SPDIF */
regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
/* flush TX FIFO */
regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
quirks->val_fctl_ftx, quirks->val_fctl_ftx);
/* clear TX counter */
regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
}
static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
struct sun4i_spdif_dev *host)
{
if (substream->runtime->channels == 1)
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_SINGLEMOD,
SUN4I_SPDIF_TXCFG_SINGLEMOD);
/* SPDIF TX ENABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
/* DRQ ENABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
/* Global enable */
regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
}
static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
struct sun4i_spdif_dev *host)
{
/* SPDIF TX DISABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_TXEN, 0);
/* DRQ DISABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
SUN4I_SPDIF_INT_TXDRQEN, 0);
/* Global disable */
regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
SUN4I_SPDIF_CTL_GEN, 0);
}
static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
sun4i_spdif_configure(host);
return 0;
}
static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
int ret = 0;
int fmt;
unsigned long rate = params_rate(params);
u32 mclk_div = 0;
unsigned int mclk = 0;
u32 reg_val;
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
struct platform_device *pdev = host->pdev;
/* Add the PCM and raw data select interface */
switch (params_channels(params)) {
case 1: /* PCM mode */
case 2:
fmt = 0;
break;
case 4: /* raw data mode */
fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
break;
default:
return -EINVAL;
}
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
break;
case SNDRV_PCM_FORMAT_S24_LE:
fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
break;
default:
return -EINVAL;
}
switch (rate) {
case 22050:
case 44100:
case 88200:
case 176400:
mclk = 22579200;
break;
case 24000:
case 32000:
case 48000:
case 96000:
case 192000:
mclk = 24576000;
break;
default:
return -EINVAL;
}
ret = clk_set_rate(host->spdif_clk, mclk);
if (ret < 0) {
dev_err(&pdev->dev,
"Setting SPDIF clock rate for %d Hz failed!\n", mclk);
return ret;
}
regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM);
switch (rate) {
case 22050:
case 24000:
mclk_div = 8;
break;
case 32000:
mclk_div = 6;
break;
case 44100:
case 48000:
mclk_div = 4;
break;
case 88200:
case 96000:
mclk_div = 2;
break;
case 176400:
case 192000:
mclk_div = 1;
break;
default:
return -EINVAL;
}
reg_val = 0;
reg_val |= SUN4I_SPDIF_TXCFG_ASS;
reg_val |= fmt; /* set non audio and bit depth */
reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
return 0;
}
static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int ret = 0;
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
sun4i_snd_txctrl_on(substream, host);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
sun4i_snd_txctrl_off(substream, host);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u8 *status = ucontrol->value.iec958.status;
status[0] = 0xff;
status[1] = 0xff;
status[2] = 0xff;
status[3] = 0xff;
status[4] = 0xff;
status[5] = 0x03;
return 0;
}
static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
u8 *status = ucontrol->value.iec958.status;
unsigned long flags;
unsigned int reg;
spin_lock_irqsave(&host->lock, flags);
regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, ®);
status[0] = reg & 0xff;
status[1] = (reg >> 8) & 0xff;
status[2] = (reg >> 16) & 0xff;
status[3] = (reg >> 24) & 0xff;
regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, ®);
status[4] = reg & 0xff;
status[5] = (reg >> 8) & 0x3;
spin_unlock_irqrestore(&host->lock, flags);
return 0;
}
static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
u8 *status = ucontrol->value.iec958.status;
unsigned long flags;
unsigned int reg;
bool chg0, chg1;
spin_lock_irqsave(&host->lock, flags);
reg = (u32)status[3] << 24;
reg |= (u32)status[2] << 16;
reg |= (u32)status[1] << 8;
reg |= (u32)status[0];
regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA0,
GENMASK(31,0), reg, &chg0);
reg = (u32)status[5] << 8;
reg |= (u32)status[4];
regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA1,
GENMASK(9,0), reg, &chg1);
reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
if (status[0] & IEC958_AES0_NONAUDIO)
reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_CHSTMODE |
SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
spin_unlock_irqrestore(&host->lock, flags);
return chg0 || chg1;
}
static struct snd_kcontrol_new sun4i_spdif_controls[] = {
{
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
.info = sun4i_spdif_info,
.get = sun4i_spdif_get_status_mask
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.info = sun4i_spdif_info,
.get = sun4i_spdif_get_status,
.put = sun4i_spdif_set_status
}
};
static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
{
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
ARRAY_SIZE(sun4i_spdif_controls));
return 0;
}
static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
.probe = sun4i_spdif_soc_dai_probe,
.startup = sun4i_spdif_startup,
.trigger = sun4i_spdif_trigger,
.hw_params = sun4i_spdif_hw_params,
};
static const struct regmap_config sun4i_spdif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN4I_SPDIF_RXCHSTA1,
};
#define SUN4I_RATES SNDRV_PCM_RATE_8000_192000
#define SUN4I_FORMATS (SNDRV_PCM_FORMAT_S16_LE | \
SNDRV_PCM_FORMAT_S20_3LE | \
SNDRV_PCM_FORMAT_S24_LE)
static struct snd_soc_dai_driver sun4i_spdif_dai = {
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SUN4I_RATES,
.formats = SUN4I_FORMATS,
},
.ops = &sun4i_spdif_dai_ops,
.name = "spdif",
};
static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
.reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
.val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
};
static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
.reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
.val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
.has_reset = true,
};
static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
.val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
.has_reset = true,
};
static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
.val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
.has_reset = true,
};
static const struct of_device_id sun4i_spdif_of_match[] = {
{
.compatible = "allwinner,sun4i-a10-spdif",
.data = &sun4i_a10_spdif_quirks,
},
{
.compatible = "allwinner,sun6i-a31-spdif",
.data = &sun6i_a31_spdif_quirks,
},
{
.compatible = "allwinner,sun8i-h3-spdif",
.data = &sun8i_h3_spdif_quirks,
},
{
.compatible = "allwinner,sun50i-h6-spdif",
.data = &sun50i_h6_spdif_quirks,
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
static const struct snd_soc_component_driver sun4i_spdif_component = {
.name = "sun4i-spdif",
.legacy_dai_naming = 1,
};
static int sun4i_spdif_runtime_suspend(struct device *dev)
{
struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
clk_disable_unprepare(host->spdif_clk);
clk_disable_unprepare(host->apb_clk);
return 0;
}
static int sun4i_spdif_runtime_resume(struct device *dev)
{
struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(host->spdif_clk);
if (ret)
return ret;
ret = clk_prepare_enable(host->apb_clk);
if (ret)
clk_disable_unprepare(host->spdif_clk);
return ret;
}
static int sun4i_spdif_probe(struct platform_device *pdev)
{
struct sun4i_spdif_dev *host;
struct resource *res;
const struct sun4i_spdif_quirks *quirks;
int ret;
void __iomem *base;
dev_dbg(&pdev->dev, "Entered %s\n", __func__);
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
if (!host)
return -ENOMEM;
host->pdev = pdev;
spin_lock_init(&host->lock);
/* Initialize this copy of the CPU DAI driver structure */
memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
host->cpu_dai_drv.name = dev_name(&pdev->dev);
/* Get the addresses */
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
quirks = of_device_get_match_data(&pdev->dev);
if (quirks == NULL) {
dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
return -ENODEV;
}
host->quirks = quirks;
host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&sun4i_spdif_regmap_config);
/* Clocks */
host->apb_clk = devm_clk_get(&pdev->dev, "apb");
if (IS_ERR(host->apb_clk)) {
dev_err(&pdev->dev, "failed to get a apb clock.\n");
return PTR_ERR(host->apb_clk);
}
host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
if (IS_ERR(host->spdif_clk)) {
dev_err(&pdev->dev, "failed to get a spdif clock.\n");
return PTR_ERR(host->spdif_clk);
}
host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
host->dma_params_tx.maxburst = 8;
host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
platform_set_drvdata(pdev, host);
if (quirks->has_reset) {
host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
NULL);
if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
return ret;
}
if (!IS_ERR(host->rst))
reset_control_deassert(host->rst);
}
ret = devm_snd_soc_register_component(&pdev->dev,
&sun4i_spdif_component, &sun4i_spdif_dai, 1);
if (ret)
return ret;
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = sun4i_spdif_runtime_resume(&pdev->dev);
if (ret)
goto err_unregister;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret)
goto err_suspend;
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
sun4i_spdif_runtime_suspend(&pdev->dev);
err_unregister:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void sun4i_spdif_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
sun4i_spdif_runtime_suspend(&pdev->dev);
}
static const struct dev_pm_ops sun4i_spdif_pm = {
SET_RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
sun4i_spdif_runtime_resume, NULL)
};
static struct platform_driver sun4i_spdif_driver = {
.driver = {
.name = "sun4i-spdif",
.of_match_table = sun4i_spdif_of_match,
.pm = &sun4i_spdif_pm,
},
.probe = sun4i_spdif_probe,
.remove_new = sun4i_spdif_remove,
};
module_platform_driver(sun4i_spdif_driver);
MODULE_AUTHOR("Marcus Cooper <[email protected]>");
MODULE_AUTHOR("Andrea Venturi <[email protected]>");
MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sun4i-spdif");
| linux-master | sound/soc/sunxi/sun4i-spdif.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Andrea Venturi
* Andrea Venturi <[email protected]>
*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#define SUN4I_I2S_CTRL_REG 0x00
#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
#define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
#define SUN4I_I2S_CTRL_TX_EN BIT(2)
#define SUN4I_I2S_CTRL_RX_EN BIT(1)
#define SUN4I_I2S_CTRL_GL_EN BIT(0)
#define SUN4I_I2S_FMT0_REG 0x04
#define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
#define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
#define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
#define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
#define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
#define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
#define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
#define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
#define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
#define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
#define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
#define SUN4I_I2S_FMT1_REG 0x08
#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8)
#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8)
#define SUN4I_I2S_FIFO_TX_REG 0x0c
#define SUN4I_I2S_FIFO_RX_REG 0x10
#define SUN4I_I2S_FIFO_CTRL_REG 0x14
#define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
#define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
#define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
#define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
#define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
#define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
#define SUN4I_I2S_FIFO_STA_REG 0x18
#define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
#define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
#define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
#define SUN4I_I2S_INT_STA_REG 0x20
#define SUN4I_I2S_CLK_DIV_REG 0x24
#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
#define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
#define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
#define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
#define SUN4I_I2S_TX_CNT_REG 0x28
#define SUN4I_I2S_RX_CNT_REG 0x2c
#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
#define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
#define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
#define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
/* Defines required for sun8i-h3 support */
#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19)
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19)
#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
#define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
#define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7)
#define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7)
#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4)
#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4)
#define SUN8I_I2S_INT_STA_REG 0x0c
#define SUN8I_I2S_FIFO_TX_REG 0x20
#define SUN8I_I2S_CHAN_CFG_REG 0x30
#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4)
#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0)
#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
/* Defines required for sun50i-h6 support */
#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
#define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin) (0x34 + 4 * (pin))
#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin) (0x44 + 8 * (pin))
#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin) (0x48 + 8 * (pin))
#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
#define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68
#define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c
#define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70
#define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74
struct sun4i_i2s;
/**
* struct sun4i_i2s_quirks - Differences between SoC variants.
* @has_reset: SoC needs reset deasserted.
* @reg_offset_txdata: offset of the tx fifo.
* @sun4i_i2s_regmap: regmap config to use.
* @field_clkdiv_mclk_en: regmap field to enable mclk output.
* @field_fmt_wss: regmap field to set word select size.
* @field_fmt_sr: regmap field to set sample resolution.
* @num_din_pins: input pins
* @num_dout_pins: output pins (currently set but unused)
* @bclk_dividers: bit clock dividers array
* @num_bclk_dividers: number of bit clock dividers
* @mclk_dividers: mclk dividers array
* @num_mclk_dividers: number of mclk dividers
* @get_bclk_parent_rate: callback to get bclk parent rate
* @get_sr: callback to get sample resolution
* @get_wss: callback to get word select size
* @set_chan_cfg: callback to set channel configuration
* @set_fmt: callback to set format
*/
struct sun4i_i2s_quirks {
bool has_reset;
unsigned int reg_offset_txdata; /* TX FIFO */
const struct regmap_config *sun4i_i2s_regmap;
/* Register fields for i2s */
struct reg_field field_clkdiv_mclk_en;
struct reg_field field_fmt_wss;
struct reg_field field_fmt_sr;
unsigned int num_din_pins;
unsigned int num_dout_pins;
const struct sun4i_i2s_clk_div *bclk_dividers;
unsigned int num_bclk_dividers;
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned int num_mclk_dividers;
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
int (*get_sr)(unsigned int width);
int (*get_wss)(unsigned int width);
/*
* In the set_chan_cfg() function pointer:
* @slots: channels per frame + padding slots, regardless of format
* @slot_width: bits per sample + padding bits, regardless of format
*/
int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width);
int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
};
struct sun4i_i2s {
struct clk *bus_clk;
struct clk *mod_clk;
struct regmap *regmap;
struct reset_control *rst;
unsigned int format;
unsigned int mclk_freq;
unsigned int slots;
unsigned int slot_width;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct snd_dmaengine_dai_dma_data playback_dma_data;
/* Register fields for i2s */
struct regmap_field *field_clkdiv_mclk_en;
struct regmap_field *field_fmt_wss;
struct regmap_field *field_fmt_sr;
const struct sun4i_i2s_quirks *variant;
};
struct sun4i_i2s_clk_div {
u8 div;
u8 val;
};
static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
{ .div = 2, .val = 0 },
{ .div = 4, .val = 1 },
{ .div = 6, .val = 2 },
{ .div = 8, .val = 3 },
{ .div = 12, .val = 4 },
{ .div = 16, .val = 5 },
/* TODO - extend divide ratio supported by newer SoCs */
};
static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
{ .div = 1, .val = 0 },
{ .div = 2, .val = 1 },
{ .div = 4, .val = 2 },
{ .div = 6, .val = 3 },
{ .div = 8, .val = 4 },
{ .div = 12, .val = 5 },
{ .div = 16, .val = 6 },
{ .div = 24, .val = 7 },
/* TODO - extend divide ratio supported by newer SoCs */
};
static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
{ .div = 1, .val = 1 },
{ .div = 2, .val = 2 },
{ .div = 4, .val = 3 },
{ .div = 6, .val = 4 },
{ .div = 8, .val = 5 },
{ .div = 12, .val = 6 },
{ .div = 16, .val = 7 },
{ .div = 24, .val = 8 },
{ .div = 32, .val = 9 },
{ .div = 48, .val = 10 },
{ .div = 64, .val = 11 },
{ .div = 96, .val = 12 },
{ .div = 128, .val = 13 },
{ .div = 176, .val = 14 },
{ .div = 192, .val = 15 },
};
static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
{
return i2s->mclk_freq;
}
static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
{
return clk_get_rate(i2s->mod_clk);
}
static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
unsigned long parent_rate,
unsigned int sampling_rate,
unsigned int channels,
unsigned int word_size)
{
const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
int div = parent_rate / sampling_rate / word_size / channels;
int i;
for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {
const struct sun4i_i2s_clk_div *bdiv = ÷rs[i];
if (bdiv->div == div)
return bdiv->val;
}
return -EINVAL;
}
static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
unsigned long parent_rate,
unsigned long mclk_rate)
{
const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
int div = parent_rate / mclk_rate;
int i;
for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {
const struct sun4i_i2s_clk_div *mdiv = ÷rs[i];
if (mdiv->div == div)
return mdiv->val;
}
return -EINVAL;
}
static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
{
int i;
for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
if (sun4i_i2s_oversample_rates[i] == oversample)
return true;
return false;
}
static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
unsigned int rate,
unsigned int slots,
unsigned int slot_width)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int oversample_rate, clk_rate, bclk_parent_rate;
int bclk_div, mclk_div;
int ret;
switch (rate) {
case 176400:
case 88200:
case 44100:
case 22050:
case 11025:
clk_rate = 22579200;
break;
case 192000:
case 128000:
case 96000:
case 64000:
case 48000:
case 32000:
case 24000:
case 16000:
case 12000:
case 8000:
clk_rate = 24576000;
break;
default:
dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
return -EINVAL;
}
ret = clk_set_rate(i2s->mod_clk, clk_rate);
if (ret)
return ret;
oversample_rate = i2s->mclk_freq / rate;
if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
dev_err(dai->dev, "Unsupported oversample rate: %d\n",
oversample_rate);
return -EINVAL;
}
bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s);
bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate,
rate, slots, slot_width);
if (bclk_div < 0) {
dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
return -EINVAL;
}
mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
if (mclk_div < 0) {
dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
return -EINVAL;
}
regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
return 0;
}
static int sun4i_i2s_get_sr(unsigned int width)
{
switch (width) {
case 16:
return 0;
case 20:
return 1;
case 24:
return 2;
}
return -EINVAL;
}
static int sun4i_i2s_get_wss(unsigned int width)
{
switch (width) {
case 16:
return 0;
case 20:
return 1;
case 24:
return 2;
case 32:
return 3;
}
return -EINVAL;
}
static int sun8i_i2s_get_sr_wss(unsigned int width)
{
switch (width) {
case 8:
return 1;
case 12:
return 2;
case 16:
return 3;
case 20:
return 4;
case 24:
return 5;
case 28:
return 6;
case 32:
return 7;
}
return -EINVAL;
}
static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width)
{
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210);
/* Configure the channels */
regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,
SUN4I_I2S_CHAN_SEL_MASK,
SUN4I_I2S_CHAN_SEL(channels));
regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG,
SUN4I_I2S_CHAN_SEL_MASK,
SUN4I_I2S_CHAN_SEL(channels));
return 0;
}
static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width)
{
unsigned int lrck_period;
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
/* Configure the channels */
regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
SUN4I_I2S_CHAN_SEL_MASK,
SUN4I_I2S_CHAN_SEL(channels));
regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
SUN4I_I2S_CHAN_SEL_MASK,
SUN4I_I2S_CHAN_SEL(channels));
regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
lrck_period = slot_width * slots;
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_I2S:
lrck_period = slot_width;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
SUN8I_I2S_TX_CHAN_EN_MASK,
SUN8I_I2S_TX_CHAN_EN(channels));
return 0;
}
static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
unsigned int channels, unsigned int slots,
unsigned int slot_width)
{
unsigned int lrck_period;
/* Map the channels for playback and capture */
regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98);
regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210);
if (i2s->variant->num_din_pins > 1) {
regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C);
regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908);
regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504);
regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100);
} else {
regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
}
/* Configure the channels */
regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
SUN50I_H6_I2S_TX_CHAN_SEL(channels));
regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
SUN50I_H6_I2S_TX_CHAN_SEL(channels));
regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
lrck_period = slot_width * slots;
break;
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
case SND_SOC_DAIFMT_I2S:
lrck_period = slot_width;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
SUN50I_H6_I2S_TX_CHAN_EN_MASK,
SUN50I_H6_I2S_TX_CHAN_EN(channels));
return 0;
}
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int word_size = params_width(params);
unsigned int slot_width = params_physical_width(params);
unsigned int channels = params_channels(params);
unsigned int slots = channels;
int ret, sr, wss;
u32 width;
if (i2s->slots)
slots = i2s->slots;
if (i2s->slot_width)
slot_width = i2s->slot_width;
ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width);
if (ret < 0) {
dev_err(dai->dev, "Invalid channel configuration\n");
return ret;
}
/* Set significant bits in our FIFOs */
regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
case 32:
width = DMA_SLAVE_BUSWIDTH_4_BYTES;
break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
return -EINVAL;
}
i2s->playback_dma_data.addr_width = width;
sr = i2s->variant->get_sr(word_size);
if (sr < 0)
return -EINVAL;
wss = i2s->variant->get_wss(slot_width);
if (wss < 0)
return -EINVAL;
regmap_field_write(i2s->field_fmt_wss, wss);
regmap_field_write(i2s->field_fmt_sr, sr);
return sun4i_i2s_set_clk_rate(dai, params_rate(params),
slots, slot_width);
}
static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
unsigned int fmt)
{
u32 val;
/* DAI clock polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_NF:
val = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK |
SUN4I_I2S_FMT0_BCLK_POLARITY_MASK,
val);
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val = SUN4I_I2S_FMT0_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = SUN4I_I2S_FMT0_FMT_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN4I_I2S_FMT0_FMT_MASK, val);
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* BCLK and LRCLK master */
val = SUN4I_I2S_CTRL_MODE_MASTER;
break;
case SND_SOC_DAIFMT_BC_FC:
/* BCLK and LRCLK slave */
val = SUN4I_I2S_CTRL_MODE_SLAVE;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_MODE_MASK, val);
return 0;
}
static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
unsigned int fmt)
{
u32 mode, val;
u8 offset;
/*
* DAI clock polarity
*
* The setup for LRCK contradicts the datasheet, but under a
* scope it's clear that the LRCK polarity is reversed
* compared to the expected polarity on the bus.
*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
val = 0;
break;
case SND_SOC_DAIFMT_NB_NF:
val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
val);
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
mode = SUN8I_I2S_CTRL_MODE_PCM;
offset = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
mode = SUN8I_I2S_CTRL_MODE_PCM;
offset = 0;
break;
case SND_SOC_DAIFMT_I2S:
mode = SUN8I_I2S_CTRL_MODE_LEFT;
offset = 1;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode = SUN8I_I2S_CTRL_MODE_LEFT;
offset = 0;
break;
case SND_SOC_DAIFMT_RIGHT_J:
mode = SUN8I_I2S_CTRL_MODE_RIGHT;
offset = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN8I_I2S_CTRL_MODE_MASK, mode);
regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
SUN8I_I2S_TX_CHAN_OFFSET_MASK,
SUN8I_I2S_TX_CHAN_OFFSET(offset));
regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
SUN8I_I2S_TX_CHAN_OFFSET_MASK,
SUN8I_I2S_TX_CHAN_OFFSET(offset));
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* BCLK and LRCLK master */
val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
break;
case SND_SOC_DAIFMT_BC_FC:
/* BCLK and LRCLK slave */
val = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
val);
/* Set sign extension to pad out LSB with 0 */
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG,
SUN8I_I2S_FMT1_REG_SEXT_MASK,
SUN8I_I2S_FMT1_REG_SEXT(0));
return 0;
}
static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
unsigned int fmt)
{
u32 mode, val;
u8 offset;
/*
* DAI clock polarity
*
* The setup for LRCK contradicts the datasheet, but under a
* scope it's clear that the LRCK polarity is reversed
* compared to the expected polarity on the bus.
*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
val = 0;
break;
case SND_SOC_DAIFMT_NB_NF:
val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
val);
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
mode = SUN8I_I2S_CTRL_MODE_PCM;
offset = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
mode = SUN8I_I2S_CTRL_MODE_PCM;
offset = 0;
break;
case SND_SOC_DAIFMT_I2S:
mode = SUN8I_I2S_CTRL_MODE_LEFT;
offset = 1;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode = SUN8I_I2S_CTRL_MODE_LEFT;
offset = 0;
break;
case SND_SOC_DAIFMT_RIGHT_J:
mode = SUN8I_I2S_CTRL_MODE_RIGHT;
offset = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN8I_I2S_CTRL_MODE_MASK, mode);
regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* BCLK and LRCLK master */
val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
break;
case SND_SOC_DAIFMT_BC_FC:
/* BCLK and LRCLK slave */
val = 0;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
val);
/* Set sign extension to pad out LSB with 0 */
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG,
SUN8I_I2S_FMT1_REG_SEXT_MASK,
SUN8I_I2S_FMT1_REG_SEXT(0));
return 0;
}
static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int ret;
ret = i2s->variant->set_fmt(i2s, fmt);
if (ret) {
dev_err(dai->dev, "Unsupported format configuration\n");
return ret;
}
i2s->format = fmt;
return 0;
}
static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
{
/* Flush RX FIFO */
regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
/* Clear RX counter */
regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
/* Enable RX Block */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_RX_EN,
SUN4I_I2S_CTRL_RX_EN);
/* Enable RX DRQ */
regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
}
static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
{
/* Flush TX FIFO */
regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
/* Clear TX counter */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
/* Enable TX Block */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_TX_EN,
SUN4I_I2S_CTRL_TX_EN);
/* Enable TX DRQ */
regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
}
static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
{
/* Disable RX Block */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_RX_EN,
0);
/* Disable RX DRQ */
regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
0);
}
static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
{
/* Disable TX Block */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_TX_EN,
0);
/* Disable TX DRQ */
regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
0);
}
static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
sun4i_i2s_start_playback(i2s);
else
sun4i_i2s_start_capture(i2s);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
sun4i_i2s_stop_playback(i2s);
else
sun4i_i2s_stop_capture(i2s);
break;
default:
return -EINVAL;
}
return 0;
}
static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
if (clk_id != 0)
return -EINVAL;
i2s->mclk_freq = freq;
return 0;
}
static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
if (slots > 8)
return -EINVAL;
i2s->slots = slots;
i2s->slot_width = slot_width;
return 0;
}
static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai,
&i2s->playback_dma_data,
&i2s->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
.probe = sun4i_i2s_dai_probe,
.hw_params = sun4i_i2s_hw_params,
.set_fmt = sun4i_i2s_set_fmt,
.set_sysclk = sun4i_i2s_set_sysclk,
.set_tdm_slot = sun4i_i2s_set_tdm_slot,
.trigger = sun4i_i2s_trigger,
};
#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver sun4i_i2s_component = {
.name = "sun4i-dai",
.legacy_dai_naming = 1,
};
static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SUN4I_I2S_FIFO_TX_REG:
return false;
default:
return true;
}
}
static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SUN4I_I2S_FIFO_RX_REG:
case SUN4I_I2S_FIFO_STA_REG:
return false;
default:
return true;
}
}
static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SUN4I_I2S_FIFO_RX_REG:
case SUN4I_I2S_INT_STA_REG:
case SUN4I_I2S_RX_CNT_REG:
case SUN4I_I2S_TX_CNT_REG:
return true;
default:
return false;
}
}
static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SUN8I_I2S_FIFO_TX_REG:
return false;
default:
return true;
}
}
static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SUN4I_I2S_FIFO_CTRL_REG:
case SUN4I_I2S_FIFO_RX_REG:
case SUN4I_I2S_FIFO_STA_REG:
case SUN4I_I2S_RX_CNT_REG:
case SUN4I_I2S_TX_CNT_REG:
case SUN8I_I2S_FIFO_TX_REG:
case SUN8I_I2S_INT_STA_REG:
return true;
default:
return false;
}
}
static const struct reg_default sun4i_i2s_reg_defaults[] = {
{ SUN4I_I2S_CTRL_REG, 0x00000000 },
{ SUN4I_I2S_FMT0_REG, 0x0000000c },
{ SUN4I_I2S_FMT1_REG, 0x00004020 },
{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
{ SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
{ SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
{ SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
{ SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
};
static const struct reg_default sun8i_i2s_reg_defaults[] = {
{ SUN4I_I2S_CTRL_REG, 0x00060000 },
{ SUN4I_I2S_FMT0_REG, 0x00000033 },
{ SUN4I_I2S_FMT1_REG, 0x00000030 },
{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
{ SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
{ SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
{ SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
{ SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
{ SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
};
static const struct reg_default sun50i_h6_i2s_reg_defaults[] = {
{ SUN4I_I2S_CTRL_REG, 0x00060000 },
{ SUN4I_I2S_FMT0_REG, 0x00000033 },
{ SUN4I_I2S_FMT1_REG, 0x00000030 },
{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
{ SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
{ SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 },
{ SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 },
{ SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 },
{ SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
{ SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
{ SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },
};
static const struct regmap_config sun4i_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN4I_I2S_RX_CHAN_MAP_REG,
.cache_type = REGCACHE_FLAT,
.reg_defaults = sun4i_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults),
.writeable_reg = sun4i_i2s_wr_reg,
.readable_reg = sun4i_i2s_rd_reg,
.volatile_reg = sun4i_i2s_volatile_reg,
};
static const struct regmap_config sun8i_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN8I_I2S_RX_CHAN_MAP_REG,
.cache_type = REGCACHE_FLAT,
.reg_defaults = sun8i_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
.writeable_reg = sun4i_i2s_wr_reg,
.readable_reg = sun8i_i2s_rd_reg,
.volatile_reg = sun8i_i2s_volatile_reg,
};
static const struct regmap_config sun50i_h6_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SUN50I_R329_I2S_RX_CHAN_MAP3_REG,
.cache_type = REGCACHE_FLAT,
.reg_defaults = sun50i_h6_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults),
.writeable_reg = sun4i_i2s_wr_reg,
.readable_reg = sun8i_i2s_rd_reg,
.volatile_reg = sun8i_i2s_volatile_reg,
};
static int sun4i_i2s_runtime_resume(struct device *dev)
{
struct sun4i_i2s *i2s = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s->bus_clk);
if (ret) {
dev_err(dev, "Failed to enable bus clock\n");
return ret;
}
regcache_cache_only(i2s->regmap, false);
regcache_mark_dirty(i2s->regmap);
ret = regcache_sync(i2s->regmap);
if (ret) {
dev_err(dev, "Failed to sync regmap cache\n");
goto err_disable_clk;
}
/* Enable the whole hardware block */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
/* Enable the first output line */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_SDO_EN_MASK,
SUN4I_I2S_CTRL_SDO_EN(0));
ret = clk_prepare_enable(i2s->mod_clk);
if (ret) {
dev_err(dev, "Failed to enable module clock\n");
goto err_disable_clk;
}
return 0;
err_disable_clk:
clk_disable_unprepare(i2s->bus_clk);
return ret;
}
static int sun4i_i2s_runtime_suspend(struct device *dev)
{
struct sun4i_i2s *i2s = dev_get_drvdata(dev);
clk_disable_unprepare(i2s->mod_clk);
/* Disable our output lines */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
/* Disable the whole hardware block */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
SUN4I_I2S_CTRL_GL_EN, 0);
regcache_cache_only(i2s->regmap, true);
clk_disable_unprepare(i2s->bus_clk);
return 0;
}
static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.has_reset = false,
.reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.bclk_dividers = sun4i_i2s_bclk_div,
.num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
.mclk_dividers = sun4i_i2s_mclk_div,
.num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
.set_fmt = sun4i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.bclk_dividers = sun4i_i2s_bclk_div,
.num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
.mclk_dividers = sun4i_i2s_mclk_div,
.num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
.set_fmt = sun4i_i2s_set_soc_fmt,
};
/*
* This doesn't describe the TDM controller documented in the A83t
* datasheet, but the three undocumented I2S controller that use the
* older design.
*/
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.bclk_dividers = sun4i_i2s_bclk_div,
.num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
.mclk_dividers = sun4i_i2s_mclk_div,
.num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
.set_fmt = sun4i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.bclk_dividers = sun8i_i2s_clk_div,
.num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.mclk_dividers = sun8i_i2s_clk_div,
.num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun8i_i2s_set_chan_cfg,
.set_fmt = sun8i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.bclk_dividers = sun4i_i2s_bclk_div,
.num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
.mclk_dividers = sun4i_i2s_mclk_div,
.num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
.set_fmt = sun4i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.bclk_dividers = sun8i_i2s_clk_div,
.num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.mclk_dividers = sun8i_i2s_clk_div,
.num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
.set_fmt = sun50i_h6_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun50i_r329_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.num_din_pins = 4,
.num_dout_pins = 4,
.bclk_dividers = sun8i_i2s_clk_div,
.num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.mclk_dividers = sun8i_i2s_clk_div,
.num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
.set_fmt = sun50i_h6_i2s_set_soc_fmt,
};
static int sun4i_i2s_init_regmap_fields(struct device *dev,
struct sun4i_i2s *i2s)
{
i2s->field_clkdiv_mclk_en =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_clkdiv_mclk_en);
if (IS_ERR(i2s->field_clkdiv_mclk_en))
return PTR_ERR(i2s->field_clkdiv_mclk_en);
i2s->field_fmt_wss =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_fmt_wss);
if (IS_ERR(i2s->field_fmt_wss))
return PTR_ERR(i2s->field_fmt_wss);
i2s->field_fmt_sr =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_fmt_sr);
if (IS_ERR(i2s->field_fmt_sr))
return PTR_ERR(i2s->field_fmt_sr);
return 0;
}
static int sun4i_i2s_probe(struct platform_device *pdev)
{
struct sun4i_i2s *i2s;
struct resource *res;
void __iomem *regs;
int irq, ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
platform_set_drvdata(pdev, i2s);
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
i2s->variant = of_device_get_match_data(&pdev->dev);
if (!i2s->variant) {
dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
return -ENODEV;
}
i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
if (IS_ERR(i2s->bus_clk)) {
dev_err(&pdev->dev, "Can't get our bus clock\n");
return PTR_ERR(i2s->bus_clk);
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
i2s->variant->sun4i_i2s_regmap);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "Regmap initialisation failed\n");
return PTR_ERR(i2s->regmap);
}
i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
if (IS_ERR(i2s->mod_clk)) {
dev_err(&pdev->dev, "Can't get our mod clock\n");
return PTR_ERR(i2s->mod_clk);
}
if (i2s->variant->has_reset) {
i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(i2s->rst)) {
dev_err(&pdev->dev, "Failed to get reset control\n");
return PTR_ERR(i2s->rst);
}
}
if (!IS_ERR(i2s->rst)) {
ret = reset_control_deassert(i2s->rst);
if (ret) {
dev_err(&pdev->dev,
"Failed to deassert the reset control\n");
return -EINVAL;
}
}
i2s->playback_dma_data.addr = res->start +
i2s->variant->reg_offset_txdata;
i2s->playback_dma_data.maxburst = 8;
i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
i2s->capture_dma_data.maxburst = 8;
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = sun4i_i2s_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
if (ret) {
dev_err(&pdev->dev, "Could not initialise regmap fields\n");
goto err_suspend;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
goto err_suspend;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&sun4i_i2s_component,
&sun4i_i2s_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
goto err_suspend;
}
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
sun4i_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
if (!IS_ERR(i2s->rst))
reset_control_assert(i2s->rst);
return ret;
}
static void sun4i_i2s_remove(struct platform_device *pdev)
{
struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
sun4i_i2s_runtime_suspend(&pdev->dev);
if (!IS_ERR(i2s->rst))
reset_control_assert(i2s->rst);
}
static const struct of_device_id sun4i_i2s_match[] = {
{
.compatible = "allwinner,sun4i-a10-i2s",
.data = &sun4i_a10_i2s_quirks,
},
{
.compatible = "allwinner,sun6i-a31-i2s",
.data = &sun6i_a31_i2s_quirks,
},
{
.compatible = "allwinner,sun8i-a83t-i2s",
.data = &sun8i_a83t_i2s_quirks,
},
{
.compatible = "allwinner,sun8i-h3-i2s",
.data = &sun8i_h3_i2s_quirks,
},
{
.compatible = "allwinner,sun50i-a64-codec-i2s",
.data = &sun50i_a64_codec_i2s_quirks,
},
{
.compatible = "allwinner,sun50i-h6-i2s",
.data = &sun50i_h6_i2s_quirks,
},
{
.compatible = "allwinner,sun50i-r329-i2s",
.data = &sun50i_r329_i2s_quirks,
},
{}
};
MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
static const struct dev_pm_ops sun4i_i2s_pm_ops = {
.runtime_resume = sun4i_i2s_runtime_resume,
.runtime_suspend = sun4i_i2s_runtime_suspend,
};
static struct platform_driver sun4i_i2s_driver = {
.probe = sun4i_i2s_probe,
.remove_new = sun4i_i2s_remove,
.driver = {
.name = "sun4i-i2s",
.of_match_table = sun4i_i2s_match,
.pm = &sun4i_i2s_pm_ops,
},
};
module_platform_driver(sun4i_i2s_driver);
MODULE_AUTHOR("Andrea Venturi <[email protected]>");
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
MODULE_DESCRIPTION("Allwinner A10 I2S driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/sunxi/sun4i-i2s.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* This driver supports the analog controls for the internal codec
* found in Allwinner's A31s, A23, A33 and H3 SoCs.
*
* Copyright 2016 Chen-Yu Tsai <[email protected]>
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include "sun8i-adda-pr-regmap.h"
/* Codec analog control register offsets and bit fields */
#define SUN8I_ADDA_HP_VOLC 0x00
#define SUN8I_ADDA_HP_VOLC_PA_CLK_GATE 7
#define SUN8I_ADDA_HP_VOLC_HP_VOL 0
#define SUN8I_ADDA_LOMIXSC 0x01
#define SUN8I_ADDA_LOMIXSC_MIC1 6
#define SUN8I_ADDA_LOMIXSC_MIC2 5
#define SUN8I_ADDA_LOMIXSC_PHONE 4
#define SUN8I_ADDA_LOMIXSC_PHONEN 3
#define SUN8I_ADDA_LOMIXSC_LINEINL 2
#define SUN8I_ADDA_LOMIXSC_DACL 1
#define SUN8I_ADDA_LOMIXSC_DACR 0
#define SUN8I_ADDA_ROMIXSC 0x02
#define SUN8I_ADDA_ROMIXSC_MIC1 6
#define SUN8I_ADDA_ROMIXSC_MIC2 5
#define SUN8I_ADDA_ROMIXSC_PHONE 4
#define SUN8I_ADDA_ROMIXSC_PHONEP 3
#define SUN8I_ADDA_ROMIXSC_LINEINR 2
#define SUN8I_ADDA_ROMIXSC_DACR 1
#define SUN8I_ADDA_ROMIXSC_DACL 0
#define SUN8I_ADDA_DAC_PA_SRC 0x03
#define SUN8I_ADDA_DAC_PA_SRC_DACAREN 7
#define SUN8I_ADDA_DAC_PA_SRC_DACALEN 6
#define SUN8I_ADDA_DAC_PA_SRC_RMIXEN 5
#define SUN8I_ADDA_DAC_PA_SRC_LMIXEN 4
#define SUN8I_ADDA_DAC_PA_SRC_RHPPAMUTE 3
#define SUN8I_ADDA_DAC_PA_SRC_LHPPAMUTE 2
#define SUN8I_ADDA_DAC_PA_SRC_RHPIS 1
#define SUN8I_ADDA_DAC_PA_SRC_LHPIS 0
#define SUN8I_ADDA_PHONEIN_GCTRL 0x04
#define SUN8I_ADDA_PHONEIN_GCTRL_PHONEPG 4
#define SUN8I_ADDA_PHONEIN_GCTRL_PHONENG 0
#define SUN8I_ADDA_LINEIN_GCTRL 0x05
#define SUN8I_ADDA_LINEIN_GCTRL_LINEING 4
#define SUN8I_ADDA_LINEIN_GCTRL_PHONEG 0
#define SUN8I_ADDA_MICIN_GCTRL 0x06
#define SUN8I_ADDA_MICIN_GCTRL_MIC1G 4
#define SUN8I_ADDA_MICIN_GCTRL_MIC2G 0
#define SUN8I_ADDA_PAEN_HP_CTRL 0x07
#define SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN 7
#define SUN8I_ADDA_PAEN_HP_CTRL_LINEOUTEN 7 /* H3 specific */
#define SUN8I_ADDA_PAEN_HP_CTRL_HPCOM_FC 5
#define SUN8I_ADDA_PAEN_HP_CTRL_COMPTEN 4
#define SUN8I_ADDA_PAEN_HP_CTRL_PA_ANTI_POP_CTRL 2
#define SUN8I_ADDA_PAEN_HP_CTRL_LTRNMUTE 1
#define SUN8I_ADDA_PAEN_HP_CTRL_RTLNMUTE 0
#define SUN8I_ADDA_PHONEOUT_CTRL 0x08
#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUTG 5
#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUTEN 4
#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_MIC1 3
#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_MIC2 2
#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_RMIX 1
#define SUN8I_ADDA_PHONEOUT_CTRL_PHONEOUT_LMIX 0
#define SUN8I_ADDA_PHONE_GAIN_CTRL 0x09
#define SUN8I_ADDA_PHONE_GAIN_CTRL_LINEOUT_VOL 3
#define SUN8I_ADDA_PHONE_GAIN_CTRL_PHONEPREG 0
#define SUN8I_ADDA_MIC2G_CTRL 0x0a
#define SUN8I_ADDA_MIC2G_CTRL_MIC2AMPEN 7
#define SUN8I_ADDA_MIC2G_CTRL_MIC2BOOST 4
#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTLEN 3
#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTREN 2
#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTLSRC 1
#define SUN8I_ADDA_MIC2G_CTRL_LINEOUTRSRC 0
#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL 0x0b
#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_HMICBIASEN 7
#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MMICBIASEN 6
#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_HMICBIAS_MODE 5
#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1AMPEN 3
#define SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1BOOST 0
#define SUN8I_ADDA_LADCMIXSC 0x0c
#define SUN8I_ADDA_LADCMIXSC_MIC1 6
#define SUN8I_ADDA_LADCMIXSC_MIC2 5
#define SUN8I_ADDA_LADCMIXSC_PHONE 4
#define SUN8I_ADDA_LADCMIXSC_PHONEN 3
#define SUN8I_ADDA_LADCMIXSC_LINEINL 2
#define SUN8I_ADDA_LADCMIXSC_OMIXRL 1
#define SUN8I_ADDA_LADCMIXSC_OMIXRR 0
#define SUN8I_ADDA_RADCMIXSC 0x0d
#define SUN8I_ADDA_RADCMIXSC_MIC1 6
#define SUN8I_ADDA_RADCMIXSC_MIC2 5
#define SUN8I_ADDA_RADCMIXSC_PHONE 4
#define SUN8I_ADDA_RADCMIXSC_PHONEP 3
#define SUN8I_ADDA_RADCMIXSC_LINEINR 2
#define SUN8I_ADDA_RADCMIXSC_OMIXR 1
#define SUN8I_ADDA_RADCMIXSC_OMIXL 0
#define SUN8I_ADDA_RES 0x0e
#define SUN8I_ADDA_RES_MMICBIAS_SEL 4
#define SUN8I_ADDA_RES_PA_ANTI_POP_CTRL 0
#define SUN8I_ADDA_ADC_AP_EN 0x0f
#define SUN8I_ADDA_ADC_AP_EN_ADCREN 7
#define SUN8I_ADDA_ADC_AP_EN_ADCLEN 6
#define SUN8I_ADDA_ADC_AP_EN_ADCG 0
/* mixer controls */
static const struct snd_kcontrol_new sun8i_codec_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("DAC Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_DACL, 1, 0),
SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_DACR, 1, 0),
SOC_DAPM_DOUBLE_R("Line In Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_LINEINL, 1, 0),
SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_MIC1, 1, 0),
SOC_DAPM_DOUBLE_R("Mic2 Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_MIC2, 1, 0),
};
/* mixer controls */
static const struct snd_kcontrol_new sun8i_v3s_codec_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("DAC Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_DACL, 1, 0),
SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_DACR, 1, 0),
SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
SUN8I_ADDA_LOMIXSC,
SUN8I_ADDA_ROMIXSC,
SUN8I_ADDA_LOMIXSC_MIC1, 1, 0),
};
/* ADC mixer controls */
static const struct snd_kcontrol_new sun8i_codec_adc_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_OMIXRL, 1, 0),
SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_OMIXRR, 1, 0),
SOC_DAPM_DOUBLE_R("Line In Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_LINEINL, 1, 0),
SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_MIC1, 1, 0),
SOC_DAPM_DOUBLE_R("Mic2 Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_MIC2, 1, 0),
};
/* ADC mixer controls */
static const struct snd_kcontrol_new sun8i_v3s_codec_adc_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_OMIXRL, 1, 0),
SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_OMIXRR, 1, 0),
SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
SUN8I_ADDA_LADCMIXSC,
SUN8I_ADDA_RADCMIXSC,
SUN8I_ADDA_LADCMIXSC_MIC1, 1, 0),
};
/* volume / mute controls */
static const DECLARE_TLV_DB_SCALE(sun8i_codec_out_mixer_pregain_scale,
-450, 150, 0);
static const DECLARE_TLV_DB_RANGE(sun8i_codec_mic_gain_scale,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
);
static const struct snd_kcontrol_new sun8i_codec_common_controls[] = {
/* Mixer pre-gain */
SOC_SINGLE_TLV("Mic1 Playback Volume", SUN8I_ADDA_MICIN_GCTRL,
SUN8I_ADDA_MICIN_GCTRL_MIC1G,
0x7, 0, sun8i_codec_out_mixer_pregain_scale),
/* Microphone Amp boost gain */
SOC_SINGLE_TLV("Mic1 Boost Volume", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1BOOST, 0x7, 0,
sun8i_codec_mic_gain_scale),
/* ADC */
SOC_SINGLE_TLV("ADC Gain Capture Volume", SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCG, 0x7, 0,
sun8i_codec_out_mixer_pregain_scale),
};
static const struct snd_soc_dapm_widget sun8i_codec_common_widgets[] = {
/* ADC */
SND_SOC_DAPM_ADC("Left ADC", NULL, SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0),
SND_SOC_DAPM_ADC("Right ADC", NULL, SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCREN, 0),
/* DAC */
SND_SOC_DAPM_DAC("Left DAC", NULL, SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_DACALEN, 0),
SND_SOC_DAPM_DAC("Right DAC", NULL, SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_DACAREN, 0),
/*
* Due to this component and the codec belonging to separate DAPM
* contexts, we need to manually link the above widgets to their
* stream widgets at the card level.
*/
/* Microphone input */
SND_SOC_DAPM_INPUT("MIC1"),
/* Mic input path */
SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1AMPEN, 0, NULL, 0),
};
static const struct snd_soc_dapm_widget sun8i_codec_mixer_widgets[] = {
SND_SOC_DAPM_MIXER("Left Mixer", SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_LMIXEN, 0,
sun8i_codec_mixer_controls,
ARRAY_SIZE(sun8i_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_RMIXEN, 0,
sun8i_codec_mixer_controls,
ARRAY_SIZE(sun8i_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Left ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0,
sun8i_codec_adc_mixer_controls,
ARRAY_SIZE(sun8i_codec_adc_mixer_controls)),
SND_SOC_DAPM_MIXER("Right ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCREN, 0,
sun8i_codec_adc_mixer_controls,
ARRAY_SIZE(sun8i_codec_adc_mixer_controls)),
};
static const struct snd_soc_dapm_widget sun8i_v3s_codec_mixer_widgets[] = {
SND_SOC_DAPM_MIXER("Left Mixer", SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_LMIXEN, 0,
sun8i_v3s_codec_mixer_controls,
ARRAY_SIZE(sun8i_v3s_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_RMIXEN, 0,
sun8i_v3s_codec_mixer_controls,
ARRAY_SIZE(sun8i_v3s_codec_mixer_controls)),
SND_SOC_DAPM_MIXER("Left ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0,
sun8i_v3s_codec_adc_mixer_controls,
ARRAY_SIZE(sun8i_v3s_codec_adc_mixer_controls)),
SND_SOC_DAPM_MIXER("Right ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
SUN8I_ADDA_ADC_AP_EN_ADCREN, 0,
sun8i_v3s_codec_adc_mixer_controls,
ARRAY_SIZE(sun8i_v3s_codec_adc_mixer_controls)),
};
static const struct snd_soc_dapm_route sun8i_codec_common_routes[] = {
/* Microphone Routes */
{ "Mic1 Amplifier", NULL, "MIC1"},
};
static const struct snd_soc_dapm_route sun8i_codec_mixer_routes[] = {
/* Left Mixer Routes */
{ "Left Mixer", "DAC Playback Switch", "Left DAC" },
{ "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
{ "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
/* Right Mixer Routes */
{ "Right Mixer", "DAC Playback Switch", "Right DAC" },
{ "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
/* Left ADC Mixer Routes */
{ "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
{ "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
{ "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
/* Right ADC Mixer Routes */
{ "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
{ "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
{ "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
/* ADC Routes */
{ "Left ADC", NULL, "Left ADC Mixer" },
{ "Right ADC", NULL, "Right ADC Mixer" },
};
/* headphone specific controls, widgets, and routes */
static const DECLARE_TLV_DB_SCALE(sun8i_codec_hp_vol_scale, -6300, 100, 1);
static const struct snd_kcontrol_new sun8i_codec_headphone_controls[] = {
SOC_SINGLE_TLV("Headphone Playback Volume",
SUN8I_ADDA_HP_VOLC,
SUN8I_ADDA_HP_VOLC_HP_VOL, 0x3f, 0,
sun8i_codec_hp_vol_scale),
SOC_DOUBLE("Headphone Playback Switch",
SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_LHPPAMUTE,
SUN8I_ADDA_DAC_PA_SRC_RHPPAMUTE, 1, 0),
};
static const char * const sun8i_codec_hp_src_enum_text[] = {
"DAC", "Mixer",
};
static SOC_ENUM_DOUBLE_DECL(sun8i_codec_hp_src_enum,
SUN8I_ADDA_DAC_PA_SRC,
SUN8I_ADDA_DAC_PA_SRC_LHPIS,
SUN8I_ADDA_DAC_PA_SRC_RHPIS,
sun8i_codec_hp_src_enum_text);
static const struct snd_kcontrol_new sun8i_codec_hp_src[] = {
SOC_DAPM_ENUM("Headphone Source Playback Route",
sun8i_codec_hp_src_enum),
};
static int sun8i_headphone_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
if (SND_SOC_DAPM_EVENT_ON(event)) {
snd_soc_component_update_bits(component, SUN8I_ADDA_PAEN_HP_CTRL,
BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN),
BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN));
/*
* Need a delay to have the amplifier up. 700ms seems the best
* compromise between the time to let the amplifier up and the
* time not to feel this delay while playing a sound.
*/
msleep(700);
} else if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_update_bits(component, SUN8I_ADDA_PAEN_HP_CTRL,
BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN),
0x0);
}
return 0;
}
static const struct snd_soc_dapm_widget sun8i_codec_headphone_widgets[] = {
SND_SOC_DAPM_MUX("Headphone Source Playback Route",
SND_SOC_NOPM, 0, 0, sun8i_codec_hp_src),
SND_SOC_DAPM_OUT_DRV_E("Headphone Amp", SUN8I_ADDA_PAEN_HP_CTRL,
SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN, 0, NULL, 0,
sun8i_headphone_amp_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN8I_ADDA_PAEN_HP_CTRL,
SUN8I_ADDA_PAEN_HP_CTRL_COMPTEN, 0, NULL, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN8I_ADDA_PAEN_HP_CTRL,
SUN8I_ADDA_PAEN_HP_CTRL_HPCOM_FC, 0x3, 0x3, 0),
SND_SOC_DAPM_OUTPUT("HP"),
};
static const struct snd_soc_dapm_route sun8i_codec_headphone_routes[] = {
{ "Headphone Source Playback Route", "DAC", "Left DAC" },
{ "Headphone Source Playback Route", "DAC", "Right DAC" },
{ "Headphone Source Playback Route", "Mixer", "Left Mixer" },
{ "Headphone Source Playback Route", "Mixer", "Right Mixer" },
{ "Headphone Amp", NULL, "Headphone Source Playback Route" },
{ "HPCOM", NULL, "HPCOM Protection" },
{ "HP", NULL, "Headphone Amp" },
};
static int sun8i_codec_add_headphone(struct snd_soc_component *cmpnt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
ret = snd_soc_add_component_controls(cmpnt,
sun8i_codec_headphone_controls,
ARRAY_SIZE(sun8i_codec_headphone_controls));
if (ret) {
dev_err(dev, "Failed to add Headphone controls: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_headphone_widgets,
ARRAY_SIZE(sun8i_codec_headphone_widgets));
if (ret) {
dev_err(dev, "Failed to add Headphone DAPM widgets: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_headphone_routes,
ARRAY_SIZE(sun8i_codec_headphone_routes));
if (ret) {
dev_err(dev, "Failed to add Headphone DAPM routes: %d\n", ret);
return ret;
}
return 0;
}
/* mbias specific widget */
static const struct snd_soc_dapm_widget sun8i_codec_mbias_widgets[] = {
SND_SOC_DAPM_SUPPLY("MBIAS", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MMICBIASEN,
0, NULL, 0),
};
static int sun8i_codec_add_mbias(struct snd_soc_component *cmpnt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_mbias_widgets,
ARRAY_SIZE(sun8i_codec_mbias_widgets));
if (ret)
dev_err(dev, "Failed to add MBIAS DAPM widgets: %d\n", ret);
return ret;
}
/* hmic specific widget */
static const struct snd_soc_dapm_widget sun8i_codec_hmic_widgets[] = {
SND_SOC_DAPM_SUPPLY("HBIAS", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
SUN8I_ADDA_MIC1G_MICBIAS_CTRL_HMICBIASEN,
0, NULL, 0),
};
static int sun8i_codec_add_hmic(struct snd_soc_component *cmpnt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_hmic_widgets,
ARRAY_SIZE(sun8i_codec_hmic_widgets));
if (ret)
dev_err(dev, "Failed to add Mic3 DAPM widgets: %d\n", ret);
return ret;
}
/* line in specific controls, widgets and rines */
static const struct snd_kcontrol_new sun8i_codec_linein_controls[] = {
/* Mixer pre-gain */
SOC_SINGLE_TLV("Line In Playback Volume", SUN8I_ADDA_LINEIN_GCTRL,
SUN8I_ADDA_LINEIN_GCTRL_LINEING,
0x7, 0, sun8i_codec_out_mixer_pregain_scale),
};
static const struct snd_soc_dapm_widget sun8i_codec_linein_widgets[] = {
/* Line input */
SND_SOC_DAPM_INPUT("LINEIN"),
};
static const struct snd_soc_dapm_route sun8i_codec_linein_routes[] = {
{ "Left Mixer", "Line In Playback Switch", "LINEIN" },
{ "Right Mixer", "Line In Playback Switch", "LINEIN" },
{ "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
{ "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
};
static int sun8i_codec_add_linein(struct snd_soc_component *cmpnt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
ret = snd_soc_add_component_controls(cmpnt,
sun8i_codec_linein_controls,
ARRAY_SIZE(sun8i_codec_linein_controls));
if (ret) {
dev_err(dev, "Failed to add Line In controls: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_linein_widgets,
ARRAY_SIZE(sun8i_codec_linein_widgets));
if (ret) {
dev_err(dev, "Failed to add Line In DAPM widgets: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_linein_routes,
ARRAY_SIZE(sun8i_codec_linein_routes));
if (ret) {
dev_err(dev, "Failed to add Line In DAPM routes: %d\n", ret);
return ret;
}
return 0;
}
/* line out specific controls, widgets and routes */
static const DECLARE_TLV_DB_RANGE(sun8i_codec_lineout_vol_scale,
0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
);
static const struct snd_kcontrol_new sun8i_codec_lineout_controls[] = {
SOC_SINGLE_TLV("Line Out Playback Volume",
SUN8I_ADDA_PHONE_GAIN_CTRL,
SUN8I_ADDA_PHONE_GAIN_CTRL_LINEOUT_VOL, 0x1f, 0,
sun8i_codec_lineout_vol_scale),
SOC_DOUBLE("Line Out Playback Switch",
SUN8I_ADDA_MIC2G_CTRL,
SUN8I_ADDA_MIC2G_CTRL_LINEOUTLEN,
SUN8I_ADDA_MIC2G_CTRL_LINEOUTREN, 1, 0),
};
static const char * const sun8i_codec_lineout_src_enum_text[] = {
"Stereo", "Mono Differential",
};
static SOC_ENUM_DOUBLE_DECL(sun8i_codec_lineout_src_enum,
SUN8I_ADDA_MIC2G_CTRL,
SUN8I_ADDA_MIC2G_CTRL_LINEOUTLSRC,
SUN8I_ADDA_MIC2G_CTRL_LINEOUTRSRC,
sun8i_codec_lineout_src_enum_text);
static const struct snd_kcontrol_new sun8i_codec_lineout_src[] = {
SOC_DAPM_ENUM("Line Out Source Playback Route",
sun8i_codec_lineout_src_enum),
};
static const struct snd_soc_dapm_widget sun8i_codec_lineout_widgets[] = {
SND_SOC_DAPM_MUX("Line Out Source Playback Route",
SND_SOC_NOPM, 0, 0, sun8i_codec_lineout_src),
/* It is unclear if this is a buffer or gate, model it as a supply */
SND_SOC_DAPM_SUPPLY("Line Out Enable", SUN8I_ADDA_PAEN_HP_CTRL,
SUN8I_ADDA_PAEN_HP_CTRL_LINEOUTEN, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("LINEOUT"),
};
static const struct snd_soc_dapm_route sun8i_codec_lineout_routes[] = {
{ "Line Out Source Playback Route", "Stereo", "Left Mixer" },
{ "Line Out Source Playback Route", "Stereo", "Right Mixer" },
{ "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
{ "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
{ "LINEOUT", NULL, "Line Out Source Playback Route" },
{ "LINEOUT", NULL, "Line Out Enable", },
};
static int sun8i_codec_add_lineout(struct snd_soc_component *cmpnt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
ret = snd_soc_add_component_controls(cmpnt,
sun8i_codec_lineout_controls,
ARRAY_SIZE(sun8i_codec_lineout_controls));
if (ret) {
dev_err(dev, "Failed to add Line Out controls: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_lineout_widgets,
ARRAY_SIZE(sun8i_codec_lineout_widgets));
if (ret) {
dev_err(dev, "Failed to add Line Out DAPM widgets: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_lineout_routes,
ARRAY_SIZE(sun8i_codec_lineout_routes));
if (ret) {
dev_err(dev, "Failed to add Line Out DAPM routes: %d\n", ret);
return ret;
}
return 0;
}
/* mic2 specific controls, widgets and routes */
static const struct snd_kcontrol_new sun8i_codec_mic2_controls[] = {
/* Mixer pre-gain */
SOC_SINGLE_TLV("Mic2 Playback Volume",
SUN8I_ADDA_MICIN_GCTRL, SUN8I_ADDA_MICIN_GCTRL_MIC2G,
0x7, 0, sun8i_codec_out_mixer_pregain_scale),
/* Microphone Amp boost gain */
SOC_SINGLE_TLV("Mic2 Boost Volume", SUN8I_ADDA_MIC2G_CTRL,
SUN8I_ADDA_MIC2G_CTRL_MIC2BOOST, 0x7, 0,
sun8i_codec_mic_gain_scale),
};
static const struct snd_soc_dapm_widget sun8i_codec_mic2_widgets[] = {
/* Microphone input */
SND_SOC_DAPM_INPUT("MIC2"),
/* Mic input path */
SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN8I_ADDA_MIC2G_CTRL,
SUN8I_ADDA_MIC2G_CTRL_MIC2AMPEN, 0, NULL, 0),
};
static const struct snd_soc_dapm_route sun8i_codec_mic2_routes[] = {
{ "Mic2 Amplifier", NULL, "MIC2"},
{ "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
{ "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
{ "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
};
static int sun8i_codec_add_mic2(struct snd_soc_component *cmpnt)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
ret = snd_soc_add_component_controls(cmpnt,
sun8i_codec_mic2_controls,
ARRAY_SIZE(sun8i_codec_mic2_controls));
if (ret) {
dev_err(dev, "Failed to add MIC2 controls: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_mic2_widgets,
ARRAY_SIZE(sun8i_codec_mic2_widgets));
if (ret) {
dev_err(dev, "Failed to add MIC2 DAPM widgets: %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_mic2_routes,
ARRAY_SIZE(sun8i_codec_mic2_routes));
if (ret) {
dev_err(dev, "Failed to add MIC2 DAPM routes: %d\n", ret);
return ret;
}
return 0;
}
struct sun8i_codec_analog_quirks {
bool has_headphone;
bool has_hmic;
bool has_linein;
bool has_lineout;
bool has_mbias;
bool has_mic2;
};
static const struct sun8i_codec_analog_quirks sun8i_a23_quirks = {
.has_headphone = true,
.has_hmic = true,
.has_linein = true,
.has_mbias = true,
.has_mic2 = true,
};
static const struct sun8i_codec_analog_quirks sun8i_h3_quirks = {
.has_linein = true,
.has_lineout = true,
.has_mbias = true,
.has_mic2 = true,
};
static int sun8i_codec_analog_add_mixer(struct snd_soc_component *cmpnt,
const struct sun8i_codec_analog_quirks *quirks)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cmpnt);
struct device *dev = cmpnt->dev;
int ret;
if (!quirks->has_mic2 && !quirks->has_linein) {
/*
* Apply the special widget set which has uses a control
* without MIC2 and Line In, for SoCs without these.
* TODO: not all special cases are supported now, this case
* is present because it's the case of V3s.
*/
ret = snd_soc_dapm_new_controls(dapm,
sun8i_v3s_codec_mixer_widgets,
ARRAY_SIZE(sun8i_v3s_codec_mixer_widgets));
if (ret) {
dev_err(dev, "Failed to add V3s Mixer DAPM widgets: %d\n", ret);
return ret;
}
} else {
/* Apply the generic mixer widget set. */
ret = snd_soc_dapm_new_controls(dapm,
sun8i_codec_mixer_widgets,
ARRAY_SIZE(sun8i_codec_mixer_widgets));
if (ret) {
dev_err(dev, "Failed to add Mixer DAPM widgets: %d\n", ret);
return ret;
}
}
ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_mixer_routes,
ARRAY_SIZE(sun8i_codec_mixer_routes));
if (ret) {
dev_err(dev, "Failed to add Mixer DAPM routes: %d\n", ret);
return ret;
}
return 0;
}
static const struct sun8i_codec_analog_quirks sun8i_v3s_quirks = {
.has_headphone = true,
.has_hmic = true,
};
static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt)
{
struct device *dev = cmpnt->dev;
const struct sun8i_codec_analog_quirks *quirks;
int ret;
/*
* This would never return NULL unless someone directly registers a
* platform device matching this driver's name, without specifying a
* device tree node.
*/
quirks = of_device_get_match_data(dev);
/* Add controls, widgets, and routes for individual features */
ret = sun8i_codec_analog_add_mixer(cmpnt, quirks);
if (ret)
return ret;
if (quirks->has_headphone) {
ret = sun8i_codec_add_headphone(cmpnt);
if (ret)
return ret;
}
if (quirks->has_hmic) {
ret = sun8i_codec_add_hmic(cmpnt);
if (ret)
return ret;
}
if (quirks->has_linein) {
ret = sun8i_codec_add_linein(cmpnt);
if (ret)
return ret;
}
if (quirks->has_lineout) {
ret = sun8i_codec_add_lineout(cmpnt);
if (ret)
return ret;
}
if (quirks->has_mbias) {
ret = sun8i_codec_add_mbias(cmpnt);
if (ret)
return ret;
}
if (quirks->has_mic2) {
ret = sun8i_codec_add_mic2(cmpnt);
if (ret)
return ret;
}
return 0;
}
static const struct snd_soc_component_driver sun8i_codec_analog_cmpnt_drv = {
.controls = sun8i_codec_common_controls,
.num_controls = ARRAY_SIZE(sun8i_codec_common_controls),
.dapm_widgets = sun8i_codec_common_widgets,
.num_dapm_widgets = ARRAY_SIZE(sun8i_codec_common_widgets),
.dapm_routes = sun8i_codec_common_routes,
.num_dapm_routes = ARRAY_SIZE(sun8i_codec_common_routes),
.probe = sun8i_codec_analog_cmpnt_probe,
};
static const struct of_device_id sun8i_codec_analog_of_match[] = {
{
.compatible = "allwinner,sun8i-a23-codec-analog",
.data = &sun8i_a23_quirks,
},
{
.compatible = "allwinner,sun8i-h3-codec-analog",
.data = &sun8i_h3_quirks,
},
{
.compatible = "allwinner,sun8i-v3s-codec-analog",
.data = &sun8i_v3s_quirks,
},
{}
};
MODULE_DEVICE_TABLE(of, sun8i_codec_analog_of_match);
static int sun8i_codec_analog_probe(struct platform_device *pdev)
{
struct regmap *regmap;
void __iomem *base;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
dev_err(&pdev->dev, "Failed to map the registers\n");
return PTR_ERR(base);
}
regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to create regmap\n");
return PTR_ERR(regmap);
}
return devm_snd_soc_register_component(&pdev->dev,
&sun8i_codec_analog_cmpnt_drv,
NULL, 0);
}
static struct platform_driver sun8i_codec_analog_driver = {
.driver = {
.name = "sun8i-codec-analog",
.of_match_table = sun8i_codec_analog_of_match,
},
.probe = sun8i_codec_analog_probe,
};
module_platform_driver(sun8i_codec_analog_driver);
MODULE_DESCRIPTION("Allwinner internal codec analog controls driver");
MODULE_AUTHOR("Chen-Yu Tsai <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sun8i-codec-analog");
| linux-master | sound/soc/sunxi/sun8i-codec-analog.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
*
* Copyright (C) 2015 Linaro, Ltd
* Author: Andy Green <[email protected]>
*
* This driver only deals with S2 interface (BT)
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <linux/interrupt.h>
#include <linux/reset.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/mfd/syscon.h>
#include <linux/reset-controller.h>
#include "hi6210-i2s.h"
struct hi6210_i2s {
struct device *dev;
struct reset_control *rc;
struct clk *clk[8];
int clocks;
struct snd_soc_dai_driver dai;
void __iomem *base;
struct regmap *sysctrl;
phys_addr_t base_phys;
struct snd_dmaengine_dai_dma_data dma_data[2];
int clk_rate;
spinlock_t lock;
int rate;
int format;
u8 bits;
u8 channels;
u8 id;
u8 channel_length;
u8 use;
u32 master:1;
u32 status:1;
};
#define SC_PERIPH_CLKEN1 0x210
#define SC_PERIPH_CLKDIS1 0x214
#define SC_PERIPH_CLKEN3 0x230
#define SC_PERIPH_CLKDIS3 0x234
#define SC_PERIPH_CLKEN12 0x270
#define SC_PERIPH_CLKDIS12 0x274
#define SC_PERIPH_RSTEN1 0x310
#define SC_PERIPH_RSTDIS1 0x314
#define SC_PERIPH_RSTSTAT1 0x318
#define SC_PERIPH_RSTEN2 0x320
#define SC_PERIPH_RSTDIS2 0x324
#define SC_PERIPH_RSTSTAT2 0x328
#define SOC_PMCTRL_BBPPLLALIAS 0x48
enum {
CLK_DACODEC,
CLK_I2S_BASE,
};
static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
{
writel(val, i2s->base + reg);
}
static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
{
return readl(i2s->base + reg);
}
static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
int ret, n;
u32 val;
/* deassert reset on ABB */
regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
if (val & BIT(4))
regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
for (n = 0; n < i2s->clocks; n++) {
ret = clk_prepare_enable(i2s->clk[n]);
if (ret)
goto err_unprepare_clk;
}
ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
if (ret) {
dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
__func__, ret);
goto err_unprepare_clk;
}
/* enable clock before frequency division */
regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
/* enable codec working clock / == "codec bus clock" */
regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
/* deassert reset on codec / interface clock / working clock */
regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
/* not interested in i2s irqs */
val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
val |= 0x3f;
hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
/* reset the stereo downlink fifo */
val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
val |= (BIT(5) | BIT(4));
hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
val &= ~(BIT(5) | BIT(4));
hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
/* mux 11/12 = APB not i2s */
val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
/* BT R ch 0 = mixer op of DACR ch */
val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
/* BT L ch = 1 = mux 7 = "mixer output of DACL */
val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
val |= HII2S_SW_RST_N__SW_RST_N;
hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
return 0;
err_unprepare_clk:
while (n--)
clk_disable_unprepare(i2s->clk[n]);
return ret;
}
static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
int n;
for (n = 0; n < i2s->clocks; n++)
clk_disable_unprepare(i2s->clk[n]);
regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
}
static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
{
struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
u32 val;
spin_lock(&i2s->lock);
if (on) {
/* enable S2 TX */
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val |= HII2S_I2S_CFG__S2_IF_TX_EN;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
} else {
/* disable S2 TX */
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
}
spin_unlock(&i2s->lock);
}
static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
{
struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
u32 val;
spin_lock(&i2s->lock);
if (on) {
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val |= HII2S_I2S_CFG__S2_IF_RX_EN;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
} else {
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
}
spin_unlock(&i2s->lock);
}
static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
/*
* We don't actually set the hardware until the hw_params
* call, but we need to validate the user input here.
*/
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
case SND_SOC_DAIFMT_BP_FP:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
break;
default:
return -EINVAL;
}
i2s->format = fmt;
i2s->master = (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
SND_SOC_DAIFMT_BP_FP;
return 0;
}
static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
u32 val;
struct snd_dmaengine_dai_dma_data *dma_data;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_U16_LE:
signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
fallthrough;
case SNDRV_PCM_FORMAT_S16_LE:
bits = HII2S_BITS_16;
break;
case SNDRV_PCM_FORMAT_U24_LE:
signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
fallthrough;
case SNDRV_PCM_FORMAT_S24_LE:
bits = HII2S_BITS_24;
break;
default:
dev_err(cpu_dai->dev, "Bad format\n");
return -EINVAL;
}
switch (params_rate(params)) {
case 8000:
rate = HII2S_FS_RATE_8KHZ;
break;
case 16000:
rate = HII2S_FS_RATE_16KHZ;
break;
case 32000:
rate = HII2S_FS_RATE_32KHZ;
break;
case 48000:
rate = HII2S_FS_RATE_48KHZ;
break;
case 96000:
rate = HII2S_FS_RATE_96KHZ;
break;
case 192000:
rate = HII2S_FS_RATE_192KHZ;
break;
default:
dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
return -EINVAL;
}
if (!(params_channels(params))) {
dev_err(cpu_dai->dev, "Bad channels\n");
return -EINVAL;
}
dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
switch (bits) {
case HII2S_BITS_24:
i2s->bits = 32;
dma_data->addr_width = 3;
break;
default:
i2s->bits = 16;
dma_data->addr_width = 2;
break;
}
i2s->rate = params_rate(params);
i2s->channels = params_channels(params);
i2s->channel_length = i2s->channels * i2s->bits;
val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
(HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
(HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
(HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
(30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
(16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
(30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
val |= (BIT(19) | BIT(18) | BIT(17) |
HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
switch (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
i2s->master = false;
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val |= HII2S_I2S_CFG__S2_MST_SLV;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
break;
case SND_SOC_DAIFMT_BP_FP:
i2s->master = true;
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val &= ~HII2S_I2S_CFG__S2_MST_SLV;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
break;
default:
WARN_ONCE(1, "Invalid i2s->fmt CLOCK_PROVIDER_MASK. This shouldn't happen\n");
return -EINVAL;
}
switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
fmt = HII2S_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
fmt = HII2S_FORMAT_LEFT_JUST;
break;
case SND_SOC_DAIFMT_RIGHT_J:
fmt = HII2S_FORMAT_RIGHT_JUST;
break;
default:
WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
return -EINVAL;
}
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
dma_data->maxburst = 2;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
else
dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
switch (i2s->channels) {
case 1:
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val |= HII2S_I2S_CFG__S2_FRAME_MODE;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
break;
default:
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
break;
}
/* clear loopback, set signed type and word length */
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
val |= signed_data;
val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
if (!i2s->master)
return 0;
/* set DAC and related units to correct rate */
val = hi6210_read_reg(i2s, HII2S_FS_CFG);
val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
hi6210_write_reg(i2s, HII2S_FS_CFG, val);
return 0;
}
static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
pr_debug("%s\n", __func__);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
hi6210_i2s_rxctrl(cpu_dai, 1);
else
hi6210_i2s_txctrl(cpu_dai, 1);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
hi6210_i2s_rxctrl(cpu_dai, 0);
else
hi6210_i2s_txctrl(cpu_dai, 0);
break;
default:
dev_err(cpu_dai->dev, "unknown cmd\n");
return -EINVAL;
}
return 0;
}
static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai,
&i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
&i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
return 0;
}
static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
.probe = hi6210_i2s_dai_probe,
.trigger = hi6210_i2s_trigger,
.hw_params = hi6210_i2s_hw_params,
.set_fmt = hi6210_i2s_set_fmt,
.startup = hi6210_i2s_startup,
.shutdown = hi6210_i2s_shutdown,
};
static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_U16_LE,
.rates = SNDRV_PCM_RATE_48000,
},
.capture = {
.channels_min = 2,
.channels_max = 2,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_U16_LE,
.rates = SNDRV_PCM_RATE_48000,
},
.ops = &hi6210_i2s_dai_ops,
};
static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
.name = "hi6210_i2s-i2s",
.legacy_dai_naming = 1,
};
static int hi6210_i2s_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct hi6210_i2s *i2s;
struct resource *res;
int ret;
i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->dev = dev;
spin_lock_init(&i2s->lock);
i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(i2s->base))
return PTR_ERR(i2s->base);
i2s->base_phys = (phys_addr_t)res->start;
i2s->dai = hi6210_i2s_dai_init;
dev_set_drvdata(dev, i2s);
i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
"hisilicon,sysctrl-syscon");
if (IS_ERR(i2s->sysctrl))
return PTR_ERR(i2s->sysctrl);
i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec");
if (IS_ERR(i2s->clk[CLK_DACODEC]))
return PTR_ERR(i2s->clk[CLK_DACODEC]);
i2s->clocks++;
i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base");
if (IS_ERR(i2s->clk[CLK_I2S_BASE]))
return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
i2s->clocks++;
ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
if (ret)
return ret;
ret = devm_snd_soc_register_component(dev, &hi6210_i2s_i2s_comp,
&i2s->dai, 1);
return ret;
}
static const struct of_device_id hi6210_i2s_dt_ids[] = {
{ .compatible = "hisilicon,hi6210-i2s" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
static struct platform_driver hi6210_i2s_driver = {
.probe = hi6210_i2s_probe,
.driver = {
.name = "hi6210_i2s",
.of_match_table = hi6210_i2s_dt_ids,
},
};
module_platform_driver(hi6210_i2s_driver);
MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
MODULE_AUTHOR("Andy Green <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/hisilicon/hi6210-i2s.c |
// SPDX-License-Identifier: GPL-2.0-or-later
// linux/sound/bcm/bcm63xx-i2s-whistler.c
// BCM63xx whistler i2s driver
// Copyright (c) 2020 Broadcom Corporation
// Author: Kevin-Ke Li <[email protected]>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "bcm63xx-i2s.h"
#define DRV_NAME "brcm-i2s"
static bool brcm_i2s_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TX_CFG ... I2S_TX_DESC_IFF_LEN:
case I2S_TX_CFG_2 ... I2S_RX_DESC_IFF_LEN:
case I2S_RX_CFG_2 ... I2S_REG_MAX:
return true;
default:
return false;
}
}
static bool brcm_i2s_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TX_CFG ... I2S_REG_MAX:
return true;
default:
return false;
}
}
static bool brcm_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TX_CFG:
case I2S_TX_IRQ_CTL:
case I2S_TX_DESC_IFF_ADDR:
case I2S_TX_DESC_IFF_LEN:
case I2S_TX_DESC_OFF_ADDR:
case I2S_TX_DESC_OFF_LEN:
case I2S_TX_CFG_2:
case I2S_RX_CFG:
case I2S_RX_IRQ_CTL:
case I2S_RX_DESC_OFF_ADDR:
case I2S_RX_DESC_OFF_LEN:
case I2S_RX_DESC_IFF_LEN:
case I2S_RX_DESC_IFF_ADDR:
case I2S_RX_CFG_2:
return true;
default:
return false;
}
}
static const struct regmap_config brcm_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = I2S_REG_MAX,
.writeable_reg = brcm_i2s_wr_reg,
.readable_reg = brcm_i2s_rd_reg,
.volatile_reg = brcm_i2s_volatile_reg,
.cache_type = REGCACHE_FLAT,
};
static int bcm63xx_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int ret = 0;
struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
ret = clk_set_rate(i2s_priv->i2s_clk, params_rate(params));
if (ret < 0)
dev_err(i2s_priv->dev,
"Can't set sample rate, err: %d\n", ret);
return ret;
}
static int bcm63xx_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
unsigned int slavemode;
struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(regmap_i2s, I2S_TX_CFG,
I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE,
I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE);
regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 0);
regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 0);
regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 1);
/* TX and RX block each have an independent bit to indicate
* if it is generating the clock for the I2S bus. The bus
* clocks need to be generated from either the TX or RX block,
* but not both
*/
regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
if (slavemode & I2S_RX_SLAVE_MODE_MASK)
regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
I2S_TX_SLAVE_MODE_MASK,
I2S_TX_MASTER_MODE);
else
regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
I2S_TX_SLAVE_MODE_MASK,
I2S_TX_SLAVE_MODE);
} else {
regmap_update_bits(regmap_i2s, I2S_RX_CFG,
I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
I2S_RX_CLOCK_ENABLE,
I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
I2S_RX_CLOCK_ENABLE);
regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 0);
regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 0);
regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 1);
regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
if (slavemode & I2S_TX_SLAVE_MODE_MASK)
regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
I2S_RX_SLAVE_MODE_MASK, 0);
else
regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
I2S_RX_SLAVE_MODE_MASK,
I2S_RX_SLAVE_MODE);
}
return 0;
}
static void bcm63xx_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
unsigned int enabled, slavemode;
struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(regmap_i2s, I2S_TX_CFG,
I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE, 0);
regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 1);
regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 4);
regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 4);
regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
slavemode = slavemode & I2S_TX_SLAVE_MODE_MASK;
if (!slavemode) {
regmap_read(regmap_i2s, I2S_RX_CFG, &enabled);
enabled = enabled & I2S_RX_ENABLE_MASK;
if (enabled)
regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
I2S_RX_SLAVE_MODE_MASK,
I2S_RX_MASTER_MODE);
}
regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
I2S_TX_SLAVE_MODE_MASK,
I2S_TX_SLAVE_MODE);
} else {
regmap_update_bits(regmap_i2s, I2S_RX_CFG,
I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
I2S_RX_CLOCK_ENABLE, 0);
regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 1);
regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 4);
regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 4);
regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
slavemode = slavemode & I2S_RX_SLAVE_MODE_MASK;
if (!slavemode) {
regmap_read(regmap_i2s, I2S_TX_CFG, &enabled);
enabled = enabled & I2S_TX_ENABLE_MASK;
if (enabled)
regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
I2S_TX_SLAVE_MODE_MASK,
I2S_TX_MASTER_MODE);
}
regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
I2S_RX_SLAVE_MODE_MASK, I2S_RX_SLAVE_MODE);
}
}
static const struct snd_soc_dai_ops bcm63xx_i2s_dai_ops = {
.startup = bcm63xx_i2s_startup,
.shutdown = bcm63xx_i2s_shutdown,
.hw_params = bcm63xx_i2s_hw_params,
};
static struct snd_soc_dai_driver bcm63xx_i2s_dai = {
.name = DRV_NAME,
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &bcm63xx_i2s_dai_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
};
static const struct snd_soc_component_driver bcm63xx_i2s_component = {
.name = "bcm63xx",
.legacy_dai_naming = 1,
};
static int bcm63xx_i2s_dev_probe(struct platform_device *pdev)
{
int ret = 0;
void __iomem *regs;
struct bcm_i2s_priv *i2s_priv;
struct regmap *regmap_i2s;
struct clk *i2s_clk;
i2s_priv = devm_kzalloc(&pdev->dev, sizeof(*i2s_priv), GFP_KERNEL);
if (!i2s_priv)
return -ENOMEM;
i2s_clk = devm_clk_get(&pdev->dev, "i2sclk");
if (IS_ERR(i2s_clk)) {
dev_err(&pdev->dev, "%s: cannot get a brcm clock: %ld\n",
__func__, PTR_ERR(i2s_clk));
return PTR_ERR(i2s_clk);
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
return ret;
}
regmap_i2s = devm_regmap_init_mmio(&pdev->dev,
regs, &brcm_i2s_regmap_config);
if (IS_ERR(regmap_i2s))
return PTR_ERR(regmap_i2s);
regmap_update_bits(regmap_i2s, I2S_MISC_CFG,
I2S_PAD_LVL_LOOP_DIS_MASK,
I2S_PAD_LVL_LOOP_DIS_ENABLE);
ret = devm_snd_soc_register_component(&pdev->dev,
&bcm63xx_i2s_component,
&bcm63xx_i2s_dai, 1);
if (ret) {
dev_err(&pdev->dev, "failed to register the dai\n");
return ret;
}
i2s_priv->dev = &pdev->dev;
i2s_priv->i2s_clk = i2s_clk;
i2s_priv->regmap_i2s = regmap_i2s;
dev_set_drvdata(&pdev->dev, i2s_priv);
ret = bcm63xx_soc_platform_probe(pdev, i2s_priv);
if (ret)
dev_err(&pdev->dev, "failed to register the pcm\n");
return ret;
}
static void bcm63xx_i2s_dev_remove(struct platform_device *pdev)
{
bcm63xx_soc_platform_remove(pdev);
}
#ifdef CONFIG_OF
static const struct of_device_id snd_soc_bcm_audio_match[] = {
{.compatible = "brcm,bcm63xx-i2s"},
{ }
};
#endif
static struct platform_driver bcm63xx_i2s_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(snd_soc_bcm_audio_match),
},
.probe = bcm63xx_i2s_dev_probe,
.remove_new = bcm63xx_i2s_dev_remove,
};
module_platform_driver(bcm63xx_i2s_driver);
MODULE_AUTHOR("Kevin,Li <[email protected]>");
MODULE_DESCRIPTION("Broadcom DSL XPON ASOC I2S Interface");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/bcm/bcm63xx-i2s-whistler.c |
// SPDX-License-Identifier: GPL-2.0-or-later
// linux/sound/bcm/bcm63xx-pcm-whistler.c
// BCM63xx whistler pcm interface
// Copyright (c) 2020 Broadcom Corporation
// Author: Kevin-Ke Li <[email protected]>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <linux/of_device.h>
#include <sound/soc.h>
#include "bcm63xx-i2s.h"
struct i2s_dma_desc {
unsigned char *dma_area;
dma_addr_t dma_addr;
unsigned int dma_len;
};
struct bcm63xx_runtime_data {
int dma_len;
dma_addr_t dma_addr;
dma_addr_t dma_addr_next;
};
static const struct snd_pcm_hardware bcm63xx_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S32_LE, /* support S32 only */
.period_bytes_max = 8192 - 32,
.periods_min = 1,
.periods_max = PAGE_SIZE/sizeof(struct i2s_dma_desc),
.buffer_bytes_max = 128 * 1024,
.fifo_size = 32,
};
static int bcm63xx_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct i2s_dma_desc *dma_desc;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
if (!dma_desc)
return -ENOMEM;
snd_soc_dai_set_dma_data(asoc_rtd_to_cpu(rtd, 0), substream, dma_desc);
return 0;
}
static int bcm63xx_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct i2s_dma_desc *dma_desc;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
kfree(dma_desc);
return 0;
}
static int bcm63xx_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd;
struct bcm_i2s_priv *i2s_priv;
struct regmap *regmap_i2s;
rtd = asoc_substream_to_rtd(substream);
i2s_priv = dev_get_drvdata(asoc_rtd_to_cpu(rtd, 0)->dev);
regmap_i2s = i2s_priv->regmap_i2s;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
regmap_update_bits(regmap_i2s,
I2S_TX_IRQ_EN,
I2S_TX_DESC_OFF_INTR_EN,
I2S_TX_DESC_OFF_INTR_EN);
regmap_update_bits(regmap_i2s,
I2S_TX_CFG,
I2S_TX_ENABLE_MASK,
I2S_TX_ENABLE);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
regmap_write(regmap_i2s,
I2S_TX_IRQ_EN,
0);
regmap_update_bits(regmap_i2s,
I2S_TX_CFG,
I2S_TX_ENABLE_MASK,
0);
break;
default:
ret = -EINVAL;
}
} else {
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
regmap_update_bits(regmap_i2s,
I2S_RX_IRQ_EN,
I2S_RX_DESC_OFF_INTR_EN_MSK,
I2S_RX_DESC_OFF_INTR_EN);
regmap_update_bits(regmap_i2s,
I2S_RX_CFG,
I2S_RX_ENABLE_MASK,
I2S_RX_ENABLE);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
regmap_update_bits(regmap_i2s,
I2S_RX_IRQ_EN,
I2S_RX_DESC_OFF_INTR_EN_MSK,
0);
regmap_update_bits(regmap_i2s,
I2S_RX_CFG,
I2S_RX_ENABLE_MASK,
0);
break;
default:
ret = -EINVAL;
}
}
return ret;
}
static int bcm63xx_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct i2s_dma_desc *dma_desc;
struct regmap *regmap_i2s;
struct bcm_i2s_priv *i2s_priv;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
uint32_t regaddr_desclen, regaddr_descaddr;
dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
dma_desc->dma_len = snd_pcm_lib_period_bytes(substream);
dma_desc->dma_addr = runtime->dma_addr;
dma_desc->dma_area = runtime->dma_area;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regaddr_desclen = I2S_TX_DESC_IFF_LEN;
regaddr_descaddr = I2S_TX_DESC_IFF_ADDR;
} else {
regaddr_desclen = I2S_RX_DESC_IFF_LEN;
regaddr_descaddr = I2S_RX_DESC_IFF_ADDR;
}
i2s_priv = dev_get_drvdata(asoc_rtd_to_cpu(rtd, 0)->dev);
regmap_i2s = i2s_priv->regmap_i2s;
regmap_write(regmap_i2s, regaddr_desclen, dma_desc->dma_len);
regmap_write(regmap_i2s, regaddr_descaddr, dma_desc->dma_addr);
return 0;
}
static snd_pcm_uframes_t
bcm63xx_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
snd_pcm_uframes_t x;
struct bcm63xx_runtime_data *prtd = substream->runtime->private_data;
if (!prtd->dma_addr_next)
prtd->dma_addr_next = substream->runtime->dma_addr;
x = bytes_to_frames(substream->runtime,
prtd->dma_addr_next - substream->runtime->dma_addr);
return x == substream->runtime->buffer_size ? 0 : x;
}
static int bcm63xx_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct bcm63xx_runtime_data *prtd;
runtime->hw = bcm63xx_pcm_hardware;
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
if (ret)
goto out;
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
if (ret)
goto out;
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
goto out;
ret = -ENOMEM;
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (!prtd)
goto out;
runtime->private_data = prtd;
return 0;
out:
return ret;
}
static int bcm63xx_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct bcm63xx_runtime_data *prtd = runtime->private_data;
kfree(prtd);
return 0;
}
static irqreturn_t i2s_dma_isr(int irq, void *bcm_i2s_priv)
{
unsigned int availdepth, ifflevel, offlevel, int_status, val_1, val_2;
struct bcm63xx_runtime_data *prtd;
struct snd_pcm_substream *substream;
struct snd_pcm_runtime *runtime;
struct regmap *regmap_i2s;
struct i2s_dma_desc *dma_desc;
struct snd_soc_pcm_runtime *rtd;
struct bcm_i2s_priv *i2s_priv;
i2s_priv = (struct bcm_i2s_priv *)bcm_i2s_priv;
regmap_i2s = i2s_priv->regmap_i2s;
/* rx */
regmap_read(regmap_i2s, I2S_RX_IRQ_CTL, &int_status);
if (int_status & I2S_RX_DESC_OFF_INTR_EN_MSK) {
substream = i2s_priv->capture_substream;
runtime = substream->runtime;
rtd = asoc_substream_to_rtd(substream);
prtd = runtime->private_data;
dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
offlevel = (int_status & I2S_RX_DESC_OFF_LEVEL_MASK) >>
I2S_RX_DESC_OFF_LEVEL_SHIFT;
while (offlevel) {
regmap_read(regmap_i2s, I2S_RX_DESC_OFF_ADDR, &val_1);
regmap_read(regmap_i2s, I2S_RX_DESC_OFF_LEN, &val_2);
offlevel--;
}
prtd->dma_addr_next = val_1 + val_2;
ifflevel = (int_status & I2S_RX_DESC_IFF_LEVEL_MASK) >>
I2S_RX_DESC_IFF_LEVEL_SHIFT;
availdepth = I2S_DESC_FIFO_DEPTH - ifflevel;
while (availdepth) {
dma_desc->dma_addr +=
snd_pcm_lib_period_bytes(substream);
dma_desc->dma_area +=
snd_pcm_lib_period_bytes(substream);
if (dma_desc->dma_addr - runtime->dma_addr >=
runtime->dma_bytes) {
dma_desc->dma_addr = runtime->dma_addr;
dma_desc->dma_area = runtime->dma_area;
}
prtd->dma_addr = dma_desc->dma_addr;
regmap_write(regmap_i2s, I2S_RX_DESC_IFF_LEN,
snd_pcm_lib_period_bytes(substream));
regmap_write(regmap_i2s, I2S_RX_DESC_IFF_ADDR,
dma_desc->dma_addr);
availdepth--;
}
snd_pcm_period_elapsed(substream);
/* Clear interrupt by writing 0 */
regmap_update_bits(regmap_i2s, I2S_RX_IRQ_CTL,
I2S_RX_INTR_MASK, 0);
}
/* tx */
regmap_read(regmap_i2s, I2S_TX_IRQ_CTL, &int_status);
if (int_status & I2S_TX_DESC_OFF_INTR_EN_MSK) {
substream = i2s_priv->play_substream;
runtime = substream->runtime;
rtd = asoc_substream_to_rtd(substream);
prtd = runtime->private_data;
dma_desc = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
offlevel = (int_status & I2S_TX_DESC_OFF_LEVEL_MASK) >>
I2S_TX_DESC_OFF_LEVEL_SHIFT;
while (offlevel) {
regmap_read(regmap_i2s, I2S_TX_DESC_OFF_ADDR, &val_1);
regmap_read(regmap_i2s, I2S_TX_DESC_OFF_LEN, &val_2);
prtd->dma_addr_next = val_1 + val_2;
offlevel--;
}
ifflevel = (int_status & I2S_TX_DESC_IFF_LEVEL_MASK) >>
I2S_TX_DESC_IFF_LEVEL_SHIFT;
availdepth = I2S_DESC_FIFO_DEPTH - ifflevel;
while (availdepth) {
dma_desc->dma_addr +=
snd_pcm_lib_period_bytes(substream);
dma_desc->dma_area +=
snd_pcm_lib_period_bytes(substream);
if (dma_desc->dma_addr - runtime->dma_addr >=
runtime->dma_bytes) {
dma_desc->dma_addr = runtime->dma_addr;
dma_desc->dma_area = runtime->dma_area;
}
prtd->dma_addr = dma_desc->dma_addr;
regmap_write(regmap_i2s, I2S_TX_DESC_IFF_LEN,
snd_pcm_lib_period_bytes(substream));
regmap_write(regmap_i2s, I2S_TX_DESC_IFF_ADDR,
dma_desc->dma_addr);
availdepth--;
}
snd_pcm_period_elapsed(substream);
/* Clear interrupt by writing 0 */
regmap_update_bits(regmap_i2s, I2S_TX_IRQ_CTL,
I2S_TX_INTR_MASK, 0);
}
return IRQ_HANDLED;
}
static int bcm63xx_soc_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
struct bcm_i2s_priv *i2s_priv;
int ret;
i2s_priv = dev_get_drvdata(asoc_rtd_to_cpu(rtd, 0)->dev);
of_dma_configure(pcm->card->dev, pcm->card->dev->of_node, 1);
ret = dma_coerce_mask_and_coherent(pcm->card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
i2s_priv->play_substream =
pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream)
i2s_priv->capture_substream =
pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC,
pcm->card->dev,
bcm63xx_pcm_hardware.buffer_bytes_max);
}
static const struct snd_soc_component_driver bcm63xx_soc_platform = {
.open = bcm63xx_pcm_open,
.close = bcm63xx_pcm_close,
.hw_params = bcm63xx_pcm_hw_params,
.hw_free = bcm63xx_pcm_hw_free,
.prepare = bcm63xx_pcm_prepare,
.trigger = bcm63xx_pcm_trigger,
.pointer = bcm63xx_pcm_pointer,
.pcm_construct = bcm63xx_soc_pcm_new,
};
int bcm63xx_soc_platform_probe(struct platform_device *pdev,
struct bcm_i2s_priv *i2s_priv)
{
int ret;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
ret = devm_request_irq(&pdev->dev, ret, i2s_dma_isr,
irq_get_trigger_type(ret), "i2s_dma", (void *)i2s_priv);
if (ret) {
dev_err(&pdev->dev,
"i2s_init: failed to request interrupt.ret=%d\n", ret);
return ret;
}
return devm_snd_soc_register_component(&pdev->dev,
&bcm63xx_soc_platform, NULL, 0);
}
int bcm63xx_soc_platform_remove(struct platform_device *pdev)
{
return 0;
}
MODULE_AUTHOR("Kevin,Li <[email protected]>");
MODULE_DESCRIPTION("Broadcom DSL XPON ASOC PCM Interface");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/bcm/bcm63xx-pcm-whistler.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014-2015 Broadcom Corporation
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "cygnus-ssp.h"
#define DEFAULT_VCO 1354750204
#define CAPTURE_FCI_ID_BASE 0x180
#define CYGNUS_SSP_TRISTATE_MASK 0x001fff
#define CYGNUS_PLLCLKSEL_MASK 0xf
/* Used with stream_on field to indicate which streams are active */
#define PLAYBACK_STREAM_MASK BIT(0)
#define CAPTURE_STREAM_MASK BIT(1)
#define I2S_STREAM_CFG_MASK 0xff003ff
#define I2S_CAP_STREAM_CFG_MASK 0xf0
#define SPDIF_STREAM_CFG_MASK 0x3ff
#define CH_GRP_STEREO 0x1
/* Begin register offset defines */
#define AUD_MISC_SEROUT_OE_REG_BASE 0x01c
#define AUD_MISC_SEROUT_SPDIF_OE 12
#define AUD_MISC_SEROUT_MCLK_OE 3
#define AUD_MISC_SEROUT_LRCK_OE 2
#define AUD_MISC_SEROUT_SCLK_OE 1
#define AUD_MISC_SEROUT_SDAT_OE 0
/* AUD_FMM_BF_CTRL_xxx regs */
#define BF_DST_CFG0_OFFSET 0x100
#define BF_DST_CFG1_OFFSET 0x104
#define BF_DST_CFG2_OFFSET 0x108
#define BF_DST_CTRL0_OFFSET 0x130
#define BF_DST_CTRL1_OFFSET 0x134
#define BF_DST_CTRL2_OFFSET 0x138
#define BF_SRC_CFG0_OFFSET 0x148
#define BF_SRC_CFG1_OFFSET 0x14c
#define BF_SRC_CFG2_OFFSET 0x150
#define BF_SRC_CFG3_OFFSET 0x154
#define BF_SRC_CTRL0_OFFSET 0x1c0
#define BF_SRC_CTRL1_OFFSET 0x1c4
#define BF_SRC_CTRL2_OFFSET 0x1c8
#define BF_SRC_CTRL3_OFFSET 0x1cc
#define BF_SRC_GRP0_OFFSET 0x1fc
#define BF_SRC_GRP1_OFFSET 0x200
#define BF_SRC_GRP2_OFFSET 0x204
#define BF_SRC_GRP3_OFFSET 0x208
#define BF_SRC_GRP_EN_OFFSET 0x320
#define BF_SRC_GRP_FLOWON_OFFSET 0x324
#define BF_SRC_GRP_SYNC_DIS_OFFSET 0x328
/* AUD_FMM_IOP_OUT_I2S_xxx regs */
#define OUT_I2S_0_STREAM_CFG_OFFSET 0xa00
#define OUT_I2S_0_CFG_OFFSET 0xa04
#define OUT_I2S_0_MCLK_CFG_OFFSET 0xa0c
#define OUT_I2S_1_STREAM_CFG_OFFSET 0xa40
#define OUT_I2S_1_CFG_OFFSET 0xa44
#define OUT_I2S_1_MCLK_CFG_OFFSET 0xa4c
#define OUT_I2S_2_STREAM_CFG_OFFSET 0xa80
#define OUT_I2S_2_CFG_OFFSET 0xa84
#define OUT_I2S_2_MCLK_CFG_OFFSET 0xa8c
/* AUD_FMM_IOP_OUT_SPDIF_xxx regs */
#define SPDIF_STREAM_CFG_OFFSET 0xac0
#define SPDIF_CTRL_OFFSET 0xac4
#define SPDIF_FORMAT_CFG_OFFSET 0xad8
#define SPDIF_MCLK_CFG_OFFSET 0xadc
/* AUD_FMM_IOP_PLL_0_xxx regs */
#define IOP_PLL_0_MACRO_OFFSET 0xb00
#define IOP_PLL_0_MDIV_Ch0_OFFSET 0xb14
#define IOP_PLL_0_MDIV_Ch1_OFFSET 0xb18
#define IOP_PLL_0_MDIV_Ch2_OFFSET 0xb1c
#define IOP_PLL_0_ACTIVE_MDIV_Ch0_OFFSET 0xb30
#define IOP_PLL_0_ACTIVE_MDIV_Ch1_OFFSET 0xb34
#define IOP_PLL_0_ACTIVE_MDIV_Ch2_OFFSET 0xb38
/* AUD_FMM_IOP_xxx regs */
#define IOP_PLL_0_CONTROL_OFFSET 0xb04
#define IOP_PLL_0_USER_NDIV_OFFSET 0xb08
#define IOP_PLL_0_ACTIVE_NDIV_OFFSET 0xb20
#define IOP_PLL_0_RESET_OFFSET 0xb5c
/* AUD_FMM_IOP_IN_I2S_xxx regs */
#define IN_I2S_0_STREAM_CFG_OFFSET 0x00
#define IN_I2S_0_CFG_OFFSET 0x04
#define IN_I2S_1_STREAM_CFG_OFFSET 0x40
#define IN_I2S_1_CFG_OFFSET 0x44
#define IN_I2S_2_STREAM_CFG_OFFSET 0x80
#define IN_I2S_2_CFG_OFFSET 0x84
/* AUD_FMM_IOP_MISC_xxx regs */
#define IOP_SW_INIT_LOGIC 0x1c0
/* End register offset defines */
/* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_0_REG */
#define I2S_OUT_MCLKRATE_SHIFT 16
/* AUD_FMM_IOP_OUT_I2S_x_MCLK_CFG_REG */
#define I2S_OUT_PLLCLKSEL_SHIFT 0
/* AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG */
#define I2S_OUT_STREAM_ENA 31
#define I2S_OUT_STREAM_CFG_GROUP_ID 20
#define I2S_OUT_STREAM_CFG_CHANNEL_GROUPING 24
/* AUD_FMM_IOP_IN_I2S_x_CAP */
#define I2S_IN_STREAM_CFG_CAP_ENA 31
#define I2S_IN_STREAM_CFG_0_GROUP_ID 4
/* AUD_FMM_IOP_OUT_I2S_x_I2S_CFG_REG */
#define I2S_OUT_CFGX_CLK_ENA 0
#define I2S_OUT_CFGX_DATA_ENABLE 1
#define I2S_OUT_CFGX_DATA_ALIGNMENT 6
#define I2S_OUT_CFGX_BITS_PER_SLOT 13
#define I2S_OUT_CFGX_VALID_SLOT 14
#define I2S_OUT_CFGX_FSYNC_WIDTH 18
#define I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32 26
#define I2S_OUT_CFGX_SLAVE_MODE 30
#define I2S_OUT_CFGX_TDM_MODE 31
/* AUD_FMM_BF_CTRL_SOURCECH_CFGx_REG */
#define BF_SRC_CFGX_SFIFO_ENA 0
#define BF_SRC_CFGX_BUFFER_PAIR_ENABLE 1
#define BF_SRC_CFGX_SAMPLE_CH_MODE 2
#define BF_SRC_CFGX_SFIFO_SZ_DOUBLE 5
#define BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY 10
#define BF_SRC_CFGX_BIT_RES 20
#define BF_SRC_CFGX_PROCESS_SEQ_ID_VALID 31
/* AUD_FMM_BF_CTRL_DESTCH_CFGx_REG */
#define BF_DST_CFGX_CAP_ENA 0
#define BF_DST_CFGX_BUFFER_PAIR_ENABLE 1
#define BF_DST_CFGX_DFIFO_SZ_DOUBLE 2
#define BF_DST_CFGX_NOT_PAUSE_WHEN_FULL 11
#define BF_DST_CFGX_FCI_ID 12
#define BF_DST_CFGX_CAP_MODE 24
#define BF_DST_CFGX_PROC_SEQ_ID_VALID 31
/* AUD_FMM_IOP_OUT_SPDIF_xxx */
#define SPDIF_0_OUT_DITHER_ENA 3
#define SPDIF_0_OUT_STREAM_ENA 31
/* AUD_FMM_IOP_PLL_0_USER */
#define IOP_PLL_0_USER_NDIV_FRAC 10
/* AUD_FMM_IOP_PLL_0_ACTIVE */
#define IOP_PLL_0_ACTIVE_NDIV_FRAC 10
#define INIT_SSP_REGS(num) (struct cygnus_ssp_regs){ \
.i2s_stream_cfg = OUT_I2S_ ##num## _STREAM_CFG_OFFSET, \
.i2s_cap_stream_cfg = IN_I2S_ ##num## _STREAM_CFG_OFFSET, \
.i2s_cfg = OUT_I2S_ ##num## _CFG_OFFSET, \
.i2s_cap_cfg = IN_I2S_ ##num## _CFG_OFFSET, \
.i2s_mclk_cfg = OUT_I2S_ ##num## _MCLK_CFG_OFFSET, \
.bf_destch_ctrl = BF_DST_CTRL ##num## _OFFSET, \
.bf_destch_cfg = BF_DST_CFG ##num## _OFFSET, \
.bf_sourcech_ctrl = BF_SRC_CTRL ##num## _OFFSET, \
.bf_sourcech_cfg = BF_SRC_CFG ##num## _OFFSET, \
.bf_sourcech_grp = BF_SRC_GRP ##num## _OFFSET \
}
struct pll_macro_entry {
u32 mclk;
u32 pll_ch_num;
};
/*
* PLL has 3 output channels (1x, 2x, and 4x). Below are
* the common MCLK frequencies used by audio driver
*/
static const struct pll_macro_entry pll_predef_mclk[] = {
{ 4096000, 0},
{ 8192000, 1},
{16384000, 2},
{ 5644800, 0},
{11289600, 1},
{22579200, 2},
{ 6144000, 0},
{12288000, 1},
{24576000, 2},
{12288000, 0},
{24576000, 1},
{49152000, 2},
{22579200, 0},
{45158400, 1},
{90316800, 2},
{24576000, 0},
{49152000, 1},
{98304000, 2},
};
#define CYGNUS_RATE_MIN 8000
#define CYGNUS_RATE_MAX 384000
/* List of valid frame sizes for tdm mode */
static const int ssp_valid_tdm_framesize[] = {32, 64, 128, 256, 512};
static const unsigned int cygnus_rates[] = {
8000, 11025, 16000, 22050, 32000, 44100, 48000,
88200, 96000, 176400, 192000, 352800, 384000
};
static const struct snd_pcm_hw_constraint_list cygnus_rate_constraint = {
.count = ARRAY_SIZE(cygnus_rates),
.list = cygnus_rates,
};
static struct cygnus_aio_port *cygnus_dai_get_portinfo(struct snd_soc_dai *dai)
{
struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
return &cygaud->portinfo[dai->id];
}
static int audio_ssp_init_portregs(struct cygnus_aio_port *aio)
{
u32 value, fci_id;
int status = 0;
switch (aio->port_type) {
case PORT_TDM:
value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
value &= ~I2S_STREAM_CFG_MASK;
/* Set Group ID */
writel(aio->portnum,
aio->cygaud->audio + aio->regs.bf_sourcech_grp);
/* Configure the AUD_FMM_IOP_OUT_I2S_x_STREAM_CFG reg */
value |= aio->portnum << I2S_OUT_STREAM_CFG_GROUP_ID;
value |= aio->portnum; /* FCI ID is the port num */
value |= CH_GRP_STEREO << I2S_OUT_STREAM_CFG_CHANNEL_GROUPING;
writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
/* Configure the AUD_FMM_BF_CTRL_SOURCECH_CFGX reg */
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
/* Configure the AUD_FMM_IOP_IN_I2S_x_CAP_STREAM_CFG_0 reg */
value = readl(aio->cygaud->i2s_in +
aio->regs.i2s_cap_stream_cfg);
value &= ~I2S_CAP_STREAM_CFG_MASK;
value |= aio->portnum << I2S_IN_STREAM_CFG_0_GROUP_ID;
writel(value, aio->cygaud->i2s_in +
aio->regs.i2s_cap_stream_cfg);
/* Configure the AUD_FMM_BF_CTRL_DESTCH_CFGX_REG_BASE reg */
fci_id = CAPTURE_FCI_ID_BASE + aio->portnum;
value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
value |= BIT(BF_DST_CFGX_DFIFO_SZ_DOUBLE);
value &= ~BIT(BF_DST_CFGX_NOT_PAUSE_WHEN_FULL);
value |= (fci_id << BF_DST_CFGX_FCI_ID);
value |= BIT(BF_DST_CFGX_PROC_SEQ_ID_VALID);
writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
/* Enable the transmit pin for this port */
value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
value &= ~BIT((aio->portnum * 4) + AUD_MISC_SEROUT_SDAT_OE);
writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
break;
case PORT_SPDIF:
writel(aio->portnum, aio->cygaud->audio + BF_SRC_GRP3_OFFSET);
value = readl(aio->cygaud->audio + SPDIF_CTRL_OFFSET);
value |= BIT(SPDIF_0_OUT_DITHER_ENA);
writel(value, aio->cygaud->audio + SPDIF_CTRL_OFFSET);
/* Enable and set the FCI ID for the SPDIF channel */
value = readl(aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
value &= ~SPDIF_STREAM_CFG_MASK;
value |= aio->portnum; /* FCI ID is the port num */
value |= BIT(SPDIF_0_OUT_STREAM_ENA);
writel(value, aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value &= ~BIT(BF_SRC_CFGX_NOT_PAUSE_WHEN_EMPTY);
value |= BIT(BF_SRC_CFGX_SFIFO_SZ_DOUBLE);
value |= BIT(BF_SRC_CFGX_PROCESS_SEQ_ID_VALID);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
/* Enable the spdif output pin */
value = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
value &= ~BIT(AUD_MISC_SEROUT_SPDIF_OE);
writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
break;
default:
dev_err(aio->cygaud->dev, "Port not supported\n");
status = -EINVAL;
}
return status;
}
static void audio_ssp_in_enable(struct cygnus_aio_port *aio)
{
u32 value;
value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
value |= BIT(BF_DST_CFGX_CAP_ENA);
writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
writel(0x1, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value |= BIT(I2S_OUT_CFGX_CLK_ENA);
value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
value |= BIT(I2S_IN_STREAM_CFG_CAP_ENA);
writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
aio->streams_on |= CAPTURE_STREAM_MASK;
}
static void audio_ssp_in_disable(struct cygnus_aio_port *aio)
{
u32 value;
value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
value &= ~BIT(I2S_IN_STREAM_CFG_CAP_ENA);
writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
aio->streams_on &= ~CAPTURE_STREAM_MASK;
/* If both playback and capture are off */
if (!aio->streams_on) {
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
}
writel(0x0, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
value = readl(aio->cygaud->audio + aio->regs.bf_destch_cfg);
value &= ~BIT(BF_DST_CFGX_CAP_ENA);
writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
}
static int audio_ssp_out_enable(struct cygnus_aio_port *aio)
{
u32 value;
int status = 0;
switch (aio->port_type) {
case PORT_TDM:
value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
value |= BIT(I2S_OUT_STREAM_ENA);
writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value |= BIT(I2S_OUT_CFGX_CLK_ENA);
value |= BIT(I2S_OUT_CFGX_DATA_ENABLE);
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
aio->streams_on |= PLAYBACK_STREAM_MASK;
break;
case PORT_SPDIF:
value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
value |= 0x3;
writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value |= BIT(BF_SRC_CFGX_SFIFO_ENA);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
break;
default:
dev_err(aio->cygaud->dev,
"Port not supported %d\n", aio->portnum);
status = -EINVAL;
}
return status;
}
static int audio_ssp_out_disable(struct cygnus_aio_port *aio)
{
u32 value;
int status = 0;
switch (aio->port_type) {
case PORT_TDM:
aio->streams_on &= ~PLAYBACK_STREAM_MASK;
/* If both playback and capture are off */
if (!aio->streams_on) {
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value &= ~BIT(I2S_OUT_CFGX_CLK_ENA);
value &= ~BIT(I2S_OUT_CFGX_DATA_ENABLE);
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
}
/* set group_sync_dis = 1 */
value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
value |= BIT(aio->portnum);
writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
/* set group_sync_dis = 0 */
value = readl(aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
value &= ~BIT(aio->portnum);
writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
value = readl(aio->cygaud->audio + aio->regs.i2s_stream_cfg);
value &= ~BIT(I2S_OUT_STREAM_ENA);
writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
/* IOP SW INIT on OUT_I2S_x */
value = readl(aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
value |= BIT(aio->portnum);
writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
value &= ~BIT(aio->portnum);
writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
break;
case PORT_SPDIF:
value = readl(aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
value &= ~0x3;
writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value &= ~BIT(BF_SRC_CFGX_SFIFO_ENA);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
break;
default:
dev_err(aio->cygaud->dev,
"Port not supported %d\n", aio->portnum);
status = -EINVAL;
}
return status;
}
static int pll_configure_mclk(struct cygnus_audio *cygaud, u32 mclk,
struct cygnus_aio_port *aio)
{
int i = 0, error;
bool found = false;
const struct pll_macro_entry *p_entry;
struct clk *ch_clk;
for (i = 0; i < ARRAY_SIZE(pll_predef_mclk); i++) {
p_entry = &pll_predef_mclk[i];
if (p_entry->mclk == mclk) {
found = true;
break;
}
}
if (!found) {
dev_err(cygaud->dev,
"%s No valid mclk freq (%u) found!\n", __func__, mclk);
return -EINVAL;
}
ch_clk = cygaud->audio_clk[p_entry->pll_ch_num];
if ((aio->clk_trace.cap_en) && (!aio->clk_trace.cap_clk_en)) {
error = clk_prepare_enable(ch_clk);
if (error) {
dev_err(cygaud->dev, "%s clk_prepare_enable failed %d\n",
__func__, error);
return error;
}
aio->clk_trace.cap_clk_en = true;
}
if ((aio->clk_trace.play_en) && (!aio->clk_trace.play_clk_en)) {
error = clk_prepare_enable(ch_clk);
if (error) {
dev_err(cygaud->dev, "%s clk_prepare_enable failed %d\n",
__func__, error);
return error;
}
aio->clk_trace.play_clk_en = true;
}
error = clk_set_rate(ch_clk, mclk);
if (error) {
dev_err(cygaud->dev, "%s Set MCLK rate failed: %d\n",
__func__, error);
return error;
}
return p_entry->pll_ch_num;
}
static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio)
{
u32 value;
u32 mask = 0xf;
u32 sclk;
u32 mclk_rate;
unsigned int bit_rate;
unsigned int ratio;
bit_rate = aio->bit_per_frame * aio->lrclk;
/*
* Check if the bit clock can be generated from the given MCLK.
* MCLK must be a perfect multiple of bit clock and must be one of the
* following values... (2,4,6,8,10,12,14)
*/
if ((aio->mclk % bit_rate) != 0)
return -EINVAL;
ratio = aio->mclk / bit_rate;
switch (ratio) {
case 2:
case 4:
case 6:
case 8:
case 10:
case 12:
case 14:
mclk_rate = ratio / 2;
break;
default:
dev_err(aio->cygaud->dev,
"Invalid combination of MCLK and BCLK\n");
dev_err(aio->cygaud->dev, "lrclk = %u, bits/frame = %u, mclk = %u\n",
aio->lrclk, aio->bit_per_frame, aio->mclk);
return -EINVAL;
}
/* Set sclk rate */
switch (aio->port_type) {
case PORT_TDM:
sclk = aio->bit_per_frame;
if (sclk == 512)
sclk = 0;
/* sclks_per_1fs_div = sclk cycles/32 */
sclk /= 32;
/* Set number of bitclks per frame */
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32);
value |= sclk << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32;
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
dev_dbg(aio->cygaud->dev,
"SCLKS_PER_1FS_DIV32 = 0x%x\n", value);
break;
case PORT_SPDIF:
break;
default:
dev_err(aio->cygaud->dev, "Unknown port type\n");
return -EINVAL;
}
/* Set MCLK_RATE ssp port (spdif and ssp are the same) */
value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
value &= ~(0xf << I2S_OUT_MCLKRATE_SHIFT);
value |= (mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
dev_dbg(aio->cygaud->dev, "mclk cfg reg = 0x%x\n", value);
dev_dbg(aio->cygaud->dev, "bits per frame = %u, mclk = %u Hz, lrclk = %u Hz\n",
aio->bit_per_frame, aio->mclk, aio->lrclk);
return 0;
}
static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
int rate, bitres;
u32 value;
u32 mask = 0x1f;
int ret = 0;
dev_dbg(aio->cygaud->dev, "%s port = %d\n", __func__, aio->portnum);
dev_dbg(aio->cygaud->dev, "params_channels %d\n",
params_channels(params));
dev_dbg(aio->cygaud->dev, "rate %d\n", params_rate(params));
dev_dbg(aio->cygaud->dev, "format %d\n", params_format(params));
rate = params_rate(params);
switch (aio->mode) {
case CYGNUS_SSPMODE_TDM:
if ((rate == 192000) && (params_channels(params) > 4)) {
dev_err(aio->cygaud->dev, "Cannot run %d channels at %dHz\n",
params_channels(params), rate);
return -EINVAL;
}
break;
case CYGNUS_SSPMODE_I2S:
aio->bit_per_frame = 64; /* I2S must be 64 bit per frame */
break;
default:
dev_err(aio->cygaud->dev,
"%s port running in unknown mode\n", __func__);
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value &= ~BIT(BF_SRC_CFGX_BUFFER_PAIR_ENABLE);
value &= ~BIT(BF_SRC_CFGX_SAMPLE_CH_MODE);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
bitres = 16;
break;
case SNDRV_PCM_FORMAT_S32_LE:
/* 32 bit mode is coded as 0 */
bitres = 0;
break;
default:
return -EINVAL;
}
value = readl(aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
value &= ~(mask << BF_SRC_CFGX_BIT_RES);
value |= (bitres << BF_SRC_CFGX_BIT_RES);
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
} else {
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
value = readl(aio->cygaud->audio +
aio->regs.bf_destch_cfg);
value |= BIT(BF_DST_CFGX_CAP_MODE);
writel(value, aio->cygaud->audio +
aio->regs.bf_destch_cfg);
break;
case SNDRV_PCM_FORMAT_S32_LE:
value = readl(aio->cygaud->audio +
aio->regs.bf_destch_cfg);
value &= ~BIT(BF_DST_CFGX_CAP_MODE);
writel(value, aio->cygaud->audio +
aio->regs.bf_destch_cfg);
break;
default:
return -EINVAL;
}
}
aio->lrclk = rate;
if (!aio->is_slave)
ret = cygnus_ssp_set_clocks(aio);
return ret;
}
/*
* This function sets the mclk frequency for pll clock
*/
static int cygnus_ssp_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
int sel;
u32 value;
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
dev_dbg(aio->cygaud->dev,
"%s Enter port = %d\n", __func__, aio->portnum);
sel = pll_configure_mclk(cygaud, freq, aio);
if (sel < 0) {
dev_err(aio->cygaud->dev,
"%s Setting mclk failed.\n", __func__);
return -EINVAL;
}
aio->mclk = freq;
dev_dbg(aio->cygaud->dev, "%s Setting MCLKSEL to %d\n", __func__, sel);
value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
value &= ~(0xf << I2S_OUT_PLLCLKSEL_SHIFT);
value |= (sel << I2S_OUT_PLLCLKSEL_SHIFT);
writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
return 0;
}
static int cygnus_ssp_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
snd_soc_dai_set_dma_data(dai, substream, aio);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aio->clk_trace.play_en = true;
else
aio->clk_trace.cap_en = true;
substream->runtime->hw.rate_min = CYGNUS_RATE_MIN;
substream->runtime->hw.rate_max = CYGNUS_RATE_MAX;
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cygnus_rate_constraint);
return 0;
}
static void cygnus_ssp_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aio->clk_trace.play_en = false;
else
aio->clk_trace.cap_en = false;
if (!aio->is_slave) {
u32 val;
val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
val &= CYGNUS_PLLCLKSEL_MASK;
if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) {
dev_err(aio->cygaud->dev, "Clk index %u is out of bounds\n",
val);
return;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (aio->clk_trace.play_clk_en) {
clk_disable_unprepare(aio->cygaud->
audio_clk[val]);
aio->clk_trace.play_clk_en = false;
}
} else {
if (aio->clk_trace.cap_clk_en) {
clk_disable_unprepare(aio->cygaud->
audio_clk[val]);
aio->clk_trace.cap_clk_en = false;
}
}
}
}
/*
* Bit Update Notes
* 31 Yes TDM Mode (1 = TDM, 0 = i2s)
* 30 Yes Slave Mode (1 = Slave, 0 = Master)
* 29:26 No Sclks per frame
* 25:18 Yes FS Width
* 17:14 No Valid Slots
* 13 No Bits (1 = 16 bits, 0 = 32 bits)
* 12:08 No Bits per samp
* 07 Yes Justifcation (1 = LSB, 0 = MSB)
* 06 Yes Alignment (1 = Delay 1 clk, 0 = no delay
* 05 Yes SCLK polarity (1 = Rising, 0 = Falling)
* 04 Yes LRCLK Polarity (1 = High for left, 0 = Low for left)
* 03:02 Yes Reserved - write as zero
* 01 No Data Enable
* 00 No CLK Enable
*/
#define I2S_OUT_CFG_REG_UPDATE_MASK 0x3C03FF03
/* Input cfg is same as output, but the FS width is not a valid field */
#define I2S_IN_CFG_REG_UPDATE_MASK (I2S_OUT_CFG_REG_UPDATE_MASK | 0x03FC0000)
int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai, int len)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
if ((len > 0) && (len < 256)) {
aio->fsync_width = len;
return 0;
} else {
return -EINVAL;
}
}
EXPORT_SYMBOL_GPL(cygnus_ssp_set_custom_fsync_width);
static int cygnus_ssp_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
u32 ssp_curcfg;
u32 ssp_newcfg;
u32 ssp_outcfg;
u32 ssp_incfg;
u32 val;
u32 mask;
dev_dbg(aio->cygaud->dev, "%s Enter fmt: %x\n", __func__, fmt);
if (aio->port_type == PORT_SPDIF)
return -EINVAL;
ssp_newcfg = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
ssp_newcfg |= BIT(I2S_OUT_CFGX_SLAVE_MODE);
aio->is_slave = 1;
break;
case SND_SOC_DAIFMT_BP_FP:
ssp_newcfg &= ~BIT(I2S_OUT_CFGX_SLAVE_MODE);
aio->is_slave = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT);
ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH);
aio->mode = CYGNUS_SSPMODE_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
case SND_SOC_DAIFMT_DSP_B:
ssp_newcfg |= BIT(I2S_OUT_CFGX_TDM_MODE);
/* DSP_A = data after FS, DSP_B = data during FS */
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A)
ssp_newcfg |= BIT(I2S_OUT_CFGX_DATA_ALIGNMENT);
if ((aio->fsync_width > 0) && (aio->fsync_width < 256))
ssp_newcfg |=
(aio->fsync_width << I2S_OUT_CFGX_FSYNC_WIDTH);
else
ssp_newcfg |= BIT(I2S_OUT_CFGX_FSYNC_WIDTH);
aio->mode = CYGNUS_SSPMODE_TDM;
break;
default:
return -EINVAL;
}
/*
* SSP out cfg.
* Retain bits we do not want to update, then OR in new bits
*/
ssp_curcfg = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
ssp_outcfg = (ssp_curcfg & I2S_OUT_CFG_REG_UPDATE_MASK) | ssp_newcfg;
writel(ssp_outcfg, aio->cygaud->audio + aio->regs.i2s_cfg);
/*
* SSP in cfg.
* Retain bits we do not want to update, then OR in new bits
*/
ssp_curcfg = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
ssp_incfg = (ssp_curcfg & I2S_IN_CFG_REG_UPDATE_MASK) | ssp_newcfg;
writel(ssp_incfg, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
val = readl(aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
/*
* Configure the word clk and bit clk as output or tristate
* Each port has 4 bits for controlling its pins.
* Shift the mask based upon port number.
*/
mask = BIT(AUD_MISC_SEROUT_LRCK_OE)
| BIT(AUD_MISC_SEROUT_SCLK_OE)
| BIT(AUD_MISC_SEROUT_MCLK_OE);
mask = mask << (aio->portnum * 4);
if (aio->is_slave)
/* Set bit for tri-state */
val |= mask;
else
/* Clear bit for drive */
val &= ~mask;
dev_dbg(aio->cygaud->dev, "%s Set OE bits 0x%x\n", __func__, val);
writel(val, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
return 0;
}
static int cygnus_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
dev_dbg(aio->cygaud->dev,
"%s cmd %d at port = %d\n", __func__, cmd, aio->portnum);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
audio_ssp_out_enable(aio);
else
audio_ssp_in_enable(aio);
cygaud->active_ports++;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
audio_ssp_out_disable(aio);
else
audio_ssp_in_disable(aio);
cygaud->active_ports--;
break;
default:
return -EINVAL;
}
return 0;
}
static int cygnus_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
u32 value;
int bits_per_slot = 0; /* default to 32-bits per slot */
int frame_bits;
unsigned int active_slots;
bool found = false;
int i;
if (tx_mask != rx_mask) {
dev_err(aio->cygaud->dev,
"%s tx_mask must equal rx_mask\n", __func__);
return -EINVAL;
}
active_slots = hweight32(tx_mask);
if (active_slots > 16)
return -EINVAL;
/* Slot value must be even */
if (active_slots % 2)
return -EINVAL;
/* We encode 16 slots as 0 in the reg */
if (active_slots == 16)
active_slots = 0;
/* Slot Width is either 16 or 32 */
switch (slot_width) {
case 16:
bits_per_slot = 1;
break;
case 32:
bits_per_slot = 0;
break;
default:
bits_per_slot = 0;
dev_warn(aio->cygaud->dev,
"%s Defaulting Slot Width to 32\n", __func__);
}
frame_bits = slots * slot_width;
for (i = 0; i < ARRAY_SIZE(ssp_valid_tdm_framesize); i++) {
if (ssp_valid_tdm_framesize[i] == frame_bits) {
found = true;
break;
}
}
if (!found) {
dev_err(aio->cygaud->dev,
"%s In TDM mode, frame bits INVALID (%d)\n",
__func__, frame_bits);
return -EINVAL;
}
aio->bit_per_frame = frame_bits;
dev_dbg(aio->cygaud->dev, "%s active_slots %u, bits per frame %d\n",
__func__, active_slots, frame_bits);
/* Set capture side of ssp port */
value = readl(aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
/* Set playback side of ssp port */
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value &= ~(0xf << I2S_OUT_CFGX_VALID_SLOT);
value |= (active_slots << I2S_OUT_CFGX_VALID_SLOT);
value &= ~BIT(I2S_OUT_CFGX_BITS_PER_SLOT);
value |= (bits_per_slot << I2S_OUT_CFGX_BITS_PER_SLOT);
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int __cygnus_ssp_suspend(struct snd_soc_dai *cpu_dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
if (!snd_soc_dai_active(cpu_dai))
return 0;
if (!aio->is_slave) {
u32 val;
val = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
val &= CYGNUS_PLLCLKSEL_MASK;
if (val >= ARRAY_SIZE(aio->cygaud->audio_clk)) {
dev_err(aio->cygaud->dev, "Clk index %u is out of bounds\n",
val);
return -EINVAL;
}
if (aio->clk_trace.cap_clk_en)
clk_disable_unprepare(aio->cygaud->audio_clk[val]);
if (aio->clk_trace.play_clk_en)
clk_disable_unprepare(aio->cygaud->audio_clk[val]);
aio->pll_clk_num = val;
}
return 0;
}
static int cygnus_ssp_suspend(struct snd_soc_component *component)
{
struct snd_soc_dai *dai;
int ret = 0;
for_each_component_dais(component, dai)
ret |= __cygnus_ssp_suspend(dai);
return ret;
}
static int __cygnus_ssp_resume(struct snd_soc_dai *cpu_dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(cpu_dai);
int error;
if (!snd_soc_dai_active(cpu_dai))
return 0;
if (!aio->is_slave) {
if (aio->clk_trace.cap_clk_en) {
error = clk_prepare_enable(aio->cygaud->
audio_clk[aio->pll_clk_num]);
if (error) {
dev_err(aio->cygaud->dev, "%s clk_prepare_enable failed\n",
__func__);
return -EINVAL;
}
}
if (aio->clk_trace.play_clk_en) {
error = clk_prepare_enable(aio->cygaud->
audio_clk[aio->pll_clk_num]);
if (error) {
if (aio->clk_trace.cap_clk_en)
clk_disable_unprepare(aio->cygaud->
audio_clk[aio->pll_clk_num]);
dev_err(aio->cygaud->dev, "%s clk_prepare_enable failed\n",
__func__);
return -EINVAL;
}
}
}
return 0;
}
static int cygnus_ssp_resume(struct snd_soc_component *component)
{
struct snd_soc_dai *dai;
int ret = 0;
for_each_component_dais(component, dai)
ret |= __cygnus_ssp_resume(dai);
return ret;
}
#else
#define cygnus_ssp_suspend NULL
#define cygnus_ssp_resume NULL
#endif
static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
.startup = cygnus_ssp_startup,
.shutdown = cygnus_ssp_shutdown,
.trigger = cygnus_ssp_trigger,
.hw_params = cygnus_ssp_hw_params,
.set_fmt = cygnus_ssp_set_fmt,
.set_sysclk = cygnus_ssp_set_sysclk,
.set_tdm_slot = cygnus_set_dai_tdm_slot,
};
static const struct snd_soc_dai_ops cygnus_spdif_dai_ops = {
.startup = cygnus_ssp_startup,
.shutdown = cygnus_ssp_shutdown,
.trigger = cygnus_ssp_trigger,
.hw_params = cygnus_ssp_hw_params,
.set_sysclk = cygnus_ssp_set_sysclk,
};
#define INIT_CPU_DAI(num) { \
.name = "cygnus-ssp" #num, \
.playback = { \
.channels_min = 2, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_KNOT, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.channels_min = 2, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_KNOT, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.ops = &cygnus_ssp_dai_ops, \
}
static const struct snd_soc_dai_driver cygnus_ssp_dai_info[] = {
INIT_CPU_DAI(0),
INIT_CPU_DAI(1),
INIT_CPU_DAI(2),
};
static const struct snd_soc_dai_driver cygnus_spdif_dai_info = {
.name = "cygnus-spdif",
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &cygnus_spdif_dai_ops,
};
static struct snd_soc_dai_driver cygnus_ssp_dai[CYGNUS_MAX_PORTS];
static const struct snd_soc_component_driver cygnus_ssp_component = {
.name = "cygnus-audio",
.suspend = cygnus_ssp_suspend,
.resume = cygnus_ssp_resume,
.legacy_dai_naming = 1,
};
/*
* Return < 0 if error
* Return 0 if disabled
* Return 1 if enabled and node is parsed successfully
*/
static int parse_ssp_child_node(struct platform_device *pdev,
struct device_node *dn,
struct cygnus_audio *cygaud,
struct snd_soc_dai_driver *p_dai)
{
struct cygnus_aio_port *aio;
struct cygnus_ssp_regs ssp_regs[3];
u32 rawval;
int portnum = -1;
enum cygnus_audio_port_type port_type;
if (of_property_read_u32(dn, "reg", &rawval)) {
dev_err(&pdev->dev, "Missing reg property\n");
return -EINVAL;
}
portnum = rawval;
switch (rawval) {
case 0:
ssp_regs[0] = INIT_SSP_REGS(0);
port_type = PORT_TDM;
break;
case 1:
ssp_regs[1] = INIT_SSP_REGS(1);
port_type = PORT_TDM;
break;
case 2:
ssp_regs[2] = INIT_SSP_REGS(2);
port_type = PORT_TDM;
break;
case 3:
port_type = PORT_SPDIF;
break;
default:
dev_err(&pdev->dev, "Bad value for reg %u\n", rawval);
return -EINVAL;
}
aio = &cygaud->portinfo[portnum];
aio->cygaud = cygaud;
aio->portnum = portnum;
aio->port_type = port_type;
aio->fsync_width = -1;
switch (port_type) {
case PORT_TDM:
aio->regs = ssp_regs[portnum];
*p_dai = cygnus_ssp_dai_info[portnum];
aio->mode = CYGNUS_SSPMODE_UNKNOWN;
break;
case PORT_SPDIF:
aio->regs.bf_sourcech_cfg = BF_SRC_CFG3_OFFSET;
aio->regs.bf_sourcech_ctrl = BF_SRC_CTRL3_OFFSET;
aio->regs.i2s_mclk_cfg = SPDIF_MCLK_CFG_OFFSET;
aio->regs.i2s_stream_cfg = SPDIF_STREAM_CFG_OFFSET;
*p_dai = cygnus_spdif_dai_info;
/* For the purposes of this code SPDIF can be I2S mode */
aio->mode = CYGNUS_SSPMODE_I2S;
break;
default:
dev_err(&pdev->dev, "Bad value for port_type %d\n", port_type);
return -EINVAL;
}
dev_dbg(&pdev->dev, "%s portnum = %d\n", __func__, aio->portnum);
aio->streams_on = 0;
aio->cygaud->dev = &pdev->dev;
aio->clk_trace.play_en = false;
aio->clk_trace.cap_en = false;
audio_ssp_init_portregs(aio);
return 0;
}
static int audio_clk_init(struct platform_device *pdev,
struct cygnus_audio *cygaud)
{
int i;
char clk_name[PROP_LEN_MAX];
for (i = 0; i < ARRAY_SIZE(cygaud->audio_clk); i++) {
snprintf(clk_name, PROP_LEN_MAX, "ch%d_audio", i);
cygaud->audio_clk[i] = devm_clk_get(&pdev->dev, clk_name);
if (IS_ERR(cygaud->audio_clk[i]))
return PTR_ERR(cygaud->audio_clk[i]);
}
return 0;
}
static int cygnus_ssp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *child_node;
struct cygnus_audio *cygaud;
int err;
int node_count;
int active_port_count;
cygaud = devm_kzalloc(dev, sizeof(struct cygnus_audio), GFP_KERNEL);
if (!cygaud)
return -ENOMEM;
dev_set_drvdata(dev, cygaud);
cygaud->audio = devm_platform_ioremap_resource_byname(pdev, "aud");
if (IS_ERR(cygaud->audio))
return PTR_ERR(cygaud->audio);
cygaud->i2s_in = devm_platform_ioremap_resource_byname(pdev, "i2s_in");
if (IS_ERR(cygaud->i2s_in))
return PTR_ERR(cygaud->i2s_in);
/* Tri-state all controlable pins until we know that we need them */
writel(CYGNUS_SSP_TRISTATE_MASK,
cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
node_count = of_get_child_count(pdev->dev.of_node);
if ((node_count < 1) || (node_count > CYGNUS_MAX_PORTS)) {
dev_err(dev, "child nodes is %d. Must be between 1 and %d\n",
node_count, CYGNUS_MAX_PORTS);
return -EINVAL;
}
active_port_count = 0;
for_each_available_child_of_node(pdev->dev.of_node, child_node) {
err = parse_ssp_child_node(pdev, child_node, cygaud,
&cygnus_ssp_dai[active_port_count]);
/* negative is err, 0 is active and good, 1 is disabled */
if (err < 0) {
of_node_put(child_node);
return err;
}
else if (!err) {
dev_dbg(dev, "Activating DAI: %s\n",
cygnus_ssp_dai[active_port_count].name);
active_port_count++;
}
}
cygaud->dev = dev;
cygaud->active_ports = 0;
dev_dbg(dev, "Registering %d DAIs\n", active_port_count);
err = devm_snd_soc_register_component(dev, &cygnus_ssp_component,
cygnus_ssp_dai, active_port_count);
if (err) {
dev_err(dev, "snd_soc_register_dai failed\n");
return err;
}
cygaud->irq_num = platform_get_irq(pdev, 0);
if (cygaud->irq_num <= 0)
return cygaud->irq_num;
err = audio_clk_init(pdev, cygaud);
if (err) {
dev_err(dev, "audio clock initialization failed\n");
return err;
}
err = cygnus_soc_platform_register(dev, cygaud);
if (err) {
dev_err(dev, "platform reg error %d\n", err);
return err;
}
return 0;
}
static void cygnus_ssp_remove(struct platform_device *pdev)
{
cygnus_soc_platform_unregister(&pdev->dev);
}
static const struct of_device_id cygnus_ssp_of_match[] = {
{ .compatible = "brcm,cygnus-audio" },
{},
};
MODULE_DEVICE_TABLE(of, cygnus_ssp_of_match);
static struct platform_driver cygnus_ssp_driver = {
.probe = cygnus_ssp_probe,
.remove_new = cygnus_ssp_remove,
.driver = {
.name = "cygnus-ssp",
.of_match_table = cygnus_ssp_of_match,
},
};
module_platform_driver(cygnus_ssp_driver);
MODULE_ALIAS("platform:cygnus-ssp");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Cygnus ASoC SSP Interface");
| linux-master | sound/soc/bcm/cygnus-ssp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
*
* Author: Florian Meier <[email protected]>
* Copyright 2013
*
* Based on
* Raspberry Pi PCM I2S ALSA Driver
* Copyright (c) by Phil Poole 2013
*
* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
* Vladimir Barinov, <[email protected]>
* Copyright (C) 2007 MontaVista Software, Inc., <[email protected]>
*
* OMAP ALSA SoC DAI driver using McBSP port
* Copyright (C) 2008 Nokia Corporation
* Contact: Jarkko Nikula <[email protected]>
* Peter Ujfalusi <[email protected]>
*
* Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
* Author: Timur Tabi <[email protected]>
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
/* I2S registers */
#define BCM2835_I2S_CS_A_REG 0x00
#define BCM2835_I2S_FIFO_A_REG 0x04
#define BCM2835_I2S_MODE_A_REG 0x08
#define BCM2835_I2S_RXC_A_REG 0x0c
#define BCM2835_I2S_TXC_A_REG 0x10
#define BCM2835_I2S_DREQ_A_REG 0x14
#define BCM2835_I2S_INTEN_A_REG 0x18
#define BCM2835_I2S_INTSTC_A_REG 0x1c
#define BCM2835_I2S_GRAY_REG 0x20
/* I2S register settings */
#define BCM2835_I2S_STBY BIT(25)
#define BCM2835_I2S_SYNC BIT(24)
#define BCM2835_I2S_RXSEX BIT(23)
#define BCM2835_I2S_RXF BIT(22)
#define BCM2835_I2S_TXE BIT(21)
#define BCM2835_I2S_RXD BIT(20)
#define BCM2835_I2S_TXD BIT(19)
#define BCM2835_I2S_RXR BIT(18)
#define BCM2835_I2S_TXW BIT(17)
#define BCM2835_I2S_CS_RXERR BIT(16)
#define BCM2835_I2S_CS_TXERR BIT(15)
#define BCM2835_I2S_RXSYNC BIT(14)
#define BCM2835_I2S_TXSYNC BIT(13)
#define BCM2835_I2S_DMAEN BIT(9)
#define BCM2835_I2S_RXTHR(v) ((v) << 7)
#define BCM2835_I2S_TXTHR(v) ((v) << 5)
#define BCM2835_I2S_RXCLR BIT(4)
#define BCM2835_I2S_TXCLR BIT(3)
#define BCM2835_I2S_TXON BIT(2)
#define BCM2835_I2S_RXON BIT(1)
#define BCM2835_I2S_EN (1)
#define BCM2835_I2S_CLKDIS BIT(28)
#define BCM2835_I2S_PDMN BIT(27)
#define BCM2835_I2S_PDME BIT(26)
#define BCM2835_I2S_FRXP BIT(25)
#define BCM2835_I2S_FTXP BIT(24)
#define BCM2835_I2S_CLKM BIT(23)
#define BCM2835_I2S_CLKI BIT(22)
#define BCM2835_I2S_FSM BIT(21)
#define BCM2835_I2S_FSI BIT(20)
#define BCM2835_I2S_FLEN(v) ((v) << 10)
#define BCM2835_I2S_FSLEN(v) (v)
#define BCM2835_I2S_CHWEX BIT(15)
#define BCM2835_I2S_CHEN BIT(14)
#define BCM2835_I2S_CHPOS(v) ((v) << 4)
#define BCM2835_I2S_CHWID(v) (v)
#define BCM2835_I2S_CH1(v) ((v) << 16)
#define BCM2835_I2S_CH2(v) (v)
#define BCM2835_I2S_CH1_POS(v) BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
#define BCM2835_I2S_CH2_POS(v) BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
#define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
#define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
#define BCM2835_I2S_TX(v) ((v) << 8)
#define BCM2835_I2S_RX(v) (v)
#define BCM2835_I2S_INT_RXERR BIT(3)
#define BCM2835_I2S_INT_TXERR BIT(2)
#define BCM2835_I2S_INT_RXR BIT(1)
#define BCM2835_I2S_INT_TXW BIT(0)
/* Frame length register is 10 bit, maximum length 1024 */
#define BCM2835_I2S_MAX_FRAME_LENGTH 1024
/* General device struct */
struct bcm2835_i2s_dev {
struct device *dev;
struct snd_dmaengine_dai_dma_data dma_data[2];
unsigned int fmt;
unsigned int tdm_slots;
unsigned int rx_mask;
unsigned int tx_mask;
unsigned int slot_width;
unsigned int frame_length;
struct regmap *i2s_regmap;
struct clk *clk;
bool clk_prepared;
int clk_rate;
};
static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
{
unsigned int provider = dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
if (dev->clk_prepared)
return;
switch (provider) {
case SND_SOC_DAIFMT_BP_FP:
case SND_SOC_DAIFMT_BP_FC:
clk_prepare_enable(dev->clk);
dev->clk_prepared = true;
break;
default:
break;
}
}
static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
{
if (dev->clk_prepared)
clk_disable_unprepare(dev->clk);
dev->clk_prepared = false;
}
static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
bool tx, bool rx)
{
int timeout = 1000;
uint32_t syncval;
uint32_t csreg;
uint32_t i2s_active_state;
bool clk_was_prepared;
uint32_t off;
uint32_t clr;
off = tx ? BCM2835_I2S_TXON : 0;
off |= rx ? BCM2835_I2S_RXON : 0;
clr = tx ? BCM2835_I2S_TXCLR : 0;
clr |= rx ? BCM2835_I2S_RXCLR : 0;
/* Backup the current state */
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
/* Start clock if not running */
clk_was_prepared = dev->clk_prepared;
if (!clk_was_prepared)
bcm2835_i2s_start_clock(dev);
/* Stop I2S module */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
/*
* Clear the FIFOs
* Requires at least 2 PCM clock cycles to take effect
*/
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
/* Wait for 2 PCM clock cycles */
/*
* Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
* FIXME: This does not seem to work for slave mode!
*/
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
syncval &= BCM2835_I2S_SYNC;
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_SYNC, ~syncval);
/* Wait for the SYNC flag changing it's state */
while (--timeout) {
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
if ((csreg & BCM2835_I2S_SYNC) != syncval)
break;
}
if (!timeout)
dev_err(dev->dev, "I2S SYNC error!\n");
/* Stop clock if it was not running before */
if (!clk_was_prepared)
bcm2835_i2s_stop_clock(dev);
/* Restore I2S state */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
}
static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
dev->fmt = fmt;
return 0;
}
static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
if (!ratio) {
dev->tdm_slots = 0;
return 0;
}
if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
return -EINVAL;
dev->tdm_slots = 2;
dev->rx_mask = 0x03;
dev->tx_mask = 0x03;
dev->slot_width = ratio / 2;
dev->frame_length = ratio;
return 0;
}
static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int width)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
if (slots) {
if (slots < 0 || width < 0)
return -EINVAL;
/* Limit masks to available slots */
rx_mask &= GENMASK(slots - 1, 0);
tx_mask &= GENMASK(slots - 1, 0);
/*
* The driver is limited to 2-channel setups.
* Check that exactly 2 bits are set in the masks.
*/
if (hweight_long((unsigned long) rx_mask) != 2
|| hweight_long((unsigned long) tx_mask) != 2)
return -EINVAL;
if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
return -EINVAL;
}
dev->tdm_slots = slots;
dev->rx_mask = rx_mask;
dev->tx_mask = tx_mask;
dev->slot_width = width;
dev->frame_length = slots * width;
return 0;
}
/*
* Convert logical slot number into physical slot number.
*
* If odd_offset is 0 sequential number is identical to logical number.
* This is used for DSP modes with slot numbering 0 1 2 3 ...
*
* Otherwise odd_offset defines the physical offset for odd numbered
* slots. This is used for I2S and left/right justified modes to
* translate from logical slot numbers 0 1 2 3 ... into physical slot
* numbers 0 2 ... 3 4 ...
*/
static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
{
if (!odd_offset)
return slot;
if (slot & 1)
return (slot >> 1) + odd_offset;
return slot >> 1;
}
/*
* Calculate channel position from mask and slot width.
*
* Mask must contain exactly 2 set bits.
* Lowest set bit is channel 1 position, highest set bit channel 2.
* The constant offset is added to both channel positions.
*
* If odd_offset is > 0 slot positions are translated to
* I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
* logical slot numbers starting at physical slot odd_offset.
*/
static void bcm2835_i2s_calc_channel_pos(
unsigned int *ch1_pos, unsigned int *ch2_pos,
unsigned int mask, unsigned int width,
unsigned int bit_offset, unsigned int odd_offset)
{
*ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
* width + bit_offset;
*ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
* width + bit_offset;
}
static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
unsigned int data_length, data_delay, framesync_length;
unsigned int slots, slot_width, odd_slot_offset;
int frame_length, bclk_rate;
unsigned int rx_mask, tx_mask;
unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
unsigned int mode, format;
bool bit_clock_provider = false;
bool frame_sync_provider = false;
bool frame_start_falling_edge = false;
uint32_t csreg;
int ret = 0;
/*
* If a stream is already enabled,
* the registers are already set properly.
*/
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
return 0;
data_length = params_width(params);
data_delay = 0;
odd_slot_offset = 0;
mode = 0;
if (dev->tdm_slots) {
slots = dev->tdm_slots;
slot_width = dev->slot_width;
frame_length = dev->frame_length;
rx_mask = dev->rx_mask;
tx_mask = dev->tx_mask;
bclk_rate = dev->frame_length * params_rate(params);
} else {
slots = 2;
slot_width = params_width(params);
rx_mask = 0x03;
tx_mask = 0x03;
frame_length = snd_soc_params_to_frame_size(params);
if (frame_length < 0)
return frame_length;
bclk_rate = snd_soc_params_to_bclk(params);
if (bclk_rate < 0)
return bclk_rate;
}
/* Check if data fits into slots */
if (data_length > slot_width)
return -EINVAL;
/* Check if CPU is bit clock provider */
switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
case SND_SOC_DAIFMT_BP_FC:
bit_clock_provider = true;
break;
case SND_SOC_DAIFMT_BC_FP:
case SND_SOC_DAIFMT_BC_FC:
bit_clock_provider = false;
break;
default:
return -EINVAL;
}
/* Check if CPU is frame sync provider */
switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
case SND_SOC_DAIFMT_BC_FP:
frame_sync_provider = true;
break;
case SND_SOC_DAIFMT_BP_FC:
case SND_SOC_DAIFMT_BC_FC:
frame_sync_provider = false;
break;
default:
return -EINVAL;
}
/* Clock should only be set up here if CPU is clock master */
if (bit_clock_provider &&
(!dev->clk_prepared || dev->clk_rate != bclk_rate)) {
if (dev->clk_prepared)
bcm2835_i2s_stop_clock(dev);
if (dev->clk_rate != bclk_rate) {
ret = clk_set_rate(dev->clk, bclk_rate);
if (ret)
return ret;
dev->clk_rate = bclk_rate;
}
bcm2835_i2s_start_clock(dev);
}
/* Setup the frame format */
format = BCM2835_I2S_CHEN;
if (data_length >= 24)
format |= BCM2835_I2S_CHWEX;
format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
/* CH2 format is the same as for CH1 */
format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* I2S mode needs an even number of slots */
if (slots & 1)
return -EINVAL;
/*
* Use I2S-style logical slot numbering: even slots
* are in first half of frame, odd slots in second half.
*/
odd_slot_offset = slots >> 1;
/* MSB starts one cycle after frame start */
data_delay = 1;
/* Setup frame sync signal for 50% duty cycle */
framesync_length = frame_length / 2;
frame_start_falling_edge = true;
break;
case SND_SOC_DAIFMT_LEFT_J:
if (slots & 1)
return -EINVAL;
odd_slot_offset = slots >> 1;
data_delay = 0;
framesync_length = frame_length / 2;
frame_start_falling_edge = false;
break;
case SND_SOC_DAIFMT_RIGHT_J:
if (slots & 1)
return -EINVAL;
/* Odd frame lengths aren't supported */
if (frame_length & 1)
return -EINVAL;
odd_slot_offset = slots >> 1;
data_delay = slot_width - data_length;
framesync_length = frame_length / 2;
frame_start_falling_edge = false;
break;
case SND_SOC_DAIFMT_DSP_A:
data_delay = 1;
framesync_length = 1;
frame_start_falling_edge = false;
break;
case SND_SOC_DAIFMT_DSP_B:
data_delay = 0;
framesync_length = 1;
frame_start_falling_edge = false;
break;
default:
return -EINVAL;
}
bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
rx_mask, slot_width, data_delay, odd_slot_offset);
bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
tx_mask, slot_width, data_delay, odd_slot_offset);
/*
* Transmitting data immediately after frame start, eg
* in left-justified or DSP mode A, only works stable
* if bcm2835 is the frame clock provider.
*/
if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_provider)
dev_warn(dev->dev,
"Unstable consumer config detected, L/R may be swapped");
/*
* Set format for both streams.
* We cannot set another frame length
* (and therefore word length) anyway,
* so the format will be the same.
*/
regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG,
format
| BCM2835_I2S_CH1_POS(rx_ch1_pos)
| BCM2835_I2S_CH2_POS(rx_ch2_pos));
regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG,
format
| BCM2835_I2S_CH1_POS(tx_ch1_pos)
| BCM2835_I2S_CH2_POS(tx_ch2_pos));
/* Setup the I2S mode */
if (data_length <= 16) {
/*
* Use frame packed mode (2 channels per 32 bit word)
* We cannot set another frame length in the second stream
* (and therefore word length) anyway,
* so the format will be the same.
*/
mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
}
mode |= BCM2835_I2S_FLEN(frame_length - 1);
mode |= BCM2835_I2S_FSLEN(framesync_length);
/* CLKM selects bcm2835 clock slave mode */
if (!bit_clock_provider)
mode |= BCM2835_I2S_CLKM;
/* FSM selects bcm2835 frame sync slave mode */
if (!frame_sync_provider)
mode |= BCM2835_I2S_FSM;
/* CLKI selects normal clocking mode, sampling on rising edge */
switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
case SND_SOC_DAIFMT_NB_IF:
mode |= BCM2835_I2S_CLKI;
break;
case SND_SOC_DAIFMT_IB_NF:
case SND_SOC_DAIFMT_IB_IF:
break;
default:
return -EINVAL;
}
/* FSI selects frame start on falling edge */
switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
case SND_SOC_DAIFMT_IB_NF:
if (frame_start_falling_edge)
mode |= BCM2835_I2S_FSI;
break;
case SND_SOC_DAIFMT_NB_IF:
case SND_SOC_DAIFMT_IB_IF:
if (!frame_start_falling_edge)
mode |= BCM2835_I2S_FSI;
break;
default:
return -EINVAL;
}
regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);
/* Setup the DMA parameters */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_RXTHR(1)
| BCM2835_I2S_TXTHR(1)
| BCM2835_I2S_DMAEN, 0xffffffff);
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
BCM2835_I2S_TX_PANIC(0x10)
| BCM2835_I2S_RX_PANIC(0x30)
| BCM2835_I2S_TX(0x30)
| BCM2835_I2S_RX(0x20), 0xffffffff);
/* Clear FIFOs */
bcm2835_i2s_clear_fifos(dev, true, true);
dev_dbg(dev->dev,
"slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
slots, slot_width, rx_mask, tx_mask);
dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
frame_length, framesync_length, data_length);
dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
params_rate(params), bclk_rate);
dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n",
!!(mode & BCM2835_I2S_CLKM),
!!(mode & BCM2835_I2S_CLKI),
!!(mode & BCM2835_I2S_FSM),
!!(mode & BCM2835_I2S_FSI),
(mode & BCM2835_I2S_FSI) ? "falling" : "rising");
return ret;
}
static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
uint32_t cs_reg;
/*
* Clear both FIFOs if the one that should be started
* is not empty at the moment. This should only happen
* after overrun. Otherwise, hw_params would have cleared
* the FIFO.
*/
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
&& !(cs_reg & BCM2835_I2S_TXE))
bcm2835_i2s_clear_fifos(dev, true, false);
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
&& (cs_reg & BCM2835_I2S_RXD))
bcm2835_i2s_clear_fifos(dev, false, true);
return 0;
}
static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
uint32_t mask;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mask = BCM2835_I2S_RXON;
else
mask = BCM2835_I2S_TXON;
regmap_update_bits(dev->i2s_regmap,
BCM2835_I2S_CS_A_REG, mask, 0);
/* Stop also the clock when not SND_SOC_DAIFMT_CONT */
if (!snd_soc_dai_active(dai) && !(dev->fmt & SND_SOC_DAIFMT_CONT))
bcm2835_i2s_stop_clock(dev);
}
static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
uint32_t mask;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
bcm2835_i2s_start_clock(dev);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mask = BCM2835_I2S_RXON;
else
mask = BCM2835_I2S_TXON;
regmap_update_bits(dev->i2s_regmap,
BCM2835_I2S_CS_A_REG, mask, mask);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
bcm2835_i2s_stop(dev, substream, dai);
break;
default:
return -EINVAL;
}
return 0;
}
static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
if (snd_soc_dai_active(dai))
return 0;
/* Should this still be running stop it */
bcm2835_i2s_stop_clock(dev);
/* Enable PCM block */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_EN, BCM2835_I2S_EN);
/*
* Disable STBY.
* Requires at least 4 PCM clock cycles to take effect.
*/
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_STBY, BCM2835_I2S_STBY);
return 0;
}
static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
bcm2835_i2s_stop(dev, substream, dai);
/* If both streams are stopped, disable module and clock */
if (snd_soc_dai_active(dai))
return;
/* Disable the module */
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
BCM2835_I2S_EN, 0);
/*
* Stopping clock is necessary, because stop does
* not stop the clock when SND_SOC_DAIFMT_CONT
*/
bcm2835_i2s_stop_clock(dev);
}
static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai,
&dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
&dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
return 0;
}
static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
.probe = bcm2835_i2s_dai_probe,
.startup = bcm2835_i2s_startup,
.shutdown = bcm2835_i2s_shutdown,
.prepare = bcm2835_i2s_prepare,
.trigger = bcm2835_i2s_trigger,
.hw_params = bcm2835_i2s_hw_params,
.set_fmt = bcm2835_i2s_set_dai_fmt,
.set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
.set_tdm_slot = bcm2835_i2s_set_dai_tdm_slot,
};
static struct snd_soc_dai_driver bcm2835_i2s_dai = {
.name = "bcm2835-i2s",
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 384000,
.formats = SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE
},
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 384000,
.formats = SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE
},
.ops = &bcm2835_i2s_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
};
static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case BCM2835_I2S_CS_A_REG:
case BCM2835_I2S_FIFO_A_REG:
case BCM2835_I2S_INTSTC_A_REG:
case BCM2835_I2S_GRAY_REG:
return true;
default:
return false;
}
}
static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case BCM2835_I2S_FIFO_A_REG:
return true;
default:
return false;
}
}
static const struct regmap_config bcm2835_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = BCM2835_I2S_GRAY_REG,
.precious_reg = bcm2835_i2s_precious_reg,
.volatile_reg = bcm2835_i2s_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct snd_soc_component_driver bcm2835_i2s_component = {
.name = "bcm2835-i2s-comp",
.legacy_dai_naming = 1,
};
static int bcm2835_i2s_probe(struct platform_device *pdev)
{
struct bcm2835_i2s_dev *dev;
int ret;
void __iomem *base;
const __be32 *addr;
dma_addr_t dma_base;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
GFP_KERNEL);
if (!dev)
return -ENOMEM;
/* get the clock */
dev->clk_prepared = false;
dev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(dev->clk),
"could not get clk\n");
/* Request ioarea */
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
&bcm2835_regmap_config);
if (IS_ERR(dev->i2s_regmap))
return PTR_ERR(dev->i2s_regmap);
/* Set the DMA address - we have to parse DT ourselves */
addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
if (!addr) {
dev_err(&pdev->dev, "could not get DMA-register address\n");
return -EINVAL;
}
dma_base = be32_to_cpup(addr);
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
dma_base + BCM2835_I2S_FIFO_A_REG;
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
dma_base + BCM2835_I2S_FIFO_A_REG;
/* Set the bus width */
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
DMA_SLAVE_BUSWIDTH_4_BYTES;
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
DMA_SLAVE_BUSWIDTH_4_BYTES;
/* Set burst */
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
/*
* Set the PACK flag to enable S16_LE support (2 S16_LE values
* packed into 32-bit transfers).
*/
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags =
SND_DMAENGINE_PCM_DAI_FLAG_PACK;
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
SND_DMAENGINE_PCM_DAI_FLAG_PACK;
/* Store the pdev */
dev->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, dev);
ret = devm_snd_soc_register_component(&pdev->dev,
&bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
return ret;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id bcm2835_i2s_of_match[] = {
{ .compatible = "brcm,bcm2835-i2s", },
{},
};
MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
static struct platform_driver bcm2835_i2s_driver = {
.probe = bcm2835_i2s_probe,
.driver = {
.name = "bcm2835-i2s",
.of_match_table = bcm2835_i2s_of_match,
},
};
module_platform_driver(bcm2835_i2s_driver);
MODULE_ALIAS("platform:bcm2835-i2s");
MODULE_DESCRIPTION("BCM2835 I2S interface");
MODULE_AUTHOR("Florian Meier <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/bcm/bcm2835-i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014-2015 Broadcom Corporation
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "cygnus-ssp.h"
/* Register offset needed for ASoC PCM module */
#define INTH_R5F_STATUS_OFFSET 0x040
#define INTH_R5F_CLEAR_OFFSET 0x048
#define INTH_R5F_MASK_SET_OFFSET 0x050
#define INTH_R5F_MASK_CLEAR_OFFSET 0x054
#define BF_REARM_FREE_MARK_OFFSET 0x344
#define BF_REARM_FULL_MARK_OFFSET 0x348
/* Ring Buffer Ctrl Regs --- Start */
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_RDADDR_REG_BASE */
#define SRC_RBUF_0_RDADDR_OFFSET 0x500
#define SRC_RBUF_1_RDADDR_OFFSET 0x518
#define SRC_RBUF_2_RDADDR_OFFSET 0x530
#define SRC_RBUF_3_RDADDR_OFFSET 0x548
#define SRC_RBUF_4_RDADDR_OFFSET 0x560
#define SRC_RBUF_5_RDADDR_OFFSET 0x578
#define SRC_RBUF_6_RDADDR_OFFSET 0x590
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_WRADDR_REG_BASE */
#define SRC_RBUF_0_WRADDR_OFFSET 0x504
#define SRC_RBUF_1_WRADDR_OFFSET 0x51c
#define SRC_RBUF_2_WRADDR_OFFSET 0x534
#define SRC_RBUF_3_WRADDR_OFFSET 0x54c
#define SRC_RBUF_4_WRADDR_OFFSET 0x564
#define SRC_RBUF_5_WRADDR_OFFSET 0x57c
#define SRC_RBUF_6_WRADDR_OFFSET 0x594
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_BASEADDR_REG_BASE */
#define SRC_RBUF_0_BASEADDR_OFFSET 0x508
#define SRC_RBUF_1_BASEADDR_OFFSET 0x520
#define SRC_RBUF_2_BASEADDR_OFFSET 0x538
#define SRC_RBUF_3_BASEADDR_OFFSET 0x550
#define SRC_RBUF_4_BASEADDR_OFFSET 0x568
#define SRC_RBUF_5_BASEADDR_OFFSET 0x580
#define SRC_RBUF_6_BASEADDR_OFFSET 0x598
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_ENDADDR_REG_BASE */
#define SRC_RBUF_0_ENDADDR_OFFSET 0x50c
#define SRC_RBUF_1_ENDADDR_OFFSET 0x524
#define SRC_RBUF_2_ENDADDR_OFFSET 0x53c
#define SRC_RBUF_3_ENDADDR_OFFSET 0x554
#define SRC_RBUF_4_ENDADDR_OFFSET 0x56c
#define SRC_RBUF_5_ENDADDR_OFFSET 0x584
#define SRC_RBUF_6_ENDADDR_OFFSET 0x59c
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_FREE_MARK_REG_BASE */
#define SRC_RBUF_0_FREE_MARK_OFFSET 0x510
#define SRC_RBUF_1_FREE_MARK_OFFSET 0x528
#define SRC_RBUF_2_FREE_MARK_OFFSET 0x540
#define SRC_RBUF_3_FREE_MARK_OFFSET 0x558
#define SRC_RBUF_4_FREE_MARK_OFFSET 0x570
#define SRC_RBUF_5_FREE_MARK_OFFSET 0x588
#define SRC_RBUF_6_FREE_MARK_OFFSET 0x5a0
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_RDADDR_REG_BASE */
#define DST_RBUF_0_RDADDR_OFFSET 0x5c0
#define DST_RBUF_1_RDADDR_OFFSET 0x5d8
#define DST_RBUF_2_RDADDR_OFFSET 0x5f0
#define DST_RBUF_3_RDADDR_OFFSET 0x608
#define DST_RBUF_4_RDADDR_OFFSET 0x620
#define DST_RBUF_5_RDADDR_OFFSET 0x638
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_WRADDR_REG_BASE */
#define DST_RBUF_0_WRADDR_OFFSET 0x5c4
#define DST_RBUF_1_WRADDR_OFFSET 0x5dc
#define DST_RBUF_2_WRADDR_OFFSET 0x5f4
#define DST_RBUF_3_WRADDR_OFFSET 0x60c
#define DST_RBUF_4_WRADDR_OFFSET 0x624
#define DST_RBUF_5_WRADDR_OFFSET 0x63c
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_BASEADDR_REG_BASE */
#define DST_RBUF_0_BASEADDR_OFFSET 0x5c8
#define DST_RBUF_1_BASEADDR_OFFSET 0x5e0
#define DST_RBUF_2_BASEADDR_OFFSET 0x5f8
#define DST_RBUF_3_BASEADDR_OFFSET 0x610
#define DST_RBUF_4_BASEADDR_OFFSET 0x628
#define DST_RBUF_5_BASEADDR_OFFSET 0x640
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_ENDADDR_REG_BASE */
#define DST_RBUF_0_ENDADDR_OFFSET 0x5cc
#define DST_RBUF_1_ENDADDR_OFFSET 0x5e4
#define DST_RBUF_2_ENDADDR_OFFSET 0x5fc
#define DST_RBUF_3_ENDADDR_OFFSET 0x614
#define DST_RBUF_4_ENDADDR_OFFSET 0x62c
#define DST_RBUF_5_ENDADDR_OFFSET 0x644
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_FULL_MARK_REG_BASE */
#define DST_RBUF_0_FULL_MARK_OFFSET 0x5d0
#define DST_RBUF_1_FULL_MARK_OFFSET 0x5e8
#define DST_RBUF_2_FULL_MARK_OFFSET 0x600
#define DST_RBUF_3_FULL_MARK_OFFSET 0x618
#define DST_RBUF_4_FULL_MARK_OFFSET 0x630
#define DST_RBUF_5_FULL_MARK_OFFSET 0x648
/* Ring Buffer Ctrl Regs --- End */
/* Error Status Regs --- Start */
/* AUD_FMM_BF_ESR_ESRX_STATUS_REG_BASE */
#define ESR0_STATUS_OFFSET 0x900
#define ESR1_STATUS_OFFSET 0x918
#define ESR2_STATUS_OFFSET 0x930
#define ESR3_STATUS_OFFSET 0x948
#define ESR4_STATUS_OFFSET 0x960
/* AUD_FMM_BF_ESR_ESRX_STATUS_CLEAR_REG_BASE */
#define ESR0_STATUS_CLR_OFFSET 0x908
#define ESR1_STATUS_CLR_OFFSET 0x920
#define ESR2_STATUS_CLR_OFFSET 0x938
#define ESR3_STATUS_CLR_OFFSET 0x950
#define ESR4_STATUS_CLR_OFFSET 0x968
/* AUD_FMM_BF_ESR_ESRX_MASK_REG_BASE */
#define ESR0_MASK_STATUS_OFFSET 0x90c
#define ESR1_MASK_STATUS_OFFSET 0x924
#define ESR2_MASK_STATUS_OFFSET 0x93c
#define ESR3_MASK_STATUS_OFFSET 0x954
#define ESR4_MASK_STATUS_OFFSET 0x96c
/* AUD_FMM_BF_ESR_ESRX_MASK_SET_REG_BASE */
#define ESR0_MASK_SET_OFFSET 0x910
#define ESR1_MASK_SET_OFFSET 0x928
#define ESR2_MASK_SET_OFFSET 0x940
#define ESR3_MASK_SET_OFFSET 0x958
#define ESR4_MASK_SET_OFFSET 0x970
/* AUD_FMM_BF_ESR_ESRX_MASK_CLEAR_REG_BASE */
#define ESR0_MASK_CLR_OFFSET 0x914
#define ESR1_MASK_CLR_OFFSET 0x92c
#define ESR2_MASK_CLR_OFFSET 0x944
#define ESR3_MASK_CLR_OFFSET 0x95c
#define ESR4_MASK_CLR_OFFSET 0x974
/* Error Status Regs --- End */
#define R5F_ESR0_SHIFT 0 /* esr0 = fifo underflow */
#define R5F_ESR1_SHIFT 1 /* esr1 = ringbuf underflow */
#define R5F_ESR2_SHIFT 2 /* esr2 = ringbuf overflow */
#define R5F_ESR3_SHIFT 3 /* esr3 = freemark */
#define R5F_ESR4_SHIFT 4 /* esr4 = fullmark */
/* Mask for R5F register. Set all relevant interrupt for playback handler */
#define ANY_PLAYBACK_IRQ (BIT(R5F_ESR0_SHIFT) | \
BIT(R5F_ESR1_SHIFT) | \
BIT(R5F_ESR3_SHIFT))
/* Mask for R5F register. Set all relevant interrupt for capture handler */
#define ANY_CAPTURE_IRQ (BIT(R5F_ESR2_SHIFT) | BIT(R5F_ESR4_SHIFT))
/*
* PERIOD_BYTES_MIN is the number of bytes to at which the interrupt will tick.
* This number should be a multiple of 256. Minimum value is 256
*/
#define PERIOD_BYTES_MIN 0x100
static const struct snd_pcm_hardware cygnus_pcm_hw = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
/* A period is basically an interrupt */
.period_bytes_min = PERIOD_BYTES_MIN,
.period_bytes_max = 0x10000,
/* period_min/max gives range of approx interrupts per buffer */
.periods_min = 2,
.periods_max = 8,
/*
* maximum buffer size in bytes = period_bytes_max * periods_max
* We allocate this amount of data for each enabled channel
*/
.buffer_bytes_max = 4 * 0x8000,
};
static u64 cygnus_dma_dmamask = DMA_BIT_MASK(32);
static struct cygnus_aio_port *cygnus_dai_get_dma_data(
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
return snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(soc_runtime, 0), substream);
}
static void ringbuf_set_initial(void __iomem *audio_io,
struct ringbuf_regs *p_rbuf,
bool is_playback,
u32 start,
u32 periodsize,
u32 bufsize)
{
u32 initial_rd;
u32 initial_wr;
u32 end;
u32 fmark_val; /* free or full mark */
p_rbuf->period_bytes = periodsize;
p_rbuf->buf_size = bufsize;
if (is_playback) {
/* Set the pointers to indicate full (flip uppermost bit) */
initial_rd = start;
initial_wr = initial_rd ^ BIT(31);
} else {
/* Set the pointers to indicate empty */
initial_wr = start;
initial_rd = initial_wr;
}
end = start + bufsize - 1;
/*
* The interrupt will fire when free/full mark is *exceeded*
* The fmark value must be multiple of PERIOD_BYTES_MIN so set fmark
* to be PERIOD_BYTES_MIN less than the period size.
*/
fmark_val = periodsize - PERIOD_BYTES_MIN;
writel(start, audio_io + p_rbuf->baseaddr);
writel(end, audio_io + p_rbuf->endaddr);
writel(fmark_val, audio_io + p_rbuf->fmark);
writel(initial_rd, audio_io + p_rbuf->rdaddr);
writel(initial_wr, audio_io + p_rbuf->wraddr);
}
static int configure_ringbuf_regs(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
struct ringbuf_regs *p_rbuf;
int status = 0;
aio = cygnus_dai_get_dma_data(substream);
/* Map the ssp portnum to a set of ring buffers. */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
p_rbuf = &aio->play_rb_regs;
switch (aio->portnum) {
case 0:
*p_rbuf = RINGBUF_REG_PLAYBACK(0);
break;
case 1:
*p_rbuf = RINGBUF_REG_PLAYBACK(2);
break;
case 2:
*p_rbuf = RINGBUF_REG_PLAYBACK(4);
break;
case 3: /* SPDIF */
*p_rbuf = RINGBUF_REG_PLAYBACK(6);
break;
default:
status = -EINVAL;
}
} else {
p_rbuf = &aio->capture_rb_regs;
switch (aio->portnum) {
case 0:
*p_rbuf = RINGBUF_REG_CAPTURE(0);
break;
case 1:
*p_rbuf = RINGBUF_REG_CAPTURE(2);
break;
case 2:
*p_rbuf = RINGBUF_REG_CAPTURE(4);
break;
default:
status = -EINVAL;
}
}
return status;
}
static struct ringbuf_regs *get_ringbuf(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
struct ringbuf_regs *p_rbuf = NULL;
aio = cygnus_dai_get_dma_data(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
p_rbuf = &aio->play_rb_regs;
else
p_rbuf = &aio->capture_rb_regs;
return p_rbuf;
}
static void enable_intr(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
u32 clear_mask;
aio = cygnus_dai_get_dma_data(substream);
/* The port number maps to the bit position to be cleared */
clear_mask = BIT(aio->portnum);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Clear interrupt status before enabling them */
writel(clear_mask, aio->cygaud->audio + ESR0_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR1_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR3_STATUS_CLR_OFFSET);
/* Unmask the interrupts of the given port*/
writel(clear_mask, aio->cygaud->audio + ESR0_MASK_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR1_MASK_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR3_MASK_CLR_OFFSET);
writel(ANY_PLAYBACK_IRQ,
aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
} else {
writel(clear_mask, aio->cygaud->audio + ESR2_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR4_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR2_MASK_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR4_MASK_CLR_OFFSET);
writel(ANY_CAPTURE_IRQ,
aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
}
}
static void disable_intr(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct cygnus_aio_port *aio;
u32 set_mask;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s on port %d\n", __func__, aio->portnum);
/* The port number maps to the bit position to be set */
set_mask = BIT(aio->portnum);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Mask the interrupts of the given port*/
writel(set_mask, aio->cygaud->audio + ESR0_MASK_SET_OFFSET);
writel(set_mask, aio->cygaud->audio + ESR1_MASK_SET_OFFSET);
writel(set_mask, aio->cygaud->audio + ESR3_MASK_SET_OFFSET);
} else {
writel(set_mask, aio->cygaud->audio + ESR2_MASK_SET_OFFSET);
writel(set_mask, aio->cygaud->audio + ESR4_MASK_SET_OFFSET);
}
}
static int cygnus_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
enable_intr(substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
disable_intr(substream);
break;
default:
ret = -EINVAL;
}
return ret;
}
static void cygnus_pcm_period_elapsed(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
struct ringbuf_regs *p_rbuf = NULL;
u32 regval;
aio = cygnus_dai_get_dma_data(substream);
p_rbuf = get_ringbuf(substream);
/*
* If free/full mark interrupt occurs, provide timestamp
* to ALSA and update appropriate idx by period_bytes
*/
snd_pcm_period_elapsed(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Set the ring buffer to full */
regval = readl(aio->cygaud->audio + p_rbuf->rdaddr);
regval = regval ^ BIT(31);
writel(regval, aio->cygaud->audio + p_rbuf->wraddr);
} else {
/* Set the ring buffer to empty */
regval = readl(aio->cygaud->audio + p_rbuf->wraddr);
writel(regval, aio->cygaud->audio + p_rbuf->rdaddr);
}
}
/*
* ESR0/1/3 status Description
* 0x1 I2S0_out port caused interrupt
* 0x2 I2S1_out port caused interrupt
* 0x4 I2S2_out port caused interrupt
* 0x8 SPDIF_out port caused interrupt
*/
static void handle_playback_irq(struct cygnus_audio *cygaud)
{
void __iomem *audio_io;
u32 port;
u32 esr_status0, esr_status1, esr_status3;
audio_io = cygaud->audio;
/*
* ESR status gets updates with/without interrupts enabled.
* So, check the ESR mask, which provides interrupt enable/
* disable status and use it to determine which ESR status
* should be serviced.
*/
esr_status0 = readl(audio_io + ESR0_STATUS_OFFSET);
esr_status0 &= ~readl(audio_io + ESR0_MASK_STATUS_OFFSET);
esr_status1 = readl(audio_io + ESR1_STATUS_OFFSET);
esr_status1 &= ~readl(audio_io + ESR1_MASK_STATUS_OFFSET);
esr_status3 = readl(audio_io + ESR3_STATUS_OFFSET);
esr_status3 &= ~readl(audio_io + ESR3_MASK_STATUS_OFFSET);
for (port = 0; port < CYGNUS_MAX_PLAYBACK_PORTS; port++) {
u32 esrmask = BIT(port);
/*
* Ringbuffer or FIFO underflow
* If we get this interrupt then, it is also true that we have
* not yet responded to the freemark interrupt.
* Log a debug message. The freemark handler below will
* handle getting everything going again.
*/
if ((esrmask & esr_status1) || (esrmask & esr_status0)) {
dev_dbg(cygaud->dev,
"Underrun: esr0=0x%x, esr1=0x%x esr3=0x%x\n",
esr_status0, esr_status1, esr_status3);
}
/*
* Freemark is hit. This is the normal interrupt.
* In typical operation the read and write regs will be equal
*/
if (esrmask & esr_status3) {
struct snd_pcm_substream *playstr;
playstr = cygaud->portinfo[port].play_stream;
cygnus_pcm_period_elapsed(playstr);
}
}
/* Clear ESR interrupt */
writel(esr_status0, audio_io + ESR0_STATUS_CLR_OFFSET);
writel(esr_status1, audio_io + ESR1_STATUS_CLR_OFFSET);
writel(esr_status3, audio_io + ESR3_STATUS_CLR_OFFSET);
/* Rearm freemark logic by writing 1 to the correct bit */
writel(esr_status3, audio_io + BF_REARM_FREE_MARK_OFFSET);
}
/*
* ESR2/4 status Description
* 0x1 I2S0_in port caused interrupt
* 0x2 I2S1_in port caused interrupt
* 0x4 I2S2_in port caused interrupt
*/
static void handle_capture_irq(struct cygnus_audio *cygaud)
{
void __iomem *audio_io;
u32 port;
u32 esr_status2, esr_status4;
audio_io = cygaud->audio;
/*
* ESR status gets updates with/without interrupts enabled.
* So, check the ESR mask, which provides interrupt enable/
* disable status and use it to determine which ESR status
* should be serviced.
*/
esr_status2 = readl(audio_io + ESR2_STATUS_OFFSET);
esr_status2 &= ~readl(audio_io + ESR2_MASK_STATUS_OFFSET);
esr_status4 = readl(audio_io + ESR4_STATUS_OFFSET);
esr_status4 &= ~readl(audio_io + ESR4_MASK_STATUS_OFFSET);
for (port = 0; port < CYGNUS_MAX_CAPTURE_PORTS; port++) {
u32 esrmask = BIT(port);
/*
* Ringbuffer or FIFO overflow
* If we get this interrupt then, it is also true that we have
* not yet responded to the fullmark interrupt.
* Log a debug message. The fullmark handler below will
* handle getting everything going again.
*/
if (esrmask & esr_status2)
dev_dbg(cygaud->dev,
"Overflow: esr2=0x%x\n", esr_status2);
if (esrmask & esr_status4) {
struct snd_pcm_substream *capstr;
capstr = cygaud->portinfo[port].capture_stream;
cygnus_pcm_period_elapsed(capstr);
}
}
writel(esr_status2, audio_io + ESR2_STATUS_CLR_OFFSET);
writel(esr_status4, audio_io + ESR4_STATUS_CLR_OFFSET);
/* Rearm fullmark logic by writing 1 to the correct bit */
writel(esr_status4, audio_io + BF_REARM_FULL_MARK_OFFSET);
}
static irqreturn_t cygnus_dma_irq(int irq, void *data)
{
u32 r5_status;
struct cygnus_audio *cygaud = data;
/*
* R5 status bits Description
* 0 ESR0 (playback FIFO interrupt)
* 1 ESR1 (playback rbuf interrupt)
* 2 ESR2 (capture rbuf interrupt)
* 3 ESR3 (Freemark play. interrupt)
* 4 ESR4 (Fullmark capt. interrupt)
*/
r5_status = readl(cygaud->audio + INTH_R5F_STATUS_OFFSET);
if (!(r5_status & (ANY_PLAYBACK_IRQ | ANY_CAPTURE_IRQ)))
return IRQ_NONE;
/* If playback interrupt happened */
if (ANY_PLAYBACK_IRQ & r5_status) {
handle_playback_irq(cygaud);
writel(ANY_PLAYBACK_IRQ & r5_status,
cygaud->audio + INTH_R5F_CLEAR_OFFSET);
}
/* If capture interrupt happened */
if (ANY_CAPTURE_IRQ & r5_status) {
handle_capture_irq(cygaud);
writel(ANY_CAPTURE_IRQ & r5_status,
cygaud->audio + INTH_R5F_CLEAR_OFFSET);
}
return IRQ_HANDLED;
}
static int cygnus_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct cygnus_aio_port *aio;
int ret;
aio = cygnus_dai_get_dma_data(substream);
if (!aio)
return -ENODEV;
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
snd_soc_set_runtime_hwparams(substream, &cygnus_pcm_hw);
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, PERIOD_BYTES_MIN);
if (ret < 0)
return ret;
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, PERIOD_BYTES_MIN);
if (ret < 0)
return ret;
/*
* Keep track of which substream belongs to which port.
* This info is needed by snd_pcm_period_elapsed() in irq_handler
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aio->play_stream = substream;
else
aio->capture_stream = substream;
return 0;
}
static int cygnus_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct cygnus_aio_port *aio;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aio->play_stream = NULL;
else
aio->capture_stream = NULL;
if (!aio->play_stream && !aio->capture_stream)
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "freed port %d\n", aio->portnum);
return 0;
}
static int cygnus_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct cygnus_aio_port *aio;
unsigned long bufsize, periodsize;
bool is_play;
u32 start;
struct ringbuf_regs *p_rbuf = NULL;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);
bufsize = snd_pcm_lib_buffer_bytes(substream);
periodsize = snd_pcm_lib_period_bytes(substream);
dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s (buf_size %lu) (period_size %lu)\n",
__func__, bufsize, periodsize);
configure_ringbuf_regs(substream);
p_rbuf = get_ringbuf(substream);
start = runtime->dma_addr;
is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1 : 0;
ringbuf_set_initial(aio->cygaud->audio, p_rbuf, is_play, start,
periodsize, bufsize);
return 0;
}
static snd_pcm_uframes_t cygnus_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
unsigned int res = 0, cur = 0, base = 0;
struct ringbuf_regs *p_rbuf = NULL;
aio = cygnus_dai_get_dma_data(substream);
/*
* Get the offset of the current read (for playack) or write
* index (for capture). Report this value back to the asoc framework.
*/
p_rbuf = get_ringbuf(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
cur = readl(aio->cygaud->audio + p_rbuf->rdaddr);
else
cur = readl(aio->cygaud->audio + p_rbuf->wraddr);
base = readl(aio->cygaud->audio + p_rbuf->baseaddr);
/*
* Mask off the MSB of the rdaddr,wraddr and baseaddr
* since MSB is not part of the address
*/
res = (cur & 0x7fffffff) - (base & 0x7fffffff);
return bytes_to_frames(substream->runtime, res);
}
static int cygnus_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
size_t size = cygnus_pcm_hw.buffer_bytes_max;
struct snd_card *card = rtd->card->snd_card;
if (!card->dev->dma_mask)
card->dev->dma_mask = &cygnus_dma_dmamask;
if (!card->dev->coherent_dma_mask)
card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
card->dev, size, size);
return 0;
}
static struct snd_soc_component_driver cygnus_soc_platform = {
.open = cygnus_pcm_open,
.close = cygnus_pcm_close,
.prepare = cygnus_pcm_prepare,
.trigger = cygnus_pcm_trigger,
.pointer = cygnus_pcm_pointer,
.pcm_construct = cygnus_dma_new,
};
int cygnus_soc_platform_register(struct device *dev,
struct cygnus_audio *cygaud)
{
int rc;
dev_dbg(dev, "%s Enter\n", __func__);
rc = devm_request_irq(dev, cygaud->irq_num, cygnus_dma_irq,
IRQF_SHARED, "cygnus-audio", cygaud);
if (rc) {
dev_err(dev, "%s request_irq error %d\n", __func__, rc);
return rc;
}
rc = devm_snd_soc_register_component(dev, &cygnus_soc_platform,
NULL, 0);
if (rc) {
dev_err(dev, "%s failed\n", __func__);
return rc;
}
return 0;
}
int cygnus_soc_platform_unregister(struct device *dev)
{
return 0;
}
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Cygnus ASoC PCM module");
| linux-master | sound/soc/bcm/cygnus-pcm.c |
/*
* ALSA PCM interface for ST SPEAr Processors
*
* sound/soc/spear/spear_pcm.c
*
* Copyright (C) 2012 ST Microelectronics
* Rajeev Kumar<[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/spear_dma.h>
#include "spear_pcm.h"
static const struct snd_pcm_hardware spear_pcm_hardware = {
.info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME),
.buffer_bytes_max = 16 * 1024, /* max buffer size */
.period_bytes_min = 2 * 1024, /* 1 msec data minimum period size */
.period_bytes_max = 2 * 1024, /* maximum period size */
.periods_min = 1, /* min # periods */
.periods_max = 8, /* max # of periods */
.fifo_size = 0, /* fifo size in bytes */
};
static const struct snd_dmaengine_pcm_config spear_dmaengine_pcm_config = {
.pcm_hardware = &spear_pcm_hardware,
.prealloc_buffer_size = 16 * 1024,
};
int devm_spear_pcm_platform_register(struct device *dev,
struct snd_dmaengine_pcm_config *config,
bool (*filter)(struct dma_chan *chan, void *slave))
{
*config = spear_dmaengine_pcm_config;
config->compat_filter_fn = filter;
return devm_snd_dmaengine_pcm_register(dev, config,
SND_DMAENGINE_PCM_FLAG_NO_DT |
SND_DMAENGINE_PCM_FLAG_COMPAT);
}
EXPORT_SYMBOL_GPL(devm_spear_pcm_platform_register);
MODULE_AUTHOR("Rajeev Kumar <[email protected]>");
MODULE_DESCRIPTION("SPEAr PCM DMA module");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/spear/spear_pcm.c |
/*
* ALSA SoC SPDIF In Audio Layer for spear processors
*
* Copyright (C) 2012 ST Microelectronics
* Vipin Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/spear_dma.h>
#include <sound/spear_spdif.h>
#include "spdif_in_regs.h"
#include "spear_pcm.h"
struct spdif_in_params {
u32 format;
};
struct spdif_in_dev {
struct clk *clk;
struct spear_dma_data dma_params;
struct spdif_in_params saved_params;
void *io_base;
struct device *dev;
void (*reset_perip)(void);
int irq;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_pcm_config config;
};
static void spdif_in_configure(struct spdif_in_dev *host)
{
u32 ctrl = SPDIF_IN_PRTYEN | SPDIF_IN_STATEN | SPDIF_IN_USREN |
SPDIF_IN_VALEN | SPDIF_IN_BLKEN;
ctrl |= SPDIF_MODE_16BIT | SPDIF_FIFO_THRES_16;
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK);
}
static int spdif_in_dai_probe(struct snd_soc_dai *dai)
{
struct spdif_in_dev *host = snd_soc_dai_get_drvdata(dai);
host->dma_params_rx.filter_data = &host->dma_params;
dai->capture_dma_data = &host->dma_params_rx;
return 0;
}
static void spdif_in_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct spdif_in_dev *host = snd_soc_dai_get_drvdata(dai);
if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
return;
writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK);
}
static void spdif_in_format(struct spdif_in_dev *host, u32 format)
{
u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL);
switch (format) {
case SNDRV_PCM_FORMAT_S16_LE:
ctrl |= SPDIF_XTRACT_16BIT;
break;
case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
ctrl &= ~SPDIF_XTRACT_16BIT;
break;
}
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
}
static int spdif_in_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct spdif_in_dev *host = snd_soc_dai_get_drvdata(dai);
u32 format;
if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
return -EINVAL;
format = params_format(params);
host->saved_params.format = format;
return 0;
}
static int spdif_in_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct spdif_in_dev *host = snd_soc_dai_get_drvdata(dai);
u32 ctrl;
int ret = 0;
if (substream->stream != SNDRV_PCM_STREAM_CAPTURE)
return -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
clk_enable(host->clk);
spdif_in_configure(host);
spdif_in_format(host, host->saved_params.format);
ctrl = readl(host->io_base + SPDIF_IN_CTRL);
ctrl |= SPDIF_IN_SAMPLE | SPDIF_IN_ENB;
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ctrl = readl(host->io_base + SPDIF_IN_CTRL);
ctrl &= ~(SPDIF_IN_SAMPLE | SPDIF_IN_ENB);
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK);
if (host->reset_perip)
host->reset_perip();
clk_disable(host->clk);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct snd_soc_dai_ops spdif_in_dai_ops = {
.shutdown = spdif_in_shutdown,
.trigger = spdif_in_trigger,
.hw_params = spdif_in_hw_params,
};
static struct snd_soc_dai_driver spdif_in_dai = {
.probe = spdif_in_dai_probe,
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000),
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
},
.ops = &spdif_in_dai_ops,
};
static const struct snd_soc_component_driver spdif_in_component = {
.name = "spdif-in",
.legacy_dai_naming = 1,
};
static irqreturn_t spdif_in_irq(int irq, void *arg)
{
struct spdif_in_dev *host = (struct spdif_in_dev *)arg;
u32 irq_status = readl(host->io_base + SPDIF_IN_IRQ);
if (!irq_status)
return IRQ_NONE;
if (irq_status & SPDIF_IRQ_FIFOWRITE)
dev_err(host->dev, "spdif in: fifo write error");
if (irq_status & SPDIF_IRQ_EMPTYFIFOREAD)
dev_err(host->dev, "spdif in: empty fifo read error");
if (irq_status & SPDIF_IRQ_FIFOFULL)
dev_err(host->dev, "spdif in: fifo full error");
if (irq_status & SPDIF_IRQ_OUTOFRANGE)
dev_err(host->dev, "spdif in: out of range error");
writel(0, host->io_base + SPDIF_IN_IRQ);
return IRQ_HANDLED;
}
static int spdif_in_probe(struct platform_device *pdev)
{
struct spdif_in_dev *host;
struct spear_spdif_platform_data *pdata;
struct resource *res_fifo;
void __iomem *io_base;
int ret;
io_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(io_base))
return PTR_ERR(io_base);
res_fifo = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!res_fifo)
return -EINVAL;
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
if (!host)
return -ENOMEM;
host->io_base = io_base;
host->irq = platform_get_irq(pdev, 0);
if (host->irq < 0) {
dev_warn(&pdev->dev, "failed to get IRQ: %d\n", host->irq);
return host->irq;
}
host->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(host->clk))
return PTR_ERR(host->clk);
pdata = dev_get_platdata(&pdev->dev);
if (!pdata)
return -EINVAL;
host->dma_params.data = pdata->dma_params;
host->dma_params.addr = res_fifo->start;
host->dma_params.max_burst = 16;
host->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
host->reset_perip = pdata->reset_perip;
host->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, host);
ret = devm_request_irq(&pdev->dev, host->irq, spdif_in_irq, 0,
"spdif-in", host);
if (ret) {
dev_warn(&pdev->dev, "request_irq failed\n");
return ret;
}
ret = devm_snd_soc_register_component(&pdev->dev, &spdif_in_component,
&spdif_in_dai, 1);
if (ret)
return ret;
return devm_spear_pcm_platform_register(&pdev->dev, &host->config,
pdata->filter);
}
static struct platform_driver spdif_in_driver = {
.probe = spdif_in_probe,
.driver = {
.name = "spdif-in",
},
};
module_platform_driver(spdif_in_driver);
MODULE_AUTHOR("Vipin Kumar <[email protected]>");
MODULE_DESCRIPTION("SPEAr SPDIF IN SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:spdif_in");
| linux-master | sound/soc/spear/spdif_in.c |
/*
* ALSA SoC SPDIF Out Audio Layer for spear processors
*
* Copyright (C) 2012 ST Microelectronics
* Vipin Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/dmaengine_pcm.h>
#include <sound/soc.h>
#include <sound/spear_dma.h>
#include <sound/spear_spdif.h>
#include "spdif_out_regs.h"
#include "spear_pcm.h"
struct spdif_out_params {
u32 rate;
u32 core_freq;
u32 mute;
};
struct spdif_out_dev {
struct clk *clk;
struct spear_dma_data dma_params;
struct spdif_out_params saved_params;
u32 running;
void __iomem *io_base;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_pcm_config config;
};
static void spdif_out_configure(struct spdif_out_dev *host)
{
writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST);
mdelay(1);
writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET,
host->io_base + SPDIF_OUT_SOFT_RST);
writel(SPDIF_OUT_FDMA_TRIG_16 | SPDIF_OUT_MEMFMT_16_16 |
SPDIF_OUT_VALID_HW | SPDIF_OUT_USER_HW |
SPDIF_OUT_CHNLSTA_HW | SPDIF_OUT_PARITY_HW,
host->io_base + SPDIF_OUT_CFG);
writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR);
writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR);
}
static int spdif_out_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
int ret;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
ret = clk_enable(host->clk);
if (ret)
return ret;
host->running = true;
spdif_out_configure(host);
return 0;
}
static void spdif_out_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return;
clk_disable(host->clk);
host->running = false;
}
static void spdif_out_clock(struct spdif_out_dev *host, u32 core_freq,
u32 rate)
{
u32 divider, ctrl;
clk_set_rate(host->clk, core_freq);
divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128));
ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
ctrl &= ~SPDIF_DIVIDER_MASK;
ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK;
writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
}
static int spdif_out_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
u32 rate, core_freq;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
rate = params_rate(params);
switch (rate) {
case 8000:
case 16000:
case 32000:
case 64000:
/*
* The clock is multiplied by 10 to bring it to feasible range
* of frequencies for sscg
*/
core_freq = 64000 * 128 * 10; /* 81.92 MHz */
break;
case 5512:
case 11025:
case 22050:
case 44100:
case 88200:
case 176400:
core_freq = 176400 * 128; /* 22.5792 MHz */
break;
case 48000:
case 96000:
case 192000:
default:
core_freq = 192000 * 128; /* 24.576 MHz */
break;
}
spdif_out_clock(host, core_freq, rate);
host->saved_params.core_freq = core_freq;
host->saved_params.rate = rate;
return 0;
}
static int spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
u32 ctrl;
int ret = 0;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
ctrl &= ~SPDIF_OPMODE_MASK;
if (!host->saved_params.mute)
ctrl |= SPDIF_OPMODE_AUD_DATA |
SPDIF_STATE_NORMAL;
else
ctrl |= SPDIF_OPMODE_MUTE_PCM;
writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
ctrl &= ~SPDIF_OPMODE_MASK;
ctrl |= SPDIF_OPMODE_OFF;
writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int spdif_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
u32 val;
host->saved_params.mute = mute;
val = readl(host->io_base + SPDIF_OUT_CTRL);
val &= ~SPDIF_OPMODE_MASK;
if (mute)
val |= SPDIF_OPMODE_MUTE_PCM;
else {
if (host->running)
val |= SPDIF_OPMODE_AUD_DATA | SPDIF_STATE_NORMAL;
else
val |= SPDIF_OPMODE_OFF;
}
writel(val, host->io_base + SPDIF_OUT_CTRL);
return 0;
}
static int spdif_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
ucontrol->value.integer.value[0] = host->saved_params.mute;
return 0;
}
static int spdif_mute_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
if (host->saved_params.mute == ucontrol->value.integer.value[0])
return 0;
spdif_mute(cpu_dai, ucontrol->value.integer.value[0],
SNDRV_PCM_STREAM_PLAYBACK);
return 1;
}
static const struct snd_kcontrol_new spdif_out_controls[] = {
SOC_SINGLE_BOOL_EXT("IEC958 Playback Switch", 0,
spdif_mute_get, spdif_mute_put),
};
static int spdif_soc_dai_probe(struct snd_soc_dai *dai)
{
struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
host->dma_params_tx.filter_data = &host->dma_params;
snd_soc_dai_dma_data_set_playback(dai, &host->dma_params_tx);
return snd_soc_add_dai_controls(dai, spdif_out_controls,
ARRAY_SIZE(spdif_out_controls));
}
static const struct snd_soc_dai_ops spdif_out_dai_ops = {
.mute_stream = spdif_mute,
.startup = spdif_out_startup,
.shutdown = spdif_out_shutdown,
.trigger = spdif_out_trigger,
.hw_params = spdif_out_hw_params,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver spdif_out_dai = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.probe = spdif_soc_dai_probe,
.ops = &spdif_out_dai_ops,
};
static const struct snd_soc_component_driver spdif_out_component = {
.name = "spdif-out",
.legacy_dai_naming = 1,
};
static int spdif_out_probe(struct platform_device *pdev)
{
struct spdif_out_dev *host;
struct spear_spdif_platform_data *pdata;
struct resource *res;
int ret;
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
if (!host)
return -ENOMEM;
host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(host->io_base))
return PTR_ERR(host->io_base);
host->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(host->clk))
return PTR_ERR(host->clk);
pdata = dev_get_platdata(&pdev->dev);
host->dma_params.data = pdata->dma_params;
host->dma_params.addr = res->start + SPDIF_OUT_FIFO_DATA;
host->dma_params.max_burst = 16;
host->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dev_set_drvdata(&pdev->dev, host);
ret = devm_snd_soc_register_component(&pdev->dev, &spdif_out_component,
&spdif_out_dai, 1);
if (ret)
return ret;
return devm_spear_pcm_platform_register(&pdev->dev, &host->config,
pdata->filter);
}
#ifdef CONFIG_PM
static int spdif_out_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct spdif_out_dev *host = dev_get_drvdata(&pdev->dev);
if (host->running)
clk_disable(host->clk);
return 0;
}
static int spdif_out_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct spdif_out_dev *host = dev_get_drvdata(&pdev->dev);
if (host->running) {
clk_enable(host->clk);
spdif_out_configure(host);
spdif_out_clock(host, host->saved_params.core_freq,
host->saved_params.rate);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(spdif_out_dev_pm_ops, spdif_out_suspend, \
spdif_out_resume);
#define SPDIF_OUT_DEV_PM_OPS (&spdif_out_dev_pm_ops)
#else
#define SPDIF_OUT_DEV_PM_OPS NULL
#endif
static struct platform_driver spdif_out_driver = {
.probe = spdif_out_probe,
.driver = {
.name = "spdif-out",
.pm = SPDIF_OUT_DEV_PM_OPS,
},
};
module_platform_driver(spdif_out_driver);
MODULE_AUTHOR("Vipin Kumar <[email protected]>");
MODULE_DESCRIPTION("SPEAr SPDIF OUT SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:spdif_out");
| linux-master | sound/soc/spear/spdif_out.c |
// SPDX-License-Identifier: GPL-2.0
//
// ASoC simple sound card support
//
// Copyright (C) 2012 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <sound/simple_card.h>
#include <sound/soc-dai.h>
#include <sound/soc.h>
#define DPCM_SELECTABLE 1
#define DAI "sound-dai"
#define CELL "#sound-dai-cells"
#define PREFIX "simple-audio-card,"
static const struct snd_soc_ops simple_ops = {
.startup = asoc_simple_startup,
.shutdown = asoc_simple_shutdown,
.hw_params = asoc_simple_hw_params,
};
static int asoc_simple_parse_platform(struct device_node *node,
struct snd_soc_dai_link_component *dlc)
{
struct of_phandle_args args;
int ret;
if (!node)
return 0;
/*
* Get node via "sound-dai = <&phandle port>"
* it will be used as xxx_of_node on soc_bind_dai_link()
*/
ret = of_parse_phandle_with_args(node, DAI, CELL, 0, &args);
if (ret)
return ret;
/* dai_name is not required and may not exist for plat component */
dlc->of_node = args.np;
return 0;
}
static int asoc_simple_parse_dai(struct device *dev,
struct device_node *node,
struct snd_soc_dai_link_component *dlc,
int *is_single_link)
{
struct of_phandle_args args;
struct snd_soc_dai *dai;
int ret;
if (!node)
return 0;
/*
* Get node via "sound-dai = <&phandle port>"
* it will be used as xxx_of_node on soc_bind_dai_link()
*/
ret = of_parse_phandle_with_args(node, DAI, CELL, 0, &args);
if (ret)
return ret;
/*
* Try to find from DAI args
*/
dai = snd_soc_get_dai_via_args(&args);
if (dai) {
dlc->dai_name = snd_soc_dai_name_get(dai);
dlc->dai_args = snd_soc_copy_dai_args(dev, &args);
if (!dlc->dai_args)
return -ENOMEM;
goto parse_dai_end;
}
/*
* FIXME
*
* Here, dlc->dai_name is pointer to CPU/Codec DAI name.
* If user unbinded CPU or Codec driver, but not for Sound Card,
* dlc->dai_name is keeping unbinded CPU or Codec
* driver's pointer.
*
* If user re-bind CPU or Codec driver again, ALSA SoC will try
* to rebind Card via snd_soc_try_rebind_card(), but because of
* above reason, it might can't bind Sound Card.
* Because Sound Card is pointing to released dai_name pointer.
*
* To avoid this rebind Card issue,
* 1) It needs to alloc memory to keep dai_name eventhough
* CPU or Codec driver was unbinded, or
* 2) user need to rebind Sound Card everytime
* if he unbinded CPU or Codec.
*/
ret = snd_soc_get_dlc(&args, dlc);
if (ret < 0)
return ret;
parse_dai_end:
if (is_single_link)
*is_single_link = !args.args_count;
return 0;
}
static void simple_parse_convert(struct device *dev,
struct device_node *np,
struct asoc_simple_data *adata)
{
struct device_node *top = dev->of_node;
struct device_node *node = of_get_parent(np);
asoc_simple_parse_convert(top, PREFIX, adata);
asoc_simple_parse_convert(node, PREFIX, adata);
asoc_simple_parse_convert(node, NULL, adata);
asoc_simple_parse_convert(np, NULL, adata);
of_node_put(node);
}
static void simple_parse_mclk_fs(struct device_node *top,
struct device_node *np,
struct simple_dai_props *props,
char *prefix)
{
struct device_node *node = of_get_parent(np);
char prop[128];
snprintf(prop, sizeof(prop), "%smclk-fs", PREFIX);
of_property_read_u32(top, prop, &props->mclk_fs);
snprintf(prop, sizeof(prop), "%smclk-fs", prefix);
of_property_read_u32(node, prop, &props->mclk_fs);
of_property_read_u32(np, prop, &props->mclk_fs);
of_node_put(node);
}
static int simple_parse_node(struct asoc_simple_priv *priv,
struct device_node *np,
struct link_info *li,
char *prefix,
int *cpu)
{
struct device *dev = simple_priv_to_dev(priv);
struct device_node *top = dev->of_node;
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, li->link);
struct snd_soc_dai_link_component *dlc;
struct asoc_simple_dai *dai;
int ret;
if (cpu) {
dlc = asoc_link_to_cpu(dai_link, 0);
dai = simple_props_to_dai_cpu(dai_props, 0);
} else {
dlc = asoc_link_to_codec(dai_link, 0);
dai = simple_props_to_dai_codec(dai_props, 0);
}
simple_parse_mclk_fs(top, np, dai_props, prefix);
ret = asoc_simple_parse_dai(dev, np, dlc, cpu);
if (ret)
return ret;
ret = asoc_simple_parse_clk(dev, np, dai, dlc);
if (ret)
return ret;
ret = asoc_simple_parse_tdm(np, dai);
if (ret)
return ret;
return 0;
}
static int simple_link_init(struct asoc_simple_priv *priv,
struct device_node *node,
struct device_node *codec,
struct link_info *li,
char *prefix, char *name)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
int ret;
ret = asoc_simple_parse_daifmt(dev, node, codec,
prefix, &dai_link->dai_fmt);
if (ret < 0)
return 0;
dai_link->init = asoc_simple_dai_init;
dai_link->ops = &simple_ops;
return asoc_simple_set_dailink_name(dev, dai_link, name);
}
static int simple_dai_link_of_dpcm(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li,
bool is_top)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, li->link);
struct device_node *top = dev->of_node;
struct device_node *node = of_get_parent(np);
char *prefix = "";
char dai_name[64];
int ret;
dev_dbg(dev, "link_of DPCM (%pOF)\n", np);
/* For single DAI link & old style of DT node */
if (is_top)
prefix = PREFIX;
if (li->cpu) {
struct snd_soc_dai_link_component *cpus = asoc_link_to_cpu(dai_link, 0);
struct snd_soc_dai_link_component *platforms = asoc_link_to_platform(dai_link, 0);
int is_single_links = 0;
/* Codec is dummy */
/* FE settings */
dai_link->dynamic = 1;
dai_link->dpcm_merged_format = 1;
ret = simple_parse_node(priv, np, li, prefix, &is_single_links);
if (ret < 0)
goto out_put_node;
snprintf(dai_name, sizeof(dai_name), "fe.%s", cpus->dai_name);
asoc_simple_canonicalize_cpu(cpus, is_single_links);
asoc_simple_canonicalize_platform(platforms, cpus);
} else {
struct snd_soc_dai_link_component *codecs = asoc_link_to_codec(dai_link, 0);
struct snd_soc_codec_conf *cconf;
/* CPU is dummy */
/* BE settings */
dai_link->no_pcm = 1;
dai_link->be_hw_params_fixup = asoc_simple_be_hw_params_fixup;
cconf = simple_props_to_codec_conf(dai_props, 0);
ret = simple_parse_node(priv, np, li, prefix, NULL);
if (ret < 0)
goto out_put_node;
snprintf(dai_name, sizeof(dai_name), "be.%s", codecs->dai_name);
/* check "prefix" from top node */
snd_soc_of_parse_node_prefix(top, cconf, codecs->of_node,
PREFIX "prefix");
snd_soc_of_parse_node_prefix(node, cconf, codecs->of_node,
"prefix");
snd_soc_of_parse_node_prefix(np, cconf, codecs->of_node,
"prefix");
}
simple_parse_convert(dev, np, &dai_props->adata);
snd_soc_dai_link_set_capabilities(dai_link);
ret = simple_link_init(priv, node, codec, li, prefix, dai_name);
out_put_node:
li->link++;
of_node_put(node);
return ret;
}
static int simple_dai_link_of(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li,
bool is_top)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct snd_soc_dai_link_component *cpus = asoc_link_to_cpu(dai_link, 0);
struct snd_soc_dai_link_component *codecs = asoc_link_to_codec(dai_link, 0);
struct snd_soc_dai_link_component *platforms = asoc_link_to_platform(dai_link, 0);
struct device_node *cpu = NULL;
struct device_node *node = NULL;
struct device_node *plat = NULL;
char dai_name[64];
char prop[128];
char *prefix = "";
int ret, single_cpu = 0;
cpu = np;
node = of_get_parent(np);
dev_dbg(dev, "link_of (%pOF)\n", node);
/* For single DAI link & old style of DT node */
if (is_top)
prefix = PREFIX;
snprintf(prop, sizeof(prop), "%splat", prefix);
plat = of_get_child_by_name(node, prop);
ret = simple_parse_node(priv, cpu, li, prefix, &single_cpu);
if (ret < 0)
goto dai_link_of_err;
ret = simple_parse_node(priv, codec, li, prefix, NULL);
if (ret < 0)
goto dai_link_of_err;
ret = asoc_simple_parse_platform(plat, platforms);
if (ret < 0)
goto dai_link_of_err;
snprintf(dai_name, sizeof(dai_name),
"%s-%s", cpus->dai_name, codecs->dai_name);
asoc_simple_canonicalize_cpu(cpus, single_cpu);
asoc_simple_canonicalize_platform(platforms, cpus);
ret = simple_link_init(priv, node, codec, li, prefix, dai_name);
dai_link_of_err:
of_node_put(plat);
of_node_put(node);
li->link++;
return ret;
}
static int __simple_for_each_link(struct asoc_simple_priv *priv,
struct link_info *li,
int (*func_noml)(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li, bool is_top),
int (*func_dpcm)(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li, bool is_top))
{
struct device *dev = simple_priv_to_dev(priv);
struct device_node *top = dev->of_node;
struct device_node *node;
struct device_node *add_devs;
uintptr_t dpcm_selectable = (uintptr_t)of_device_get_match_data(dev);
bool is_top = 0;
int ret = 0;
/* Check if it has dai-link */
node = of_get_child_by_name(top, PREFIX "dai-link");
if (!node) {
node = of_node_get(top);
is_top = 1;
}
add_devs = of_get_child_by_name(top, PREFIX "additional-devs");
/* loop for all dai-link */
do {
struct asoc_simple_data adata;
struct device_node *codec;
struct device_node *plat;
struct device_node *np;
int num = of_get_child_count(node);
/* Skip additional-devs node */
if (node == add_devs) {
node = of_get_next_child(top, node);
continue;
}
/* get codec */
codec = of_get_child_by_name(node, is_top ?
PREFIX "codec" : "codec");
if (!codec) {
ret = -ENODEV;
goto error;
}
/* get platform */
plat = of_get_child_by_name(node, is_top ?
PREFIX "plat" : "plat");
/* get convert-xxx property */
memset(&adata, 0, sizeof(adata));
for_each_child_of_node(node, np) {
if (np == add_devs)
continue;
simple_parse_convert(dev, np, &adata);
}
/* loop for all CPU/Codec node */
for_each_child_of_node(node, np) {
if (plat == np || add_devs == np)
continue;
/*
* It is DPCM
* if it has many CPUs,
* or has convert-xxx property
*/
if (dpcm_selectable &&
(num > 2 || asoc_simple_is_convert_required(&adata))) {
/*
* np
* |1(CPU)|0(Codec) li->cpu
* CPU |Pass |return
* Codec |return|Pass
*/
if (li->cpu != (np == codec))
ret = func_dpcm(priv, np, codec, li, is_top);
/* else normal sound */
} else {
/*
* np
* |1(CPU)|0(Codec) li->cpu
* CPU |Pass |return
* Codec |return|return
*/
if (li->cpu && (np != codec))
ret = func_noml(priv, np, codec, li, is_top);
}
if (ret < 0) {
of_node_put(codec);
of_node_put(plat);
of_node_put(np);
goto error;
}
}
of_node_put(codec);
of_node_put(plat);
node = of_get_next_child(top, node);
} while (!is_top && node);
error:
of_node_put(add_devs);
of_node_put(node);
return ret;
}
static int simple_for_each_link(struct asoc_simple_priv *priv,
struct link_info *li,
int (*func_noml)(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li, bool is_top),
int (*func_dpcm)(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li, bool is_top))
{
int ret;
/*
* Detect all CPU first, and Detect all Codec 2nd.
*
* In Normal sound case, all DAIs are detected
* as "CPU-Codec".
*
* In DPCM sound case,
* all CPUs are detected as "CPU-dummy", and
* all Codecs are detected as "dummy-Codec".
* To avoid random sub-device numbering,
* detect "dummy-Codec" in last;
*/
for (li->cpu = 1; li->cpu >= 0; li->cpu--) {
ret = __simple_for_each_link(priv, li, func_noml, func_dpcm);
if (ret < 0)
break;
}
return ret;
}
static void simple_depopulate_aux(void *data)
{
struct asoc_simple_priv *priv = data;
of_platform_depopulate(simple_priv_to_dev(priv));
}
static int simple_populate_aux(struct asoc_simple_priv *priv)
{
struct device *dev = simple_priv_to_dev(priv);
struct device_node *node;
int ret;
node = of_get_child_by_name(dev->of_node, PREFIX "additional-devs");
if (!node)
return 0;
ret = of_platform_populate(node, NULL, NULL, dev);
of_node_put(node);
if (ret)
return ret;
return devm_add_action_or_reset(dev, simple_depopulate_aux, priv);
}
static int simple_parse_of(struct asoc_simple_priv *priv, struct link_info *li)
{
struct snd_soc_card *card = simple_priv_to_card(priv);
int ret;
ret = asoc_simple_parse_widgets(card, PREFIX);
if (ret < 0)
return ret;
ret = asoc_simple_parse_routing(card, PREFIX);
if (ret < 0)
return ret;
ret = asoc_simple_parse_pin_switches(card, PREFIX);
if (ret < 0)
return ret;
/* Single/Muti DAI link(s) & New style of DT node */
memset(li, 0, sizeof(*li));
ret = simple_for_each_link(priv, li,
simple_dai_link_of,
simple_dai_link_of_dpcm);
if (ret < 0)
return ret;
ret = asoc_simple_parse_card_name(card, PREFIX);
if (ret < 0)
return ret;
ret = simple_populate_aux(priv);
if (ret < 0)
return ret;
ret = snd_soc_of_parse_aux_devs(card, PREFIX "aux-devs");
return ret;
}
static int simple_count_noml(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li, bool is_top)
{
if (li->link >= SNDRV_MAX_LINKS) {
struct device *dev = simple_priv_to_dev(priv);
dev_err(dev, "too many links\n");
return -EINVAL;
}
/*
* DON'T REMOVE platforms
*
* Some CPU might be using soc-generic-dmaengine-pcm. This means CPU and Platform
* are different Component, but are sharing same component->dev.
* Simple Card had been supported it without special Platform selection.
* We need platforms here.
*
* In case of no Platform, it will be Platform == CPU, but Platform will be
* ignored by snd_soc_rtd_add_component().
*
* see
* simple-card-utils.c :: asoc_simple_canonicalize_platform()
*/
li->num[li->link].cpus = 1;
li->num[li->link].platforms = 1;
li->num[li->link].codecs = 1;
li->link += 1;
return 0;
}
static int simple_count_dpcm(struct asoc_simple_priv *priv,
struct device_node *np,
struct device_node *codec,
struct link_info *li, bool is_top)
{
if (li->link >= SNDRV_MAX_LINKS) {
struct device *dev = simple_priv_to_dev(priv);
dev_err(dev, "too many links\n");
return -EINVAL;
}
if (li->cpu) {
/*
* DON'T REMOVE platforms
* see
* simple_count_noml()
*/
li->num[li->link].cpus = 1;
li->num[li->link].platforms = 1;
li->link++; /* CPU-dummy */
} else {
li->num[li->link].codecs = 1;
li->link++; /* dummy-Codec */
}
return 0;
}
static int simple_get_dais_count(struct asoc_simple_priv *priv,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
struct device_node *top = dev->of_node;
/*
* link_num : number of links.
* CPU-Codec / CPU-dummy / dummy-Codec
* dais_num : number of DAIs
* ccnf_num : number of codec_conf
* same number for "dummy-Codec"
*
* ex1)
* CPU0 --- Codec0 link : 5
* CPU1 --- Codec1 dais : 7
* CPU2 -/ ccnf : 1
* CPU3 --- Codec2
*
* => 5 links = 2xCPU-Codec + 2xCPU-dummy + 1xdummy-Codec
* => 7 DAIs = 4xCPU + 3xCodec
* => 1 ccnf = 1xdummy-Codec
*
* ex2)
* CPU0 --- Codec0 link : 5
* CPU1 --- Codec1 dais : 6
* CPU2 -/ ccnf : 1
* CPU3 -/
*
* => 5 links = 1xCPU-Codec + 3xCPU-dummy + 1xdummy-Codec
* => 6 DAIs = 4xCPU + 2xCodec
* => 1 ccnf = 1xdummy-Codec
*
* ex3)
* CPU0 --- Codec0 link : 6
* CPU1 -/ dais : 6
* CPU2 --- Codec1 ccnf : 2
* CPU3 -/
*
* => 6 links = 0xCPU-Codec + 4xCPU-dummy + 2xdummy-Codec
* => 6 DAIs = 4xCPU + 2xCodec
* => 2 ccnf = 2xdummy-Codec
*
* ex4)
* CPU0 --- Codec0 (convert-rate) link : 3
* CPU1 --- Codec1 dais : 4
* ccnf : 1
*
* => 3 links = 1xCPU-Codec + 1xCPU-dummy + 1xdummy-Codec
* => 4 DAIs = 2xCPU + 2xCodec
* => 1 ccnf = 1xdummy-Codec
*/
if (!top) {
li->num[0].cpus = 1;
li->num[0].codecs = 1;
li->num[0].platforms = 1;
li->link = 1;
return 0;
}
return simple_for_each_link(priv, li,
simple_count_noml,
simple_count_dpcm);
}
static int simple_soc_probe(struct snd_soc_card *card)
{
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(card);
int ret;
ret = asoc_simple_init_hp(card, &priv->hp_jack, PREFIX);
if (ret < 0)
return ret;
ret = asoc_simple_init_mic(card, &priv->mic_jack, PREFIX);
if (ret < 0)
return ret;
ret = asoc_simple_init_aux_jacks(priv, PREFIX);
if (ret < 0)
return ret;
return 0;
}
static int asoc_simple_probe(struct platform_device *pdev)
{
struct asoc_simple_priv *priv;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct snd_soc_card *card;
struct link_info *li;
int ret;
/* Allocate the private data and the DAI link array */
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
card = simple_priv_to_card(priv);
card->owner = THIS_MODULE;
card->dev = dev;
card->probe = simple_soc_probe;
card->driver_name = "simple-card";
li = devm_kzalloc(dev, sizeof(*li), GFP_KERNEL);
if (!li)
return -ENOMEM;
ret = simple_get_dais_count(priv, li);
if (ret < 0)
return ret;
if (!li->link)
return -EINVAL;
ret = asoc_simple_init_priv(priv, li);
if (ret < 0)
return ret;
if (np && of_device_is_available(np)) {
ret = simple_parse_of(priv, li);
if (ret < 0) {
dev_err_probe(dev, ret, "parse error\n");
goto err;
}
} else {
struct asoc_simple_card_info *cinfo;
struct snd_soc_dai_link_component *cpus;
struct snd_soc_dai_link_component *codecs;
struct snd_soc_dai_link_component *platform;
struct snd_soc_dai_link *dai_link = priv->dai_link;
struct simple_dai_props *dai_props = priv->dai_props;
cinfo = dev->platform_data;
if (!cinfo) {
dev_err(dev, "no info for asoc-simple-card\n");
return -EINVAL;
}
if (!cinfo->name ||
!cinfo->codec_dai.name ||
!cinfo->codec ||
!cinfo->platform ||
!cinfo->cpu_dai.name) {
dev_err(dev, "insufficient asoc_simple_card_info settings\n");
return -EINVAL;
}
cpus = dai_link->cpus;
cpus->dai_name = cinfo->cpu_dai.name;
codecs = dai_link->codecs;
codecs->name = cinfo->codec;
codecs->dai_name = cinfo->codec_dai.name;
platform = dai_link->platforms;
platform->name = cinfo->platform;
card->name = (cinfo->card) ? cinfo->card : cinfo->name;
dai_link->name = cinfo->name;
dai_link->stream_name = cinfo->name;
dai_link->dai_fmt = cinfo->daifmt;
dai_link->init = asoc_simple_dai_init;
memcpy(dai_props->cpu_dai, &cinfo->cpu_dai,
sizeof(*dai_props->cpu_dai));
memcpy(dai_props->codec_dai, &cinfo->codec_dai,
sizeof(*dai_props->codec_dai));
}
snd_soc_card_set_drvdata(card, priv);
asoc_simple_debug_info(priv);
ret = devm_snd_soc_register_card(dev, card);
if (ret < 0)
goto err;
devm_kfree(dev, li);
return 0;
err:
asoc_simple_clean_reference(card);
return ret;
}
static const struct of_device_id simple_of_match[] = {
{ .compatible = "simple-audio-card", },
{ .compatible = "simple-scu-audio-card",
.data = (void *)DPCM_SELECTABLE },
{},
};
MODULE_DEVICE_TABLE(of, simple_of_match);
static struct platform_driver asoc_simple_card = {
.driver = {
.name = "asoc-simple-card",
.pm = &snd_soc_pm_ops,
.of_match_table = simple_of_match,
},
.probe = asoc_simple_probe,
.remove = asoc_simple_remove,
};
module_platform_driver(asoc_simple_card);
MODULE_ALIAS("platform:asoc-simple-card");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ASoC Simple Sound Card");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
| linux-master | sound/soc/generic/simple-card.c |
// SPDX-License-Identifier: GPL-2.0
//
// audio-graph-card2-custom-sample.c
//
// Copyright (C) 2020 Renesas Electronics Corp.
// Copyright (C) 2020 Kuninori Morimoto <[email protected]>
//
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <sound/graph_card.h>
/*
* Custom driver can have own priv
* which includes asoc_simple_priv.
*/
struct custom_priv {
struct asoc_simple_priv simple_priv;
/* custom driver's own params */
int custom_params;
};
/* You can get custom_priv from simple_priv */
#define simple_to_custom(simple) container_of((simple), struct custom_priv, simple_priv)
static int custom_card_probe(struct snd_soc_card *card)
{
struct asoc_simple_priv *simple_priv = snd_soc_card_get_drvdata(card);
struct custom_priv *custom_priv = simple_to_custom(simple_priv);
struct device *dev = simple_priv_to_dev(simple_priv);
dev_info(dev, "custom probe\n");
custom_priv->custom_params = 1;
/* you can use generic probe function */
return asoc_graph_card_probe(card);
}
static int custom_hook_pre(struct asoc_simple_priv *priv)
{
struct device *dev = simple_priv_to_dev(priv);
/* You can custom before parsing */
dev_info(dev, "hook : %s\n", __func__);
return 0;
}
static int custom_hook_post(struct asoc_simple_priv *priv)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_card *card;
/* You can custom after parsing */
dev_info(dev, "hook : %s\n", __func__);
/* overwrite .probe sample */
card = simple_priv_to_card(priv);
card->probe = custom_card_probe;
return 0;
}
static int custom_normal(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
/*
* You can custom Normal parsing
* before/affter audio_graph2_link_normal()
*/
dev_info(dev, "hook : %s\n", __func__);
return audio_graph2_link_normal(priv, lnk, li);
}
static int custom_dpcm(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
/*
* You can custom DPCM parsing
* before/affter audio_graph2_link_dpcm()
*/
dev_info(dev, "hook : %s\n", __func__);
return audio_graph2_link_dpcm(priv, lnk, li);
}
static int custom_c2c(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
/*
* You can custom Codec2Codec parsing
* before/affter audio_graph2_link_c2c()
*/
dev_info(dev, "hook : %s\n", __func__);
return audio_graph2_link_c2c(priv, lnk, li);
}
/*
* audio-graph-card2 has many hooks for your customizing.
*/
static struct graph2_custom_hooks custom_hooks = {
.hook_pre = custom_hook_pre,
.hook_post = custom_hook_post,
.custom_normal = custom_normal,
.custom_dpcm = custom_dpcm,
.custom_c2c = custom_c2c,
};
static int custom_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct device *dev = simple_priv_to_dev(priv);
dev_info(dev, "custom startup\n");
return asoc_simple_startup(substream);
}
/* You can use custom ops */
static const struct snd_soc_ops custom_ops = {
.startup = custom_startup,
.shutdown = asoc_simple_shutdown,
.hw_params = asoc_simple_hw_params,
};
static int custom_probe(struct platform_device *pdev)
{
struct custom_priv *custom_priv;
struct asoc_simple_priv *simple_priv;
struct device *dev = &pdev->dev;
int ret;
custom_priv = devm_kzalloc(dev, sizeof(*custom_priv), GFP_KERNEL);
if (!custom_priv)
return -ENOMEM;
simple_priv = &custom_priv->simple_priv;
simple_priv->ops = &custom_ops; /* customize dai_link ops */
/* "audio-graph-card2-custom-sample" is too long */
simple_priv->snd_card.name = "card2-custom";
/* use audio-graph-card2 parsing with own custom hooks */
ret = audio_graph2_parse_of(simple_priv, dev, &custom_hooks);
if (ret < 0)
return ret;
/* customize more if needed */
return 0;
}
static const struct of_device_id custom_of_match[] = {
{ .compatible = "audio-graph-card2-custom-sample", },
{},
};
MODULE_DEVICE_TABLE(of, custom_of_match);
static struct platform_driver custom_card = {
.driver = {
.name = "audio-graph-card2-custom-sample",
.of_match_table = custom_of_match,
},
.probe = custom_probe,
.remove = asoc_simple_remove,
};
module_platform_driver(custom_card);
MODULE_ALIAS("platform:asoc-audio-graph-card2-custom-sample");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ASoC Audio Graph Card2 Custom Sample");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
| linux-master | sound/soc/generic/audio-graph-card2-custom-sample.c |
// SPDX-License-Identifier: GPL-2.0
//
// ASoC Audio Graph Card2 support
//
// Copyright (C) 2020 Renesas Electronics Corp.
// Copyright (C) 2020 Kuninori Morimoto <[email protected]>
//
// based on ${LINUX}/sound/soc/generic/audio-graph-card.c
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <sound/graph_card.h>
/************************************
daifmt
************************************
ports {
format = "left_j";
port@0 {
bitclock-master;
sample0: endpoint@0 {
frame-master;
};
sample1: endpoint@1 {
format = "i2s";
};
};
...
};
You can set daifmt at ports/port/endpoint.
It uses *latest* format, and *share* master settings.
In above case,
sample0: left_j, bitclock-master, frame-master
sample1: i2s, bitclock-master
If there was no settings, *Codec* will be
bitclock/frame provider as default.
see
graph_parse_daifmt().
"format" property is no longer needed on DT if both CPU/Codec drivers are
supporting snd_soc_dai_ops :: .auto_selectable_formats.
see
snd_soc_runtime_get_dai_fmt()
sample driver
linux/sound/soc/sh/rcar/core.c
linux/sound/soc/codecs/ak4613.c
linux/sound/soc/codecs/pcm3168a.c
linux/sound/soc/soc-utils.c
linux/sound/soc/generic/test-component.c
************************************
Normal Audio-Graph
************************************
CPU <---> Codec
sound {
compatible = "audio-graph-card2";
links = <&cpu>;
};
CPU {
cpu: port {
bitclock-master;
frame-master;
cpu_ep: endpoint { remote-endpoint = <&codec_ep>; }; };
};
Codec {
port { codec_ep: endpoint { remote-endpoint = <&cpu_ep>; }; };
};
************************************
Multi-CPU/Codec
************************************
It has connection part (= X) and list part (= y).
links indicates connection part of CPU side (= A).
+-+ (A) +-+
CPU1 --(y) | | <-(X)--(X)-> | | (y)-- Codec1
CPU2 --(y) | | | | (y)-- Codec2
+-+ +-+
sound {
compatible = "audio-graph-card2";
(A) links = <&mcpu>;
multi {
ports@0 {
(X) (A) mcpu: port@0 { mcpu0_ep: endpoint { remote-endpoint = <&mcodec0_ep>; }; };
(y) port@1 { mcpu1_ep: endpoint { remote-endpoint = <&cpu1_ep>; }; };
(y) port@2 { mcpu2_ep: endpoint { remote-endpoint = <&cpu2_ep>; }; };
};
ports@1 {
(X) port@0 { mcodec0_ep: endpoint { remote-endpoint = <&mcpu0_ep>; }; };
(y) port@1 { mcodec1_ep: endpoint { remote-endpoint = <&codec1_ep>; }; };
(y) port@2 { mcodec2_ep: endpoint { remote-endpoint = <&codec2_ep>; }; };
};
};
};
CPU {
ports {
bitclock-master;
frame-master;
port@0 { cpu1_ep: endpoint { remote-endpoint = <&mcpu1_ep>; }; };
port@1 { cpu2_ep: endpoint { remote-endpoint = <&mcpu2_ep>; }; };
};
};
Codec {
ports {
port@0 { codec1_ep: endpoint { remote-endpoint = <&mcodec1_ep>; }; };
port@1 { codec2_ep: endpoint { remote-endpoint = <&mcodec2_ep>; }; };
};
};
************************************
DPCM
************************************
DSP
************
PCM0 <--> * fe0 be0 * <--> DAI0: Codec Headset
PCM1 <--> * fe1 be1 * <--> DAI1: Codec Speakers
PCM2 <--> * fe2 be2 * <--> DAI2: MODEM
PCM3 <--> * fe3 be3 * <--> DAI3: BT
* be4 * <--> DAI4: DMIC
* be5 * <--> DAI5: FM
************
sound {
compatible = "audio-graph-card2";
// indicate routing
routing = "xxx Playback", "xxx Playback",
"xxx Playback", "xxx Playback",
"xxx Playback", "xxx Playback";
// indicate all Front-End, Back-End
links = <&fe0, &fe1, ...,
&be0, &be1, ...>;
dpcm {
// Front-End
ports@0 {
fe0: port@0 { fe0_ep: endpoint { remote-endpoint = <&pcm0_ep>; }; };
fe1: port@1 { fe1_ep: endpoint { remote-endpoint = <&pcm1_ep>; }; };
...
};
// Back-End
ports@1 {
be0: port@0 { be0_ep: endpoint { remote-endpoint = <&dai0_ep>; }; };
be1: port@1 { be1_ep: endpoint { remote-endpoint = <&dai1_ep>; }; };
...
};
};
};
CPU {
ports {
bitclock-master;
frame-master;
port@0 { pcm0_ep: endpoint { remote-endpoint = <&fe0_ep>; }; };
port@1 { pcm1_ep: endpoint { remote-endpoint = <&fe1_ep>; }; };
...
};
};
Codec {
ports {
port@0 { dai0_ep: endpoint { remote-endpoint = <&be0_ep>; }; };
port@1 { dai1_ep: endpoint { remote-endpoint = <&be1_ep>; }; };
...
};
};
************************************
Codec to Codec
************************************
+--+
| |<-- Codec0 <- IN
| |--> Codec1 -> OUT
+--+
sound {
compatible = "audio-graph-card2";
routing = "OUT" ,"DAI1 Playback",
"DAI0 Capture", "IN";
links = <&c2c>;
codec2codec {
ports {
rate = <48000>;
c2c: port@0 { c2cf_ep: endpoint { remote-endpoint = <&codec0_ep>; }; };
port@1 { c2cb_ep: endpoint { remote-endpoint = <&codec1_ep>; }; };
};
};
Codec {
ports {
port@0 {
bitclock-master;
frame-master;
codec0_ep: endpoint { remote-endpoint = <&c2cf_ep>; }; };
port@1 { codec1_ep: endpoint { remote-endpoint = <&c2cb_ep>; }; };
};
};
*/
enum graph_type {
GRAPH_NORMAL,
GRAPH_DPCM,
GRAPH_C2C,
GRAPH_MULTI, /* don't use ! Use this only in __graph_get_type() */
};
#define GRAPH_NODENAME_MULTI "multi"
#define GRAPH_NODENAME_DPCM "dpcm"
#define GRAPH_NODENAME_C2C "codec2codec"
#define port_to_endpoint(port) of_get_child_by_name(port, "endpoint")
static enum graph_type __graph_get_type(struct device_node *lnk)
{
struct device_node *np, *parent_np;
enum graph_type ret;
/*
* target {
* ports {
* => lnk: port@0 { ... };
* port@1 { ... };
* };
* };
*/
np = of_get_parent(lnk);
if (of_node_name_eq(np, "ports")) {
parent_np = of_get_parent(np);
of_node_put(np);
np = parent_np;
}
if (of_node_name_eq(np, GRAPH_NODENAME_MULTI)) {
ret = GRAPH_MULTI;
goto out_put;
}
if (of_node_name_eq(np, GRAPH_NODENAME_DPCM)) {
ret = GRAPH_DPCM;
goto out_put;
}
if (of_node_name_eq(np, GRAPH_NODENAME_C2C)) {
ret = GRAPH_C2C;
goto out_put;
}
ret = GRAPH_NORMAL;
out_put:
of_node_put(np);
return ret;
}
static enum graph_type graph_get_type(struct asoc_simple_priv *priv,
struct device_node *lnk)
{
enum graph_type type = __graph_get_type(lnk);
/* GRAPH_MULTI here means GRAPH_NORMAL */
if (type == GRAPH_MULTI)
type = GRAPH_NORMAL;
#ifdef DEBUG
{
struct device *dev = simple_priv_to_dev(priv);
const char *str = "Normal";
switch (type) {
case GRAPH_DPCM:
if (asoc_graph_is_ports0(lnk))
str = "DPCM Front-End";
else
str = "DPCM Back-End";
break;
case GRAPH_C2C:
str = "Codec2Codec";
break;
default:
break;
}
dev_dbg(dev, "%pOF (%s)", lnk, str);
}
#endif
return type;
}
static int graph_lnk_is_multi(struct device_node *lnk)
{
return __graph_get_type(lnk) == GRAPH_MULTI;
}
static struct device_node *graph_get_next_multi_ep(struct device_node **port)
{
struct device_node *ports = of_get_parent(*port);
struct device_node *ep = NULL;
struct device_node *rep = NULL;
/*
* multi {
* ports {
* => lnk: port@0 { ... };
* port@1 { ep { ... = rep0 } };
* port@2 { ep { ... = rep1 } };
* ...
* };
* };
*
* xxx {
* port@0 { rep0 };
* port@1 { rep1 };
* };
*/
do {
*port = of_get_next_child(ports, *port);
if (!*port)
break;
} while (!of_node_name_eq(*port, "port"));
if (*port) {
ep = port_to_endpoint(*port);
rep = of_graph_get_remote_endpoint(ep);
}
of_node_put(ep);
of_node_put(ports);
return rep;
}
static const struct snd_soc_ops graph_ops = {
.startup = asoc_simple_startup,
.shutdown = asoc_simple_shutdown,
.hw_params = asoc_simple_hw_params,
};
static void graph_parse_convert(struct device_node *ep,
struct simple_dai_props *props)
{
struct device_node *port = of_get_parent(ep);
struct device_node *ports = of_get_parent(port);
struct asoc_simple_data *adata = &props->adata;
if (of_node_name_eq(ports, "ports"))
asoc_simple_parse_convert(ports, NULL, adata);
asoc_simple_parse_convert(port, NULL, adata);
asoc_simple_parse_convert(ep, NULL, adata);
of_node_put(port);
of_node_put(ports);
}
static void graph_parse_mclk_fs(struct device_node *ep,
struct simple_dai_props *props)
{
struct device_node *port = of_get_parent(ep);
struct device_node *ports = of_get_parent(port);
if (of_node_name_eq(ports, "ports"))
of_property_read_u32(ports, "mclk-fs", &props->mclk_fs);
of_property_read_u32(port, "mclk-fs", &props->mclk_fs);
of_property_read_u32(ep, "mclk-fs", &props->mclk_fs);
of_node_put(port);
of_node_put(ports);
}
static int __graph_parse_node(struct asoc_simple_priv *priv,
enum graph_type gtype,
struct device_node *ep,
struct link_info *li,
int is_cpu, int idx)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, li->link);
struct snd_soc_dai_link_component *dlc;
struct asoc_simple_dai *dai;
int ret, is_single_links = 0;
if (is_cpu) {
dlc = asoc_link_to_cpu(dai_link, idx);
dai = simple_props_to_dai_cpu(dai_props, idx);
} else {
dlc = asoc_link_to_codec(dai_link, idx);
dai = simple_props_to_dai_codec(dai_props, idx);
}
graph_parse_mclk_fs(ep, dai_props);
ret = asoc_graph_parse_dai(dev, ep, dlc, &is_single_links);
if (ret < 0)
return ret;
ret = asoc_simple_parse_tdm(ep, dai);
if (ret < 0)
return ret;
ret = asoc_simple_parse_tdm_width_map(dev, ep, dai);
if (ret < 0)
return ret;
ret = asoc_simple_parse_clk(dev, ep, dai, dlc);
if (ret < 0)
return ret;
/*
* set DAI Name
*/
if (!dai_link->name) {
struct snd_soc_dai_link_component *cpus = dlc;
struct snd_soc_dai_link_component *codecs = asoc_link_to_codec(dai_link, idx);
char *cpu_multi = "";
char *codec_multi = "";
if (dai_link->num_cpus > 1)
cpu_multi = "_multi";
if (dai_link->num_codecs > 1)
codec_multi = "_multi";
switch (gtype) {
case GRAPH_NORMAL:
/* run is_cpu only. see audio_graph2_link_normal() */
if (is_cpu)
asoc_simple_set_dailink_name(dev, dai_link, "%s%s-%s%s",
cpus->dai_name, cpu_multi,
codecs->dai_name, codec_multi);
break;
case GRAPH_DPCM:
if (is_cpu)
asoc_simple_set_dailink_name(dev, dai_link, "fe.%pOFP.%s%s",
cpus->of_node, cpus->dai_name, cpu_multi);
else
asoc_simple_set_dailink_name(dev, dai_link, "be.%pOFP.%s%s",
codecs->of_node, codecs->dai_name, codec_multi);
break;
case GRAPH_C2C:
/* run is_cpu only. see audio_graph2_link_c2c() */
if (is_cpu)
asoc_simple_set_dailink_name(dev, dai_link, "c2c.%s%s-%s%s",
cpus->dai_name, cpu_multi,
codecs->dai_name, codec_multi);
break;
default:
break;
}
}
/*
* Check "prefix" from top node
* if DPCM-BE case
*/
if (!is_cpu && gtype == GRAPH_DPCM) {
struct snd_soc_dai_link_component *codecs = asoc_link_to_codec(dai_link, idx);
struct snd_soc_codec_conf *cconf = simple_props_to_codec_conf(dai_props, idx);
struct device_node *rport = of_get_parent(ep);
struct device_node *rports = of_get_parent(rport);
if (of_node_name_eq(rports, "ports"))
snd_soc_of_parse_node_prefix(rports, cconf, codecs->of_node, "prefix");
snd_soc_of_parse_node_prefix(rport, cconf, codecs->of_node, "prefix");
of_node_put(rport);
of_node_put(rports);
}
if (is_cpu) {
struct snd_soc_dai_link_component *cpus = dlc;
struct snd_soc_dai_link_component *platforms = asoc_link_to_platform(dai_link, idx);
asoc_simple_canonicalize_cpu(cpus, is_single_links);
asoc_simple_canonicalize_platform(platforms, cpus);
}
return 0;
}
static int graph_parse_node(struct asoc_simple_priv *priv,
enum graph_type gtype,
struct device_node *port,
struct link_info *li, int is_cpu)
{
struct device_node *ep;
int ret = 0;
if (graph_lnk_is_multi(port)) {
int idx;
of_node_get(port);
for (idx = 0;; idx++) {
ep = graph_get_next_multi_ep(&port);
if (!ep)
break;
ret = __graph_parse_node(priv, gtype, ep,
li, is_cpu, idx);
of_node_put(ep);
if (ret < 0)
break;
}
} else {
/* Single CPU / Codec */
ep = port_to_endpoint(port);
ret = __graph_parse_node(priv, gtype, ep, li, is_cpu, 0);
of_node_put(ep);
}
return ret;
}
static void graph_parse_daifmt(struct device_node *node,
unsigned int *daifmt, unsigned int *bit_frame)
{
unsigned int fmt;
/*
* see also above "daifmt" explanation
* and samples.
*/
/*
* ports {
* (A)
* port {
* (B)
* endpoint {
* (C)
* };
* };
* };
* };
*/
/*
* clock_provider:
*
* It can be judged it is provider
* if (A) or (B) or (C) has bitclock-master / frame-master flag.
*
* use "or"
*/
*bit_frame |= snd_soc_daifmt_parse_clock_provider_as_bitmap(node, NULL);
#define update_daifmt(name) \
if (!(*daifmt & SND_SOC_DAIFMT_##name##_MASK) && \
(fmt & SND_SOC_DAIFMT_##name##_MASK)) \
*daifmt |= fmt & SND_SOC_DAIFMT_##name##_MASK
/*
* format
*
* This function is called by (C) -> (B) -> (A) order.
* Set if applicable part was not yet set.
*/
fmt = snd_soc_daifmt_parse_format(node, NULL);
update_daifmt(FORMAT);
update_daifmt(CLOCK);
update_daifmt(INV);
}
static void graph_link_init(struct asoc_simple_priv *priv,
struct device_node *port,
struct link_info *li,
int is_cpu_node)
{
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct device_node *ep;
struct device_node *ports;
unsigned int daifmt = 0, daiclk = 0;
unsigned int bit_frame = 0;
if (graph_lnk_is_multi(port)) {
of_node_get(port);
ep = graph_get_next_multi_ep(&port);
port = of_get_parent(ep);
} else {
ep = port_to_endpoint(port);
}
ports = of_get_parent(port);
/*
* ports {
* (A)
* port {
* (B)
* endpoint {
* (C)
* };
* };
* };
* };
*/
graph_parse_daifmt(ep, &daifmt, &bit_frame); /* (C) */
graph_parse_daifmt(port, &daifmt, &bit_frame); /* (B) */
if (of_node_name_eq(ports, "ports"))
graph_parse_daifmt(ports, &daifmt, &bit_frame); /* (A) */
/*
* convert bit_frame
* We need to flip clock_provider if it was CPU node,
* because it is Codec base.
*/
daiclk = snd_soc_daifmt_clock_provider_from_bitmap(bit_frame);
if (is_cpu_node)
daiclk = snd_soc_daifmt_clock_provider_flipped(daiclk);
dai_link->dai_fmt = daifmt | daiclk;
dai_link->init = asoc_simple_dai_init;
dai_link->ops = &graph_ops;
if (priv->ops)
dai_link->ops = priv->ops;
}
int audio_graph2_link_normal(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device_node *cpu_port = lnk;
struct device_node *cpu_ep = port_to_endpoint(cpu_port);
struct device_node *codec_port = of_graph_get_remote_port(cpu_ep);
int ret;
/*
* call Codec first.
* see
* __graph_parse_node() :: DAI Naming
*/
ret = graph_parse_node(priv, GRAPH_NORMAL, codec_port, li, 0);
if (ret < 0)
goto err;
/*
* call CPU, and set DAI Name
*/
ret = graph_parse_node(priv, GRAPH_NORMAL, cpu_port, li, 1);
if (ret < 0)
goto err;
graph_link_init(priv, cpu_port, li, 1);
err:
of_node_put(codec_port);
of_node_put(cpu_ep);
return ret;
}
EXPORT_SYMBOL_GPL(audio_graph2_link_normal);
int audio_graph2_link_dpcm(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device_node *ep = port_to_endpoint(lnk);
struct device_node *rep = of_graph_get_remote_endpoint(ep);
struct device_node *rport = of_graph_get_remote_port(ep);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, li->link);
int is_cpu = asoc_graph_is_ports0(lnk);
int ret;
if (is_cpu) {
/*
* dpcm {
* // Front-End
* ports@0 {
* => lnk: port@0 { ep: { ... = rep }; };
* ...
* };
* // Back-End
* ports@0 {
* ...
* };
* };
*
* CPU {
* rports: ports {
* rport: port@0 { rep: { ... = ep } };
* }
* }
*/
/*
* setup CPU here, Codec is already set as dummy.
* see
* asoc_simple_init_priv()
*/
dai_link->dynamic = 1;
dai_link->dpcm_merged_format = 1;
ret = graph_parse_node(priv, GRAPH_DPCM, rport, li, 1);
if (ret)
goto err;
} else {
/*
* dpcm {
* // Front-End
* ports@0 {
* ...
* };
* // Back-End
* ports@0 {
* => lnk: port@0 { ep: { ... = rep; }; };
* ...
* };
* };
*
* Codec {
* rports: ports {
* rport: port@0 { rep: { ... = ep; }; };
* }
* }
*/
/*
* setup Codec here, CPU is already set as dummy.
* see
* asoc_simple_init_priv()
*/
/* BE settings */
dai_link->no_pcm = 1;
dai_link->be_hw_params_fixup = asoc_simple_be_hw_params_fixup;
ret = graph_parse_node(priv, GRAPH_DPCM, rport, li, 0);
if (ret < 0)
goto err;
}
graph_parse_convert(ep, dai_props); /* at node of <dpcm> */
graph_parse_convert(rep, dai_props); /* at node of <CPU/Codec> */
snd_soc_dai_link_set_capabilities(dai_link);
graph_link_init(priv, rport, li, is_cpu);
err:
of_node_put(ep);
of_node_put(rep);
of_node_put(rport);
return ret;
}
EXPORT_SYMBOL_GPL(audio_graph2_link_dpcm);
int audio_graph2_link_c2c(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct device_node *port0, *port1, *ports;
struct device_node *codec0_port, *codec1_port;
struct device_node *ep0, *ep1;
u32 val = 0;
int ret = -EINVAL;
/*
* codec2codec {
* ports {
* rate = <48000>;
* => lnk: port@0 { c2c0_ep: { ... = codec0_ep; }; };
* port@1 { c2c1_ep: { ... = codec1_ep; }; };
* };
* };
*
* Codec {
* ports {
* port@0 { codec0_ep: ... }; };
* port@1 { codec1_ep: ... }; };
* };
* };
*/
of_node_get(lnk);
port0 = lnk;
ports = of_get_parent(port0);
port1 = of_get_next_child(ports, lnk);
/*
* Card2 can use original Codec2Codec settings if DT has.
* It will use default settings if no settings on DT.
* see
* asoc_simple_init_for_codec2codec()
*
* Add more settings here if needed
*/
of_property_read_u32(ports, "rate", &val);
if (val) {
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_pcm_stream *c2c_conf;
c2c_conf = devm_kzalloc(dev, sizeof(*c2c_conf), GFP_KERNEL);
if (!c2c_conf)
goto err1;
c2c_conf->formats = SNDRV_PCM_FMTBIT_S32_LE; /* update ME */
c2c_conf->rates = SNDRV_PCM_RATE_8000_384000;
c2c_conf->rate_min =
c2c_conf->rate_max = val;
c2c_conf->channels_min =
c2c_conf->channels_max = 2; /* update ME */
dai_link->c2c_params = c2c_conf;
dai_link->num_c2c_params = 1;
}
ep0 = port_to_endpoint(port0);
ep1 = port_to_endpoint(port1);
codec0_port = of_graph_get_remote_port(ep0);
codec1_port = of_graph_get_remote_port(ep1);
/*
* call Codec first.
* see
* __graph_parse_node() :: DAI Naming
*/
ret = graph_parse_node(priv, GRAPH_C2C, codec1_port, li, 0);
if (ret < 0)
goto err2;
/*
* call CPU, and set DAI Name
*/
ret = graph_parse_node(priv, GRAPH_C2C, codec0_port, li, 1);
if (ret < 0)
goto err2;
graph_link_init(priv, codec0_port, li, 1);
err2:
of_node_put(ep0);
of_node_put(ep1);
of_node_put(codec0_port);
of_node_put(codec1_port);
err1:
of_node_put(ports);
of_node_put(port0);
of_node_put(port1);
return ret;
}
EXPORT_SYMBOL_GPL(audio_graph2_link_c2c);
static int graph_link(struct asoc_simple_priv *priv,
struct graph2_custom_hooks *hooks,
enum graph_type gtype,
struct device_node *lnk,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
GRAPH2_CUSTOM func = NULL;
int ret = -EINVAL;
switch (gtype) {
case GRAPH_NORMAL:
if (hooks && hooks->custom_normal)
func = hooks->custom_normal;
else
func = audio_graph2_link_normal;
break;
case GRAPH_DPCM:
if (hooks && hooks->custom_dpcm)
func = hooks->custom_dpcm;
else
func = audio_graph2_link_dpcm;
break;
case GRAPH_C2C:
if (hooks && hooks->custom_c2c)
func = hooks->custom_c2c;
else
func = audio_graph2_link_c2c;
break;
default:
break;
}
if (!func) {
dev_err(dev, "non supported gtype (%d)\n", gtype);
goto err;
}
ret = func(priv, lnk, li);
if (ret < 0)
goto err;
li->link++;
err:
return ret;
}
static int graph_counter(struct device_node *lnk)
{
/*
* Multi CPU / Codec
*
* multi {
* ports {
* => lnk: port@0 { ... };
* port@1 { ... };
* port@2 { ... };
* ...
* };
* };
*
* ignore first lnk part
*/
if (graph_lnk_is_multi(lnk))
return of_graph_get_endpoint_count(of_get_parent(lnk)) - 1;
/*
* Single CPU / Codec
*/
else
return 1;
}
static int graph_count_normal(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device_node *cpu_port = lnk;
struct device_node *cpu_ep = port_to_endpoint(cpu_port);
struct device_node *codec_port = of_graph_get_remote_port(cpu_ep);
/*
* CPU {
* => lnk: port { endpoint { .. }; };
* };
*/
/*
* DON'T REMOVE platforms
* see
* simple-card.c :: simple_count_noml()
*/
li->num[li->link].cpus =
li->num[li->link].platforms = graph_counter(cpu_port);
li->num[li->link].codecs = graph_counter(codec_port);
of_node_put(cpu_ep);
of_node_put(codec_port);
return 0;
}
static int graph_count_dpcm(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device_node *ep = port_to_endpoint(lnk);
struct device_node *rport = of_graph_get_remote_port(ep);
/*
* dpcm {
* // Front-End
* ports@0 {
* => lnk: port@0 { endpoint { ... }; };
* ...
* };
* // Back-End
* ports@1 {
* => lnk: port@0 { endpoint { ... }; };
* ...
* };
* };
*/
if (asoc_graph_is_ports0(lnk)) {
/*
* DON'T REMOVE platforms
* see
* simple-card.c :: simple_count_noml()
*/
li->num[li->link].cpus = graph_counter(rport); /* FE */
li->num[li->link].platforms = graph_counter(rport);
} else {
li->num[li->link].codecs = graph_counter(rport); /* BE */
}
of_node_put(ep);
of_node_put(rport);
return 0;
}
static int graph_count_c2c(struct asoc_simple_priv *priv,
struct device_node *lnk,
struct link_info *li)
{
struct device_node *ports = of_get_parent(lnk);
struct device_node *port0 = lnk;
struct device_node *port1 = of_get_next_child(ports, lnk);
struct device_node *ep0 = port_to_endpoint(port0);
struct device_node *ep1 = port_to_endpoint(port1);
struct device_node *codec0 = of_graph_get_remote_port(ep0);
struct device_node *codec1 = of_graph_get_remote_port(ep1);
of_node_get(lnk);
/*
* codec2codec {
* ports {
* => lnk: port@0 { endpoint { ... }; };
* port@1 { endpoint { ... }; };
* };
* };
*/
/*
* DON'T REMOVE platforms
* see
* simple-card.c :: simple_count_noml()
*/
li->num[li->link].cpus =
li->num[li->link].platforms = graph_counter(codec0);
li->num[li->link].codecs = graph_counter(codec1);
of_node_put(ports);
of_node_put(port1);
of_node_put(ep0);
of_node_put(ep1);
of_node_put(codec0);
of_node_put(codec1);
return 0;
}
static int graph_count(struct asoc_simple_priv *priv,
struct graph2_custom_hooks *hooks,
enum graph_type gtype,
struct device_node *lnk,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
GRAPH2_CUSTOM func = NULL;
int ret = -EINVAL;
if (li->link >= SNDRV_MAX_LINKS) {
dev_err(dev, "too many links\n");
return ret;
}
switch (gtype) {
case GRAPH_NORMAL:
func = graph_count_normal;
break;
case GRAPH_DPCM:
func = graph_count_dpcm;
break;
case GRAPH_C2C:
func = graph_count_c2c;
break;
default:
break;
}
if (!func) {
dev_err(dev, "non supported gtype (%d)\n", gtype);
goto err;
}
ret = func(priv, lnk, li);
if (ret < 0)
goto err;
li->link++;
err:
return ret;
}
static int graph_for_each_link(struct asoc_simple_priv *priv,
struct graph2_custom_hooks *hooks,
struct link_info *li,
int (*func)(struct asoc_simple_priv *priv,
struct graph2_custom_hooks *hooks,
enum graph_type gtype,
struct device_node *lnk,
struct link_info *li))
{
struct of_phandle_iterator it;
struct device *dev = simple_priv_to_dev(priv);
struct device_node *node = dev->of_node;
struct device_node *lnk;
enum graph_type gtype;
int rc, ret;
/* loop for all listed CPU port */
of_for_each_phandle(&it, rc, node, "links", NULL, 0) {
lnk = it.node;
gtype = graph_get_type(priv, lnk);
ret = func(priv, hooks, gtype, lnk, li);
if (ret < 0)
return ret;
}
return 0;
}
int audio_graph2_parse_of(struct asoc_simple_priv *priv, struct device *dev,
struct graph2_custom_hooks *hooks)
{
struct snd_soc_card *card = simple_priv_to_card(priv);
struct link_info *li;
int ret;
li = devm_kzalloc(dev, sizeof(*li), GFP_KERNEL);
if (!li)
return -ENOMEM;
card->probe = asoc_graph_card_probe;
card->owner = THIS_MODULE;
card->dev = dev;
if ((hooks) && (hooks)->hook_pre) {
ret = (hooks)->hook_pre(priv);
if (ret < 0)
goto err;
}
ret = graph_for_each_link(priv, hooks, li, graph_count);
if (!li->link)
ret = -EINVAL;
if (ret < 0)
goto err;
ret = asoc_simple_init_priv(priv, li);
if (ret < 0)
goto err;
priv->pa_gpio = devm_gpiod_get_optional(dev, "pa", GPIOD_OUT_LOW);
if (IS_ERR(priv->pa_gpio)) {
ret = PTR_ERR(priv->pa_gpio);
dev_err(dev, "failed to get amplifier gpio: %d\n", ret);
goto err;
}
ret = asoc_simple_parse_widgets(card, NULL);
if (ret < 0)
goto err;
ret = asoc_simple_parse_routing(card, NULL);
if (ret < 0)
goto err;
memset(li, 0, sizeof(*li));
ret = graph_for_each_link(priv, hooks, li, graph_link);
if (ret < 0)
goto err;
ret = asoc_simple_parse_card_name(card, NULL);
if (ret < 0)
goto err;
snd_soc_card_set_drvdata(card, priv);
if ((hooks) && (hooks)->hook_post) {
ret = (hooks)->hook_post(priv);
if (ret < 0)
goto err;
}
asoc_simple_debug_info(priv);
ret = devm_snd_soc_register_card(dev, card);
err:
devm_kfree(dev, li);
if (ret < 0)
dev_err_probe(dev, ret, "parse error\n");
return ret;
}
EXPORT_SYMBOL_GPL(audio_graph2_parse_of);
static int graph_probe(struct platform_device *pdev)
{
struct asoc_simple_priv *priv;
struct device *dev = &pdev->dev;
/* Allocate the private data and the DAI link array */
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
return audio_graph2_parse_of(priv, dev, NULL);
}
static const struct of_device_id graph_of_match[] = {
{ .compatible = "audio-graph-card2", },
{},
};
MODULE_DEVICE_TABLE(of, graph_of_match);
static struct platform_driver graph_card = {
.driver = {
.name = "asoc-audio-graph-card2",
.pm = &snd_soc_pm_ops,
.of_match_table = graph_of_match,
},
.probe = graph_probe,
.remove = asoc_simple_remove,
};
module_platform_driver(graph_card);
MODULE_ALIAS("platform:asoc-audio-graph-card2");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ASoC Audio Graph Card2");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
| linux-master | sound/soc/generic/audio-graph-card2.c |
// SPDX-License-Identifier: GPL-2.0
//
// simple-card-utils.c
//
// Copyright (c) 2016 Kuninori Morimoto <[email protected]>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/simple_card_utils.h>
static void asoc_simple_fixup_sample_fmt(struct asoc_simple_data *data,
struct snd_pcm_hw_params *params)
{
int i;
struct snd_mask *mask = hw_param_mask(params,
SNDRV_PCM_HW_PARAM_FORMAT);
struct {
char *fmt;
u32 val;
} of_sample_fmt_table[] = {
{ "s8", SNDRV_PCM_FORMAT_S8},
{ "s16_le", SNDRV_PCM_FORMAT_S16_LE},
{ "s24_le", SNDRV_PCM_FORMAT_S24_LE},
{ "s24_3le", SNDRV_PCM_FORMAT_S24_3LE},
{ "s32_le", SNDRV_PCM_FORMAT_S32_LE},
};
for (i = 0; i < ARRAY_SIZE(of_sample_fmt_table); i++) {
if (!strcmp(data->convert_sample_format,
of_sample_fmt_table[i].fmt)) {
snd_mask_none(mask);
snd_mask_set(mask, of_sample_fmt_table[i].val);
break;
}
}
}
void asoc_simple_parse_convert(struct device_node *np,
char *prefix,
struct asoc_simple_data *data)
{
char prop[128];
if (!prefix)
prefix = "";
/* sampling rate convert */
snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-rate");
of_property_read_u32(np, prop, &data->convert_rate);
/* channels transfer */
snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-channels");
of_property_read_u32(np, prop, &data->convert_channels);
/* convert sample format */
snprintf(prop, sizeof(prop), "%s%s", prefix, "convert-sample-format");
of_property_read_string(np, prop, &data->convert_sample_format);
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_convert);
/**
* asoc_simple_is_convert_required() - Query if HW param conversion was requested
* @data: Link data.
*
* Returns true if any HW param conversion was requested for this DAI link with
* any "convert-xxx" properties.
*/
bool asoc_simple_is_convert_required(const struct asoc_simple_data *data)
{
return data->convert_rate ||
data->convert_channels ||
data->convert_sample_format;
}
EXPORT_SYMBOL_GPL(asoc_simple_is_convert_required);
int asoc_simple_parse_daifmt(struct device *dev,
struct device_node *node,
struct device_node *codec,
char *prefix,
unsigned int *retfmt)
{
struct device_node *bitclkmaster = NULL;
struct device_node *framemaster = NULL;
unsigned int daifmt;
daifmt = snd_soc_daifmt_parse_format(node, prefix);
snd_soc_daifmt_parse_clock_provider_as_phandle(node, prefix, &bitclkmaster, &framemaster);
if (!bitclkmaster && !framemaster) {
/*
* No dai-link level and master setting was not found from
* sound node level, revert back to legacy DT parsing and
* take the settings from codec node.
*/
dev_dbg(dev, "Revert to legacy daifmt parsing\n");
daifmt |= snd_soc_daifmt_parse_clock_provider_as_flag(codec, NULL);
} else {
daifmt |= snd_soc_daifmt_clock_provider_from_bitmap(
((codec == bitclkmaster) << 4) | (codec == framemaster));
}
of_node_put(bitclkmaster);
of_node_put(framemaster);
*retfmt = daifmt;
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_daifmt);
int asoc_simple_parse_tdm_width_map(struct device *dev, struct device_node *np,
struct asoc_simple_dai *dai)
{
u32 *array_values, *p;
int n, i, ret;
if (!of_property_read_bool(np, "dai-tdm-slot-width-map"))
return 0;
n = of_property_count_elems_of_size(np, "dai-tdm-slot-width-map", sizeof(u32));
if (n % 3) {
dev_err(dev, "Invalid number of cells for dai-tdm-slot-width-map\n");
return -EINVAL;
}
dai->tdm_width_map = devm_kcalloc(dev, n, sizeof(*dai->tdm_width_map), GFP_KERNEL);
if (!dai->tdm_width_map)
return -ENOMEM;
array_values = kcalloc(n, sizeof(*array_values), GFP_KERNEL);
if (!array_values)
return -ENOMEM;
ret = of_property_read_u32_array(np, "dai-tdm-slot-width-map", array_values, n);
if (ret < 0) {
dev_err(dev, "Could not read dai-tdm-slot-width-map: %d\n", ret);
goto out;
}
p = array_values;
for (i = 0; i < n / 3; ++i) {
dai->tdm_width_map[i].sample_bits = *p++;
dai->tdm_width_map[i].slot_width = *p++;
dai->tdm_width_map[i].slot_count = *p++;
}
dai->n_tdm_widths = i;
ret = 0;
out:
kfree(array_values);
return ret;
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_tdm_width_map);
int asoc_simple_set_dailink_name(struct device *dev,
struct snd_soc_dai_link *dai_link,
const char *fmt, ...)
{
va_list ap;
char *name = NULL;
int ret = -ENOMEM;
va_start(ap, fmt);
name = devm_kvasprintf(dev, GFP_KERNEL, fmt, ap);
va_end(ap);
if (name) {
ret = 0;
dai_link->name = name;
dai_link->stream_name = name;
}
return ret;
}
EXPORT_SYMBOL_GPL(asoc_simple_set_dailink_name);
int asoc_simple_parse_card_name(struct snd_soc_card *card,
char *prefix)
{
int ret;
if (!prefix)
prefix = "";
/* Parse the card name from DT */
ret = snd_soc_of_parse_card_name(card, "label");
if (ret < 0 || !card->name) {
char prop[128];
snprintf(prop, sizeof(prop), "%sname", prefix);
ret = snd_soc_of_parse_card_name(card, prop);
if (ret < 0)
return ret;
}
if (!card->name && card->dai_link)
card->name = card->dai_link->name;
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_card_name);
static int asoc_simple_clk_enable(struct asoc_simple_dai *dai)
{
if (dai)
return clk_prepare_enable(dai->clk);
return 0;
}
static void asoc_simple_clk_disable(struct asoc_simple_dai *dai)
{
if (dai)
clk_disable_unprepare(dai->clk);
}
int asoc_simple_parse_clk(struct device *dev,
struct device_node *node,
struct asoc_simple_dai *simple_dai,
struct snd_soc_dai_link_component *dlc)
{
struct clk *clk;
u32 val;
/*
* Parse dai->sysclk come from "clocks = <&xxx>"
* (if system has common clock)
* or "system-clock-frequency = <xxx>"
* or device's module clock.
*/
clk = devm_get_clk_from_child(dev, node, NULL);
simple_dai->clk_fixed = of_property_read_bool(
node, "system-clock-fixed");
if (!IS_ERR(clk)) {
simple_dai->sysclk = clk_get_rate(clk);
simple_dai->clk = clk;
} else if (!of_property_read_u32(node, "system-clock-frequency", &val)) {
simple_dai->sysclk = val;
simple_dai->clk_fixed = true;
} else {
clk = devm_get_clk_from_child(dev, dlc->of_node, NULL);
if (!IS_ERR(clk))
simple_dai->sysclk = clk_get_rate(clk);
}
if (of_property_read_bool(node, "system-clock-direction-out"))
simple_dai->clk_direction = SND_SOC_CLOCK_OUT;
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_clk);
static int asoc_simple_check_fixed_sysclk(struct device *dev,
struct asoc_simple_dai *dai,
unsigned int *fixed_sysclk)
{
if (dai->clk_fixed) {
if (*fixed_sysclk && *fixed_sysclk != dai->sysclk) {
dev_err(dev, "inconsistent fixed sysclk rates (%u vs %u)\n",
*fixed_sysclk, dai->sysclk);
return -EINVAL;
}
*fixed_sysclk = dai->sysclk;
}
return 0;
}
int asoc_simple_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct simple_dai_props *props = simple_priv_to_props(priv, rtd->num);
struct asoc_simple_dai *dai;
unsigned int fixed_sysclk = 0;
int i1, i2, i;
int ret;
for_each_prop_dai_cpu(props, i1, dai) {
ret = asoc_simple_clk_enable(dai);
if (ret)
goto cpu_err;
ret = asoc_simple_check_fixed_sysclk(rtd->dev, dai, &fixed_sysclk);
if (ret)
goto cpu_err;
}
for_each_prop_dai_codec(props, i2, dai) {
ret = asoc_simple_clk_enable(dai);
if (ret)
goto codec_err;
ret = asoc_simple_check_fixed_sysclk(rtd->dev, dai, &fixed_sysclk);
if (ret)
goto codec_err;
}
if (fixed_sysclk && props->mclk_fs) {
unsigned int fixed_rate = fixed_sysclk / props->mclk_fs;
if (fixed_sysclk % props->mclk_fs) {
dev_err(rtd->dev, "fixed sysclk %u not divisible by mclk_fs %u\n",
fixed_sysclk, props->mclk_fs);
return -EINVAL;
}
ret = snd_pcm_hw_constraint_minmax(substream->runtime, SNDRV_PCM_HW_PARAM_RATE,
fixed_rate, fixed_rate);
if (ret < 0)
goto codec_err;
}
return 0;
codec_err:
for_each_prop_dai_codec(props, i, dai) {
if (i >= i2)
break;
asoc_simple_clk_disable(dai);
}
cpu_err:
for_each_prop_dai_cpu(props, i, dai) {
if (i >= i1)
break;
asoc_simple_clk_disable(dai);
}
return ret;
}
EXPORT_SYMBOL_GPL(asoc_simple_startup);
void asoc_simple_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct simple_dai_props *props = simple_priv_to_props(priv, rtd->num);
struct asoc_simple_dai *dai;
int i;
for_each_prop_dai_cpu(props, i, dai) {
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, i);
if (props->mclk_fs && !dai->clk_fixed && !snd_soc_dai_active(cpu_dai))
snd_soc_dai_set_sysclk(cpu_dai,
0, 0, SND_SOC_CLOCK_OUT);
asoc_simple_clk_disable(dai);
}
for_each_prop_dai_codec(props, i, dai) {
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, i);
if (props->mclk_fs && !dai->clk_fixed && !snd_soc_dai_active(codec_dai))
snd_soc_dai_set_sysclk(codec_dai,
0, 0, SND_SOC_CLOCK_IN);
asoc_simple_clk_disable(dai);
}
}
EXPORT_SYMBOL_GPL(asoc_simple_shutdown);
static int asoc_simple_set_clk_rate(struct device *dev,
struct asoc_simple_dai *simple_dai,
unsigned long rate)
{
if (!simple_dai)
return 0;
if (simple_dai->clk_fixed && rate != simple_dai->sysclk) {
dev_err(dev, "dai %s invalid clock rate %lu\n", simple_dai->name, rate);
return -EINVAL;
}
if (!simple_dai->clk)
return 0;
if (clk_get_rate(simple_dai->clk) == rate)
return 0;
return clk_set_rate(simple_dai->clk, rate);
}
static int asoc_simple_set_tdm(struct snd_soc_dai *dai,
struct asoc_simple_dai *simple_dai,
struct snd_pcm_hw_params *params)
{
int sample_bits = params_width(params);
int slot_width, slot_count;
int i, ret;
if (!simple_dai || !simple_dai->tdm_width_map)
return 0;
slot_width = simple_dai->slot_width;
slot_count = simple_dai->slots;
if (slot_width == 0)
slot_width = sample_bits;
for (i = 0; i < simple_dai->n_tdm_widths; ++i) {
if (simple_dai->tdm_width_map[i].sample_bits == sample_bits) {
slot_width = simple_dai->tdm_width_map[i].slot_width;
slot_count = simple_dai->tdm_width_map[i].slot_count;
break;
}
}
ret = snd_soc_dai_set_tdm_slot(dai,
simple_dai->tx_slot_mask,
simple_dai->rx_slot_mask,
slot_count,
slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(dai->dev, "simple-card: set_tdm_slot error: %d\n", ret);
return ret;
}
return 0;
}
int asoc_simple_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct asoc_simple_dai *pdai;
struct snd_soc_dai *sdai;
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct simple_dai_props *props = simple_priv_to_props(priv, rtd->num);
unsigned int mclk, mclk_fs = 0;
int i, ret;
if (props->mclk_fs)
mclk_fs = props->mclk_fs;
if (mclk_fs) {
struct snd_soc_component *component;
mclk = params_rate(params) * mclk_fs;
for_each_prop_dai_codec(props, i, pdai) {
ret = asoc_simple_set_clk_rate(rtd->dev, pdai, mclk);
if (ret < 0)
return ret;
}
for_each_prop_dai_cpu(props, i, pdai) {
ret = asoc_simple_set_clk_rate(rtd->dev, pdai, mclk);
if (ret < 0)
return ret;
}
/* Ensure sysclk is set on all components in case any
* (such as platform components) are missed by calls to
* snd_soc_dai_set_sysclk.
*/
for_each_rtd_components(rtd, i, component) {
ret = snd_soc_component_set_sysclk(component, 0, 0,
mclk, SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP)
return ret;
}
for_each_rtd_codec_dais(rtd, i, sdai) {
ret = snd_soc_dai_set_sysclk(sdai, 0, mclk, SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP)
return ret;
}
for_each_rtd_cpu_dais(rtd, i, sdai) {
ret = snd_soc_dai_set_sysclk(sdai, 0, mclk, SND_SOC_CLOCK_OUT);
if (ret && ret != -ENOTSUPP)
return ret;
}
}
for_each_prop_dai_codec(props, i, pdai) {
sdai = asoc_rtd_to_codec(rtd, i);
ret = asoc_simple_set_tdm(sdai, pdai, params);
if (ret < 0)
return ret;
}
for_each_prop_dai_cpu(props, i, pdai) {
sdai = asoc_rtd_to_cpu(rtd, i);
ret = asoc_simple_set_tdm(sdai, pdai, params);
if (ret < 0)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_hw_params);
int asoc_simple_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, rtd->num);
struct asoc_simple_data *data = &dai_props->adata;
struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
if (data->convert_rate)
rate->min =
rate->max = data->convert_rate;
if (data->convert_channels)
channels->min =
channels->max = data->convert_channels;
if (data->convert_sample_format)
asoc_simple_fixup_sample_fmt(data, params);
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_be_hw_params_fixup);
static int asoc_simple_init_dai(struct snd_soc_dai *dai,
struct asoc_simple_dai *simple_dai)
{
int ret;
if (!simple_dai)
return 0;
if (simple_dai->sysclk) {
ret = snd_soc_dai_set_sysclk(dai, 0, simple_dai->sysclk,
simple_dai->clk_direction);
if (ret && ret != -ENOTSUPP) {
dev_err(dai->dev, "simple-card: set_sysclk error\n");
return ret;
}
}
if (simple_dai->slots) {
ret = snd_soc_dai_set_tdm_slot(dai,
simple_dai->tx_slot_mask,
simple_dai->rx_slot_mask,
simple_dai->slots,
simple_dai->slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(dai->dev, "simple-card: set_tdm_slot error\n");
return ret;
}
}
return 0;
}
static inline int asoc_simple_component_is_codec(struct snd_soc_component *component)
{
return component->driver->endianness;
}
static int asoc_simple_init_for_codec2codec(struct snd_soc_pcm_runtime *rtd,
struct simple_dai_props *dai_props)
{
struct snd_soc_dai_link *dai_link = rtd->dai_link;
struct snd_soc_component *component;
struct snd_soc_pcm_stream *c2c_params;
struct snd_pcm_hardware hw;
int i, ret, stream;
/* Do nothing if it already has Codec2Codec settings */
if (dai_link->c2c_params)
return 0;
/* Do nothing if it was DPCM :: BE */
if (dai_link->no_pcm)
return 0;
/* Only Codecs */
for_each_rtd_components(rtd, i, component) {
if (!asoc_simple_component_is_codec(component))
return 0;
}
/* Assumes the capabilities are the same for all supported streams */
for_each_pcm_streams(stream) {
ret = snd_soc_runtime_calc_hw(rtd, &hw, stream);
if (ret == 0)
break;
}
if (ret < 0) {
dev_err(rtd->dev, "simple-card: no valid dai_link params\n");
return ret;
}
c2c_params = devm_kzalloc(rtd->dev, sizeof(*c2c_params), GFP_KERNEL);
if (!c2c_params)
return -ENOMEM;
c2c_params->formats = hw.formats;
c2c_params->rates = hw.rates;
c2c_params->rate_min = hw.rate_min;
c2c_params->rate_max = hw.rate_max;
c2c_params->channels_min = hw.channels_min;
c2c_params->channels_max = hw.channels_max;
dai_link->c2c_params = c2c_params;
dai_link->num_c2c_params = 1;
return 0;
}
int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct simple_dai_props *props = simple_priv_to_props(priv, rtd->num);
struct asoc_simple_dai *dai;
int i, ret;
for_each_prop_dai_codec(props, i, dai) {
ret = asoc_simple_init_dai(asoc_rtd_to_codec(rtd, i), dai);
if (ret < 0)
return ret;
}
for_each_prop_dai_cpu(props, i, dai) {
ret = asoc_simple_init_dai(asoc_rtd_to_cpu(rtd, i), dai);
if (ret < 0)
return ret;
}
ret = asoc_simple_init_for_codec2codec(rtd, props);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_dai_init);
void asoc_simple_canonicalize_platform(struct snd_soc_dai_link_component *platforms,
struct snd_soc_dai_link_component *cpus)
{
/*
* Assumes Platform == CPU
*
* Some CPU might be using soc-generic-dmaengine-pcm. This means CPU and Platform
* are different Component, but are sharing same component->dev.
*
* Let's assume Platform is same as CPU if it doesn't identify Platform on DT.
* see
* simple-card.c :: simple_count_noml()
*/
if (!platforms->of_node)
snd_soc_dlc_use_cpu_as_platform(platforms, cpus);
}
EXPORT_SYMBOL_GPL(asoc_simple_canonicalize_platform);
void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link_component *cpus,
int is_single_links)
{
/*
* In soc_bind_dai_link() will check cpu name after
* of_node matching if dai_link has cpu_dai_name.
* but, it will never match if name was created by
* fmt_single_name() remove cpu_dai_name if cpu_args
* was 0. See:
* fmt_single_name()
* fmt_multiple_name()
*/
if (is_single_links)
cpus->dai_name = NULL;
}
EXPORT_SYMBOL_GPL(asoc_simple_canonicalize_cpu);
void asoc_simple_clean_reference(struct snd_soc_card *card)
{
struct snd_soc_dai_link *dai_link;
struct snd_soc_dai_link_component *cpu;
struct snd_soc_dai_link_component *codec;
int i, j;
for_each_card_prelinks(card, i, dai_link) {
for_each_link_cpus(dai_link, j, cpu)
of_node_put(cpu->of_node);
for_each_link_codecs(dai_link, j, codec)
of_node_put(codec->of_node);
}
}
EXPORT_SYMBOL_GPL(asoc_simple_clean_reference);
int asoc_simple_parse_routing(struct snd_soc_card *card,
char *prefix)
{
struct device_node *node = card->dev->of_node;
char prop[128];
if (!prefix)
prefix = "";
snprintf(prop, sizeof(prop), "%s%s", prefix, "routing");
if (!of_property_read_bool(node, prop))
return 0;
return snd_soc_of_parse_audio_routing(card, prop);
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_routing);
int asoc_simple_parse_widgets(struct snd_soc_card *card,
char *prefix)
{
struct device_node *node = card->dev->of_node;
char prop[128];
if (!prefix)
prefix = "";
snprintf(prop, sizeof(prop), "%s%s", prefix, "widgets");
if (of_property_read_bool(node, prop))
return snd_soc_of_parse_audio_simple_widgets(card, prop);
/* no widgets is not error */
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_widgets);
int asoc_simple_parse_pin_switches(struct snd_soc_card *card,
char *prefix)
{
char prop[128];
if (!prefix)
prefix = "";
snprintf(prop, sizeof(prop), "%s%s", prefix, "pin-switches");
return snd_soc_of_parse_pin_switches(card, prop);
}
EXPORT_SYMBOL_GPL(asoc_simple_parse_pin_switches);
int asoc_simple_init_jack(struct snd_soc_card *card,
struct asoc_simple_jack *sjack,
int is_hp, char *prefix,
char *pin)
{
struct device *dev = card->dev;
struct gpio_desc *desc;
char prop[128];
char *pin_name;
char *gpio_name;
int mask;
int error;
if (!prefix)
prefix = "";
sjack->gpio.gpio = -ENOENT;
if (is_hp) {
snprintf(prop, sizeof(prop), "%shp-det", prefix);
pin_name = pin ? pin : "Headphones";
gpio_name = "Headphone detection";
mask = SND_JACK_HEADPHONE;
} else {
snprintf(prop, sizeof(prop), "%smic-det", prefix);
pin_name = pin ? pin : "Mic Jack";
gpio_name = "Mic detection";
mask = SND_JACK_MICROPHONE;
}
desc = gpiod_get_optional(dev, prop, GPIOD_IN);
error = PTR_ERR_OR_ZERO(desc);
if (error)
return error;
if (desc) {
error = gpiod_set_consumer_name(desc, gpio_name);
if (error)
return error;
sjack->pin.pin = pin_name;
sjack->pin.mask = mask;
sjack->gpio.name = gpio_name;
sjack->gpio.report = mask;
sjack->gpio.desc = desc;
sjack->gpio.debounce_time = 150;
snd_soc_card_jack_new_pins(card, pin_name, mask, &sjack->jack,
&sjack->pin, 1);
snd_soc_jack_add_gpios(&sjack->jack, 1, &sjack->gpio);
}
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_init_jack);
int asoc_simple_init_aux_jacks(struct asoc_simple_priv *priv, char *prefix)
{
struct snd_soc_card *card = simple_priv_to_card(priv);
struct snd_soc_component *component;
int found_jack_index = 0;
int type = 0;
int num = 0;
int ret;
if (priv->aux_jacks)
return 0;
for_each_card_auxs(card, component) {
type = snd_soc_component_get_jack_type(component);
if (type > 0)
num++;
}
if (num < 1)
return 0;
priv->aux_jacks = devm_kcalloc(card->dev, num,
sizeof(struct snd_soc_jack), GFP_KERNEL);
if (!priv->aux_jacks)
return -ENOMEM;
for_each_card_auxs(card, component) {
char id[128];
struct snd_soc_jack *jack;
if (found_jack_index >= num)
break;
type = snd_soc_component_get_jack_type(component);
if (type <= 0)
continue;
/* create jack */
jack = &(priv->aux_jacks[found_jack_index++]);
snprintf(id, sizeof(id), "%s-jack", component->name);
ret = snd_soc_card_jack_new(card, id, type, jack);
if (ret)
continue;
(void)snd_soc_component_set_jack(component, jack, NULL);
}
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_init_aux_jacks);
int asoc_simple_init_priv(struct asoc_simple_priv *priv,
struct link_info *li)
{
struct snd_soc_card *card = simple_priv_to_card(priv);
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link;
struct simple_dai_props *dai_props;
struct asoc_simple_dai *dais;
struct snd_soc_dai_link_component *dlcs;
struct snd_soc_codec_conf *cconf = NULL;
int i, dai_num = 0, dlc_num = 0, cnf_num = 0;
dai_props = devm_kcalloc(dev, li->link, sizeof(*dai_props), GFP_KERNEL);
dai_link = devm_kcalloc(dev, li->link, sizeof(*dai_link), GFP_KERNEL);
if (!dai_props || !dai_link)
return -ENOMEM;
/*
* dais (= CPU+Codec)
* dlcs (= CPU+Codec+Platform)
*/
for (i = 0; i < li->link; i++) {
int cc = li->num[i].cpus + li->num[i].codecs;
dai_num += cc;
dlc_num += cc + li->num[i].platforms;
if (!li->num[i].cpus)
cnf_num += li->num[i].codecs;
}
dais = devm_kcalloc(dev, dai_num, sizeof(*dais), GFP_KERNEL);
dlcs = devm_kcalloc(dev, dlc_num, sizeof(*dlcs), GFP_KERNEL);
if (!dais || !dlcs)
return -ENOMEM;
if (cnf_num) {
cconf = devm_kcalloc(dev, cnf_num, sizeof(*cconf), GFP_KERNEL);
if (!cconf)
return -ENOMEM;
}
dev_dbg(dev, "link %d, dais %d, ccnf %d\n",
li->link, dai_num, cnf_num);
priv->dai_props = dai_props;
priv->dai_link = dai_link;
priv->dais = dais;
priv->dlcs = dlcs;
priv->codec_conf = cconf;
card->dai_link = priv->dai_link;
card->num_links = li->link;
card->codec_conf = cconf;
card->num_configs = cnf_num;
for (i = 0; i < li->link; i++) {
if (li->num[i].cpus) {
/* Normal CPU */
dai_link[i].cpus = dlcs;
dai_props[i].num.cpus =
dai_link[i].num_cpus = li->num[i].cpus;
dai_props[i].cpu_dai = dais;
dlcs += li->num[i].cpus;
dais += li->num[i].cpus;
} else {
/* DPCM Be's CPU = dummy */
dai_link[i].cpus = &asoc_dummy_dlc;
dai_props[i].num.cpus =
dai_link[i].num_cpus = 1;
}
if (li->num[i].codecs) {
/* Normal Codec */
dai_link[i].codecs = dlcs;
dai_props[i].num.codecs =
dai_link[i].num_codecs = li->num[i].codecs;
dai_props[i].codec_dai = dais;
dlcs += li->num[i].codecs;
dais += li->num[i].codecs;
if (!li->num[i].cpus) {
/* DPCM Be's Codec */
dai_props[i].codec_conf = cconf;
cconf += li->num[i].codecs;
}
} else {
/* DPCM Fe's Codec = dummy */
dai_link[i].codecs = &asoc_dummy_dlc;
dai_props[i].num.codecs =
dai_link[i].num_codecs = 1;
}
if (li->num[i].platforms) {
/* Have Platform */
dai_link[i].platforms = dlcs;
dai_props[i].num.platforms =
dai_link[i].num_platforms = li->num[i].platforms;
dlcs += li->num[i].platforms;
} else {
/* Doesn't have Platform */
dai_link[i].platforms = NULL;
dai_props[i].num.platforms =
dai_link[i].num_platforms = 0;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_init_priv);
int asoc_simple_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
asoc_simple_clean_reference(card);
return 0;
}
EXPORT_SYMBOL_GPL(asoc_simple_remove);
int asoc_graph_card_probe(struct snd_soc_card *card)
{
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(card);
int ret;
ret = asoc_simple_init_hp(card, &priv->hp_jack, NULL);
if (ret < 0)
return ret;
ret = asoc_simple_init_mic(card, &priv->mic_jack, NULL);
if (ret < 0)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(asoc_graph_card_probe);
int asoc_graph_is_ports0(struct device_node *np)
{
struct device_node *port, *ports, *ports0, *top;
int ret;
/* np is "endpoint" or "port" */
if (of_node_name_eq(np, "endpoint")) {
port = of_get_parent(np);
} else {
port = np;
of_node_get(port);
}
ports = of_get_parent(port);
top = of_get_parent(ports);
ports0 = of_get_child_by_name(top, "ports");
ret = ports0 == ports;
of_node_put(port);
of_node_put(ports);
of_node_put(ports0);
of_node_put(top);
return ret;
}
EXPORT_SYMBOL_GPL(asoc_graph_is_ports0);
static int graph_get_dai_id(struct device_node *ep)
{
struct device_node *node;
struct device_node *endpoint;
struct of_endpoint info;
int i, id;
int ret;
/* use driver specified DAI ID if exist */
ret = snd_soc_get_dai_id(ep);
if (ret != -ENOTSUPP)
return ret;
/* use endpoint/port reg if exist */
ret = of_graph_parse_endpoint(ep, &info);
if (ret == 0) {
/*
* Because it will count port/endpoint if it doesn't have "reg".
* But, we can't judge whether it has "no reg", or "reg = <0>"
* only of_graph_parse_endpoint().
* We need to check "reg" property
*/
if (of_property_present(ep, "reg"))
return info.id;
node = of_get_parent(ep);
ret = of_property_present(node, "reg");
of_node_put(node);
if (ret)
return info.port;
}
node = of_graph_get_port_parent(ep);
/*
* Non HDMI sound case, counting port/endpoint on its DT
* is enough. Let's count it.
*/
i = 0;
id = -1;
for_each_endpoint_of_node(node, endpoint) {
if (endpoint == ep)
id = i;
i++;
}
of_node_put(node);
if (id < 0)
return -ENODEV;
return id;
}
int asoc_graph_parse_dai(struct device *dev, struct device_node *ep,
struct snd_soc_dai_link_component *dlc, int *is_single_link)
{
struct device_node *node;
struct of_phandle_args args = {};
struct snd_soc_dai *dai;
int ret;
if (!ep)
return 0;
node = of_graph_get_port_parent(ep);
/*
* Try to find from DAI node
*/
args.np = ep;
dai = snd_soc_get_dai_via_args(&args);
if (dai) {
dlc->dai_name = snd_soc_dai_name_get(dai);
dlc->dai_args = snd_soc_copy_dai_args(dev, &args);
if (!dlc->dai_args)
return -ENOMEM;
goto parse_dai_end;
}
/* Get dai->name */
args.np = node;
args.args[0] = graph_get_dai_id(ep);
args.args_count = (of_graph_get_endpoint_count(node) > 1);
/*
* FIXME
*
* Here, dlc->dai_name is pointer to CPU/Codec DAI name.
* If user unbinded CPU or Codec driver, but not for Sound Card,
* dlc->dai_name is keeping unbinded CPU or Codec
* driver's pointer.
*
* If user re-bind CPU or Codec driver again, ALSA SoC will try
* to rebind Card via snd_soc_try_rebind_card(), but because of
* above reason, it might can't bind Sound Card.
* Because Sound Card is pointing to released dai_name pointer.
*
* To avoid this rebind Card issue,
* 1) It needs to alloc memory to keep dai_name eventhough
* CPU or Codec driver was unbinded, or
* 2) user need to rebind Sound Card everytime
* if he unbinded CPU or Codec.
*/
ret = snd_soc_get_dlc(&args, dlc);
if (ret < 0) {
of_node_put(node);
return ret;
}
parse_dai_end:
if (is_single_link)
*is_single_link = of_graph_get_endpoint_count(node) == 1;
return 0;
}
EXPORT_SYMBOL_GPL(asoc_graph_parse_dai);
/* Module information */
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC Simple Card Utils");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/generic/simple-card-utils.c |
// SPDX-License-Identifier: GPL-2.0
//
// ASoC audio graph sound card support
//
// Copyright (C) 2016 Renesas Solutions Corp.
// Kuninori Morimoto <[email protected]>
//
// based on ${LINUX}/sound/soc/generic/simple-card.c
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <sound/graph_card.h>
#define DPCM_SELECTABLE 1
static int graph_outdrv_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(dapm->card);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
gpiod_set_value_cansleep(priv->pa_gpio, 1);
break;
case SND_SOC_DAPM_PRE_PMD:
gpiod_set_value_cansleep(priv->pa_gpio, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dapm_widget graph_dapm_widgets[] = {
SND_SOC_DAPM_OUT_DRV_E("Amplifier", SND_SOC_NOPM,
0, 0, NULL, 0, graph_outdrv_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
};
static const struct snd_soc_ops graph_ops = {
.startup = asoc_simple_startup,
.shutdown = asoc_simple_shutdown,
.hw_params = asoc_simple_hw_params,
};
static bool soc_component_is_pcm(struct snd_soc_dai_link_component *dlc)
{
struct snd_soc_dai *dai = snd_soc_find_dai_with_mutex(dlc);
if (dai && (dai->component->driver->pcm_construct ||
(dai->driver->ops && dai->driver->ops->pcm_new)))
return true;
return false;
}
static void graph_parse_convert(struct device *dev,
struct device_node *ep,
struct asoc_simple_data *adata)
{
struct device_node *top = dev->of_node;
struct device_node *port = of_get_parent(ep);
struct device_node *ports = of_get_parent(port);
struct device_node *node = of_graph_get_port_parent(ep);
asoc_simple_parse_convert(top, NULL, adata);
if (of_node_name_eq(ports, "ports"))
asoc_simple_parse_convert(ports, NULL, adata);
asoc_simple_parse_convert(port, NULL, adata);
asoc_simple_parse_convert(ep, NULL, adata);
of_node_put(port);
of_node_put(ports);
of_node_put(node);
}
static void graph_parse_mclk_fs(struct device_node *top,
struct device_node *ep,
struct simple_dai_props *props)
{
struct device_node *port = of_get_parent(ep);
struct device_node *ports = of_get_parent(port);
of_property_read_u32(top, "mclk-fs", &props->mclk_fs);
if (of_node_name_eq(ports, "ports"))
of_property_read_u32(ports, "mclk-fs", &props->mclk_fs);
of_property_read_u32(port, "mclk-fs", &props->mclk_fs);
of_property_read_u32(ep, "mclk-fs", &props->mclk_fs);
of_node_put(port);
of_node_put(ports);
}
static int graph_parse_node(struct asoc_simple_priv *priv,
struct device_node *ep,
struct link_info *li,
int *cpu)
{
struct device *dev = simple_priv_to_dev(priv);
struct device_node *top = dev->of_node;
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, li->link);
struct snd_soc_dai_link_component *dlc;
struct asoc_simple_dai *dai;
int ret;
if (cpu) {
dlc = asoc_link_to_cpu(dai_link, 0);
dai = simple_props_to_dai_cpu(dai_props, 0);
} else {
dlc = asoc_link_to_codec(dai_link, 0);
dai = simple_props_to_dai_codec(dai_props, 0);
}
graph_parse_mclk_fs(top, ep, dai_props);
ret = asoc_graph_parse_dai(dev, ep, dlc, cpu);
if (ret < 0)
return ret;
ret = asoc_simple_parse_tdm(ep, dai);
if (ret < 0)
return ret;
ret = asoc_simple_parse_clk(dev, ep, dai, dlc);
if (ret < 0)
return ret;
return 0;
}
static int graph_link_init(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li,
char *name)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
int ret;
ret = asoc_simple_parse_daifmt(dev, cpu_ep, codec_ep,
NULL, &dai_link->dai_fmt);
if (ret < 0)
return ret;
dai_link->init = asoc_simple_dai_init;
dai_link->ops = &graph_ops;
if (priv->ops)
dai_link->ops = priv->ops;
return asoc_simple_set_dailink_name(dev, dai_link, name);
}
static int graph_dai_link_of_dpcm(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct simple_dai_props *dai_props = simple_priv_to_props(priv, li->link);
struct device_node *top = dev->of_node;
struct device_node *ep = li->cpu ? cpu_ep : codec_ep;
char dai_name[64];
int ret;
dev_dbg(dev, "link_of DPCM (%pOF)\n", ep);
if (li->cpu) {
struct snd_soc_card *card = simple_priv_to_card(priv);
struct snd_soc_dai_link_component *cpus = asoc_link_to_cpu(dai_link, 0);
struct snd_soc_dai_link_component *platforms = asoc_link_to_platform(dai_link, 0);
int is_single_links = 0;
/* Codec is dummy */
/* FE settings */
dai_link->dynamic = 1;
dai_link->dpcm_merged_format = 1;
ret = graph_parse_node(priv, cpu_ep, li, &is_single_links);
if (ret)
return ret;
snprintf(dai_name, sizeof(dai_name),
"fe.%pOFP.%s", cpus->of_node, cpus->dai_name);
/*
* In BE<->BE connections it is not required to create
* PCM devices at CPU end of the dai link and thus 'no_pcm'
* flag needs to be set. It is useful when there are many
* BE components and some of these have to be connected to
* form a valid audio path.
*
* For example: FE <-> BE1 <-> BE2 <-> ... <-> BEn where
* there are 'n' BE components in the path.
*/
if (card->component_chaining && !soc_component_is_pcm(cpus)) {
dai_link->no_pcm = 1;
dai_link->be_hw_params_fixup = asoc_simple_be_hw_params_fixup;
}
asoc_simple_canonicalize_cpu(cpus, is_single_links);
asoc_simple_canonicalize_platform(platforms, cpus);
} else {
struct snd_soc_codec_conf *cconf = simple_props_to_codec_conf(dai_props, 0);
struct snd_soc_dai_link_component *codecs = asoc_link_to_codec(dai_link, 0);
struct device_node *port;
struct device_node *ports;
/* CPU is dummy */
/* BE settings */
dai_link->no_pcm = 1;
dai_link->be_hw_params_fixup = asoc_simple_be_hw_params_fixup;
ret = graph_parse_node(priv, codec_ep, li, NULL);
if (ret < 0)
return ret;
snprintf(dai_name, sizeof(dai_name),
"be.%pOFP.%s", codecs->of_node, codecs->dai_name);
/* check "prefix" from top node */
port = of_get_parent(ep);
ports = of_get_parent(port);
snd_soc_of_parse_node_prefix(top, cconf, codecs->of_node,
"prefix");
if (of_node_name_eq(ports, "ports"))
snd_soc_of_parse_node_prefix(ports, cconf, codecs->of_node, "prefix");
snd_soc_of_parse_node_prefix(port, cconf, codecs->of_node,
"prefix");
of_node_put(ports);
of_node_put(port);
}
graph_parse_convert(dev, ep, &dai_props->adata);
snd_soc_dai_link_set_capabilities(dai_link);
ret = graph_link_init(priv, cpu_ep, codec_ep, li, dai_name);
li->link++;
return ret;
}
static int graph_dai_link_of(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, li->link);
struct snd_soc_dai_link_component *cpus = asoc_link_to_cpu(dai_link, 0);
struct snd_soc_dai_link_component *codecs = asoc_link_to_codec(dai_link, 0);
struct snd_soc_dai_link_component *platforms = asoc_link_to_platform(dai_link, 0);
char dai_name[64];
int ret, is_single_links = 0;
dev_dbg(dev, "link_of (%pOF)\n", cpu_ep);
ret = graph_parse_node(priv, cpu_ep, li, &is_single_links);
if (ret < 0)
return ret;
ret = graph_parse_node(priv, codec_ep, li, NULL);
if (ret < 0)
return ret;
snprintf(dai_name, sizeof(dai_name),
"%s-%s", cpus->dai_name, codecs->dai_name);
asoc_simple_canonicalize_cpu(cpus, is_single_links);
asoc_simple_canonicalize_platform(platforms, cpus);
ret = graph_link_init(priv, cpu_ep, codec_ep, li, dai_name);
if (ret < 0)
return ret;
li->link++;
return 0;
}
static inline bool parse_as_dpcm_link(struct asoc_simple_priv *priv,
struct device_node *codec_port,
struct asoc_simple_data *adata)
{
if (priv->force_dpcm)
return true;
if (!priv->dpcm_selectable)
return false;
/*
* It is DPCM
* if Codec port has many endpoints,
* or has convert-xxx property
*/
if ((of_get_child_count(codec_port) > 1) ||
asoc_simple_is_convert_required(adata))
return true;
return false;
}
static int __graph_for_each_link(struct asoc_simple_priv *priv,
struct link_info *li,
int (*func_noml)(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li),
int (*func_dpcm)(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li))
{
struct of_phandle_iterator it;
struct device *dev = simple_priv_to_dev(priv);
struct device_node *node = dev->of_node;
struct device_node *cpu_port;
struct device_node *cpu_ep;
struct device_node *codec_ep;
struct device_node *codec_port;
struct device_node *codec_port_old = NULL;
struct asoc_simple_data adata;
int rc, ret = 0;
/* loop for all listed CPU port */
of_for_each_phandle(&it, rc, node, "dais", NULL, 0) {
cpu_port = it.node;
cpu_ep = NULL;
/* loop for all CPU endpoint */
while (1) {
cpu_ep = of_get_next_child(cpu_port, cpu_ep);
if (!cpu_ep)
break;
/* get codec */
codec_ep = of_graph_get_remote_endpoint(cpu_ep);
codec_port = of_get_parent(codec_ep);
/* get convert-xxx property */
memset(&adata, 0, sizeof(adata));
graph_parse_convert(dev, codec_ep, &adata);
graph_parse_convert(dev, cpu_ep, &adata);
/* check if link requires DPCM parsing */
if (parse_as_dpcm_link(priv, codec_port, &adata)) {
/*
* Codec endpoint can be NULL for pluggable audio HW.
* Platform DT can populate the Codec endpoint depending on the
* plugged HW.
*/
/* Do it all CPU endpoint, and 1st Codec endpoint */
if (li->cpu ||
((codec_port_old != codec_port) && codec_ep))
ret = func_dpcm(priv, cpu_ep, codec_ep, li);
/* else normal sound */
} else {
if (li->cpu)
ret = func_noml(priv, cpu_ep, codec_ep, li);
}
of_node_put(codec_ep);
of_node_put(codec_port);
if (ret < 0) {
of_node_put(cpu_ep);
return ret;
}
codec_port_old = codec_port;
}
}
return 0;
}
static int graph_for_each_link(struct asoc_simple_priv *priv,
struct link_info *li,
int (*func_noml)(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li),
int (*func_dpcm)(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li))
{
int ret;
/*
* Detect all CPU first, and Detect all Codec 2nd.
*
* In Normal sound case, all DAIs are detected
* as "CPU-Codec".
*
* In DPCM sound case,
* all CPUs are detected as "CPU-dummy", and
* all Codecs are detected as "dummy-Codec".
* To avoid random sub-device numbering,
* detect "dummy-Codec" in last;
*/
for (li->cpu = 1; li->cpu >= 0; li->cpu--) {
ret = __graph_for_each_link(priv, li, func_noml, func_dpcm);
if (ret < 0)
break;
}
return ret;
}
static int graph_count_noml(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
if (li->link >= SNDRV_MAX_LINKS) {
dev_err(dev, "too many links\n");
return -EINVAL;
}
/*
* DON'T REMOVE platforms
* see
* simple-card.c :: simple_count_noml()
*/
li->num[li->link].cpus = 1;
li->num[li->link].platforms = 1;
li->num[li->link].codecs = 1;
li->link += 1; /* 1xCPU-Codec */
dev_dbg(dev, "Count As Normal\n");
return 0;
}
static int graph_count_dpcm(struct asoc_simple_priv *priv,
struct device_node *cpu_ep,
struct device_node *codec_ep,
struct link_info *li)
{
struct device *dev = simple_priv_to_dev(priv);
if (li->link >= SNDRV_MAX_LINKS) {
dev_err(dev, "too many links\n");
return -EINVAL;
}
if (li->cpu) {
/*
* DON'T REMOVE platforms
* see
* simple-card.c :: simple_count_noml()
*/
li->num[li->link].cpus = 1;
li->num[li->link].platforms = 1;
li->link++; /* 1xCPU-dummy */
} else {
li->num[li->link].codecs = 1;
li->link++; /* 1xdummy-Codec */
}
dev_dbg(dev, "Count As DPCM\n");
return 0;
}
static int graph_get_dais_count(struct asoc_simple_priv *priv,
struct link_info *li)
{
/*
* link_num : number of links.
* CPU-Codec / CPU-dummy / dummy-Codec
* dais_num : number of DAIs
* ccnf_num : number of codec_conf
* same number for "dummy-Codec"
*
* ex1)
* CPU0 --- Codec0 link : 5
* CPU1 --- Codec1 dais : 7
* CPU2 -/ ccnf : 1
* CPU3 --- Codec2
*
* => 5 links = 2xCPU-Codec + 2xCPU-dummy + 1xdummy-Codec
* => 7 DAIs = 4xCPU + 3xCodec
* => 1 ccnf = 1xdummy-Codec
*
* ex2)
* CPU0 --- Codec0 link : 5
* CPU1 --- Codec1 dais : 6
* CPU2 -/ ccnf : 1
* CPU3 -/
*
* => 5 links = 1xCPU-Codec + 3xCPU-dummy + 1xdummy-Codec
* => 6 DAIs = 4xCPU + 2xCodec
* => 1 ccnf = 1xdummy-Codec
*
* ex3)
* CPU0 --- Codec0 link : 6
* CPU1 -/ dais : 6
* CPU2 --- Codec1 ccnf : 2
* CPU3 -/
*
* => 6 links = 0xCPU-Codec + 4xCPU-dummy + 2xdummy-Codec
* => 6 DAIs = 4xCPU + 2xCodec
* => 2 ccnf = 2xdummy-Codec
*
* ex4)
* CPU0 --- Codec0 (convert-rate) link : 3
* CPU1 --- Codec1 dais : 4
* ccnf : 1
*
* => 3 links = 1xCPU-Codec + 1xCPU-dummy + 1xdummy-Codec
* => 4 DAIs = 2xCPU + 2xCodec
* => 1 ccnf = 1xdummy-Codec
*/
return graph_for_each_link(priv, li,
graph_count_noml,
graph_count_dpcm);
}
int audio_graph_parse_of(struct asoc_simple_priv *priv, struct device *dev)
{
struct snd_soc_card *card = simple_priv_to_card(priv);
struct link_info *li;
int ret;
li = devm_kzalloc(dev, sizeof(*li), GFP_KERNEL);
if (!li)
return -ENOMEM;
card->owner = THIS_MODULE;
card->dev = dev;
ret = graph_get_dais_count(priv, li);
if (ret < 0)
return ret;
if (!li->link)
return -EINVAL;
ret = asoc_simple_init_priv(priv, li);
if (ret < 0)
return ret;
priv->pa_gpio = devm_gpiod_get_optional(dev, "pa", GPIOD_OUT_LOW);
if (IS_ERR(priv->pa_gpio)) {
ret = PTR_ERR(priv->pa_gpio);
dev_err(dev, "failed to get amplifier gpio: %d\n", ret);
return ret;
}
ret = asoc_simple_parse_widgets(card, NULL);
if (ret < 0)
return ret;
ret = asoc_simple_parse_routing(card, NULL);
if (ret < 0)
return ret;
memset(li, 0, sizeof(*li));
ret = graph_for_each_link(priv, li,
graph_dai_link_of,
graph_dai_link_of_dpcm);
if (ret < 0)
goto err;
ret = asoc_simple_parse_card_name(card, NULL);
if (ret < 0)
goto err;
snd_soc_card_set_drvdata(card, priv);
asoc_simple_debug_info(priv);
ret = devm_snd_soc_register_card(dev, card);
if (ret < 0)
goto err;
devm_kfree(dev, li);
return 0;
err:
asoc_simple_clean_reference(card);
return dev_err_probe(dev, ret, "parse error\n");
}
EXPORT_SYMBOL_GPL(audio_graph_parse_of);
static int graph_probe(struct platform_device *pdev)
{
struct asoc_simple_priv *priv;
struct device *dev = &pdev->dev;
struct snd_soc_card *card;
/* Allocate the private data and the DAI link array */
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
card = simple_priv_to_card(priv);
card->dapm_widgets = graph_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(graph_dapm_widgets);
card->probe = asoc_graph_card_probe;
if (of_device_get_match_data(dev))
priv->dpcm_selectable = 1;
return audio_graph_parse_of(priv, dev);
}
static const struct of_device_id graph_of_match[] = {
{ .compatible = "audio-graph-card", },
{ .compatible = "audio-graph-scu-card",
.data = (void *)DPCM_SELECTABLE },
{},
};
MODULE_DEVICE_TABLE(of, graph_of_match);
static struct platform_driver graph_card = {
.driver = {
.name = "asoc-audio-graph-card",
.pm = &snd_soc_pm_ops,
.of_match_table = graph_of_match,
},
.probe = graph_probe,
.remove = asoc_simple_remove,
};
module_platform_driver(graph_card);
MODULE_ALIAS("platform:asoc-audio-graph-card");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("ASoC Audio Graph Sound Card");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
| linux-master | sound/soc/generic/audio-graph-card.c |
// SPDX-License-Identifier: GPL-2.0
//
// test-component.c -- Test Audio Component driver
//
// Copyright (C) 2020 Renesas Electronics Corporation
// Kuninori Morimoto <[email protected]>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/module.h>
#include <linux/workqueue.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#define TEST_NAME_LEN 32
struct test_dai_name {
char name[TEST_NAME_LEN];
char name_playback[TEST_NAME_LEN];
char name_capture[TEST_NAME_LEN];
};
struct test_priv {
struct device *dev;
struct snd_pcm_substream *substream;
struct delayed_work dwork;
struct snd_soc_component_driver *component_driver;
struct snd_soc_dai_driver *dai_driver;
struct test_dai_name *name;
};
struct test_adata {
u32 is_cpu:1;
u32 cmp_v:1;
u32 dai_v:1;
};
#define mile_stone(d) dev_info((d)->dev, "%s() : %s", __func__, (d)->driver->name)
#define mile_stone_x(dev) dev_info(dev, "%s()", __func__)
static int test_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
mile_stone(dai);
return 0;
}
static int test_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
mile_stone(dai);
return 0;
}
static int test_dai_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
mile_stone(dai);
return 0;
}
static int test_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
unsigned int format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
unsigned int clock = fmt & SND_SOC_DAIFMT_CLOCK_MASK;
unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK;
unsigned int master = fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
char *str;
dev_info(dai->dev, "name : %s", dai->name);
str = "unknown";
switch (format) {
case SND_SOC_DAIFMT_I2S:
str = "i2s";
break;
case SND_SOC_DAIFMT_RIGHT_J:
str = "right_j";
break;
case SND_SOC_DAIFMT_LEFT_J:
str = "left_j";
break;
case SND_SOC_DAIFMT_DSP_A:
str = "dsp_a";
break;
case SND_SOC_DAIFMT_DSP_B:
str = "dsp_b";
break;
case SND_SOC_DAIFMT_AC97:
str = "ac97";
break;
case SND_SOC_DAIFMT_PDM:
str = "pdm";
break;
}
dev_info(dai->dev, "format : %s", str);
if (clock == SND_SOC_DAIFMT_CONT)
str = "continuous";
else
str = "gated";
dev_info(dai->dev, "clock : %s", str);
str = "unknown";
switch (master) {
case SND_SOC_DAIFMT_BP_FP:
str = "clk provider, frame provider";
break;
case SND_SOC_DAIFMT_BC_FP:
str = "clk consumer, frame provider";
break;
case SND_SOC_DAIFMT_BP_FC:
str = "clk provider, frame consumer";
break;
case SND_SOC_DAIFMT_BC_FC:
str = "clk consumer, frame consumer";
break;
}
dev_info(dai->dev, "clock : codec is %s", str);
str = "unknown";
switch (inv) {
case SND_SOC_DAIFMT_NB_NF:
str = "normal bit, normal frame";
break;
case SND_SOC_DAIFMT_NB_IF:
str = "normal bit, invert frame";
break;
case SND_SOC_DAIFMT_IB_NF:
str = "invert bit, normal frame";
break;
case SND_SOC_DAIFMT_IB_IF:
str = "invert bit, invert frame";
break;
}
dev_info(dai->dev, "signal : %s", str);
return 0;
}
static int test_dai_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
mile_stone(dai);
return 0;
}
static int test_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
mile_stone(dai);
return 0;
}
static void test_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
mile_stone(dai);
}
static int test_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
mile_stone(dai);
return 0;
}
static int test_dai_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
mile_stone(dai);
return 0;
}
static int test_dai_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
{
mile_stone(dai);
return 0;
}
static int test_dai_bespoke_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
mile_stone(dai);
return 0;
}
static u64 test_dai_formats =
/*
* Select below from Sound Card, not auto
* SND_SOC_POSSIBLE_DAIFMT_BP_FP
* SND_SOC_POSSIBLE_DAIFMT_BC_FP
* SND_SOC_POSSIBLE_DAIFMT_BP_FC
* SND_SOC_POSSIBLE_DAIFMT_BC_FC
*/
SND_SOC_POSSIBLE_DAIFMT_I2S |
SND_SOC_POSSIBLE_DAIFMT_RIGHT_J |
SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
SND_SOC_POSSIBLE_DAIFMT_DSP_A |
SND_SOC_POSSIBLE_DAIFMT_DSP_B |
SND_SOC_POSSIBLE_DAIFMT_AC97 |
SND_SOC_POSSIBLE_DAIFMT_PDM |
SND_SOC_POSSIBLE_DAIFMT_NB_NF |
SND_SOC_POSSIBLE_DAIFMT_NB_IF |
SND_SOC_POSSIBLE_DAIFMT_IB_NF |
SND_SOC_POSSIBLE_DAIFMT_IB_IF;
static const struct snd_soc_dai_ops test_ops = {
.set_fmt = test_dai_set_fmt,
.startup = test_dai_startup,
.shutdown = test_dai_shutdown,
.auto_selectable_formats = &test_dai_formats,
.num_auto_selectable_formats = 1,
};
static const struct snd_soc_dai_ops test_verbose_ops = {
.set_sysclk = test_dai_set_sysclk,
.set_pll = test_dai_set_pll,
.set_clkdiv = test_dai_set_clkdiv,
.set_fmt = test_dai_set_fmt,
.mute_stream = test_dai_mute_stream,
.startup = test_dai_startup,
.shutdown = test_dai_shutdown,
.hw_params = test_dai_hw_params,
.hw_free = test_dai_hw_free,
.trigger = test_dai_trigger,
.bespoke_trigger = test_dai_bespoke_trigger,
.auto_selectable_formats = &test_dai_formats,
.num_auto_selectable_formats = 1,
};
#define STUB_RATES SNDRV_PCM_RATE_8000_384000
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_U32_LE)
static int test_component_probe(struct snd_soc_component *component)
{
mile_stone(component);
return 0;
}
static void test_component_remove(struct snd_soc_component *component)
{
mile_stone(component);
}
static int test_component_suspend(struct snd_soc_component *component)
{
mile_stone(component);
return 0;
}
static int test_component_resume(struct snd_soc_component *component)
{
mile_stone(component);
return 0;
}
#define PREALLOC_BUFFER (32 * 1024)
static int test_component_pcm_construct(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
mile_stone(component);
snd_pcm_set_managed_buffer_all(
rtd->pcm,
SNDRV_DMA_TYPE_DEV,
rtd->card->snd_card->dev,
PREALLOC_BUFFER, PREALLOC_BUFFER);
return 0;
}
static void test_component_pcm_destruct(struct snd_soc_component *component,
struct snd_pcm *pcm)
{
mile_stone(component);
}
static int test_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
mile_stone(component);
return 0;
}
static int test_component_set_pll(struct snd_soc_component *component, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
mile_stone(component);
return 0;
}
static int test_component_set_jack(struct snd_soc_component *component,
struct snd_soc_jack *jack, void *data)
{
mile_stone(component);
return 0;
}
static void test_component_seq_notifier(struct snd_soc_component *component,
enum snd_soc_dapm_type type, int subseq)
{
mile_stone(component);
}
static int test_component_stream_event(struct snd_soc_component *component, int event)
{
mile_stone(component);
return 0;
}
static int test_component_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
mile_stone(component);
return 0;
}
static const struct snd_pcm_hardware test_component_hardware = {
/* Random values to keep userspace happy when checking constraints */
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID,
.buffer_bytes_max = 32 * 1024,
.period_bytes_min = 32,
.period_bytes_max = 8192,
.periods_min = 1,
.periods_max = 128,
.fifo_size = 256,
};
static int test_component_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
mile_stone(component);
/* BE's dont need dummy params */
if (!rtd->dai_link->no_pcm)
snd_soc_set_runtime_hwparams(substream, &test_component_hardware);
return 0;
}
static int test_component_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
mile_stone(component);
return 0;
}
static int test_component_ioctl(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
unsigned int cmd, void *arg)
{
mile_stone(component);
return 0;
}
static int test_component_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
mile_stone(component);
return 0;
}
static int test_component_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
mile_stone(component);
return 0;
}
static int test_component_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
mile_stone(component);
return 0;
}
static void test_component_timer_stop(struct test_priv *priv)
{
cancel_delayed_work(&priv->dwork);
}
static void test_component_timer_start(struct test_priv *priv)
{
schedule_delayed_work(&priv->dwork, msecs_to_jiffies(10));
}
static void test_component_dwork(struct work_struct *work)
{
struct test_priv *priv = container_of(work, struct test_priv, dwork.work);
if (priv->substream)
snd_pcm_period_elapsed(priv->substream);
test_component_timer_start(priv);
}
static int test_component_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct test_priv *priv = dev_get_drvdata(component->dev);
mile_stone(component);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
test_component_timer_start(priv);
priv->substream = substream; /* set substream later */
break;
case SNDRV_PCM_TRIGGER_STOP:
priv->substream = NULL;
test_component_timer_stop(priv);
}
return 0;
}
static int test_component_sync_stop(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
mile_stone(component);
return 0;
}
static snd_pcm_uframes_t test_component_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
static int pointer;
if (!runtime)
return 0;
pointer += 10;
if (pointer > PREALLOC_BUFFER)
pointer = 0;
/* mile_stone(component); */
return bytes_to_frames(runtime, pointer);
}
static int test_component_get_time_info(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct timespec64 *system_ts,
struct timespec64 *audio_ts,
struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
{
mile_stone(component);
return 0;
}
static int test_component_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
mile_stone_x(rtd->dev);
return 0;
}
/* CPU */
static const struct test_adata test_cpu = { .is_cpu = 1, .cmp_v = 0, .dai_v = 0, };
static const struct test_adata test_cpu_vv = { .is_cpu = 1, .cmp_v = 1, .dai_v = 1, };
static const struct test_adata test_cpu_nv = { .is_cpu = 1, .cmp_v = 0, .dai_v = 1, };
static const struct test_adata test_cpu_vn = { .is_cpu = 1, .cmp_v = 1, .dai_v = 0, };
/* Codec */
static const struct test_adata test_codec = { .is_cpu = 0, .cmp_v = 0, .dai_v = 0, };
static const struct test_adata test_codec_vv = { .is_cpu = 0, .cmp_v = 1, .dai_v = 1, };
static const struct test_adata test_codec_nv = { .is_cpu = 0, .cmp_v = 0, .dai_v = 1, };
static const struct test_adata test_codec_vn = { .is_cpu = 0, .cmp_v = 1, .dai_v = 0, };
static const struct of_device_id test_of_match[] = {
{ .compatible = "test-cpu", .data = (void *)&test_cpu, },
{ .compatible = "test-cpu-verbose", .data = (void *)&test_cpu_vv, },
{ .compatible = "test-cpu-verbose-dai", .data = (void *)&test_cpu_nv, },
{ .compatible = "test-cpu-verbose-component", .data = (void *)&test_cpu_vn, },
{ .compatible = "test-codec", .data = (void *)&test_codec, },
{ .compatible = "test-codec-verbose", .data = (void *)&test_codec_vv, },
{ .compatible = "test-codec-verbose-dai", .data = (void *)&test_codec_nv, },
{ .compatible = "test-codec-verbose-component", .data = (void *)&test_codec_vn, },
{},
};
MODULE_DEVICE_TABLE(of, test_of_match);
static const struct snd_soc_dapm_widget widgets[] = {
/*
* FIXME
*
* Just IN/OUT is OK for now,
* but need to be updated ?
*/
SND_SOC_DAPM_INPUT("IN"),
SND_SOC_DAPM_OUTPUT("OUT"),
};
static int test_driver_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct device_node *ep;
const struct test_adata *adata = of_device_get_match_data(&pdev->dev);
struct snd_soc_component_driver *cdriv;
struct snd_soc_dai_driver *ddriv;
struct test_dai_name *dname;
struct test_priv *priv;
int num, ret, i;
num = of_graph_get_endpoint_count(node);
if (!num) {
dev_err(dev, "no port exits\n");
return -EINVAL;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
cdriv = devm_kzalloc(dev, sizeof(*cdriv), GFP_KERNEL);
ddriv = devm_kzalloc(dev, sizeof(*ddriv) * num, GFP_KERNEL);
dname = devm_kzalloc(dev, sizeof(*dname) * num, GFP_KERNEL);
if (!priv || !cdriv || !ddriv || !dname || !adata)
return -EINVAL;
priv->dev = dev;
priv->component_driver = cdriv;
priv->dai_driver = ddriv;
priv->name = dname;
INIT_DELAYED_WORK(&priv->dwork, test_component_dwork);
dev_set_drvdata(dev, priv);
if (adata->is_cpu) {
cdriv->name = "test_cpu";
cdriv->pcm_construct = test_component_pcm_construct;
cdriv->pointer = test_component_pointer;
cdriv->trigger = test_component_trigger;
cdriv->legacy_dai_naming = 1;
} else {
cdriv->name = "test_codec";
cdriv->idle_bias_on = 1;
cdriv->endianness = 1;
}
cdriv->open = test_component_open;
cdriv->dapm_widgets = widgets;
cdriv->num_dapm_widgets = ARRAY_SIZE(widgets);
if (adata->cmp_v) {
cdriv->probe = test_component_probe;
cdriv->remove = test_component_remove;
cdriv->suspend = test_component_suspend;
cdriv->resume = test_component_resume;
cdriv->set_sysclk = test_component_set_sysclk;
cdriv->set_pll = test_component_set_pll;
cdriv->set_jack = test_component_set_jack;
cdriv->seq_notifier = test_component_seq_notifier;
cdriv->stream_event = test_component_stream_event;
cdriv->set_bias_level = test_component_set_bias_level;
cdriv->close = test_component_close;
cdriv->ioctl = test_component_ioctl;
cdriv->hw_params = test_component_hw_params;
cdriv->hw_free = test_component_hw_free;
cdriv->prepare = test_component_prepare;
cdriv->sync_stop = test_component_sync_stop;
cdriv->get_time_info = test_component_get_time_info;
cdriv->be_hw_params_fixup = test_component_be_hw_params_fixup;
if (adata->is_cpu)
cdriv->pcm_destruct = test_component_pcm_destruct;
}
i = 0;
for_each_endpoint_of_node(node, ep) {
snprintf(dname[i].name, TEST_NAME_LEN, "%s.%d", node->name, i);
ddriv[i].name = dname[i].name;
snprintf(dname[i].name_playback, TEST_NAME_LEN, "DAI%d Playback", i);
ddriv[i].playback.stream_name = dname[i].name_playback;
ddriv[i].playback.channels_min = 1;
ddriv[i].playback.channels_max = 384;
ddriv[i].playback.rates = STUB_RATES;
ddriv[i].playback.formats = STUB_FORMATS;
snprintf(dname[i].name_capture, TEST_NAME_LEN, "DAI%d Capture", i);
ddriv[i].capture.stream_name = dname[i].name_capture;
ddriv[i].capture.channels_min = 1;
ddriv[i].capture.channels_max = 384;
ddriv[i].capture.rates = STUB_RATES;
ddriv[i].capture.formats = STUB_FORMATS;
if (adata->dai_v)
ddriv[i].ops = &test_verbose_ops;
else
ddriv[i].ops = &test_ops;
i++;
}
ret = devm_snd_soc_register_component(dev, cdriv, ddriv, num);
if (ret < 0)
return ret;
mile_stone_x(dev);
return 0;
}
static void test_driver_remove(struct platform_device *pdev)
{
mile_stone_x(&pdev->dev);
}
static struct platform_driver test_driver = {
.driver = {
.name = "test-component",
.of_match_table = test_of_match,
},
.probe = test_driver_probe,
.remove_new = test_driver_remove,
};
module_platform_driver(test_driver);
MODULE_ALIAS("platform:asoc-test-component");
MODULE_AUTHOR("Kuninori Morimoto <[email protected]>");
MODULE_DESCRIPTION("ASoC Test Component");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/generic/test-component.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
// Generic firmware loader.
//
#include <linux/firmware.h>
#include "sof-priv.h"
#include "ops.h"
int snd_sof_load_firmware_raw(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *plat_data = sdev->pdata;
const char *fw_filename;
ssize_t ext_man_size;
int ret;
/* Don't request firmware again if firmware is already requested */
if (sdev->basefw.fw)
return 0;
fw_filename = kasprintf(GFP_KERNEL, "%s/%s",
plat_data->fw_filename_prefix,
plat_data->fw_filename);
if (!fw_filename)
return -ENOMEM;
ret = request_firmware(&sdev->basefw.fw, fw_filename, sdev->dev);
if (ret < 0) {
dev_err(sdev->dev,
"error: sof firmware file is missing, you might need to\n");
dev_err(sdev->dev,
" download it from https://github.com/thesofproject/sof-bin/\n");
goto err;
} else {
dev_dbg(sdev->dev, "request_firmware %s successful\n",
fw_filename);
}
/* check for extended manifest */
ext_man_size = sdev->ipc->ops->fw_loader->parse_ext_manifest(sdev);
if (ext_man_size > 0) {
/* when no error occurred, drop extended manifest */
sdev->basefw.payload_offset = ext_man_size;
} else if (!ext_man_size) {
/* No extended manifest, so nothing to skip during FW load */
dev_dbg(sdev->dev, "firmware doesn't contain extended manifest\n");
} else {
ret = ext_man_size;
dev_err(sdev->dev, "error: firmware %s contains unsupported or invalid extended manifest: %d\n",
fw_filename, ret);
}
err:
kfree(fw_filename);
return ret;
}
EXPORT_SYMBOL(snd_sof_load_firmware_raw);
int snd_sof_load_firmware_memcpy(struct snd_sof_dev *sdev)
{
int ret;
ret = snd_sof_load_firmware_raw(sdev);
if (ret < 0)
return ret;
/* make sure the FW header and file is valid */
ret = sdev->ipc->ops->fw_loader->validate(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: invalid FW header\n");
goto error;
}
/* prepare the DSP for FW loading */
ret = snd_sof_dsp_reset(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to reset DSP\n");
goto error;
}
/* parse and load firmware modules to DSP */
if (sdev->ipc->ops->fw_loader->load_fw_to_dsp) {
ret = sdev->ipc->ops->fw_loader->load_fw_to_dsp(sdev);
if (ret < 0) {
dev_err(sdev->dev, "Firmware loading failed\n");
goto error;
}
}
return 0;
error:
release_firmware(sdev->basefw.fw);
sdev->basefw.fw = NULL;
return ret;
}
EXPORT_SYMBOL(snd_sof_load_firmware_memcpy);
int snd_sof_run_firmware(struct snd_sof_dev *sdev)
{
int ret;
init_waitqueue_head(&sdev->boot_wait);
/* (re-)enable dsp dump */
sdev->dbg_dump_printed = false;
sdev->ipc_dump_printed = false;
/* create read-only fw_version debugfs to store boot version info */
if (sdev->first_boot) {
ret = snd_sof_debugfs_buf_item(sdev, &sdev->fw_version,
sizeof(sdev->fw_version),
"fw_version", 0444);
/* errors are only due to memory allocation, not debugfs */
if (ret < 0) {
dev_err(sdev->dev, "snd_sof_debugfs_buf_item failed\n");
return ret;
}
}
/* perform pre fw run operations */
ret = snd_sof_dsp_pre_fw_run(sdev);
if (ret < 0) {
dev_err(sdev->dev, "failed pre fw run op\n");
return ret;
}
dev_dbg(sdev->dev, "booting DSP firmware\n");
/* boot the firmware on the DSP */
ret = snd_sof_dsp_run(sdev);
if (ret < 0) {
snd_sof_dsp_dbg_dump(sdev, "Failed to start DSP",
SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_PCI);
return ret;
}
/*
* now wait for the DSP to boot. There are 3 possible outcomes:
* 1. Boot wait times out indicating FW boot failure.
* 2. FW boots successfully and fw_ready op succeeds.
* 3. FW boots but fw_ready op fails.
*/
ret = wait_event_timeout(sdev->boot_wait,
sdev->fw_state > SOF_FW_BOOT_IN_PROGRESS,
msecs_to_jiffies(sdev->boot_timeout));
if (ret == 0) {
snd_sof_dsp_dbg_dump(sdev, "Firmware boot failure due to timeout",
SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX |
SOF_DBG_DUMP_TEXT | SOF_DBG_DUMP_PCI);
return -EIO;
}
if (sdev->fw_state == SOF_FW_BOOT_READY_FAILED)
return -EIO; /* FW boots but fw_ready op failed */
dev_dbg(sdev->dev, "firmware boot complete\n");
sof_set_fw_state(sdev, SOF_FW_BOOT_COMPLETE);
/* perform post fw run operations */
ret = snd_sof_dsp_post_fw_run(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed post fw run op\n");
return ret;
}
if (sdev->ipc->ops->post_fw_boot)
return sdev->ipc->ops->post_fw_boot(sdev);
return 0;
}
EXPORT_SYMBOL(snd_sof_run_firmware);
void snd_sof_fw_unload(struct snd_sof_dev *sdev)
{
/* TODO: support module unloading at runtime */
release_firmware(sdev->basefw.fw);
sdev->basefw.fw = NULL;
}
EXPORT_SYMBOL(snd_sof_fw_unload);
| linux-master | sound/soc/sof/loader.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright 2019 NXP
//
// Author: Daniel Baluta <[email protected]>
//
#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pm_runtime.h>
#include <sound/sof.h>
#include "sof-of-dev.h"
#include "ops.h"
static char *fw_path;
module_param(fw_path, charp, 0444);
MODULE_PARM_DESC(fw_path, "alternate path for SOF firmware.");
static char *tplg_path;
module_param(tplg_path, charp, 0444);
MODULE_PARM_DESC(tplg_path, "alternate path for SOF topology.");
const struct dev_pm_ops sof_of_pm = {
.prepare = snd_sof_prepare,
.complete = snd_sof_complete,
SET_SYSTEM_SLEEP_PM_OPS(snd_sof_suspend, snd_sof_resume)
SET_RUNTIME_PM_OPS(snd_sof_runtime_suspend, snd_sof_runtime_resume,
NULL)
};
EXPORT_SYMBOL(sof_of_pm);
static void sof_of_probe_complete(struct device *dev)
{
/* allow runtime_pm */
pm_runtime_set_autosuspend_delay(dev, SND_SOF_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
}
int sof_of_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct sof_dev_desc *desc;
struct snd_sof_pdata *sof_pdata;
dev_info(&pdev->dev, "DT DSP detected");
sof_pdata = devm_kzalloc(dev, sizeof(*sof_pdata), GFP_KERNEL);
if (!sof_pdata)
return -ENOMEM;
desc = device_get_match_data(dev);
if (!desc)
return -ENODEV;
if (!desc->ops) {
dev_err(dev, "error: no matching DT descriptor ops\n");
return -ENODEV;
}
sof_pdata->desc = desc;
sof_pdata->dev = &pdev->dev;
sof_pdata->fw_filename = desc->default_fw_filename[SOF_IPC];
if (fw_path)
sof_pdata->fw_filename_prefix = fw_path;
else
sof_pdata->fw_filename_prefix = sof_pdata->desc->default_fw_path[SOF_IPC];
if (tplg_path)
sof_pdata->tplg_filename_prefix = tplg_path;
else
sof_pdata->tplg_filename_prefix = sof_pdata->desc->default_tplg_path[SOF_IPC];
/* set callback to be called on successful device probe to enable runtime_pm */
sof_pdata->sof_probe_complete = sof_of_probe_complete;
/* call sof helper for DSP hardware probe */
return snd_sof_device_probe(dev, sof_pdata);
}
EXPORT_SYMBOL(sof_of_probe);
int sof_of_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
/* call sof helper for DSP hardware remove */
snd_sof_device_remove(&pdev->dev);
return 0;
}
EXPORT_SYMBOL(sof_of_remove);
void sof_of_shutdown(struct platform_device *pdev)
{
snd_sof_device_shutdown(&pdev->dev);
}
EXPORT_SYMBOL(sof_of_shutdown);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/sof-of-dev.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Intel Corporation. All rights reserved.
//
//
#include <sound/sof/stream.h>
#include <sound/sof/control.h>
#include <trace/events/sof.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc3-priv.h"
#include "ops.h"
typedef void (*ipc3_rx_callback)(struct snd_sof_dev *sdev, void *msg_buf);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
static void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
{
u8 *str;
u8 *str2 = NULL;
u32 glb;
u32 type;
bool is_sof_ipc_stream_position = false;
glb = cmd & SOF_GLB_TYPE_MASK;
type = cmd & SOF_CMD_TYPE_MASK;
switch (glb) {
case SOF_IPC_GLB_REPLY:
str = "GLB_REPLY"; break;
case SOF_IPC_GLB_COMPOUND:
str = "GLB_COMPOUND"; break;
case SOF_IPC_GLB_TPLG_MSG:
str = "GLB_TPLG_MSG";
switch (type) {
case SOF_IPC_TPLG_COMP_NEW:
str2 = "COMP_NEW"; break;
case SOF_IPC_TPLG_COMP_FREE:
str2 = "COMP_FREE"; break;
case SOF_IPC_TPLG_COMP_CONNECT:
str2 = "COMP_CONNECT"; break;
case SOF_IPC_TPLG_PIPE_NEW:
str2 = "PIPE_NEW"; break;
case SOF_IPC_TPLG_PIPE_FREE:
str2 = "PIPE_FREE"; break;
case SOF_IPC_TPLG_PIPE_CONNECT:
str2 = "PIPE_CONNECT"; break;
case SOF_IPC_TPLG_PIPE_COMPLETE:
str2 = "PIPE_COMPLETE"; break;
case SOF_IPC_TPLG_BUFFER_NEW:
str2 = "BUFFER_NEW"; break;
case SOF_IPC_TPLG_BUFFER_FREE:
str2 = "BUFFER_FREE"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_PM_MSG:
str = "GLB_PM_MSG";
switch (type) {
case SOF_IPC_PM_CTX_SAVE:
str2 = "CTX_SAVE"; break;
case SOF_IPC_PM_CTX_RESTORE:
str2 = "CTX_RESTORE"; break;
case SOF_IPC_PM_CTX_SIZE:
str2 = "CTX_SIZE"; break;
case SOF_IPC_PM_CLK_SET:
str2 = "CLK_SET"; break;
case SOF_IPC_PM_CLK_GET:
str2 = "CLK_GET"; break;
case SOF_IPC_PM_CLK_REQ:
str2 = "CLK_REQ"; break;
case SOF_IPC_PM_CORE_ENABLE:
str2 = "CORE_ENABLE"; break;
case SOF_IPC_PM_GATE:
str2 = "GATE"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_COMP_MSG:
str = "GLB_COMP_MSG";
switch (type) {
case SOF_IPC_COMP_SET_VALUE:
str2 = "SET_VALUE"; break;
case SOF_IPC_COMP_GET_VALUE:
str2 = "GET_VALUE"; break;
case SOF_IPC_COMP_SET_DATA:
str2 = "SET_DATA"; break;
case SOF_IPC_COMP_GET_DATA:
str2 = "GET_DATA"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_STREAM_MSG:
str = "GLB_STREAM_MSG";
switch (type) {
case SOF_IPC_STREAM_PCM_PARAMS:
str2 = "PCM_PARAMS"; break;
case SOF_IPC_STREAM_PCM_PARAMS_REPLY:
str2 = "PCM_REPLY"; break;
case SOF_IPC_STREAM_PCM_FREE:
str2 = "PCM_FREE"; break;
case SOF_IPC_STREAM_TRIG_START:
str2 = "TRIG_START"; break;
case SOF_IPC_STREAM_TRIG_STOP:
str2 = "TRIG_STOP"; break;
case SOF_IPC_STREAM_TRIG_PAUSE:
str2 = "TRIG_PAUSE"; break;
case SOF_IPC_STREAM_TRIG_RELEASE:
str2 = "TRIG_RELEASE"; break;
case SOF_IPC_STREAM_TRIG_DRAIN:
str2 = "TRIG_DRAIN"; break;
case SOF_IPC_STREAM_TRIG_XRUN:
str2 = "TRIG_XRUN"; break;
case SOF_IPC_STREAM_POSITION:
is_sof_ipc_stream_position = true;
str2 = "POSITION"; break;
case SOF_IPC_STREAM_VORBIS_PARAMS:
str2 = "VORBIS_PARAMS"; break;
case SOF_IPC_STREAM_VORBIS_FREE:
str2 = "VORBIS_FREE"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_FW_READY:
str = "FW_READY"; break;
case SOF_IPC_GLB_DAI_MSG:
str = "GLB_DAI_MSG";
switch (type) {
case SOF_IPC_DAI_CONFIG:
str2 = "CONFIG"; break;
case SOF_IPC_DAI_LOOPBACK:
str2 = "LOOPBACK"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_TRACE_MSG:
str = "GLB_TRACE_MSG";
switch (type) {
case SOF_IPC_TRACE_DMA_PARAMS:
str2 = "DMA_PARAMS"; break;
case SOF_IPC_TRACE_DMA_POSITION:
if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
return;
str2 = "DMA_POSITION"; break;
case SOF_IPC_TRACE_DMA_PARAMS_EXT:
str2 = "DMA_PARAMS_EXT"; break;
case SOF_IPC_TRACE_FILTER_UPDATE:
str2 = "FILTER_UPDATE"; break;
case SOF_IPC_TRACE_DMA_FREE:
str2 = "DMA_FREE"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_TEST_MSG:
str = "GLB_TEST_MSG";
switch (type) {
case SOF_IPC_TEST_IPC_FLOOD:
str2 = "IPC_FLOOD"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_DEBUG:
str = "GLB_DEBUG";
switch (type) {
case SOF_IPC_DEBUG_MEM_USAGE:
str2 = "MEM_USAGE"; break;
default:
str2 = "unknown type"; break;
}
break;
case SOF_IPC_GLB_PROBE:
str = "GLB_PROBE";
switch (type) {
case SOF_IPC_PROBE_INIT:
str2 = "INIT"; break;
case SOF_IPC_PROBE_DEINIT:
str2 = "DEINIT"; break;
case SOF_IPC_PROBE_DMA_ADD:
str2 = "DMA_ADD"; break;
case SOF_IPC_PROBE_DMA_INFO:
str2 = "DMA_INFO"; break;
case SOF_IPC_PROBE_DMA_REMOVE:
str2 = "DMA_REMOVE"; break;
case SOF_IPC_PROBE_POINT_ADD:
str2 = "POINT_ADD"; break;
case SOF_IPC_PROBE_POINT_INFO:
str2 = "POINT_INFO"; break;
case SOF_IPC_PROBE_POINT_REMOVE:
str2 = "POINT_REMOVE"; break;
default:
str2 = "unknown type"; break;
}
break;
default:
str = "unknown GLB command"; break;
}
if (str2) {
if (is_sof_ipc_stream_position)
trace_sof_stream_position_ipc_rx(dev);
else
dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2);
} else {
dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str);
}
}
#else
static inline void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
{
if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG)
dev_dbg(dev, "%s: 0x%x\n", text, cmd);
}
#endif
static void sof_ipc3_dump_payload(struct snd_sof_dev *sdev,
void *ipc_data, size_t size)
{
printk(KERN_DEBUG "Size of payload following the header: %zu\n", size);
print_hex_dump_debug("Message payload: ", DUMP_PREFIX_OFFSET,
16, 4, ipc_data, size, false);
}
static int sof_ipc3_get_reply(struct snd_sof_dev *sdev)
{
struct snd_sof_ipc_msg *msg = sdev->msg;
struct sof_ipc_reply *reply;
int ret = 0;
/* get the generic reply */
reply = msg->reply_data;
snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset, reply, sizeof(*reply));
if (reply->error < 0)
return reply->error;
if (!reply->hdr.size) {
/* Reply should always be >= sizeof(struct sof_ipc_reply) */
if (msg->reply_size)
dev_err(sdev->dev,
"empty reply received, expected %zu bytes\n",
msg->reply_size);
else
dev_err(sdev->dev, "empty reply received\n");
return -EINVAL;
}
if (msg->reply_size > 0) {
if (reply->hdr.size == msg->reply_size) {
ret = 0;
} else if (reply->hdr.size < msg->reply_size) {
dev_dbg(sdev->dev,
"reply size (%u) is less than expected (%zu)\n",
reply->hdr.size, msg->reply_size);
msg->reply_size = reply->hdr.size;
ret = 0;
} else {
dev_err(sdev->dev,
"reply size (%u) exceeds the buffer size (%zu)\n",
reply->hdr.size, msg->reply_size);
ret = -EINVAL;
}
/*
* get the full message if reply->hdr.size <= msg->reply_size
* and the reply->hdr.size > sizeof(struct sof_ipc_reply)
*/
if (!ret && msg->reply_size > sizeof(*reply))
snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset,
msg->reply_data, msg->reply_size);
}
return ret;
}
/* wait for IPC message reply */
static int ipc3_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data)
{
struct snd_sof_ipc_msg *msg = &ipc->msg;
struct sof_ipc_cmd_hdr *hdr = msg->msg_data;
struct snd_sof_dev *sdev = ipc->sdev;
int ret;
/* wait for DSP IPC completion */
ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
msecs_to_jiffies(sdev->ipc_timeout));
if (ret == 0) {
dev_err(sdev->dev,
"ipc tx timed out for %#x (msg/reply size: %d/%zu)\n",
hdr->cmd, hdr->size, msg->reply_size);
snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout");
ret = -ETIMEDOUT;
} else {
ret = msg->reply_error;
if (ret < 0) {
dev_err(sdev->dev,
"ipc tx error for %#x (msg/reply size: %d/%zu): %d\n",
hdr->cmd, hdr->size, msg->reply_size, ret);
} else {
if (sof_debug_check_flag(SOF_DBG_PRINT_IPC_SUCCESS_LOGS))
ipc3_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd);
if (reply_data && msg->reply_size)
/* copy the data returned from DSP */
memcpy(reply_data, msg->reply_data,
msg->reply_size);
}
/* re-enable dumps after successful IPC tx */
if (sdev->ipc_dump_printed) {
sdev->dbg_dump_printed = false;
sdev->ipc_dump_printed = false;
}
}
return ret;
}
/* send IPC message from host to DSP */
static int ipc3_tx_msg_unlocked(struct snd_sof_ipc *ipc,
void *msg_data, size_t msg_bytes,
void *reply_data, size_t reply_bytes)
{
struct sof_ipc_cmd_hdr *hdr = msg_data;
struct snd_sof_dev *sdev = ipc->sdev;
int ret;
ipc3_log_header(sdev->dev, "ipc tx", hdr->cmd);
ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes);
if (ret) {
dev_err_ratelimited(sdev->dev,
"%s: ipc message send for %#x failed: %d\n",
__func__, hdr->cmd, ret);
return ret;
}
/* now wait for completion */
return ipc3_wait_tx_done(ipc, reply_data);
}
static int sof_ipc3_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
void *reply_data, size_t reply_bytes, bool no_pm)
{
struct snd_sof_ipc *ipc = sdev->ipc;
int ret;
if (!msg_data || msg_bytes < sizeof(struct sof_ipc_cmd_hdr)) {
dev_err_ratelimited(sdev->dev, "No IPC message to send\n");
return -EINVAL;
}
if (!no_pm) {
const struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D0,
};
/* ensure the DSP is in D0 before sending a new IPC */
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
if (ret < 0) {
dev_err(sdev->dev, "%s: resuming DSP failed: %d\n",
__func__, ret);
return ret;
}
}
/* Serialise IPC TX */
mutex_lock(&ipc->tx_mutex);
ret = ipc3_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes);
if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
size_t payload_bytes, header_bytes;
char *payload = NULL;
/* payload is indicated by non zero msg/reply_bytes */
if (msg_bytes > sizeof(struct sof_ipc_cmd_hdr)) {
payload = msg_data;
header_bytes = sizeof(struct sof_ipc_cmd_hdr);
payload_bytes = msg_bytes - header_bytes;
} else if (reply_bytes > sizeof(struct sof_ipc_reply)) {
payload = reply_data;
header_bytes = sizeof(struct sof_ipc_reply);
payload_bytes = reply_bytes - header_bytes;
}
if (payload) {
payload += header_bytes;
sof_ipc3_dump_payload(sdev, payload, payload_bytes);
}
}
mutex_unlock(&ipc->tx_mutex);
return ret;
}
static int sof_ipc3_set_get_data(struct snd_sof_dev *sdev, void *data, size_t data_bytes,
bool set)
{
size_t msg_bytes, hdr_bytes, payload_size, send_bytes;
struct sof_ipc_ctrl_data *cdata = data;
struct sof_ipc_ctrl_data *cdata_chunk;
struct snd_sof_ipc *ipc = sdev->ipc;
size_t offset = 0;
u8 *src, *dst;
u32 num_msg;
int ret = 0;
int i;
if (!cdata || data_bytes < sizeof(*cdata))
return -EINVAL;
if ((cdata->rhdr.hdr.cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_COMP_MSG) {
dev_err(sdev->dev, "%s: Not supported message type of %#x\n",
__func__, cdata->rhdr.hdr.cmd);
return -EINVAL;
}
/* send normal size ipc in one part */
if (cdata->rhdr.hdr.size <= ipc->max_payload_size)
return sof_ipc3_tx_msg(sdev, cdata, cdata->rhdr.hdr.size,
cdata, cdata->rhdr.hdr.size, false);
cdata_chunk = kzalloc(ipc->max_payload_size, GFP_KERNEL);
if (!cdata_chunk)
return -ENOMEM;
switch (cdata->type) {
case SOF_CTRL_TYPE_VALUE_CHAN_GET:
case SOF_CTRL_TYPE_VALUE_CHAN_SET:
hdr_bytes = sizeof(struct sof_ipc_ctrl_data);
if (set) {
src = (u8 *)cdata->chanv;
dst = (u8 *)cdata_chunk->chanv;
} else {
src = (u8 *)cdata_chunk->chanv;
dst = (u8 *)cdata->chanv;
}
break;
case SOF_CTRL_TYPE_DATA_GET:
case SOF_CTRL_TYPE_DATA_SET:
hdr_bytes = sizeof(struct sof_ipc_ctrl_data) + sizeof(struct sof_abi_hdr);
if (set) {
src = (u8 *)cdata->data->data;
dst = (u8 *)cdata_chunk->data->data;
} else {
src = (u8 *)cdata_chunk->data->data;
dst = (u8 *)cdata->data->data;
}
break;
default:
kfree(cdata_chunk);
return -EINVAL;
}
msg_bytes = cdata->rhdr.hdr.size - hdr_bytes;
payload_size = ipc->max_payload_size - hdr_bytes;
num_msg = DIV_ROUND_UP(msg_bytes, payload_size);
/* copy the header data */
memcpy(cdata_chunk, cdata, hdr_bytes);
/* Serialise IPC TX */
mutex_lock(&sdev->ipc->tx_mutex);
/* copy the payload data in a loop */
for (i = 0; i < num_msg; i++) {
send_bytes = min(msg_bytes, payload_size);
cdata_chunk->num_elems = send_bytes;
cdata_chunk->rhdr.hdr.size = hdr_bytes + send_bytes;
cdata_chunk->msg_index = i;
msg_bytes -= send_bytes;
cdata_chunk->elems_remaining = msg_bytes;
if (set)
memcpy(dst, src + offset, send_bytes);
ret = ipc3_tx_msg_unlocked(sdev->ipc,
cdata_chunk, cdata_chunk->rhdr.hdr.size,
cdata_chunk, cdata_chunk->rhdr.hdr.size);
if (ret < 0)
break;
if (!set)
memcpy(dst + offset, src, send_bytes);
offset += payload_size;
}
if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
size_t header_bytes = sizeof(struct sof_ipc_reply);
char *payload = (char *)cdata;
payload += header_bytes;
sof_ipc3_dump_payload(sdev, payload, data_bytes - header_bytes);
}
mutex_unlock(&sdev->ipc->tx_mutex);
kfree(cdata_chunk);
return ret;
}
int sof_ipc3_get_ext_windows(struct snd_sof_dev *sdev,
const struct sof_ipc_ext_data_hdr *ext_hdr)
{
const struct sof_ipc_window *w =
container_of(ext_hdr, struct sof_ipc_window, ext_hdr);
if (w->num_windows == 0 || w->num_windows > SOF_IPC_MAX_ELEMS)
return -EINVAL;
if (sdev->info_window) {
if (memcmp(sdev->info_window, w, ext_hdr->hdr.size)) {
dev_err(sdev->dev, "mismatch between window descriptor from extended manifest and mailbox");
return -EINVAL;
}
return 0;
}
/* keep a local copy of the data */
sdev->info_window = devm_kmemdup(sdev->dev, w, ext_hdr->hdr.size, GFP_KERNEL);
if (!sdev->info_window)
return -ENOMEM;
return 0;
}
int sof_ipc3_get_cc_info(struct snd_sof_dev *sdev,
const struct sof_ipc_ext_data_hdr *ext_hdr)
{
int ret;
const struct sof_ipc_cc_version *cc =
container_of(ext_hdr, struct sof_ipc_cc_version, ext_hdr);
if (sdev->cc_version) {
if (memcmp(sdev->cc_version, cc, cc->ext_hdr.hdr.size)) {
dev_err(sdev->dev,
"Receive diverged cc_version descriptions");
return -EINVAL;
}
return 0;
}
dev_dbg(sdev->dev,
"Firmware info: used compiler %s %d:%d:%d%s used optimization flags %s\n",
cc->name, cc->major, cc->minor, cc->micro, cc->desc, cc->optim);
/* create read-only cc_version debugfs to store compiler version info */
/* use local copy of the cc_version to prevent data corruption */
if (sdev->first_boot) {
sdev->cc_version = devm_kmemdup(sdev->dev, cc, cc->ext_hdr.hdr.size, GFP_KERNEL);
if (!sdev->cc_version)
return -ENOMEM;
ret = snd_sof_debugfs_buf_item(sdev, sdev->cc_version,
cc->ext_hdr.hdr.size,
"cc_version", 0444);
/* errors are only due to memory allocation, not debugfs */
if (ret < 0) {
dev_err(sdev->dev, "snd_sof_debugfs_buf_item failed\n");
return ret;
}
}
return 0;
}
/* parse the extended FW boot data structures from FW boot message */
static int ipc3_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 offset)
{
struct sof_ipc_ext_data_hdr *ext_hdr;
void *ext_data;
int ret = 0;
ext_data = kzalloc(PAGE_SIZE, GFP_KERNEL);
if (!ext_data)
return -ENOMEM;
/* get first header */
snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
sizeof(*ext_hdr));
ext_hdr = ext_data;
while (ext_hdr->hdr.cmd == SOF_IPC_FW_READY) {
/* read in ext structure */
snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM,
offset + sizeof(*ext_hdr),
(void *)((u8 *)ext_data + sizeof(*ext_hdr)),
ext_hdr->hdr.size - sizeof(*ext_hdr));
dev_dbg(sdev->dev, "found ext header type %d size 0x%x\n",
ext_hdr->type, ext_hdr->hdr.size);
/* process structure data */
switch (ext_hdr->type) {
case SOF_IPC_EXT_WINDOW:
ret = sof_ipc3_get_ext_windows(sdev, ext_hdr);
break;
case SOF_IPC_EXT_CC_INFO:
ret = sof_ipc3_get_cc_info(sdev, ext_hdr);
break;
case SOF_IPC_EXT_UNUSED:
case SOF_IPC_EXT_PROBE_INFO:
case SOF_IPC_EXT_USER_ABI_INFO:
/* They are supported but we don't do anything here */
break;
default:
dev_info(sdev->dev, "unknown ext header type %d size 0x%x\n",
ext_hdr->type, ext_hdr->hdr.size);
ret = 0;
break;
}
if (ret < 0) {
dev_err(sdev->dev, "Failed to parse ext data type %d\n",
ext_hdr->type);
break;
}
/* move to next header */
offset += ext_hdr->hdr.size;
snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
sizeof(*ext_hdr));
ext_hdr = ext_data;
}
kfree(ext_data);
return ret;
}
static void ipc3_get_windows(struct snd_sof_dev *sdev)
{
struct sof_ipc_window_elem *elem;
u32 outbox_offset = 0;
u32 stream_offset = 0;
u32 inbox_offset = 0;
u32 outbox_size = 0;
u32 stream_size = 0;
u32 inbox_size = 0;
u32 debug_size = 0;
u32 debug_offset = 0;
int window_offset;
int i;
if (!sdev->info_window) {
dev_err(sdev->dev, "%s: No window info present\n", __func__);
return;
}
for (i = 0; i < sdev->info_window->num_windows; i++) {
elem = &sdev->info_window->window[i];
window_offset = snd_sof_dsp_get_window_offset(sdev, elem->id);
if (window_offset < 0) {
dev_warn(sdev->dev, "No offset for window %d\n", elem->id);
continue;
}
switch (elem->type) {
case SOF_IPC_REGION_UPBOX:
inbox_offset = window_offset + elem->offset;
inbox_size = elem->size;
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
inbox_offset,
elem->size, "inbox",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
case SOF_IPC_REGION_DOWNBOX:
outbox_offset = window_offset + elem->offset;
outbox_size = elem->size;
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
outbox_offset,
elem->size, "outbox",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
case SOF_IPC_REGION_TRACE:
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
window_offset + elem->offset,
elem->size, "etrace",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
case SOF_IPC_REGION_DEBUG:
debug_offset = window_offset + elem->offset;
debug_size = elem->size;
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
window_offset + elem->offset,
elem->size, "debug",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
case SOF_IPC_REGION_STREAM:
stream_offset = window_offset + elem->offset;
stream_size = elem->size;
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
stream_offset,
elem->size, "stream",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
case SOF_IPC_REGION_REGS:
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
window_offset + elem->offset,
elem->size, "regs",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
case SOF_IPC_REGION_EXCEPTION:
sdev->dsp_oops_offset = window_offset + elem->offset;
snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
window_offset + elem->offset,
elem->size, "exception",
SOF_DEBUGFS_ACCESS_D0_ONLY);
break;
default:
dev_err(sdev->dev, "%s: Illegal window info: %u\n",
__func__, elem->type);
return;
}
}
if (outbox_size == 0 || inbox_size == 0) {
dev_err(sdev->dev, "%s: Illegal mailbox window\n", __func__);
return;
}
sdev->dsp_box.offset = inbox_offset;
sdev->dsp_box.size = inbox_size;
sdev->host_box.offset = outbox_offset;
sdev->host_box.size = outbox_size;
sdev->stream_box.offset = stream_offset;
sdev->stream_box.size = stream_size;
sdev->debug_box.offset = debug_offset;
sdev->debug_box.size = debug_size;
dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
inbox_offset, inbox_size);
dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
outbox_offset, outbox_size);
dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
stream_offset, stream_size);
dev_dbg(sdev->dev, " debug region 0x%x - size 0x%x\n",
debug_offset, debug_size);
}
static int ipc3_init_reply_data_buffer(struct snd_sof_dev *sdev)
{
struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
msg->reply_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL);
if (!msg->reply_data)
return -ENOMEM;
sdev->ipc->max_payload_size = SOF_IPC_MSG_MAX_SIZE;
return 0;
}
int sof_ipc3_validate_fw_version(struct snd_sof_dev *sdev)
{
struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
struct sof_ipc_fw_version *v = &ready->version;
dev_info(sdev->dev,
"Firmware info: version %d:%d:%d-%s\n", v->major, v->minor,
v->micro, v->tag);
dev_info(sdev->dev,
"Firmware: ABI %d:%d:%d Kernel ABI %d:%d:%d\n",
SOF_ABI_VERSION_MAJOR(v->abi_version),
SOF_ABI_VERSION_MINOR(v->abi_version),
SOF_ABI_VERSION_PATCH(v->abi_version),
SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) {
dev_err(sdev->dev, "incompatible FW ABI version\n");
return -EINVAL;
}
if (IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS) &&
SOF_ABI_VERSION_MINOR(v->abi_version) > SOF_ABI_MINOR) {
dev_err(sdev->dev, "FW ABI is more recent than kernel\n");
return -EINVAL;
}
if (ready->flags & SOF_IPC_INFO_BUILD) {
dev_info(sdev->dev,
"Firmware debug build %d on %s-%s - options:\n"
" GDB: %s\n"
" lock debug: %s\n"
" lock vdebug: %s\n",
v->build, v->date, v->time,
(ready->flags & SOF_IPC_INFO_GDB) ?
"enabled" : "disabled",
(ready->flags & SOF_IPC_INFO_LOCKS) ?
"enabled" : "disabled",
(ready->flags & SOF_IPC_INFO_LOCKSV) ?
"enabled" : "disabled");
}
/* copy the fw_version into debugfs at first boot */
memcpy(&sdev->fw_version, v, sizeof(*v));
return 0;
}
static int ipc3_fw_ready(struct snd_sof_dev *sdev, u32 cmd)
{
struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
int offset;
int ret;
/* mailbox must be on 4k boundary */
offset = snd_sof_dsp_get_mailbox_offset(sdev);
if (offset < 0) {
dev_err(sdev->dev, "%s: no mailbox offset\n", __func__);
return offset;
}
dev_dbg(sdev->dev, "DSP is ready 0x%8.8x offset 0x%x\n", cmd, offset);
/* no need to re-check version/ABI for subsequent boots */
if (!sdev->first_boot)
return 0;
/*
* copy data from the DSP FW ready offset
* Subsequent error handling is not needed for BLK_TYPE_SRAM
*/
ret = snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, fw_ready,
sizeof(*fw_ready));
if (ret) {
dev_err(sdev->dev,
"Unable to read fw_ready, read from TYPE_SRAM failed\n");
return ret;
}
/* make sure ABI version is compatible */
ret = sof_ipc3_validate_fw_version(sdev);
if (ret < 0)
return ret;
/* now check for extended data */
ipc3_fw_parse_ext_data(sdev, offset + sizeof(struct sof_ipc_fw_ready));
ipc3_get_windows(sdev);
return ipc3_init_reply_data_buffer(sdev);
}
/* IPC stream position. */
static void ipc3_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id)
{
struct snd_soc_component *scomp = sdev->component;
struct snd_sof_pcm_stream *stream;
struct sof_ipc_stream_posn posn;
struct snd_sof_pcm *spcm;
int direction, ret;
spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
if (!spcm) {
dev_err(sdev->dev, "period elapsed for unknown stream, msg_id %d\n",
msg_id);
return;
}
stream = &spcm->stream[direction];
ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
if (ret < 0) {
dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
return;
}
trace_sof_ipc3_period_elapsed_position(sdev, &posn);
memcpy(&stream->posn, &posn, sizeof(posn));
if (spcm->pcm.compress)
snd_sof_compr_fragment_elapsed(stream->cstream);
else if (stream->substream->runtime &&
!stream->substream->runtime->no_period_wakeup)
/* only inform ALSA for period_wakeup mode */
snd_sof_pcm_period_elapsed(stream->substream);
}
/* DSP notifies host of an XRUN within FW */
static void ipc3_xrun(struct snd_sof_dev *sdev, u32 msg_id)
{
struct snd_soc_component *scomp = sdev->component;
struct snd_sof_pcm_stream *stream;
struct sof_ipc_stream_posn posn;
struct snd_sof_pcm *spcm;
int direction, ret;
spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
if (!spcm) {
dev_err(sdev->dev, "XRUN for unknown stream, msg_id %d\n",
msg_id);
return;
}
stream = &spcm->stream[direction];
ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
if (ret < 0) {
dev_warn(sdev->dev, "failed to read overrun position: %d\n", ret);
return;
}
dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n",
posn.host_posn, posn.xrun_comp_id, posn.xrun_size);
#if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP)
/* stop PCM on XRUN - used for pipeline debug */
memcpy(&stream->posn, &posn, sizeof(posn));
snd_pcm_stop_xrun(stream->substream);
#endif
}
/* stream notifications from firmware */
static void ipc3_stream_message(struct snd_sof_dev *sdev, void *msg_buf)
{
struct sof_ipc_cmd_hdr *hdr = msg_buf;
u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
u32 msg_id = SOF_IPC_MESSAGE_ID(hdr->cmd);
switch (msg_type) {
case SOF_IPC_STREAM_POSITION:
ipc3_period_elapsed(sdev, msg_id);
break;
case SOF_IPC_STREAM_TRIG_XRUN:
ipc3_xrun(sdev, msg_id);
break;
default:
dev_err(sdev->dev, "unhandled stream message %#x\n",
msg_id);
break;
}
}
/* component notifications from firmware */
static void ipc3_comp_notification(struct snd_sof_dev *sdev, void *msg_buf)
{
const struct sof_ipc_tplg_ops *tplg_ops = sdev->ipc->ops->tplg;
struct sof_ipc_cmd_hdr *hdr = msg_buf;
u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
switch (msg_type) {
case SOF_IPC_COMP_GET_VALUE:
case SOF_IPC_COMP_GET_DATA:
break;
default:
dev_err(sdev->dev, "unhandled component message %#x\n", msg_type);
return;
}
if (tplg_ops->control->update)
tplg_ops->control->update(sdev, msg_buf);
}
static void ipc3_trace_message(struct snd_sof_dev *sdev, void *msg_buf)
{
struct sof_ipc_cmd_hdr *hdr = msg_buf;
u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
switch (msg_type) {
case SOF_IPC_TRACE_DMA_POSITION:
ipc3_dtrace_posn_update(sdev, msg_buf);
break;
default:
dev_err(sdev->dev, "unhandled trace message %#x\n", msg_type);
break;
}
}
void sof_ipc3_do_rx_work(struct snd_sof_dev *sdev, struct sof_ipc_cmd_hdr *hdr, void *msg_buf)
{
ipc3_rx_callback rx_callback = NULL;
u32 cmd;
int err;
ipc3_log_header(sdev->dev, "ipc rx", hdr->cmd);
if (hdr->size < sizeof(*hdr) || hdr->size > SOF_IPC_MSG_MAX_SIZE) {
dev_err(sdev->dev, "The received message size is invalid: %u\n",
hdr->size);
return;
}
cmd = hdr->cmd & SOF_GLB_TYPE_MASK;
/* check message type */
switch (cmd) {
case SOF_IPC_GLB_REPLY:
dev_err(sdev->dev, "ipc reply unknown\n");
break;
case SOF_IPC_FW_READY:
/* check for FW boot completion */
if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
err = ipc3_fw_ready(sdev, cmd);
if (err < 0)
sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED);
else
sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK);
/* wake up firmware loader */
wake_up(&sdev->boot_wait);
}
break;
case SOF_IPC_GLB_COMPOUND:
case SOF_IPC_GLB_TPLG_MSG:
case SOF_IPC_GLB_PM_MSG:
break;
case SOF_IPC_GLB_COMP_MSG:
rx_callback = ipc3_comp_notification;
break;
case SOF_IPC_GLB_STREAM_MSG:
rx_callback = ipc3_stream_message;
break;
case SOF_IPC_GLB_TRACE_MSG:
rx_callback = ipc3_trace_message;
break;
default:
dev_err(sdev->dev, "%s: Unknown DSP message: 0x%x\n", __func__, cmd);
break;
}
/* Call local handler for the message */
if (rx_callback)
rx_callback(sdev, msg_buf);
/* Notify registered clients */
sof_client_ipc_rx_dispatcher(sdev, msg_buf);
ipc3_log_header(sdev->dev, "ipc rx done", hdr->cmd);
}
EXPORT_SYMBOL(sof_ipc3_do_rx_work);
/* DSP firmware has sent host a message */
static void sof_ipc3_rx_msg(struct snd_sof_dev *sdev)
{
struct sof_ipc_cmd_hdr hdr;
void *msg_buf;
int err;
/* read back header */
err = snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr));
if (err < 0) {
dev_warn(sdev->dev, "failed to read IPC header: %d\n", err);
return;
}
if (hdr.size < sizeof(hdr)) {
dev_err(sdev->dev, "The received message size is invalid\n");
return;
}
/* read the full message */
msg_buf = kmalloc(hdr.size, GFP_KERNEL);
if (!msg_buf)
return;
err = snd_sof_ipc_msg_data(sdev, NULL, msg_buf, hdr.size);
if (err < 0) {
dev_err(sdev->dev, "%s: Failed to read message: %d\n", __func__, err);
kfree(msg_buf);
return;
}
sof_ipc3_do_rx_work(sdev, &hdr, msg_buf);
kfree(msg_buf);
}
static int sof_ipc3_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
{
struct sof_ipc_pm_core_config core_cfg = {
.hdr.size = sizeof(core_cfg),
.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
};
if (on)
core_cfg.enable_mask = sdev->enabled_cores_mask | BIT(core_idx);
else
core_cfg.enable_mask = sdev->enabled_cores_mask & ~BIT(core_idx);
return sof_ipc3_tx_msg(sdev, &core_cfg, sizeof(core_cfg), NULL, 0, false);
}
static int sof_ipc3_ctx_ipc(struct snd_sof_dev *sdev, int cmd)
{
struct sof_ipc_pm_ctx pm_ctx = {
.hdr.size = sizeof(pm_ctx),
.hdr.cmd = SOF_IPC_GLB_PM_MSG | cmd,
};
/* send ctx save ipc to dsp */
return sof_ipc3_tx_msg(sdev, &pm_ctx, sizeof(pm_ctx), NULL, 0, false);
}
static int sof_ipc3_ctx_save(struct snd_sof_dev *sdev)
{
return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_SAVE);
}
static int sof_ipc3_ctx_restore(struct snd_sof_dev *sdev)
{
return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_RESTORE);
}
static int sof_ipc3_set_pm_gate(struct snd_sof_dev *sdev, u32 flags)
{
struct sof_ipc_pm_gate pm_gate;
memset(&pm_gate, 0, sizeof(pm_gate));
/* configure pm_gate ipc message */
pm_gate.hdr.size = sizeof(pm_gate);
pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
pm_gate.flags = flags;
/* send pm_gate ipc to dsp */
return sof_ipc_tx_message_no_pm_no_reply(sdev->ipc, &pm_gate, sizeof(pm_gate));
}
static const struct sof_ipc_pm_ops ipc3_pm_ops = {
.ctx_save = sof_ipc3_ctx_save,
.ctx_restore = sof_ipc3_ctx_restore,
.set_core_state = sof_ipc3_set_core_state,
.set_pm_gate = sof_ipc3_set_pm_gate,
};
const struct sof_ipc_ops ipc3_ops = {
.tplg = &ipc3_tplg_ops,
.pm = &ipc3_pm_ops,
.pcm = &ipc3_pcm_ops,
.fw_loader = &ipc3_loader_ops,
.fw_tracing = &ipc3_dtrace_ops,
.tx_msg = sof_ipc3_tx_msg,
.rx_msg = sof_ipc3_rx_msg,
.set_get_data = sof_ipc3_set_get_data,
.get_reply = sof_ipc3_get_reply,
};
| linux-master | sound/soc/sof/ipc3.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
#include "sof-priv.h"
int sof_fw_trace_init(struct snd_sof_dev *sdev)
{
const struct sof_ipc_fw_tracing_ops *fw_tracing = sof_ipc_get_ops(sdev, fw_tracing);
if (!fw_tracing) {
dev_info(sdev->dev, "Firmware tracing is not available\n");
sdev->fw_trace_is_supported = false;
return 0;
}
return fw_tracing->init(sdev);
}
void sof_fw_trace_free(struct snd_sof_dev *sdev)
{
if (!sdev->fw_trace_is_supported)
return;
if (sdev->ipc->ops->fw_tracing->free)
sdev->ipc->ops->fw_tracing->free(sdev);
}
void sof_fw_trace_fw_crashed(struct snd_sof_dev *sdev)
{
if (!sdev->fw_trace_is_supported)
return;
if (sdev->ipc->ops->fw_tracing->fw_crashed)
sdev->ipc->ops->fw_tracing->fw_crashed(sdev);
}
void sof_fw_trace_suspend(struct snd_sof_dev *sdev, pm_message_t pm_state)
{
if (!sdev->fw_trace_is_supported)
return;
sdev->ipc->ops->fw_tracing->suspend(sdev, pm_state);
}
int sof_fw_trace_resume(struct snd_sof_dev *sdev)
{
if (!sdev->fw_trace_is_supported)
return 0;
return sdev->ipc->ops->fw_tracing->resume(sdev);
}
| linux-master | sound/soc/sof/trace.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
#include <linux/debugfs.h>
#include <linux/sched/signal.h>
#include <sound/sof/ipc4/header.h>
#include "sof-priv.h"
#include "ipc4-priv.h"
/*
* debug info window is organized in 16 (equal sized) pages:
*
* ------------------------
* | Page0 - descriptors |
* ------------------------
* | Page1 - slot0 |
* ------------------------
* | Page2 - slot1 |
* ------------------------
* | ... |
* ------------------------
* | Page14 - slot13 |
* ------------------------
* | Page15 - slot14 |
* ------------------------
*
* The slot size == page size
*
* The first page contains descriptors for the remaining 15 cores
* The slot descriptor is:
* u32 res_id;
* u32 type;
* u32 vma;
*
* Log buffer slots have the following layout:
* u32 host_read_ptr;
* u32 dsp_write_ptr;
* u8 buffer[];
*
* The two pointers are offsets within the buffer.
*/
#define SOF_MTRACE_DESCRIPTOR_SIZE 12 /* 3 x u32 */
#define FW_EPOCH_DELTA 11644473600LL
#define INVALID_SLOT_OFFSET 0xffffffff
#define MAX_ALLOWED_LIBRARIES 16
#define MAX_MTRACE_SLOTS 15
#define SOF_MTRACE_PAGE_SIZE 0x1000
#define SOF_MTRACE_SLOT_SIZE SOF_MTRACE_PAGE_SIZE
/* debug log slot types */
#define SOF_MTRACE_SLOT_UNUSED 0x00000000
#define SOF_MTRACE_SLOT_CRITICAL_LOG 0x54524300 /* byte 0: core ID */
#define SOF_MTRACE_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */
#define SOF_MTRACE_SLOT_GDB_STUB 0x42444700
#define SOF_MTRACE_SLOT_TELEMETRY 0x4c455400
#define SOF_MTRACE_SLOT_BROKEN 0x44414544
/* for debug and critical types */
#define SOF_MTRACE_SLOT_CORE_MASK GENMASK(7, 0)
#define SOF_MTRACE_SLOT_TYPE_MASK GENMASK(31, 8)
#define DEFAULT_AGING_TIMER_PERIOD_MS 0x100
#define DEFAULT_FIFO_FULL_TIMER_PERIOD_MS 0x1000
/* ipc4 log level and source definitions for logs_priorities_mask */
#define SOF_MTRACE_LOG_LEVEL_CRITICAL BIT(0)
#define SOF_MTRACE_LOG_LEVEL_ERROR BIT(1)
#define SOF_MTRACE_LOG_LEVEL_WARNING BIT(2)
#define SOF_MTRACE_LOG_LEVEL_INFO BIT(3)
#define SOF_MTRACE_LOG_LEVEL_VERBOSE BIT(4)
#define SOF_MTRACE_LOG_SOURCE_INFRA BIT(5) /* log source 0 */
#define SOF_MTRACE_LOG_SOURCE_HAL BIT(6)
#define SOF_MTRACE_LOG_SOURCE_MODULE BIT(7)
#define SOF_MTRACE_LOG_SOURCE_AUDIO BIT(8)
#define SOF_MTRACE_LOG_SOURCE_SCHEDULER BIT(9)
#define SOF_MTRACE_LOG_SOURCE_ULP_INFRA BIT(10)
#define SOF_MTRACE_LOG_SOURCE_ULP_MODULE BIT(11)
#define SOF_MTRACE_LOG_SOURCE_VISION BIT(12) /* log source 7 */
#define DEFAULT_LOGS_PRIORITIES_MASK (SOF_MTRACE_LOG_LEVEL_CRITICAL | \
SOF_MTRACE_LOG_LEVEL_ERROR | \
SOF_MTRACE_LOG_LEVEL_WARNING | \
SOF_MTRACE_LOG_LEVEL_INFO | \
SOF_MTRACE_LOG_SOURCE_INFRA | \
SOF_MTRACE_LOG_SOURCE_HAL | \
SOF_MTRACE_LOG_SOURCE_MODULE | \
SOF_MTRACE_LOG_SOURCE_AUDIO)
struct sof_log_state_info {
u32 aging_timer_period;
u32 fifo_full_timer_period;
u32 enable;
u32 logs_priorities_mask[MAX_ALLOWED_LIBRARIES];
} __packed;
enum sof_mtrace_state {
SOF_MTRACE_DISABLED,
SOF_MTRACE_INITIALIZING,
SOF_MTRACE_ENABLED,
};
struct sof_mtrace_core_data {
struct snd_sof_dev *sdev;
int id;
u32 slot_offset;
void *log_buffer;
struct mutex buffer_lock; /* for log_buffer alloc/free */
u32 host_read_ptr;
u32 dsp_write_ptr;
/* pos update IPC arrived before the slot offset is known, queried */
bool delayed_pos_update;
wait_queue_head_t trace_sleep;
};
struct sof_mtrace_priv {
struct snd_sof_dev *sdev;
enum sof_mtrace_state mtrace_state;
struct sof_log_state_info state_info;
struct sof_mtrace_core_data cores[];
};
static int sof_ipc4_mtrace_dfs_open(struct inode *inode, struct file *file)
{
struct sof_mtrace_core_data *core_data = inode->i_private;
int ret;
mutex_lock(&core_data->buffer_lock);
if (core_data->log_buffer) {
ret = -EBUSY;
goto out;
}
ret = debugfs_file_get(file->f_path.dentry);
if (unlikely(ret))
goto out;
core_data->log_buffer = kmalloc(SOF_MTRACE_SLOT_SIZE, GFP_KERNEL);
if (!core_data->log_buffer) {
debugfs_file_put(file->f_path.dentry);
ret = -ENOMEM;
goto out;
}
ret = simple_open(inode, file);
if (ret) {
kfree(core_data->log_buffer);
debugfs_file_put(file->f_path.dentry);
}
out:
mutex_unlock(&core_data->buffer_lock);
return ret;
}
static bool sof_wait_mtrace_avail(struct sof_mtrace_core_data *core_data)
{
wait_queue_entry_t wait;
/* data immediately available */
if (core_data->host_read_ptr != core_data->dsp_write_ptr)
return true;
/* wait for available trace data from FW */
init_waitqueue_entry(&wait, current);
set_current_state(TASK_INTERRUPTIBLE);
add_wait_queue(&core_data->trace_sleep, &wait);
if (!signal_pending(current)) {
/* set timeout to max value, no error code */
schedule_timeout(MAX_SCHEDULE_TIMEOUT);
}
remove_wait_queue(&core_data->trace_sleep, &wait);
if (core_data->host_read_ptr != core_data->dsp_write_ptr)
return true;
return false;
}
static ssize_t sof_ipc4_mtrace_dfs_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_mtrace_core_data *core_data = file->private_data;
u32 log_buffer_offset, log_buffer_size, read_ptr, write_ptr;
struct snd_sof_dev *sdev = core_data->sdev;
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
void *log_buffer = core_data->log_buffer;
loff_t lpos = *ppos;
u32 avail;
int ret;
/* check pos and count */
if (lpos < 0)
return -EINVAL;
if (!count || count < sizeof(avail))
return 0;
/* get available count based on current host offset */
if (!sof_wait_mtrace_avail(core_data)) {
/* No data available */
avail = 0;
if (copy_to_user(buffer, &avail, sizeof(avail)))
return -EFAULT;
return 0;
}
if (core_data->slot_offset == INVALID_SLOT_OFFSET)
return 0;
/* The log data buffer starts after the two pointer in the slot */
log_buffer_offset = core_data->slot_offset + (sizeof(u32) * 2);
/* The log data size excludes the pointers */
log_buffer_size = SOF_MTRACE_SLOT_SIZE - (sizeof(u32) * 2);
read_ptr = core_data->host_read_ptr;
write_ptr = core_data->dsp_write_ptr;
if (read_ptr < write_ptr)
avail = write_ptr - read_ptr;
else
avail = log_buffer_size - read_ptr + write_ptr;
if (!avail)
return 0;
if (avail > log_buffer_size)
avail = log_buffer_size;
/* Need space for the initial u32 of the avail */
if (avail > count - sizeof(avail))
avail = count - sizeof(avail);
if (sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
dev_dbg(sdev->dev,
"core%d, host read: %#x, dsp write: %#x, avail: %#x\n",
core_data->id, read_ptr, write_ptr, avail);
if (read_ptr < write_ptr) {
/* Read data between read pointer and write pointer */
sof_mailbox_read(sdev, log_buffer_offset + read_ptr, log_buffer, avail);
} else {
/* read from read pointer to end of the slot */
sof_mailbox_read(sdev, log_buffer_offset + read_ptr, log_buffer,
avail - write_ptr);
/* read from slot start to write pointer */
if (write_ptr)
sof_mailbox_read(sdev, log_buffer_offset,
(u8 *)(log_buffer) + avail - write_ptr,
write_ptr);
}
/* first write the number of bytes we have gathered */
ret = copy_to_user(buffer, &avail, sizeof(avail));
if (ret)
return -EFAULT;
/* Followed by the data itself */
ret = copy_to_user(buffer + sizeof(avail), log_buffer, avail);
if (ret)
return -EFAULT;
/* Update the host_read_ptr in the slot for this core */
read_ptr += avail;
if (read_ptr >= log_buffer_size)
read_ptr -= log_buffer_size;
sof_mailbox_write(sdev, core_data->slot_offset, &read_ptr, sizeof(read_ptr));
/* Only update the host_read_ptr if mtrace is enabled */
if (priv->mtrace_state != SOF_MTRACE_DISABLED)
core_data->host_read_ptr = read_ptr;
/*
* Ask for a new buffer from user space for the next chunk, not
* streaming due to the heading number of bytes value.
*/
*ppos += count;
return count;
}
static int sof_ipc4_mtrace_dfs_release(struct inode *inode, struct file *file)
{
struct sof_mtrace_core_data *core_data = inode->i_private;
debugfs_file_put(file->f_path.dentry);
mutex_lock(&core_data->buffer_lock);
kfree(core_data->log_buffer);
core_data->log_buffer = NULL;
mutex_unlock(&core_data->buffer_lock);
return 0;
}
static const struct file_operations sof_dfs_mtrace_fops = {
.open = sof_ipc4_mtrace_dfs_open,
.read = sof_ipc4_mtrace_dfs_read,
.llseek = default_llseek,
.release = sof_ipc4_mtrace_dfs_release,
.owner = THIS_MODULE,
};
static ssize_t sof_ipc4_priority_mask_dfs_read(struct file *file, char __user *to,
size_t count, loff_t *ppos)
{
struct sof_mtrace_priv *priv = file->private_data;
int i, ret, offset, remaining;
char *buf;
/*
* one entry (14 char + new line = 15):
* " 0: 000001ef"
*
* 16 * 15 + 1 = 241
*/
buf = kzalloc(241, GFP_KERNEL);
if (!buf)
return -ENOMEM;
for (i = 0; i < MAX_ALLOWED_LIBRARIES; i++) {
offset = strlen(buf);
remaining = 241 - offset;
snprintf(buf + offset, remaining, "%2d: 0x%08x\n", i,
priv->state_info.logs_priorities_mask[i]);
}
ret = simple_read_from_buffer(to, count, ppos, buf, strlen(buf));
kfree(buf);
return ret;
}
static ssize_t sof_ipc4_priority_mask_dfs_write(struct file *file,
const char __user *from,
size_t count, loff_t *ppos)
{
struct sof_mtrace_priv *priv = file->private_data;
unsigned int id;
char *buf;
u32 mask;
int ret;
/*
* To update Nth mask entry, write:
* "N,0x1234" or "N,1234" to the debugfs file
* The mask will be interpreted as hexadecimal number
*/
buf = memdup_user_nul(from, count);
if (IS_ERR(buf))
return PTR_ERR(buf);
ret = sscanf(buf, "%u,0x%x", &id, &mask);
if (ret != 2) {
ret = sscanf(buf, "%u,%x", &id, &mask);
if (ret != 2) {
ret = -EINVAL;
goto out;
}
}
if (id >= MAX_ALLOWED_LIBRARIES) {
ret = -EINVAL;
goto out;
}
priv->state_info.logs_priorities_mask[id] = mask;
ret = count;
out:
kfree(buf);
return ret;
}
static const struct file_operations sof_dfs_priority_mask_fops = {
.open = simple_open,
.read = sof_ipc4_priority_mask_dfs_read,
.write = sof_ipc4_priority_mask_dfs_write,
.llseek = default_llseek,
.owner = THIS_MODULE,
};
static int mtrace_debugfs_create(struct snd_sof_dev *sdev)
{
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
struct dentry *dfs_root;
char dfs_name[100];
int i;
dfs_root = debugfs_create_dir("mtrace", sdev->debugfs_root);
if (IS_ERR_OR_NULL(dfs_root))
return 0;
/* Create files for the logging parameters */
debugfs_create_u32("aging_timer_period", 0644, dfs_root,
&priv->state_info.aging_timer_period);
debugfs_create_u32("fifo_full_timer_period", 0644, dfs_root,
&priv->state_info.fifo_full_timer_period);
debugfs_create_file("logs_priorities_mask", 0644, dfs_root, priv,
&sof_dfs_priority_mask_fops);
/* Separate log files per core */
for (i = 0; i < sdev->num_cores; i++) {
snprintf(dfs_name, sizeof(dfs_name), "core%d", i);
debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i],
&sof_dfs_mtrace_fops);
}
return 0;
}
static int ipc4_mtrace_enable(struct snd_sof_dev *sdev)
{
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
const struct sof_ipc_ops *iops = sdev->ipc->ops;
struct sof_ipc4_msg msg;
u64 system_time;
ktime_t kt;
int ret;
if (priv->mtrace_state != SOF_MTRACE_DISABLED)
return 0;
msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_SYSTEM_TIME);
/* The system time is in usec, UTC, epoch is 1601-01-01 00:00:00 */
kt = ktime_add_us(ktime_get_real(), FW_EPOCH_DELTA * USEC_PER_SEC);
system_time = ktime_to_us(kt);
msg.data_size = sizeof(system_time);
msg.data_ptr = &system_time;
ret = iops->set_get_data(sdev, &msg, msg.data_size, true);
if (ret)
return ret;
msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_ENABLE_LOGS);
priv->state_info.enable = 1;
msg.data_size = sizeof(priv->state_info);
msg.data_ptr = &priv->state_info;
priv->mtrace_state = SOF_MTRACE_INITIALIZING;
ret = iops->set_get_data(sdev, &msg, msg.data_size, true);
if (ret) {
priv->mtrace_state = SOF_MTRACE_DISABLED;
return ret;
}
priv->mtrace_state = SOF_MTRACE_ENABLED;
return 0;
}
static void ipc4_mtrace_disable(struct snd_sof_dev *sdev)
{
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
const struct sof_ipc_ops *iops = sdev->ipc->ops;
struct sof_ipc4_msg msg;
int i;
if (priv->mtrace_state == SOF_MTRACE_DISABLED)
return;
msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_ENABLE_LOGS);
priv->state_info.enable = 0;
msg.data_size = sizeof(priv->state_info);
msg.data_ptr = &priv->state_info;
iops->set_get_data(sdev, &msg, msg.data_size, true);
priv->mtrace_state = SOF_MTRACE_DISABLED;
for (i = 0; i < sdev->num_cores; i++) {
struct sof_mtrace_core_data *core_data = &priv->cores[i];
core_data->host_read_ptr = 0;
core_data->dsp_write_ptr = 0;
wake_up(&core_data->trace_sleep);
}
}
/*
* Each DSP core logs to a dedicated slot.
* Parse the slot descriptors at debug_box offset to find the debug log slots
* and map them to cores.
* There are 15 slots and therefore 15 descriptors to check (MAX_MTRACE_SLOTS)
*/
static void sof_mtrace_find_core_slots(struct snd_sof_dev *sdev)
{
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
struct sof_mtrace_core_data *core_data;
u32 slot_desc_type_offset, type, core;
int i;
for (i = 0; i < MAX_MTRACE_SLOTS; i++) {
/* The type is the second u32 in the slot descriptor */
slot_desc_type_offset = sdev->debug_box.offset;
slot_desc_type_offset += SOF_MTRACE_DESCRIPTOR_SIZE * i + sizeof(u32);
sof_mailbox_read(sdev, slot_desc_type_offset, &type, sizeof(type));
if ((type & SOF_MTRACE_SLOT_TYPE_MASK) == SOF_MTRACE_SLOT_DEBUG_LOG) {
core = type & SOF_MTRACE_SLOT_CORE_MASK;
if (core >= sdev->num_cores) {
dev_dbg(sdev->dev, "core%u is invalid for slot%d\n",
core, i);
continue;
}
core_data = &priv->cores[core];
/*
* The area reserved for descriptors have the same size
* as a slot.
* In other words: slot0 starts at
* debug_box + SOF_MTRACE_SLOT_SIZE offset
*/
core_data->slot_offset = sdev->debug_box.offset;
core_data->slot_offset += SOF_MTRACE_SLOT_SIZE * (i + 1);
dev_dbg(sdev->dev, "slot%d is used for core%u\n", i, core);
if (core_data->delayed_pos_update) {
sof_ipc4_mtrace_update_pos(sdev, core);
core_data->delayed_pos_update = false;
}
} else if (type) {
dev_dbg(sdev->dev, "slot%d is not a log slot (%#x)\n", i, type);
}
}
}
static int ipc4_mtrace_init(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_mtrace_priv *priv;
int i, ret;
if (sdev->fw_trace_data) {
dev_err(sdev->dev, "fw_trace_data has been already allocated\n");
return -EBUSY;
}
if (!ipc4_data->mtrace_log_bytes ||
ipc4_data->mtrace_type != SOF_IPC4_MTRACE_INTEL_CAVS_2) {
sdev->fw_trace_is_supported = false;
return 0;
}
priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
sdev->fw_trace_data = priv;
/* Set initial values for mtrace parameters */
priv->state_info.aging_timer_period = DEFAULT_AGING_TIMER_PERIOD_MS;
priv->state_info.fifo_full_timer_period = DEFAULT_FIFO_FULL_TIMER_PERIOD_MS;
/* Only enable basefw logs initially (index 0 is always basefw) */
priv->state_info.logs_priorities_mask[0] = DEFAULT_LOGS_PRIORITIES_MASK;
for (i = 0; i < sdev->num_cores; i++) {
struct sof_mtrace_core_data *core_data = &priv->cores[i];
init_waitqueue_head(&core_data->trace_sleep);
mutex_init(&core_data->buffer_lock);
core_data->sdev = sdev;
core_data->id = i;
}
ret = ipc4_mtrace_enable(sdev);
if (ret) {
/*
* Mark firmware tracing as not supported and return 0 to not
* block the whole audio stack
*/
sdev->fw_trace_is_supported = false;
dev_dbg(sdev->dev, "initialization failed, fw tracing is disabled\n");
return 0;
}
sof_mtrace_find_core_slots(sdev);
ret = mtrace_debugfs_create(sdev);
if (ret)
ipc4_mtrace_disable(sdev);
return ret;
}
static void ipc4_mtrace_free(struct snd_sof_dev *sdev)
{
ipc4_mtrace_disable(sdev);
}
static int sof_ipc4_mtrace_update_pos_all_cores(struct snd_sof_dev *sdev)
{
int i;
for (i = 0; i < sdev->num_cores; i++)
sof_ipc4_mtrace_update_pos(sdev, i);
return 0;
}
int sof_ipc4_mtrace_update_pos(struct snd_sof_dev *sdev, int core)
{
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
struct sof_mtrace_core_data *core_data;
if (!sdev->fw_trace_is_supported ||
priv->mtrace_state == SOF_MTRACE_DISABLED)
return 0;
if (core >= sdev->num_cores)
return -EINVAL;
core_data = &priv->cores[core];
if (core_data->slot_offset == INVALID_SLOT_OFFSET) {
core_data->delayed_pos_update = true;
return 0;
}
/* Read out the dsp_write_ptr from the slot for this core */
sof_mailbox_read(sdev, core_data->slot_offset + sizeof(u32),
&core_data->dsp_write_ptr, 4);
core_data->dsp_write_ptr -= core_data->dsp_write_ptr % 4;
if (sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
dev_dbg(sdev->dev, "core%d, host read: %#x, dsp write: %#x",
core, core_data->host_read_ptr, core_data->dsp_write_ptr);
wake_up(&core_data->trace_sleep);
return 0;
}
static void ipc4_mtrace_fw_crashed(struct snd_sof_dev *sdev)
{
/*
* The DSP might not be able to send SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS
* messages anymore, so check the log buffer status on all
* cores and process any pending messages.
*/
sof_ipc4_mtrace_update_pos_all_cores(sdev);
}
static int ipc4_mtrace_resume(struct snd_sof_dev *sdev)
{
return ipc4_mtrace_enable(sdev);
}
static void ipc4_mtrace_suspend(struct snd_sof_dev *sdev, pm_message_t pm_state)
{
ipc4_mtrace_disable(sdev);
}
const struct sof_ipc_fw_tracing_ops ipc4_mtrace_ops = {
.init = ipc4_mtrace_init,
.free = ipc4_mtrace_free,
.fw_crashed = ipc4_mtrace_fw_crashed,
.suspend = ipc4_mtrace_suspend,
.resume = ipc4_mtrace_resume,
};
| linux-master | sound/soc/sof/ipc4-mtrace.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2019-2022 Intel Corporation. All rights reserved.
//
// Author: Jyri Sarha <[email protected]>
//
#include <sound/soc.h>
#include <sound/sof/ipc4/header.h>
#include <uapi/sound/sof/header.h>
#include "sof-priv.h"
#include "ipc4-priv.h"
#include "sof-client.h"
#include "sof-client-probes.h"
enum sof_ipc4_dma_type {
SOF_IPC4_DMA_HDA_HOST_OUTPUT = 0,
SOF_IPC4_DMA_HDA_HOST_INPUT = 1,
SOF_IPC4_DMA_HDA_LINK_OUTPUT = 8,
SOF_IPC4_DMA_HDA_LINK_INPUT = 9,
SOF_IPC4_DMA_DMIC_LINK_INPUT = 11,
SOF_IPC4_DMA_I2S_LINK_OUTPUT = 12,
SOF_IPC4_DMA_I2S_LINK_INPUT = 13,
};
enum sof_ipc4_probe_runtime_param {
SOF_IPC4_PROBE_INJECTION_DMA = 1,
SOF_IPC4_PROBE_INJECTION_DMA_DETACH,
SOF_IPC4_PROBE_POINTS,
SOF_IPC4_PROBE_POINTS_DISCONNECT,
};
struct sof_ipc4_probe_gtw_cfg {
u32 node_id;
u32 dma_buffer_size;
} __packed __aligned(4);
#define SOF_IPC4_PROBE_NODE_ID_INDEX(x) ((x) & GENMASK(7, 0))
#define SOF_IPC4_PROBE_NODE_ID_TYPE(x) (((x) << 8) & GENMASK(12, 8))
struct sof_ipc4_probe_cfg {
struct sof_ipc4_base_module_cfg base;
struct sof_ipc4_probe_gtw_cfg gtw_cfg;
} __packed __aligned(4);
enum sof_ipc4_probe_type {
SOF_IPC4_PROBE_TYPE_INPUT = 0,
SOF_IPC4_PROBE_TYPE_OUTPUT,
SOF_IPC4_PROBE_TYPE_INTERNAL
};
struct sof_ipc4_probe_point {
u32 point_id;
u32 purpose;
u32 stream_tag;
} __packed __aligned(4);
#define INVALID_PIPELINE_ID 0xFF
/**
* sof_ipc4_probe_get_module_info - Get IPC4 module info for probe module
* @cdev: SOF client device
* @return: Pointer to IPC4 probe module info
*
* Look up the IPC4 probe module info based on the hard coded uuid and
* store the value for the future calls.
*/
static struct sof_man4_module *sof_ipc4_probe_get_module_info(struct sof_client_dev *cdev)
{
struct sof_probes_priv *priv = cdev->data;
struct device *dev = &cdev->auxdev.dev;
static const guid_t probe_uuid =
GUID_INIT(0x7CAD0808, 0xAB10, 0xCD23,
0xEF, 0x45, 0x12, 0xAB, 0x34, 0xCD, 0x56, 0xEF);
if (!priv->ipc_priv) {
struct sof_ipc4_fw_module *fw_module =
sof_client_ipc4_find_module(cdev, &probe_uuid);
if (!fw_module) {
dev_err(dev, "%s: no matching uuid found", __func__);
return NULL;
}
priv->ipc_priv = &fw_module->man4_module_entry;
}
return (struct sof_man4_module *)priv->ipc_priv;
}
/**
* ipc4_probes_init - initialize data probing
* @cdev: SOF client device
* @stream_tag: Extractor stream tag
* @buffer_size: DMA buffer size to set for extractor
* @return: 0 on success, negative error code on error
*
* Host chooses whether extraction is supported or not by providing
* valid stream tag to DSP. Once specified, stream described by that
* tag will be tied to DSP for extraction for the entire lifetime of
* probe.
*
* Probing is initialized only once and each INIT request must be
* matched by DEINIT call.
*/
static int ipc4_probes_init(struct sof_client_dev *cdev, u32 stream_tag,
size_t buffer_size)
{
struct sof_man4_module *mentry = sof_ipc4_probe_get_module_info(cdev);
struct sof_ipc4_msg msg;
struct sof_ipc4_probe_cfg cfg;
if (!mentry)
return -ENODEV;
memset(&cfg, '\0', sizeof(cfg));
cfg.gtw_cfg.node_id = SOF_IPC4_PROBE_NODE_ID_INDEX(stream_tag - 1) |
SOF_IPC4_PROBE_NODE_ID_TYPE(SOF_IPC4_DMA_HDA_HOST_INPUT);
cfg.gtw_cfg.dma_buffer_size = buffer_size;
msg.primary = mentry->id;
msg.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_INIT_INSTANCE);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension = SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(INVALID_PIPELINE_ID);
msg.extension |= SOF_IPC4_MOD_EXT_CORE_ID(0);
msg.data_size = sizeof(cfg);
msg.data_ptr = &cfg;
return sof_client_ipc_tx_message_no_reply(cdev, &msg);
}
/**
* ipc4_probes_deinit - cleanup after data probing
* @cdev: SOF client device
* @return: 0 on success, negative error code on error
*
* Host sends DEINIT request to free previously initialized probe
* on DSP side once it is no longer needed. DEINIT only when there
* are no probes connected and with all injectors detached.
*/
static int ipc4_probes_deinit(struct sof_client_dev *cdev)
{
struct sof_man4_module *mentry = sof_ipc4_probe_get_module_info(cdev);
struct sof_ipc4_msg msg;
if (!mentry)
return -ENODEV;
msg.primary = mentry->id;
msg.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_DELETE_INSTANCE);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension = SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(INVALID_PIPELINE_ID);
msg.extension |= SOF_IPC4_MOD_EXT_CORE_ID(0);
msg.data_size = 0;
msg.data_ptr = NULL;
return sof_client_ipc_tx_message_no_reply(cdev, &msg);
}
/**
* ipc4_probes_points_info - retrieve list of active probe points
* @cdev: SOF client device
* @desc: Returned list of active probes
* @num_desc: Returned count of active probes
* @return: 0 on success, negative error code on error
*
* Dummy implementation returning empty list of probes.
*/
static int ipc4_probes_points_info(struct sof_client_dev *cdev,
struct sof_probe_point_desc **desc,
size_t *num_desc)
{
/* TODO: Firmware side implementation needed first */
*desc = NULL;
*num_desc = 0;
return 0;
}
/**
* ipc4_probes_points_add - connect specified probes
* @cdev: SOF client device
* @desc: List of probe points to connect
* @num_desc: Number of elements in @desc
* @return: 0 on success, negative error code on error
*
* Translates the generic probe point presentation to an IPC4
* message to dynamically connect the provided set of endpoints.
*/
static int ipc4_probes_points_add(struct sof_client_dev *cdev,
struct sof_probe_point_desc *desc,
size_t num_desc)
{
struct sof_man4_module *mentry = sof_ipc4_probe_get_module_info(cdev);
struct sof_ipc4_probe_point *points;
struct sof_ipc4_msg msg;
int i, ret;
if (!mentry)
return -ENODEV;
/* The sof_probe_point_desc and sof_ipc4_probe_point structs
* are of same size and even the integers are the same in the
* same order, and similar meaning, but since there is no
* performance issue I wrote the conversion explicitly open for
* future development.
*/
points = kcalloc(num_desc, sizeof(*points), GFP_KERNEL);
if (!points)
return -ENOMEM;
for (i = 0; i < num_desc; i++) {
points[i].point_id = desc[i].buffer_id;
points[i].purpose = desc[i].purpose;
points[i].stream_tag = desc[i].stream_tag;
}
msg.primary = mentry->id;
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_PROBE_POINTS);
msg.data_size = sizeof(*points) * num_desc;
msg.data_ptr = points;
ret = sof_client_ipc_set_get_data(cdev, &msg, true);
kfree(points);
return ret;
}
/**
* ipc4_probes_points_remove - disconnect specified probes
* @cdev: SOF client device
* @buffer_id: List of probe points to disconnect
* @num_buffer_id: Number of elements in @desc
* @return: 0 on success, negative error code on error
*
* Converts the generic buffer_id to IPC4 probe_point_id and remove
* the probe points with an IPC4 for message.
*/
static int ipc4_probes_points_remove(struct sof_client_dev *cdev,
unsigned int *buffer_id, size_t num_buffer_id)
{
struct sof_man4_module *mentry = sof_ipc4_probe_get_module_info(cdev);
struct sof_ipc4_msg msg;
u32 *probe_point_ids;
int i, ret;
if (!mentry)
return -ENODEV;
probe_point_ids = kcalloc(num_buffer_id, sizeof(*probe_point_ids),
GFP_KERNEL);
if (!probe_point_ids)
return -ENOMEM;
for (i = 0; i < num_buffer_id; i++)
probe_point_ids[i] = buffer_id[i];
msg.primary = mentry->id;
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension =
SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_PROBE_POINTS_DISCONNECT);
msg.data_size = num_buffer_id * sizeof(*probe_point_ids);
msg.data_ptr = probe_point_ids;
ret = sof_client_ipc_set_get_data(cdev, &msg, true);
kfree(probe_point_ids);
return ret;
}
const struct sof_probes_ipc_ops ipc4_probe_ops = {
.init = ipc4_probes_init,
.deinit = ipc4_probes_deinit,
.points_info = ipc4_probes_points_info,
.points_add = ipc4_probes_points_add,
.points_remove = ipc4_probes_points_remove,
};
| linux-master | sound/soc/sof/sof-client-probes-ipc4.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2023 Google Inc. All rights reserved.
//
// Author: Curtis Malainey <[email protected]>
//
#include <linux/auxiliary_bus.h>
#include <linux/debugfs.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <sound/sof/header.h>
#include "sof-client.h"
#define SOF_IPC_CLIENT_SUSPEND_DELAY_MS 3000
struct sof_msg_inject_priv {
struct dentry *kernel_dfs_file;
size_t max_msg_size;
void *kernel_buffer;
};
static int sof_msg_inject_dfs_open(struct inode *inode, struct file *file)
{
int ret = debugfs_file_get(file->f_path.dentry);
if (unlikely(ret))
return ret;
ret = simple_open(inode, file);
if (ret)
debugfs_file_put(file->f_path.dentry);
return ret;
}
static ssize_t sof_kernel_msg_inject_dfs_write(struct file *file, const char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_msg_inject_priv *priv = cdev->data;
struct sof_ipc_cmd_hdr *hdr = priv->kernel_buffer;
struct device *dev = &cdev->auxdev.dev;
ssize_t size;
int ret;
if (*ppos)
return 0;
size = simple_write_to_buffer(priv->kernel_buffer, priv->max_msg_size,
ppos, buffer, count);
if (size < 0)
return size;
if (size != count)
return -EFAULT;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(dev, "debugfs write failed to resume %d\n", ret);
return ret;
}
sof_client_ipc_rx_message(cdev, hdr, priv->kernel_buffer);
pm_runtime_mark_last_busy(dev);
ret = pm_runtime_put_autosuspend(dev);
if (ret < 0)
dev_err_ratelimited(dev, "debugfs write failed to idle %d\n", ret);
return count;
};
static int sof_msg_inject_dfs_release(struct inode *inode, struct file *file)
{
debugfs_file_put(file->f_path.dentry);
return 0;
}
static const struct file_operations sof_kernel_msg_inject_fops = {
.open = sof_msg_inject_dfs_open,
.write = sof_kernel_msg_inject_dfs_write,
.release = sof_msg_inject_dfs_release,
.owner = THIS_MODULE,
};
static int sof_msg_inject_probe(struct auxiliary_device *auxdev,
const struct auxiliary_device_id *id)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct dentry *debugfs_root = sof_client_get_debugfs_root(cdev);
struct device *dev = &auxdev->dev;
struct sof_msg_inject_priv *priv;
size_t alloc_size;
/* allocate memory for client data */
priv = devm_kzalloc(&auxdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->max_msg_size = sof_client_get_ipc_max_payload_size(cdev);
alloc_size = priv->max_msg_size;
priv->kernel_buffer = devm_kmalloc(dev, alloc_size, GFP_KERNEL);
if (!priv->kernel_buffer)
return -ENOMEM;
cdev->data = priv;
priv->kernel_dfs_file = debugfs_create_file("kernel_ipc_msg_inject", 0644,
debugfs_root, cdev,
&sof_kernel_msg_inject_fops);
/* enable runtime PM */
pm_runtime_set_autosuspend_delay(dev, SOF_IPC_CLIENT_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_idle(dev);
return 0;
}
static void sof_msg_inject_remove(struct auxiliary_device *auxdev)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct sof_msg_inject_priv *priv = cdev->data;
pm_runtime_disable(&auxdev->dev);
debugfs_remove(priv->kernel_dfs_file);
}
static const struct auxiliary_device_id sof_msg_inject_client_id_table[] = {
{ .name = "snd_sof.kernel_injector" },
{},
};
MODULE_DEVICE_TABLE(auxiliary, sof_msg_inject_client_id_table);
/*
* No need for driver pm_ops as the generic pm callbacks in the auxiliary bus
* type are enough to ensure that the parent SOF device resumes to bring the DSP
* back to D0.
* Driver name will be set based on KBUILD_MODNAME.
*/
static struct auxiliary_driver sof_msg_inject_client_drv = {
.probe = sof_msg_inject_probe,
.remove = sof_msg_inject_remove,
.id_table = sof_msg_inject_client_id_table,
};
module_auxiliary_driver(sof_msg_inject_client_drv);
MODULE_DESCRIPTION("SOF IPC Kernel Injector Client Driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_CLIENT);
| linux-master | sound/soc/sof/sof-client-ipc-kernel-injector.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
// Authors: Ranjani Sridharan <[email protected]>
// Peter Ujfalusi <[email protected]>
//
#include <linux/auxiliary_bus.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/ktime.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <sound/sof/header.h>
#include "sof-client.h"
#define MAX_IPC_FLOOD_DURATION_MS 1000
#define MAX_IPC_FLOOD_COUNT 10000
#define IPC_FLOOD_TEST_RESULT_LEN 512
#define SOF_IPC_CLIENT_SUSPEND_DELAY_MS 3000
#define DEBUGFS_IPC_FLOOD_COUNT "ipc_flood_count"
#define DEBUGFS_IPC_FLOOD_DURATION "ipc_flood_duration_ms"
struct sof_ipc_flood_priv {
struct dentry *dfs_root;
struct dentry *dfs_link[2];
char *buf;
};
static int sof_ipc_flood_dfs_open(struct inode *inode, struct file *file)
{
struct sof_client_dev *cdev = inode->i_private;
int ret;
if (sof_client_get_fw_state(cdev) == SOF_FW_CRASHED)
return -ENODEV;
ret = debugfs_file_get(file->f_path.dentry);
if (unlikely(ret))
return ret;
ret = simple_open(inode, file);
if (ret)
debugfs_file_put(file->f_path.dentry);
return ret;
}
/*
* helper function to perform the flood test. Only one of the two params, ipc_duration_ms
* or ipc_count, will be non-zero and will determine the type of test
*/
static int sof_debug_ipc_flood_test(struct sof_client_dev *cdev,
bool flood_duration_test,
unsigned long ipc_duration_ms,
unsigned long ipc_count)
{
struct sof_ipc_flood_priv *priv = cdev->data;
struct device *dev = &cdev->auxdev.dev;
struct sof_ipc_cmd_hdr hdr;
u64 min_response_time = U64_MAX;
ktime_t start, end, test_end;
u64 avg_response_time = 0;
u64 max_response_time = 0;
u64 ipc_response_time;
int i = 0;
int ret;
/* configure test IPC */
hdr.cmd = SOF_IPC_GLB_TEST_MSG | SOF_IPC_TEST_IPC_FLOOD;
hdr.size = sizeof(hdr);
/* set test end time for duration flood test */
if (flood_duration_test)
test_end = ktime_get_ns() + ipc_duration_ms * NSEC_PER_MSEC;
/* send test IPC's */
while (1) {
start = ktime_get();
ret = sof_client_ipc_tx_message_no_reply(cdev, &hdr);
end = ktime_get();
if (ret < 0)
break;
/* compute min and max response times */
ipc_response_time = ktime_to_ns(ktime_sub(end, start));
min_response_time = min(min_response_time, ipc_response_time);
max_response_time = max(max_response_time, ipc_response_time);
/* sum up response times */
avg_response_time += ipc_response_time;
i++;
/* test complete? */
if (flood_duration_test) {
if (ktime_to_ns(end) >= test_end)
break;
} else {
if (i == ipc_count)
break;
}
}
if (ret < 0)
dev_err(dev, "ipc flood test failed at %d iterations\n", i);
/* return if the first IPC fails */
if (!i)
return ret;
/* compute average response time */
do_div(avg_response_time, i);
/* clear previous test output */
memset(priv->buf, 0, IPC_FLOOD_TEST_RESULT_LEN);
if (!ipc_count) {
dev_dbg(dev, "IPC Flood test duration: %lums\n", ipc_duration_ms);
snprintf(priv->buf, IPC_FLOOD_TEST_RESULT_LEN,
"IPC Flood test duration: %lums\n", ipc_duration_ms);
}
dev_dbg(dev, "IPC Flood count: %d, Avg response time: %lluns\n",
i, avg_response_time);
dev_dbg(dev, "Max response time: %lluns\n", max_response_time);
dev_dbg(dev, "Min response time: %lluns\n", min_response_time);
/* format output string and save test results */
snprintf(priv->buf + strlen(priv->buf),
IPC_FLOOD_TEST_RESULT_LEN - strlen(priv->buf),
"IPC Flood count: %d\nAvg response time: %lluns\n",
i, avg_response_time);
snprintf(priv->buf + strlen(priv->buf),
IPC_FLOOD_TEST_RESULT_LEN - strlen(priv->buf),
"Max response time: %lluns\nMin response time: %lluns\n",
max_response_time, min_response_time);
return ret;
}
/*
* Writing to the debugfs entry initiates the IPC flood test based on
* the IPC count or the duration specified by the user.
*/
static ssize_t sof_ipc_flood_dfs_write(struct file *file, const char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct device *dev = &cdev->auxdev.dev;
unsigned long ipc_duration_ms = 0;
bool flood_duration_test = false;
unsigned long ipc_count = 0;
struct dentry *dentry;
int err;
size_t size;
char *string;
int ret;
string = kzalloc(count + 1, GFP_KERNEL);
if (!string)
return -ENOMEM;
size = simple_write_to_buffer(string, count, ppos, buffer, count);
/*
* write op is only supported for ipc_flood_count or
* ipc_flood_duration_ms debugfs entries atm.
* ipc_flood_count floods the DSP with the number of IPC's specified.
* ipc_duration_ms test floods the DSP for the time specified
* in the debugfs entry.
*/
dentry = file->f_path.dentry;
if (strcmp(dentry->d_name.name, DEBUGFS_IPC_FLOOD_COUNT) &&
strcmp(dentry->d_name.name, DEBUGFS_IPC_FLOOD_DURATION)) {
ret = -EINVAL;
goto out;
}
if (!strcmp(dentry->d_name.name, DEBUGFS_IPC_FLOOD_DURATION))
flood_duration_test = true;
/* test completion criterion */
if (flood_duration_test)
ret = kstrtoul(string, 0, &ipc_duration_ms);
else
ret = kstrtoul(string, 0, &ipc_count);
if (ret < 0)
goto out;
/* limit max duration/ipc count for flood test */
if (flood_duration_test) {
if (!ipc_duration_ms) {
ret = size;
goto out;
}
/* find the minimum. min() is not used to avoid warnings */
if (ipc_duration_ms > MAX_IPC_FLOOD_DURATION_MS)
ipc_duration_ms = MAX_IPC_FLOOD_DURATION_MS;
} else {
if (!ipc_count) {
ret = size;
goto out;
}
/* find the minimum. min() is not used to avoid warnings */
if (ipc_count > MAX_IPC_FLOOD_COUNT)
ipc_count = MAX_IPC_FLOOD_COUNT;
}
ret = pm_runtime_resume_and_get(dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(dev, "debugfs write failed to resume %d\n", ret);
goto out;
}
/* flood test */
ret = sof_debug_ipc_flood_test(cdev, flood_duration_test,
ipc_duration_ms, ipc_count);
pm_runtime_mark_last_busy(dev);
err = pm_runtime_put_autosuspend(dev);
if (err < 0)
dev_err_ratelimited(dev, "debugfs write failed to idle %d\n", err);
/* return size if test is successful */
if (ret >= 0)
ret = size;
out:
kfree(string);
return ret;
}
/* return the result of the last IPC flood test */
static ssize_t sof_ipc_flood_dfs_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_ipc_flood_priv *priv = cdev->data;
size_t size_ret;
struct dentry *dentry;
dentry = file->f_path.dentry;
if (!strcmp(dentry->d_name.name, DEBUGFS_IPC_FLOOD_COUNT) ||
!strcmp(dentry->d_name.name, DEBUGFS_IPC_FLOOD_DURATION)) {
if (*ppos)
return 0;
count = min_t(size_t, count, strlen(priv->buf));
size_ret = copy_to_user(buffer, priv->buf, count);
if (size_ret)
return -EFAULT;
*ppos += count;
return count;
}
return count;
}
static int sof_ipc_flood_dfs_release(struct inode *inode, struct file *file)
{
debugfs_file_put(file->f_path.dentry);
return 0;
}
static const struct file_operations sof_ipc_flood_fops = {
.open = sof_ipc_flood_dfs_open,
.read = sof_ipc_flood_dfs_read,
.llseek = default_llseek,
.write = sof_ipc_flood_dfs_write,
.release = sof_ipc_flood_dfs_release,
.owner = THIS_MODULE,
};
/*
* The IPC test client creates a couple of debugfs entries that will be used
* flood tests. Users can write to these entries to execute the IPC flood test
* by specifying either the number of IPCs to flood the DSP with or the duration
* (in ms) for which the DSP should be flooded with test IPCs. At the
* end of each test, the average, min and max response times are reported back.
* The results of the last flood test can be accessed by reading the debugfs
* entries.
*/
static int sof_ipc_flood_probe(struct auxiliary_device *auxdev,
const struct auxiliary_device_id *id)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct dentry *debugfs_root = sof_client_get_debugfs_root(cdev);
struct device *dev = &auxdev->dev;
struct sof_ipc_flood_priv *priv;
/* allocate memory for client data */
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->buf = devm_kmalloc(dev, IPC_FLOOD_TEST_RESULT_LEN, GFP_KERNEL);
if (!priv->buf)
return -ENOMEM;
cdev->data = priv;
/* create debugfs root folder with device name under parent SOF dir */
priv->dfs_root = debugfs_create_dir(dev_name(dev), debugfs_root);
if (!IS_ERR_OR_NULL(priv->dfs_root)) {
/* create read-write ipc_flood_count debugfs entry */
debugfs_create_file(DEBUGFS_IPC_FLOOD_COUNT, 0644, priv->dfs_root,
cdev, &sof_ipc_flood_fops);
/* create read-write ipc_flood_duration_ms debugfs entry */
debugfs_create_file(DEBUGFS_IPC_FLOOD_DURATION, 0644,
priv->dfs_root, cdev, &sof_ipc_flood_fops);
if (auxdev->id == 0) {
/*
* Create symlinks for backwards compatibility to the
* first IPC flood test instance
*/
char target[100];
snprintf(target, 100, "%s/" DEBUGFS_IPC_FLOOD_COUNT,
dev_name(dev));
priv->dfs_link[0] =
debugfs_create_symlink(DEBUGFS_IPC_FLOOD_COUNT,
debugfs_root, target);
snprintf(target, 100, "%s/" DEBUGFS_IPC_FLOOD_DURATION,
dev_name(dev));
priv->dfs_link[1] =
debugfs_create_symlink(DEBUGFS_IPC_FLOOD_DURATION,
debugfs_root, target);
}
}
/* enable runtime PM */
pm_runtime_set_autosuspend_delay(dev, SOF_IPC_CLIENT_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_idle(dev);
return 0;
}
static void sof_ipc_flood_remove(struct auxiliary_device *auxdev)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct sof_ipc_flood_priv *priv = cdev->data;
pm_runtime_disable(&auxdev->dev);
if (auxdev->id == 0) {
debugfs_remove(priv->dfs_link[0]);
debugfs_remove(priv->dfs_link[1]);
}
debugfs_remove_recursive(priv->dfs_root);
}
static const struct auxiliary_device_id sof_ipc_flood_client_id_table[] = {
{ .name = "snd_sof.ipc_flood" },
{},
};
MODULE_DEVICE_TABLE(auxiliary, sof_ipc_flood_client_id_table);
/*
* No need for driver pm_ops as the generic pm callbacks in the auxiliary bus
* type are enough to ensure that the parent SOF device resumes to bring the DSP
* back to D0.
* Driver name will be set based on KBUILD_MODNAME.
*/
static struct auxiliary_driver sof_ipc_flood_client_drv = {
.probe = sof_ipc_flood_probe,
.remove = sof_ipc_flood_remove,
.id_table = sof_ipc_flood_client_id_table,
};
module_auxiliary_driver(sof_ipc_flood_client_drv);
MODULE_DESCRIPTION("SOF IPC Flood Test Client Driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_CLIENT);
| linux-master | sound/soc/sof/sof-client-ipc-flood-test.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright 2021 NXP
//
// Author: Daniel Baluta <[email protected]>
#include <sound/soc.h>
#include <sound/sof.h>
#include <sound/compress_driver.h>
#include "sof-audio.h"
#include "sof-priv.h"
#include "sof-utils.h"
#include "ops.h"
static void sof_set_transferred_bytes(struct sof_compr_stream *sstream,
u64 host_pos, u64 buffer_size)
{
u64 prev_pos;
unsigned int copied;
div64_u64_rem(sstream->copied_total, buffer_size, &prev_pos);
if (host_pos < prev_pos)
copied = (buffer_size - prev_pos) + host_pos;
else
copied = host_pos - prev_pos;
sstream->copied_total += copied;
}
static void snd_sof_compr_fragment_elapsed_work(struct work_struct *work)
{
struct snd_sof_pcm_stream *sps =
container_of(work, struct snd_sof_pcm_stream,
period_elapsed_work);
snd_compr_fragment_elapsed(sps->cstream);
}
void snd_sof_compr_init_elapsed_work(struct work_struct *work)
{
INIT_WORK(work, snd_sof_compr_fragment_elapsed_work);
}
/*
* sof compr fragment elapse, this could be called in irq thread context
*/
void snd_sof_compr_fragment_elapsed(struct snd_compr_stream *cstream)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_compr_runtime *crtd;
struct snd_soc_component *component;
struct sof_compr_stream *sstream;
struct snd_sof_pcm *spcm;
if (!cstream)
return;
rtd = cstream->private_data;
crtd = cstream->runtime;
sstream = crtd->private_data;
component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm) {
dev_err(component->dev,
"fragment elapsed called for unknown stream!\n");
return;
}
sof_set_transferred_bytes(sstream, spcm->stream[cstream->direction].posn.host_posn,
crtd->buffer_size);
/* use the same workqueue-based solution as for PCM, cf. snd_sof_pcm_elapsed */
schedule_work(&spcm->stream[cstream->direction].period_elapsed_work);
}
static int create_page_table(struct snd_soc_component *component,
struct snd_compr_stream *cstream,
unsigned char *dma_area, size_t size)
{
struct snd_dma_buffer *dmab = cstream->runtime->dma_buffer_p;
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
int dir = cstream->direction;
struct snd_sof_pcm *spcm;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
return snd_sof_create_page_table(component->dev, dmab,
spcm->stream[dir].page_table.area, size);
}
static int sof_compr_open(struct snd_soc_component *component,
struct snd_compr_stream *cstream)
{
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
struct snd_compr_runtime *crtd = cstream->runtime;
struct sof_compr_stream *sstream;
struct snd_sof_pcm *spcm;
int dir;
sstream = kzalloc(sizeof(*sstream), GFP_KERNEL);
if (!sstream)
return -ENOMEM;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm) {
kfree(sstream);
return -EINVAL;
}
dir = cstream->direction;
if (spcm->stream[dir].cstream) {
kfree(sstream);
return -EBUSY;
}
spcm->stream[dir].cstream = cstream;
spcm->stream[dir].posn.host_posn = 0;
spcm->stream[dir].posn.dai_posn = 0;
spcm->prepared[dir] = false;
crtd->private_data = sstream;
return 0;
}
static int sof_compr_free(struct snd_soc_component *component,
struct snd_compr_stream *cstream)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct sof_compr_stream *sstream = cstream->runtime->private_data;
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
struct sof_ipc_stream stream;
struct snd_sof_pcm *spcm;
int ret = 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
stream.hdr.size = sizeof(stream);
stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_PCM_FREE;
stream.comp_id = spcm->stream[cstream->direction].comp_id;
if (spcm->prepared[cstream->direction]) {
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &stream, sizeof(stream));
if (!ret)
spcm->prepared[cstream->direction] = false;
}
cancel_work_sync(&spcm->stream[cstream->direction].period_elapsed_work);
spcm->stream[cstream->direction].cstream = NULL;
kfree(sstream);
return ret;
}
static int sof_compr_set_params(struct snd_soc_component *component,
struct snd_compr_stream *cstream, struct snd_compr_params *params)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
struct snd_compr_runtime *crtd = cstream->runtime;
struct sof_ipc_pcm_params_reply ipc_params_reply;
struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
struct sof_ipc_fw_version *v = &ready->version;
struct sof_compr_stream *sstream;
struct sof_ipc_pcm_params *pcm;
struct snd_sof_pcm *spcm;
size_t ext_data_size;
int ret;
if (v->abi_version < SOF_ABI_VER(3, 22, 0)) {
dev_err(component->dev,
"Compress params not supported with FW ABI version %d:%d:%d\n",
SOF_ABI_VERSION_MAJOR(v->abi_version),
SOF_ABI_VERSION_MINOR(v->abi_version),
SOF_ABI_VERSION_PATCH(v->abi_version));
return -EINVAL;
}
sstream = crtd->private_data;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
ext_data_size = sizeof(params->codec);
if (sizeof(*pcm) + ext_data_size > sdev->ipc->max_payload_size)
return -EINVAL;
pcm = kzalloc(sizeof(*pcm) + ext_data_size, GFP_KERNEL);
if (!pcm)
return -ENOMEM;
cstream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV_SG;
cstream->dma_buffer.dev.dev = sdev->dev;
ret = snd_compr_malloc_pages(cstream, crtd->buffer_size);
if (ret < 0)
goto out;
ret = create_page_table(component, cstream, crtd->dma_area, crtd->dma_bytes);
if (ret < 0)
goto out;
pcm->params.buffer.pages = PFN_UP(crtd->dma_bytes);
pcm->hdr.size = sizeof(*pcm) + ext_data_size;
pcm->hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_PCM_PARAMS;
pcm->comp_id = spcm->stream[cstream->direction].comp_id;
pcm->params.hdr.size = sizeof(pcm->params) + ext_data_size;
pcm->params.buffer.phy_addr = spcm->stream[cstream->direction].page_table.addr;
pcm->params.buffer.size = crtd->dma_bytes;
pcm->params.direction = cstream->direction;
pcm->params.channels = params->codec.ch_out;
pcm->params.rate = params->codec.sample_rate;
pcm->params.buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
pcm->params.frame_fmt = SOF_IPC_FRAME_S32_LE;
pcm->params.sample_container_bytes =
snd_pcm_format_physical_width(SNDRV_PCM_FORMAT_S32) >> 3;
pcm->params.host_period_bytes = params->buffer.fragment_size;
pcm->params.ext_data_length = ext_data_size;
memcpy((u8 *)pcm->params.ext_data, ¶ms->codec, ext_data_size);
ret = sof_ipc_tx_message(sdev->ipc, pcm, sizeof(*pcm) + ext_data_size,
&ipc_params_reply, sizeof(ipc_params_reply));
if (ret < 0) {
dev_err(component->dev, "error ipc failed\n");
goto out;
}
ret = snd_sof_set_stream_data_offset(sdev, &spcm->stream[cstream->direction],
ipc_params_reply.posn_offset);
if (ret < 0) {
dev_err(component->dev, "Invalid stream data offset for Compr %d\n",
spcm->pcm.pcm_id);
goto out;
}
sstream->sampling_rate = params->codec.sample_rate;
sstream->channels = params->codec.ch_out;
sstream->sample_container_bytes = pcm->params.sample_container_bytes;
spcm->prepared[cstream->direction] = true;
out:
kfree(pcm);
return ret;
}
static int sof_compr_get_params(struct snd_soc_component *component,
struct snd_compr_stream *cstream, struct snd_codec *params)
{
/* TODO: we don't query the supported codecs for now, if the
* application asks for an unsupported codec the set_params() will fail.
*/
return 0;
}
static int sof_compr_trigger(struct snd_soc_component *component,
struct snd_compr_stream *cstream, int cmd)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
struct sof_ipc_stream stream;
struct snd_sof_pcm *spcm;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
stream.hdr.size = sizeof(stream);
stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG;
stream.comp_id = spcm->stream[cstream->direction].comp_id;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_START;
break;
case SNDRV_PCM_TRIGGER_STOP:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_STOP;
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_PAUSE;
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_RELEASE;
break;
default:
dev_err(component->dev, "error: unhandled trigger cmd %d\n", cmd);
break;
}
return sof_ipc_tx_message_no_reply(sdev->ipc, &stream, sizeof(stream));
}
static int sof_compr_copy_playback(struct snd_compr_runtime *rtd,
char __user *buf, size_t count)
{
void *ptr;
unsigned int offset, n;
int ret;
div_u64_rem(rtd->total_bytes_available, rtd->buffer_size, &offset);
ptr = rtd->dma_area + offset;
n = rtd->buffer_size - offset;
if (count < n) {
ret = copy_from_user(ptr, buf, count);
} else {
ret = copy_from_user(ptr, buf, n);
ret += copy_from_user(rtd->dma_area, buf + n, count - n);
}
return count - ret;
}
static int sof_compr_copy_capture(struct snd_compr_runtime *rtd,
char __user *buf, size_t count)
{
void *ptr;
unsigned int offset, n;
int ret;
div_u64_rem(rtd->total_bytes_transferred, rtd->buffer_size, &offset);
ptr = rtd->dma_area + offset;
n = rtd->buffer_size - offset;
if (count < n) {
ret = copy_to_user(buf, ptr, count);
} else {
ret = copy_to_user(buf, ptr, n);
ret += copy_to_user(buf + n, rtd->dma_area, count - n);
}
return count - ret;
}
static int sof_compr_copy(struct snd_soc_component *component,
struct snd_compr_stream *cstream,
char __user *buf, size_t count)
{
struct snd_compr_runtime *rtd = cstream->runtime;
if (count > rtd->buffer_size)
count = rtd->buffer_size;
if (cstream->direction == SND_COMPRESS_PLAYBACK)
return sof_compr_copy_playback(rtd, buf, count);
else
return sof_compr_copy_capture(rtd, buf, count);
}
static int sof_compr_pointer(struct snd_soc_component *component,
struct snd_compr_stream *cstream,
struct snd_compr_tstamp *tstamp)
{
struct snd_sof_pcm *spcm;
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
struct sof_compr_stream *sstream = cstream->runtime->private_data;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
tstamp->sampling_rate = sstream->sampling_rate;
tstamp->copied_total = sstream->copied_total;
tstamp->pcm_io_frames = div_u64(spcm->stream[cstream->direction].posn.dai_posn,
sstream->channels * sstream->sample_container_bytes);
return 0;
}
struct snd_compress_ops sof_compressed_ops = {
.open = sof_compr_open,
.free = sof_compr_free,
.set_params = sof_compr_set_params,
.get_params = sof_compr_get_params,
.trigger = sof_compr_trigger,
.pointer = sof_compr_pointer,
.copy = sof_compr_copy,
};
EXPORT_SYMBOL(sof_compressed_ops);
| linux-master | sound/soc/sof/compress.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/firmware.h>
#include <linux/workqueue.h>
#include <sound/tlv.h>
#include <uapi/sound/sof/tokens.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ops.h"
#define COMP_ID_UNASSIGNED 0xffffffff
/*
* Constants used in the computation of linear volume gain
* from dB gain 20th root of 10 in Q1.16 fixed-point notation
*/
#define VOL_TWENTIETH_ROOT_OF_TEN 73533
/* 40th root of 10 in Q1.16 fixed-point notation*/
#define VOL_FORTIETH_ROOT_OF_TEN 69419
/* 0.5 dB step value in topology TLV */
#define VOL_HALF_DB_STEP 50
/* TLV data items */
#define TLV_MIN 0
#define TLV_STEP 1
#define TLV_MUTE 2
/**
* sof_update_ipc_object - Parse multiple sets of tokens within the token array associated with the
* token ID.
* @scomp: pointer to SOC component
* @object: target IPC struct to save the parsed values
* @token_id: token ID for the token array to be searched
* @tuples: pointer to the tuples array
* @num_tuples: number of tuples in the tuples array
* @object_size: size of the object
* @token_instance_num: number of times the same @token_id needs to be parsed i.e. the function
* looks for @token_instance_num of each token in the token array associated
* with the @token_id
*/
int sof_update_ipc_object(struct snd_soc_component *scomp, void *object, enum sof_tokens token_id,
struct snd_sof_tuple *tuples, int num_tuples,
size_t object_size, int token_instance_num)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
const struct sof_token_info *token_list;
const struct sof_topology_token *tokens;
int i, j;
token_list = tplg_ops ? tplg_ops->token_list : NULL;
/* nothing to do if token_list is NULL */
if (!token_list)
return 0;
if (token_list[token_id].count < 0) {
dev_err(scomp->dev, "Invalid token count for token ID: %d\n", token_id);
return -EINVAL;
}
/* No tokens to match */
if (!token_list[token_id].count)
return 0;
tokens = token_list[token_id].tokens;
if (!tokens) {
dev_err(scomp->dev, "Invalid tokens for token id: %d\n", token_id);
return -EINVAL;
}
for (i = 0; i < token_list[token_id].count; i++) {
int offset = 0;
int num_tokens_matched = 0;
for (j = 0; j < num_tuples; j++) {
if (tokens[i].token == tuples[j].token) {
switch (tokens[i].type) {
case SND_SOC_TPLG_TUPLE_TYPE_WORD:
{
u32 *val = (u32 *)((u8 *)object + tokens[i].offset +
offset);
*val = tuples[j].value.v;
break;
}
case SND_SOC_TPLG_TUPLE_TYPE_SHORT:
case SND_SOC_TPLG_TUPLE_TYPE_BOOL:
{
u16 *val = (u16 *)((u8 *)object + tokens[i].offset +
offset);
*val = (u16)tuples[j].value.v;
break;
}
case SND_SOC_TPLG_TUPLE_TYPE_STRING:
{
if (!tokens[i].get_token) {
dev_err(scomp->dev,
"get_token not defined for token %d in %s\n",
tokens[i].token, token_list[token_id].name);
return -EINVAL;
}
tokens[i].get_token((void *)tuples[j].value.s, object,
tokens[i].offset + offset);
break;
}
default:
break;
}
num_tokens_matched++;
/* found all required sets of current token. Move to the next one */
if (!(num_tokens_matched % token_instance_num))
break;
/* move to the next object */
offset += object_size;
}
}
}
return 0;
}
static inline int get_tlv_data(const int *p, int tlv[SOF_TLV_ITEMS])
{
/* we only support dB scale TLV type at the moment */
if ((int)p[SNDRV_CTL_TLVO_TYPE] != SNDRV_CTL_TLVT_DB_SCALE)
return -EINVAL;
/* min value in topology tlv data is multiplied by 100 */
tlv[TLV_MIN] = (int)p[SNDRV_CTL_TLVO_DB_SCALE_MIN] / 100;
/* volume steps */
tlv[TLV_STEP] = (int)(p[SNDRV_CTL_TLVO_DB_SCALE_MUTE_AND_STEP] &
TLV_DB_SCALE_MASK);
/* mute ON/OFF */
if ((p[SNDRV_CTL_TLVO_DB_SCALE_MUTE_AND_STEP] &
TLV_DB_SCALE_MUTE) == 0)
tlv[TLV_MUTE] = 0;
else
tlv[TLV_MUTE] = 1;
return 0;
}
/*
* Function to truncate an unsigned 64-bit number
* by x bits and return 32-bit unsigned number. This
* function also takes care of rounding while truncating
*/
static inline u32 vol_shift_64(u64 i, u32 x)
{
/* do not truncate more than 32 bits */
if (x > 32)
x = 32;
if (x == 0)
return (u32)i;
return (u32)(((i >> (x - 1)) + 1) >> 1);
}
/*
* Function to compute a ^ exp where,
* a is a fractional number represented by a fixed-point
* integer with a fractional world length of "fwl"
* exp is an integer
* fwl is the fractional word length
* Return value is a fractional number represented by a
* fixed-point integer with a fractional word length of "fwl"
*/
static u32 vol_pow32(u32 a, int exp, u32 fwl)
{
int i, iter;
u32 power = 1 << fwl;
u64 numerator;
/* if exponent is 0, return 1 */
if (exp == 0)
return power;
/* determine the number of iterations based on the exponent */
if (exp < 0)
iter = exp * -1;
else
iter = exp;
/* mutiply a "iter" times to compute power */
for (i = 0; i < iter; i++) {
/*
* Product of 2 Qx.fwl fixed-point numbers yields a Q2*x.2*fwl
* Truncate product back to fwl fractional bits with rounding
*/
power = vol_shift_64((u64)power * a, fwl);
}
if (exp > 0) {
/* if exp is positive, return the result */
return power;
}
/* if exp is negative, return the multiplicative inverse */
numerator = (u64)1 << (fwl << 1);
do_div(numerator, power);
return (u32)numerator;
}
/*
* Function to calculate volume gain from TLV data.
* This function can only handle gain steps that are multiples of 0.5 dB
*/
u32 vol_compute_gain(u32 value, int *tlv)
{
int dB_gain;
u32 linear_gain;
int f_step;
/* mute volume */
if (value == 0 && tlv[TLV_MUTE])
return 0;
/*
* compute dB gain from tlv. tlv_step
* in topology is multiplied by 100
*/
dB_gain = tlv[TLV_MIN] + (value * tlv[TLV_STEP]) / 100;
/*
* compute linear gain represented by fixed-point
* int with VOLUME_FWL fractional bits
*/
linear_gain = vol_pow32(VOL_TWENTIETH_ROOT_OF_TEN, dB_gain, VOLUME_FWL);
/* extract the fractional part of volume step */
f_step = tlv[TLV_STEP] - (tlv[TLV_STEP] / 100);
/* if volume step is an odd multiple of 0.5 dB */
if (f_step == VOL_HALF_DB_STEP && (value & 1))
linear_gain = vol_shift_64((u64)linear_gain *
VOL_FORTIETH_ROOT_OF_TEN,
VOLUME_FWL);
return linear_gain;
}
/*
* Set up volume table for kcontrols from tlv data
* "size" specifies the number of entries in the table
*/
static int set_up_volume_table(struct snd_sof_control *scontrol,
int tlv[SOF_TLV_ITEMS], int size)
{
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->set_up_volume_table)
return tplg_ops->control->set_up_volume_table(scontrol, tlv, size);
dev_err(scomp->dev, "Mandatory op %s not set\n", __func__);
return -EINVAL;
}
struct sof_dai_types {
const char *name;
enum sof_ipc_dai_type type;
};
static const struct sof_dai_types sof_dais[] = {
{"SSP", SOF_DAI_INTEL_SSP},
{"HDA", SOF_DAI_INTEL_HDA},
{"DMIC", SOF_DAI_INTEL_DMIC},
{"ALH", SOF_DAI_INTEL_ALH},
{"SAI", SOF_DAI_IMX_SAI},
{"ESAI", SOF_DAI_IMX_ESAI},
{"ACP", SOF_DAI_AMD_BT},
{"ACPSP", SOF_DAI_AMD_SP},
{"ACPDMIC", SOF_DAI_AMD_DMIC},
{"ACPHS", SOF_DAI_AMD_HS},
{"AFE", SOF_DAI_MEDIATEK_AFE},
{"ACPSP_VIRTUAL", SOF_DAI_AMD_SP_VIRTUAL},
{"ACPHS_VIRTUAL", SOF_DAI_AMD_HS_VIRTUAL},
};
static enum sof_ipc_dai_type find_dai(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(sof_dais); i++) {
if (strcmp(name, sof_dais[i].name) == 0)
return sof_dais[i].type;
}
return SOF_DAI_INTEL_NONE;
}
/*
* Supported Frame format types and lookup, add new ones to end of list.
*/
struct sof_frame_types {
const char *name;
enum sof_ipc_frame frame;
};
static const struct sof_frame_types sof_frames[] = {
{"s16le", SOF_IPC_FRAME_S16_LE},
{"s24le", SOF_IPC_FRAME_S24_4LE},
{"s32le", SOF_IPC_FRAME_S32_LE},
{"float", SOF_IPC_FRAME_FLOAT},
};
static enum sof_ipc_frame find_format(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(sof_frames); i++) {
if (strcmp(name, sof_frames[i].name) == 0)
return sof_frames[i].frame;
}
/* use s32le if nothing is specified */
return SOF_IPC_FRAME_S32_LE;
}
int get_token_u32(void *elem, void *object, u32 offset)
{
struct snd_soc_tplg_vendor_value_elem *velem = elem;
u32 *val = (u32 *)((u8 *)object + offset);
*val = le32_to_cpu(velem->value);
return 0;
}
int get_token_u16(void *elem, void *object, u32 offset)
{
struct snd_soc_tplg_vendor_value_elem *velem = elem;
u16 *val = (u16 *)((u8 *)object + offset);
*val = (u16)le32_to_cpu(velem->value);
return 0;
}
int get_token_uuid(void *elem, void *object, u32 offset)
{
struct snd_soc_tplg_vendor_uuid_elem *velem = elem;
u8 *dst = (u8 *)object + offset;
memcpy(dst, velem->uuid, UUID_SIZE);
return 0;
}
/*
* The string gets from topology will be stored in heap, the owner only
* holds a char* member point to the heap.
*/
int get_token_string(void *elem, void *object, u32 offset)
{
/* "dst" here points to the char* member of the owner */
char **dst = (char **)((u8 *)object + offset);
*dst = kstrdup(elem, GFP_KERNEL);
if (!*dst)
return -ENOMEM;
return 0;
};
int get_token_comp_format(void *elem, void *object, u32 offset)
{
u32 *val = (u32 *)((u8 *)object + offset);
*val = find_format((const char *)elem);
return 0;
}
int get_token_dai_type(void *elem, void *object, u32 offset)
{
u32 *val = (u32 *)((u8 *)object + offset);
*val = find_dai((const char *)elem);
return 0;
}
/* PCM */
static const struct sof_topology_token stream_tokens[] = {
{SOF_TKN_STREAM_PLAYBACK_COMPATIBLE_D0I3, SND_SOC_TPLG_TUPLE_TYPE_BOOL, get_token_u16,
offsetof(struct snd_sof_pcm, stream[0].d0i3_compatible)},
{SOF_TKN_STREAM_CAPTURE_COMPATIBLE_D0I3, SND_SOC_TPLG_TUPLE_TYPE_BOOL, get_token_u16,
offsetof(struct snd_sof_pcm, stream[1].d0i3_compatible)},
};
/* Leds */
static const struct sof_topology_token led_tokens[] = {
{SOF_TKN_MUTE_LED_USE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct snd_sof_led_control, use_led)},
{SOF_TKN_MUTE_LED_DIRECTION, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct snd_sof_led_control, direction)},
};
static const struct sof_topology_token comp_pin_tokens[] = {
{SOF_TKN_COMP_NUM_INPUT_PINS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct snd_sof_widget, num_input_pins)},
{SOF_TKN_COMP_NUM_OUTPUT_PINS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct snd_sof_widget, num_output_pins)},
};
static const struct sof_topology_token comp_input_pin_binding_tokens[] = {
{SOF_TKN_COMP_INPUT_PIN_BINDING_WNAME, SND_SOC_TPLG_TUPLE_TYPE_STRING,
get_token_string, 0},
};
static const struct sof_topology_token comp_output_pin_binding_tokens[] = {
{SOF_TKN_COMP_OUTPUT_PIN_BINDING_WNAME, SND_SOC_TPLG_TUPLE_TYPE_STRING,
get_token_string, 0},
};
/**
* sof_parse_uuid_tokens - Parse multiple sets of UUID tokens
* @scomp: pointer to soc component
* @object: target ipc struct for parsed values
* @offset: offset within the object pointer
* @tokens: array of struct sof_topology_token containing the tokens to be matched
* @num_tokens: number of tokens in tokens array
* @array: source pointer to consecutive vendor arrays in topology
*
* This function parses multiple sets of string type tokens in vendor arrays
*/
static int sof_parse_uuid_tokens(struct snd_soc_component *scomp,
void *object, size_t offset,
const struct sof_topology_token *tokens, int num_tokens,
struct snd_soc_tplg_vendor_array *array)
{
struct snd_soc_tplg_vendor_uuid_elem *elem;
int found = 0;
int i, j;
/* parse element by element */
for (i = 0; i < le32_to_cpu(array->num_elems); i++) {
elem = &array->uuid[i];
/* search for token */
for (j = 0; j < num_tokens; j++) {
/* match token type */
if (tokens[j].type != SND_SOC_TPLG_TUPLE_TYPE_UUID)
continue;
/* match token id */
if (tokens[j].token != le32_to_cpu(elem->token))
continue;
/* matched - now load token */
tokens[j].get_token(elem, object,
offset + tokens[j].offset);
found++;
}
}
return found;
}
/**
* sof_copy_tuples - Parse tokens and copy them to the @tuples array
* @sdev: pointer to struct snd_sof_dev
* @array: source pointer to consecutive vendor arrays in topology
* @array_size: size of @array
* @token_id: Token ID associated with a token array
* @token_instance_num: number of times the same @token_id needs to be parsed i.e. the function
* looks for @token_instance_num of each token in the token array associated
* with the @token_id
* @tuples: tuples array to copy the matched tuples to
* @tuples_size: size of @tuples
* @num_copied_tuples: pointer to the number of copied tuples in the tuples array
*
*/
static int sof_copy_tuples(struct snd_sof_dev *sdev, struct snd_soc_tplg_vendor_array *array,
int array_size, u32 token_id, int token_instance_num,
struct snd_sof_tuple *tuples, int tuples_size, int *num_copied_tuples)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
const struct sof_token_info *token_list;
const struct sof_topology_token *tokens;
int found = 0;
int num_tokens, asize;
int i, j;
token_list = tplg_ops ? tplg_ops->token_list : NULL;
/* nothing to do if token_list is NULL */
if (!token_list)
return 0;
if (!tuples || !num_copied_tuples) {
dev_err(sdev->dev, "Invalid tuples array\n");
return -EINVAL;
}
tokens = token_list[token_id].tokens;
num_tokens = token_list[token_id].count;
if (!tokens) {
dev_err(sdev->dev, "No token array defined for token ID: %d\n", token_id);
return -EINVAL;
}
/* check if there's space in the tuples array for new tokens */
if (*num_copied_tuples >= tuples_size) {
dev_err(sdev->dev, "No space in tuples array for new tokens from %s",
token_list[token_id].name);
return -EINVAL;
}
while (array_size > 0 && found < num_tokens * token_instance_num) {
asize = le32_to_cpu(array->size);
/* validate asize */
if (asize < 0) {
dev_err(sdev->dev, "Invalid array size 0x%x\n", asize);
return -EINVAL;
}
/* make sure there is enough data before parsing */
array_size -= asize;
if (array_size < 0) {
dev_err(sdev->dev, "Invalid array size 0x%x\n", asize);
return -EINVAL;
}
/* parse element by element */
for (i = 0; i < le32_to_cpu(array->num_elems); i++) {
/* search for token */
for (j = 0; j < num_tokens; j++) {
/* match token type */
if (!(tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_WORD ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_SHORT ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_BYTE ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_BOOL ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_STRING))
continue;
if (tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_STRING) {
struct snd_soc_tplg_vendor_string_elem *elem;
elem = &array->string[i];
/* match token id */
if (tokens[j].token != le32_to_cpu(elem->token))
continue;
tuples[*num_copied_tuples].token = tokens[j].token;
tuples[*num_copied_tuples].value.s = elem->string;
} else {
struct snd_soc_tplg_vendor_value_elem *elem;
elem = &array->value[i];
/* match token id */
if (tokens[j].token != le32_to_cpu(elem->token))
continue;
tuples[*num_copied_tuples].token = tokens[j].token;
tuples[*num_copied_tuples].value.v =
le32_to_cpu(elem->value);
}
found++;
(*num_copied_tuples)++;
/* stop if there's no space for any more new tuples */
if (*num_copied_tuples == tuples_size)
return 0;
}
/* stop when we've found the required token instances */
if (found == num_tokens * token_instance_num)
return 0;
}
/* next array */
array = (struct snd_soc_tplg_vendor_array *)((u8 *)array + asize);
}
return 0;
}
/**
* sof_parse_string_tokens - Parse multiple sets of tokens
* @scomp: pointer to soc component
* @object: target ipc struct for parsed values
* @offset: offset within the object pointer
* @tokens: array of struct sof_topology_token containing the tokens to be matched
* @num_tokens: number of tokens in tokens array
* @array: source pointer to consecutive vendor arrays in topology
*
* This function parses multiple sets of string type tokens in vendor arrays
*/
static int sof_parse_string_tokens(struct snd_soc_component *scomp,
void *object, int offset,
const struct sof_topology_token *tokens, int num_tokens,
struct snd_soc_tplg_vendor_array *array)
{
struct snd_soc_tplg_vendor_string_elem *elem;
int found = 0;
int i, j, ret;
/* parse element by element */
for (i = 0; i < le32_to_cpu(array->num_elems); i++) {
elem = &array->string[i];
/* search for token */
for (j = 0; j < num_tokens; j++) {
/* match token type */
if (tokens[j].type != SND_SOC_TPLG_TUPLE_TYPE_STRING)
continue;
/* match token id */
if (tokens[j].token != le32_to_cpu(elem->token))
continue;
/* matched - now load token */
ret = tokens[j].get_token(elem->string, object, offset + tokens[j].offset);
if (ret < 0)
return ret;
found++;
}
}
return found;
}
/**
* sof_parse_word_tokens - Parse multiple sets of tokens
* @scomp: pointer to soc component
* @object: target ipc struct for parsed values
* @offset: offset within the object pointer
* @tokens: array of struct sof_topology_token containing the tokens to be matched
* @num_tokens: number of tokens in tokens array
* @array: source pointer to consecutive vendor arrays in topology
*
* This function parses multiple sets of word type tokens in vendor arrays
*/
static int sof_parse_word_tokens(struct snd_soc_component *scomp,
void *object, int offset,
const struct sof_topology_token *tokens, int num_tokens,
struct snd_soc_tplg_vendor_array *array)
{
struct snd_soc_tplg_vendor_value_elem *elem;
int found = 0;
int i, j;
/* parse element by element */
for (i = 0; i < le32_to_cpu(array->num_elems); i++) {
elem = &array->value[i];
/* search for token */
for (j = 0; j < num_tokens; j++) {
/* match token type */
if (!(tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_WORD ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_SHORT ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_BYTE ||
tokens[j].type == SND_SOC_TPLG_TUPLE_TYPE_BOOL))
continue;
/* match token id */
if (tokens[j].token != le32_to_cpu(elem->token))
continue;
/* load token */
tokens[j].get_token(elem, object, offset + tokens[j].offset);
found++;
}
}
return found;
}
/**
* sof_parse_token_sets - Parse multiple sets of tokens
* @scomp: pointer to soc component
* @object: target ipc struct for parsed values
* @tokens: token definition array describing what tokens to parse
* @count: number of tokens in definition array
* @array: source pointer to consecutive vendor arrays in topology
* @array_size: total size of @array
* @token_instance_num: number of times the same tokens needs to be parsed i.e. the function
* looks for @token_instance_num of each token in the @tokens
* @object_size: offset to next target ipc struct with multiple sets
*
* This function parses multiple sets of tokens in vendor arrays into
* consecutive ipc structs.
*/
static int sof_parse_token_sets(struct snd_soc_component *scomp,
void *object, const struct sof_topology_token *tokens,
int count, struct snd_soc_tplg_vendor_array *array,
int array_size, int token_instance_num, size_t object_size)
{
size_t offset = 0;
int found = 0;
int total = 0;
int asize;
int ret;
while (array_size > 0 && total < count * token_instance_num) {
asize = le32_to_cpu(array->size);
/* validate asize */
if (asize < 0) { /* FIXME: A zero-size array makes no sense */
dev_err(scomp->dev, "error: invalid array size 0x%x\n",
asize);
return -EINVAL;
}
/* make sure there is enough data before parsing */
array_size -= asize;
if (array_size < 0) {
dev_err(scomp->dev, "error: invalid array size 0x%x\n",
asize);
return -EINVAL;
}
/* call correct parser depending on type */
switch (le32_to_cpu(array->type)) {
case SND_SOC_TPLG_TUPLE_TYPE_UUID:
found += sof_parse_uuid_tokens(scomp, object, offset, tokens, count,
array);
break;
case SND_SOC_TPLG_TUPLE_TYPE_STRING:
ret = sof_parse_string_tokens(scomp, object, offset, tokens, count,
array);
if (ret < 0) {
dev_err(scomp->dev, "error: no memory to copy string token\n");
return ret;
}
found += ret;
break;
case SND_SOC_TPLG_TUPLE_TYPE_BOOL:
case SND_SOC_TPLG_TUPLE_TYPE_BYTE:
case SND_SOC_TPLG_TUPLE_TYPE_WORD:
case SND_SOC_TPLG_TUPLE_TYPE_SHORT:
found += sof_parse_word_tokens(scomp, object, offset, tokens, count,
array);
break;
default:
dev_err(scomp->dev, "error: unknown token type %d\n",
array->type);
return -EINVAL;
}
/* next array */
array = (struct snd_soc_tplg_vendor_array *)((u8 *)array
+ asize);
/* move to next target struct */
if (found >= count) {
offset += object_size;
total += found;
found = 0;
}
}
return 0;
}
/**
* sof_parse_tokens - Parse one set of tokens
* @scomp: pointer to soc component
* @object: target ipc struct for parsed values
* @tokens: token definition array describing what tokens to parse
* @num_tokens: number of tokens in definition array
* @array: source pointer to consecutive vendor arrays in topology
* @array_size: total size of @array
*
* This function parses a single set of tokens in vendor arrays into
* consecutive ipc structs.
*/
static int sof_parse_tokens(struct snd_soc_component *scomp, void *object,
const struct sof_topology_token *tokens, int num_tokens,
struct snd_soc_tplg_vendor_array *array,
int array_size)
{
/*
* sof_parse_tokens is used when topology contains only a single set of
* identical tuples arrays. So additional parameters to
* sof_parse_token_sets are sets = 1 (only 1 set) and
* object_size = 0 (irrelevant).
*/
return sof_parse_token_sets(scomp, object, tokens, num_tokens, array,
array_size, 1, 0);
}
/*
* Standard Kcontrols.
*/
static int sof_control_load_volume(struct snd_soc_component *scomp,
struct snd_sof_control *scontrol,
struct snd_kcontrol_new *kc,
struct snd_soc_tplg_ctl_hdr *hdr)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_soc_tplg_mixer_control *mc =
container_of(hdr, struct snd_soc_tplg_mixer_control, hdr);
int tlv[SOF_TLV_ITEMS];
unsigned int mask;
int ret;
/* validate topology data */
if (le32_to_cpu(mc->num_channels) > SND_SOC_TPLG_MAX_CHAN)
return -EINVAL;
/*
* If control has more than 2 channels we need to override the info. This is because even if
* ASoC layer has defined topology's max channel count to SND_SOC_TPLG_MAX_CHAN = 8, the
* pre-defined dapm control types (and related functions) creating the actual control
* restrict the channels only to mono or stereo.
*/
if (le32_to_cpu(mc->num_channels) > 2)
kc->info = snd_sof_volume_info;
scontrol->comp_id = sdev->next_comp_id;
scontrol->min_volume_step = le32_to_cpu(mc->min);
scontrol->max_volume_step = le32_to_cpu(mc->max);
scontrol->num_channels = le32_to_cpu(mc->num_channels);
scontrol->max = le32_to_cpu(mc->max);
if (le32_to_cpu(mc->max) == 1)
goto skip;
/* extract tlv data */
if (!kc->tlv.p || get_tlv_data(kc->tlv.p, tlv) < 0) {
dev_err(scomp->dev, "error: invalid TLV data\n");
return -EINVAL;
}
/* set up volume table */
ret = set_up_volume_table(scontrol, tlv, le32_to_cpu(mc->max) + 1);
if (ret < 0) {
dev_err(scomp->dev, "error: setting up volume table\n");
return ret;
}
skip:
/* set up possible led control from mixer private data */
ret = sof_parse_tokens(scomp, &scontrol->led_ctl, led_tokens,
ARRAY_SIZE(led_tokens), mc->priv.array,
le32_to_cpu(mc->priv.size));
if (ret != 0) {
dev_err(scomp->dev, "error: parse led tokens failed %d\n",
le32_to_cpu(mc->priv.size));
goto err;
}
if (scontrol->led_ctl.use_led) {
mask = scontrol->led_ctl.direction ? SNDRV_CTL_ELEM_ACCESS_MIC_LED :
SNDRV_CTL_ELEM_ACCESS_SPK_LED;
scontrol->access &= ~SNDRV_CTL_ELEM_ACCESS_LED_MASK;
scontrol->access |= mask;
kc->access &= ~SNDRV_CTL_ELEM_ACCESS_LED_MASK;
kc->access |= mask;
sdev->led_present = true;
}
dev_dbg(scomp->dev, "tplg: load kcontrol index %d chans %d\n",
scontrol->comp_id, scontrol->num_channels);
return 0;
err:
if (le32_to_cpu(mc->max) > 1)
kfree(scontrol->volume_table);
return ret;
}
static int sof_control_load_enum(struct snd_soc_component *scomp,
struct snd_sof_control *scontrol,
struct snd_kcontrol_new *kc,
struct snd_soc_tplg_ctl_hdr *hdr)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_soc_tplg_enum_control *ec =
container_of(hdr, struct snd_soc_tplg_enum_control, hdr);
/* validate topology data */
if (le32_to_cpu(ec->num_channels) > SND_SOC_TPLG_MAX_CHAN)
return -EINVAL;
scontrol->comp_id = sdev->next_comp_id;
scontrol->num_channels = le32_to_cpu(ec->num_channels);
dev_dbg(scomp->dev, "tplg: load kcontrol index %d chans %d comp_id %d\n",
scontrol->comp_id, scontrol->num_channels, scontrol->comp_id);
return 0;
}
static int sof_control_load_bytes(struct snd_soc_component *scomp,
struct snd_sof_control *scontrol,
struct snd_kcontrol_new *kc,
struct snd_soc_tplg_ctl_hdr *hdr)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_soc_tplg_bytes_control *control =
container_of(hdr, struct snd_soc_tplg_bytes_control, hdr);
struct soc_bytes_ext *sbe = (struct soc_bytes_ext *)kc->private_value;
size_t priv_size = le32_to_cpu(control->priv.size);
scontrol->max_size = sbe->max;
scontrol->comp_id = sdev->next_comp_id;
dev_dbg(scomp->dev, "tplg: load kcontrol index %d\n", scontrol->comp_id);
/* copy the private data */
if (priv_size > 0) {
scontrol->priv = kmemdup(control->priv.data, priv_size, GFP_KERNEL);
if (!scontrol->priv)
return -ENOMEM;
scontrol->priv_size = priv_size;
}
return 0;
}
/* external kcontrol init - used for any driver specific init */
static int sof_control_load(struct snd_soc_component *scomp, int index,
struct snd_kcontrol_new *kc,
struct snd_soc_tplg_ctl_hdr *hdr)
{
struct soc_mixer_control *sm;
struct soc_bytes_ext *sbe;
struct soc_enum *se;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_soc_dobj *dobj;
struct snd_sof_control *scontrol;
int ret;
dev_dbg(scomp->dev, "tplg: load control type %d name : %s\n",
hdr->type, hdr->name);
scontrol = kzalloc(sizeof(*scontrol), GFP_KERNEL);
if (!scontrol)
return -ENOMEM;
scontrol->name = kstrdup(hdr->name, GFP_KERNEL);
if (!scontrol->name) {
kfree(scontrol);
return -ENOMEM;
}
scontrol->scomp = scomp;
scontrol->access = kc->access;
scontrol->info_type = le32_to_cpu(hdr->ops.info);
scontrol->index = kc->index;
switch (le32_to_cpu(hdr->ops.info)) {
case SND_SOC_TPLG_CTL_VOLSW:
case SND_SOC_TPLG_CTL_VOLSW_SX:
case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
sm = (struct soc_mixer_control *)kc->private_value;
dobj = &sm->dobj;
ret = sof_control_load_volume(scomp, scontrol, kc, hdr);
break;
case SND_SOC_TPLG_CTL_BYTES:
sbe = (struct soc_bytes_ext *)kc->private_value;
dobj = &sbe->dobj;
ret = sof_control_load_bytes(scomp, scontrol, kc, hdr);
break;
case SND_SOC_TPLG_CTL_ENUM:
case SND_SOC_TPLG_CTL_ENUM_VALUE:
se = (struct soc_enum *)kc->private_value;
dobj = &se->dobj;
ret = sof_control_load_enum(scomp, scontrol, kc, hdr);
break;
case SND_SOC_TPLG_CTL_RANGE:
case SND_SOC_TPLG_CTL_STROBE:
case SND_SOC_TPLG_DAPM_CTL_VOLSW:
case SND_SOC_TPLG_DAPM_CTL_ENUM_DOUBLE:
case SND_SOC_TPLG_DAPM_CTL_ENUM_VIRT:
case SND_SOC_TPLG_DAPM_CTL_ENUM_VALUE:
case SND_SOC_TPLG_DAPM_CTL_PIN:
default:
dev_warn(scomp->dev, "control type not supported %d:%d:%d\n",
hdr->ops.get, hdr->ops.put, hdr->ops.info);
kfree(scontrol->name);
kfree(scontrol);
return 0;
}
if (ret < 0) {
kfree(scontrol->name);
kfree(scontrol);
return ret;
}
scontrol->led_ctl.led_value = -1;
dobj->private = scontrol;
list_add(&scontrol->list, &sdev->kcontrol_list);
return 0;
}
static int sof_control_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_sof_control *scontrol = dobj->private;
int ret = 0;
dev_dbg(scomp->dev, "tplg: unload control name : %s\n", scontrol->name);
if (tplg_ops && tplg_ops->control_free) {
ret = tplg_ops->control_free(sdev, scontrol);
if (ret < 0)
dev_err(scomp->dev, "failed to free control: %s\n", scontrol->name);
}
/* free all data before returning in case of error too */
kfree(scontrol->ipc_control_data);
kfree(scontrol->priv);
kfree(scontrol->name);
list_del(&scontrol->list);
kfree(scontrol);
return ret;
}
/*
* DAI Topology
*/
static int sof_connect_dai_widget(struct snd_soc_component *scomp,
struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tw,
struct snd_sof_dai *dai)
{
struct snd_soc_card *card = scomp->card;
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *cpu_dai;
int stream;
int i;
if (!w->sname) {
dev_err(scomp->dev, "Widget %s does not have stream\n", w->name);
return -EINVAL;
}
if (w->id == snd_soc_dapm_dai_out)
stream = SNDRV_PCM_STREAM_CAPTURE;
else if (w->id == snd_soc_dapm_dai_in)
stream = SNDRV_PCM_STREAM_PLAYBACK;
else
goto end;
list_for_each_entry(rtd, &card->rtd_list, list) {
/* does stream match DAI link ? */
if (!rtd->dai_link->stream_name ||
!strstr(rtd->dai_link->stream_name, w->sname))
continue;
for_each_rtd_cpu_dais(rtd, i, cpu_dai) {
/*
* Please create DAI widget in the right order
* to ensure BE will connect to the right DAI
* widget.
*/
if (!snd_soc_dai_get_widget(cpu_dai, stream)) {
snd_soc_dai_set_widget(cpu_dai, stream, w);
break;
}
}
if (i == rtd->dai_link->num_cpus) {
dev_err(scomp->dev, "error: can't find BE for DAI %s\n", w->name);
return -EINVAL;
}
dai->name = rtd->dai_link->name;
dev_dbg(scomp->dev, "tplg: connected widget %s -> DAI link %s\n",
w->name, rtd->dai_link->name);
}
end:
/* check we have a connection */
if (!dai->name) {
dev_err(scomp->dev, "error: can't connect DAI %s stream %s\n",
w->name, w->sname);
return -EINVAL;
}
return 0;
}
static void sof_disconnect_dai_widget(struct snd_soc_component *scomp,
struct snd_soc_dapm_widget *w)
{
struct snd_soc_card *card = scomp->card;
struct snd_soc_pcm_runtime *rtd;
const char *sname = w->sname;
struct snd_soc_dai *cpu_dai;
int i, stream;
if (!sname)
return;
if (w->id == snd_soc_dapm_dai_out)
stream = SNDRV_PCM_STREAM_CAPTURE;
else if (w->id == snd_soc_dapm_dai_in)
stream = SNDRV_PCM_STREAM_PLAYBACK;
else
return;
list_for_each_entry(rtd, &card->rtd_list, list) {
/* does stream match DAI link ? */
if (!rtd->dai_link->stream_name ||
strcmp(sname, rtd->dai_link->stream_name))
continue;
for_each_rtd_cpu_dais(rtd, i, cpu_dai)
if (snd_soc_dai_get_widget(cpu_dai, stream) == w) {
snd_soc_dai_set_widget(cpu_dai, stream, NULL);
break;
}
}
}
/* bind PCM ID to host component ID */
static int spcm_bind(struct snd_soc_component *scomp, struct snd_sof_pcm *spcm,
int dir)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_widget *host_widget;
if (sdev->dspless_mode_selected)
return 0;
host_widget = snd_sof_find_swidget_sname(scomp,
spcm->pcm.caps[dir].name,
dir);
if (!host_widget) {
dev_err(scomp->dev, "can't find host comp to bind pcm\n");
return -EINVAL;
}
spcm->stream[dir].comp_id = host_widget->comp_id;
return 0;
}
static int sof_get_token_value(u32 token_id, struct snd_sof_tuple *tuples, int num_tuples)
{
int i;
if (!tuples)
return -EINVAL;
for (i = 0; i < num_tuples; i++) {
if (tuples[i].token == token_id)
return tuples[i].value.v;
}
return -EINVAL;
}
static int sof_widget_parse_tokens(struct snd_soc_component *scomp, struct snd_sof_widget *swidget,
struct snd_soc_tplg_dapm_widget *tw,
enum sof_tokens *object_token_list, int count)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_soc_tplg_private *private = &tw->priv;
const struct sof_token_info *token_list;
int num_tuples = 0;
int ret, i;
token_list = tplg_ops ? tplg_ops->token_list : NULL;
/* nothing to do if token_list is NULL */
if (!token_list)
return 0;
if (count > 0 && !object_token_list) {
dev_err(scomp->dev, "No token list for widget %s\n", swidget->widget->name);
return -EINVAL;
}
/* calculate max size of tuples array */
for (i = 0; i < count; i++)
num_tuples += token_list[object_token_list[i]].count;
/* allocate memory for tuples array */
swidget->tuples = kcalloc(num_tuples, sizeof(*swidget->tuples), GFP_KERNEL);
if (!swidget->tuples)
return -ENOMEM;
/* parse token list for widget */
for (i = 0; i < count; i++) {
int num_sets = 1;
if (object_token_list[i] >= SOF_TOKEN_COUNT) {
dev_err(scomp->dev, "Invalid token id %d for widget %s\n",
object_token_list[i], swidget->widget->name);
ret = -EINVAL;
goto err;
}
switch (object_token_list[i]) {
case SOF_COMP_EXT_TOKENS:
/* parse and save UUID in swidget */
ret = sof_parse_tokens(scomp, swidget,
token_list[object_token_list[i]].tokens,
token_list[object_token_list[i]].count,
private->array, le32_to_cpu(private->size));
if (ret < 0) {
dev_err(scomp->dev, "Failed parsing %s for widget %s\n",
token_list[object_token_list[i]].name,
swidget->widget->name);
goto err;
}
continue;
case SOF_IN_AUDIO_FORMAT_TOKENS:
num_sets = sof_get_token_value(SOF_TKN_COMP_NUM_INPUT_AUDIO_FORMATS,
swidget->tuples, swidget->num_tuples);
if (num_sets < 0) {
dev_err(sdev->dev, "Invalid input audio format count for %s\n",
swidget->widget->name);
ret = num_sets;
goto err;
}
break;
case SOF_OUT_AUDIO_FORMAT_TOKENS:
num_sets = sof_get_token_value(SOF_TKN_COMP_NUM_OUTPUT_AUDIO_FORMATS,
swidget->tuples, swidget->num_tuples);
if (num_sets < 0) {
dev_err(sdev->dev, "Invalid output audio format count for %s\n",
swidget->widget->name);
ret = num_sets;
goto err;
}
break;
default:
break;
}
if (num_sets > 1) {
struct snd_sof_tuple *new_tuples;
num_tuples += token_list[object_token_list[i]].count * (num_sets - 1);
new_tuples = krealloc(swidget->tuples,
sizeof(*new_tuples) * num_tuples, GFP_KERNEL);
if (!new_tuples) {
ret = -ENOMEM;
goto err;
}
swidget->tuples = new_tuples;
}
/* copy one set of tuples per token ID into swidget->tuples */
ret = sof_copy_tuples(sdev, private->array, le32_to_cpu(private->size),
object_token_list[i], num_sets, swidget->tuples,
num_tuples, &swidget->num_tuples);
if (ret < 0) {
dev_err(scomp->dev, "Failed parsing %s for widget %s err: %d\n",
token_list[object_token_list[i]].name, swidget->widget->name, ret);
goto err;
}
}
return 0;
err:
kfree(swidget->tuples);
return ret;
}
static void sof_free_pin_binding(struct snd_sof_widget *swidget,
bool pin_type)
{
char **pin_binding;
u32 num_pins;
int i;
if (pin_type == SOF_PIN_TYPE_INPUT) {
pin_binding = swidget->input_pin_binding;
num_pins = swidget->num_input_pins;
} else {
pin_binding = swidget->output_pin_binding;
num_pins = swidget->num_output_pins;
}
if (pin_binding) {
for (i = 0; i < num_pins; i++)
kfree(pin_binding[i]);
}
kfree(pin_binding);
}
static int sof_parse_pin_binding(struct snd_sof_widget *swidget,
struct snd_soc_tplg_private *priv, bool pin_type)
{
const struct sof_topology_token *pin_binding_token;
char *pin_binding[SOF_WIDGET_MAX_NUM_PINS];
int token_count;
u32 num_pins;
char **pb;
int ret;
int i;
if (pin_type == SOF_PIN_TYPE_INPUT) {
num_pins = swidget->num_input_pins;
pin_binding_token = comp_input_pin_binding_tokens;
token_count = ARRAY_SIZE(comp_input_pin_binding_tokens);
} else {
num_pins = swidget->num_output_pins;
pin_binding_token = comp_output_pin_binding_tokens;
token_count = ARRAY_SIZE(comp_output_pin_binding_tokens);
}
memset(pin_binding, 0, SOF_WIDGET_MAX_NUM_PINS * sizeof(char *));
ret = sof_parse_token_sets(swidget->scomp, pin_binding, pin_binding_token,
token_count, priv->array, le32_to_cpu(priv->size),
num_pins, sizeof(char *));
if (ret < 0)
goto err;
/* copy pin binding array to swidget only if it is defined in topology */
if (pin_binding[0]) {
pb = kmemdup(pin_binding, num_pins * sizeof(char *), GFP_KERNEL);
if (!pb) {
ret = -ENOMEM;
goto err;
}
if (pin_type == SOF_PIN_TYPE_INPUT)
swidget->input_pin_binding = pb;
else
swidget->output_pin_binding = pb;
}
return 0;
err:
for (i = 0; i < num_pins; i++)
kfree(pin_binding[i]);
return ret;
}
static int get_w_no_wname_in_long_name(void *elem, void *object, u32 offset)
{
struct snd_soc_tplg_vendor_value_elem *velem = elem;
struct snd_soc_dapm_widget *w = object;
w->no_wname_in_kcontrol_name = !!le32_to_cpu(velem->value);
return 0;
}
static const struct sof_topology_token dapm_widget_tokens[] = {
{SOF_TKN_COMP_NO_WNAME_IN_KCONTROL_NAME, SND_SOC_TPLG_TUPLE_TYPE_BOOL,
get_w_no_wname_in_long_name, 0}
};
/* external widget init - used for any driver specific init */
static int sof_widget_ready(struct snd_soc_component *scomp, int index,
struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tw)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
const struct sof_ipc_tplg_widget_ops *widget_ops;
struct snd_soc_tplg_private *priv = &tw->priv;
enum sof_tokens *token_list = NULL;
struct snd_sof_widget *swidget;
struct snd_sof_dai *dai;
int token_list_size = 0;
int ret = 0;
swidget = kzalloc(sizeof(*swidget), GFP_KERNEL);
if (!swidget)
return -ENOMEM;
swidget->scomp = scomp;
swidget->widget = w;
swidget->comp_id = sdev->next_comp_id++;
swidget->id = w->id;
swidget->pipeline_id = index;
swidget->private = NULL;
mutex_init(&swidget->setup_mutex);
ida_init(&swidget->output_queue_ida);
ida_init(&swidget->input_queue_ida);
ret = sof_parse_tokens(scomp, w, dapm_widget_tokens, ARRAY_SIZE(dapm_widget_tokens),
priv->array, le32_to_cpu(priv->size));
if (ret < 0) {
dev_err(scomp->dev, "failed to parse dapm widget tokens for %s\n",
w->name);
goto widget_free;
}
ret = sof_parse_tokens(scomp, swidget, comp_pin_tokens,
ARRAY_SIZE(comp_pin_tokens), priv->array,
le32_to_cpu(priv->size));
if (ret < 0) {
dev_err(scomp->dev, "failed to parse component pin tokens for %s\n",
w->name);
goto widget_free;
}
if (swidget->num_input_pins > SOF_WIDGET_MAX_NUM_PINS ||
swidget->num_output_pins > SOF_WIDGET_MAX_NUM_PINS) {
dev_err(scomp->dev, "invalid pins for %s: [input: %d, output: %d]\n",
swidget->widget->name, swidget->num_input_pins, swidget->num_output_pins);
ret = -EINVAL;
goto widget_free;
}
if (swidget->num_input_pins > 1) {
ret = sof_parse_pin_binding(swidget, priv, SOF_PIN_TYPE_INPUT);
/* on parsing error, pin binding is not allocated, nothing to free. */
if (ret < 0) {
dev_err(scomp->dev, "failed to parse input pin binding for %s\n",
w->name);
goto widget_free;
}
}
if (swidget->num_output_pins > 1) {
ret = sof_parse_pin_binding(swidget, priv, SOF_PIN_TYPE_OUTPUT);
/* on parsing error, pin binding is not allocated, nothing to free. */
if (ret < 0) {
dev_err(scomp->dev, "failed to parse output pin binding for %s\n",
w->name);
goto widget_free;
}
}
dev_dbg(scomp->dev,
"tplg: widget %d (%s) is ready [type: %d, pipe: %d, pins: %d / %d, stream: %s]\n",
swidget->comp_id, w->name, swidget->id, index,
swidget->num_input_pins, swidget->num_output_pins,
strnlen(w->sname, SNDRV_CTL_ELEM_ID_NAME_MAXLEN) > 0 ? w->sname : "none");
widget_ops = tplg_ops ? tplg_ops->widget : NULL;
if (widget_ops) {
token_list = widget_ops[w->id].token_list;
token_list_size = widget_ops[w->id].token_list_size;
}
/* handle any special case widgets */
switch (w->id) {
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
dai = kzalloc(sizeof(*dai), GFP_KERNEL);
if (!dai) {
ret = -ENOMEM;
goto widget_free;
}
ret = sof_widget_parse_tokens(scomp, swidget, tw, token_list, token_list_size);
if (!ret)
ret = sof_connect_dai_widget(scomp, w, tw, dai);
if (ret < 0) {
kfree(dai);
break;
}
list_add(&dai->list, &sdev->dai_list);
swidget->private = dai;
break;
case snd_soc_dapm_effect:
/* check we have some tokens - we need at least process type */
if (le32_to_cpu(tw->priv.size) == 0) {
dev_err(scomp->dev, "error: process tokens not found\n");
ret = -EINVAL;
break;
}
ret = sof_widget_parse_tokens(scomp, swidget, tw, token_list, token_list_size);
break;
case snd_soc_dapm_pga:
if (!le32_to_cpu(tw->num_kcontrols)) {
dev_err(scomp->dev, "invalid kcontrol count %d for volume\n",
tw->num_kcontrols);
ret = -EINVAL;
break;
}
fallthrough;
case snd_soc_dapm_mixer:
case snd_soc_dapm_buffer:
case snd_soc_dapm_scheduler:
case snd_soc_dapm_aif_out:
case snd_soc_dapm_aif_in:
case snd_soc_dapm_src:
case snd_soc_dapm_asrc:
case snd_soc_dapm_siggen:
case snd_soc_dapm_mux:
case snd_soc_dapm_demux:
ret = sof_widget_parse_tokens(scomp, swidget, tw, token_list, token_list_size);
break;
case snd_soc_dapm_switch:
case snd_soc_dapm_dai_link:
case snd_soc_dapm_kcontrol:
default:
dev_dbg(scomp->dev, "widget type %d name %s not handled\n", swidget->id, tw->name);
break;
}
/* check token parsing reply */
if (ret < 0) {
dev_err(scomp->dev,
"error: failed to add widget id %d type %d name : %s stream %s\n",
tw->shift, swidget->id, tw->name,
strnlen(tw->sname, SNDRV_CTL_ELEM_ID_NAME_MAXLEN) > 0
? tw->sname : "none");
goto widget_free;
}
if (sof_debug_check_flag(SOF_DBG_DISABLE_MULTICORE)) {
swidget->core = SOF_DSP_PRIMARY_CORE;
} else {
int core = sof_get_token_value(SOF_TKN_COMP_CORE_ID, swidget->tuples,
swidget->num_tuples);
if (core >= 0)
swidget->core = core;
}
/* bind widget to external event */
if (tw->event_type) {
if (widget_ops && widget_ops[w->id].bind_event) {
ret = widget_ops[w->id].bind_event(scomp, swidget,
le16_to_cpu(tw->event_type));
if (ret) {
dev_err(scomp->dev, "widget event binding failed for %s\n",
swidget->widget->name);
goto free;
}
}
}
/* create and add pipeline for scheduler type widgets */
if (w->id == snd_soc_dapm_scheduler) {
struct snd_sof_pipeline *spipe;
spipe = kzalloc(sizeof(*spipe), GFP_KERNEL);
if (!spipe) {
ret = -ENOMEM;
goto free;
}
spipe->pipe_widget = swidget;
swidget->spipe = spipe;
list_add(&spipe->list, &sdev->pipeline_list);
}
w->dobj.private = swidget;
list_add(&swidget->list, &sdev->widget_list);
return ret;
free:
kfree(swidget->private);
kfree(swidget->tuples);
widget_free:
kfree(swidget);
return ret;
}
static int sof_route_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_sof_route *sroute;
sroute = dobj->private;
if (!sroute)
return 0;
/* free sroute and its private data */
kfree(sroute->private);
list_del(&sroute->list);
kfree(sroute);
return 0;
}
static int sof_widget_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
const struct sof_ipc_tplg_widget_ops *widget_ops;
const struct snd_kcontrol_new *kc;
struct snd_soc_dapm_widget *widget;
struct snd_sof_control *scontrol;
struct snd_sof_widget *swidget;
struct soc_mixer_control *sm;
struct soc_bytes_ext *sbe;
struct snd_sof_dai *dai;
struct soc_enum *se;
int i;
swidget = dobj->private;
if (!swidget)
return 0;
widget = swidget->widget;
switch (swidget->id) {
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
dai = swidget->private;
if (dai)
list_del(&dai->list);
sof_disconnect_dai_widget(scomp, widget);
break;
case snd_soc_dapm_scheduler:
{
struct snd_sof_pipeline *spipe = swidget->spipe;
list_del(&spipe->list);
kfree(spipe);
swidget->spipe = NULL;
break;
}
default:
break;
}
for (i = 0; i < widget->num_kcontrols; i++) {
kc = &widget->kcontrol_news[i];
switch (widget->dobj.widget.kcontrol_type[i]) {
case SND_SOC_TPLG_TYPE_MIXER:
sm = (struct soc_mixer_control *)kc->private_value;
scontrol = sm->dobj.private;
if (sm->max > 1)
kfree(scontrol->volume_table);
break;
case SND_SOC_TPLG_TYPE_ENUM:
se = (struct soc_enum *)kc->private_value;
scontrol = se->dobj.private;
break;
case SND_SOC_TPLG_TYPE_BYTES:
sbe = (struct soc_bytes_ext *)kc->private_value;
scontrol = sbe->dobj.private;
break;
default:
dev_warn(scomp->dev, "unsupported kcontrol_type\n");
goto out;
}
kfree(scontrol->ipc_control_data);
list_del(&scontrol->list);
kfree(scontrol->name);
kfree(scontrol);
}
out:
/* free IPC related data */
widget_ops = tplg_ops ? tplg_ops->widget : NULL;
if (widget_ops && widget_ops[swidget->id].ipc_free)
widget_ops[swidget->id].ipc_free(swidget);
ida_destroy(&swidget->output_queue_ida);
ida_destroy(&swidget->input_queue_ida);
sof_free_pin_binding(swidget, SOF_PIN_TYPE_INPUT);
sof_free_pin_binding(swidget, SOF_PIN_TYPE_OUTPUT);
kfree(swidget->tuples);
/* remove and free swidget object */
list_del(&swidget->list);
kfree(swidget);
return 0;
}
/*
* DAI HW configuration.
*/
/* FE DAI - used for any driver specific init */
static int sof_dai_load(struct snd_soc_component *scomp, int index,
struct snd_soc_dai_driver *dai_drv,
struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_pcm_ops *ipc_pcm_ops = sof_ipc_get_ops(sdev, pcm);
struct snd_soc_tplg_stream_caps *caps;
struct snd_soc_tplg_private *private = &pcm->priv;
struct snd_sof_pcm *spcm;
int stream;
int ret;
/* nothing to do for BEs atm */
if (!pcm)
return 0;
spcm = kzalloc(sizeof(*spcm), GFP_KERNEL);
if (!spcm)
return -ENOMEM;
spcm->scomp = scomp;
for_each_pcm_streams(stream) {
spcm->stream[stream].comp_id = COMP_ID_UNASSIGNED;
if (pcm->compress)
snd_sof_compr_init_elapsed_work(&spcm->stream[stream].period_elapsed_work);
else
snd_sof_pcm_init_elapsed_work(&spcm->stream[stream].period_elapsed_work);
}
spcm->pcm = *pcm;
dev_dbg(scomp->dev, "tplg: load pcm %s\n", pcm->dai_name);
/* perform pcm set op */
if (ipc_pcm_ops && ipc_pcm_ops->pcm_setup) {
ret = ipc_pcm_ops->pcm_setup(sdev, spcm);
if (ret < 0)
return ret;
}
dai_drv->dobj.private = spcm;
list_add(&spcm->list, &sdev->pcm_list);
ret = sof_parse_tokens(scomp, spcm, stream_tokens,
ARRAY_SIZE(stream_tokens), private->array,
le32_to_cpu(private->size));
if (ret) {
dev_err(scomp->dev, "error: parse stream tokens failed %d\n",
le32_to_cpu(private->size));
return ret;
}
/* do we need to allocate playback PCM DMA pages */
if (!spcm->pcm.playback)
goto capture;
stream = SNDRV_PCM_STREAM_PLAYBACK;
caps = &spcm->pcm.caps[stream];
/* allocate playback page table buffer */
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, sdev->dev,
PAGE_SIZE, &spcm->stream[stream].page_table);
if (ret < 0) {
dev_err(scomp->dev, "error: can't alloc page table for %s %d\n",
caps->name, ret);
return ret;
}
/* bind pcm to host comp */
ret = spcm_bind(scomp, spcm, stream);
if (ret) {
dev_err(scomp->dev,
"error: can't bind pcm to host\n");
goto free_playback_tables;
}
capture:
stream = SNDRV_PCM_STREAM_CAPTURE;
/* do we need to allocate capture PCM DMA pages */
if (!spcm->pcm.capture)
return ret;
caps = &spcm->pcm.caps[stream];
/* allocate capture page table buffer */
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, sdev->dev,
PAGE_SIZE, &spcm->stream[stream].page_table);
if (ret < 0) {
dev_err(scomp->dev, "error: can't alloc page table for %s %d\n",
caps->name, ret);
goto free_playback_tables;
}
/* bind pcm to host comp */
ret = spcm_bind(scomp, spcm, stream);
if (ret) {
dev_err(scomp->dev,
"error: can't bind pcm to host\n");
snd_dma_free_pages(&spcm->stream[stream].page_table);
goto free_playback_tables;
}
return ret;
free_playback_tables:
if (spcm->pcm.playback)
snd_dma_free_pages(&spcm->stream[SNDRV_PCM_STREAM_PLAYBACK].page_table);
return ret;
}
static int sof_dai_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_pcm_ops *ipc_pcm_ops = sof_ipc_get_ops(sdev, pcm);
struct snd_sof_pcm *spcm = dobj->private;
/* free PCM DMA pages */
if (spcm->pcm.playback)
snd_dma_free_pages(&spcm->stream[SNDRV_PCM_STREAM_PLAYBACK].page_table);
if (spcm->pcm.capture)
snd_dma_free_pages(&spcm->stream[SNDRV_PCM_STREAM_CAPTURE].page_table);
/* perform pcm free op */
if (ipc_pcm_ops && ipc_pcm_ops->pcm_free)
ipc_pcm_ops->pcm_free(sdev, spcm);
/* remove from list and free spcm */
list_del(&spcm->list);
kfree(spcm);
return 0;
}
static const struct sof_topology_token common_dai_link_tokens[] = {
{SOF_TKN_DAI_TYPE, SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_dai_type,
offsetof(struct snd_sof_dai_link, type)},
};
/* DAI link - used for any driver specific init */
static int sof_link_load(struct snd_soc_component *scomp, int index, struct snd_soc_dai_link *link,
struct snd_soc_tplg_link_config *cfg)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_soc_tplg_private *private = &cfg->priv;
const struct sof_token_info *token_list;
struct snd_sof_dai_link *slink;
u32 token_id = 0;
int num_tuples = 0;
int ret, num_sets;
if (!link->platforms) {
dev_err(scomp->dev, "error: no platforms\n");
return -EINVAL;
}
link->platforms->name = dev_name(scomp->dev);
if (tplg_ops && tplg_ops->link_setup) {
ret = tplg_ops->link_setup(sdev, link);
if (ret < 0)
return ret;
}
/* Set nonatomic property for FE dai links as their trigger action involves IPC's */
if (!link->no_pcm) {
link->nonatomic = true;
return 0;
}
/* check we have some tokens - we need at least DAI type */
if (le32_to_cpu(private->size) == 0) {
dev_err(scomp->dev, "error: expected tokens for DAI, none found\n");
return -EINVAL;
}
slink = kzalloc(sizeof(*slink), GFP_KERNEL);
if (!slink)
return -ENOMEM;
slink->num_hw_configs = le32_to_cpu(cfg->num_hw_configs);
slink->hw_configs = kmemdup(cfg->hw_config,
sizeof(*slink->hw_configs) * slink->num_hw_configs,
GFP_KERNEL);
if (!slink->hw_configs) {
kfree(slink);
return -ENOMEM;
}
slink->default_hw_cfg_id = le32_to_cpu(cfg->default_hw_config_id);
slink->link = link;
dev_dbg(scomp->dev, "tplg: %d hw_configs found, default id: %d for dai link %s!\n",
slink->num_hw_configs, slink->default_hw_cfg_id, link->name);
ret = sof_parse_tokens(scomp, slink, common_dai_link_tokens,
ARRAY_SIZE(common_dai_link_tokens),
private->array, le32_to_cpu(private->size));
if (ret < 0) {
dev_err(scomp->dev, "Failed tp parse common DAI link tokens\n");
kfree(slink->hw_configs);
kfree(slink);
return ret;
}
token_list = tplg_ops ? tplg_ops->token_list : NULL;
if (!token_list)
goto out;
/* calculate size of tuples array */
num_tuples += token_list[SOF_DAI_LINK_TOKENS].count;
num_sets = slink->num_hw_configs;
switch (slink->type) {
case SOF_DAI_INTEL_SSP:
token_id = SOF_SSP_TOKENS;
num_tuples += token_list[SOF_SSP_TOKENS].count * slink->num_hw_configs;
break;
case SOF_DAI_INTEL_DMIC:
token_id = SOF_DMIC_TOKENS;
num_tuples += token_list[SOF_DMIC_TOKENS].count;
/* Allocate memory for max PDM controllers */
num_tuples += token_list[SOF_DMIC_PDM_TOKENS].count * SOF_DAI_INTEL_DMIC_NUM_CTRL;
break;
case SOF_DAI_INTEL_HDA:
token_id = SOF_HDA_TOKENS;
num_tuples += token_list[SOF_HDA_TOKENS].count;
break;
case SOF_DAI_INTEL_ALH:
token_id = SOF_ALH_TOKENS;
num_tuples += token_list[SOF_ALH_TOKENS].count;
break;
case SOF_DAI_IMX_SAI:
token_id = SOF_SAI_TOKENS;
num_tuples += token_list[SOF_SAI_TOKENS].count;
break;
case SOF_DAI_IMX_ESAI:
token_id = SOF_ESAI_TOKENS;
num_tuples += token_list[SOF_ESAI_TOKENS].count;
break;
case SOF_DAI_MEDIATEK_AFE:
token_id = SOF_AFE_TOKENS;
num_tuples += token_list[SOF_AFE_TOKENS].count;
break;
case SOF_DAI_AMD_DMIC:
token_id = SOF_ACPDMIC_TOKENS;
num_tuples += token_list[SOF_ACPDMIC_TOKENS].count;
break;
case SOF_DAI_AMD_SP:
case SOF_DAI_AMD_HS:
case SOF_DAI_AMD_SP_VIRTUAL:
case SOF_DAI_AMD_HS_VIRTUAL:
token_id = SOF_ACPI2S_TOKENS;
num_tuples += token_list[SOF_ACPI2S_TOKENS].count;
break;
default:
break;
}
/* allocate memory for tuples array */
slink->tuples = kcalloc(num_tuples, sizeof(*slink->tuples), GFP_KERNEL);
if (!slink->tuples) {
kfree(slink->hw_configs);
kfree(slink);
return -ENOMEM;
}
if (token_list[SOF_DAI_LINK_TOKENS].tokens) {
/* parse one set of DAI link tokens */
ret = sof_copy_tuples(sdev, private->array, le32_to_cpu(private->size),
SOF_DAI_LINK_TOKENS, 1, slink->tuples,
num_tuples, &slink->num_tuples);
if (ret < 0) {
dev_err(scomp->dev, "failed to parse %s for dai link %s\n",
token_list[SOF_DAI_LINK_TOKENS].name, link->name);
goto err;
}
}
/* nothing more to do if there are no DAI type-specific tokens defined */
if (!token_id || !token_list[token_id].tokens)
goto out;
/* parse "num_sets" sets of DAI-specific tokens */
ret = sof_copy_tuples(sdev, private->array, le32_to_cpu(private->size),
token_id, num_sets, slink->tuples, num_tuples, &slink->num_tuples);
if (ret < 0) {
dev_err(scomp->dev, "failed to parse %s for dai link %s\n",
token_list[token_id].name, link->name);
goto err;
}
/* for DMIC, also parse all sets of DMIC PDM tokens based on active PDM count */
if (token_id == SOF_DMIC_TOKENS) {
num_sets = sof_get_token_value(SOF_TKN_INTEL_DMIC_NUM_PDM_ACTIVE,
slink->tuples, slink->num_tuples);
if (num_sets < 0) {
dev_err(sdev->dev, "Invalid active PDM count for %s\n", link->name);
ret = num_sets;
goto err;
}
ret = sof_copy_tuples(sdev, private->array, le32_to_cpu(private->size),
SOF_DMIC_PDM_TOKENS, num_sets, slink->tuples,
num_tuples, &slink->num_tuples);
if (ret < 0) {
dev_err(scomp->dev, "failed to parse %s for dai link %s\n",
token_list[SOF_DMIC_PDM_TOKENS].name, link->name);
goto err;
}
}
out:
link->dobj.private = slink;
list_add(&slink->list, &sdev->dai_link_list);
return 0;
err:
kfree(slink->tuples);
kfree(slink->hw_configs);
kfree(slink);
return ret;
}
static int sof_link_unload(struct snd_soc_component *scomp, struct snd_soc_dobj *dobj)
{
struct snd_sof_dai_link *slink = dobj->private;
if (!slink)
return 0;
kfree(slink->tuples);
list_del(&slink->list);
kfree(slink->hw_configs);
kfree(slink);
dobj->private = NULL;
return 0;
}
/* DAI link - used for any driver specific init */
static int sof_route_load(struct snd_soc_component *scomp, int index,
struct snd_soc_dapm_route *route)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_widget *source_swidget, *sink_swidget;
struct snd_soc_dobj *dobj = &route->dobj;
struct snd_sof_route *sroute;
int ret = 0;
/* allocate memory for sroute and connect */
sroute = kzalloc(sizeof(*sroute), GFP_KERNEL);
if (!sroute)
return -ENOMEM;
sroute->scomp = scomp;
dev_dbg(scomp->dev, "sink %s control %s source %s\n",
route->sink, route->control ? route->control : "none",
route->source);
/* source component */
source_swidget = snd_sof_find_swidget(scomp, (char *)route->source);
if (!source_swidget) {
dev_err(scomp->dev, "error: source %s not found\n",
route->source);
ret = -EINVAL;
goto err;
}
/*
* Virtual widgets of type output/out_drv may be added in topology
* for compatibility. These are not handled by the FW.
* So, don't send routes whose source/sink widget is of such types
* to the DSP.
*/
if (source_swidget->id == snd_soc_dapm_out_drv ||
source_swidget->id == snd_soc_dapm_output)
goto err;
/* sink component */
sink_swidget = snd_sof_find_swidget(scomp, (char *)route->sink);
if (!sink_swidget) {
dev_err(scomp->dev, "error: sink %s not found\n",
route->sink);
ret = -EINVAL;
goto err;
}
/*
* Don't send routes whose sink widget is of type
* output or out_drv to the DSP
*/
if (sink_swidget->id == snd_soc_dapm_out_drv ||
sink_swidget->id == snd_soc_dapm_output)
goto err;
sroute->route = route;
dobj->private = sroute;
sroute->src_widget = source_swidget;
sroute->sink_widget = sink_swidget;
/* add route to route list */
list_add(&sroute->list, &sdev->route_list);
return 0;
err:
kfree(sroute);
return ret;
}
/**
* sof_set_widget_pipeline - Set pipeline for a component
* @sdev: pointer to struct snd_sof_dev
* @spipe: pointer to struct snd_sof_pipeline
* @swidget: pointer to struct snd_sof_widget that has the same pipeline ID as @pipe_widget
*
* Return: 0 if successful, -EINVAL on error.
* The function checks if @swidget is associated with any volatile controls. If so, setting
* the dynamic_pipeline_widget is disallowed.
*/
static int sof_set_widget_pipeline(struct snd_sof_dev *sdev, struct snd_sof_pipeline *spipe,
struct snd_sof_widget *swidget)
{
struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
struct snd_sof_control *scontrol;
if (pipe_widget->dynamic_pipeline_widget) {
/* dynamic widgets cannot have volatile kcontrols */
list_for_each_entry(scontrol, &sdev->kcontrol_list, list)
if (scontrol->comp_id == swidget->comp_id &&
(scontrol->access & SNDRV_CTL_ELEM_ACCESS_VOLATILE)) {
dev_err(sdev->dev,
"error: volatile control found for dynamic widget %s\n",
swidget->widget->name);
return -EINVAL;
}
}
/* set the pipeline and apply the dynamic_pipeline_widget_flag */
swidget->spipe = spipe;
swidget->dynamic_pipeline_widget = pipe_widget->dynamic_pipeline_widget;
return 0;
}
/* completion - called at completion of firmware loading */
static int sof_complete(struct snd_soc_component *scomp)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
const struct sof_ipc_tplg_widget_ops *widget_ops;
struct snd_sof_control *scontrol;
struct snd_sof_pipeline *spipe;
int ret;
widget_ops = tplg_ops ? tplg_ops->widget : NULL;
/* first update all control IPC structures based on the IPC version */
if (tplg_ops && tplg_ops->control_setup)
list_for_each_entry(scontrol, &sdev->kcontrol_list, list) {
ret = tplg_ops->control_setup(sdev, scontrol);
if (ret < 0) {
dev_err(sdev->dev, "failed updating IPC struct for control %s\n",
scontrol->name);
return ret;
}
}
/* set up the IPC structures for the pipeline widgets */
list_for_each_entry(spipe, &sdev->pipeline_list, list) {
struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
struct snd_sof_widget *swidget;
pipe_widget->instance_id = -EINVAL;
/* Update the scheduler widget's IPC structure */
if (widget_ops && widget_ops[pipe_widget->id].ipc_setup) {
ret = widget_ops[pipe_widget->id].ipc_setup(pipe_widget);
if (ret < 0) {
dev_err(sdev->dev, "failed updating IPC struct for %s\n",
pipe_widget->widget->name);
return ret;
}
}
/* set the pipeline and update the IPC structure for the non scheduler widgets */
list_for_each_entry(swidget, &sdev->widget_list, list)
if (swidget->widget->id != snd_soc_dapm_scheduler &&
swidget->pipeline_id == pipe_widget->pipeline_id) {
ret = sof_set_widget_pipeline(sdev, spipe, swidget);
if (ret < 0)
return ret;
if (widget_ops && widget_ops[swidget->id].ipc_setup) {
ret = widget_ops[swidget->id].ipc_setup(swidget);
if (ret < 0) {
dev_err(sdev->dev,
"failed updating IPC struct for %s\n",
swidget->widget->name);
return ret;
}
}
}
}
/* verify topology components loading including dynamic pipelines */
if (sof_debug_check_flag(SOF_DBG_VERIFY_TPLG)) {
if (tplg_ops && tplg_ops->set_up_all_pipelines &&
tplg_ops->tear_down_all_pipelines) {
ret = tplg_ops->set_up_all_pipelines(sdev, true);
if (ret < 0) {
dev_err(sdev->dev, "Failed to set up all topology pipelines: %d\n",
ret);
return ret;
}
ret = tplg_ops->tear_down_all_pipelines(sdev, true);
if (ret < 0) {
dev_err(sdev->dev, "Failed to tear down topology pipelines: %d\n",
ret);
return ret;
}
}
}
/* set up static pipelines */
if (tplg_ops && tplg_ops->set_up_all_pipelines)
return tplg_ops->set_up_all_pipelines(sdev, false);
return 0;
}
/* manifest - optional to inform component of manifest */
static int sof_manifest(struct snd_soc_component *scomp, int index,
struct snd_soc_tplg_manifest *man)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->parse_manifest)
return tplg_ops->parse_manifest(scomp, index, man);
return 0;
}
/* vendor specific kcontrol handlers available for binding */
static const struct snd_soc_tplg_kcontrol_ops sof_io_ops[] = {
{SOF_TPLG_KCTL_VOL_ID, snd_sof_volume_get, snd_sof_volume_put},
{SOF_TPLG_KCTL_BYTES_ID, snd_sof_bytes_get, snd_sof_bytes_put},
{SOF_TPLG_KCTL_ENUM_ID, snd_sof_enum_get, snd_sof_enum_put},
{SOF_TPLG_KCTL_SWITCH_ID, snd_sof_switch_get, snd_sof_switch_put},
};
/* vendor specific bytes ext handlers available for binding */
static const struct snd_soc_tplg_bytes_ext_ops sof_bytes_ext_ops[] = {
{SOF_TPLG_KCTL_BYTES_ID, snd_sof_bytes_ext_get, snd_sof_bytes_ext_put},
{SOF_TPLG_KCTL_BYTES_VOLATILE_RO, snd_sof_bytes_ext_volatile_get},
};
static struct snd_soc_tplg_ops sof_tplg_ops = {
/* external kcontrol init - used for any driver specific init */
.control_load = sof_control_load,
.control_unload = sof_control_unload,
/* external kcontrol init - used for any driver specific init */
.dapm_route_load = sof_route_load,
.dapm_route_unload = sof_route_unload,
/* external widget init - used for any driver specific init */
/* .widget_load is not currently used */
.widget_ready = sof_widget_ready,
.widget_unload = sof_widget_unload,
/* FE DAI - used for any driver specific init */
.dai_load = sof_dai_load,
.dai_unload = sof_dai_unload,
/* DAI link - used for any driver specific init */
.link_load = sof_link_load,
.link_unload = sof_link_unload,
/* completion - called at completion of firmware loading */
.complete = sof_complete,
/* manifest - optional to inform component of manifest */
.manifest = sof_manifest,
/* vendor specific kcontrol handlers available for binding */
.io_ops = sof_io_ops,
.io_ops_count = ARRAY_SIZE(sof_io_ops),
/* vendor specific bytes ext handlers available for binding */
.bytes_ext_ops = sof_bytes_ext_ops,
.bytes_ext_ops_count = ARRAY_SIZE(sof_bytes_ext_ops),
};
static int snd_sof_dspless_kcontrol(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
return 0;
}
static const struct snd_soc_tplg_kcontrol_ops sof_dspless_io_ops[] = {
{SOF_TPLG_KCTL_VOL_ID, snd_sof_dspless_kcontrol, snd_sof_dspless_kcontrol},
{SOF_TPLG_KCTL_BYTES_ID, snd_sof_dspless_kcontrol, snd_sof_dspless_kcontrol},
{SOF_TPLG_KCTL_ENUM_ID, snd_sof_dspless_kcontrol, snd_sof_dspless_kcontrol},
{SOF_TPLG_KCTL_SWITCH_ID, snd_sof_dspless_kcontrol, snd_sof_dspless_kcontrol},
};
static int snd_sof_dspless_bytes_ext_get(struct snd_kcontrol *kcontrol,
unsigned int __user *binary_data,
unsigned int size)
{
return 0;
}
static int snd_sof_dspless_bytes_ext_put(struct snd_kcontrol *kcontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
return 0;
}
static const struct snd_soc_tplg_bytes_ext_ops sof_dspless_bytes_ext_ops[] = {
{SOF_TPLG_KCTL_BYTES_ID, snd_sof_dspless_bytes_ext_get, snd_sof_dspless_bytes_ext_put},
{SOF_TPLG_KCTL_BYTES_VOLATILE_RO, snd_sof_dspless_bytes_ext_get},
};
/* external widget init - used for any driver specific init */
static int sof_dspless_widget_ready(struct snd_soc_component *scomp, int index,
struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tw)
{
if (WIDGET_IS_DAI(w->id)) {
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_widget *swidget;
struct snd_sof_dai dai;
int ret;
swidget = kzalloc(sizeof(*swidget), GFP_KERNEL);
if (!swidget)
return -ENOMEM;
memset(&dai, 0, sizeof(dai));
ret = sof_connect_dai_widget(scomp, w, tw, &dai);
if (ret) {
kfree(swidget);
return ret;
}
swidget->scomp = scomp;
swidget->widget = w;
mutex_init(&swidget->setup_mutex);
w->dobj.private = swidget;
list_add(&swidget->list, &sdev->widget_list);
}
return 0;
}
static int sof_dspless_widget_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_soc_dapm_widget *w = container_of(dobj, struct snd_soc_dapm_widget, dobj);
if (WIDGET_IS_DAI(w->id)) {
struct snd_sof_widget *swidget = dobj->private;
sof_disconnect_dai_widget(scomp, w);
if (!swidget)
return 0;
/* remove and free swidget object */
list_del(&swidget->list);
kfree(swidget);
}
return 0;
}
static int sof_dspless_link_load(struct snd_soc_component *scomp, int index,
struct snd_soc_dai_link *link,
struct snd_soc_tplg_link_config *cfg)
{
link->platforms->name = dev_name(scomp->dev);
/* Set nonatomic property for FE dai links for FE-BE compatibility */
if (!link->no_pcm)
link->nonatomic = true;
return 0;
}
static struct snd_soc_tplg_ops sof_dspless_tplg_ops = {
/* external widget init - used for any driver specific init */
.widget_ready = sof_dspless_widget_ready,
.widget_unload = sof_dspless_widget_unload,
/* FE DAI - used for any driver specific init */
.dai_load = sof_dai_load,
.dai_unload = sof_dai_unload,
/* DAI link - used for any driver specific init */
.link_load = sof_dspless_link_load,
/* vendor specific kcontrol handlers available for binding */
.io_ops = sof_dspless_io_ops,
.io_ops_count = ARRAY_SIZE(sof_dspless_io_ops),
/* vendor specific bytes ext handlers available for binding */
.bytes_ext_ops = sof_dspless_bytes_ext_ops,
.bytes_ext_ops_count = ARRAY_SIZE(sof_dspless_bytes_ext_ops),
};
int snd_sof_load_topology(struct snd_soc_component *scomp, const char *file)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct firmware *fw;
int ret;
dev_dbg(scomp->dev, "loading topology:%s\n", file);
ret = request_firmware(&fw, file, scomp->dev);
if (ret < 0) {
dev_err(scomp->dev, "error: tplg request firmware %s failed err: %d\n",
file, ret);
dev_err(scomp->dev,
"you may need to download the firmware from https://github.com/thesofproject/sof-bin/\n");
return ret;
}
if (sdev->dspless_mode_selected)
ret = snd_soc_tplg_component_load(scomp, &sof_dspless_tplg_ops, fw);
else
ret = snd_soc_tplg_component_load(scomp, &sof_tplg_ops, fw);
if (ret < 0) {
dev_err(scomp->dev, "error: tplg component load failed %d\n",
ret);
ret = -EINVAL;
}
release_firmware(fw);
if (ret >= 0 && sdev->led_present)
ret = snd_ctl_led_request();
return ret;
}
EXPORT_SYMBOL(snd_sof_load_topology);
| linux-master | sound/soc/sof/topology.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/pci.h>
#include "ops.h"
static
bool snd_sof_pci_update_bits_unlocked(struct snd_sof_dev *sdev, u32 offset,
u32 mask, u32 value)
{
struct pci_dev *pci = to_pci_dev(sdev->dev);
unsigned int old, new;
u32 ret = 0;
pci_read_config_dword(pci, offset, &ret);
old = ret;
dev_dbg(sdev->dev, "Debug PCIR: %8.8x at %8.8x\n", old & mask, offset);
new = (old & ~mask) | (value & mask);
if (old == new)
return false;
pci_write_config_dword(pci, offset, new);
dev_dbg(sdev->dev, "Debug PCIW: %8.8x at %8.8x\n", value,
offset);
return true;
}
bool snd_sof_pci_update_bits(struct snd_sof_dev *sdev, u32 offset,
u32 mask, u32 value)
{
unsigned long flags;
bool change;
spin_lock_irqsave(&sdev->hw_lock, flags);
change = snd_sof_pci_update_bits_unlocked(sdev, offset, mask, value);
spin_unlock_irqrestore(&sdev->hw_lock, flags);
return change;
}
EXPORT_SYMBOL(snd_sof_pci_update_bits);
bool snd_sof_dsp_update_bits_unlocked(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u32 mask, u32 value)
{
unsigned int old, new;
u32 ret;
ret = snd_sof_dsp_read(sdev, bar, offset);
old = ret;
new = (old & ~mask) | (value & mask);
if (old == new)
return false;
snd_sof_dsp_write(sdev, bar, offset, new);
return true;
}
EXPORT_SYMBOL(snd_sof_dsp_update_bits_unlocked);
bool snd_sof_dsp_update_bits64_unlocked(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u64 mask, u64 value)
{
u64 old, new;
old = snd_sof_dsp_read64(sdev, bar, offset);
new = (old & ~mask) | (value & mask);
if (old == new)
return false;
snd_sof_dsp_write64(sdev, bar, offset, new);
return true;
}
EXPORT_SYMBOL(snd_sof_dsp_update_bits64_unlocked);
/* This is for registers bits with attribute RWC */
bool snd_sof_dsp_update_bits(struct snd_sof_dev *sdev, u32 bar, u32 offset,
u32 mask, u32 value)
{
unsigned long flags;
bool change;
spin_lock_irqsave(&sdev->hw_lock, flags);
change = snd_sof_dsp_update_bits_unlocked(sdev, bar, offset, mask,
value);
spin_unlock_irqrestore(&sdev->hw_lock, flags);
return change;
}
EXPORT_SYMBOL(snd_sof_dsp_update_bits);
bool snd_sof_dsp_update_bits64(struct snd_sof_dev *sdev, u32 bar, u32 offset,
u64 mask, u64 value)
{
unsigned long flags;
bool change;
spin_lock_irqsave(&sdev->hw_lock, flags);
change = snd_sof_dsp_update_bits64_unlocked(sdev, bar, offset, mask,
value);
spin_unlock_irqrestore(&sdev->hw_lock, flags);
return change;
}
EXPORT_SYMBOL(snd_sof_dsp_update_bits64);
static
void snd_sof_dsp_update_bits_forced_unlocked(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u32 mask, u32 value)
{
unsigned int old, new;
u32 ret;
ret = snd_sof_dsp_read(sdev, bar, offset);
old = ret;
new = (old & ~mask) | (value & mask);
snd_sof_dsp_write(sdev, bar, offset, new);
}
/* This is for registers bits with attribute RWC */
void snd_sof_dsp_update_bits_forced(struct snd_sof_dev *sdev, u32 bar,
u32 offset, u32 mask, u32 value)
{
unsigned long flags;
spin_lock_irqsave(&sdev->hw_lock, flags);
snd_sof_dsp_update_bits_forced_unlocked(sdev, bar, offset, mask, value);
spin_unlock_irqrestore(&sdev->hw_lock, flags);
}
EXPORT_SYMBOL(snd_sof_dsp_update_bits_forced);
/**
* snd_sof_dsp_panic - handle a received DSP panic message
* @sdev: Pointer to the device's sdev
* @offset: offset of panic information
* @non_recoverable: the panic is fatal, no recovery will be done by the caller
*/
void snd_sof_dsp_panic(struct snd_sof_dev *sdev, u32 offset, bool non_recoverable)
{
/*
* if DSP is not ready and the dsp_oops_offset is not yet set, use the
* offset from the panic message.
*/
if (!sdev->dsp_oops_offset)
sdev->dsp_oops_offset = offset;
/*
* Print warning if the offset from the panic message differs from
* dsp_oops_offset
*/
if (sdev->dsp_oops_offset != offset)
dev_warn(sdev->dev,
"%s: dsp_oops_offset %zu differs from panic offset %u\n",
__func__, sdev->dsp_oops_offset, offset);
/*
* Set the fw_state to crashed only in case of non recoverable DSP panic
* event.
* Use different message within the snd_sof_dsp_dbg_dump() depending on
* the non_recoverable flag.
*/
sdev->dbg_dump_printed = false;
if (non_recoverable) {
snd_sof_dsp_dbg_dump(sdev, "DSP panic!",
SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX);
sof_set_fw_state(sdev, SOF_FW_CRASHED);
sof_fw_trace_fw_crashed(sdev);
} else {
snd_sof_dsp_dbg_dump(sdev,
"DSP panic (recovery will be attempted)",
SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX);
}
}
EXPORT_SYMBOL(snd_sof_dsp_panic);
| linux-master | sound/soc/sof/ops.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
// Author: Peter Ujfalusi <[email protected]>
//
#include <linux/auxiliary_bus.h>
#include <linux/completion.h>
#include <linux/debugfs.h>
#include <linux/ktime.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <sound/sof/header.h>
#include <sound/sof/ipc4/header.h>
#include "sof-client.h"
#define SOF_IPC_CLIENT_SUSPEND_DELAY_MS 3000
struct sof_msg_inject_priv {
struct dentry *dfs_file;
size_t max_msg_size;
enum sof_ipc_type ipc_type;
void *tx_buffer;
void *rx_buffer;
};
static int sof_msg_inject_dfs_open(struct inode *inode, struct file *file)
{
struct sof_client_dev *cdev = inode->i_private;
int ret;
if (sof_client_get_fw_state(cdev) == SOF_FW_CRASHED)
return -ENODEV;
ret = debugfs_file_get(file->f_path.dentry);
if (unlikely(ret))
return ret;
ret = simple_open(inode, file);
if (ret)
debugfs_file_put(file->f_path.dentry);
return ret;
}
static ssize_t sof_msg_inject_dfs_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_msg_inject_priv *priv = cdev->data;
struct sof_ipc_reply *rhdr = priv->rx_buffer;
if (!rhdr->hdr.size || !count || *ppos)
return 0;
if (count > rhdr->hdr.size)
count = rhdr->hdr.size;
if (copy_to_user(buffer, priv->rx_buffer, count))
return -EFAULT;
*ppos += count;
return count;
}
static ssize_t sof_msg_inject_ipc4_dfs_read(struct file *file,
char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_msg_inject_priv *priv = cdev->data;
struct sof_ipc4_msg *ipc4_msg = priv->rx_buffer;
size_t header_size = sizeof(ipc4_msg->header_u64);
size_t remaining;
if (!ipc4_msg->header_u64 || !count || *ppos)
return 0;
/* we need space for the header at minimum (u64) */
if (count < header_size)
return -ENOSPC;
remaining = header_size;
/* Only get large config have payload */
if (SOF_IPC4_MSG_IS_MODULE_MSG(ipc4_msg->primary) &&
(SOF_IPC4_MSG_TYPE_GET(ipc4_msg->primary) == SOF_IPC4_MOD_LARGE_CONFIG_GET))
remaining += ipc4_msg->data_size;
if (count > remaining)
count = remaining;
else if (count < remaining)
remaining = count;
/* copy the header first */
if (copy_to_user(buffer, &ipc4_msg->header_u64, header_size))
return -EFAULT;
*ppos += header_size;
remaining -= header_size;
if (!remaining)
return count;
if (remaining > ipc4_msg->data_size)
remaining = ipc4_msg->data_size;
/* Copy the payload */
if (copy_to_user(buffer + *ppos, ipc4_msg->data_ptr, remaining))
return -EFAULT;
*ppos += remaining;
return count;
}
static int sof_msg_inject_send_message(struct sof_client_dev *cdev)
{
struct sof_msg_inject_priv *priv = cdev->data;
struct device *dev = &cdev->auxdev.dev;
int ret, err;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(dev, "debugfs write failed to resume %d\n", ret);
return ret;
}
/* send the message */
ret = sof_client_ipc_tx_message(cdev, priv->tx_buffer, priv->rx_buffer,
priv->max_msg_size);
if (ret)
dev_err(dev, "IPC message send failed: %d\n", ret);
pm_runtime_mark_last_busy(dev);
err = pm_runtime_put_autosuspend(dev);
if (err < 0)
dev_err_ratelimited(dev, "debugfs write failed to idle %d\n", err);
return ret;
}
static ssize_t sof_msg_inject_dfs_write(struct file *file, const char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_msg_inject_priv *priv = cdev->data;
ssize_t size;
int ret;
if (*ppos)
return 0;
size = simple_write_to_buffer(priv->tx_buffer, priv->max_msg_size,
ppos, buffer, count);
if (size < 0)
return size;
if (size != count)
return -EFAULT;
memset(priv->rx_buffer, 0, priv->max_msg_size);
ret = sof_msg_inject_send_message(cdev);
/* return the error code if test failed */
if (ret < 0)
size = ret;
return size;
};
static ssize_t sof_msg_inject_ipc4_dfs_write(struct file *file,
const char __user *buffer,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_msg_inject_priv *priv = cdev->data;
struct sof_ipc4_msg *ipc4_msg = priv->tx_buffer;
size_t data_size;
int ret;
if (*ppos)
return 0;
if (count < sizeof(ipc4_msg->header_u64))
return -EINVAL;
/* copy the header first */
if (copy_from_user(&ipc4_msg->header_u64, buffer,
sizeof(ipc4_msg->header_u64)))
return -EFAULT;
data_size = count - sizeof(ipc4_msg->header_u64);
if (data_size > priv->max_msg_size)
return -EINVAL;
/* Copy the payload */
if (copy_from_user(ipc4_msg->data_ptr,
buffer + sizeof(ipc4_msg->header_u64), data_size))
return -EFAULT;
ipc4_msg->data_size = data_size;
/* Initialize the reply storage */
ipc4_msg = priv->rx_buffer;
ipc4_msg->header_u64 = 0;
ipc4_msg->data_size = priv->max_msg_size;
memset(ipc4_msg->data_ptr, 0, priv->max_msg_size);
ret = sof_msg_inject_send_message(cdev);
/* return the error code if test failed */
if (ret < 0)
return ret;
return count;
};
static int sof_msg_inject_dfs_release(struct inode *inode, struct file *file)
{
debugfs_file_put(file->f_path.dentry);
return 0;
}
static const struct file_operations sof_msg_inject_fops = {
.open = sof_msg_inject_dfs_open,
.read = sof_msg_inject_dfs_read,
.write = sof_msg_inject_dfs_write,
.llseek = default_llseek,
.release = sof_msg_inject_dfs_release,
.owner = THIS_MODULE,
};
static const struct file_operations sof_msg_inject_ipc4_fops = {
.open = sof_msg_inject_dfs_open,
.read = sof_msg_inject_ipc4_dfs_read,
.write = sof_msg_inject_ipc4_dfs_write,
.llseek = default_llseek,
.release = sof_msg_inject_dfs_release,
.owner = THIS_MODULE,
};
static int sof_msg_inject_probe(struct auxiliary_device *auxdev,
const struct auxiliary_device_id *id)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct dentry *debugfs_root = sof_client_get_debugfs_root(cdev);
static const struct file_operations *fops;
struct device *dev = &auxdev->dev;
struct sof_msg_inject_priv *priv;
size_t alloc_size;
/* allocate memory for client data */
priv = devm_kzalloc(&auxdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->ipc_type = sof_client_get_ipc_type(cdev);
priv->max_msg_size = sof_client_get_ipc_max_payload_size(cdev);
alloc_size = priv->max_msg_size;
if (priv->ipc_type == SOF_INTEL_IPC4)
alloc_size += sizeof(struct sof_ipc4_msg);
priv->tx_buffer = devm_kmalloc(dev, alloc_size, GFP_KERNEL);
priv->rx_buffer = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
if (!priv->tx_buffer || !priv->rx_buffer)
return -ENOMEM;
if (priv->ipc_type == SOF_INTEL_IPC4) {
struct sof_ipc4_msg *ipc4_msg;
ipc4_msg = priv->tx_buffer;
ipc4_msg->data_ptr = priv->tx_buffer + sizeof(struct sof_ipc4_msg);
ipc4_msg = priv->rx_buffer;
ipc4_msg->data_ptr = priv->rx_buffer + sizeof(struct sof_ipc4_msg);
fops = &sof_msg_inject_ipc4_fops;
} else {
fops = &sof_msg_inject_fops;
}
cdev->data = priv;
priv->dfs_file = debugfs_create_file("ipc_msg_inject", 0644, debugfs_root,
cdev, fops);
/* enable runtime PM */
pm_runtime_set_autosuspend_delay(dev, SOF_IPC_CLIENT_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_idle(dev);
return 0;
}
static void sof_msg_inject_remove(struct auxiliary_device *auxdev)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct sof_msg_inject_priv *priv = cdev->data;
pm_runtime_disable(&auxdev->dev);
debugfs_remove(priv->dfs_file);
}
static const struct auxiliary_device_id sof_msg_inject_client_id_table[] = {
{ .name = "snd_sof.msg_injector" },
{},
};
MODULE_DEVICE_TABLE(auxiliary, sof_msg_inject_client_id_table);
/*
* No need for driver pm_ops as the generic pm callbacks in the auxiliary bus
* type are enough to ensure that the parent SOF device resumes to bring the DSP
* back to D0.
* Driver name will be set based on KBUILD_MODNAME.
*/
static struct auxiliary_driver sof_msg_inject_client_drv = {
.probe = sof_msg_inject_probe,
.remove = sof_msg_inject_remove,
.id_table = sof_msg_inject_client_id_table,
};
module_auxiliary_driver(sof_msg_inject_client_drv);
MODULE_DESCRIPTION("SOF IPC Message Injector Client Driver");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_CLIENT);
| linux-master | sound/soc/sof/sof-client-ipc-msg-injector.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
// PCM Layer, interface between ALSA and IPC.
//
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <sound/sof.h>
#include <trace/events/sof.h>
#include "sof-of-dev.h"
#include "sof-priv.h"
#include "sof-audio.h"
#include "sof-utils.h"
#include "ops.h"
/* Create DMA buffer page table for DSP */
static int create_page_table(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
unsigned char *dma_area, size_t size)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_pcm *spcm;
struct snd_dma_buffer *dmab = snd_pcm_get_dma_buf(substream);
int stream = substream->stream;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
return snd_sof_create_page_table(component->dev, dmab,
spcm->stream[stream].page_table.area, size);
}
/*
* sof pcm period elapse work
*/
static void snd_sof_pcm_period_elapsed_work(struct work_struct *work)
{
struct snd_sof_pcm_stream *sps =
container_of(work, struct snd_sof_pcm_stream,
period_elapsed_work);
snd_pcm_period_elapsed(sps->substream);
}
void snd_sof_pcm_init_elapsed_work(struct work_struct *work)
{
INIT_WORK(work, snd_sof_pcm_period_elapsed_work);
}
/*
* sof pcm period elapse, this could be called at irq thread context.
*/
void snd_sof_pcm_period_elapsed(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
struct snd_sof_pcm *spcm;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm) {
dev_err(component->dev,
"error: period elapsed for unknown stream!\n");
return;
}
/*
* snd_pcm_period_elapsed() can be called in interrupt context
* before IRQ_HANDLED is returned. Inside snd_pcm_period_elapsed(),
* when the PCM is done draining or xrun happened, a STOP IPC will
* then be sent and this IPC will hit IPC timeout.
* To avoid sending IPC before the previous IPC is handled, we
* schedule delayed work here to call the snd_pcm_period_elapsed().
*/
schedule_work(&spcm->stream[substream->stream].period_elapsed_work);
}
EXPORT_SYMBOL(snd_sof_pcm_period_elapsed);
static int
sof_pcm_setup_connected_widgets(struct snd_sof_dev *sdev, struct snd_soc_pcm_runtime *rtd,
struct snd_sof_pcm *spcm, struct snd_pcm_hw_params *params,
struct snd_sof_platform_stream_params *platform_params, int dir)
{
struct snd_soc_dai *dai;
int ret, j;
/* query DAPM for list of connected widgets and set them up */
for_each_rtd_cpu_dais(rtd, j, dai) {
struct snd_soc_dapm_widget_list *list;
ret = snd_soc_dapm_dai_get_connected_widgets(dai, dir, &list,
dpcm_end_walk_at_be);
if (ret < 0) {
dev_err(sdev->dev, "error: dai %s has no valid %s path\n", dai->name,
dir == SNDRV_PCM_STREAM_PLAYBACK ? "playback" : "capture");
return ret;
}
spcm->stream[dir].list = list;
ret = sof_widget_list_setup(sdev, spcm, params, platform_params, dir);
if (ret < 0) {
dev_err(sdev->dev, "error: failed widget list set up for pcm %d dir %d\n",
spcm->pcm.pcm_id, dir);
spcm->stream[dir].list = NULL;
snd_soc_dapm_dai_free_widgets(&list);
return ret;
}
}
return 0;
}
static int sof_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
const struct sof_ipc_pcm_ops *pcm_ops = sof_ipc_get_ops(sdev, pcm);
struct snd_sof_platform_stream_params platform_params = { 0 };
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_sof_pcm *spcm;
int ret;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
/*
* Handle repeated calls to hw_params() without free_pcm() in
* between. At least ALSA OSS emulation depends on this.
*/
if (pcm_ops && pcm_ops->hw_free && spcm->prepared[substream->stream]) {
ret = pcm_ops->hw_free(component, substream);
if (ret < 0)
return ret;
spcm->prepared[substream->stream] = false;
}
dev_dbg(component->dev, "pcm: hw params stream %d dir %d\n",
spcm->pcm.pcm_id, substream->stream);
ret = snd_sof_pcm_platform_hw_params(sdev, substream, params, &platform_params);
if (ret < 0) {
dev_err(component->dev, "platform hw params failed\n");
return ret;
}
/* if this is a repeated hw_params without hw_free, skip setting up widgets */
if (!spcm->stream[substream->stream].list) {
ret = sof_pcm_setup_connected_widgets(sdev, rtd, spcm, params, &platform_params,
substream->stream);
if (ret < 0)
return ret;
}
/* create compressed page table for audio firmware */
if (runtime->buffer_changed) {
ret = create_page_table(component, substream, runtime->dma_area,
runtime->dma_bytes);
if (ret < 0)
return ret;
}
if (pcm_ops && pcm_ops->hw_params) {
ret = pcm_ops->hw_params(component, substream, params, &platform_params);
if (ret < 0)
return ret;
}
spcm->prepared[substream->stream] = true;
/* save pcm hw_params */
memcpy(&spcm->params[substream->stream], params, sizeof(*params));
return 0;
}
static int sof_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
const struct sof_ipc_pcm_ops *pcm_ops = sof_ipc_get_ops(sdev, pcm);
struct snd_sof_pcm *spcm;
int ret, err = 0;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
dev_dbg(component->dev, "pcm: free stream %d dir %d\n",
spcm->pcm.pcm_id, substream->stream);
if (spcm->prepared[substream->stream]) {
/* stop DMA first if needed */
if (pcm_ops && pcm_ops->platform_stop_during_hw_free)
snd_sof_pcm_platform_trigger(sdev, substream, SNDRV_PCM_TRIGGER_STOP);
/* free PCM in the DSP */
if (pcm_ops && pcm_ops->hw_free) {
ret = pcm_ops->hw_free(component, substream);
if (ret < 0)
err = ret;
}
spcm->prepared[substream->stream] = false;
}
/* reset DMA */
ret = snd_sof_pcm_platform_hw_free(sdev, substream);
if (ret < 0) {
dev_err(component->dev, "error: platform hw free failed\n");
err = ret;
}
/* free the DAPM widget list */
ret = sof_widget_list_free(sdev, spcm, substream->stream);
if (ret < 0)
err = ret;
cancel_work_sync(&spcm->stream[substream->stream].period_elapsed_work);
return err;
}
static int sof_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_pcm *spcm;
int ret;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
if (spcm->prepared[substream->stream])
return 0;
dev_dbg(component->dev, "pcm: prepare stream %d dir %d\n",
spcm->pcm.pcm_id, substream->stream);
/* set hw_params */
ret = sof_pcm_hw_params(component,
substream, &spcm->params[substream->stream]);
if (ret < 0) {
dev_err(component->dev,
"error: set pcm hw_params after resume\n");
return ret;
}
return 0;
}
/*
* FE dai link trigger actions are always executed in non-atomic context because
* they involve IPC's.
*/
static int sof_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
const struct sof_ipc_pcm_ops *pcm_ops = sof_ipc_get_ops(sdev, pcm);
struct snd_sof_pcm *spcm;
bool reset_hw_params = false;
bool ipc_first = false;
int ret = 0;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
dev_dbg(component->dev, "pcm: trigger stream %d dir %d cmd %d\n",
spcm->pcm.pcm_id, substream->stream, cmd);
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ipc_first = true;
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (pcm_ops && pcm_ops->ipc_first_on_start)
ipc_first = true;
break;
case SNDRV_PCM_TRIGGER_START:
if (spcm->stream[substream->stream].suspend_ignored) {
/*
* This case will be triggered when INFO_RESUME is
* not supported, no need to re-start streams that
* remained enabled in D0ix.
*/
spcm->stream[substream->stream].suspend_ignored = false;
return 0;
}
if (pcm_ops && pcm_ops->ipc_first_on_start)
ipc_first = true;
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
if (sdev->system_suspend_target == SOF_SUSPEND_S0IX &&
spcm->stream[substream->stream].d0i3_compatible) {
/*
* trap the event, not sending trigger stop to
* prevent the FW pipelines from being stopped,
* and mark the flag to ignore the upcoming DAPM
* PM events.
*/
spcm->stream[substream->stream].suspend_ignored = true;
return 0;
}
/* On suspend the DMA must be stopped in DSPless mode */
if (sdev->dspless_mode_selected)
reset_hw_params = true;
fallthrough;
case SNDRV_PCM_TRIGGER_STOP:
ipc_first = true;
if (pcm_ops && pcm_ops->reset_hw_params_during_stop)
reset_hw_params = true;
break;
default:
dev_err(component->dev, "Unhandled trigger cmd %d\n", cmd);
return -EINVAL;
}
if (!ipc_first)
snd_sof_pcm_platform_trigger(sdev, substream, cmd);
if (pcm_ops && pcm_ops->trigger)
ret = pcm_ops->trigger(component, substream, cmd);
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_START:
/* invoke platform trigger to start DMA only if pcm_ops is successful */
if (ipc_first && !ret)
snd_sof_pcm_platform_trigger(sdev, substream, cmd);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
/* invoke platform trigger to stop DMA even if pcm_ops isn't set or if it failed */
if (!pcm_ops || !pcm_ops->platform_stop_during_hw_free)
snd_sof_pcm_platform_trigger(sdev, substream, cmd);
break;
default:
break;
}
/* free PCM if reset_hw_params is set and the STOP IPC is successful */
if (!ret && reset_hw_params)
ret = sof_pcm_stream_free(sdev, substream, spcm, substream->stream, false);
return ret;
}
static snd_pcm_uframes_t sof_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_sof_pcm *spcm;
snd_pcm_uframes_t host, dai;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
/* use dsp ops pointer callback directly if set */
if (sof_ops(sdev)->pcm_pointer)
return sof_ops(sdev)->pcm_pointer(sdev, substream);
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
/* read position from DSP */
host = bytes_to_frames(substream->runtime,
spcm->stream[substream->stream].posn.host_posn);
dai = bytes_to_frames(substream->runtime,
spcm->stream[substream->stream].posn.dai_posn);
trace_sof_pcm_pointer_position(sdev, spcm, substream, host, dai);
return host;
}
static int sof_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_sof_dsp_ops *ops = sof_ops(sdev);
struct snd_sof_pcm *spcm;
struct snd_soc_tplg_stream_caps *caps;
int ret;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
dev_dbg(component->dev, "pcm: open stream %d dir %d\n",
spcm->pcm.pcm_id, substream->stream);
caps = &spcm->pcm.caps[substream->stream];
/* set runtime config */
runtime->hw.info = ops->hw_info; /* platform-specific */
/* set any runtime constraints based on topology */
runtime->hw.formats = le64_to_cpu(caps->formats);
runtime->hw.period_bytes_min = le32_to_cpu(caps->period_size_min);
runtime->hw.period_bytes_max = le32_to_cpu(caps->period_size_max);
runtime->hw.periods_min = le32_to_cpu(caps->periods_min);
runtime->hw.periods_max = le32_to_cpu(caps->periods_max);
/*
* caps->buffer_size_min is not used since the
* snd_pcm_hardware structure only defines buffer_bytes_max
*/
runtime->hw.buffer_bytes_max = le32_to_cpu(caps->buffer_size_max);
dev_dbg(component->dev, "period min %zd max %zd bytes\n",
runtime->hw.period_bytes_min,
runtime->hw.period_bytes_max);
dev_dbg(component->dev, "period count %d max %d\n",
runtime->hw.periods_min,
runtime->hw.periods_max);
dev_dbg(component->dev, "buffer max %zd bytes\n",
runtime->hw.buffer_bytes_max);
/* set wait time - TODO: come from topology */
substream->wait_time = 500;
spcm->stream[substream->stream].posn.host_posn = 0;
spcm->stream[substream->stream].posn.dai_posn = 0;
spcm->stream[substream->stream].substream = substream;
spcm->prepared[substream->stream] = false;
ret = snd_sof_pcm_platform_open(sdev, substream);
if (ret < 0)
dev_err(component->dev, "error: pcm open failed %d\n", ret);
return ret;
}
static int sof_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_sof_pcm *spcm;
int err;
/* nothing to do for BE */
if (rtd->dai_link->no_pcm)
return 0;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
dev_dbg(component->dev, "pcm: close stream %d dir %d\n",
spcm->pcm.pcm_id, substream->stream);
err = snd_sof_pcm_platform_close(sdev, substream);
if (err < 0) {
dev_err(component->dev, "error: pcm close failed %d\n",
err);
/*
* keep going, no point in preventing the close
* from happening
*/
}
return 0;
}
/*
* Pre-allocate playback/capture audio buffer pages.
* no need to explicitly release memory preallocated by sof_pcm_new in pcm_free
* snd_pcm_lib_preallocate_free_for_all() is called by the core.
*/
static int sof_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_sof_pcm *spcm;
struct snd_pcm *pcm = rtd->pcm;
struct snd_soc_tplg_stream_caps *caps;
int stream = SNDRV_PCM_STREAM_PLAYBACK;
/* find SOF PCM for this RTD */
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm) {
dev_warn(component->dev, "warn: can't find PCM with DAI ID %d\n",
rtd->dai_link->id);
return 0;
}
dev_dbg(component->dev, "creating new PCM %s\n", spcm->pcm.pcm_name);
/* do we need to pre-allocate playback audio buffer pages */
if (!spcm->pcm.playback)
goto capture;
caps = &spcm->pcm.caps[stream];
/* pre-allocate playback audio buffer pages */
dev_dbg(component->dev,
"spcm: allocate %s playback DMA buffer size 0x%x max 0x%x\n",
caps->name, caps->buffer_size_min, caps->buffer_size_max);
if (!pcm->streams[stream].substream) {
dev_err(component->dev, "error: NULL playback substream!\n");
return -EINVAL;
}
snd_pcm_set_managed_buffer(pcm->streams[stream].substream,
SNDRV_DMA_TYPE_DEV_SG, sdev->dev,
0, le32_to_cpu(caps->buffer_size_max));
capture:
stream = SNDRV_PCM_STREAM_CAPTURE;
/* do we need to pre-allocate capture audio buffer pages */
if (!spcm->pcm.capture)
return 0;
caps = &spcm->pcm.caps[stream];
/* pre-allocate capture audio buffer pages */
dev_dbg(component->dev,
"spcm: allocate %s capture DMA buffer size 0x%x max 0x%x\n",
caps->name, caps->buffer_size_min, caps->buffer_size_max);
if (!pcm->streams[stream].substream) {
dev_err(component->dev, "error: NULL capture substream!\n");
return -EINVAL;
}
snd_pcm_set_managed_buffer(pcm->streams[stream].substream,
SNDRV_DMA_TYPE_DEV_SG, sdev->dev,
0, le32_to_cpu(caps->buffer_size_max));
return 0;
}
/* fixup the BE DAI link to match any values from topology */
int sof_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd, struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
struct snd_sof_dai *dai =
snd_sof_find_dai(component, (char *)rtd->dai_link->name);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
const struct sof_ipc_pcm_ops *pcm_ops = sof_ipc_get_ops(sdev, pcm);
/* no topology exists for this BE, try a common configuration */
if (!dai) {
dev_warn(component->dev,
"warning: no topology found for BE DAI %s config\n",
rtd->dai_link->name);
/* set 48k, stereo, 16bits by default */
rate->min = 48000;
rate->max = 48000;
channels->min = 2;
channels->max = 2;
snd_mask_none(fmt);
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
if (pcm_ops && pcm_ops->dai_link_fixup)
return pcm_ops->dai_link_fixup(rtd, params);
return 0;
}
EXPORT_SYMBOL(sof_pcm_dai_link_fixup);
static int sof_pcm_probe(struct snd_soc_component *component)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_sof_pdata *plat_data = sdev->pdata;
const char *tplg_filename;
int ret;
/*
* make sure the device is pm_runtime_active before loading the
* topology and initiating IPC or bus transactions
*/
ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0 && ret != -EACCES)
return ret;
/* load the default topology */
sdev->component = component;
tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
"%s/%s",
plat_data->tplg_filename_prefix,
plat_data->tplg_filename);
if (!tplg_filename) {
ret = -ENOMEM;
goto pm_error;
}
ret = snd_sof_load_topology(component, tplg_filename);
if (ret < 0)
dev_err(component->dev, "error: failed to load DSP topology %d\n",
ret);
pm_error:
pm_runtime_mark_last_busy(component->dev);
pm_runtime_put_autosuspend(component->dev);
return ret;
}
static void sof_pcm_remove(struct snd_soc_component *component)
{
/* remove topology */
snd_soc_tplg_component_remove(component);
}
static int sof_pcm_ack(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
return snd_sof_pcm_platform_ack(sdev, substream);
}
static snd_pcm_sframes_t sof_pcm_delay(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
const struct sof_ipc_pcm_ops *pcm_ops = sof_ipc_get_ops(sdev, pcm);
if (pcm_ops && pcm_ops->delay)
return pcm_ops->delay(component, substream);
return 0;
}
void snd_sof_new_platform_drv(struct snd_sof_dev *sdev)
{
struct snd_soc_component_driver *pd = &sdev->plat_drv;
struct snd_sof_pdata *plat_data = sdev->pdata;
const char *drv_name;
if (plat_data->machine)
drv_name = plat_data->machine->drv_name;
else if (plat_data->of_machine)
drv_name = plat_data->of_machine->drv_name;
else
drv_name = NULL;
pd->name = "sof-audio-component";
pd->probe = sof_pcm_probe;
pd->remove = sof_pcm_remove;
pd->open = sof_pcm_open;
pd->close = sof_pcm_close;
pd->hw_params = sof_pcm_hw_params;
pd->prepare = sof_pcm_prepare;
pd->hw_free = sof_pcm_hw_free;
pd->trigger = sof_pcm_trigger;
pd->pointer = sof_pcm_pointer;
pd->ack = sof_pcm_ack;
pd->delay = sof_pcm_delay;
#if IS_ENABLED(CONFIG_SND_SOC_SOF_COMPRESS)
pd->compress_ops = &sof_compressed_ops;
#endif
pd->pcm_construct = sof_pcm_new;
pd->ignore_machine = drv_name;
pd->be_pcm_base = SOF_BE_PCM_BASE;
pd->use_dai_pcm_id = true;
pd->topology_name_prefix = "sof";
/* increment module refcount when a pcm is opened */
pd->module_get_upon_open = 1;
pd->legacy_dai_naming = 1;
/*
* The fixup is only needed when the DSP is in use as with the DSPless
* mode we are directly using the audio interface
*/
if (!sdev->dspless_mode_selected)
pd->be_hw_params_fixup = sof_pcm_dai_link_fixup;
}
| linux-master | sound/soc/sof/pcm.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
// Authors: Rander Wang <[email protected]>
// Peter Ujfalusi <[email protected]>
//
#include <linux/firmware.h>
#include <sound/sof/header.h>
#include <sound/sof/ipc4/header.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc4-fw-reg.h"
#include "ipc4-priv.h"
#include "ops.h"
static const struct sof_ipc4_fw_status {
int status;
char *msg;
} ipc4_status[] = {
{0, "The operation was successful"},
{1, "Invalid parameter specified"},
{2, "Unknown message type specified"},
{3, "Not enough space in the IPC reply buffer to complete the request"},
{4, "The system or resource is busy"},
{5, "Replaced ADSP IPC PENDING (unused)"},
{6, "Unknown error while processing the request"},
{7, "Unsupported operation requested"},
{8, "Reserved (ADSP_STAGE_UNINITIALIZED removed)"},
{9, "Specified resource not found"},
{10, "A resource's ID requested to be created is already assigned"},
{11, "Reserved (ADSP_IPC_OUT_OF_MIPS removed)"},
{12, "Required resource is in invalid state"},
{13, "Requested power transition failed to complete"},
{14, "Manifest of the library being loaded is invalid"},
{15, "Requested service or data is unavailable on the target platform"},
{42, "Library target address is out of storage memory range"},
{43, "Reserved"},
{44, "Image verification by CSE failed"},
{100, "General module management error"},
{101, "Module loading failed"},
{102, "Integrity check of the loaded module content failed"},
{103, "Attempt to unload code of the module in use"},
{104, "Other failure of module instance initialization request"},
{105, "Reserved (ADSP_IPC_OUT_OF_MIPS removed)"},
{106, "Reserved (ADSP_IPC_CONFIG_GET_ERROR removed)"},
{107, "Reserved (ADSP_IPC_CONFIG_SET_ERROR removed)"},
{108, "Reserved (ADSP_IPC_LARGE_CONFIG_GET_ERROR removed)"},
{109, "Reserved (ADSP_IPC_LARGE_CONFIG_SET_ERROR removed)"},
{110, "Invalid (out of range) module ID provided"},
{111, "Invalid module instance ID provided"},
{112, "Invalid queue (pin) ID provided"},
{113, "Invalid destination queue (pin) ID provided"},
{114, "Reserved (ADSP_IPC_BIND_UNBIND_DST_SINK_UNSUPPORTED removed)"},
{115, "Reserved (ADSP_IPC_UNLOAD_INST_EXISTS removed)"},
{116, "Invalid target code ID provided"},
{117, "Injection DMA buffer is too small for probing the input pin"},
{118, "Extraction DMA buffer is too small for probing the output pin"},
{120, "Invalid ID of configuration item provided in TLV list"},
{121, "Invalid length of configuration item provided in TLV list"},
{122, "Invalid structure of configuration item provided"},
{140, "Initialization of DMA Gateway failed"},
{141, "Invalid ID of gateway provided"},
{142, "Setting state of DMA Gateway failed"},
{143, "DMA_CONTROL message targeting gateway not allocated yet"},
{150, "Attempt to configure SCLK while I2S port is running"},
{151, "Attempt to configure MCLK while I2S port is running"},
{152, "Attempt to stop SCLK that is not running"},
{153, "Attempt to stop MCLK that is not running"},
{160, "Reserved (ADSP_IPC_PIPELINE_NOT_INITIALIZED removed)"},
{161, "Reserved (ADSP_IPC_PIPELINE_NOT_EXIST removed)"},
{162, "Reserved (ADSP_IPC_PIPELINE_SAVE_FAILED removed)"},
{163, "Reserved (ADSP_IPC_PIPELINE_RESTORE_FAILED removed)"},
{165, "Reserved (ADSP_IPC_PIPELINE_ALREADY_EXISTS removed)"},
};
static int sof_ipc4_check_reply_status(struct snd_sof_dev *sdev, u32 status)
{
int i, ret;
status &= SOF_IPC4_REPLY_STATUS;
if (!status)
return 0;
for (i = 0; i < ARRAY_SIZE(ipc4_status); i++) {
if (ipc4_status[i].status == status) {
dev_err(sdev->dev, "FW reported error: %u - %s\n",
status, ipc4_status[i].msg);
goto to_errno;
}
}
if (i == ARRAY_SIZE(ipc4_status))
dev_err(sdev->dev, "FW reported error: %u - Unknown\n", status);
to_errno:
switch (status) {
case 8:
case 11:
case 105 ... 109:
case 114 ... 115:
case 160 ... 163:
case 165:
ret = -ENOENT;
break;
case 4:
case 150:
case 151:
ret = -EBUSY;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
#define DBG_IPC4_MSG_TYPE_ENTRY(type) [SOF_IPC4_##type] = #type
static const char * const ipc4_dbg_mod_msg_type[] = {
DBG_IPC4_MSG_TYPE_ENTRY(MOD_INIT_INSTANCE),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_CONFIG_GET),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_CONFIG_SET),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_LARGE_CONFIG_GET),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_LARGE_CONFIG_SET),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_BIND),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_UNBIND),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_SET_DX),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_SET_D0IX),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_ENTER_MODULE_RESTORE),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_EXIT_MODULE_RESTORE),
DBG_IPC4_MSG_TYPE_ENTRY(MOD_DELETE_INSTANCE),
};
static const char * const ipc4_dbg_glb_msg_type[] = {
DBG_IPC4_MSG_TYPE_ENTRY(GLB_BOOT_CONFIG),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_ROM_CONTROL),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_IPCGATEWAY_CMD),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_PERF_MEASUREMENTS_CMD),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_CHAIN_DMA),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_MULTIPLE_MODULES),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_UNLOAD_MULTIPLE_MODULES),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_CREATE_PIPELINE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_DELETE_PIPELINE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_SET_PIPELINE_STATE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_GET_PIPELINE_STATE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_GET_PIPELINE_CONTEXT_SIZE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_SAVE_PIPELINE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_RESTORE_PIPELINE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_LIBRARY),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_INTERNAL_MESSAGE),
DBG_IPC4_MSG_TYPE_ENTRY(GLB_NOTIFICATION),
};
#define DBG_IPC4_NOTIFICATION_TYPE_ENTRY(type) [SOF_IPC4_NOTIFY_##type] = #type
static const char * const ipc4_dbg_notification_type[] = {
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(PHRASE_DETECTED),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(RESOURCE_EVENT),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(LOG_BUFFER_STATUS),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(TIMESTAMP_CAPTURED),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(FW_READY),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(FW_AUD_CLASS_RESULT),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(EXCEPTION_CAUGHT),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(MODULE_NOTIFICATION),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(PROBE_DATA_AVAILABLE),
DBG_IPC4_NOTIFICATION_TYPE_ENTRY(ASYNC_MSG_SRVC_MESSAGE),
};
static void sof_ipc4_log_header(struct device *dev, u8 *text, struct sof_ipc4_msg *msg,
bool data_size_valid)
{
u32 val, type;
const u8 *str2 = NULL;
const u8 *str = NULL;
val = msg->primary & SOF_IPC4_MSG_TARGET_MASK;
type = SOF_IPC4_MSG_TYPE_GET(msg->primary);
if (val == SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG)) {
/* Module message */
if (type < SOF_IPC4_MOD_TYPE_LAST)
str = ipc4_dbg_mod_msg_type[type];
if (!str)
str = "Unknown Module message type";
} else {
/* Global FW message */
if (type < SOF_IPC4_GLB_TYPE_LAST)
str = ipc4_dbg_glb_msg_type[type];
if (!str)
str = "Unknown Global message type";
if (type == SOF_IPC4_GLB_NOTIFICATION) {
/* Notification message */
u32 notif = SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary);
/* Do not print log buffer notification if not desired */
if (notif == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS &&
!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
return;
if (notif < SOF_IPC4_NOTIFY_TYPE_LAST)
str2 = ipc4_dbg_notification_type[notif];
if (!str2)
str2 = "Unknown Global notification";
}
}
if (str2) {
if (data_size_valid && msg->data_size)
dev_dbg(dev, "%s: %#x|%#x: %s|%s [data size: %zu]\n",
text, msg->primary, msg->extension, str, str2,
msg->data_size);
else
dev_dbg(dev, "%s: %#x|%#x: %s|%s\n", text, msg->primary,
msg->extension, str, str2);
} else {
if (data_size_valid && msg->data_size)
dev_dbg(dev, "%s: %#x|%#x: %s [data size: %zu]\n",
text, msg->primary, msg->extension, str,
msg->data_size);
else
dev_dbg(dev, "%s: %#x|%#x: %s\n", text, msg->primary,
msg->extension, str);
}
}
#else /* CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC */
static void sof_ipc4_log_header(struct device *dev, u8 *text, struct sof_ipc4_msg *msg,
bool data_size_valid)
{
/* Do not print log buffer notification if not desired */
if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS) &&
!SOF_IPC4_MSG_IS_MODULE_MSG(msg->primary) &&
SOF_IPC4_MSG_TYPE_GET(msg->primary) == SOF_IPC4_GLB_NOTIFICATION &&
SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary) == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS)
return;
if (data_size_valid && msg->data_size)
dev_dbg(dev, "%s: %#x|%#x [data size: %zu]\n", text,
msg->primary, msg->extension, msg->data_size);
else
dev_dbg(dev, "%s: %#x|%#x\n", text, msg->primary, msg->extension);
}
#endif
static void sof_ipc4_dump_payload(struct snd_sof_dev *sdev,
void *ipc_data, size_t size)
{
print_hex_dump_debug("Message payload: ", DUMP_PREFIX_OFFSET,
16, 4, ipc_data, size, false);
}
static int sof_ipc4_get_reply(struct snd_sof_dev *sdev)
{
struct snd_sof_ipc_msg *msg = sdev->msg;
struct sof_ipc4_msg *ipc4_reply;
int ret;
/* get the generic reply */
ipc4_reply = msg->reply_data;
sof_ipc4_log_header(sdev->dev, "ipc tx reply", ipc4_reply, false);
ret = sof_ipc4_check_reply_status(sdev, ipc4_reply->primary);
if (ret)
return ret;
/* No other information is expected for non large config get replies */
if (!msg->reply_size || !SOF_IPC4_MSG_IS_MODULE_MSG(ipc4_reply->primary) ||
(SOF_IPC4_MSG_TYPE_GET(ipc4_reply->primary) != SOF_IPC4_MOD_LARGE_CONFIG_GET))
return 0;
/* Read the requested payload */
snd_sof_dsp_mailbox_read(sdev, sdev->dsp_box.offset, ipc4_reply->data_ptr,
msg->reply_size);
return 0;
}
/* wait for IPC message reply */
static int ipc4_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data)
{
struct snd_sof_ipc_msg *msg = &ipc->msg;
struct sof_ipc4_msg *ipc4_msg = msg->msg_data;
struct snd_sof_dev *sdev = ipc->sdev;
int ret;
/* wait for DSP IPC completion */
ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
msecs_to_jiffies(sdev->ipc_timeout));
if (ret == 0) {
dev_err(sdev->dev, "ipc timed out for %#x|%#x\n",
ipc4_msg->primary, ipc4_msg->extension);
snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout");
return -ETIMEDOUT;
}
if (msg->reply_error) {
dev_err(sdev->dev, "ipc error for msg %#x|%#x\n",
ipc4_msg->primary, ipc4_msg->extension);
ret = msg->reply_error;
} else {
if (reply_data) {
struct sof_ipc4_msg *ipc4_reply = msg->reply_data;
struct sof_ipc4_msg *ipc4_reply_data = reply_data;
/* Copy the header */
ipc4_reply_data->header_u64 = ipc4_reply->header_u64;
if (msg->reply_size && ipc4_reply_data->data_ptr) {
/* copy the payload returned from DSP */
memcpy(ipc4_reply_data->data_ptr, ipc4_reply->data_ptr,
msg->reply_size);
ipc4_reply_data->data_size = msg->reply_size;
}
}
ret = 0;
sof_ipc4_log_header(sdev->dev, "ipc tx done ", ipc4_msg, true);
}
/* re-enable dumps after successful IPC tx */
if (sdev->ipc_dump_printed) {
sdev->dbg_dump_printed = false;
sdev->ipc_dump_printed = false;
}
return ret;
}
static int ipc4_tx_msg_unlocked(struct snd_sof_ipc *ipc,
void *msg_data, size_t msg_bytes,
void *reply_data, size_t reply_bytes)
{
struct sof_ipc4_msg *ipc4_msg = msg_data;
struct snd_sof_dev *sdev = ipc->sdev;
int ret;
if (msg_bytes > ipc->max_payload_size || reply_bytes > ipc->max_payload_size)
return -EINVAL;
sof_ipc4_log_header(sdev->dev, "ipc tx ", msg_data, true);
ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes);
if (ret) {
dev_err_ratelimited(sdev->dev,
"%s: ipc message send for %#x|%#x failed: %d\n",
__func__, ipc4_msg->primary, ipc4_msg->extension, ret);
return ret;
}
/* now wait for completion */
return ipc4_wait_tx_done(ipc, reply_data);
}
static int sof_ipc4_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
void *reply_data, size_t reply_bytes, bool no_pm)
{
struct snd_sof_ipc *ipc = sdev->ipc;
int ret;
if (!msg_data)
return -EINVAL;
if (!no_pm) {
const struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D0,
};
/* ensure the DSP is in D0i0 before sending a new IPC */
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
if (ret < 0)
return ret;
}
/* Serialise IPC TX */
mutex_lock(&ipc->tx_mutex);
ret = ipc4_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes);
if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
struct sof_ipc4_msg *msg = NULL;
/* payload is indicated by non zero msg/reply_bytes */
if (msg_bytes)
msg = msg_data;
else if (reply_bytes)
msg = reply_data;
if (msg)
sof_ipc4_dump_payload(sdev, msg->data_ptr, msg->data_size);
}
mutex_unlock(&ipc->tx_mutex);
return ret;
}
static int sof_ipc4_set_get_data(struct snd_sof_dev *sdev, void *data,
size_t payload_bytes, bool set)
{
const struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D0,
};
size_t payload_limit = sdev->ipc->max_payload_size;
struct sof_ipc4_msg *ipc4_msg = data;
struct sof_ipc4_msg tx = {{ 0 }};
struct sof_ipc4_msg rx = {{ 0 }};
size_t remaining = payload_bytes;
size_t offset = 0;
size_t chunk_size;
int ret;
if (!data)
return -EINVAL;
if ((ipc4_msg->primary & SOF_IPC4_MSG_TARGET_MASK) !=
SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG))
return -EINVAL;
ipc4_msg->primary &= ~SOF_IPC4_MSG_TYPE_MASK;
tx.primary = ipc4_msg->primary;
tx.extension = ipc4_msg->extension;
if (set)
tx.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_SET);
else
tx.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_GET);
tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_SIZE_MASK;
tx.extension |= SOF_IPC4_MOD_EXT_MSG_SIZE(payload_bytes);
tx.extension |= SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(1);
/* ensure the DSP is in D0i0 before sending IPC */
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
if (ret < 0)
return ret;
/* Serialise IPC TX */
mutex_lock(&sdev->ipc->tx_mutex);
do {
size_t tx_size, rx_size;
if (remaining > payload_limit) {
chunk_size = payload_limit;
} else {
chunk_size = remaining;
if (set)
tx.extension |= SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(1);
}
if (offset) {
tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK;
tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_SIZE_MASK;
tx.extension |= SOF_IPC4_MOD_EXT_MSG_SIZE(offset);
}
if (set) {
tx.data_size = chunk_size;
tx.data_ptr = ipc4_msg->data_ptr + offset;
tx_size = chunk_size;
rx_size = 0;
} else {
rx.primary = 0;
rx.extension = 0;
rx.data_size = chunk_size;
rx.data_ptr = ipc4_msg->data_ptr + offset;
tx_size = 0;
rx_size = chunk_size;
}
/* Send the message for the current chunk */
ret = ipc4_tx_msg_unlocked(sdev->ipc, &tx, tx_size, &rx, rx_size);
if (ret < 0) {
dev_err(sdev->dev,
"%s: large config %s failed at offset %zu: %d\n",
__func__, set ? "set" : "get", offset, ret);
goto out;
}
if (!set && rx.extension & SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK) {
/* Verify the firmware reported total payload size */
rx_size = rx.extension & SOF_IPC4_MOD_EXT_MSG_SIZE_MASK;
if (rx_size > payload_bytes) {
dev_err(sdev->dev,
"%s: Receive buffer (%zu) is too small for %zu\n",
__func__, payload_bytes, rx_size);
ret = -ENOMEM;
goto out;
}
if (rx_size < chunk_size) {
chunk_size = rx_size;
remaining = rx_size;
} else if (rx_size < payload_bytes) {
remaining = rx_size;
}
}
offset += chunk_size;
remaining -= chunk_size;
} while (remaining);
/* Adjust the received data size if needed */
if (!set && payload_bytes != offset)
ipc4_msg->data_size = offset;
if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD))
sof_ipc4_dump_payload(sdev, ipc4_msg->data_ptr, ipc4_msg->data_size);
out:
mutex_unlock(&sdev->ipc->tx_mutex);
return ret;
}
static int sof_ipc4_init_msg_memory(struct snd_sof_dev *sdev)
{
struct sof_ipc4_msg *ipc4_msg;
struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
/* TODO: get max_payload_size from firmware */
sdev->ipc->max_payload_size = SOF_IPC4_MSG_MAX_SIZE;
/* Allocate memory for the ipc4 container and the maximum payload */
msg->reply_data = devm_kzalloc(sdev->dev, sdev->ipc->max_payload_size +
sizeof(struct sof_ipc4_msg), GFP_KERNEL);
if (!msg->reply_data)
return -ENOMEM;
ipc4_msg = msg->reply_data;
ipc4_msg->data_ptr = msg->reply_data + sizeof(struct sof_ipc4_msg);
return 0;
}
static int ipc4_fw_ready(struct snd_sof_dev *sdev, struct sof_ipc4_msg *ipc4_msg)
{
int inbox_offset, inbox_size, outbox_offset, outbox_size;
/* no need to re-check version/ABI for subsequent boots */
if (!sdev->first_boot)
return 0;
/* Set up the windows for IPC communication */
inbox_offset = snd_sof_dsp_get_mailbox_offset(sdev);
if (inbox_offset < 0) {
dev_err(sdev->dev, "%s: No mailbox offset\n", __func__);
return inbox_offset;
}
inbox_size = SOF_IPC4_MSG_MAX_SIZE;
outbox_offset = snd_sof_dsp_get_window_offset(sdev, SOF_IPC4_OUTBOX_WINDOW_IDX);
outbox_size = SOF_IPC4_MSG_MAX_SIZE;
sdev->fw_info_box.offset = snd_sof_dsp_get_window_offset(sdev, SOF_IPC4_INBOX_WINDOW_IDX);
sdev->fw_info_box.size = sizeof(struct sof_ipc4_fw_registers);
sdev->dsp_box.offset = inbox_offset;
sdev->dsp_box.size = inbox_size;
sdev->host_box.offset = outbox_offset;
sdev->host_box.size = outbox_size;
sdev->debug_box.offset = snd_sof_dsp_get_window_offset(sdev,
SOF_IPC4_DEBUG_WINDOW_IDX);
dev_dbg(sdev->dev, "mailbox upstream 0x%x - size 0x%x\n",
inbox_offset, inbox_size);
dev_dbg(sdev->dev, "mailbox downstream 0x%x - size 0x%x\n",
outbox_offset, outbox_size);
dev_dbg(sdev->dev, "debug box 0x%x\n", sdev->debug_box.offset);
return sof_ipc4_init_msg_memory(sdev);
}
static void sof_ipc4_rx_msg(struct snd_sof_dev *sdev)
{
struct sof_ipc4_msg *ipc4_msg = sdev->ipc->msg.rx_data;
size_t data_size = 0;
int err;
if (!ipc4_msg || !SOF_IPC4_MSG_IS_NOTIFICATION(ipc4_msg->primary))
return;
ipc4_msg->data_ptr = NULL;
ipc4_msg->data_size = 0;
sof_ipc4_log_header(sdev->dev, "ipc rx ", ipc4_msg, false);
switch (SOF_IPC4_NOTIFICATION_TYPE_GET(ipc4_msg->primary)) {
case SOF_IPC4_NOTIFY_FW_READY:
/* check for FW boot completion */
if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
err = ipc4_fw_ready(sdev, ipc4_msg);
if (err < 0)
sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED);
else
sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK);
/* wake up firmware loader */
wake_up(&sdev->boot_wait);
}
break;
case SOF_IPC4_NOTIFY_RESOURCE_EVENT:
data_size = sizeof(struct sof_ipc4_notify_resource_data);
break;
case SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS:
sof_ipc4_mtrace_update_pos(sdev, SOF_IPC4_LOG_CORE_GET(ipc4_msg->primary));
break;
default:
dev_dbg(sdev->dev, "Unhandled DSP message: %#x|%#x\n",
ipc4_msg->primary, ipc4_msg->extension);
break;
}
if (data_size) {
ipc4_msg->data_ptr = kmalloc(data_size, GFP_KERNEL);
if (!ipc4_msg->data_ptr)
return;
ipc4_msg->data_size = data_size;
snd_sof_ipc_msg_data(sdev, NULL, ipc4_msg->data_ptr, ipc4_msg->data_size);
}
sof_ipc4_log_header(sdev->dev, "ipc rx done ", ipc4_msg, true);
if (data_size) {
kfree(ipc4_msg->data_ptr);
ipc4_msg->data_ptr = NULL;
ipc4_msg->data_size = 0;
}
}
static int sof_ipc4_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
{
struct sof_ipc4_dx_state_info dx_state;
struct sof_ipc4_msg msg;
dx_state.core_mask = BIT(core_idx);
if (on)
dx_state.dx_mask = BIT(core_idx);
else
dx_state.dx_mask = 0;
msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension = 0;
msg.data_ptr = &dx_state;
msg.data_size = sizeof(dx_state);
return sof_ipc4_tx_msg(sdev, &msg, msg.data_size, NULL, 0, false);
}
/*
* The context save callback is used to send a message to the firmware notifying
* it that the primary core is going to be turned off, which is used as an
* indication to prepare for a full power down, thus preparing for IMR boot
* (when supported)
*
* Note: in IPC4 there is no message used to restore context, thus no context
* restore callback is implemented
*/
static int sof_ipc4_ctx_save(struct snd_sof_dev *sdev)
{
return sof_ipc4_set_core_state(sdev, SOF_DSP_PRIMARY_CORE, false);
}
static int sof_ipc4_set_pm_gate(struct snd_sof_dev *sdev, u32 flags)
{
struct sof_ipc4_msg msg = {{0}};
msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_D0IX);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension = flags;
return sof_ipc4_tx_msg(sdev, &msg, 0, NULL, 0, true);
}
static const struct sof_ipc_pm_ops ipc4_pm_ops = {
.ctx_save = sof_ipc4_ctx_save,
.set_core_state = sof_ipc4_set_core_state,
.set_pm_gate = sof_ipc4_set_pm_gate,
};
static int sof_ipc4_init(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
mutex_init(&ipc4_data->pipeline_state_mutex);
xa_init_flags(&ipc4_data->fw_lib_xa, XA_FLAGS_ALLOC);
return 0;
}
static void sof_ipc4_exit(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_fw_library *fw_lib;
unsigned long lib_id;
xa_for_each(&ipc4_data->fw_lib_xa, lib_id, fw_lib) {
/*
* The basefw (ID == 0) is handled by generic code, it is not
* loaded by IPC4 code.
*/
if (lib_id != 0)
release_firmware(fw_lib->sof_fw.fw);
fw_lib->sof_fw.fw = NULL;
}
xa_destroy(&ipc4_data->fw_lib_xa);
}
static int sof_ipc4_post_boot(struct snd_sof_dev *sdev)
{
if (sdev->first_boot)
return sof_ipc4_query_fw_configuration(sdev);
return sof_ipc4_reload_fw_libraries(sdev);
}
const struct sof_ipc_ops ipc4_ops = {
.init = sof_ipc4_init,
.exit = sof_ipc4_exit,
.post_fw_boot = sof_ipc4_post_boot,
.tx_msg = sof_ipc4_tx_msg,
.rx_msg = sof_ipc4_rx_msg,
.set_get_data = sof_ipc4_set_get_data,
.get_reply = sof_ipc4_get_reply,
.pm = &ipc4_pm_ops,
.fw_loader = &ipc4_loader_ops,
.tplg = &ipc4_tplg_ops,
.pcm = &ipc4_pcm_ops,
.fw_tracing = &ipc4_mtrace_ops,
};
| linux-master | sound/soc/sof/ipc4.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
// Authors: Ranjani Sridharan <[email protected]>
// Peter Ujfalusi <[email protected]>
//
#include <linux/debugfs.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <sound/sof/ipc4/header.h>
#include "ops.h"
#include "sof-client.h"
#include "sof-priv.h"
#include "ipc3-priv.h"
#include "ipc4-priv.h"
/**
* struct sof_ipc_event_entry - IPC client event description
* @ipc_msg_type: IPC msg type of the event the client is interested
* @cdev: sof_client_dev of the requesting client
* @callback: Callback function of the client
* @list: item in SOF core client event list
*/
struct sof_ipc_event_entry {
u32 ipc_msg_type;
struct sof_client_dev *cdev;
sof_client_event_callback callback;
struct list_head list;
};
/**
* struct sof_state_event_entry - DSP panic event subscription entry
* @cdev: sof_client_dev of the requesting client
* @callback: Callback function of the client
* @list: item in SOF core client event list
*/
struct sof_state_event_entry {
struct sof_client_dev *cdev;
sof_client_fw_state_callback callback;
struct list_head list;
};
static void sof_client_auxdev_release(struct device *dev)
{
struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
kfree(cdev->auxdev.dev.platform_data);
kfree(cdev);
}
static int sof_client_dev_add_data(struct sof_client_dev *cdev, const void *data,
size_t size)
{
void *d = NULL;
if (data) {
d = kmemdup(data, size, GFP_KERNEL);
if (!d)
return -ENOMEM;
}
cdev->auxdev.dev.platform_data = d;
return 0;
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST)
static int sof_register_ipc_flood_test(struct snd_sof_dev *sdev)
{
int ret = 0;
int i;
if (sdev->pdata->ipc_type != SOF_IPC)
return 0;
for (i = 0; i < CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM; i++) {
ret = sof_client_dev_register(sdev, "ipc_flood", i, NULL, 0);
if (ret < 0)
break;
}
if (ret) {
for (; i >= 0; --i)
sof_client_dev_unregister(sdev, "ipc_flood", i);
}
return ret;
}
static void sof_unregister_ipc_flood_test(struct snd_sof_dev *sdev)
{
int i;
for (i = 0; i < CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM; i++)
sof_client_dev_unregister(sdev, "ipc_flood", i);
}
#else
static inline int sof_register_ipc_flood_test(struct snd_sof_dev *sdev)
{
return 0;
}
static inline void sof_unregister_ipc_flood_test(struct snd_sof_dev *sdev) {}
#endif /* CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST */
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR)
static int sof_register_ipc_msg_injector(struct snd_sof_dev *sdev)
{
return sof_client_dev_register(sdev, "msg_injector", 0, NULL, 0);
}
static void sof_unregister_ipc_msg_injector(struct snd_sof_dev *sdev)
{
sof_client_dev_unregister(sdev, "msg_injector", 0);
}
#else
static inline int sof_register_ipc_msg_injector(struct snd_sof_dev *sdev)
{
return 0;
}
static inline void sof_unregister_ipc_msg_injector(struct snd_sof_dev *sdev) {}
#endif /* CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR */
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_KERNEL_INJECTOR)
static int sof_register_ipc_kernel_injector(struct snd_sof_dev *sdev)
{
/* Only IPC3 supported right now */
if (sdev->pdata->ipc_type != SOF_IPC)
return 0;
return sof_client_dev_register(sdev, "kernel_injector", 0, NULL, 0);
}
static void sof_unregister_ipc_kernel_injector(struct snd_sof_dev *sdev)
{
sof_client_dev_unregister(sdev, "kernel_injector", 0);
}
#else
static inline int sof_register_ipc_kernel_injector(struct snd_sof_dev *sdev)
{
return 0;
}
static inline void sof_unregister_ipc_kernel_injector(struct snd_sof_dev *sdev) {}
#endif /* CONFIG_SND_SOC_SOF_DEBUG_IPC_KERNEL_INJECTOR */
int sof_register_clients(struct snd_sof_dev *sdev)
{
int ret;
if (sdev->dspless_mode_selected)
return 0;
/* Register platform independent client devices */
ret = sof_register_ipc_flood_test(sdev);
if (ret) {
dev_err(sdev->dev, "IPC flood test client registration failed\n");
return ret;
}
ret = sof_register_ipc_msg_injector(sdev);
if (ret) {
dev_err(sdev->dev, "IPC message injector client registration failed\n");
goto err_msg_injector;
}
ret = sof_register_ipc_kernel_injector(sdev);
if (ret) {
dev_err(sdev->dev, "IPC kernel injector client registration failed\n");
goto err_kernel_injector;
}
/* Platform depndent client device registration */
if (sof_ops(sdev) && sof_ops(sdev)->register_ipc_clients)
ret = sof_ops(sdev)->register_ipc_clients(sdev);
if (!ret)
return 0;
sof_unregister_ipc_kernel_injector(sdev);
err_kernel_injector:
sof_unregister_ipc_msg_injector(sdev);
err_msg_injector:
sof_unregister_ipc_flood_test(sdev);
return ret;
}
void sof_unregister_clients(struct snd_sof_dev *sdev)
{
if (sof_ops(sdev) && sof_ops(sdev)->unregister_ipc_clients)
sof_ops(sdev)->unregister_ipc_clients(sdev);
sof_unregister_ipc_kernel_injector(sdev);
sof_unregister_ipc_msg_injector(sdev);
sof_unregister_ipc_flood_test(sdev);
}
int sof_client_dev_register(struct snd_sof_dev *sdev, const char *name, u32 id,
const void *data, size_t size)
{
struct auxiliary_device *auxdev;
struct sof_client_dev *cdev;
int ret;
cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
if (!cdev)
return -ENOMEM;
cdev->sdev = sdev;
auxdev = &cdev->auxdev;
auxdev->name = name;
auxdev->dev.parent = sdev->dev;
auxdev->dev.release = sof_client_auxdev_release;
auxdev->id = id;
ret = sof_client_dev_add_data(cdev, data, size);
if (ret < 0)
goto err_dev_add_data;
ret = auxiliary_device_init(auxdev);
if (ret < 0) {
dev_err(sdev->dev, "failed to initialize client dev %s.%d\n", name, id);
goto err_dev_init;
}
ret = auxiliary_device_add(&cdev->auxdev);
if (ret < 0) {
dev_err(sdev->dev, "failed to add client dev %s.%d\n", name, id);
/*
* sof_client_auxdev_release() will be invoked to free up memory
* allocations through put_device()
*/
auxiliary_device_uninit(&cdev->auxdev);
return ret;
}
/* add to list of SOF client devices */
mutex_lock(&sdev->ipc_client_mutex);
list_add(&cdev->list, &sdev->ipc_client_list);
mutex_unlock(&sdev->ipc_client_mutex);
return 0;
err_dev_init:
kfree(cdev->auxdev.dev.platform_data);
err_dev_add_data:
kfree(cdev);
return ret;
}
EXPORT_SYMBOL_NS_GPL(sof_client_dev_register, SND_SOC_SOF_CLIENT);
void sof_client_dev_unregister(struct snd_sof_dev *sdev, const char *name, u32 id)
{
struct sof_client_dev *cdev;
mutex_lock(&sdev->ipc_client_mutex);
/*
* sof_client_auxdev_release() will be invoked to free up memory
* allocations through put_device()
*/
list_for_each_entry(cdev, &sdev->ipc_client_list, list) {
if (!strcmp(cdev->auxdev.name, name) && cdev->auxdev.id == id) {
list_del(&cdev->list);
auxiliary_device_delete(&cdev->auxdev);
auxiliary_device_uninit(&cdev->auxdev);
break;
}
}
mutex_unlock(&sdev->ipc_client_mutex);
}
EXPORT_SYMBOL_NS_GPL(sof_client_dev_unregister, SND_SOC_SOF_CLIENT);
int sof_client_ipc_tx_message(struct sof_client_dev *cdev, void *ipc_msg,
void *reply_data, size_t reply_bytes)
{
if (cdev->sdev->pdata->ipc_type == SOF_IPC) {
struct sof_ipc_cmd_hdr *hdr = ipc_msg;
return sof_ipc_tx_message(cdev->sdev->ipc, ipc_msg, hdr->size,
reply_data, reply_bytes);
} else if (cdev->sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
struct sof_ipc4_msg *msg = ipc_msg;
return sof_ipc_tx_message(cdev->sdev->ipc, ipc_msg, msg->data_size,
reply_data, reply_bytes);
}
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(sof_client_ipc_tx_message, SND_SOC_SOF_CLIENT);
int sof_client_ipc_rx_message(struct sof_client_dev *cdev, void *ipc_msg, void *msg_buf)
{
if (cdev->sdev->pdata->ipc_type == SOF_IPC) {
struct sof_ipc_cmd_hdr *hdr = ipc_msg;
if (hdr->size < sizeof(hdr)) {
dev_err(cdev->sdev->dev, "The received message size is invalid\n");
return -EINVAL;
}
sof_ipc3_do_rx_work(cdev->sdev, ipc_msg, msg_buf);
return 0;
}
return -EOPNOTSUPP;
}
EXPORT_SYMBOL_NS_GPL(sof_client_ipc_rx_message, SND_SOC_SOF_CLIENT);
int sof_client_ipc_set_get_data(struct sof_client_dev *cdev, void *ipc_msg,
bool set)
{
if (cdev->sdev->pdata->ipc_type == SOF_IPC) {
struct sof_ipc_cmd_hdr *hdr = ipc_msg;
return sof_ipc_set_get_data(cdev->sdev->ipc, ipc_msg, hdr->size,
set);
} else if (cdev->sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
struct sof_ipc4_msg *msg = ipc_msg;
return sof_ipc_set_get_data(cdev->sdev->ipc, ipc_msg,
msg->data_size, set);
}
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(sof_client_ipc_set_get_data, SND_SOC_SOF_CLIENT);
#ifdef CONFIG_SND_SOC_SOF_INTEL_IPC4
struct sof_ipc4_fw_module *sof_client_ipc4_find_module(struct sof_client_dev *c, const guid_t *uuid)
{
struct snd_sof_dev *sdev = c->sdev;
if (sdev->pdata->ipc_type == SOF_INTEL_IPC4)
return sof_ipc4_find_module_by_uuid(sdev, uuid);
dev_err(sdev->dev, "Only supported with IPC4\n");
return NULL;
}
EXPORT_SYMBOL_NS_GPL(sof_client_ipc4_find_module, SND_SOC_SOF_CLIENT);
#endif
int sof_suspend_clients(struct snd_sof_dev *sdev, pm_message_t state)
{
struct auxiliary_driver *adrv;
struct sof_client_dev *cdev;
mutex_lock(&sdev->ipc_client_mutex);
list_for_each_entry(cdev, &sdev->ipc_client_list, list) {
/* Skip devices without loaded driver */
if (!cdev->auxdev.dev.driver)
continue;
adrv = to_auxiliary_drv(cdev->auxdev.dev.driver);
if (adrv->suspend)
adrv->suspend(&cdev->auxdev, state);
}
mutex_unlock(&sdev->ipc_client_mutex);
return 0;
}
EXPORT_SYMBOL_NS_GPL(sof_suspend_clients, SND_SOC_SOF_CLIENT);
int sof_resume_clients(struct snd_sof_dev *sdev)
{
struct auxiliary_driver *adrv;
struct sof_client_dev *cdev;
mutex_lock(&sdev->ipc_client_mutex);
list_for_each_entry(cdev, &sdev->ipc_client_list, list) {
/* Skip devices without loaded driver */
if (!cdev->auxdev.dev.driver)
continue;
adrv = to_auxiliary_drv(cdev->auxdev.dev.driver);
if (adrv->resume)
adrv->resume(&cdev->auxdev);
}
mutex_unlock(&sdev->ipc_client_mutex);
return 0;
}
EXPORT_SYMBOL_NS_GPL(sof_resume_clients, SND_SOC_SOF_CLIENT);
struct dentry *sof_client_get_debugfs_root(struct sof_client_dev *cdev)
{
return cdev->sdev->debugfs_root;
}
EXPORT_SYMBOL_NS_GPL(sof_client_get_debugfs_root, SND_SOC_SOF_CLIENT);
/* DMA buffer allocation in client drivers must use the core SOF device */
struct device *sof_client_get_dma_dev(struct sof_client_dev *cdev)
{
return cdev->sdev->dev;
}
EXPORT_SYMBOL_NS_GPL(sof_client_get_dma_dev, SND_SOC_SOF_CLIENT);
const struct sof_ipc_fw_version *sof_client_get_fw_version(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
return &sdev->fw_ready.version;
}
EXPORT_SYMBOL_NS_GPL(sof_client_get_fw_version, SND_SOC_SOF_CLIENT);
size_t sof_client_get_ipc_max_payload_size(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
return sdev->ipc->max_payload_size;
}
EXPORT_SYMBOL_NS_GPL(sof_client_get_ipc_max_payload_size, SND_SOC_SOF_CLIENT);
enum sof_ipc_type sof_client_get_ipc_type(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
return sdev->pdata->ipc_type;
}
EXPORT_SYMBOL_NS_GPL(sof_client_get_ipc_type, SND_SOC_SOF_CLIENT);
/* module refcount management of SOF core */
int sof_client_core_module_get(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
if (!try_module_get(sdev->dev->driver->owner))
return -ENODEV;
return 0;
}
EXPORT_SYMBOL_NS_GPL(sof_client_core_module_get, SND_SOC_SOF_CLIENT);
void sof_client_core_module_put(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
module_put(sdev->dev->driver->owner);
}
EXPORT_SYMBOL_NS_GPL(sof_client_core_module_put, SND_SOC_SOF_CLIENT);
/* IPC event handling */
void sof_client_ipc_rx_dispatcher(struct snd_sof_dev *sdev, void *msg_buf)
{
struct sof_ipc_event_entry *event;
u32 msg_type;
if (sdev->pdata->ipc_type == SOF_IPC) {
struct sof_ipc_cmd_hdr *hdr = msg_buf;
msg_type = hdr->cmd & SOF_GLB_TYPE_MASK;
} else if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
struct sof_ipc4_msg *msg = msg_buf;
msg_type = SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary);
} else {
dev_dbg_once(sdev->dev, "Not supported IPC version: %d\n",
sdev->pdata->ipc_type);
return;
}
mutex_lock(&sdev->client_event_handler_mutex);
list_for_each_entry(event, &sdev->ipc_rx_handler_list, list) {
if (event->ipc_msg_type == msg_type)
event->callback(event->cdev, msg_buf);
}
mutex_unlock(&sdev->client_event_handler_mutex);
}
int sof_client_register_ipc_rx_handler(struct sof_client_dev *cdev,
u32 ipc_msg_type,
sof_client_event_callback callback)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
struct sof_ipc_event_entry *event;
if (!callback)
return -EINVAL;
if (cdev->sdev->pdata->ipc_type == SOF_IPC) {
if (!(ipc_msg_type & SOF_GLB_TYPE_MASK))
return -EINVAL;
} else if (cdev->sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
if (!(ipc_msg_type & SOF_IPC4_NOTIFICATION_TYPE_MASK))
return -EINVAL;
} else {
dev_warn(sdev->dev, "%s: Not supported IPC version: %d\n",
__func__, sdev->pdata->ipc_type);
return -EINVAL;
}
event = kmalloc(sizeof(*event), GFP_KERNEL);
if (!event)
return -ENOMEM;
event->ipc_msg_type = ipc_msg_type;
event->cdev = cdev;
event->callback = callback;
/* add to list of SOF client devices */
mutex_lock(&sdev->client_event_handler_mutex);
list_add(&event->list, &sdev->ipc_rx_handler_list);
mutex_unlock(&sdev->client_event_handler_mutex);
return 0;
}
EXPORT_SYMBOL_NS_GPL(sof_client_register_ipc_rx_handler, SND_SOC_SOF_CLIENT);
void sof_client_unregister_ipc_rx_handler(struct sof_client_dev *cdev,
u32 ipc_msg_type)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
struct sof_ipc_event_entry *event;
mutex_lock(&sdev->client_event_handler_mutex);
list_for_each_entry(event, &sdev->ipc_rx_handler_list, list) {
if (event->cdev == cdev && event->ipc_msg_type == ipc_msg_type) {
list_del(&event->list);
kfree(event);
break;
}
}
mutex_unlock(&sdev->client_event_handler_mutex);
}
EXPORT_SYMBOL_NS_GPL(sof_client_unregister_ipc_rx_handler, SND_SOC_SOF_CLIENT);
/*DSP state notification and query */
void sof_client_fw_state_dispatcher(struct snd_sof_dev *sdev)
{
struct sof_state_event_entry *event;
mutex_lock(&sdev->client_event_handler_mutex);
list_for_each_entry(event, &sdev->fw_state_handler_list, list)
event->callback(event->cdev, sdev->fw_state);
mutex_unlock(&sdev->client_event_handler_mutex);
}
int sof_client_register_fw_state_handler(struct sof_client_dev *cdev,
sof_client_fw_state_callback callback)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
struct sof_state_event_entry *event;
if (!callback)
return -EINVAL;
event = kmalloc(sizeof(*event), GFP_KERNEL);
if (!event)
return -ENOMEM;
event->cdev = cdev;
event->callback = callback;
/* add to list of SOF client devices */
mutex_lock(&sdev->client_event_handler_mutex);
list_add(&event->list, &sdev->fw_state_handler_list);
mutex_unlock(&sdev->client_event_handler_mutex);
return 0;
}
EXPORT_SYMBOL_NS_GPL(sof_client_register_fw_state_handler, SND_SOC_SOF_CLIENT);
void sof_client_unregister_fw_state_handler(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
struct sof_state_event_entry *event;
mutex_lock(&sdev->client_event_handler_mutex);
list_for_each_entry(event, &sdev->fw_state_handler_list, list) {
if (event->cdev == cdev) {
list_del(&event->list);
kfree(event);
break;
}
}
mutex_unlock(&sdev->client_event_handler_mutex);
}
EXPORT_SYMBOL_NS_GPL(sof_client_unregister_fw_state_handler, SND_SOC_SOF_CLIENT);
enum sof_fw_state sof_client_get_fw_state(struct sof_client_dev *cdev)
{
struct snd_sof_dev *sdev = sof_client_dev_to_sof_dev(cdev);
return sdev->fw_state;
}
EXPORT_SYMBOL_NS_GPL(sof_client_get_fw_state, SND_SOC_SOF_CLIENT);
| linux-master | sound/soc/sof/sof-client.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2019-2022 Intel Corporation. All rights reserved.
//
// Author: Cezary Rojewski <[email protected]>
//
// Code moved to this file by:
// Jyri Sarha <[email protected]>
//
#include <linux/stddef.h>
#include <sound/soc.h>
#include <sound/sof/header.h>
#include "sof-client.h"
#include "sof-client-probes.h"
struct sof_probe_dma {
unsigned int stream_tag;
unsigned int dma_buffer_size;
} __packed;
struct sof_ipc_probe_dma_add_params {
struct sof_ipc_cmd_hdr hdr;
unsigned int num_elems;
struct sof_probe_dma dma[];
} __packed;
struct sof_ipc_probe_info_params {
struct sof_ipc_reply rhdr;
unsigned int num_elems;
union {
DECLARE_FLEX_ARRAY(struct sof_probe_dma, dma);
DECLARE_FLEX_ARRAY(struct sof_probe_point_desc, desc);
};
} __packed;
struct sof_ipc_probe_point_add_params {
struct sof_ipc_cmd_hdr hdr;
unsigned int num_elems;
struct sof_probe_point_desc desc[];
} __packed;
struct sof_ipc_probe_point_remove_params {
struct sof_ipc_cmd_hdr hdr;
unsigned int num_elems;
unsigned int buffer_id[];
} __packed;
/**
* ipc3_probes_init - initialize data probing
* @cdev: SOF client device
* @stream_tag: Extractor stream tag
* @buffer_size: DMA buffer size to set for extractor
*
* Host chooses whether extraction is supported or not by providing
* valid stream tag to DSP. Once specified, stream described by that
* tag will be tied to DSP for extraction for the entire lifetime of
* probe.
*
* Probing is initialized only once and each INIT request must be
* matched by DEINIT call.
*/
static int ipc3_probes_init(struct sof_client_dev *cdev, u32 stream_tag,
size_t buffer_size)
{
struct sof_ipc_probe_dma_add_params *msg;
size_t size = struct_size(msg, dma, 1);
int ret;
msg = kmalloc(size, GFP_KERNEL);
if (!msg)
return -ENOMEM;
msg->hdr.size = size;
msg->hdr.cmd = SOF_IPC_GLB_PROBE | SOF_IPC_PROBE_INIT;
msg->num_elems = 1;
msg->dma[0].stream_tag = stream_tag;
msg->dma[0].dma_buffer_size = buffer_size;
ret = sof_client_ipc_tx_message_no_reply(cdev, msg);
kfree(msg);
return ret;
}
/**
* ipc3_probes_deinit - cleanup after data probing
* @cdev: SOF client device
*
* Host sends DEINIT request to free previously initialized probe
* on DSP side once it is no longer needed. DEINIT only when there
* are no probes connected and with all injectors detached.
*/
static int ipc3_probes_deinit(struct sof_client_dev *cdev)
{
struct sof_ipc_cmd_hdr msg;
msg.size = sizeof(msg);
msg.cmd = SOF_IPC_GLB_PROBE | SOF_IPC_PROBE_DEINIT;
return sof_client_ipc_tx_message_no_reply(cdev, &msg);
}
static int ipc3_probes_info(struct sof_client_dev *cdev, unsigned int cmd,
void **params, size_t *num_params)
{
size_t max_msg_size = sof_client_get_ipc_max_payload_size(cdev);
struct sof_ipc_probe_info_params msg = {{{0}}};
struct sof_ipc_probe_info_params *reply;
size_t bytes;
int ret;
*params = NULL;
*num_params = 0;
reply = kzalloc(max_msg_size, GFP_KERNEL);
if (!reply)
return -ENOMEM;
msg.rhdr.hdr.size = sizeof(msg);
msg.rhdr.hdr.cmd = SOF_IPC_GLB_PROBE | cmd;
ret = sof_client_ipc_tx_message(cdev, &msg, reply, max_msg_size);
if (ret < 0 || reply->rhdr.error < 0)
goto exit;
if (!reply->num_elems)
goto exit;
if (cmd == SOF_IPC_PROBE_DMA_INFO)
bytes = sizeof(reply->dma[0]);
else
bytes = sizeof(reply->desc[0]);
bytes *= reply->num_elems;
*params = kmemdup(&reply->dma[0], bytes, GFP_KERNEL);
if (!*params) {
ret = -ENOMEM;
goto exit;
}
*num_params = reply->num_elems;
exit:
kfree(reply);
return ret;
}
/**
* ipc3_probes_points_info - retrieve list of active probe points
* @cdev: SOF client device
* @desc: Returned list of active probes
* @num_desc: Returned count of active probes
*
* Host sends PROBE_POINT_INFO request to obtain list of active probe
* points, valid for disconnection when given probe is no longer
* required.
*/
static int ipc3_probes_points_info(struct sof_client_dev *cdev,
struct sof_probe_point_desc **desc,
size_t *num_desc)
{
return ipc3_probes_info(cdev, SOF_IPC_PROBE_POINT_INFO,
(void **)desc, num_desc);
}
/**
* ipc3_probes_points_add - connect specified probes
* @cdev: SOF client device
* @desc: List of probe points to connect
* @num_desc: Number of elements in @desc
*
* Dynamically connects to provided set of endpoints. Immediately
* after connection is established, host must be prepared to
* transfer data from or to target stream given the probing purpose.
*
* Each probe point should be removed using PROBE_POINT_REMOVE
* request when no longer needed.
*/
static int ipc3_probes_points_add(struct sof_client_dev *cdev,
struct sof_probe_point_desc *desc,
size_t num_desc)
{
struct sof_ipc_probe_point_add_params *msg;
size_t size = struct_size(msg, desc, num_desc);
int ret;
msg = kmalloc(size, GFP_KERNEL);
if (!msg)
return -ENOMEM;
msg->hdr.size = size;
msg->num_elems = num_desc;
msg->hdr.cmd = SOF_IPC_GLB_PROBE | SOF_IPC_PROBE_POINT_ADD;
memcpy(&msg->desc[0], desc, size - sizeof(*msg));
ret = sof_client_ipc_tx_message_no_reply(cdev, msg);
kfree(msg);
return ret;
}
/**
* ipc3_probes_points_remove - disconnect specified probes
* @cdev: SOF client device
* @buffer_id: List of probe points to disconnect
* @num_buffer_id: Number of elements in @desc
*
* Removes previously connected probes from list of active probe
* points and frees all resources on DSP side.
*/
static int ipc3_probes_points_remove(struct sof_client_dev *cdev,
unsigned int *buffer_id,
size_t num_buffer_id)
{
struct sof_ipc_probe_point_remove_params *msg;
size_t size = struct_size(msg, buffer_id, num_buffer_id);
int ret;
msg = kmalloc(size, GFP_KERNEL);
if (!msg)
return -ENOMEM;
msg->hdr.size = size;
msg->num_elems = num_buffer_id;
msg->hdr.cmd = SOF_IPC_GLB_PROBE | SOF_IPC_PROBE_POINT_REMOVE;
memcpy(&msg->buffer_id[0], buffer_id, size - sizeof(*msg));
ret = sof_client_ipc_tx_message_no_reply(cdev, msg);
kfree(msg);
return ret;
}
const struct sof_probes_ipc_ops ipc3_probe_ops = {
.init = ipc3_probes_init,
.deinit = ipc3_probes_deinit,
.points_info = ipc3_probes_points_info,
.points_add = ipc3_probes_points_add,
.points_remove = ipc3_probes_points_remove,
};
| linux-master | sound/soc/sof/sof-client-probes-ipc3.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/firmware.h>
#include <linux/dmi.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_data/x86/soc.h>
#include <linux/pm_runtime.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "ops.h"
#include "sof-pci-dev.h"
static char *fw_path;
module_param(fw_path, charp, 0444);
MODULE_PARM_DESC(fw_path, "alternate path for SOF firmware.");
static char *fw_filename;
module_param(fw_filename, charp, 0444);
MODULE_PARM_DESC(fw_filename, "alternate filename for SOF firmware.");
static char *lib_path;
module_param(lib_path, charp, 0444);
MODULE_PARM_DESC(lib_path, "alternate path for SOF firmware libraries.");
static char *tplg_path;
module_param(tplg_path, charp, 0444);
MODULE_PARM_DESC(tplg_path, "alternate path for SOF topology.");
static char *tplg_filename;
module_param(tplg_filename, charp, 0444);
MODULE_PARM_DESC(tplg_filename, "alternate filename for SOF topology.");
static int sof_pci_debug;
module_param_named(sof_pci_debug, sof_pci_debug, int, 0444);
MODULE_PARM_DESC(sof_pci_debug, "SOF PCI debug options (0x0 all off)");
static int sof_pci_ipc_type = -1;
module_param_named(ipc_type, sof_pci_ipc_type, int, 0444);
MODULE_PARM_DESC(ipc_type, "SOF IPC type (0): SOF, (1) Intel CAVS");
static const char *sof_dmi_override_tplg_name;
static bool sof_dmi_use_community_key;
#define SOF_PCI_DISABLE_PM_RUNTIME BIT(0)
static int sof_tplg_cb(const struct dmi_system_id *id)
{
sof_dmi_override_tplg_name = id->driver_data;
return 1;
}
static const struct dmi_system_id sof_tplg_table[] = {
{
.callback = sof_tplg_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Volteer"),
DMI_MATCH(DMI_OEM_STRING, "AUDIO-MAX98373_ALC5682I_I2S_UP4"),
},
.driver_data = "sof-tgl-rt5682-ssp0-max98373-ssp2.tplg",
},
{
.callback = sof_tplg_cb,
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "Alder Lake Client Platform"),
DMI_MATCH(DMI_OEM_STRING, "AUDIO-ADL_MAX98373_ALC5682I_I2S"),
},
.driver_data = "sof-adl-rt5682-ssp0-max98373-ssp2.tplg",
},
{
.callback = sof_tplg_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"),
DMI_MATCH(DMI_OEM_STRING, "AUDIO-MAX98390_ALC5682I_I2S"),
},
.driver_data = "sof-adl-max98390-ssp2-rt5682-ssp0.tplg",
},
{
.callback = sof_tplg_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"),
DMI_MATCH(DMI_OEM_STRING, "AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY"),
},
.driver_data = "sof-adl-max98360a-rt5682-2way.tplg",
},
{
.callback = sof_tplg_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"),
DMI_MATCH(DMI_OEM_STRING, "AUDIO-AUDIO_MAX98357_ALC5682I_I2S_2WAY"),
},
.driver_data = "sof-adl-max98357a-rt5682-2way.tplg",
},
{
.callback = sof_tplg_cb,
.matches = {
DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"),
DMI_MATCH(DMI_OEM_STRING, "AUDIO-MAX98360_ALC5682I_I2S_AMP_SSP2"),
},
.driver_data = "sof-adl-max98357a-rt5682.tplg",
},
{}
};
/* all Up boards use the community key */
static int up_use_community_key(const struct dmi_system_id *id)
{
sof_dmi_use_community_key = true;
return 1;
}
/*
* For ApolloLake Chromebooks we want to force the use of the Intel production key.
* All newer platforms use the community key
*/
static int chromebook_use_community_key(const struct dmi_system_id *id)
{
if (!soc_intel_is_apl())
sof_dmi_use_community_key = true;
return 1;
}
static const struct dmi_system_id community_key_platforms[] = {
{
.ident = "Up boards",
.callback = up_use_community_key,
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "AAEON"),
}
},
{
.ident = "Google Chromebooks",
.callback = chromebook_use_community_key,
.matches = {
DMI_MATCH(DMI_PRODUCT_FAMILY, "Google"),
}
},
{},
};
const struct dev_pm_ops sof_pci_pm = {
.prepare = snd_sof_prepare,
.complete = snd_sof_complete,
SET_SYSTEM_SLEEP_PM_OPS(snd_sof_suspend, snd_sof_resume)
SET_RUNTIME_PM_OPS(snd_sof_runtime_suspend, snd_sof_runtime_resume,
snd_sof_runtime_idle)
};
EXPORT_SYMBOL_NS(sof_pci_pm, SND_SOC_SOF_PCI_DEV);
static void sof_pci_probe_complete(struct device *dev)
{
dev_dbg(dev, "Completing SOF PCI probe");
if (sof_pci_debug & SOF_PCI_DISABLE_PM_RUNTIME)
return;
/* allow runtime_pm */
pm_runtime_set_autosuspend_delay(dev, SND_SOF_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
/*
* runtime pm for pci device is "forbidden" by default.
* so call pm_runtime_allow() to enable it.
*/
pm_runtime_allow(dev);
/* mark last_busy for pm_runtime to make sure not suspend immediately */
pm_runtime_mark_last_busy(dev);
/* follow recommendation in pci-driver.c to decrement usage counter */
pm_runtime_put_noidle(dev);
}
int sof_pci_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
{
struct device *dev = &pci->dev;
const struct sof_dev_desc *desc =
(const struct sof_dev_desc *)pci_id->driver_data;
struct snd_sof_pdata *sof_pdata;
int ret;
dev_dbg(&pci->dev, "PCI DSP detected");
if (!desc) {
dev_err(dev, "error: no matching PCI descriptor\n");
return -ENODEV;
}
if (!desc->ops) {
dev_err(dev, "error: no matching PCI descriptor ops\n");
return -ENODEV;
}
sof_pdata = devm_kzalloc(dev, sizeof(*sof_pdata), GFP_KERNEL);
if (!sof_pdata)
return -ENOMEM;
ret = pcim_enable_device(pci);
if (ret < 0)
return ret;
ret = pci_request_regions(pci, "Audio DSP");
if (ret < 0)
return ret;
sof_pdata->name = pci_name(pci);
sof_pdata->desc = desc;
sof_pdata->dev = dev;
sof_pdata->ipc_type = desc->ipc_default;
if (sof_pci_ipc_type < 0) {
sof_pdata->ipc_type = desc->ipc_default;
} else {
dev_info(dev, "overriding default IPC %d to requested %d\n",
desc->ipc_default, sof_pci_ipc_type);
if (sof_pci_ipc_type >= SOF_IPC_TYPE_COUNT) {
dev_err(dev, "invalid request value %d\n", sof_pci_ipc_type);
ret = -EINVAL;
goto out;
}
if (!(BIT(sof_pci_ipc_type) & desc->ipc_supported_mask)) {
dev_err(dev, "invalid request value %d, supported mask is %#x\n",
sof_pci_ipc_type, desc->ipc_supported_mask);
ret = -EINVAL;
goto out;
}
sof_pdata->ipc_type = sof_pci_ipc_type;
}
if (fw_filename) {
sof_pdata->fw_filename = fw_filename;
dev_dbg(dev, "Module parameter used, changed fw filename to %s\n",
sof_pdata->fw_filename);
} else {
sof_pdata->fw_filename = desc->default_fw_filename[sof_pdata->ipc_type];
}
/*
* for platforms using the SOF community key, change the
* default path automatically to pick the right files from the
* linux-firmware tree. This can be overridden with the
* fw_path kernel parameter, e.g. for developers.
*/
/* alternate fw and tplg filenames ? */
if (fw_path) {
sof_pdata->fw_filename_prefix = fw_path;
dev_dbg(dev,
"Module parameter used, changed fw path to %s\n",
sof_pdata->fw_filename_prefix);
} else if (dmi_check_system(community_key_platforms) && sof_dmi_use_community_key) {
sof_pdata->fw_filename_prefix =
devm_kasprintf(dev, GFP_KERNEL, "%s/%s",
sof_pdata->desc->default_fw_path[sof_pdata->ipc_type],
"community");
dev_dbg(dev,
"Platform uses community key, changed fw path to %s\n",
sof_pdata->fw_filename_prefix);
} else {
sof_pdata->fw_filename_prefix =
sof_pdata->desc->default_fw_path[sof_pdata->ipc_type];
}
if (lib_path) {
sof_pdata->fw_lib_prefix = lib_path;
dev_dbg(dev, "Module parameter used, changed fw_lib path to %s\n",
sof_pdata->fw_lib_prefix);
} else if (sof_pdata->desc->default_lib_path[sof_pdata->ipc_type]) {
if (dmi_check_system(community_key_platforms) && sof_dmi_use_community_key) {
sof_pdata->fw_lib_prefix =
devm_kasprintf(dev, GFP_KERNEL, "%s/%s",
sof_pdata->desc->default_lib_path[sof_pdata->ipc_type],
"community");
dev_dbg(dev,
"Platform uses community key, changed fw_lib path to %s\n",
sof_pdata->fw_lib_prefix);
} else {
sof_pdata->fw_lib_prefix =
sof_pdata->desc->default_lib_path[sof_pdata->ipc_type];
}
}
if (tplg_path)
sof_pdata->tplg_filename_prefix = tplg_path;
else
sof_pdata->tplg_filename_prefix =
sof_pdata->desc->default_tplg_path[sof_pdata->ipc_type];
/*
* the topology filename will be provided in the machine descriptor, unless
* it is overridden by a module parameter or DMI quirk.
*/
if (tplg_filename) {
sof_pdata->tplg_filename = tplg_filename;
dev_dbg(dev, "Module parameter used, changed tplg filename to %s\n",
sof_pdata->tplg_filename);
} else {
dmi_check_system(sof_tplg_table);
if (sof_dmi_override_tplg_name)
sof_pdata->tplg_filename = sof_dmi_override_tplg_name;
}
/* set callback to be called on successful device probe to enable runtime_pm */
sof_pdata->sof_probe_complete = sof_pci_probe_complete;
/* call sof helper for DSP hardware probe */
ret = snd_sof_device_probe(dev, sof_pdata);
out:
if (ret)
pci_release_regions(pci);
return ret;
}
EXPORT_SYMBOL_NS(sof_pci_probe, SND_SOC_SOF_PCI_DEV);
void sof_pci_remove(struct pci_dev *pci)
{
/* call sof helper for DSP hardware remove */
snd_sof_device_remove(&pci->dev);
/* follow recommendation in pci-driver.c to increment usage counter */
if (snd_sof_device_probe_completed(&pci->dev) &&
!(sof_pci_debug & SOF_PCI_DISABLE_PM_RUNTIME))
pm_runtime_get_noresume(&pci->dev);
/* release pci regions and disable device */
pci_release_regions(pci);
}
EXPORT_SYMBOL_NS(sof_pci_remove, SND_SOC_SOF_PCI_DEV);
void sof_pci_shutdown(struct pci_dev *pci)
{
snd_sof_device_shutdown(&pci->dev);
}
EXPORT_SYMBOL_NS(sof_pci_shutdown, SND_SOC_SOF_PCI_DEV);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/sof-pci-dev.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
/* Mixer Controls */
#include <linux/pm_runtime.h>
#include <linux/leds.h>
#include "sof-priv.h"
#include "sof-audio.h"
int snd_sof_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *sm = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_sof_control *scontrol = sm->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->volume_get)
return tplg_ops->control->volume_get(scontrol, ucontrol);
return 0;
}
int snd_sof_volume_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *sm = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_sof_control *scontrol = sm->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->volume_put)
return tplg_ops->control->volume_put(scontrol, ucontrol);
return false;
}
int snd_sof_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
struct soc_mixer_control *sm = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_sof_control *scontrol = sm->dobj.private;
unsigned int channels = scontrol->num_channels;
int platform_max;
if (!sm->platform_max)
sm->platform_max = sm->max;
platform_max = sm->platform_max;
if (platform_max == 1 && !strstr(kcontrol->id.name, " Volume"))
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
else
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = channels;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = platform_max - sm->min;
return 0;
}
int snd_sof_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *sm = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_sof_control *scontrol = sm->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->switch_get)
return tplg_ops->control->switch_get(scontrol, ucontrol);
return 0;
}
int snd_sof_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *sm = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_sof_control *scontrol = sm->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->switch_put)
return tplg_ops->control->switch_put(scontrol, ucontrol);
return false;
}
int snd_sof_enum_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *se = (struct soc_enum *)kcontrol->private_value;
struct snd_sof_control *scontrol = se->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->enum_get)
return tplg_ops->control->enum_get(scontrol, ucontrol);
return 0;
}
int snd_sof_enum_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *se = (struct soc_enum *)kcontrol->private_value;
struct snd_sof_control *scontrol = se->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->enum_put)
return tplg_ops->control->enum_put(scontrol, ucontrol);
return false;
}
int snd_sof_bytes_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_bytes_ext *be = (struct soc_bytes_ext *)kcontrol->private_value;
struct snd_sof_control *scontrol = be->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->bytes_get)
return tplg_ops->control->bytes_get(scontrol, ucontrol);
return 0;
}
int snd_sof_bytes_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_bytes_ext *be = (struct soc_bytes_ext *)kcontrol->private_value;
struct snd_sof_control *scontrol = be->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->bytes_put)
return tplg_ops->control->bytes_put(scontrol, ucontrol);
return 0;
}
int snd_sof_bytes_ext_put(struct snd_kcontrol *kcontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
struct soc_bytes_ext *be = (struct soc_bytes_ext *)kcontrol->private_value;
struct snd_sof_control *scontrol = be->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
/* make sure we have at least a header */
if (size < sizeof(struct snd_ctl_tlv))
return -EINVAL;
if (tplg_ops && tplg_ops->control && tplg_ops->control->bytes_ext_put)
return tplg_ops->control->bytes_ext_put(scontrol, binary_data, size);
return 0;
}
int snd_sof_bytes_ext_volatile_get(struct snd_kcontrol *kcontrol, unsigned int __user *binary_data,
unsigned int size)
{
struct soc_bytes_ext *be = (struct soc_bytes_ext *)kcontrol->private_value;
struct snd_sof_control *scontrol = be->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
int ret, err;
ret = pm_runtime_resume_and_get(scomp->dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(scomp->dev, "%s: failed to resume %d\n", __func__, ret);
return ret;
}
if (tplg_ops && tplg_ops->control && tplg_ops->control->bytes_ext_volatile_get)
ret = tplg_ops->control->bytes_ext_volatile_get(scontrol, binary_data, size);
pm_runtime_mark_last_busy(scomp->dev);
err = pm_runtime_put_autosuspend(scomp->dev);
if (err < 0)
dev_err_ratelimited(scomp->dev, "%s: failed to idle %d\n", __func__, err);
return ret;
}
int snd_sof_bytes_ext_get(struct snd_kcontrol *kcontrol,
unsigned int __user *binary_data,
unsigned int size)
{
struct soc_bytes_ext *be = (struct soc_bytes_ext *)kcontrol->private_value;
struct snd_sof_control *scontrol = be->dobj.private;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
if (tplg_ops && tplg_ops->control && tplg_ops->control->bytes_ext_get)
return tplg_ops->control->bytes_ext_get(scontrol, binary_data, size);
return 0;
}
| linux-master | sound/soc/sof/control.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/firmware.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/sof.h>
#include "sof-priv.h"
#include "ops.h"
#define CREATE_TRACE_POINTS
#include <trace/events/sof.h>
/* see SOF_DBG_ flags */
static int sof_core_debug = IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_FIRMWARE_TRACE);
module_param_named(sof_debug, sof_core_debug, int, 0444);
MODULE_PARM_DESC(sof_debug, "SOF core debug options (0x0 all off)");
/* SOF defaults if not provided by the platform in ms */
#define TIMEOUT_DEFAULT_IPC_MS 500
#define TIMEOUT_DEFAULT_BOOT_MS 2000
/**
* sof_debug_check_flag - check if a given flag(s) is set in sof_core_debug
* @mask: Flag or combination of flags to check
*
* Returns true if all bits set in mask is also set in sof_core_debug, otherwise
* false
*/
bool sof_debug_check_flag(int mask)
{
if ((sof_core_debug & mask) == mask)
return true;
return false;
}
EXPORT_SYMBOL(sof_debug_check_flag);
/*
* FW Panic/fault handling.
*/
struct sof_panic_msg {
u32 id;
const char *msg;
};
/* standard FW panic types */
static const struct sof_panic_msg panic_msg[] = {
{SOF_IPC_PANIC_MEM, "out of memory"},
{SOF_IPC_PANIC_WORK, "work subsystem init failed"},
{SOF_IPC_PANIC_IPC, "IPC subsystem init failed"},
{SOF_IPC_PANIC_ARCH, "arch init failed"},
{SOF_IPC_PANIC_PLATFORM, "platform init failed"},
{SOF_IPC_PANIC_TASK, "scheduler init failed"},
{SOF_IPC_PANIC_EXCEPTION, "runtime exception"},
{SOF_IPC_PANIC_DEADLOCK, "deadlock"},
{SOF_IPC_PANIC_STACK, "stack overflow"},
{SOF_IPC_PANIC_IDLE, "can't enter idle"},
{SOF_IPC_PANIC_WFI, "invalid wait state"},
{SOF_IPC_PANIC_ASSERT, "assertion failed"},
};
/**
* sof_print_oops_and_stack - Handle the printing of DSP oops and stack trace
* @sdev: Pointer to the device's sdev
* @level: prink log level to use for the printing
* @panic_code: the panic code
* @tracep_code: tracepoint code
* @oops: Pointer to DSP specific oops data
* @panic_info: Pointer to the received panic information message
* @stack: Pointer to the call stack data
* @stack_words: Number of words in the stack data
*
* helper to be called from .dbg_dump callbacks. No error code is
* provided, it's left as an exercise for the caller of .dbg_dump
* (typically IPC or loader)
*/
void sof_print_oops_and_stack(struct snd_sof_dev *sdev, const char *level,
u32 panic_code, u32 tracep_code, void *oops,
struct sof_ipc_panic_info *panic_info,
void *stack, size_t stack_words)
{
u32 code;
int i;
/* is firmware dead ? */
if ((panic_code & SOF_IPC_PANIC_MAGIC_MASK) != SOF_IPC_PANIC_MAGIC) {
dev_printk(level, sdev->dev, "unexpected fault %#010x trace %#010x\n",
panic_code, tracep_code);
return; /* no fault ? */
}
code = panic_code & (SOF_IPC_PANIC_MAGIC_MASK | SOF_IPC_PANIC_CODE_MASK);
for (i = 0; i < ARRAY_SIZE(panic_msg); i++) {
if (panic_msg[i].id == code) {
dev_printk(level, sdev->dev, "reason: %s (%#x)\n",
panic_msg[i].msg, code & SOF_IPC_PANIC_CODE_MASK);
dev_printk(level, sdev->dev, "trace point: %#010x\n", tracep_code);
goto out;
}
}
/* unknown error */
dev_printk(level, sdev->dev, "unknown panic code: %#x\n",
code & SOF_IPC_PANIC_CODE_MASK);
dev_printk(level, sdev->dev, "trace point: %#010x\n", tracep_code);
out:
dev_printk(level, sdev->dev, "panic at %s:%d\n", panic_info->filename,
panic_info->linenum);
sof_oops(sdev, level, oops);
sof_stack(sdev, level, oops, stack, stack_words);
}
EXPORT_SYMBOL(sof_print_oops_and_stack);
/* Helper to manage DSP state */
void sof_set_fw_state(struct snd_sof_dev *sdev, enum sof_fw_state new_state)
{
if (sdev->fw_state == new_state)
return;
dev_dbg(sdev->dev, "fw_state change: %d -> %d\n", sdev->fw_state, new_state);
sdev->fw_state = new_state;
switch (new_state) {
case SOF_FW_BOOT_NOT_STARTED:
case SOF_FW_BOOT_COMPLETE:
case SOF_FW_CRASHED:
sof_client_fw_state_dispatcher(sdev);
fallthrough;
default:
break;
}
}
EXPORT_SYMBOL(sof_set_fw_state);
/*
* FW Boot State Transition Diagram
*
* +----------------------------------------------------------------------+
* | |
* ------------------ ------------------ |
* | | | | |
* | BOOT_FAILED |<-------| READY_FAILED | |
* | |<--+ | | ------------------ |
* ------------------ | ------------------ | | |
* ^ | ^ | CRASHED |---+ |
* | | | | | | |
* (FW Boot Timeout) | (FW_READY FAIL) ------------------ | |
* | | | ^ | |
* | | | |(DSP Panic) | |
* ------------------ | | ------------------ | |
* | | | | | | | |
* | IN_PROGRESS |---------------+------------->| COMPLETE | | |
* | | (FW Boot OK) (FW_READY OK) | | | |
* ------------------ | ------------------ | |
* ^ | | | |
* | | | | |
* (FW Loading OK) | (System Suspend/Runtime Suspend)
* | | | | |
* | (FW Loading Fail) | | |
* ------------------ | ------------------ | | |
* | | | | |<-----+ | |
* | PREPARE |---+ | NOT_STARTED |<---------------------+ |
* | | | |<--------------------------+
* ------------------ ------------------
* | ^ | ^
* | | | |
* | +-----------------------+ |
* | (DSP Probe OK) |
* | |
* | |
* +------------------------------------+
* (System Suspend/Runtime Suspend)
*/
static int sof_probe_continue(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *plat_data = sdev->pdata;
int ret;
/* probe the DSP hardware */
ret = snd_sof_probe(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to probe DSP %d\n", ret);
goto probe_err;
}
sof_set_fw_state(sdev, SOF_FW_BOOT_PREPARE);
/* check machine info */
ret = sof_machine_check(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to get machine info %d\n",
ret);
goto dsp_err;
}
/* set up platform component driver */
snd_sof_new_platform_drv(sdev);
if (sdev->dspless_mode_selected) {
sof_set_fw_state(sdev, SOF_DSPLESS_MODE);
goto skip_dsp_init;
}
/* register any debug/trace capabilities */
ret = snd_sof_dbg_init(sdev);
if (ret < 0) {
/*
* debugfs issues are suppressed in snd_sof_dbg_init() since
* we cannot rely on debugfs
* here we trap errors due to memory allocation only.
*/
dev_err(sdev->dev, "error: failed to init DSP trace/debug %d\n",
ret);
goto dbg_err;
}
/* init the IPC */
sdev->ipc = snd_sof_ipc_init(sdev);
if (!sdev->ipc) {
ret = -ENOMEM;
dev_err(sdev->dev, "error: failed to init DSP IPC %d\n", ret);
goto ipc_err;
}
/* load the firmware */
ret = snd_sof_load_firmware(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to load DSP firmware %d\n",
ret);
sof_set_fw_state(sdev, SOF_FW_BOOT_FAILED);
goto fw_load_err;
}
sof_set_fw_state(sdev, SOF_FW_BOOT_IN_PROGRESS);
/*
* Boot the firmware. The FW boot status will be modified
* in snd_sof_run_firmware() depending on the outcome.
*/
ret = snd_sof_run_firmware(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to boot DSP firmware %d\n",
ret);
sof_set_fw_state(sdev, SOF_FW_BOOT_FAILED);
goto fw_run_err;
}
if (sof_debug_check_flag(SOF_DBG_ENABLE_TRACE)) {
sdev->fw_trace_is_supported = true;
/* init firmware tracing */
ret = sof_fw_trace_init(sdev);
if (ret < 0) {
/* non fatal */
dev_warn(sdev->dev, "failed to initialize firmware tracing %d\n",
ret);
}
} else {
dev_dbg(sdev->dev, "SOF firmware trace disabled\n");
}
skip_dsp_init:
/* hereafter all FW boot flows are for PM reasons */
sdev->first_boot = false;
/* now register audio DSP platform driver and dai */
ret = devm_snd_soc_register_component(sdev->dev, &sdev->plat_drv,
sof_ops(sdev)->drv,
sof_ops(sdev)->num_drv);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to register DSP DAI driver %d\n", ret);
goto fw_trace_err;
}
ret = snd_sof_machine_register(sdev, plat_data);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to register machine driver %d\n", ret);
goto fw_trace_err;
}
ret = sof_register_clients(sdev);
if (ret < 0) {
dev_err(sdev->dev, "failed to register clients %d\n", ret);
goto sof_machine_err;
}
/*
* Some platforms in SOF, ex: BYT, may not have their platform PM
* callbacks set. Increment the usage count so as to
* prevent the device from entering runtime suspend.
*/
if (!sof_ops(sdev)->runtime_suspend || !sof_ops(sdev)->runtime_resume)
pm_runtime_get_noresume(sdev->dev);
if (plat_data->sof_probe_complete)
plat_data->sof_probe_complete(sdev->dev);
sdev->probe_completed = true;
return 0;
sof_machine_err:
snd_sof_machine_unregister(sdev, plat_data);
fw_trace_err:
sof_fw_trace_free(sdev);
fw_run_err:
snd_sof_fw_unload(sdev);
fw_load_err:
snd_sof_ipc_free(sdev);
ipc_err:
dbg_err:
snd_sof_free_debug(sdev);
dsp_err:
snd_sof_remove(sdev);
probe_err:
sof_ops_free(sdev);
/* all resources freed, update state to match */
sof_set_fw_state(sdev, SOF_FW_BOOT_NOT_STARTED);
sdev->first_boot = true;
return ret;
}
static void sof_probe_work(struct work_struct *work)
{
struct snd_sof_dev *sdev =
container_of(work, struct snd_sof_dev, probe_work);
int ret;
ret = sof_probe_continue(sdev);
if (ret < 0) {
/* errors cannot be propagated, log */
dev_err(sdev->dev, "error: %s failed err: %d\n", __func__, ret);
}
}
int snd_sof_device_probe(struct device *dev, struct snd_sof_pdata *plat_data)
{
struct snd_sof_dev *sdev;
int ret;
sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
if (!sdev)
return -ENOMEM;
/* initialize sof device */
sdev->dev = dev;
/* initialize default DSP power state */
sdev->dsp_power_state.state = SOF_DSP_PM_D0;
sdev->pdata = plat_data;
sdev->first_boot = true;
dev_set_drvdata(dev, sdev);
if (sof_core_debug)
dev_info(dev, "sof_debug value: %#x\n", sof_core_debug);
if (sof_debug_check_flag(SOF_DBG_DSPLESS_MODE)) {
if (plat_data->desc->dspless_mode_supported) {
dev_info(dev, "Switching to DSPless mode\n");
sdev->dspless_mode_selected = true;
} else {
dev_info(dev, "DSPless mode is not supported by the platform\n");
}
}
/* check IPC support */
if (!(BIT(plat_data->ipc_type) & plat_data->desc->ipc_supported_mask)) {
dev_err(dev, "ipc_type %d is not supported on this platform, mask is %#x\n",
plat_data->ipc_type, plat_data->desc->ipc_supported_mask);
return -EINVAL;
}
/* init ops, if necessary */
ret = sof_ops_init(sdev);
if (ret < 0)
return ret;
/* check all mandatory ops */
if (!sof_ops(sdev) || !sof_ops(sdev)->probe) {
sof_ops_free(sdev);
dev_err(dev, "missing mandatory ops\n");
return -EINVAL;
}
if (!sdev->dspless_mode_selected &&
(!sof_ops(sdev)->run || !sof_ops(sdev)->block_read ||
!sof_ops(sdev)->block_write || !sof_ops(sdev)->send_msg ||
!sof_ops(sdev)->load_firmware || !sof_ops(sdev)->ipc_msg_data)) {
sof_ops_free(sdev);
dev_err(dev, "missing mandatory DSP ops\n");
return -EINVAL;
}
INIT_LIST_HEAD(&sdev->pcm_list);
INIT_LIST_HEAD(&sdev->kcontrol_list);
INIT_LIST_HEAD(&sdev->widget_list);
INIT_LIST_HEAD(&sdev->pipeline_list);
INIT_LIST_HEAD(&sdev->dai_list);
INIT_LIST_HEAD(&sdev->dai_link_list);
INIT_LIST_HEAD(&sdev->route_list);
INIT_LIST_HEAD(&sdev->ipc_client_list);
INIT_LIST_HEAD(&sdev->ipc_rx_handler_list);
INIT_LIST_HEAD(&sdev->fw_state_handler_list);
spin_lock_init(&sdev->ipc_lock);
spin_lock_init(&sdev->hw_lock);
mutex_init(&sdev->power_state_access);
mutex_init(&sdev->ipc_client_mutex);
mutex_init(&sdev->client_event_handler_mutex);
/* set default timeouts if none provided */
if (plat_data->desc->ipc_timeout == 0)
sdev->ipc_timeout = TIMEOUT_DEFAULT_IPC_MS;
else
sdev->ipc_timeout = plat_data->desc->ipc_timeout;
if (plat_data->desc->boot_timeout == 0)
sdev->boot_timeout = TIMEOUT_DEFAULT_BOOT_MS;
else
sdev->boot_timeout = plat_data->desc->boot_timeout;
sof_set_fw_state(sdev, SOF_FW_BOOT_NOT_STARTED);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE)) {
INIT_WORK(&sdev->probe_work, sof_probe_work);
schedule_work(&sdev->probe_work);
return 0;
}
return sof_probe_continue(sdev);
}
EXPORT_SYMBOL(snd_sof_device_probe);
bool snd_sof_device_probe_completed(struct device *dev)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
return sdev->probe_completed;
}
EXPORT_SYMBOL(snd_sof_device_probe_completed);
int snd_sof_device_remove(struct device *dev)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
struct snd_sof_pdata *pdata = sdev->pdata;
int ret;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE))
cancel_work_sync(&sdev->probe_work);
/*
* Unregister any registered client device first before IPC and debugfs
* to allow client drivers to be removed cleanly
*/
sof_unregister_clients(sdev);
/*
* Unregister machine driver. This will unbind the snd_card which
* will remove the component driver and unload the topology
* before freeing the snd_card.
*/
snd_sof_machine_unregister(sdev, pdata);
if (sdev->fw_state > SOF_FW_BOOT_NOT_STARTED) {
sof_fw_trace_free(sdev);
ret = snd_sof_dsp_power_down_notify(sdev);
if (ret < 0)
dev_warn(dev, "error: %d failed to prepare DSP for device removal",
ret);
snd_sof_ipc_free(sdev);
snd_sof_free_debug(sdev);
snd_sof_remove(sdev);
sof_ops_free(sdev);
}
/* release firmware */
snd_sof_fw_unload(sdev);
return 0;
}
EXPORT_SYMBOL(snd_sof_device_remove);
int snd_sof_device_shutdown(struct device *dev)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE))
cancel_work_sync(&sdev->probe_work);
if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
sof_fw_trace_free(sdev);
return snd_sof_shutdown(sdev);
}
return 0;
}
EXPORT_SYMBOL(snd_sof_device_shutdown);
MODULE_AUTHOR("Liam Girdwood");
MODULE_DESCRIPTION("Sound Open Firmware (SOF) Core");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("platform:sof-audio");
MODULE_IMPORT_NS(SND_SOC_SOF_CLIENT);
| linux-master | sound/soc/sof/core.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
// Generic debug routines used to export DSP MMIO and memories to userspace
// for firmware debugging.
//
#include <linux/debugfs.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <sound/sof/ext_manifest.h>
#include <sound/sof/debug.h>
#include "sof-priv.h"
#include "ops.h"
static ssize_t sof_dfsentry_write(struct file *file, const char __user *buffer,
size_t count, loff_t *ppos)
{
size_t size;
char *string;
int ret;
string = kzalloc(count+1, GFP_KERNEL);
if (!string)
return -ENOMEM;
size = simple_write_to_buffer(string, count, ppos, buffer, count);
ret = size;
kfree(string);
return ret;
}
static ssize_t sof_dfsentry_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct snd_sof_dfsentry *dfse = file->private_data;
struct snd_sof_dev *sdev = dfse->sdev;
loff_t pos = *ppos;
size_t size_ret;
int skip = 0;
int size;
u8 *buf;
size = dfse->size;
/* validate position & count */
if (pos < 0)
return -EINVAL;
if (pos >= size || !count)
return 0;
/* find the minimum. min() is not used since it adds sparse warnings */
if (count > size - pos)
count = size - pos;
/* align io read start to u32 multiple */
pos = ALIGN_DOWN(pos, 4);
/* intermediate buffer size must be u32 multiple */
size = ALIGN(count, 4);
/* if start position is unaligned, read extra u32 */
if (unlikely(pos != *ppos)) {
skip = *ppos - pos;
if (pos + size + 4 < dfse->size)
size += 4;
}
buf = kzalloc(size, GFP_KERNEL);
if (!buf)
return -ENOMEM;
if (dfse->type == SOF_DFSENTRY_TYPE_IOMEM) {
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE)
/*
* If the DSP is active: copy from IO.
* If the DSP is suspended:
* - Copy from IO if the memory is always accessible.
* - Otherwise, copy from cached buffer.
*/
if (pm_runtime_active(sdev->dev) ||
dfse->access_type == SOF_DEBUGFS_ACCESS_ALWAYS) {
memcpy_fromio(buf, dfse->io_mem + pos, size);
} else {
dev_info(sdev->dev,
"Copying cached debugfs data\n");
memcpy(buf, dfse->cache_buf + pos, size);
}
#else
/* if the DSP is in D3 */
if (!pm_runtime_active(sdev->dev) &&
dfse->access_type == SOF_DEBUGFS_ACCESS_D0_ONLY) {
dev_err(sdev->dev,
"error: debugfs entry cannot be read in DSP D3\n");
kfree(buf);
return -EINVAL;
}
memcpy_fromio(buf, dfse->io_mem + pos, size);
#endif
} else {
memcpy(buf, ((u8 *)(dfse->buf) + pos), size);
}
/* copy to userspace */
size_ret = copy_to_user(buffer, buf + skip, count);
kfree(buf);
/* update count & position if copy succeeded */
if (size_ret)
return -EFAULT;
*ppos = pos + count;
return count;
}
static const struct file_operations sof_dfs_fops = {
.open = simple_open,
.read = sof_dfsentry_read,
.llseek = default_llseek,
.write = sof_dfsentry_write,
};
/* create FS entry for debug files that can expose DSP memories, registers */
static int snd_sof_debugfs_io_item(struct snd_sof_dev *sdev,
void __iomem *base, size_t size,
const char *name,
enum sof_debugfs_access_type access_type)
{
struct snd_sof_dfsentry *dfse;
if (!sdev)
return -EINVAL;
dfse = devm_kzalloc(sdev->dev, sizeof(*dfse), GFP_KERNEL);
if (!dfse)
return -ENOMEM;
dfse->type = SOF_DFSENTRY_TYPE_IOMEM;
dfse->io_mem = base;
dfse->size = size;
dfse->sdev = sdev;
dfse->access_type = access_type;
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE)
/*
* allocate cache buffer that will be used to save the mem window
* contents prior to suspend
*/
if (access_type == SOF_DEBUGFS_ACCESS_D0_ONLY) {
dfse->cache_buf = devm_kzalloc(sdev->dev, size, GFP_KERNEL);
if (!dfse->cache_buf)
return -ENOMEM;
}
#endif
debugfs_create_file(name, 0444, sdev->debugfs_root, dfse,
&sof_dfs_fops);
/* add to dfsentry list */
list_add(&dfse->list, &sdev->dfsentry_list);
return 0;
}
int snd_sof_debugfs_add_region_item_iomem(struct snd_sof_dev *sdev,
enum snd_sof_fw_blk_type blk_type, u32 offset,
size_t size, const char *name,
enum sof_debugfs_access_type access_type)
{
int bar = snd_sof_dsp_get_bar_index(sdev, blk_type);
if (bar < 0)
return bar;
return snd_sof_debugfs_io_item(sdev, sdev->bar[bar] + offset, size, name,
access_type);
}
EXPORT_SYMBOL_GPL(snd_sof_debugfs_add_region_item_iomem);
/* create FS entry for debug files to expose kernel memory */
int snd_sof_debugfs_buf_item(struct snd_sof_dev *sdev,
void *base, size_t size,
const char *name, mode_t mode)
{
struct snd_sof_dfsentry *dfse;
if (!sdev)
return -EINVAL;
dfse = devm_kzalloc(sdev->dev, sizeof(*dfse), GFP_KERNEL);
if (!dfse)
return -ENOMEM;
dfse->type = SOF_DFSENTRY_TYPE_BUF;
dfse->buf = base;
dfse->size = size;
dfse->sdev = sdev;
debugfs_create_file(name, mode, sdev->debugfs_root, dfse,
&sof_dfs_fops);
/* add to dfsentry list */
list_add(&dfse->list, &sdev->dfsentry_list);
return 0;
}
EXPORT_SYMBOL_GPL(snd_sof_debugfs_buf_item);
static int memory_info_update(struct snd_sof_dev *sdev, char *buf, size_t buff_size)
{
struct sof_ipc_cmd_hdr msg = {
.size = sizeof(struct sof_ipc_cmd_hdr),
.cmd = SOF_IPC_GLB_DEBUG | SOF_IPC_DEBUG_MEM_USAGE,
};
struct sof_ipc_dbg_mem_usage *reply;
int len;
int ret;
int i;
reply = kmalloc(SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL);
if (!reply)
return -ENOMEM;
ret = pm_runtime_resume_and_get(sdev->dev);
if (ret < 0 && ret != -EACCES) {
dev_err(sdev->dev, "error: enabling device failed: %d\n", ret);
goto error;
}
ret = sof_ipc_tx_message(sdev->ipc, &msg, msg.size, reply, SOF_IPC_MSG_MAX_SIZE);
pm_runtime_mark_last_busy(sdev->dev);
pm_runtime_put_autosuspend(sdev->dev);
if (ret < 0 || reply->rhdr.error < 0) {
ret = min(ret, reply->rhdr.error);
dev_err(sdev->dev, "error: reading memory info failed, %d\n", ret);
goto error;
}
if (struct_size(reply, elems, reply->num_elems) != reply->rhdr.hdr.size) {
dev_err(sdev->dev, "error: invalid memory info ipc struct size, %d\n",
reply->rhdr.hdr.size);
ret = -EINVAL;
goto error;
}
for (i = 0, len = 0; i < reply->num_elems; i++) {
ret = scnprintf(buf + len, buff_size - len, "zone %d.%d used %#8x free %#8x\n",
reply->elems[i].zone, reply->elems[i].id,
reply->elems[i].used, reply->elems[i].free);
if (ret < 0)
goto error;
len += ret;
}
ret = len;
error:
kfree(reply);
return ret;
}
static ssize_t memory_info_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
{
struct snd_sof_dfsentry *dfse = file->private_data;
struct snd_sof_dev *sdev = dfse->sdev;
int data_length;
/* read memory info from FW only once for each file read */
if (!*ppos) {
dfse->buf_data_size = 0;
data_length = memory_info_update(sdev, dfse->buf, dfse->size);
if (data_length < 0)
return data_length;
dfse->buf_data_size = data_length;
}
return simple_read_from_buffer(to, count, ppos, dfse->buf, dfse->buf_data_size);
}
static int memory_info_open(struct inode *inode, struct file *file)
{
struct snd_sof_dfsentry *dfse = inode->i_private;
struct snd_sof_dev *sdev = dfse->sdev;
file->private_data = dfse;
/* allocate buffer memory only in first open run, to save memory when unused */
if (!dfse->buf) {
dfse->buf = devm_kmalloc(sdev->dev, PAGE_SIZE, GFP_KERNEL);
if (!dfse->buf)
return -ENOMEM;
dfse->size = PAGE_SIZE;
}
return 0;
}
static const struct file_operations memory_info_fops = {
.open = memory_info_open,
.read = memory_info_read,
.llseek = default_llseek,
};
int snd_sof_dbg_memory_info_init(struct snd_sof_dev *sdev)
{
struct snd_sof_dfsentry *dfse;
dfse = devm_kzalloc(sdev->dev, sizeof(*dfse), GFP_KERNEL);
if (!dfse)
return -ENOMEM;
/* don't allocate buffer before first usage, to save memory when unused */
dfse->type = SOF_DFSENTRY_TYPE_BUF;
dfse->sdev = sdev;
debugfs_create_file("memory_info", 0444, sdev->debugfs_root, dfse, &memory_info_fops);
/* add to dfsentry list */
list_add(&dfse->list, &sdev->dfsentry_list);
return 0;
}
EXPORT_SYMBOL_GPL(snd_sof_dbg_memory_info_init);
int snd_sof_dbg_init(struct snd_sof_dev *sdev)
{
struct snd_sof_dsp_ops *ops = sof_ops(sdev);
const struct snd_sof_debugfs_map *map;
int i;
int err;
/* use "sof" as top level debugFS dir */
sdev->debugfs_root = debugfs_create_dir("sof", NULL);
/* init dfsentry list */
INIT_LIST_HEAD(&sdev->dfsentry_list);
/* create debugFS files for platform specific MMIO/DSP memories */
for (i = 0; i < ops->debug_map_count; i++) {
map = &ops->debug_map[i];
err = snd_sof_debugfs_io_item(sdev, sdev->bar[map->bar] +
map->offset, map->size,
map->name, map->access_type);
/* errors are only due to memory allocation, not debugfs */
if (err < 0)
return err;
}
return snd_sof_debugfs_buf_item(sdev, &sdev->fw_state,
sizeof(sdev->fw_state),
"fw_state", 0444);
}
EXPORT_SYMBOL_GPL(snd_sof_dbg_init);
void snd_sof_free_debug(struct snd_sof_dev *sdev)
{
debugfs_remove_recursive(sdev->debugfs_root);
}
EXPORT_SYMBOL_GPL(snd_sof_free_debug);
static const struct soc_fw_state_info {
enum sof_fw_state state;
const char *name;
} fw_state_dbg[] = {
{SOF_FW_BOOT_NOT_STARTED, "SOF_FW_BOOT_NOT_STARTED"},
{SOF_DSPLESS_MODE, "SOF_DSPLESS_MODE"},
{SOF_FW_BOOT_PREPARE, "SOF_FW_BOOT_PREPARE"},
{SOF_FW_BOOT_IN_PROGRESS, "SOF_FW_BOOT_IN_PROGRESS"},
{SOF_FW_BOOT_FAILED, "SOF_FW_BOOT_FAILED"},
{SOF_FW_BOOT_READY_FAILED, "SOF_FW_BOOT_READY_FAILED"},
{SOF_FW_BOOT_READY_OK, "SOF_FW_BOOT_READY_OK"},
{SOF_FW_BOOT_COMPLETE, "SOF_FW_BOOT_COMPLETE"},
{SOF_FW_CRASHED, "SOF_FW_CRASHED"},
};
static void snd_sof_dbg_print_fw_state(struct snd_sof_dev *sdev, const char *level)
{
int i;
for (i = 0; i < ARRAY_SIZE(fw_state_dbg); i++) {
if (sdev->fw_state == fw_state_dbg[i].state) {
dev_printk(level, sdev->dev, "fw_state: %s (%d)\n",
fw_state_dbg[i].name, i);
return;
}
}
dev_printk(level, sdev->dev, "fw_state: UNKNOWN (%d)\n", sdev->fw_state);
}
void snd_sof_dsp_dbg_dump(struct snd_sof_dev *sdev, const char *msg, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
bool print_all = sof_debug_check_flag(SOF_DBG_PRINT_ALL_DUMPS);
if (flags & SOF_DBG_DUMP_OPTIONAL && !print_all)
return;
if (sof_ops(sdev)->dbg_dump && !sdev->dbg_dump_printed) {
dev_printk(level, sdev->dev,
"------------[ DSP dump start ]------------\n");
if (msg)
dev_printk(level, sdev->dev, "%s\n", msg);
snd_sof_dbg_print_fw_state(sdev, level);
sof_ops(sdev)->dbg_dump(sdev, flags);
dev_printk(level, sdev->dev,
"------------[ DSP dump end ]------------\n");
if (!print_all)
sdev->dbg_dump_printed = true;
} else if (msg) {
dev_printk(level, sdev->dev, "%s\n", msg);
}
}
EXPORT_SYMBOL(snd_sof_dsp_dbg_dump);
static void snd_sof_ipc_dump(struct snd_sof_dev *sdev)
{
if (sof_ops(sdev)->ipc_dump && !sdev->ipc_dump_printed) {
dev_err(sdev->dev, "------------[ IPC dump start ]------------\n");
sof_ops(sdev)->ipc_dump(sdev);
dev_err(sdev->dev, "------------[ IPC dump end ]------------\n");
if (!sof_debug_check_flag(SOF_DBG_PRINT_ALL_DUMPS))
sdev->ipc_dump_printed = true;
}
}
void snd_sof_handle_fw_exception(struct snd_sof_dev *sdev, const char *msg)
{
if (IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_RETAIN_DSP_CONTEXT) ||
sof_debug_check_flag(SOF_DBG_RETAIN_CTX)) {
/* should we prevent DSP entering D3 ? */
if (!sdev->ipc_dump_printed)
dev_info(sdev->dev,
"Attempting to prevent DSP from entering D3 state to preserve context\n");
pm_runtime_get_if_in_use(sdev->dev);
}
/* dump vital information to the logs */
snd_sof_ipc_dump(sdev);
snd_sof_dsp_dbg_dump(sdev, msg, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX);
sof_fw_trace_fw_crashed(sdev);
}
EXPORT_SYMBOL(snd_sof_handle_fw_exception);
| linux-master | sound/soc/sof/debug.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
#include <linux/debugfs.h>
#include <linux/sched/signal.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ops.h"
#include "sof-utils.h"
#include "ipc3-priv.h"
#define TRACE_FILTER_ELEMENTS_PER_ENTRY 4
#define TRACE_FILTER_MAX_CONFIG_STRING_LENGTH 1024
enum sof_dtrace_state {
SOF_DTRACE_DISABLED,
SOF_DTRACE_STOPPED,
SOF_DTRACE_INITIALIZING,
SOF_DTRACE_ENABLED,
};
struct sof_dtrace_priv {
struct snd_dma_buffer dmatb;
struct snd_dma_buffer dmatp;
int dma_trace_pages;
wait_queue_head_t trace_sleep;
u32 host_offset;
bool dtrace_error;
bool dtrace_draining;
enum sof_dtrace_state dtrace_state;
};
static bool trace_pos_update_expected(struct sof_dtrace_priv *priv)
{
if (priv->dtrace_state == SOF_DTRACE_ENABLED ||
priv->dtrace_state == SOF_DTRACE_INITIALIZING)
return true;
return false;
}
static int trace_filter_append_elem(struct snd_sof_dev *sdev, u32 key, u32 value,
struct sof_ipc_trace_filter_elem *elem_list,
int capacity, int *counter)
{
if (*counter >= capacity)
return -ENOMEM;
elem_list[*counter].key = key;
elem_list[*counter].value = value;
++*counter;
return 0;
}
static int trace_filter_parse_entry(struct snd_sof_dev *sdev, const char *line,
struct sof_ipc_trace_filter_elem *elem,
int capacity, int *counter)
{
int log_level, pipe_id, comp_id, read, ret;
int len = strlen(line);
int cnt = *counter;
u32 uuid_id;
/* ignore empty content */
ret = sscanf(line, " %n", &read);
if (!ret && read == len)
return len;
ret = sscanf(line, " %d %x %d %d %n", &log_level, &uuid_id, &pipe_id, &comp_id, &read);
if (ret != TRACE_FILTER_ELEMENTS_PER_ENTRY || read != len) {
dev_err(sdev->dev, "Invalid trace filter entry '%s'\n", line);
return -EINVAL;
}
if (uuid_id > 0) {
ret = trace_filter_append_elem(sdev, SOF_IPC_TRACE_FILTER_ELEM_BY_UUID,
uuid_id, elem, capacity, &cnt);
if (ret)
return ret;
}
if (pipe_id >= 0) {
ret = trace_filter_append_elem(sdev, SOF_IPC_TRACE_FILTER_ELEM_BY_PIPE,
pipe_id, elem, capacity, &cnt);
if (ret)
return ret;
}
if (comp_id >= 0) {
ret = trace_filter_append_elem(sdev, SOF_IPC_TRACE_FILTER_ELEM_BY_COMP,
comp_id, elem, capacity, &cnt);
if (ret)
return ret;
}
ret = trace_filter_append_elem(sdev, SOF_IPC_TRACE_FILTER_ELEM_SET_LEVEL |
SOF_IPC_TRACE_FILTER_ELEM_FIN,
log_level, elem, capacity, &cnt);
if (ret)
return ret;
/* update counter only when parsing whole entry passed */
*counter = cnt;
return len;
}
static int trace_filter_parse(struct snd_sof_dev *sdev, char *string,
int *out_elem_cnt,
struct sof_ipc_trace_filter_elem **out)
{
static const char entry_delimiter[] = ";";
char *entry = string;
int capacity = 0;
int entry_len;
int cnt = 0;
/*
* Each entry contains at least 1, up to TRACE_FILTER_ELEMENTS_PER_ENTRY
* IPC elements, depending on content. Calculate IPC elements capacity
* for the input string where each element is set.
*/
while (entry) {
capacity += TRACE_FILTER_ELEMENTS_PER_ENTRY;
entry = strchr(entry + 1, entry_delimiter[0]);
}
*out = kmalloc(capacity * sizeof(**out), GFP_KERNEL);
if (!*out)
return -ENOMEM;
/* split input string by ';', and parse each entry separately in trace_filter_parse_entry */
while ((entry = strsep(&string, entry_delimiter))) {
entry_len = trace_filter_parse_entry(sdev, entry, *out, capacity, &cnt);
if (entry_len < 0) {
dev_err(sdev->dev,
"Parsing filter entry '%s' failed with %d\n",
entry, entry_len);
return -EINVAL;
}
}
*out_elem_cnt = cnt;
return 0;
}
static int ipc3_trace_update_filter(struct snd_sof_dev *sdev, int num_elems,
struct sof_ipc_trace_filter_elem *elems)
{
struct sof_ipc_trace_filter *msg;
size_t size;
int ret;
size = struct_size(msg, elems, num_elems);
if (size > SOF_IPC_MSG_MAX_SIZE)
return -EINVAL;
msg = kmalloc(size, GFP_KERNEL);
if (!msg)
return -ENOMEM;
msg->hdr.size = size;
msg->hdr.cmd = SOF_IPC_GLB_TRACE_MSG | SOF_IPC_TRACE_FILTER_UPDATE;
msg->elem_cnt = num_elems;
memcpy(&msg->elems[0], elems, num_elems * sizeof(*elems));
ret = pm_runtime_resume_and_get(sdev->dev);
if (ret < 0 && ret != -EACCES) {
dev_err(sdev->dev, "enabling device failed: %d\n", ret);
goto error;
}
ret = sof_ipc_tx_message_no_reply(sdev->ipc, msg, msg->hdr.size);
pm_runtime_mark_last_busy(sdev->dev);
pm_runtime_put_autosuspend(sdev->dev);
error:
kfree(msg);
return ret;
}
static ssize_t dfsentry_trace_filter_write(struct file *file, const char __user *from,
size_t count, loff_t *ppos)
{
struct snd_sof_dfsentry *dfse = file->private_data;
struct sof_ipc_trace_filter_elem *elems = NULL;
struct snd_sof_dev *sdev = dfse->sdev;
int num_elems;
char *string;
int ret;
if (count > TRACE_FILTER_MAX_CONFIG_STRING_LENGTH) {
dev_err(sdev->dev, "%s too long input, %zu > %d\n", __func__, count,
TRACE_FILTER_MAX_CONFIG_STRING_LENGTH);
return -EINVAL;
}
string = memdup_user_nul(from, count);
if (IS_ERR(string))
return PTR_ERR(string);
ret = trace_filter_parse(sdev, string, &num_elems, &elems);
if (ret < 0)
goto error;
if (num_elems) {
ret = ipc3_trace_update_filter(sdev, num_elems, elems);
if (ret < 0) {
dev_err(sdev->dev, "Filter update failed: %d\n", ret);
goto error;
}
}
ret = count;
error:
kfree(string);
kfree(elems);
return ret;
}
static const struct file_operations sof_dfs_trace_filter_fops = {
.open = simple_open,
.write = dfsentry_trace_filter_write,
.llseek = default_llseek,
};
static int debugfs_create_trace_filter(struct snd_sof_dev *sdev)
{
struct snd_sof_dfsentry *dfse;
dfse = devm_kzalloc(sdev->dev, sizeof(*dfse), GFP_KERNEL);
if (!dfse)
return -ENOMEM;
dfse->sdev = sdev;
dfse->type = SOF_DFSENTRY_TYPE_BUF;
debugfs_create_file("filter", 0200, sdev->debugfs_root, dfse,
&sof_dfs_trace_filter_fops);
/* add to dfsentry list */
list_add(&dfse->list, &sdev->dfsentry_list);
return 0;
}
static bool sof_dtrace_set_host_offset(struct sof_dtrace_priv *priv, u32 new_offset)
{
u32 host_offset = READ_ONCE(priv->host_offset);
if (host_offset != new_offset) {
/* This is a bit paranoid and unlikely that it is needed */
u32 ret = cmpxchg(&priv->host_offset, host_offset, new_offset);
if (ret == host_offset)
return true;
}
return false;
}
static size_t sof_dtrace_avail(struct snd_sof_dev *sdev,
loff_t pos, size_t buffer_size)
{
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
loff_t host_offset = READ_ONCE(priv->host_offset);
/*
* If host offset is less than local pos, it means write pointer of
* host DMA buffer has been wrapped. We should output the trace data
* at the end of host DMA buffer at first.
*/
if (host_offset < pos)
return buffer_size - pos;
/* If there is available trace data now, it is unnecessary to wait. */
if (host_offset > pos)
return host_offset - pos;
return 0;
}
static size_t sof_wait_dtrace_avail(struct snd_sof_dev *sdev, loff_t pos,
size_t buffer_size)
{
size_t ret = sof_dtrace_avail(sdev, pos, buffer_size);
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
wait_queue_entry_t wait;
/* data immediately available */
if (ret)
return ret;
if (priv->dtrace_draining && !trace_pos_update_expected(priv)) {
/*
* tracing has ended and all traces have been
* read by client, return EOF
*/
priv->dtrace_draining = false;
return 0;
}
/* wait for available trace data from FW */
init_waitqueue_entry(&wait, current);
set_current_state(TASK_INTERRUPTIBLE);
add_wait_queue(&priv->trace_sleep, &wait);
if (!signal_pending(current)) {
/* set timeout to max value, no error code */
schedule_timeout(MAX_SCHEDULE_TIMEOUT);
}
remove_wait_queue(&priv->trace_sleep, &wait);
return sof_dtrace_avail(sdev, pos, buffer_size);
}
static ssize_t dfsentry_dtrace_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct snd_sof_dfsentry *dfse = file->private_data;
struct snd_sof_dev *sdev = dfse->sdev;
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
unsigned long rem;
loff_t lpos = *ppos;
size_t avail, buffer_size = dfse->size;
u64 lpos_64;
/* make sure we know about any failures on the DSP side */
priv->dtrace_error = false;
/* check pos and count */
if (lpos < 0)
return -EINVAL;
if (!count)
return 0;
/* check for buffer wrap and count overflow */
lpos_64 = lpos;
lpos = do_div(lpos_64, buffer_size);
/* get available count based on current host offset */
avail = sof_wait_dtrace_avail(sdev, lpos, buffer_size);
if (priv->dtrace_error) {
dev_err(sdev->dev, "trace IO error\n");
return -EIO;
}
/* no new trace data */
if (!avail)
return 0;
/* make sure count is <= avail */
if (count > avail)
count = avail;
/*
* make sure that all trace data is available for the CPU as the trace
* data buffer might be allocated from non consistent memory.
* Note: snd_dma_buffer_sync() is called for normal audio playback and
* capture streams also.
*/
snd_dma_buffer_sync(&priv->dmatb, SNDRV_DMA_SYNC_CPU);
/* copy available trace data to debugfs */
rem = copy_to_user(buffer, ((u8 *)(dfse->buf) + lpos), count);
if (rem)
return -EFAULT;
*ppos += count;
/* move debugfs reading position */
return count;
}
static int dfsentry_dtrace_release(struct inode *inode, struct file *file)
{
struct snd_sof_dfsentry *dfse = inode->i_private;
struct snd_sof_dev *sdev = dfse->sdev;
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
/* avoid duplicate traces at next open */
if (priv->dtrace_state != SOF_DTRACE_ENABLED)
sof_dtrace_set_host_offset(priv, 0);
return 0;
}
static const struct file_operations sof_dfs_dtrace_fops = {
.open = simple_open,
.read = dfsentry_dtrace_read,
.llseek = default_llseek,
.release = dfsentry_dtrace_release,
};
static int debugfs_create_dtrace(struct snd_sof_dev *sdev)
{
struct sof_dtrace_priv *priv;
struct snd_sof_dfsentry *dfse;
int ret;
if (!sdev)
return -EINVAL;
priv = sdev->fw_trace_data;
ret = debugfs_create_trace_filter(sdev);
if (ret < 0)
dev_warn(sdev->dev, "failed to create filter debugfs file: %d", ret);
dfse = devm_kzalloc(sdev->dev, sizeof(*dfse), GFP_KERNEL);
if (!dfse)
return -ENOMEM;
dfse->type = SOF_DFSENTRY_TYPE_BUF;
dfse->buf = priv->dmatb.area;
dfse->size = priv->dmatb.bytes;
dfse->sdev = sdev;
debugfs_create_file("trace", 0444, sdev->debugfs_root, dfse,
&sof_dfs_dtrace_fops);
return 0;
}
static int ipc3_dtrace_enable(struct snd_sof_dev *sdev)
{
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
struct sof_ipc_fw_version *v = &ready->version;
struct sof_ipc_dma_trace_params_ext params;
int ret;
if (!sdev->fw_trace_is_supported)
return 0;
if (priv->dtrace_state == SOF_DTRACE_ENABLED || !priv->dma_trace_pages)
return -EINVAL;
if (priv->dtrace_state == SOF_DTRACE_STOPPED)
goto start;
/* set IPC parameters */
params.hdr.cmd = SOF_IPC_GLB_TRACE_MSG;
/* PARAMS_EXT is only supported from ABI 3.7.0 onwards */
if (v->abi_version >= SOF_ABI_VER(3, 7, 0)) {
params.hdr.size = sizeof(struct sof_ipc_dma_trace_params_ext);
params.hdr.cmd |= SOF_IPC_TRACE_DMA_PARAMS_EXT;
params.timestamp_ns = ktime_get(); /* in nanosecond */
} else {
params.hdr.size = sizeof(struct sof_ipc_dma_trace_params);
params.hdr.cmd |= SOF_IPC_TRACE_DMA_PARAMS;
}
params.buffer.phy_addr = priv->dmatp.addr;
params.buffer.size = priv->dmatb.bytes;
params.buffer.pages = priv->dma_trace_pages;
params.stream_tag = 0;
sof_dtrace_set_host_offset(priv, 0);
priv->dtrace_draining = false;
ret = sof_dtrace_host_init(sdev, &priv->dmatb, ¶ms);
if (ret < 0) {
dev_err(sdev->dev, "Host dtrace init failed: %d\n", ret);
return ret;
}
dev_dbg(sdev->dev, "stream_tag: %d\n", params.stream_tag);
/* send IPC to the DSP */
priv->dtrace_state = SOF_DTRACE_INITIALIZING;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, ¶ms, sizeof(params));
if (ret < 0) {
dev_err(sdev->dev, "can't set params for DMA for trace %d\n", ret);
goto trace_release;
}
start:
priv->dtrace_state = SOF_DTRACE_ENABLED;
ret = sof_dtrace_host_trigger(sdev, SNDRV_PCM_TRIGGER_START);
if (ret < 0) {
dev_err(sdev->dev, "Host dtrace trigger start failed: %d\n", ret);
goto trace_release;
}
return 0;
trace_release:
priv->dtrace_state = SOF_DTRACE_DISABLED;
sof_dtrace_host_release(sdev);
return ret;
}
static int ipc3_dtrace_init(struct snd_sof_dev *sdev)
{
struct sof_dtrace_priv *priv;
int ret;
/* dtrace is only supported with SOF_IPC */
if (sdev->pdata->ipc_type != SOF_IPC)
return -EOPNOTSUPP;
if (sdev->fw_trace_data) {
dev_err(sdev->dev, "fw_trace_data has been already allocated\n");
return -EBUSY;
}
priv = devm_kzalloc(sdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
sdev->fw_trace_data = priv;
/* set false before start initialization */
priv->dtrace_state = SOF_DTRACE_DISABLED;
/* allocate trace page table buffer */
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, sdev->dev,
PAGE_SIZE, &priv->dmatp);
if (ret < 0) {
dev_err(sdev->dev, "can't alloc page table for trace %d\n", ret);
return ret;
}
/* allocate trace data buffer */
ret = snd_dma_alloc_dir_pages(SNDRV_DMA_TYPE_DEV_SG, sdev->dev,
DMA_FROM_DEVICE, DMA_BUF_SIZE_FOR_TRACE,
&priv->dmatb);
if (ret < 0) {
dev_err(sdev->dev, "can't alloc buffer for trace %d\n", ret);
goto page_err;
}
/* create compressed page table for audio firmware */
ret = snd_sof_create_page_table(sdev->dev, &priv->dmatb,
priv->dmatp.area, priv->dmatb.bytes);
if (ret < 0)
goto table_err;
priv->dma_trace_pages = ret;
dev_dbg(sdev->dev, "dma_trace_pages: %d\n", priv->dma_trace_pages);
if (sdev->first_boot) {
ret = debugfs_create_dtrace(sdev);
if (ret < 0)
goto table_err;
}
init_waitqueue_head(&priv->trace_sleep);
ret = ipc3_dtrace_enable(sdev);
if (ret < 0)
goto table_err;
return 0;
table_err:
priv->dma_trace_pages = 0;
snd_dma_free_pages(&priv->dmatb);
page_err:
snd_dma_free_pages(&priv->dmatp);
return ret;
}
int ipc3_dtrace_posn_update(struct snd_sof_dev *sdev,
struct sof_ipc_dma_trace_posn *posn)
{
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
if (!sdev->fw_trace_is_supported)
return 0;
if (trace_pos_update_expected(priv) &&
sof_dtrace_set_host_offset(priv, posn->host_offset))
wake_up(&priv->trace_sleep);
if (posn->overflow != 0)
dev_err(sdev->dev,
"DSP trace buffer overflow %u bytes. Total messages %d\n",
posn->overflow, posn->messages);
return 0;
}
/* an error has occurred within the DSP that prevents further trace */
static void ipc3_dtrace_fw_crashed(struct snd_sof_dev *sdev)
{
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
if (priv->dtrace_state == SOF_DTRACE_ENABLED) {
priv->dtrace_error = true;
wake_up(&priv->trace_sleep);
}
}
static void ipc3_dtrace_release(struct snd_sof_dev *sdev, bool only_stop)
{
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
struct sof_ipc_fw_version *v = &ready->version;
struct sof_ipc_cmd_hdr hdr;
int ret;
if (!sdev->fw_trace_is_supported || priv->dtrace_state == SOF_DTRACE_DISABLED)
return;
ret = sof_dtrace_host_trigger(sdev, SNDRV_PCM_TRIGGER_STOP);
if (ret < 0)
dev_err(sdev->dev, "Host dtrace trigger stop failed: %d\n", ret);
priv->dtrace_state = SOF_DTRACE_STOPPED;
/*
* stop and free trace DMA in the DSP. TRACE_DMA_FREE is only supported from
* ABI 3.20.0 onwards
*/
if (v->abi_version >= SOF_ABI_VER(3, 20, 0)) {
hdr.size = sizeof(hdr);
hdr.cmd = SOF_IPC_GLB_TRACE_MSG | SOF_IPC_TRACE_DMA_FREE;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &hdr, hdr.size);
if (ret < 0)
dev_err(sdev->dev, "DMA_TRACE_FREE failed with error: %d\n", ret);
}
if (only_stop)
goto out;
ret = sof_dtrace_host_release(sdev);
if (ret < 0)
dev_err(sdev->dev, "Host dtrace release failed %d\n", ret);
priv->dtrace_state = SOF_DTRACE_DISABLED;
out:
priv->dtrace_draining = true;
wake_up(&priv->trace_sleep);
}
static void ipc3_dtrace_suspend(struct snd_sof_dev *sdev, pm_message_t pm_state)
{
ipc3_dtrace_release(sdev, pm_state.event == SOF_DSP_PM_D0);
}
static int ipc3_dtrace_resume(struct snd_sof_dev *sdev)
{
return ipc3_dtrace_enable(sdev);
}
static void ipc3_dtrace_free(struct snd_sof_dev *sdev)
{
struct sof_dtrace_priv *priv = sdev->fw_trace_data;
/* release trace */
ipc3_dtrace_release(sdev, false);
if (priv->dma_trace_pages) {
snd_dma_free_pages(&priv->dmatb);
snd_dma_free_pages(&priv->dmatp);
priv->dma_trace_pages = 0;
}
}
const struct sof_ipc_fw_tracing_ops ipc3_dtrace_ops = {
.init = ipc3_dtrace_init,
.free = ipc3_dtrace_free,
.fw_crashed = ipc3_dtrace_fw_crashed,
.suspend = ipc3_dtrace_suspend,
.resume = ipc3_dtrace_resume,
};
| linux-master | sound/soc/sof/ipc3-dtrace.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Intel Corporation. All rights reserved.
//
//
#include <sound/pcm_params.h>
#include "ipc3-priv.h"
#include "ops.h"
#include "sof-priv.h"
#include "sof-audio.h"
static int sof_ipc3_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sof_ipc_stream stream;
struct snd_sof_pcm *spcm;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
if (!spcm->prepared[substream->stream])
return 0;
stream.hdr.size = sizeof(stream);
stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_PCM_FREE;
stream.comp_id = spcm->stream[substream->stream].comp_id;
/* send IPC to the DSP */
return sof_ipc_tx_message_no_reply(sdev->ipc, &stream, sizeof(stream));
}
static int sof_ipc3_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_sof_platform_stream_params *platform_params)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
struct snd_pcm_runtime *runtime = substream->runtime;
struct sof_ipc_pcm_params_reply ipc_params_reply;
struct sof_ipc_pcm_params pcm;
struct snd_sof_pcm *spcm;
int ret;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
memset(&pcm, 0, sizeof(pcm));
/* number of pages should be rounded up */
pcm.params.buffer.pages = PFN_UP(runtime->dma_bytes);
/* set IPC PCM parameters */
pcm.hdr.size = sizeof(pcm);
pcm.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_PCM_PARAMS;
pcm.comp_id = spcm->stream[substream->stream].comp_id;
pcm.params.hdr.size = sizeof(pcm.params);
pcm.params.buffer.phy_addr = spcm->stream[substream->stream].page_table.addr;
pcm.params.buffer.size = runtime->dma_bytes;
pcm.params.direction = substream->stream;
pcm.params.sample_valid_bytes = params_width(params) >> 3;
pcm.params.buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
pcm.params.rate = params_rate(params);
pcm.params.channels = params_channels(params);
pcm.params.host_period_bytes = params_period_bytes(params);
/* container size */
ret = snd_pcm_format_physical_width(params_format(params));
if (ret < 0)
return ret;
pcm.params.sample_container_bytes = ret >> 3;
/* format */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16:
pcm.params.frame_fmt = SOF_IPC_FRAME_S16_LE;
break;
case SNDRV_PCM_FORMAT_S24:
pcm.params.frame_fmt = SOF_IPC_FRAME_S24_4LE;
break;
case SNDRV_PCM_FORMAT_S32:
pcm.params.frame_fmt = SOF_IPC_FRAME_S32_LE;
break;
case SNDRV_PCM_FORMAT_FLOAT:
pcm.params.frame_fmt = SOF_IPC_FRAME_FLOAT;
break;
default:
return -EINVAL;
}
/* Update the IPC message with information from the platform */
pcm.params.stream_tag = platform_params->stream_tag;
if (platform_params->use_phy_address)
pcm.params.buffer.phy_addr = platform_params->phy_addr;
if (platform_params->no_ipc_position) {
/* For older ABIs set host_period_bytes to zero to inform
* FW we don't want position updates. Newer versions use
* no_stream_position for this purpose.
*/
if (v->abi_version < SOF_ABI_VER(3, 10, 0))
pcm.params.host_period_bytes = 0;
else
pcm.params.no_stream_position = 1;
}
if (platform_params->cont_update_posn)
pcm.params.cont_update_posn = 1;
dev_dbg(component->dev, "stream_tag %d", pcm.params.stream_tag);
/* send hw_params IPC to the DSP */
ret = sof_ipc_tx_message(sdev->ipc, &pcm, sizeof(pcm),
&ipc_params_reply, sizeof(ipc_params_reply));
if (ret < 0) {
dev_err(component->dev, "HW params ipc failed for stream %d\n",
pcm.params.stream_tag);
return ret;
}
ret = snd_sof_set_stream_data_offset(sdev, &spcm->stream[substream->stream],
ipc_params_reply.posn_offset);
if (ret < 0) {
dev_err(component->dev, "%s: invalid stream data offset for PCM %d\n",
__func__, spcm->pcm.pcm_id);
return ret;
}
return ret;
}
static int sof_ipc3_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct sof_ipc_stream stream;
struct snd_sof_pcm *spcm;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
stream.hdr.size = sizeof(stream);
stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG;
stream.comp_id = spcm->stream[substream->stream].comp_id;
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_PAUSE;
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_RELEASE;
break;
case SNDRV_PCM_TRIGGER_START:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_START;
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
fallthrough;
case SNDRV_PCM_TRIGGER_STOP:
stream.hdr.cmd |= SOF_IPC_STREAM_TRIG_STOP;
break;
default:
dev_err(component->dev, "Unhandled trigger cmd %d\n", cmd);
return -EINVAL;
}
/* send IPC to the DSP */
return sof_ipc_tx_message_no_reply(sdev->ipc, &stream, sizeof(stream));
}
static void ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
struct snd_pcm_hw_params *params)
{
struct sof_ipc_dai_config *config;
struct snd_sof_dai *dai;
int i;
/*
* Search for all matching DAIs as we can have both playback and capture DAI
* associated with the same link.
*/
list_for_each_entry(dai, &sdev->dai_list, list) {
if (!dai->name || strcmp(link_name, dai->name))
continue;
for (i = 0; i < dai->number_configs; i++) {
struct sof_dai_private_data *private = dai->private;
config = &private->dai_config[i];
if (config->ssp.fsync_rate == params_rate(params)) {
dev_dbg(sdev->dev, "DAI config %d matches pcm hw params\n", i);
dai->current_config = i;
break;
}
}
}
}
static int sof_ipc3_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_sof_dai *dai = snd_sof_find_dai(component, (char *)rtd->dai_link->name);
struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct sof_dai_private_data *private;
struct snd_soc_dpcm *dpcm;
if (!dai) {
dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
rtd->dai_link->name);
return -EINVAL;
}
private = dai->private;
if (!private) {
dev_err(component->dev, "%s: No private data found for DAI %s\n", __func__,
rtd->dai_link->name);
return -EINVAL;
}
/* read format from topology */
snd_mask_none(fmt);
switch (private->comp_dai->config.frame_fmt) {
case SOF_IPC_FRAME_S16_LE:
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
break;
case SOF_IPC_FRAME_S24_4LE:
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
break;
case SOF_IPC_FRAME_S32_LE:
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);
break;
default:
dev_err(component->dev, "No available DAI format!\n");
return -EINVAL;
}
/* read rate and channels from topology */
switch (private->dai_config->type) {
case SOF_DAI_INTEL_SSP:
/* search for config to pcm params match, if not found use default */
ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
rate->min = private->dai_config[dai->current_config].ssp.fsync_rate;
rate->max = private->dai_config[dai->current_config].ssp.fsync_rate;
channels->min = private->dai_config[dai->current_config].ssp.tdm_slots;
channels->max = private->dai_config[dai->current_config].ssp.tdm_slots;
dev_dbg(component->dev, "rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_INTEL_DMIC:
/* DMIC only supports 16 or 32 bit formats */
if (private->comp_dai->config.frame_fmt == SOF_IPC_FRAME_S24_4LE) {
dev_err(component->dev, "Invalid fmt %d for DAI type %d\n",
private->comp_dai->config.frame_fmt,
private->dai_config->type);
}
break;
case SOF_DAI_INTEL_HDA:
/*
* HDAudio does not follow the default trigger
* sequence due to firmware implementation
*/
for_each_dpcm_fe(rtd, SNDRV_PCM_STREAM_PLAYBACK, dpcm) {
struct snd_soc_pcm_runtime *fe = dpcm->fe;
fe->dai_link->trigger[SNDRV_PCM_STREAM_PLAYBACK] =
SND_SOC_DPCM_TRIGGER_POST;
}
break;
case SOF_DAI_INTEL_ALH:
/*
* Dai could run with different channel count compared with
* front end, so get dai channel count from topology
*/
channels->min = private->dai_config->alh.channels;
channels->max = private->dai_config->alh.channels;
break;
case SOF_DAI_IMX_ESAI:
rate->min = private->dai_config->esai.fsync_rate;
rate->max = private->dai_config->esai.fsync_rate;
channels->min = private->dai_config->esai.tdm_slots;
channels->max = private->dai_config->esai.tdm_slots;
dev_dbg(component->dev, "rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_MEDIATEK_AFE:
rate->min = private->dai_config->afe.rate;
rate->max = private->dai_config->afe.rate;
channels->min = private->dai_config->afe.channels;
channels->max = private->dai_config->afe.channels;
snd_mask_none(fmt);
switch (private->dai_config->afe.format) {
case SOF_IPC_FRAME_S16_LE:
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
break;
case SOF_IPC_FRAME_S24_4LE:
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
break;
case SOF_IPC_FRAME_S32_LE:
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);
break;
default:
dev_err(component->dev, "Not available format!\n");
return -EINVAL;
}
dev_dbg(component->dev, "rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_IMX_SAI:
rate->min = private->dai_config->sai.fsync_rate;
rate->max = private->dai_config->sai.fsync_rate;
channels->min = private->dai_config->sai.tdm_slots;
channels->max = private->dai_config->sai.tdm_slots;
dev_dbg(component->dev, "rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_AMD_BT:
rate->min = private->dai_config->acpbt.fsync_rate;
rate->max = private->dai_config->acpbt.fsync_rate;
channels->min = private->dai_config->acpbt.tdm_slots;
channels->max = private->dai_config->acpbt.tdm_slots;
dev_dbg(component->dev,
"AMD_BT rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "AMD_BT channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_AMD_SP:
case SOF_DAI_AMD_SP_VIRTUAL:
rate->min = private->dai_config->acpsp.fsync_rate;
rate->max = private->dai_config->acpsp.fsync_rate;
channels->min = private->dai_config->acpsp.tdm_slots;
channels->max = private->dai_config->acpsp.tdm_slots;
dev_dbg(component->dev,
"AMD_SP rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "AMD_SP channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
case SOF_DAI_AMD_HS:
case SOF_DAI_AMD_HS_VIRTUAL:
rate->min = private->dai_config->acphs.fsync_rate;
rate->max = private->dai_config->acphs.fsync_rate;
channels->min = private->dai_config->acphs.tdm_slots;
channels->max = private->dai_config->acphs.tdm_slots;
dev_dbg(component->dev,
"AMD_HS channel_max: %d rate_max: %d\n", channels->max, rate->max);
break;
case SOF_DAI_AMD_DMIC:
rate->min = private->dai_config->acpdmic.pdm_rate;
rate->max = private->dai_config->acpdmic.pdm_rate;
channels->min = private->dai_config->acpdmic.pdm_ch;
channels->max = private->dai_config->acpdmic.pdm_ch;
dev_dbg(component->dev,
"AMD_DMIC rate_min: %d rate_max: %d\n", rate->min, rate->max);
dev_dbg(component->dev, "AMD_DMIC channels_min: %d channels_max: %d\n",
channels->min, channels->max);
break;
default:
dev_err(component->dev, "Invalid DAI type %d\n", private->dai_config->type);
break;
}
return 0;
}
const struct sof_ipc_pcm_ops ipc3_pcm_ops = {
.hw_params = sof_ipc3_pcm_hw_params,
.hw_free = sof_ipc3_pcm_hw_free,
.trigger = sof_ipc3_pcm_trigger,
.dai_link_fixup = sof_ipc3_pcm_dai_link_fixup,
.reset_hw_params_during_stop = true,
};
| linux-master | sound/soc/sof/ipc3-pcm.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include "ops.h"
#include "sof-priv.h"
#include "sof-audio.h"
/*
* Helper function to determine the target DSP state during
* system suspend. This function only cares about the device
* D-states. Platform-specific substates, if any, should be
* handled by the platform-specific parts.
*/
static u32 snd_sof_dsp_power_target(struct snd_sof_dev *sdev)
{
u32 target_dsp_state;
switch (sdev->system_suspend_target) {
case SOF_SUSPEND_S5:
case SOF_SUSPEND_S4:
/* DSP should be in D3 if the system is suspending to S3+ */
case SOF_SUSPEND_S3:
/* DSP should be in D3 if the system is suspending to S3 */
target_dsp_state = SOF_DSP_PM_D3;
break;
case SOF_SUSPEND_S0IX:
/*
* Currently, the only criterion for retaining the DSP in D0
* is that there are streams that ignored the suspend trigger.
* Additional criteria such Soundwire clock-stop mode and
* device suspend latency considerations will be added later.
*/
if (snd_sof_stream_suspend_ignored(sdev))
target_dsp_state = SOF_DSP_PM_D0;
else
target_dsp_state = SOF_DSP_PM_D3;
break;
default:
/* This case would be during runtime suspend */
target_dsp_state = SOF_DSP_PM_D3;
break;
}
return target_dsp_state;
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE)
static void sof_cache_debugfs(struct snd_sof_dev *sdev)
{
struct snd_sof_dfsentry *dfse;
list_for_each_entry(dfse, &sdev->dfsentry_list, list) {
/* nothing to do if debugfs buffer is not IO mem */
if (dfse->type == SOF_DFSENTRY_TYPE_BUF)
continue;
/* cache memory that is only accessible in D0 */
if (dfse->access_type == SOF_DEBUGFS_ACCESS_D0_ONLY)
memcpy_fromio(dfse->cache_buf, dfse->io_mem,
dfse->size);
}
}
#endif
static int sof_resume(struct device *dev, bool runtime_resume)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
u32 old_state = sdev->dsp_power_state.state;
int ret;
/* do nothing if dsp resume callbacks are not set */
if (!runtime_resume && !sof_ops(sdev)->resume)
return 0;
if (runtime_resume && !sof_ops(sdev)->runtime_resume)
return 0;
/* DSP was never successfully started, nothing to resume */
if (sdev->first_boot)
return 0;
/*
* if the runtime_resume flag is set, call the runtime_resume routine
* or else call the system resume routine
*/
if (runtime_resume)
ret = snd_sof_dsp_runtime_resume(sdev);
else
ret = snd_sof_dsp_resume(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to power up DSP after resume\n");
return ret;
}
if (sdev->dspless_mode_selected) {
sof_set_fw_state(sdev, SOF_DSPLESS_MODE);
return 0;
}
/*
* Nothing further to be done for platforms that support the low power
* D0 substate. Resume trace and return when resuming from
* low-power D0 substate
*/
if (!runtime_resume && sof_ops(sdev)->set_power_state &&
old_state == SOF_DSP_PM_D0) {
ret = sof_fw_trace_resume(sdev);
if (ret < 0)
/* non fatal */
dev_warn(sdev->dev,
"failed to enable trace after resume %d\n", ret);
return 0;
}
sof_set_fw_state(sdev, SOF_FW_BOOT_PREPARE);
/* load the firmware */
ret = snd_sof_load_firmware(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to load DSP firmware after resume %d\n",
ret);
sof_set_fw_state(sdev, SOF_FW_BOOT_FAILED);
return ret;
}
sof_set_fw_state(sdev, SOF_FW_BOOT_IN_PROGRESS);
/*
* Boot the firmware. The FW boot status will be modified
* in snd_sof_run_firmware() depending on the outcome.
*/
ret = snd_sof_run_firmware(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to boot DSP firmware after resume %d\n",
ret);
sof_set_fw_state(sdev, SOF_FW_BOOT_FAILED);
return ret;
}
/* resume DMA trace */
ret = sof_fw_trace_resume(sdev);
if (ret < 0) {
/* non fatal */
dev_warn(sdev->dev,
"warning: failed to init trace after resume %d\n",
ret);
}
/* restore pipelines */
if (tplg_ops && tplg_ops->set_up_all_pipelines) {
ret = tplg_ops->set_up_all_pipelines(sdev, false);
if (ret < 0) {
dev_err(sdev->dev, "Failed to restore pipeline after resume %d\n", ret);
goto setup_fail;
}
}
/* Notify clients not managed by pm framework about core resume */
sof_resume_clients(sdev);
/* notify DSP of system resume */
if (pm_ops && pm_ops->ctx_restore) {
ret = pm_ops->ctx_restore(sdev);
if (ret < 0)
dev_err(sdev->dev, "ctx_restore IPC error during resume: %d\n", ret);
}
setup_fail:
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE)
if (ret < 0) {
/*
* Debugfs cannot be read in runtime suspend, so cache
* the contents upon failure. This allows to capture
* possible DSP coredump information.
*/
sof_cache_debugfs(sdev);
}
#endif
return ret;
}
static int sof_suspend(struct device *dev, bool runtime_suspend)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
pm_message_t pm_state;
u32 target_state = snd_sof_dsp_power_target(sdev);
u32 old_state = sdev->dsp_power_state.state;
int ret;
/* do nothing if dsp suspend callback is not set */
if (!runtime_suspend && !sof_ops(sdev)->suspend)
return 0;
if (runtime_suspend && !sof_ops(sdev)->runtime_suspend)
return 0;
/* we need to tear down pipelines only if the DSP hardware is
* active, which happens for PCI devices. if the device is
* suspended, it is brought back to full power and then
* suspended again
*/
if (tplg_ops && tplg_ops->tear_down_all_pipelines && (old_state == SOF_DSP_PM_D0))
tplg_ops->tear_down_all_pipelines(sdev, false);
if (sdev->fw_state != SOF_FW_BOOT_COMPLETE)
goto suspend;
/* prepare for streams to be resumed properly upon resume */
if (!runtime_suspend) {
ret = snd_sof_dsp_hw_params_upon_resume(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: setting hw_params flag during suspend %d\n",
ret);
return ret;
}
}
pm_state.event = target_state;
/* suspend DMA trace */
sof_fw_trace_suspend(sdev, pm_state);
/* Notify clients not managed by pm framework about core suspend */
sof_suspend_clients(sdev, pm_state);
/* Skip to platform-specific suspend if DSP is entering D0 */
if (target_state == SOF_DSP_PM_D0)
goto suspend;
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE)
/* cache debugfs contents during runtime suspend */
if (runtime_suspend)
sof_cache_debugfs(sdev);
#endif
/* notify DSP of upcoming power down */
if (pm_ops && pm_ops->ctx_save) {
ret = pm_ops->ctx_save(sdev);
if (ret == -EBUSY || ret == -EAGAIN) {
/*
* runtime PM has logic to handle -EBUSY/-EAGAIN so
* pass these errors up
*/
dev_err(sdev->dev, "ctx_save IPC error during suspend: %d\n", ret);
return ret;
} else if (ret < 0) {
/* FW in unexpected state, continue to power down */
dev_warn(sdev->dev, "ctx_save IPC error: %d, proceeding with suspend\n",
ret);
}
}
suspend:
/* return if the DSP was not probed successfully */
if (sdev->fw_state == SOF_FW_BOOT_NOT_STARTED)
return 0;
/* platform-specific suspend */
if (runtime_suspend)
ret = snd_sof_dsp_runtime_suspend(sdev);
else
ret = snd_sof_dsp_suspend(sdev, target_state);
if (ret < 0)
dev_err(sdev->dev,
"error: failed to power down DSP during suspend %d\n",
ret);
/* Do not reset FW state if DSP is in D0 */
if (target_state == SOF_DSP_PM_D0)
return ret;
/* reset FW state */
sof_set_fw_state(sdev, SOF_FW_BOOT_NOT_STARTED);
sdev->enabled_cores_mask = 0;
return ret;
}
int snd_sof_dsp_power_down_notify(struct snd_sof_dev *sdev)
{
const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm);
/* Notify DSP of upcoming power down */
if (sof_ops(sdev)->remove && pm_ops && pm_ops->ctx_save)
return pm_ops->ctx_save(sdev);
return 0;
}
int snd_sof_runtime_suspend(struct device *dev)
{
return sof_suspend(dev, true);
}
EXPORT_SYMBOL(snd_sof_runtime_suspend);
int snd_sof_runtime_idle(struct device *dev)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
return snd_sof_dsp_runtime_idle(sdev);
}
EXPORT_SYMBOL(snd_sof_runtime_idle);
int snd_sof_runtime_resume(struct device *dev)
{
return sof_resume(dev, true);
}
EXPORT_SYMBOL(snd_sof_runtime_resume);
int snd_sof_resume(struct device *dev)
{
return sof_resume(dev, false);
}
EXPORT_SYMBOL(snd_sof_resume);
int snd_sof_suspend(struct device *dev)
{
return sof_suspend(dev, false);
}
EXPORT_SYMBOL(snd_sof_suspend);
int snd_sof_prepare(struct device *dev)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
const struct sof_dev_desc *desc = sdev->pdata->desc;
/* will suspend to S3 by default */
sdev->system_suspend_target = SOF_SUSPEND_S3;
/*
* if the firmware is crashed or boot failed then we try to aim for S3
* to reboot the firmware
*/
if (sdev->fw_state == SOF_FW_CRASHED ||
sdev->fw_state == SOF_FW_BOOT_FAILED)
return 0;
if (!desc->use_acpi_target_states)
return 0;
#if defined(CONFIG_ACPI)
switch (acpi_target_system_state()) {
case ACPI_STATE_S0:
sdev->system_suspend_target = SOF_SUSPEND_S0IX;
break;
case ACPI_STATE_S1:
case ACPI_STATE_S2:
case ACPI_STATE_S3:
sdev->system_suspend_target = SOF_SUSPEND_S3;
break;
case ACPI_STATE_S4:
sdev->system_suspend_target = SOF_SUSPEND_S4;
break;
case ACPI_STATE_S5:
sdev->system_suspend_target = SOF_SUSPEND_S5;
break;
default:
break;
}
#endif
return 0;
}
EXPORT_SYMBOL(snd_sof_prepare);
void snd_sof_complete(struct device *dev)
{
struct snd_sof_dev *sdev = dev_get_drvdata(dev);
sdev->system_suspend_target = SOF_SUSPEND_NONE;
}
EXPORT_SYMBOL(snd_sof_complete);
| linux-master | sound/soc/sof/pm.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Intel Corporation. All rights reserved.
//
//
#include <uapi/sound/sof/tokens.h>
#include <sound/pcm_params.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc3-priv.h"
#include "ops.h"
/* Full volume for default values */
#define VOL_ZERO_DB BIT(VOLUME_FWL)
/* size of tplg ABI in bytes */
#define SOF_IPC3_TPLG_ABI_SIZE 3
struct sof_widget_data {
int ctrl_type;
int ipc_cmd;
void *pdata;
size_t pdata_size;
struct snd_sof_control *control;
};
struct sof_process_types {
const char *name;
enum sof_ipc_process_type type;
enum sof_comp_type comp_type;
};
static const struct sof_process_types sof_process[] = {
{"EQFIR", SOF_PROCESS_EQFIR, SOF_COMP_EQ_FIR},
{"EQIIR", SOF_PROCESS_EQIIR, SOF_COMP_EQ_IIR},
{"KEYWORD_DETECT", SOF_PROCESS_KEYWORD_DETECT, SOF_COMP_KEYWORD_DETECT},
{"KPB", SOF_PROCESS_KPB, SOF_COMP_KPB},
{"CHAN_SELECTOR", SOF_PROCESS_CHAN_SELECTOR, SOF_COMP_SELECTOR},
{"MUX", SOF_PROCESS_MUX, SOF_COMP_MUX},
{"DEMUX", SOF_PROCESS_DEMUX, SOF_COMP_DEMUX},
{"DCBLOCK", SOF_PROCESS_DCBLOCK, SOF_COMP_DCBLOCK},
{"SMART_AMP", SOF_PROCESS_SMART_AMP, SOF_COMP_SMART_AMP},
};
static enum sof_ipc_process_type find_process(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(sof_process); i++) {
if (strcmp(name, sof_process[i].name) == 0)
return sof_process[i].type;
}
return SOF_PROCESS_NONE;
}
static int get_token_process_type(void *elem, void *object, u32 offset)
{
u32 *val = (u32 *)((u8 *)object + offset);
*val = find_process((const char *)elem);
return 0;
}
/* Buffers */
static const struct sof_topology_token buffer_tokens[] = {
{SOF_TKN_BUF_SIZE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_buffer, size)},
{SOF_TKN_BUF_CAPS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_buffer, caps)},
};
/* DAI */
static const struct sof_topology_token dai_tokens[] = {
{SOF_TKN_DAI_TYPE, SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_dai_type,
offsetof(struct sof_ipc_comp_dai, type)},
{SOF_TKN_DAI_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_dai, dai_index)},
{SOF_TKN_DAI_DIRECTION, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_dai, direction)},
};
/* BE DAI link */
static const struct sof_topology_token dai_link_tokens[] = {
{SOF_TKN_DAI_TYPE, SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_dai_type,
offsetof(struct sof_ipc_dai_config, type)},
{SOF_TKN_DAI_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_config, dai_index)},
};
/* scheduling */
static const struct sof_topology_token sched_tokens[] = {
{SOF_TKN_SCHED_PERIOD, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_pipe_new, period)},
{SOF_TKN_SCHED_PRIORITY, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_pipe_new, priority)},
{SOF_TKN_SCHED_MIPS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_pipe_new, period_mips)},
{SOF_TKN_SCHED_CORE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_pipe_new, core)},
{SOF_TKN_SCHED_FRAMES, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_pipe_new, frames_per_sched)},
{SOF_TKN_SCHED_TIME_DOMAIN, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_pipe_new, time_domain)},
};
static const struct sof_topology_token pipeline_tokens[] = {
{SOF_TKN_SCHED_DYNAMIC_PIPELINE, SND_SOC_TPLG_TUPLE_TYPE_BOOL, get_token_u16,
offsetof(struct snd_sof_widget, dynamic_pipeline_widget)},
};
/* volume */
static const struct sof_topology_token volume_tokens[] = {
{SOF_TKN_VOLUME_RAMP_STEP_TYPE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_volume, ramp)},
{SOF_TKN_VOLUME_RAMP_STEP_MS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_volume, initial_ramp)},
};
/* SRC */
static const struct sof_topology_token src_tokens[] = {
{SOF_TKN_SRC_RATE_IN, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_src, source_rate)},
{SOF_TKN_SRC_RATE_OUT, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_src, sink_rate)},
};
/* ASRC */
static const struct sof_topology_token asrc_tokens[] = {
{SOF_TKN_ASRC_RATE_IN, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_asrc, source_rate)},
{SOF_TKN_ASRC_RATE_OUT, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_asrc, sink_rate)},
{SOF_TKN_ASRC_ASYNCHRONOUS_MODE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_asrc, asynchronous_mode)},
{SOF_TKN_ASRC_OPERATION_MODE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_asrc, operation_mode)},
};
/* EFFECT */
static const struct sof_topology_token process_tokens[] = {
{SOF_TKN_PROCESS_TYPE, SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_process_type,
offsetof(struct sof_ipc_comp_process, type)},
};
/* PCM */
static const struct sof_topology_token pcm_tokens[] = {
{SOF_TKN_PCM_DMAC_CONFIG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_host, dmac_config)},
};
/* Generic components */
static const struct sof_topology_token comp_tokens[] = {
{SOF_TKN_COMP_PERIOD_SINK_COUNT, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_config, periods_sink)},
{SOF_TKN_COMP_PERIOD_SOURCE_COUNT, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp_config, periods_source)},
{SOF_TKN_COMP_FORMAT,
SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_comp_format,
offsetof(struct sof_ipc_comp_config, frame_fmt)},
};
/* SSP */
static const struct sof_topology_token ssp_tokens[] = {
{SOF_TKN_INTEL_SSP_CLKS_CONTROL, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_ssp_params, clks_control)},
{SOF_TKN_INTEL_SSP_MCLK_ID, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_ssp_params, mclk_id)},
{SOF_TKN_INTEL_SSP_SAMPLE_BITS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_ssp_params, sample_valid_bits)},
{SOF_TKN_INTEL_SSP_FRAME_PULSE_WIDTH, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_ssp_params, frame_pulse_width)},
{SOF_TKN_INTEL_SSP_QUIRKS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_ssp_params, quirks)},
{SOF_TKN_INTEL_SSP_TDM_PADDING_PER_SLOT, SND_SOC_TPLG_TUPLE_TYPE_BOOL, get_token_u16,
offsetof(struct sof_ipc_dai_ssp_params, tdm_per_slot_padding_flag)},
{SOF_TKN_INTEL_SSP_BCLK_DELAY, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_ssp_params, bclk_delay)},
};
/* ALH */
static const struct sof_topology_token alh_tokens[] = {
{SOF_TKN_INTEL_ALH_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_alh_params, rate)},
{SOF_TKN_INTEL_ALH_CH, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_alh_params, channels)},
};
/* DMIC */
static const struct sof_topology_token dmic_tokens[] = {
{SOF_TKN_INTEL_DMIC_DRIVER_VERSION, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_dmic_params, driver_ipc_version)},
{SOF_TKN_INTEL_DMIC_CLK_MIN, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_dmic_params, pdmclk_min)},
{SOF_TKN_INTEL_DMIC_CLK_MAX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_dmic_params, pdmclk_max)},
{SOF_TKN_INTEL_DMIC_SAMPLE_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_dmic_params, fifo_fs)},
{SOF_TKN_INTEL_DMIC_DUTY_MIN, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_params, duty_min)},
{SOF_TKN_INTEL_DMIC_DUTY_MAX, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_params, duty_max)},
{SOF_TKN_INTEL_DMIC_NUM_PDM_ACTIVE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_dmic_params, num_pdm_active)},
{SOF_TKN_INTEL_DMIC_FIFO_WORD_LENGTH, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_params, fifo_bits)},
{SOF_TKN_INTEL_DMIC_UNMUTE_RAMP_TIME_MS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_dmic_params, unmute_ramp_time)},
};
/* ESAI */
static const struct sof_topology_token esai_tokens[] = {
{SOF_TKN_IMX_ESAI_MCLK_ID, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_esai_params, mclk_id)},
};
/* SAI */
static const struct sof_topology_token sai_tokens[] = {
{SOF_TKN_IMX_SAI_MCLK_ID, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_sai_params, mclk_id)},
};
/*
* DMIC PDM Tokens
* SOF_TKN_INTEL_DMIC_PDM_CTRL_ID should be the first token
* as it increments the index while parsing the array of pdm tokens
* and determines the correct offset
*/
static const struct sof_topology_token dmic_pdm_tokens[] = {
{SOF_TKN_INTEL_DMIC_PDM_CTRL_ID, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, id)},
{SOF_TKN_INTEL_DMIC_PDM_MIC_A_Enable, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, enable_mic_a)},
{SOF_TKN_INTEL_DMIC_PDM_MIC_B_Enable, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, enable_mic_b)},
{SOF_TKN_INTEL_DMIC_PDM_POLARITY_A, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, polarity_mic_a)},
{SOF_TKN_INTEL_DMIC_PDM_POLARITY_B, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, polarity_mic_b)},
{SOF_TKN_INTEL_DMIC_PDM_CLK_EDGE, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, clk_edge)},
{SOF_TKN_INTEL_DMIC_PDM_SKEW, SND_SOC_TPLG_TUPLE_TYPE_SHORT, get_token_u16,
offsetof(struct sof_ipc_dai_dmic_pdm_ctrl, skew)},
};
/* HDA */
static const struct sof_topology_token hda_tokens[] = {
{SOF_TKN_INTEL_HDA_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_hda_params, rate)},
{SOF_TKN_INTEL_HDA_CH, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_hda_params, channels)},
};
/* AFE */
static const struct sof_topology_token afe_tokens[] = {
{SOF_TKN_MEDIATEK_AFE_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_mtk_afe_params, rate)},
{SOF_TKN_MEDIATEK_AFE_CH, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_mtk_afe_params, channels)},
{SOF_TKN_MEDIATEK_AFE_FORMAT, SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_comp_format,
offsetof(struct sof_ipc_dai_mtk_afe_params, format)},
};
/* ACPDMIC */
static const struct sof_topology_token acpdmic_tokens[] = {
{SOF_TKN_AMD_ACPDMIC_RATE,
SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_acpdmic_params, pdm_rate)},
{SOF_TKN_AMD_ACPDMIC_CH,
SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_acpdmic_params, pdm_ch)},
};
/* ACPI2S */
static const struct sof_topology_token acpi2s_tokens[] = {
{SOF_TKN_AMD_ACPI2S_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_acp_params, fsync_rate)},
{SOF_TKN_AMD_ACPI2S_CH, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_acp_params, tdm_slots)},
{SOF_TKN_AMD_ACPI2S_TDM_MODE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_dai_acp_params, tdm_mode)},
};
/* Core tokens */
static const struct sof_topology_token core_tokens[] = {
{SOF_TKN_COMP_CORE_ID, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc_comp, core)},
};
/* Component extended tokens */
static const struct sof_topology_token comp_ext_tokens[] = {
{SOF_TKN_COMP_UUID, SND_SOC_TPLG_TUPLE_TYPE_UUID, get_token_uuid,
offsetof(struct snd_sof_widget, uuid)},
};
static const struct sof_token_info ipc3_token_list[SOF_TOKEN_COUNT] = {
[SOF_PCM_TOKENS] = {"PCM tokens", pcm_tokens, ARRAY_SIZE(pcm_tokens)},
[SOF_PIPELINE_TOKENS] = {"Pipeline tokens", pipeline_tokens, ARRAY_SIZE(pipeline_tokens)},
[SOF_SCHED_TOKENS] = {"Scheduler tokens", sched_tokens, ARRAY_SIZE(sched_tokens)},
[SOF_COMP_TOKENS] = {"Comp tokens", comp_tokens, ARRAY_SIZE(comp_tokens)},
[SOF_CORE_TOKENS] = {"Core tokens", core_tokens, ARRAY_SIZE(core_tokens)},
[SOF_COMP_EXT_TOKENS] = {"AFE tokens", comp_ext_tokens, ARRAY_SIZE(comp_ext_tokens)},
[SOF_BUFFER_TOKENS] = {"Buffer tokens", buffer_tokens, ARRAY_SIZE(buffer_tokens)},
[SOF_VOLUME_TOKENS] = {"Volume tokens", volume_tokens, ARRAY_SIZE(volume_tokens)},
[SOF_SRC_TOKENS] = {"SRC tokens", src_tokens, ARRAY_SIZE(src_tokens)},
[SOF_ASRC_TOKENS] = {"ASRC tokens", asrc_tokens, ARRAY_SIZE(asrc_tokens)},
[SOF_PROCESS_TOKENS] = {"Process tokens", process_tokens, ARRAY_SIZE(process_tokens)},
[SOF_DAI_TOKENS] = {"DAI tokens", dai_tokens, ARRAY_SIZE(dai_tokens)},
[SOF_DAI_LINK_TOKENS] = {"DAI link tokens", dai_link_tokens, ARRAY_SIZE(dai_link_tokens)},
[SOF_HDA_TOKENS] = {"HDA tokens", hda_tokens, ARRAY_SIZE(hda_tokens)},
[SOF_SSP_TOKENS] = {"SSP tokens", ssp_tokens, ARRAY_SIZE(ssp_tokens)},
[SOF_ALH_TOKENS] = {"ALH tokens", alh_tokens, ARRAY_SIZE(alh_tokens)},
[SOF_DMIC_TOKENS] = {"DMIC tokens", dmic_tokens, ARRAY_SIZE(dmic_tokens)},
[SOF_DMIC_PDM_TOKENS] = {"DMIC PDM tokens", dmic_pdm_tokens, ARRAY_SIZE(dmic_pdm_tokens)},
[SOF_ESAI_TOKENS] = {"ESAI tokens", esai_tokens, ARRAY_SIZE(esai_tokens)},
[SOF_SAI_TOKENS] = {"SAI tokens", sai_tokens, ARRAY_SIZE(sai_tokens)},
[SOF_AFE_TOKENS] = {"AFE tokens", afe_tokens, ARRAY_SIZE(afe_tokens)},
[SOF_ACPDMIC_TOKENS] = {"ACPDMIC tokens", acpdmic_tokens, ARRAY_SIZE(acpdmic_tokens)},
[SOF_ACPI2S_TOKENS] = {"ACPI2S tokens", acpi2s_tokens, ARRAY_SIZE(acpi2s_tokens)},
};
/**
* sof_comp_alloc - allocate and initialize buffer for a new component
* @swidget: pointer to struct snd_sof_widget containing extended data
* @ipc_size: IPC payload size that will be updated depending on valid
* extended data.
* @index: ID of the pipeline the component belongs to
*
* Return: The pointer to the new allocated component, NULL if failed.
*/
static void *sof_comp_alloc(struct snd_sof_widget *swidget, size_t *ipc_size,
int index)
{
struct sof_ipc_comp *comp;
size_t total_size = *ipc_size;
size_t ext_size = sizeof(swidget->uuid);
/* only non-zero UUID is valid */
if (!guid_is_null(&swidget->uuid))
total_size += ext_size;
comp = kzalloc(total_size, GFP_KERNEL);
if (!comp)
return NULL;
/* configure comp new IPC message */
comp->hdr.size = total_size;
comp->hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_COMP_NEW;
comp->id = swidget->comp_id;
comp->pipeline_id = index;
comp->core = swidget->core;
/* handle the extended data if needed */
if (total_size > *ipc_size) {
/* append extended data to the end of the component */
memcpy((u8 *)comp + *ipc_size, &swidget->uuid, ext_size);
comp->ext_data_length = ext_size;
}
/* update ipc_size and return */
*ipc_size = total_size;
return comp;
}
static void sof_dbg_comp_config(struct snd_soc_component *scomp, struct sof_ipc_comp_config *config)
{
dev_dbg(scomp->dev, " config: periods snk %d src %d fmt %d\n",
config->periods_sink, config->periods_source,
config->frame_fmt);
}
static int sof_ipc3_widget_setup_comp_host(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_host *host;
size_t ipc_size = sizeof(*host);
int ret;
host = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!host)
return -ENOMEM;
swidget->private = host;
/* configure host comp IPC message */
host->comp.type = SOF_COMP_HOST;
host->config.hdr.size = sizeof(host->config);
if (swidget->id == snd_soc_dapm_aif_out)
host->direction = SOF_IPC_STREAM_CAPTURE;
else
host->direction = SOF_IPC_STREAM_PLAYBACK;
/* parse one set of pcm_tokens */
ret = sof_update_ipc_object(scomp, host, SOF_PCM_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*host), 1);
if (ret < 0)
goto err;
/* parse one set of comp_tokens */
ret = sof_update_ipc_object(scomp, &host->config, SOF_COMP_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(host->config), 1);
if (ret < 0)
goto err;
dev_dbg(scomp->dev, "loaded host %s\n", swidget->widget->name);
sof_dbg_comp_config(scomp, &host->config);
return 0;
err:
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
static void sof_ipc3_widget_free_comp(struct snd_sof_widget *swidget)
{
kfree(swidget->private);
}
static int sof_ipc3_widget_setup_comp_tone(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_tone *tone;
size_t ipc_size = sizeof(*tone);
int ret;
tone = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!tone)
return -ENOMEM;
swidget->private = tone;
/* configure siggen IPC message */
tone->comp.type = SOF_COMP_TONE;
tone->config.hdr.size = sizeof(tone->config);
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &tone->config, SOF_COMP_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(tone->config), 1);
if (ret < 0) {
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
dev_dbg(scomp->dev, "tone %s: frequency %d amplitude %d\n",
swidget->widget->name, tone->frequency, tone->amplitude);
sof_dbg_comp_config(scomp, &tone->config);
return 0;
}
static int sof_ipc3_widget_setup_comp_mixer(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_mixer *mixer;
size_t ipc_size = sizeof(*mixer);
int ret;
mixer = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!mixer)
return -ENOMEM;
swidget->private = mixer;
/* configure mixer IPC message */
mixer->comp.type = SOF_COMP_MIXER;
mixer->config.hdr.size = sizeof(mixer->config);
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &mixer->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples,
sizeof(mixer->config), 1);
if (ret < 0) {
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
dev_dbg(scomp->dev, "loaded mixer %s\n", swidget->widget->name);
sof_dbg_comp_config(scomp, &mixer->config);
return 0;
}
static int sof_ipc3_widget_setup_comp_pipeline(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_pipe_new *pipeline;
struct snd_sof_widget *comp_swidget;
int ret;
pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL);
if (!pipeline)
return -ENOMEM;
/* configure pipeline IPC message */
pipeline->hdr.size = sizeof(*pipeline);
pipeline->hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_PIPE_NEW;
pipeline->pipeline_id = swidget->pipeline_id;
pipeline->comp_id = swidget->comp_id;
swidget->private = pipeline;
/* component at start of pipeline is our stream id */
comp_swidget = snd_sof_find_swidget(scomp, swidget->widget->sname);
if (!comp_swidget) {
dev_err(scomp->dev, "scheduler %s refers to non existent widget %s\n",
swidget->widget->name, swidget->widget->sname);
ret = -EINVAL;
goto err;
}
pipeline->sched_id = comp_swidget->comp_id;
/* parse one set of scheduler tokens */
ret = sof_update_ipc_object(scomp, pipeline, SOF_SCHED_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*pipeline), 1);
if (ret < 0)
goto err;
/* parse one set of pipeline tokens */
ret = sof_update_ipc_object(scomp, swidget, SOF_PIPELINE_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*swidget), 1);
if (ret < 0)
goto err;
if (sof_debug_check_flag(SOF_DBG_DISABLE_MULTICORE))
pipeline->core = SOF_DSP_PRIMARY_CORE;
if (sof_debug_check_flag(SOF_DBG_DYNAMIC_PIPELINES_OVERRIDE))
swidget->dynamic_pipeline_widget =
sof_debug_check_flag(SOF_DBG_DYNAMIC_PIPELINES_ENABLE);
dev_dbg(scomp->dev, "pipeline %s: period %d pri %d mips %d core %d frames %d dynamic %d\n",
swidget->widget->name, pipeline->period, pipeline->priority,
pipeline->period_mips, pipeline->core, pipeline->frames_per_sched,
swidget->dynamic_pipeline_widget);
swidget->core = pipeline->core;
return 0;
err:
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
static int sof_ipc3_widget_setup_comp_buffer(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_buffer *buffer;
int ret;
buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
if (!buffer)
return -ENOMEM;
swidget->private = buffer;
/* configure dai IPC message */
buffer->comp.hdr.size = sizeof(*buffer);
buffer->comp.hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_BUFFER_NEW;
buffer->comp.id = swidget->comp_id;
buffer->comp.type = SOF_COMP_BUFFER;
buffer->comp.pipeline_id = swidget->pipeline_id;
buffer->comp.core = swidget->core;
/* parse one set of buffer tokens */
ret = sof_update_ipc_object(scomp, buffer, SOF_BUFFER_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*buffer), 1);
if (ret < 0) {
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
dev_dbg(scomp->dev, "buffer %s: size %d caps 0x%x\n",
swidget->widget->name, buffer->size, buffer->caps);
return 0;
}
static int sof_ipc3_widget_setup_comp_src(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_src *src;
size_t ipc_size = sizeof(*src);
int ret;
src = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!src)
return -ENOMEM;
swidget->private = src;
/* configure src IPC message */
src->comp.type = SOF_COMP_SRC;
src->config.hdr.size = sizeof(src->config);
/* parse one set of src tokens */
ret = sof_update_ipc_object(scomp, src, SOF_SRC_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*src), 1);
if (ret < 0)
goto err;
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &src->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples, sizeof(src->config), 1);
if (ret < 0)
goto err;
dev_dbg(scomp->dev, "src %s: source rate %d sink rate %d\n",
swidget->widget->name, src->source_rate, src->sink_rate);
sof_dbg_comp_config(scomp, &src->config);
return 0;
err:
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
static int sof_ipc3_widget_setup_comp_asrc(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_asrc *asrc;
size_t ipc_size = sizeof(*asrc);
int ret;
asrc = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!asrc)
return -ENOMEM;
swidget->private = asrc;
/* configure ASRC IPC message */
asrc->comp.type = SOF_COMP_ASRC;
asrc->config.hdr.size = sizeof(asrc->config);
/* parse one set of asrc tokens */
ret = sof_update_ipc_object(scomp, asrc, SOF_ASRC_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*asrc), 1);
if (ret < 0)
goto err;
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &asrc->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples, sizeof(asrc->config), 1);
if (ret < 0)
goto err;
dev_dbg(scomp->dev, "asrc %s: source rate %d sink rate %d asynch %d operation %d\n",
swidget->widget->name, asrc->source_rate, asrc->sink_rate,
asrc->asynchronous_mode, asrc->operation_mode);
sof_dbg_comp_config(scomp, &asrc->config);
return 0;
err:
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
/*
* Mux topology
*/
static int sof_ipc3_widget_setup_comp_mux(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_mux *mux;
size_t ipc_size = sizeof(*mux);
int ret;
mux = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!mux)
return -ENOMEM;
swidget->private = mux;
/* configure mux IPC message */
mux->comp.type = SOF_COMP_MUX;
mux->config.hdr.size = sizeof(mux->config);
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &mux->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples, sizeof(mux->config), 1);
if (ret < 0) {
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
dev_dbg(scomp->dev, "loaded mux %s\n", swidget->widget->name);
sof_dbg_comp_config(scomp, &mux->config);
return 0;
}
/*
* PGA Topology
*/
static int sof_ipc3_widget_setup_comp_pga(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc_comp_volume *volume;
struct snd_sof_control *scontrol;
size_t ipc_size = sizeof(*volume);
int min_step, max_step;
int ret;
volume = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!volume)
return -ENOMEM;
swidget->private = volume;
/* configure volume IPC message */
volume->comp.type = SOF_COMP_VOLUME;
volume->config.hdr.size = sizeof(volume->config);
/* parse one set of volume tokens */
ret = sof_update_ipc_object(scomp, volume, SOF_VOLUME_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*volume), 1);
if (ret < 0)
goto err;
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &volume->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples,
sizeof(volume->config), 1);
if (ret < 0)
goto err;
dev_dbg(scomp->dev, "loaded PGA %s\n", swidget->widget->name);
sof_dbg_comp_config(scomp, &volume->config);
list_for_each_entry(scontrol, &sdev->kcontrol_list, list) {
if (scontrol->comp_id == swidget->comp_id &&
scontrol->volume_table) {
min_step = scontrol->min_volume_step;
max_step = scontrol->max_volume_step;
volume->min_value = scontrol->volume_table[min_step];
volume->max_value = scontrol->volume_table[max_step];
volume->channels = scontrol->num_channels;
break;
}
}
return 0;
err:
kfree(swidget->private);
swidget->private = NULL;
return ret;
}
static int sof_get_control_data(struct snd_soc_component *scomp,
struct snd_soc_dapm_widget *widget,
struct sof_widget_data *wdata, size_t *size)
{
const struct snd_kcontrol_new *kc;
struct sof_ipc_ctrl_data *cdata;
struct soc_mixer_control *sm;
struct soc_bytes_ext *sbe;
struct soc_enum *se;
int i;
*size = 0;
for (i = 0; i < widget->num_kcontrols; i++) {
kc = &widget->kcontrol_news[i];
switch (widget->dobj.widget.kcontrol_type[i]) {
case SND_SOC_TPLG_TYPE_MIXER:
sm = (struct soc_mixer_control *)kc->private_value;
wdata[i].control = sm->dobj.private;
break;
case SND_SOC_TPLG_TYPE_BYTES:
sbe = (struct soc_bytes_ext *)kc->private_value;
wdata[i].control = sbe->dobj.private;
break;
case SND_SOC_TPLG_TYPE_ENUM:
se = (struct soc_enum *)kc->private_value;
wdata[i].control = se->dobj.private;
break;
default:
dev_err(scomp->dev, "Unknown kcontrol type %u in widget %s\n",
widget->dobj.widget.kcontrol_type[i], widget->name);
return -EINVAL;
}
if (!wdata[i].control) {
dev_err(scomp->dev, "No scontrol for widget %s\n", widget->name);
return -EINVAL;
}
cdata = wdata[i].control->ipc_control_data;
if (widget->dobj.widget.kcontrol_type[i] == SND_SOC_TPLG_TYPE_BYTES) {
/* make sure data is valid - data can be updated at runtime */
if (cdata->data->magic != SOF_ABI_MAGIC)
return -EINVAL;
wdata[i].pdata = cdata->data->data;
wdata[i].pdata_size = cdata->data->size;
} else {
/* points to the control data union */
wdata[i].pdata = cdata->chanv;
/*
* wdata[i].control->size is calculated with struct_size
* and includes the size of struct sof_ipc_ctrl_data
*/
wdata[i].pdata_size = wdata[i].control->size -
sizeof(struct sof_ipc_ctrl_data);
}
*size += wdata[i].pdata_size;
/* get data type */
switch (cdata->cmd) {
case SOF_CTRL_CMD_VOLUME:
case SOF_CTRL_CMD_ENUM:
case SOF_CTRL_CMD_SWITCH:
wdata[i].ipc_cmd = SOF_IPC_COMP_SET_VALUE;
wdata[i].ctrl_type = SOF_CTRL_TYPE_VALUE_CHAN_SET;
break;
case SOF_CTRL_CMD_BINARY:
wdata[i].ipc_cmd = SOF_IPC_COMP_SET_DATA;
wdata[i].ctrl_type = SOF_CTRL_TYPE_DATA_SET;
break;
default:
break;
}
}
return 0;
}
static int sof_process_load(struct snd_soc_component *scomp,
struct snd_sof_widget *swidget, int type)
{
struct snd_soc_dapm_widget *widget = swidget->widget;
struct sof_ipc_comp_process *process;
struct sof_widget_data *wdata = NULL;
size_t ipc_data_size = 0;
size_t ipc_size;
int offset = 0;
int ret;
int i;
/* allocate struct for widget control data sizes and types */
if (widget->num_kcontrols) {
wdata = kcalloc(widget->num_kcontrols, sizeof(*wdata), GFP_KERNEL);
if (!wdata)
return -ENOMEM;
/* get possible component controls and get size of all pdata */
ret = sof_get_control_data(scomp, widget, wdata, &ipc_data_size);
if (ret < 0)
goto out;
}
ipc_size = sizeof(struct sof_ipc_comp_process) + ipc_data_size;
/* we are exceeding max ipc size, config needs to be sent separately */
if (ipc_size > SOF_IPC_MSG_MAX_SIZE) {
ipc_size -= ipc_data_size;
ipc_data_size = 0;
}
process = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!process) {
ret = -ENOMEM;
goto out;
}
swidget->private = process;
/* configure iir IPC message */
process->comp.type = type;
process->config.hdr.size = sizeof(process->config);
/* parse one set of comp tokens */
ret = sof_update_ipc_object(scomp, &process->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples,
sizeof(process->config), 1);
if (ret < 0)
goto err;
dev_dbg(scomp->dev, "loaded process %s\n", swidget->widget->name);
sof_dbg_comp_config(scomp, &process->config);
/*
* found private data in control, so copy it.
* get possible component controls - get size of all pdata,
* then memcpy with headers
*/
if (ipc_data_size) {
for (i = 0; i < widget->num_kcontrols; i++) {
if (!wdata[i].pdata_size)
continue;
memcpy(&process->data[offset], wdata[i].pdata,
wdata[i].pdata_size);
offset += wdata[i].pdata_size;
}
}
process->size = ipc_data_size;
kfree(wdata);
return 0;
err:
kfree(swidget->private);
swidget->private = NULL;
out:
kfree(wdata);
return ret;
}
static enum sof_comp_type find_process_comp_type(enum sof_ipc_process_type type)
{
int i;
for (i = 0; i < ARRAY_SIZE(sof_process); i++) {
if (sof_process[i].type == type)
return sof_process[i].comp_type;
}
return SOF_COMP_NONE;
}
/*
* Processing Component Topology - can be "effect", "codec", or general
* "processing".
*/
static int sof_widget_update_ipc_comp_process(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc_comp_process config;
int ret;
memset(&config, 0, sizeof(config));
config.comp.core = swidget->core;
/* parse one set of process tokens */
ret = sof_update_ipc_object(scomp, &config, SOF_PROCESS_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(config), 1);
if (ret < 0)
return ret;
/* now load process specific data and send IPC */
return sof_process_load(scomp, swidget, find_process_comp_type(config.type));
}
static int sof_link_hda_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* init IPC */
memset(&config->hda, 0, sizeof(config->hda));
config->hdr.size = size;
/* parse one set of HDA tokens */
ret = sof_update_ipc_object(scomp, &config->hda, SOF_HDA_TOKENS, slink->tuples,
slink->num_tuples, size, 1);
if (ret < 0)
return ret;
dev_dbg(scomp->dev, "HDA config rate %d channels %d\n",
config->hda.rate, config->hda.channels);
config->hda.link_dma_ch = DMA_CHAN_INVALID;
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static void sof_dai_set_format(struct snd_soc_tplg_hw_config *hw_config,
struct sof_ipc_dai_config *config)
{
/* clock directions wrt codec */
config->format &= ~SOF_DAI_FMT_CLOCK_PROVIDER_MASK;
if (hw_config->bclk_provider == SND_SOC_TPLG_BCLK_CP) {
/* codec is bclk provider */
if (hw_config->fsync_provider == SND_SOC_TPLG_FSYNC_CP)
config->format |= SOF_DAI_FMT_CBP_CFP;
else
config->format |= SOF_DAI_FMT_CBP_CFC;
} else {
/* codec is bclk consumer */
if (hw_config->fsync_provider == SND_SOC_TPLG_FSYNC_CP)
config->format |= SOF_DAI_FMT_CBC_CFP;
else
config->format |= SOF_DAI_FMT_CBC_CFC;
}
/* inverted clocks ? */
config->format &= ~SOF_DAI_FMT_INV_MASK;
if (hw_config->invert_bclk) {
if (hw_config->invert_fsync)
config->format |= SOF_DAI_FMT_IB_IF;
else
config->format |= SOF_DAI_FMT_IB_NF;
} else {
if (hw_config->invert_fsync)
config->format |= SOF_DAI_FMT_NB_IF;
else
config->format |= SOF_DAI_FMT_NB_NF;
}
}
static int sof_link_sai_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* handle master/slave and inverted clocks */
sof_dai_set_format(hw_config, config);
/* init IPC */
memset(&config->sai, 0, sizeof(config->sai));
config->hdr.size = size;
/* parse one set of SAI tokens */
ret = sof_update_ipc_object(scomp, &config->sai, SOF_SAI_TOKENS, slink->tuples,
slink->num_tuples, size, 1);
if (ret < 0)
return ret;
config->sai.mclk_rate = le32_to_cpu(hw_config->mclk_rate);
config->sai.bclk_rate = le32_to_cpu(hw_config->bclk_rate);
config->sai.fsync_rate = le32_to_cpu(hw_config->fsync_rate);
config->sai.mclk_direction = hw_config->mclk_direction;
config->sai.tdm_slots = le32_to_cpu(hw_config->tdm_slots);
config->sai.tdm_slot_width = le32_to_cpu(hw_config->tdm_slot_width);
config->sai.rx_slots = le32_to_cpu(hw_config->rx_slots);
config->sai.tx_slots = le32_to_cpu(hw_config->tx_slots);
dev_info(scomp->dev,
"tplg: config SAI%d fmt 0x%x mclk %d width %d slots %d mclk id %d\n",
config->dai_index, config->format,
config->sai.mclk_rate, config->sai.tdm_slot_width,
config->sai.tdm_slots, config->sai.mclk_id);
if (config->sai.tdm_slots < 1 || config->sai.tdm_slots > 8) {
dev_err(scomp->dev, "Invalid channel count for SAI%d\n", config->dai_index);
return -EINVAL;
}
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_esai_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* handle master/slave and inverted clocks */
sof_dai_set_format(hw_config, config);
/* init IPC */
memset(&config->esai, 0, sizeof(config->esai));
config->hdr.size = size;
/* parse one set of ESAI tokens */
ret = sof_update_ipc_object(scomp, &config->esai, SOF_ESAI_TOKENS, slink->tuples,
slink->num_tuples, size, 1);
if (ret < 0)
return ret;
config->esai.mclk_rate = le32_to_cpu(hw_config->mclk_rate);
config->esai.bclk_rate = le32_to_cpu(hw_config->bclk_rate);
config->esai.fsync_rate = le32_to_cpu(hw_config->fsync_rate);
config->esai.mclk_direction = hw_config->mclk_direction;
config->esai.tdm_slots = le32_to_cpu(hw_config->tdm_slots);
config->esai.tdm_slot_width = le32_to_cpu(hw_config->tdm_slot_width);
config->esai.rx_slots = le32_to_cpu(hw_config->rx_slots);
config->esai.tx_slots = le32_to_cpu(hw_config->tx_slots);
dev_info(scomp->dev,
"tplg: config ESAI%d fmt 0x%x mclk %d width %d slots %d mclk id %d\n",
config->dai_index, config->format,
config->esai.mclk_rate, config->esai.tdm_slot_width,
config->esai.tdm_slots, config->esai.mclk_id);
if (config->esai.tdm_slots < 1 || config->esai.tdm_slots > 8) {
dev_err(scomp->dev, "Invalid channel count for ESAI%d\n", config->dai_index);
return -EINVAL;
}
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_acp_dmic_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* handle master/slave and inverted clocks */
sof_dai_set_format(hw_config, config);
config->hdr.size = size;
/* parse the required set of ACPDMIC tokens based on num_hw_cfgs */
ret = sof_update_ipc_object(scomp, &config->acpdmic, SOF_ACPDMIC_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
dev_info(scomp->dev, "ACP_DMIC config ACP%d channel %d rate %d\n",
config->dai_index, config->acpdmic.pdm_ch,
config->acpdmic.pdm_rate);
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_acp_bt_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
/* handle master/slave and inverted clocks */
sof_dai_set_format(hw_config, config);
/* init IPC */
memset(&config->acpbt, 0, sizeof(config->acpbt));
config->hdr.size = size;
config->acpbt.fsync_rate = le32_to_cpu(hw_config->fsync_rate);
config->acpbt.tdm_slots = le32_to_cpu(hw_config->tdm_slots);
dev_info(scomp->dev, "ACP_BT config ACP%d channel %d rate %d\n",
config->dai_index, config->acpbt.tdm_slots,
config->acpbt.fsync_rate);
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_acp_sp_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* handle master/slave and inverted clocks */
sof_dai_set_format(hw_config, config);
/* init IPC */
memset(&config->acpsp, 0, sizeof(config->acpsp));
config->hdr.size = size;
ret = sof_update_ipc_object(scomp, &config->acpsp, SOF_ACPI2S_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
dev_info(scomp->dev, "ACP_SP config ACP%d channel %d rate %d tdm_mode %d\n",
config->dai_index, config->acpsp.tdm_slots,
config->acpsp.fsync_rate, config->acpsp.tdm_mode);
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_acp_hs_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* Configures the DAI hardware format and inverted clocks */
sof_dai_set_format(hw_config, config);
/* init IPC */
memset(&config->acphs, 0, sizeof(config->acphs));
config->hdr.size = size;
ret = sof_update_ipc_object(scomp, &config->acphs, SOF_ACPI2S_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
dev_info(scomp->dev, "ACP_HS config ACP%d channel %d rate %d tdm_mode %d\n",
config->dai_index, config->acphs.tdm_slots,
config->acphs.fsync_rate, config->acphs.tdm_mode);
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_afe_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
config->hdr.size = size;
/* parse the required set of AFE tokens based on num_hw_cfgs */
ret = sof_update_ipc_object(scomp, &config->afe, SOF_AFE_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
dev_dbg(scomp->dev, "AFE config rate %d channels %d format:%d\n",
config->afe.rate, config->afe.channels, config->afe.format);
config->afe.stream_id = DMA_CHAN_INVALID;
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_ssp_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_soc_tplg_hw_config *hw_config = slink->hw_configs;
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int current_config = 0;
int i, ret;
/*
* Parse common data, we should have 1 common data per hw_config.
*/
ret = sof_update_ipc_object(scomp, &config->ssp, SOF_SSP_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
/* process all possible hw configs */
for (i = 0; i < slink->num_hw_configs; i++) {
if (le32_to_cpu(hw_config[i].id) == slink->default_hw_cfg_id)
current_config = i;
/* handle master/slave and inverted clocks */
sof_dai_set_format(&hw_config[i], &config[i]);
config[i].hdr.size = size;
if (sdev->mclk_id_override) {
dev_dbg(scomp->dev, "tplg: overriding topology mclk_id %d by quirk %d\n",
config[i].ssp.mclk_id, sdev->mclk_id_quirk);
config[i].ssp.mclk_id = sdev->mclk_id_quirk;
}
/* copy differentiating hw configs to ipc structs */
config[i].ssp.mclk_rate = le32_to_cpu(hw_config[i].mclk_rate);
config[i].ssp.bclk_rate = le32_to_cpu(hw_config[i].bclk_rate);
config[i].ssp.fsync_rate = le32_to_cpu(hw_config[i].fsync_rate);
config[i].ssp.tdm_slots = le32_to_cpu(hw_config[i].tdm_slots);
config[i].ssp.tdm_slot_width = le32_to_cpu(hw_config[i].tdm_slot_width);
config[i].ssp.mclk_direction = hw_config[i].mclk_direction;
config[i].ssp.rx_slots = le32_to_cpu(hw_config[i].rx_slots);
config[i].ssp.tx_slots = le32_to_cpu(hw_config[i].tx_slots);
dev_dbg(scomp->dev, "tplg: config SSP%d fmt %#x mclk %d bclk %d fclk %d width (%d)%d slots %d mclk id %d quirks %d clks_control %#x\n",
config[i].dai_index, config[i].format,
config[i].ssp.mclk_rate, config[i].ssp.bclk_rate,
config[i].ssp.fsync_rate, config[i].ssp.sample_valid_bits,
config[i].ssp.tdm_slot_width, config[i].ssp.tdm_slots,
config[i].ssp.mclk_id, config[i].ssp.quirks, config[i].ssp.clks_control);
/* validate SSP fsync rate and channel count */
if (config[i].ssp.fsync_rate < 8000 || config[i].ssp.fsync_rate > 192000) {
dev_err(scomp->dev, "Invalid fsync rate for SSP%d\n", config[i].dai_index);
return -EINVAL;
}
if (config[i].ssp.tdm_slots < 1 || config[i].ssp.tdm_slots > 8) {
dev_err(scomp->dev, "Invalid channel count for SSP%d\n",
config[i].dai_index);
return -EINVAL;
}
}
dai->number_configs = slink->num_hw_configs;
dai->current_config = current_config;
private->dai_config = kmemdup(config, size * slink->num_hw_configs, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_dmic_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_dai_private_data *private = dai->private;
struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
struct sof_ipc_fw_version *v = &ready->version;
size_t size = sizeof(*config);
int i, ret;
/* Ensure the entire DMIC config struct is zeros */
memset(&config->dmic, 0, sizeof(config->dmic));
/* parse the required set of DMIC tokens based on num_hw_cfgs */
ret = sof_update_ipc_object(scomp, &config->dmic, SOF_DMIC_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
/* parse the required set of DMIC PDM tokens based on number of active PDM's */
ret = sof_update_ipc_object(scomp, &config->dmic.pdm[0], SOF_DMIC_PDM_TOKENS,
slink->tuples, slink->num_tuples,
sizeof(struct sof_ipc_dai_dmic_pdm_ctrl),
config->dmic.num_pdm_active);
if (ret < 0)
return ret;
/* set IPC header size */
config->hdr.size = size;
/* debug messages */
dev_dbg(scomp->dev, "tplg: config DMIC%d driver version %d\n",
config->dai_index, config->dmic.driver_ipc_version);
dev_dbg(scomp->dev, "pdmclk_min %d pdm_clkmax %d duty_min %d\n",
config->dmic.pdmclk_min, config->dmic.pdmclk_max,
config->dmic.duty_min);
dev_dbg(scomp->dev, "duty_max %d fifo_fs %d num_pdms active %d\n",
config->dmic.duty_max, config->dmic.fifo_fs,
config->dmic.num_pdm_active);
dev_dbg(scomp->dev, "fifo word length %d\n", config->dmic.fifo_bits);
for (i = 0; i < config->dmic.num_pdm_active; i++) {
dev_dbg(scomp->dev, "pdm %d mic a %d mic b %d\n",
config->dmic.pdm[i].id,
config->dmic.pdm[i].enable_mic_a,
config->dmic.pdm[i].enable_mic_b);
dev_dbg(scomp->dev, "pdm %d polarity a %d polarity b %d\n",
config->dmic.pdm[i].id,
config->dmic.pdm[i].polarity_mic_a,
config->dmic.pdm[i].polarity_mic_b);
dev_dbg(scomp->dev, "pdm %d clk_edge %d skew %d\n",
config->dmic.pdm[i].id,
config->dmic.pdm[i].clk_edge,
config->dmic.pdm[i].skew);
}
/*
* this takes care of backwards compatible handling of fifo_bits_b.
* It is deprecated since firmware ABI version 3.0.1.
*/
if (SOF_ABI_VER(v->major, v->minor, v->micro) < SOF_ABI_VER(3, 0, 1))
config->dmic.fifo_bits_b = config->dmic.fifo_bits;
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_link_alh_load(struct snd_soc_component *scomp, struct snd_sof_dai_link *slink,
struct sof_ipc_dai_config *config, struct snd_sof_dai *dai)
{
struct sof_dai_private_data *private = dai->private;
u32 size = sizeof(*config);
int ret;
/* parse the required set of ALH tokens based on num_hw_cfgs */
ret = sof_update_ipc_object(scomp, &config->alh, SOF_ALH_TOKENS, slink->tuples,
slink->num_tuples, size, slink->num_hw_configs);
if (ret < 0)
return ret;
/* init IPC */
config->hdr.size = size;
/* set config for all DAI's with name matching the link name */
dai->number_configs = 1;
dai->current_config = 0;
private->dai_config = kmemdup(config, size, GFP_KERNEL);
if (!private->dai_config)
return -ENOMEM;
return 0;
}
static int sof_ipc3_widget_setup_comp_dai(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_dai *dai = swidget->private;
struct sof_dai_private_data *private;
struct sof_ipc_comp_dai *comp_dai;
size_t ipc_size = sizeof(*comp_dai);
struct sof_ipc_dai_config *config;
struct snd_sof_dai_link *slink;
int ret;
private = kzalloc(sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
dai->private = private;
private->comp_dai = sof_comp_alloc(swidget, &ipc_size, swidget->pipeline_id);
if (!private->comp_dai) {
ret = -ENOMEM;
goto free;
}
/* configure dai IPC message */
comp_dai = private->comp_dai;
comp_dai->comp.type = SOF_COMP_DAI;
comp_dai->config.hdr.size = sizeof(comp_dai->config);
/* parse one set of DAI tokens */
ret = sof_update_ipc_object(scomp, comp_dai, SOF_DAI_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*comp_dai), 1);
if (ret < 0)
goto free;
/* update comp_tokens */
ret = sof_update_ipc_object(scomp, &comp_dai->config, SOF_COMP_TOKENS,
swidget->tuples, swidget->num_tuples,
sizeof(comp_dai->config), 1);
if (ret < 0)
goto free;
dev_dbg(scomp->dev, "dai %s: type %d index %d\n",
swidget->widget->name, comp_dai->type, comp_dai->dai_index);
sof_dbg_comp_config(scomp, &comp_dai->config);
/* now update DAI config */
list_for_each_entry(slink, &sdev->dai_link_list, list) {
struct sof_ipc_dai_config common_config;
int i;
if (strcmp(slink->link->name, dai->name))
continue;
/* Reserve memory for all hw configs, eventually freed by widget */
config = kcalloc(slink->num_hw_configs, sizeof(*config), GFP_KERNEL);
if (!config) {
ret = -ENOMEM;
goto free_comp;
}
/* parse one set of DAI link tokens */
ret = sof_update_ipc_object(scomp, &common_config, SOF_DAI_LINK_TOKENS,
slink->tuples, slink->num_tuples,
sizeof(common_config), 1);
if (ret < 0)
goto free_config;
for (i = 0; i < slink->num_hw_configs; i++) {
config[i].hdr.cmd = SOF_IPC_GLB_DAI_MSG | SOF_IPC_DAI_CONFIG;
config[i].format = le32_to_cpu(slink->hw_configs[i].fmt);
config[i].type = common_config.type;
config[i].dai_index = comp_dai->dai_index;
}
switch (common_config.type) {
case SOF_DAI_INTEL_SSP:
ret = sof_link_ssp_load(scomp, slink, config, dai);
break;
case SOF_DAI_INTEL_DMIC:
ret = sof_link_dmic_load(scomp, slink, config, dai);
break;
case SOF_DAI_INTEL_HDA:
ret = sof_link_hda_load(scomp, slink, config, dai);
break;
case SOF_DAI_INTEL_ALH:
ret = sof_link_alh_load(scomp, slink, config, dai);
break;
case SOF_DAI_IMX_SAI:
ret = sof_link_sai_load(scomp, slink, config, dai);
break;
case SOF_DAI_IMX_ESAI:
ret = sof_link_esai_load(scomp, slink, config, dai);
break;
case SOF_DAI_AMD_BT:
ret = sof_link_acp_bt_load(scomp, slink, config, dai);
break;
case SOF_DAI_AMD_SP:
case SOF_DAI_AMD_SP_VIRTUAL:
ret = sof_link_acp_sp_load(scomp, slink, config, dai);
break;
case SOF_DAI_AMD_HS:
case SOF_DAI_AMD_HS_VIRTUAL:
ret = sof_link_acp_hs_load(scomp, slink, config, dai);
break;
case SOF_DAI_AMD_DMIC:
ret = sof_link_acp_dmic_load(scomp, slink, config, dai);
break;
case SOF_DAI_MEDIATEK_AFE:
ret = sof_link_afe_load(scomp, slink, config, dai);
break;
default:
break;
}
if (ret < 0) {
dev_err(scomp->dev, "failed to load config for dai %s\n", dai->name);
goto free_config;
}
kfree(config);
}
return 0;
free_config:
kfree(config);
free_comp:
kfree(comp_dai);
free:
kfree(private);
dai->private = NULL;
return ret;
}
static void sof_ipc3_widget_free_comp_dai(struct snd_sof_widget *swidget)
{
switch (swidget->id) {
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
{
struct snd_sof_dai *dai = swidget->private;
struct sof_dai_private_data *dai_data;
if (!dai)
return;
dai_data = dai->private;
if (dai_data) {
kfree(dai_data->comp_dai);
kfree(dai_data->dai_config);
kfree(dai_data);
}
kfree(dai);
break;
}
default:
break;
}
}
static int sof_ipc3_route_setup(struct snd_sof_dev *sdev, struct snd_sof_route *sroute)
{
struct sof_ipc_pipe_comp_connect connect;
int ret;
connect.hdr.size = sizeof(connect);
connect.hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_COMP_CONNECT;
connect.source_id = sroute->src_widget->comp_id;
connect.sink_id = sroute->sink_widget->comp_id;
dev_dbg(sdev->dev, "setting up route %s -> %s\n",
sroute->src_widget->widget->name,
sroute->sink_widget->widget->name);
/* send ipc */
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &connect, sizeof(connect));
if (ret < 0)
dev_err(sdev->dev, "%s: route %s -> %s failed\n", __func__,
sroute->src_widget->widget->name, sroute->sink_widget->widget->name);
return ret;
}
static int sof_ipc3_control_load_bytes(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
struct sof_ipc_ctrl_data *cdata;
size_t priv_size_check;
int ret;
if (scontrol->max_size < (sizeof(*cdata) + sizeof(struct sof_abi_hdr))) {
dev_err(sdev->dev, "%s: insufficient size for a bytes control: %zu.\n",
__func__, scontrol->max_size);
return -EINVAL;
}
if (scontrol->priv_size > scontrol->max_size - sizeof(*cdata)) {
dev_err(sdev->dev,
"%s: bytes data size %zu exceeds max %zu.\n", __func__,
scontrol->priv_size, scontrol->max_size - sizeof(*cdata));
return -EINVAL;
}
scontrol->ipc_control_data = kzalloc(scontrol->max_size, GFP_KERNEL);
if (!scontrol->ipc_control_data)
return -ENOMEM;
scontrol->size = sizeof(struct sof_ipc_ctrl_data) + scontrol->priv_size;
cdata = scontrol->ipc_control_data;
cdata->cmd = SOF_CTRL_CMD_BINARY;
cdata->index = scontrol->index;
if (scontrol->priv_size > 0) {
memcpy(cdata->data, scontrol->priv, scontrol->priv_size);
kfree(scontrol->priv);
scontrol->priv = NULL;
if (cdata->data->magic != SOF_ABI_MAGIC) {
dev_err(sdev->dev, "Wrong ABI magic 0x%08x.\n", cdata->data->magic);
ret = -EINVAL;
goto err;
}
if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, cdata->data->abi)) {
dev_err(sdev->dev, "Incompatible ABI version 0x%08x.\n",
cdata->data->abi);
ret = -EINVAL;
goto err;
}
priv_size_check = cdata->data->size + sizeof(struct sof_abi_hdr);
if (priv_size_check != scontrol->priv_size) {
dev_err(sdev->dev, "Conflict in bytes (%zu) vs. priv size (%zu).\n",
priv_size_check, scontrol->priv_size);
ret = -EINVAL;
goto err;
}
}
return 0;
err:
kfree(scontrol->ipc_control_data);
scontrol->ipc_control_data = NULL;
return ret;
}
static int sof_ipc3_control_load_volume(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
struct sof_ipc_ctrl_data *cdata;
int i;
/* init the volume get/put data */
scontrol->size = struct_size(cdata, chanv, scontrol->num_channels);
scontrol->ipc_control_data = kzalloc(scontrol->size, GFP_KERNEL);
if (!scontrol->ipc_control_data)
return -ENOMEM;
cdata = scontrol->ipc_control_data;
cdata->index = scontrol->index;
/* set cmd for mixer control */
if (scontrol->max == 1) {
cdata->cmd = SOF_CTRL_CMD_SWITCH;
return 0;
}
cdata->cmd = SOF_CTRL_CMD_VOLUME;
/* set default volume values to 0dB in control */
for (i = 0; i < scontrol->num_channels; i++) {
cdata->chanv[i].channel = i;
cdata->chanv[i].value = VOL_ZERO_DB;
}
return 0;
}
static int sof_ipc3_control_load_enum(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
struct sof_ipc_ctrl_data *cdata;
/* init the enum get/put data */
scontrol->size = struct_size(cdata, chanv, scontrol->num_channels);
scontrol->ipc_control_data = kzalloc(scontrol->size, GFP_KERNEL);
if (!scontrol->ipc_control_data)
return -ENOMEM;
cdata = scontrol->ipc_control_data;
cdata->index = scontrol->index;
cdata->cmd = SOF_CTRL_CMD_ENUM;
return 0;
}
static int sof_ipc3_control_setup(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
switch (scontrol->info_type) {
case SND_SOC_TPLG_CTL_VOLSW:
case SND_SOC_TPLG_CTL_VOLSW_SX:
case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
return sof_ipc3_control_load_volume(sdev, scontrol);
case SND_SOC_TPLG_CTL_BYTES:
return sof_ipc3_control_load_bytes(sdev, scontrol);
case SND_SOC_TPLG_CTL_ENUM:
case SND_SOC_TPLG_CTL_ENUM_VALUE:
return sof_ipc3_control_load_enum(sdev, scontrol);
default:
break;
}
return 0;
}
static int sof_ipc3_control_free(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
struct sof_ipc_free fcomp;
fcomp.hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_COMP_FREE;
fcomp.hdr.size = sizeof(fcomp);
fcomp.id = scontrol->comp_id;
/* send IPC to the DSP */
return sof_ipc_tx_message_no_reply(sdev->ipc, &fcomp, sizeof(fcomp));
}
/* send pcm params ipc */
static int sof_ipc3_keyword_detect_pcm_params(struct snd_sof_widget *swidget, int dir)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_pcm_hw_params *params;
struct sof_ipc_pcm_params pcm;
struct snd_sof_pcm *spcm;
int ret;
/* get runtime PCM params using widget's stream name */
spcm = snd_sof_find_spcm_name(scomp, swidget->widget->sname);
if (!spcm) {
dev_err(scomp->dev, "Cannot find PCM for %s\n", swidget->widget->name);
return -EINVAL;
}
params = &spcm->params[dir];
/* set IPC PCM params */
memset(&pcm, 0, sizeof(pcm));
pcm.hdr.size = sizeof(pcm);
pcm.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_PCM_PARAMS;
pcm.comp_id = swidget->comp_id;
pcm.params.hdr.size = sizeof(pcm.params);
pcm.params.direction = dir;
pcm.params.sample_valid_bytes = params_width(params) >> 3;
pcm.params.buffer_fmt = SOF_IPC_BUFFER_INTERLEAVED;
pcm.params.rate = params_rate(params);
pcm.params.channels = params_channels(params);
pcm.params.host_period_bytes = params_period_bytes(params);
/* set format */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16:
pcm.params.frame_fmt = SOF_IPC_FRAME_S16_LE;
break;
case SNDRV_PCM_FORMAT_S24:
pcm.params.frame_fmt = SOF_IPC_FRAME_S24_4LE;
break;
case SNDRV_PCM_FORMAT_S32:
pcm.params.frame_fmt = SOF_IPC_FRAME_S32_LE;
break;
default:
return -EINVAL;
}
/* send IPC to the DSP */
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &pcm, sizeof(pcm));
if (ret < 0)
dev_err(scomp->dev, "%s: PCM params failed for %s\n", __func__,
swidget->widget->name);
return ret;
}
/* send stream trigger ipc */
static int sof_ipc3_keyword_detect_trigger(struct snd_sof_widget *swidget, int cmd)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc_stream stream;
int ret;
/* set IPC stream params */
stream.hdr.size = sizeof(stream);
stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | cmd;
stream.comp_id = swidget->comp_id;
/* send IPC to the DSP */
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &stream, sizeof(stream));
if (ret < 0)
dev_err(scomp->dev, "%s: Failed to trigger %s\n", __func__, swidget->widget->name);
return ret;
}
static int sof_ipc3_keyword_dapm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_sof_widget *swidget = w->dobj.private;
struct snd_soc_component *scomp;
int stream = SNDRV_PCM_STREAM_CAPTURE;
struct snd_sof_pcm *spcm;
int ret = 0;
if (!swidget)
return 0;
scomp = swidget->scomp;
dev_dbg(scomp->dev, "received event %d for widget %s\n",
event, w->name);
/* get runtime PCM params using widget's stream name */
spcm = snd_sof_find_spcm_name(scomp, swidget->widget->sname);
if (!spcm) {
dev_err(scomp->dev, "%s: Cannot find PCM for %s\n", __func__,
swidget->widget->name);
return -EINVAL;
}
/* process events */
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (spcm->stream[stream].suspend_ignored) {
dev_dbg(scomp->dev, "PRE_PMU event ignored, KWD pipeline is already RUNNING\n");
return 0;
}
/* set pcm params */
ret = sof_ipc3_keyword_detect_pcm_params(swidget, stream);
if (ret < 0) {
dev_err(scomp->dev, "%s: Failed to set pcm params for widget %s\n",
__func__, swidget->widget->name);
break;
}
/* start trigger */
ret = sof_ipc3_keyword_detect_trigger(swidget, SOF_IPC_STREAM_TRIG_START);
if (ret < 0)
dev_err(scomp->dev, "%s: Failed to trigger widget %s\n", __func__,
swidget->widget->name);
break;
case SND_SOC_DAPM_POST_PMD:
if (spcm->stream[stream].suspend_ignored) {
dev_dbg(scomp->dev,
"POST_PMD event ignored, KWD pipeline will remain RUNNING\n");
return 0;
}
/* stop trigger */
ret = sof_ipc3_keyword_detect_trigger(swidget, SOF_IPC_STREAM_TRIG_STOP);
if (ret < 0)
dev_err(scomp->dev, "%s: Failed to trigger widget %s\n", __func__,
swidget->widget->name);
/* pcm free */
ret = sof_ipc3_keyword_detect_trigger(swidget, SOF_IPC_STREAM_PCM_FREE);
if (ret < 0)
dev_err(scomp->dev, "%s: Failed to free PCM for widget %s\n", __func__,
swidget->widget->name);
break;
default:
break;
}
return ret;
}
/* event handlers for keyword detect component */
static const struct snd_soc_tplg_widget_events sof_kwd_events[] = {
{SOF_KEYWORD_DETECT_DAPM_EVENT, sof_ipc3_keyword_dapm_event},
};
static int sof_ipc3_widget_bind_event(struct snd_soc_component *scomp,
struct snd_sof_widget *swidget, u16 event_type)
{
struct sof_ipc_comp *ipc_comp;
/* validate widget event type */
switch (event_type) {
case SOF_KEYWORD_DETECT_DAPM_EVENT:
/* only KEYWORD_DETECT comps should handle this */
if (swidget->id != snd_soc_dapm_effect)
break;
ipc_comp = swidget->private;
if (ipc_comp && ipc_comp->type != SOF_COMP_KEYWORD_DETECT)
break;
/* bind event to keyword detect comp */
return snd_soc_tplg_widget_bind_event(swidget->widget, sof_kwd_events,
ARRAY_SIZE(sof_kwd_events), event_type);
default:
break;
}
dev_err(scomp->dev, "Invalid event type %d for widget %s\n", event_type,
swidget->widget->name);
return -EINVAL;
}
static int sof_ipc3_complete_pipeline(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
struct sof_ipc_pipe_ready ready;
int ret;
dev_dbg(sdev->dev, "tplg: complete pipeline %s id %d\n",
swidget->widget->name, swidget->comp_id);
memset(&ready, 0, sizeof(ready));
ready.hdr.size = sizeof(ready);
ready.hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_PIPE_COMPLETE;
ready.comp_id = swidget->comp_id;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &ready, sizeof(ready));
if (ret < 0)
return ret;
return 1;
}
static int sof_ipc3_widget_free(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
struct sof_ipc_free ipc_free = {
.hdr = {
.size = sizeof(ipc_free),
.cmd = SOF_IPC_GLB_TPLG_MSG,
},
.id = swidget->comp_id,
};
int ret;
if (!swidget->private)
return 0;
switch (swidget->id) {
case snd_soc_dapm_scheduler:
{
ipc_free.hdr.cmd |= SOF_IPC_TPLG_PIPE_FREE;
break;
}
case snd_soc_dapm_buffer:
ipc_free.hdr.cmd |= SOF_IPC_TPLG_BUFFER_FREE;
break;
default:
ipc_free.hdr.cmd |= SOF_IPC_TPLG_COMP_FREE;
break;
}
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &ipc_free, sizeof(ipc_free));
if (ret < 0)
dev_err(sdev->dev, "failed to free widget %s\n", swidget->widget->name);
return ret;
}
static int sof_ipc3_dai_config(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget,
unsigned int flags, struct snd_sof_dai_config_data *data)
{
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
struct snd_sof_dai *dai = swidget->private;
struct sof_dai_private_data *private;
struct sof_ipc_dai_config *config;
int ret = 0;
if (!dai || !dai->private) {
dev_err(sdev->dev, "No private data for DAI %s\n", swidget->widget->name);
return -EINVAL;
}
private = dai->private;
if (!private->dai_config) {
dev_err(sdev->dev, "No config for DAI %s\n", dai->name);
return -EINVAL;
}
config = &private->dai_config[dai->current_config];
if (!config) {
dev_err(sdev->dev, "Invalid current config for DAI %s\n", dai->name);
return -EINVAL;
}
switch (config->type) {
case SOF_DAI_INTEL_SSP:
/*
* DAI_CONFIG IPC during hw_params/hw_free for SSP DAI's is not supported in older
* firmware
*/
if (v->abi_version < SOF_ABI_VER(3, 18, 0) &&
((flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) ||
(flags & SOF_DAI_CONFIG_FLAGS_HW_FREE)))
return 0;
break;
case SOF_DAI_INTEL_HDA:
if (data)
config->hda.link_dma_ch = data->dai_data;
break;
case SOF_DAI_INTEL_ALH:
if (data) {
/* save the dai_index during hw_params and reuse it for hw_free */
if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS)
config->dai_index = data->dai_index;
config->alh.stream_id = data->dai_data;
}
break;
default:
break;
}
/*
* The dai_config op is invoked several times and the flags argument varies as below:
* BE DAI hw_params: When the op is invoked during the BE DAI hw_params, flags contains
* SOF_DAI_CONFIG_FLAGS_HW_PARAMS along with quirks
* FE DAI hw_params: When invoked during FE DAI hw_params after the DAI widget has
* just been set up in the DSP, flags is set to SOF_DAI_CONFIG_FLAGS_HW_PARAMS with no
* quirks
* BE DAI trigger: When invoked during the BE DAI trigger, flags is set to
* SOF_DAI_CONFIG_FLAGS_PAUSE and contains no quirks
* BE DAI hw_free: When invoked during the BE DAI hw_free, flags is set to
* SOF_DAI_CONFIG_FLAGS_HW_FREE and contains no quirks
* FE DAI hw_free: When invoked during the FE DAI hw_free, flags is set to
* SOF_DAI_CONFIG_FLAGS_HW_FREE and contains no quirks
*
* The DAI_CONFIG IPC is sent to the DSP, only after the widget is set up during the FE
* DAI hw_params. But since the BE DAI hw_params precedes the FE DAI hw_params, the quirks
* need to be preserved when assigning the flags before sending the IPC.
* For the case of PAUSE/HW_FREE, since there are no quirks, flags can be used as is.
*/
if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) {
/* Clear stale command */
config->flags &= ~SOF_DAI_CONFIG_FLAGS_CMD_MASK;
config->flags |= flags;
} else {
config->flags = flags;
}
/* only send the IPC if the widget is set up in the DSP */
if (swidget->use_count > 0) {
ret = sof_ipc_tx_message_no_reply(sdev->ipc, config, config->hdr.size);
if (ret < 0)
dev_err(sdev->dev, "Failed to set dai config for %s\n", dai->name);
/* clear the flags once the IPC has been sent even if it fails */
config->flags = SOF_DAI_CONFIG_FLAGS_NONE;
}
return ret;
}
static int sof_ipc3_widget_setup(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
int ret;
if (!swidget->private)
return 0;
switch (swidget->id) {
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
{
struct snd_sof_dai *dai = swidget->private;
struct sof_dai_private_data *dai_data = dai->private;
struct sof_ipc_comp *comp = &dai_data->comp_dai->comp;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, dai_data->comp_dai, comp->hdr.size);
break;
}
case snd_soc_dapm_scheduler:
{
struct sof_ipc_pipe_new *pipeline;
pipeline = swidget->private;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, pipeline, sizeof(*pipeline));
break;
}
default:
{
struct sof_ipc_cmd_hdr *hdr;
hdr = swidget->private;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, swidget->private, hdr->size);
break;
}
}
if (ret < 0)
dev_err(sdev->dev, "Failed to setup widget %s\n", swidget->widget->name);
return ret;
}
static int sof_ipc3_set_up_all_pipelines(struct snd_sof_dev *sdev, bool verify)
{
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
struct snd_sof_widget *swidget;
struct snd_sof_route *sroute;
int ret;
/* restore pipeline components */
list_for_each_entry(swidget, &sdev->widget_list, list) {
/* only set up the widgets belonging to static pipelines */
if (!verify && swidget->dynamic_pipeline_widget)
continue;
/*
* For older firmware, skip scheduler widgets in this loop,
* sof_widget_setup() will be called in the 'complete pipeline' loop
*/
if (v->abi_version < SOF_ABI_VER(3, 19, 0) &&
swidget->id == snd_soc_dapm_scheduler)
continue;
/* update DAI config. The IPC will be sent in sof_widget_setup() */
if (WIDGET_IS_DAI(swidget->id)) {
struct snd_sof_dai *dai = swidget->private;
struct sof_dai_private_data *private;
struct sof_ipc_dai_config *config;
if (!dai || !dai->private)
continue;
private = dai->private;
if (!private->dai_config)
continue;
config = private->dai_config;
/*
* The link DMA channel would be invalidated for running
* streams but not for streams that were in the PAUSED
* state during suspend. So invalidate it here before setting
* the dai config in the DSP.
*/
if (config->type == SOF_DAI_INTEL_HDA)
config->hda.link_dma_ch = DMA_CHAN_INVALID;
}
ret = sof_widget_setup(sdev, swidget);
if (ret < 0)
return ret;
}
/* restore pipeline connections */
list_for_each_entry(sroute, &sdev->route_list, list) {
/* only set up routes belonging to static pipelines */
if (!verify && (sroute->src_widget->dynamic_pipeline_widget ||
sroute->sink_widget->dynamic_pipeline_widget))
continue;
/*
* For virtual routes, both sink and source are not buffer. IPC3 only supports
* connections between a buffer and a component. Ignore the rest.
*/
if (sroute->src_widget->id != snd_soc_dapm_buffer &&
sroute->sink_widget->id != snd_soc_dapm_buffer)
continue;
ret = sof_route_setup(sdev, sroute->src_widget->widget,
sroute->sink_widget->widget);
if (ret < 0) {
dev_err(sdev->dev, "%s: route set up failed\n", __func__);
return ret;
}
}
/* complete pipeline */
list_for_each_entry(swidget, &sdev->widget_list, list) {
switch (swidget->id) {
case snd_soc_dapm_scheduler:
/* only complete static pipelines */
if (!verify && swidget->dynamic_pipeline_widget)
continue;
if (v->abi_version < SOF_ABI_VER(3, 19, 0)) {
ret = sof_widget_setup(sdev, swidget);
if (ret < 0)
return ret;
}
swidget->spipe->complete = sof_ipc3_complete_pipeline(sdev, swidget);
if (swidget->spipe->complete < 0)
return swidget->spipe->complete;
break;
default:
break;
}
}
return 0;
}
/*
* Free the PCM, its associated widgets and set the prepared flag to false for all PCMs that
* did not get suspended(ex: paused streams) so the widgets can be set up again during resume.
*/
static int sof_tear_down_left_over_pipelines(struct snd_sof_dev *sdev)
{
struct snd_sof_widget *swidget;
struct snd_sof_pcm *spcm;
int dir, ret;
/*
* free all PCMs and their associated DAPM widgets if their connected DAPM widget
* list is not NULL. This should only be true for paused streams at this point.
* This is equivalent to the handling of FE DAI suspend trigger for running streams.
*/
list_for_each_entry(spcm, &sdev->pcm_list, list) {
for_each_pcm_streams(dir) {
struct snd_pcm_substream *substream = spcm->stream[dir].substream;
if (!substream || !substream->runtime || spcm->stream[dir].suspend_ignored)
continue;
if (spcm->stream[dir].list) {
ret = sof_pcm_stream_free(sdev, substream, spcm, dir, true);
if (ret < 0)
return ret;
}
}
}
/*
* free any left over DAI widgets. This is equivalent to the handling of suspend trigger
* for the BE DAI for running streams.
*/
list_for_each_entry(swidget, &sdev->widget_list, list)
if (WIDGET_IS_DAI(swidget->id) && swidget->use_count == 1) {
ret = sof_widget_free(sdev, swidget);
if (ret < 0)
return ret;
}
return 0;
}
/*
* For older firmware, this function doesn't free widgets for static pipelines during suspend.
* It only resets use_count for all widgets.
*/
static int sof_ipc3_tear_down_all_pipelines(struct snd_sof_dev *sdev, bool verify)
{
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
struct snd_sof_widget *swidget;
struct snd_sof_route *sroute;
bool dyn_widgets = false;
int ret;
/*
* This function is called during suspend and for one-time topology verification during
* first boot. In both cases, there is no need to protect swidget->use_count and
* sroute->setup because during suspend all running streams are suspended and during
* topology loading the sound card unavailable to open PCMs.
*/
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (swidget->dynamic_pipeline_widget) {
dyn_widgets = true;
continue;
}
/* Do not free widgets for static pipelines with FW older than SOF2.2 */
if (!verify && !swidget->dynamic_pipeline_widget &&
SOF_FW_VER(v->major, v->minor, v->micro) < SOF_FW_VER(2, 2, 0)) {
mutex_lock(&swidget->setup_mutex);
swidget->use_count = 0;
mutex_unlock(&swidget->setup_mutex);
if (swidget->spipe)
swidget->spipe->complete = 0;
continue;
}
ret = sof_widget_free(sdev, swidget);
if (ret < 0)
return ret;
}
/*
* Tear down all pipelines associated with PCMs that did not get suspended
* and unset the prepare flag so that they can be set up again during resume.
* Skip this step for older firmware unless topology has any
* dynamic pipeline (in which case the step is mandatory).
*/
if (!verify && (dyn_widgets || SOF_FW_VER(v->major, v->minor, v->micro) >=
SOF_FW_VER(2, 2, 0))) {
ret = sof_tear_down_left_over_pipelines(sdev);
if (ret < 0) {
dev_err(sdev->dev, "failed to tear down paused pipelines\n");
return ret;
}
}
list_for_each_entry(sroute, &sdev->route_list, list)
sroute->setup = false;
/*
* before suspending, make sure the refcounts are all zeroed out. There's no way
* to recover at this point but this will help root cause bad sequences leading to
* more issues on resume
*/
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (swidget->use_count != 0) {
dev_err(sdev->dev, "%s: widget %s is still in use: count %d\n",
__func__, swidget->widget->name, swidget->use_count);
}
}
return 0;
}
static int sof_ipc3_dai_get_clk(struct snd_sof_dev *sdev, struct snd_sof_dai *dai, int clk_type)
{
struct sof_dai_private_data *private = dai->private;
if (!private || !private->dai_config)
return 0;
switch (private->dai_config->type) {
case SOF_DAI_INTEL_SSP:
switch (clk_type) {
case SOF_DAI_CLK_INTEL_SSP_MCLK:
return private->dai_config->ssp.mclk_rate;
case SOF_DAI_CLK_INTEL_SSP_BCLK:
return private->dai_config->ssp.bclk_rate;
default:
break;
}
dev_err(sdev->dev, "fail to get SSP clk %d rate\n", clk_type);
break;
default:
/* not yet implemented for platforms other than the above */
dev_err(sdev->dev, "DAI type %d not supported yet!\n", private->dai_config->type);
break;
}
return -EINVAL;
}
static int sof_ipc3_parse_manifest(struct snd_soc_component *scomp, int index,
struct snd_soc_tplg_manifest *man)
{
u32 size = le32_to_cpu(man->priv.size);
u32 abi_version;
/* backward compatible with tplg without ABI info */
if (!size) {
dev_dbg(scomp->dev, "No topology ABI info\n");
return 0;
}
if (size != SOF_IPC3_TPLG_ABI_SIZE) {
dev_err(scomp->dev, "%s: Invalid topology ABI size: %u\n",
__func__, size);
return -EINVAL;
}
dev_info(scomp->dev,
"Topology: ABI %d:%d:%d Kernel ABI %d:%d:%d\n",
man->priv.data[0], man->priv.data[1], man->priv.data[2],
SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
abi_version = SOF_ABI_VER(man->priv.data[0], man->priv.data[1], man->priv.data[2]);
if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, abi_version)) {
dev_err(scomp->dev, "%s: Incompatible topology ABI version\n", __func__);
return -EINVAL;
}
if (IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS) &&
SOF_ABI_VERSION_MINOR(abi_version) > SOF_ABI_MINOR) {
dev_err(scomp->dev, "%s: Topology ABI is more recent than kernel\n", __func__);
return -EINVAL;
}
return 0;
}
static int sof_ipc3_link_setup(struct snd_sof_dev *sdev, struct snd_soc_dai_link *link)
{
if (link->no_pcm)
return 0;
/*
* set default trigger order for all links. Exceptions to
* the rule will be handled in sof_pcm_dai_link_fixup()
* For playback, the sequence is the following: start FE,
* start BE, stop BE, stop FE; for Capture the sequence is
* inverted start BE, start FE, stop FE, stop BE
*/
link->trigger[SNDRV_PCM_STREAM_PLAYBACK] = SND_SOC_DPCM_TRIGGER_PRE;
link->trigger[SNDRV_PCM_STREAM_CAPTURE] = SND_SOC_DPCM_TRIGGER_POST;
return 0;
}
/* token list for each topology object */
static enum sof_tokens host_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_PCM_TOKENS,
SOF_COMP_TOKENS,
};
static enum sof_tokens comp_generic_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_COMP_TOKENS,
};
static enum sof_tokens buffer_token_list[] = {
SOF_BUFFER_TOKENS,
};
static enum sof_tokens pipeline_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_PIPELINE_TOKENS,
SOF_SCHED_TOKENS,
};
static enum sof_tokens asrc_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_ASRC_TOKENS,
SOF_COMP_TOKENS,
};
static enum sof_tokens src_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_SRC_TOKENS,
SOF_COMP_TOKENS
};
static enum sof_tokens pga_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_VOLUME_TOKENS,
SOF_COMP_TOKENS,
};
static enum sof_tokens dai_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_DAI_TOKENS,
SOF_COMP_TOKENS,
};
static enum sof_tokens process_token_list[] = {
SOF_CORE_TOKENS,
SOF_COMP_EXT_TOKENS,
SOF_PROCESS_TOKENS,
SOF_COMP_TOKENS,
};
static const struct sof_ipc_tplg_widget_ops tplg_ipc3_widget_ops[SND_SOC_DAPM_TYPE_COUNT] = {
[snd_soc_dapm_aif_in] = {sof_ipc3_widget_setup_comp_host, sof_ipc3_widget_free_comp,
host_token_list, ARRAY_SIZE(host_token_list), NULL},
[snd_soc_dapm_aif_out] = {sof_ipc3_widget_setup_comp_host, sof_ipc3_widget_free_comp,
host_token_list, ARRAY_SIZE(host_token_list), NULL},
[snd_soc_dapm_dai_in] = {sof_ipc3_widget_setup_comp_dai, sof_ipc3_widget_free_comp_dai,
dai_token_list, ARRAY_SIZE(dai_token_list), NULL},
[snd_soc_dapm_dai_out] = {sof_ipc3_widget_setup_comp_dai, sof_ipc3_widget_free_comp_dai,
dai_token_list, ARRAY_SIZE(dai_token_list), NULL},
[snd_soc_dapm_buffer] = {sof_ipc3_widget_setup_comp_buffer, sof_ipc3_widget_free_comp,
buffer_token_list, ARRAY_SIZE(buffer_token_list), NULL},
[snd_soc_dapm_mixer] = {sof_ipc3_widget_setup_comp_mixer, sof_ipc3_widget_free_comp,
comp_generic_token_list, ARRAY_SIZE(comp_generic_token_list),
NULL},
[snd_soc_dapm_src] = {sof_ipc3_widget_setup_comp_src, sof_ipc3_widget_free_comp,
src_token_list, ARRAY_SIZE(src_token_list), NULL},
[snd_soc_dapm_asrc] = {sof_ipc3_widget_setup_comp_asrc, sof_ipc3_widget_free_comp,
asrc_token_list, ARRAY_SIZE(asrc_token_list), NULL},
[snd_soc_dapm_siggen] = {sof_ipc3_widget_setup_comp_tone, sof_ipc3_widget_free_comp,
comp_generic_token_list, ARRAY_SIZE(comp_generic_token_list),
NULL},
[snd_soc_dapm_scheduler] = {sof_ipc3_widget_setup_comp_pipeline, sof_ipc3_widget_free_comp,
pipeline_token_list, ARRAY_SIZE(pipeline_token_list), NULL},
[snd_soc_dapm_pga] = {sof_ipc3_widget_setup_comp_pga, sof_ipc3_widget_free_comp,
pga_token_list, ARRAY_SIZE(pga_token_list), NULL},
[snd_soc_dapm_mux] = {sof_ipc3_widget_setup_comp_mux, sof_ipc3_widget_free_comp,
comp_generic_token_list, ARRAY_SIZE(comp_generic_token_list), NULL},
[snd_soc_dapm_demux] = {sof_ipc3_widget_setup_comp_mux, sof_ipc3_widget_free_comp,
comp_generic_token_list, ARRAY_SIZE(comp_generic_token_list),
NULL},
[snd_soc_dapm_effect] = {sof_widget_update_ipc_comp_process, sof_ipc3_widget_free_comp,
process_token_list, ARRAY_SIZE(process_token_list),
sof_ipc3_widget_bind_event},
};
const struct sof_ipc_tplg_ops ipc3_tplg_ops = {
.widget = tplg_ipc3_widget_ops,
.control = &tplg_ipc3_control_ops,
.route_setup = sof_ipc3_route_setup,
.control_setup = sof_ipc3_control_setup,
.control_free = sof_ipc3_control_free,
.pipeline_complete = sof_ipc3_complete_pipeline,
.token_list = ipc3_token_list,
.widget_free = sof_ipc3_widget_free,
.widget_setup = sof_ipc3_widget_setup,
.dai_config = sof_ipc3_dai_config,
.dai_get_clk = sof_ipc3_dai_get_clk,
.set_up_all_pipelines = sof_ipc3_set_up_all_pipelines,
.tear_down_all_pipelines = sof_ipc3_tear_down_all_pipelines,
.parse_manifest = sof_ipc3_parse_manifest,
.link_setup = sof_ipc3_link_setup,
};
| linux-master | sound/soc/sof/ipc3-topology.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2022 Intel Corporation. All rights reserved.
//
// Author: Keyon Jie <[email protected]>
//
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/platform_device.h>
#include <asm/unaligned.h>
#include <sound/soc.h>
#include <sound/sof.h>
#include "sof-priv.h"
#include "ops.h"
/*
* Register IO
*
* The sof_io_xyz() wrappers are typically referenced in snd_sof_dsp_ops
* structures and cannot be inlined.
*/
void sof_io_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value)
{
writel(value, addr);
}
EXPORT_SYMBOL(sof_io_write);
u32 sof_io_read(struct snd_sof_dev *sdev, void __iomem *addr)
{
return readl(addr);
}
EXPORT_SYMBOL(sof_io_read);
void sof_io_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value)
{
writeq(value, addr);
}
EXPORT_SYMBOL(sof_io_write64);
u64 sof_io_read64(struct snd_sof_dev *sdev, void __iomem *addr)
{
return readq(addr);
}
EXPORT_SYMBOL(sof_io_read64);
/*
* IPC Mailbox IO
*/
void sof_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
void *message, size_t bytes)
{
void __iomem *dest = sdev->bar[sdev->mailbox_bar] + offset;
memcpy_toio(dest, message, bytes);
}
EXPORT_SYMBOL(sof_mailbox_write);
void sof_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
void *message, size_t bytes)
{
void __iomem *src = sdev->bar[sdev->mailbox_bar] + offset;
memcpy_fromio(message, src, bytes);
}
EXPORT_SYMBOL(sof_mailbox_read);
/*
* Memory copy.
*/
int sof_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
u32 offset, void *src, size_t size)
{
int bar = snd_sof_dsp_get_bar_index(sdev, blk_type);
const u8 *src_byte = src;
void __iomem *dest;
u32 affected_mask;
u32 tmp;
int m, n;
if (bar < 0)
return bar;
dest = sdev->bar[bar] + offset;
m = size / 4;
n = size % 4;
/* __iowrite32_copy use 32bit size values so divide by 4 */
__iowrite32_copy(dest, src, m);
if (n) {
affected_mask = (1 << (8 * n)) - 1;
/* first read the 32bit data of dest, then change affected
* bytes, and write back to dest. For unaffected bytes, it
* should not be changed
*/
tmp = ioread32(dest + m * 4);
tmp &= ~affected_mask;
tmp |= *(u32 *)(src_byte + m * 4) & affected_mask;
iowrite32(tmp, dest + m * 4);
}
return 0;
}
EXPORT_SYMBOL(sof_block_write);
int sof_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
u32 offset, void *dest, size_t size)
{
int bar = snd_sof_dsp_get_bar_index(sdev, blk_type);
if (bar < 0)
return bar;
memcpy_fromio(dest, sdev->bar[bar] + offset, size);
return 0;
}
EXPORT_SYMBOL(sof_block_read);
| linux-master | sound/soc/sof/iomem-utils.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2021 Intel Corporation. All rights reserved.
//
//
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc3-priv.h"
/* IPC set()/get() for kcontrols. */
static int sof_ipc3_set_get_kcontrol_data(struct snd_sof_control *scontrol,
bool set, bool lock)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scontrol->scomp);
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
const struct sof_ipc_ops *iops = sdev->ipc->ops;
enum sof_ipc_ctrl_type ctrl_type;
struct snd_sof_widget *swidget;
bool widget_found = false;
u32 ipc_cmd, msg_bytes;
int ret = 0;
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (swidget->comp_id == scontrol->comp_id) {
widget_found = true;
break;
}
}
if (!widget_found) {
dev_err(sdev->dev, "%s: can't find widget with id %d\n", __func__,
scontrol->comp_id);
return -EINVAL;
}
if (lock)
mutex_lock(&swidget->setup_mutex);
else
lockdep_assert_held(&swidget->setup_mutex);
/*
* Volatile controls should always be part of static pipelines and the
* widget use_count would always be > 0 in this case. For the others,
* just return the cached value if the widget is not set up.
*/
if (!swidget->use_count)
goto unlock;
/*
* Select the IPC cmd and the ctrl_type based on the ctrl_cmd and the
* direction
* Note: SOF_CTRL_TYPE_VALUE_COMP_* is not used and supported currently
* for ctrl_type
*/
if (cdata->cmd == SOF_CTRL_CMD_BINARY) {
ipc_cmd = set ? SOF_IPC_COMP_SET_DATA : SOF_IPC_COMP_GET_DATA;
ctrl_type = set ? SOF_CTRL_TYPE_DATA_SET : SOF_CTRL_TYPE_DATA_GET;
} else {
ipc_cmd = set ? SOF_IPC_COMP_SET_VALUE : SOF_IPC_COMP_GET_VALUE;
ctrl_type = set ? SOF_CTRL_TYPE_VALUE_CHAN_SET : SOF_CTRL_TYPE_VALUE_CHAN_GET;
}
cdata->rhdr.hdr.cmd = SOF_IPC_GLB_COMP_MSG | ipc_cmd;
cdata->type = ctrl_type;
cdata->comp_id = scontrol->comp_id;
cdata->msg_index = 0;
/* calculate header and data size */
switch (cdata->type) {
case SOF_CTRL_TYPE_VALUE_CHAN_GET:
case SOF_CTRL_TYPE_VALUE_CHAN_SET:
cdata->num_elems = scontrol->num_channels;
msg_bytes = scontrol->num_channels *
sizeof(struct sof_ipc_ctrl_value_chan);
msg_bytes += sizeof(struct sof_ipc_ctrl_data);
break;
case SOF_CTRL_TYPE_DATA_GET:
case SOF_CTRL_TYPE_DATA_SET:
cdata->num_elems = cdata->data->size;
msg_bytes = cdata->data->size;
msg_bytes += sizeof(struct sof_ipc_ctrl_data) +
sizeof(struct sof_abi_hdr);
break;
default:
ret = -EINVAL;
goto unlock;
}
cdata->rhdr.hdr.size = msg_bytes;
cdata->elems_remaining = 0;
ret = iops->set_get_data(sdev, cdata, cdata->rhdr.hdr.size, set);
if (!set)
goto unlock;
/* It is a set-data operation, and we have a backup that we can restore */
if (ret < 0) {
if (!scontrol->old_ipc_control_data)
goto unlock;
/*
* Current ipc_control_data is not valid, we use the last known good
* configuration
*/
memcpy(scontrol->ipc_control_data, scontrol->old_ipc_control_data,
scontrol->max_size);
kfree(scontrol->old_ipc_control_data);
scontrol->old_ipc_control_data = NULL;
/* Send the last known good configuration to firmware */
ret = iops->set_get_data(sdev, cdata, cdata->rhdr.hdr.size, set);
if (ret < 0)
goto unlock;
}
unlock:
if (lock)
mutex_unlock(&swidget->setup_mutex);
return ret;
}
static void sof_ipc3_refresh_control(struct snd_sof_control *scontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
int ret;
if (!scontrol->comp_data_dirty)
return;
if (!pm_runtime_active(scomp->dev))
return;
/* set the ABI header values */
cdata->data->magic = SOF_ABI_MAGIC;
cdata->data->abi = SOF_ABI_VERSION;
/* refresh the component data from DSP */
scontrol->comp_data_dirty = false;
ret = sof_ipc3_set_get_kcontrol_data(scontrol, false, true);
if (ret < 0) {
dev_err(scomp->dev, "Failed to get control data: %d\n", ret);
/* Set the flag to re-try next time to get the data */
scontrol->comp_data_dirty = true;
}
}
static int sof_ipc3_volume_get(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
unsigned int channels = scontrol->num_channels;
unsigned int i;
sof_ipc3_refresh_control(scontrol);
/* read back each channel */
for (i = 0; i < channels; i++)
ucontrol->value.integer.value[i] = ipc_to_mixer(cdata->chanv[i].value,
scontrol->volume_table,
scontrol->max + 1);
return 0;
}
static bool sof_ipc3_volume_put(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
unsigned int channels = scontrol->num_channels;
unsigned int i;
bool change = false;
/* update each channel */
for (i = 0; i < channels; i++) {
u32 value = mixer_to_ipc(ucontrol->value.integer.value[i],
scontrol->volume_table, scontrol->max + 1);
change = change || (value != cdata->chanv[i].value);
cdata->chanv[i].channel = i;
cdata->chanv[i].value = value;
}
/* notify DSP of mixer updates */
if (pm_runtime_active(scomp->dev)) {
int ret = sof_ipc3_set_get_kcontrol_data(scontrol, true, true);
if (ret < 0) {
dev_err(scomp->dev, "Failed to set mixer updates for %s\n",
scontrol->name);
return false;
}
}
return change;
}
static int sof_ipc3_switch_get(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
unsigned int channels = scontrol->num_channels;
unsigned int i;
sof_ipc3_refresh_control(scontrol);
/* read back each channel */
for (i = 0; i < channels; i++)
ucontrol->value.integer.value[i] = cdata->chanv[i].value;
return 0;
}
static bool sof_ipc3_switch_put(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
unsigned int channels = scontrol->num_channels;
unsigned int i;
bool change = false;
u32 value;
/* update each channel */
for (i = 0; i < channels; i++) {
value = ucontrol->value.integer.value[i];
change = change || (value != cdata->chanv[i].value);
cdata->chanv[i].channel = i;
cdata->chanv[i].value = value;
}
/* notify DSP of mixer updates */
if (pm_runtime_active(scomp->dev)) {
int ret = sof_ipc3_set_get_kcontrol_data(scontrol, true, true);
if (ret < 0) {
dev_err(scomp->dev, "Failed to set mixer updates for %s\n",
scontrol->name);
return false;
}
}
return change;
}
static int sof_ipc3_enum_get(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
unsigned int channels = scontrol->num_channels;
unsigned int i;
sof_ipc3_refresh_control(scontrol);
/* read back each channel */
for (i = 0; i < channels; i++)
ucontrol->value.enumerated.item[i] = cdata->chanv[i].value;
return 0;
}
static bool sof_ipc3_enum_put(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
unsigned int channels = scontrol->num_channels;
unsigned int i;
bool change = false;
u32 value;
/* update each channel */
for (i = 0; i < channels; i++) {
value = ucontrol->value.enumerated.item[i];
change = change || (value != cdata->chanv[i].value);
cdata->chanv[i].channel = i;
cdata->chanv[i].value = value;
}
/* notify DSP of enum updates */
if (pm_runtime_active(scomp->dev)) {
int ret = sof_ipc3_set_get_kcontrol_data(scontrol, true, true);
if (ret < 0) {
dev_err(scomp->dev, "Failed to set enum updates for %s\n",
scontrol->name);
return false;
}
}
return change;
}
static int sof_ipc3_bytes_get(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct sof_abi_hdr *data = cdata->data;
size_t size;
sof_ipc3_refresh_control(scontrol);
if (scontrol->max_size > sizeof(ucontrol->value.bytes.data)) {
dev_err_ratelimited(scomp->dev, "data max %zu exceeds ucontrol data array size\n",
scontrol->max_size);
return -EINVAL;
}
/* be->max has been verified to be >= sizeof(struct sof_abi_hdr) */
if (data->size > scontrol->max_size - sizeof(*data)) {
dev_err_ratelimited(scomp->dev,
"%u bytes of control data is invalid, max is %zu\n",
data->size, scontrol->max_size - sizeof(*data));
return -EINVAL;
}
size = data->size + sizeof(*data);
/* copy back to kcontrol */
memcpy(ucontrol->value.bytes.data, data, size);
return 0;
}
static int sof_ipc3_bytes_put(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct sof_abi_hdr *data = cdata->data;
size_t size;
if (scontrol->max_size > sizeof(ucontrol->value.bytes.data)) {
dev_err_ratelimited(scomp->dev, "data max %zu exceeds ucontrol data array size\n",
scontrol->max_size);
return -EINVAL;
}
/* scontrol->max_size has been verified to be >= sizeof(struct sof_abi_hdr) */
if (data->size > scontrol->max_size - sizeof(*data)) {
dev_err_ratelimited(scomp->dev, "data size too big %u bytes max is %zu\n",
data->size, scontrol->max_size - sizeof(*data));
return -EINVAL;
}
size = data->size + sizeof(*data);
/* copy from kcontrol */
memcpy(data, ucontrol->value.bytes.data, size);
/* notify DSP of byte control updates */
if (pm_runtime_active(scomp->dev))
return sof_ipc3_set_get_kcontrol_data(scontrol, true, true);
return 0;
}
static int sof_ipc3_bytes_ext_put(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
const struct snd_ctl_tlv __user *tlvd = (const struct snd_ctl_tlv __user *)binary_data;
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_ctl_tlv header;
int ret = -EINVAL;
/*
* The beginning of bytes data contains a header from where
* the length (as bytes) is needed to know the correct copy
* length of data from tlvd->tlv.
*/
if (copy_from_user(&header, tlvd, sizeof(struct snd_ctl_tlv)))
return -EFAULT;
/* make sure TLV info is consistent */
if (header.length + sizeof(struct snd_ctl_tlv) > size) {
dev_err_ratelimited(scomp->dev, "Inconsistent TLV, data %d + header %zu > %d\n",
header.length, sizeof(struct snd_ctl_tlv), size);
return -EINVAL;
}
/* be->max is coming from topology */
if (header.length > scontrol->max_size) {
dev_err_ratelimited(scomp->dev, "Bytes data size %d exceeds max %zu\n",
header.length, scontrol->max_size);
return -EINVAL;
}
/* Check that header id matches the command */
if (header.numid != cdata->cmd) {
dev_err_ratelimited(scomp->dev, "Incorrect command for bytes put %d\n",
header.numid);
return -EINVAL;
}
if (!scontrol->old_ipc_control_data) {
/* Create a backup of the current, valid bytes control */
scontrol->old_ipc_control_data = kmemdup(scontrol->ipc_control_data,
scontrol->max_size, GFP_KERNEL);
if (!scontrol->old_ipc_control_data)
return -ENOMEM;
}
if (copy_from_user(cdata->data, tlvd->tlv, header.length)) {
ret = -EFAULT;
goto err_restore;
}
if (cdata->data->magic != SOF_ABI_MAGIC) {
dev_err_ratelimited(scomp->dev, "Wrong ABI magic 0x%08x\n", cdata->data->magic);
goto err_restore;
}
if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, cdata->data->abi)) {
dev_err_ratelimited(scomp->dev, "Incompatible ABI version 0x%08x\n",
cdata->data->abi);
goto err_restore;
}
/* be->max has been verified to be >= sizeof(struct sof_abi_hdr) */
if (cdata->data->size > scontrol->max_size - sizeof(struct sof_abi_hdr)) {
dev_err_ratelimited(scomp->dev, "Mismatch in ABI data size (truncated?)\n");
goto err_restore;
}
/* notify DSP of byte control updates */
if (pm_runtime_active(scomp->dev)) {
/* Actually send the data to the DSP; this is an opportunity to validate the data */
return sof_ipc3_set_get_kcontrol_data(scontrol, true, true);
}
return 0;
err_restore:
/* If we have an issue, we restore the old, valid bytes control data */
if (scontrol->old_ipc_control_data) {
memcpy(cdata->data, scontrol->old_ipc_control_data, scontrol->max_size);
kfree(scontrol->old_ipc_control_data);
scontrol->old_ipc_control_data = NULL;
}
return ret;
}
static int _sof_ipc3_bytes_ext_get(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size, bool from_dsp)
{
struct snd_ctl_tlv __user *tlvd = (struct snd_ctl_tlv __user *)binary_data;
struct sof_ipc_ctrl_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_ctl_tlv header;
size_t data_size;
/*
* Decrement the limit by ext bytes header size to
* ensure the user space buffer is not exceeded.
*/
if (size < sizeof(struct snd_ctl_tlv))
return -ENOSPC;
size -= sizeof(struct snd_ctl_tlv);
/* set the ABI header values */
cdata->data->magic = SOF_ABI_MAGIC;
cdata->data->abi = SOF_ABI_VERSION;
/* get all the component data from DSP */
if (from_dsp) {
int ret = sof_ipc3_set_get_kcontrol_data(scontrol, false, true);
if (ret < 0)
return ret;
}
/* check data size doesn't exceed max coming from topology */
if (cdata->data->size > scontrol->max_size - sizeof(struct sof_abi_hdr)) {
dev_err_ratelimited(scomp->dev, "User data size %d exceeds max size %zu\n",
cdata->data->size,
scontrol->max_size - sizeof(struct sof_abi_hdr));
return -EINVAL;
}
data_size = cdata->data->size + sizeof(struct sof_abi_hdr);
/* make sure we don't exceed size provided by user space for data */
if (data_size > size)
return -ENOSPC;
header.numid = cdata->cmd;
header.length = data_size;
if (copy_to_user(tlvd, &header, sizeof(struct snd_ctl_tlv)))
return -EFAULT;
if (copy_to_user(tlvd->tlv, cdata->data, data_size))
return -EFAULT;
return 0;
}
static int sof_ipc3_bytes_ext_get(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data, unsigned int size)
{
return _sof_ipc3_bytes_ext_get(scontrol, binary_data, size, false);
}
static int sof_ipc3_bytes_ext_volatile_get(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
return _sof_ipc3_bytes_ext_get(scontrol, binary_data, size, true);
}
static void snd_sof_update_control(struct snd_sof_control *scontrol,
struct sof_ipc_ctrl_data *cdata)
{
struct snd_soc_component *scomp = scontrol->scomp;
struct sof_ipc_ctrl_data *local_cdata;
int i;
local_cdata = scontrol->ipc_control_data;
if (cdata->cmd == SOF_CTRL_CMD_BINARY) {
if (cdata->num_elems != local_cdata->data->size) {
dev_err(scomp->dev, "cdata binary size mismatch %u - %u\n",
cdata->num_elems, local_cdata->data->size);
return;
}
/* copy the new binary data */
memcpy(local_cdata->data, cdata->data, cdata->num_elems);
} else if (cdata->num_elems != scontrol->num_channels) {
dev_err(scomp->dev, "cdata channel count mismatch %u - %d\n",
cdata->num_elems, scontrol->num_channels);
} else {
/* copy the new values */
for (i = 0; i < cdata->num_elems; i++)
local_cdata->chanv[i].value = cdata->chanv[i].value;
}
}
static void sof_ipc3_control_update(struct snd_sof_dev *sdev, void *ipc_control_message)
{
struct sof_ipc_ctrl_data *cdata = ipc_control_message;
struct snd_soc_dapm_widget *widget;
struct snd_sof_control *scontrol;
struct snd_sof_widget *swidget;
struct snd_kcontrol *kc = NULL;
struct soc_mixer_control *sm;
struct soc_bytes_ext *be;
size_t expected_size;
struct soc_enum *se;
bool found = false;
int i, type;
if (cdata->type == SOF_CTRL_TYPE_VALUE_COMP_GET ||
cdata->type == SOF_CTRL_TYPE_VALUE_COMP_SET) {
dev_err(sdev->dev, "Component data is not supported in control notification\n");
return;
}
/* Find the swidget first */
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (swidget->comp_id == cdata->comp_id) {
found = true;
break;
}
}
if (!found)
return;
/* Translate SOF cmd to TPLG type */
switch (cdata->cmd) {
case SOF_CTRL_CMD_VOLUME:
case SOF_CTRL_CMD_SWITCH:
type = SND_SOC_TPLG_TYPE_MIXER;
break;
case SOF_CTRL_CMD_BINARY:
type = SND_SOC_TPLG_TYPE_BYTES;
break;
case SOF_CTRL_CMD_ENUM:
type = SND_SOC_TPLG_TYPE_ENUM;
break;
default:
dev_err(sdev->dev, "Unknown cmd %u in %s\n", cdata->cmd, __func__);
return;
}
widget = swidget->widget;
for (i = 0; i < widget->num_kcontrols; i++) {
/* skip non matching types or non matching indexes within type */
if (widget->dobj.widget.kcontrol_type[i] == type &&
widget->kcontrol_news[i].index == cdata->index) {
kc = widget->kcontrols[i];
break;
}
}
if (!kc)
return;
switch (cdata->cmd) {
case SOF_CTRL_CMD_VOLUME:
case SOF_CTRL_CMD_SWITCH:
sm = (struct soc_mixer_control *)kc->private_value;
scontrol = sm->dobj.private;
break;
case SOF_CTRL_CMD_BINARY:
be = (struct soc_bytes_ext *)kc->private_value;
scontrol = be->dobj.private;
break;
case SOF_CTRL_CMD_ENUM:
se = (struct soc_enum *)kc->private_value;
scontrol = se->dobj.private;
break;
default:
return;
}
expected_size = sizeof(struct sof_ipc_ctrl_data);
switch (cdata->type) {
case SOF_CTRL_TYPE_VALUE_CHAN_GET:
case SOF_CTRL_TYPE_VALUE_CHAN_SET:
expected_size += cdata->num_elems *
sizeof(struct sof_ipc_ctrl_value_chan);
break;
case SOF_CTRL_TYPE_DATA_GET:
case SOF_CTRL_TYPE_DATA_SET:
expected_size += cdata->num_elems + sizeof(struct sof_abi_hdr);
break;
default:
return;
}
if (cdata->rhdr.hdr.size != expected_size) {
dev_err(sdev->dev, "Component notification size mismatch\n");
return;
}
if (cdata->num_elems)
/*
* The message includes the updated value/data, update the
* control's local cache using the received notification
*/
snd_sof_update_control(scontrol, cdata);
else
/* Mark the scontrol that the value/data is changed in SOF */
scontrol->comp_data_dirty = true;
snd_ctl_notify_one(swidget->scomp->card->snd_card, SNDRV_CTL_EVENT_MASK_VALUE, kc, 0);
}
static int sof_ipc3_widget_kcontrol_setup(struct snd_sof_dev *sdev,
struct snd_sof_widget *swidget)
{
struct snd_sof_control *scontrol;
int ret;
/* set up all controls for the widget */
list_for_each_entry(scontrol, &sdev->kcontrol_list, list)
if (scontrol->comp_id == swidget->comp_id) {
/* set kcontrol data in DSP */
ret = sof_ipc3_set_get_kcontrol_data(scontrol, true, false);
if (ret < 0) {
dev_err(sdev->dev,
"kcontrol %d set up failed for widget %s\n",
scontrol->comp_id, swidget->widget->name);
return ret;
}
/*
* Read back the data from the DSP for static widgets.
* This is particularly useful for binary kcontrols
* associated with static pipeline widgets to initialize
* the data size to match that in the DSP.
*/
if (swidget->dynamic_pipeline_widget)
continue;
ret = sof_ipc3_set_get_kcontrol_data(scontrol, false, false);
if (ret < 0)
dev_warn(sdev->dev,
"kcontrol %d read failed for widget %s\n",
scontrol->comp_id, swidget->widget->name);
}
return 0;
}
static int
sof_ipc3_set_up_volume_table(struct snd_sof_control *scontrol, int tlv[SOF_TLV_ITEMS], int size)
{
int i;
/* init the volume table */
scontrol->volume_table = kcalloc(size, sizeof(u32), GFP_KERNEL);
if (!scontrol->volume_table)
return -ENOMEM;
/* populate the volume table */
for (i = 0; i < size ; i++)
scontrol->volume_table[i] = vol_compute_gain(i, tlv);
return 0;
}
const struct sof_ipc_tplg_control_ops tplg_ipc3_control_ops = {
.volume_put = sof_ipc3_volume_put,
.volume_get = sof_ipc3_volume_get,
.switch_put = sof_ipc3_switch_put,
.switch_get = sof_ipc3_switch_get,
.enum_put = sof_ipc3_enum_put,
.enum_get = sof_ipc3_enum_get,
.bytes_put = sof_ipc3_bytes_put,
.bytes_get = sof_ipc3_bytes_get,
.bytes_ext_put = sof_ipc3_bytes_ext_put,
.bytes_ext_get = sof_ipc3_bytes_ext_get,
.bytes_ext_volatile_get = sof_ipc3_bytes_ext_volatile_get,
.update = sof_ipc3_control_update,
.widget_kcontrol_setup = sof_ipc3_widget_kcontrol_setup,
.set_up_volume_table = sof_ipc3_set_up_volume_table,
};
| linux-master | sound/soc/sof/ipc3-control.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/acpi.h>
#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "../intel/common/soc-intel-quirks.h"
#include "ops.h"
#include "sof-acpi-dev.h"
/* platform specific devices */
#include "intel/shim.h"
static char *fw_path;
module_param(fw_path, charp, 0444);
MODULE_PARM_DESC(fw_path, "alternate path for SOF firmware.");
static char *tplg_path;
module_param(tplg_path, charp, 0444);
MODULE_PARM_DESC(tplg_path, "alternate path for SOF topology.");
static int sof_acpi_debug;
module_param_named(sof_acpi_debug, sof_acpi_debug, int, 0444);
MODULE_PARM_DESC(sof_acpi_debug, "SOF ACPI debug options (0x0 all off)");
#define SOF_ACPI_DISABLE_PM_RUNTIME BIT(0)
const struct dev_pm_ops sof_acpi_pm = {
SET_SYSTEM_SLEEP_PM_OPS(snd_sof_suspend, snd_sof_resume)
SET_RUNTIME_PM_OPS(snd_sof_runtime_suspend, snd_sof_runtime_resume,
snd_sof_runtime_idle)
};
EXPORT_SYMBOL_NS(sof_acpi_pm, SND_SOC_SOF_ACPI_DEV);
static void sof_acpi_probe_complete(struct device *dev)
{
dev_dbg(dev, "Completing SOF ACPI probe");
if (sof_acpi_debug & SOF_ACPI_DISABLE_PM_RUNTIME)
return;
/* allow runtime_pm */
pm_runtime_set_autosuspend_delay(dev, SND_SOF_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
}
int sof_acpi_probe(struct platform_device *pdev, const struct sof_dev_desc *desc)
{
struct device *dev = &pdev->dev;
struct snd_sof_pdata *sof_pdata;
dev_dbg(dev, "ACPI DSP detected");
sof_pdata = devm_kzalloc(dev, sizeof(*sof_pdata), GFP_KERNEL);
if (!sof_pdata)
return -ENOMEM;
if (!desc->ops) {
dev_err(dev, "error: no matching ACPI descriptor ops\n");
return -ENODEV;
}
sof_pdata->desc = desc;
sof_pdata->dev = &pdev->dev;
sof_pdata->fw_filename = desc->default_fw_filename[SOF_IPC];
/* alternate fw and tplg filenames ? */
if (fw_path)
sof_pdata->fw_filename_prefix = fw_path;
else
sof_pdata->fw_filename_prefix =
sof_pdata->desc->default_fw_path[SOF_IPC];
if (tplg_path)
sof_pdata->tplg_filename_prefix = tplg_path;
else
sof_pdata->tplg_filename_prefix =
sof_pdata->desc->default_tplg_path[SOF_IPC];
/* set callback to be called on successful device probe to enable runtime_pm */
sof_pdata->sof_probe_complete = sof_acpi_probe_complete;
/* call sof helper for DSP hardware probe */
return snd_sof_device_probe(dev, sof_pdata);
}
EXPORT_SYMBOL_NS(sof_acpi_probe, SND_SOC_SOF_ACPI_DEV);
int sof_acpi_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
if (!(sof_acpi_debug & SOF_ACPI_DISABLE_PM_RUNTIME))
pm_runtime_disable(dev);
/* call sof helper for DSP hardware remove */
snd_sof_device_remove(dev);
return 0;
}
EXPORT_SYMBOL_NS(sof_acpi_remove, SND_SOC_SOF_ACPI_DEV);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/sof-acpi-dev.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2019-2022 Intel Corporation. All rights reserved.
//
// Author: Cezary Rojewski <[email protected]>
//
// SOF client support:
// Ranjani Sridharan <[email protected]>
// Peter Ujfalusi <[email protected]>
//
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/string_helpers.h>
#include <linux/stddef.h>
#include <sound/soc.h>
#include <sound/sof/header.h>
#include "sof-client.h"
#include "sof-client-probes.h"
#define SOF_PROBES_SUSPEND_DELAY_MS 3000
/* only extraction supported for now */
#define SOF_PROBES_NUM_DAI_LINKS 1
#define SOF_PROBES_INVALID_NODE_ID UINT_MAX
static bool __read_mostly sof_probes_enabled;
module_param_named(enable, sof_probes_enabled, bool, 0444);
MODULE_PARM_DESC(enable, "Enable SOF probes support");
static int sof_probes_compr_startup(struct snd_compr_stream *cstream,
struct snd_soc_dai *dai)
{
struct snd_soc_card *card = snd_soc_component_get_drvdata(dai->component);
struct sof_client_dev *cdev = snd_soc_card_get_drvdata(card);
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_host_ops *ops = priv->host_ops;
int ret;
if (sof_client_get_fw_state(cdev) == SOF_FW_CRASHED)
return -ENODEV;
ret = sof_client_core_module_get(cdev);
if (ret)
return ret;
ret = ops->startup(cdev, cstream, dai, &priv->extractor_stream_tag);
if (ret) {
dev_err(dai->dev, "Failed to startup probe stream: %d\n", ret);
priv->extractor_stream_tag = SOF_PROBES_INVALID_NODE_ID;
sof_client_core_module_put(cdev);
}
return ret;
}
static int sof_probes_compr_shutdown(struct snd_compr_stream *cstream,
struct snd_soc_dai *dai)
{
struct snd_soc_card *card = snd_soc_component_get_drvdata(dai->component);
struct sof_client_dev *cdev = snd_soc_card_get_drvdata(card);
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_host_ops *ops = priv->host_ops;
const struct sof_probes_ipc_ops *ipc = priv->ipc_ops;
struct sof_probe_point_desc *desc;
size_t num_desc;
int i, ret;
/* disconnect all probe points */
ret = ipc->points_info(cdev, &desc, &num_desc);
if (ret < 0) {
dev_err(dai->dev, "Failed to get probe points: %d\n", ret);
goto exit;
}
for (i = 0; i < num_desc; i++)
ipc->points_remove(cdev, &desc[i].buffer_id, 1);
kfree(desc);
exit:
ret = ipc->deinit(cdev);
if (ret < 0)
dev_err(dai->dev, "Failed to deinit probe: %d\n", ret);
priv->extractor_stream_tag = SOF_PROBES_INVALID_NODE_ID;
snd_compr_free_pages(cstream);
ret = ops->shutdown(cdev, cstream, dai);
sof_client_core_module_put(cdev);
return ret;
}
static int sof_probes_compr_set_params(struct snd_compr_stream *cstream,
struct snd_compr_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_card *card = snd_soc_component_get_drvdata(dai->component);
struct sof_client_dev *cdev = snd_soc_card_get_drvdata(card);
struct snd_compr_runtime *rtd = cstream->runtime;
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_host_ops *ops = priv->host_ops;
const struct sof_probes_ipc_ops *ipc = priv->ipc_ops;
int ret;
cstream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV_SG;
cstream->dma_buffer.dev.dev = sof_client_get_dma_dev(cdev);
ret = snd_compr_malloc_pages(cstream, rtd->buffer_size);
if (ret < 0)
return ret;
ret = ops->set_params(cdev, cstream, params, dai);
if (ret)
return ret;
ret = ipc->init(cdev, priv->extractor_stream_tag, rtd->dma_bytes);
if (ret < 0) {
dev_err(dai->dev, "Failed to init probe: %d\n", ret);
return ret;
}
return 0;
}
static int sof_probes_compr_trigger(struct snd_compr_stream *cstream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_card *card = snd_soc_component_get_drvdata(dai->component);
struct sof_client_dev *cdev = snd_soc_card_get_drvdata(card);
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_host_ops *ops = priv->host_ops;
return ops->trigger(cdev, cstream, cmd, dai);
}
static int sof_probes_compr_pointer(struct snd_compr_stream *cstream,
struct snd_compr_tstamp *tstamp,
struct snd_soc_dai *dai)
{
struct snd_soc_card *card = snd_soc_component_get_drvdata(dai->component);
struct sof_client_dev *cdev = snd_soc_card_get_drvdata(card);
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_host_ops *ops = priv->host_ops;
return ops->pointer(cdev, cstream, tstamp, dai);
}
static const struct snd_soc_cdai_ops sof_probes_compr_ops = {
.startup = sof_probes_compr_startup,
.shutdown = sof_probes_compr_shutdown,
.set_params = sof_probes_compr_set_params,
.trigger = sof_probes_compr_trigger,
.pointer = sof_probes_compr_pointer,
};
static int sof_probes_compr_copy(struct snd_soc_component *component,
struct snd_compr_stream *cstream,
char __user *buf, size_t count)
{
struct snd_compr_runtime *rtd = cstream->runtime;
unsigned int offset, n;
void *ptr;
int ret;
if (count > rtd->buffer_size)
count = rtd->buffer_size;
div_u64_rem(rtd->total_bytes_transferred, rtd->buffer_size, &offset);
ptr = rtd->dma_area + offset;
n = rtd->buffer_size - offset;
if (count < n) {
ret = copy_to_user(buf, ptr, count);
} else {
ret = copy_to_user(buf, ptr, n);
ret += copy_to_user(buf + n, rtd->dma_area, count - n);
}
if (ret)
return count - ret;
return count;
}
static const struct snd_compress_ops sof_probes_compressed_ops = {
.copy = sof_probes_compr_copy,
};
static ssize_t sof_probes_dfs_points_read(struct file *file, char __user *to,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_probes_priv *priv = cdev->data;
struct device *dev = &cdev->auxdev.dev;
struct sof_probe_point_desc *desc;
const struct sof_probes_ipc_ops *ipc = priv->ipc_ops;
int remaining, offset;
size_t num_desc;
char *buf;
int i, ret, err;
if (priv->extractor_stream_tag == SOF_PROBES_INVALID_NODE_ID) {
dev_warn(dev, "no extractor stream running\n");
return -ENOENT;
}
buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(dev, "debugfs read failed to resume %d\n", ret);
goto exit;
}
ret = ipc->points_info(cdev, &desc, &num_desc);
if (ret < 0)
goto pm_error;
for (i = 0; i < num_desc; i++) {
offset = strlen(buf);
remaining = PAGE_SIZE - offset;
ret = snprintf(buf + offset, remaining,
"Id: %#010x Purpose: %u Node id: %#x\n",
desc[i].buffer_id, desc[i].purpose, desc[i].stream_tag);
if (ret < 0 || ret >= remaining) {
/* truncate the output buffer at the last full line */
buf[offset] = '\0';
break;
}
}
ret = simple_read_from_buffer(to, count, ppos, buf, strlen(buf));
kfree(desc);
pm_error:
pm_runtime_mark_last_busy(dev);
err = pm_runtime_put_autosuspend(dev);
if (err < 0)
dev_err_ratelimited(dev, "debugfs read failed to idle %d\n", err);
exit:
kfree(buf);
return ret;
}
static ssize_t
sof_probes_dfs_points_write(struct file *file, const char __user *from,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_ipc_ops *ipc = priv->ipc_ops;
struct device *dev = &cdev->auxdev.dev;
struct sof_probe_point_desc *desc;
u32 num_elems, *array;
size_t bytes;
int ret, err;
if (priv->extractor_stream_tag == SOF_PROBES_INVALID_NODE_ID) {
dev_warn(dev, "no extractor stream running\n");
return -ENOENT;
}
ret = parse_int_array_user(from, count, (int **)&array);
if (ret < 0)
return ret;
num_elems = *array;
bytes = sizeof(*array) * num_elems;
if (bytes % sizeof(*desc)) {
ret = -EINVAL;
goto exit;
}
desc = (struct sof_probe_point_desc *)&array[1];
ret = pm_runtime_resume_and_get(dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(dev, "debugfs write failed to resume %d\n", ret);
goto exit;
}
ret = ipc->points_add(cdev, desc, bytes / sizeof(*desc));
if (!ret)
ret = count;
pm_runtime_mark_last_busy(dev);
err = pm_runtime_put_autosuspend(dev);
if (err < 0)
dev_err_ratelimited(dev, "debugfs write failed to idle %d\n", err);
exit:
kfree(array);
return ret;
}
static const struct file_operations sof_probes_points_fops = {
.open = simple_open,
.read = sof_probes_dfs_points_read,
.write = sof_probes_dfs_points_write,
.llseek = default_llseek,
.owner = THIS_MODULE,
};
static ssize_t
sof_probes_dfs_points_remove_write(struct file *file, const char __user *from,
size_t count, loff_t *ppos)
{
struct sof_client_dev *cdev = file->private_data;
struct sof_probes_priv *priv = cdev->data;
const struct sof_probes_ipc_ops *ipc = priv->ipc_ops;
struct device *dev = &cdev->auxdev.dev;
int ret, err;
u32 *array;
if (priv->extractor_stream_tag == SOF_PROBES_INVALID_NODE_ID) {
dev_warn(dev, "no extractor stream running\n");
return -ENOENT;
}
ret = parse_int_array_user(from, count, (int **)&array);
if (ret < 0)
return ret;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
dev_err_ratelimited(dev, "debugfs write failed to resume %d\n", ret);
goto exit;
}
ret = ipc->points_remove(cdev, &array[1], array[0]);
if (!ret)
ret = count;
pm_runtime_mark_last_busy(dev);
err = pm_runtime_put_autosuspend(dev);
if (err < 0)
dev_err_ratelimited(dev, "debugfs write failed to idle %d\n", err);
exit:
kfree(array);
return ret;
}
static const struct file_operations sof_probes_points_remove_fops = {
.open = simple_open,
.write = sof_probes_dfs_points_remove_write,
.llseek = default_llseek,
.owner = THIS_MODULE,
};
static const struct snd_soc_dai_ops sof_probes_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static struct snd_soc_dai_driver sof_probes_dai_drv[] = {
{
.name = "Probe Extraction CPU DAI",
.ops = &sof_probes_dai_ops,
.cops = &sof_probes_compr_ops,
.capture = {
.stream_name = "Probe Extraction",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
},
},
};
static const struct snd_soc_component_driver sof_probes_component = {
.name = "sof-probes-component",
.compress_ops = &sof_probes_compressed_ops,
.module_get_upon_open = 1,
.legacy_dai_naming = 1,
};
SND_SOC_DAILINK_DEF(dummy, DAILINK_COMP_ARRAY(COMP_DUMMY()));
static int sof_probes_client_probe(struct auxiliary_device *auxdev,
const struct auxiliary_device_id *id)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct dentry *dfsroot = sof_client_get_debugfs_root(cdev);
struct device *dev = &auxdev->dev;
struct snd_soc_dai_link_component platform_component[] = {
{
.name = dev_name(dev),
}
};
struct snd_soc_card *card;
struct sof_probes_priv *priv;
struct snd_soc_dai_link_component *cpus;
struct sof_probes_host_ops *ops;
struct snd_soc_dai_link *links;
int ret;
/* do not set up the probes support if it is not enabled */
if (!sof_probes_enabled)
return -ENXIO;
ops = dev_get_platdata(dev);
if (!ops) {
dev_err(dev, "missing platform data\n");
return -ENODEV;
}
if (!ops->startup || !ops->shutdown || !ops->set_params || !ops->trigger ||
!ops->pointer) {
dev_err(dev, "missing platform callback(s)\n");
return -ENODEV;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->host_ops = ops;
switch (sof_client_get_ipc_type(cdev)) {
#ifdef CONFIG_SND_SOC_SOF_INTEL_IPC4
case SOF_INTEL_IPC4:
priv->ipc_ops = &ipc4_probe_ops;
break;
#endif
#ifdef CONFIG_SND_SOC_SOF_IPC3
case SOF_IPC:
priv->ipc_ops = &ipc3_probe_ops;
break;
#endif
default:
dev_err(dev, "Matching IPC ops not found.");
return -ENODEV;
}
cdev->data = priv;
/* register probes component driver and dai */
ret = devm_snd_soc_register_component(dev, &sof_probes_component,
sof_probes_dai_drv,
ARRAY_SIZE(sof_probes_dai_drv));
if (ret < 0) {
dev_err(dev, "failed to register SOF probes DAI driver %d\n", ret);
return ret;
}
/* set client data */
priv->extractor_stream_tag = SOF_PROBES_INVALID_NODE_ID;
/* create read-write probes_points debugfs entry */
priv->dfs_points = debugfs_create_file("probe_points", 0644, dfsroot,
cdev, &sof_probes_points_fops);
/* create read-write probe_points_remove debugfs entry */
priv->dfs_points_remove = debugfs_create_file("probe_points_remove", 0644,
dfsroot, cdev,
&sof_probes_points_remove_fops);
links = devm_kcalloc(dev, SOF_PROBES_NUM_DAI_LINKS, sizeof(*links), GFP_KERNEL);
cpus = devm_kcalloc(dev, SOF_PROBES_NUM_DAI_LINKS, sizeof(*cpus), GFP_KERNEL);
if (!links || !cpus) {
debugfs_remove(priv->dfs_points);
debugfs_remove(priv->dfs_points_remove);
return -ENOMEM;
}
/* extraction DAI link */
links[0].name = "Compress Probe Capture";
links[0].id = 0;
links[0].cpus = &cpus[0];
links[0].num_cpus = 1;
links[0].cpus->dai_name = "Probe Extraction CPU DAI";
links[0].codecs = dummy;
links[0].num_codecs = 1;
links[0].platforms = platform_component;
links[0].num_platforms = ARRAY_SIZE(platform_component);
links[0].nonatomic = 1;
card = &priv->card;
card->dev = dev;
card->name = "sof-probes";
card->owner = THIS_MODULE;
card->num_links = SOF_PROBES_NUM_DAI_LINKS;
card->dai_link = links;
/* set idle_bias_off to prevent the core from resuming the card->dev */
card->dapm.idle_bias_off = true;
snd_soc_card_set_drvdata(card, cdev);
ret = devm_snd_soc_register_card(dev, card);
if (ret < 0) {
debugfs_remove(priv->dfs_points);
debugfs_remove(priv->dfs_points_remove);
dev_err(dev, "Probes card register failed %d\n", ret);
return ret;
}
/* enable runtime PM */
pm_runtime_set_autosuspend_delay(dev, SOF_PROBES_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
pm_runtime_enable(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_idle(dev);
return 0;
}
static void sof_probes_client_remove(struct auxiliary_device *auxdev)
{
struct sof_client_dev *cdev = auxiliary_dev_to_sof_client_dev(auxdev);
struct sof_probes_priv *priv = cdev->data;
if (!sof_probes_enabled)
return;
pm_runtime_disable(&auxdev->dev);
debugfs_remove(priv->dfs_points);
debugfs_remove(priv->dfs_points_remove);
}
static const struct auxiliary_device_id sof_probes_client_id_table[] = {
{ .name = "snd_sof.hda-probes", },
{ .name = "snd_sof.acp-probes", },
{},
};
MODULE_DEVICE_TABLE(auxiliary, sof_probes_client_id_table);
/* driver name will be set based on KBUILD_MODNAME */
static struct auxiliary_driver sof_probes_client_drv = {
.probe = sof_probes_client_probe,
.remove = sof_probes_client_remove,
.id_table = sof_probes_client_id_table,
};
module_auxiliary_driver(sof_probes_client_drv);
MODULE_DESCRIPTION("SOF Probes Client Driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(SND_SOC_SOF_CLIENT);
| linux-master | sound/soc/sof/sof-client-probes.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2019 Intel Corporation. All rights reserved.
//
// Authors: Guennadi Liakhovetski <[email protected]>
/* Generic SOF IPC code */
#include <linux/device.h>
#include <linux/export.h>
#include <linux/module.h>
#include <linux/types.h>
#include <sound/pcm.h>
#include <sound/sof/stream.h>
#include "ops.h"
#include "sof-priv.h"
#include "sof-audio.h"
struct sof_stream {
size_t posn_offset;
};
/* Mailbox-based Generic IPC implementation */
int sof_ipc_msg_data(struct snd_sof_dev *sdev,
struct snd_sof_pcm_stream *sps,
void *p, size_t sz)
{
if (!sps || !sdev->stream_box.size) {
snd_sof_dsp_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
} else {
size_t posn_offset;
if (sps->substream) {
struct sof_stream *stream = sps->substream->runtime->private_data;
/* The stream might already be closed */
if (!stream)
return -ESTRPIPE;
posn_offset = stream->posn_offset;
} else {
struct sof_compr_stream *sstream = sps->cstream->runtime->private_data;
if (!sstream)
return -ESTRPIPE;
posn_offset = sstream->posn_offset;
}
snd_sof_dsp_mailbox_read(sdev, posn_offset, p, sz);
}
return 0;
}
EXPORT_SYMBOL(sof_ipc_msg_data);
int sof_set_stream_data_offset(struct snd_sof_dev *sdev,
struct snd_sof_pcm_stream *sps,
size_t posn_offset)
{
/* check if offset is overflow or it is not aligned */
if (posn_offset > sdev->stream_box.size ||
posn_offset % sizeof(struct sof_ipc_stream_posn) != 0)
return -EINVAL;
posn_offset += sdev->stream_box.offset;
if (sps->substream) {
struct sof_stream *stream = sps->substream->runtime->private_data;
stream->posn_offset = posn_offset;
dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
sps->substream->stream, posn_offset);
} else if (sps->cstream) {
struct sof_compr_stream *sstream = sps->cstream->runtime->private_data;
sstream->posn_offset = posn_offset;
dev_dbg(sdev->dev, "compr: stream dir %d, posn mailbox offset is %zu",
sps->cstream->direction, posn_offset);
} else {
dev_err(sdev->dev, "No stream opened");
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL(sof_set_stream_data_offset);
int sof_stream_pcm_open(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
struct sof_stream *stream = kmalloc(sizeof(*stream), GFP_KERNEL);
if (!stream)
return -ENOMEM;
/* binding pcm substream to hda stream */
substream->runtime->private_data = stream;
/* align to DMA minimum transfer size */
snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
/* avoid circular buffer wrap in middle of period */
snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
return 0;
}
EXPORT_SYMBOL(sof_stream_pcm_open);
int sof_stream_pcm_close(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
struct sof_stream *stream = substream->runtime->private_data;
substream->runtime->private_data = NULL;
kfree(stream);
return 0;
}
EXPORT_SYMBOL(sof_stream_pcm_close);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/stream-ipc.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/module.h>
#include <sound/sof.h>
#include "sof-audio.h"
#include "sof-priv.h"
static struct snd_soc_card sof_nocodec_card = {
.name = "nocodec", /* the sof- prefix is added by the core */
.topology_shortname = "sof-nocodec",
.owner = THIS_MODULE
};
static int sof_nocodec_bes_setup(struct device *dev,
struct snd_soc_dai_driver *drv,
struct snd_soc_dai_link *links,
int link_num, struct snd_soc_card *card)
{
struct snd_soc_dai_link_component *dlc;
int i;
if (!drv || !links || !card)
return -EINVAL;
/* set up BE dai_links */
for (i = 0; i < link_num; i++) {
dlc = devm_kcalloc(dev, 2, sizeof(*dlc), GFP_KERNEL);
if (!dlc)
return -ENOMEM;
links[i].name = devm_kasprintf(dev, GFP_KERNEL,
"NoCodec-%d", i);
if (!links[i].name)
return -ENOMEM;
links[i].stream_name = links[i].name;
links[i].cpus = &dlc[0];
links[i].codecs = &asoc_dummy_dlc;
links[i].platforms = &dlc[1];
links[i].num_cpus = 1;
links[i].num_codecs = 1;
links[i].num_platforms = 1;
links[i].id = i;
links[i].no_pcm = 1;
links[i].cpus->dai_name = drv[i].name;
links[i].platforms->name = dev_name(dev->parent);
if (drv[i].playback.channels_min)
links[i].dpcm_playback = 1;
if (drv[i].capture.channels_min)
links[i].dpcm_capture = 1;
links[i].be_hw_params_fixup = sof_pcm_dai_link_fixup;
}
card->dai_link = links;
card->num_links = link_num;
return 0;
}
static int sof_nocodec_setup(struct device *dev,
u32 num_dai_drivers,
struct snd_soc_dai_driver *dai_drivers)
{
struct snd_soc_dai_link *links;
/* create dummy BE dai_links */
links = devm_kcalloc(dev, num_dai_drivers, sizeof(struct snd_soc_dai_link), GFP_KERNEL);
if (!links)
return -ENOMEM;
return sof_nocodec_bes_setup(dev, dai_drivers, links, num_dai_drivers, &sof_nocodec_card);
}
static int sof_nocodec_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &sof_nocodec_card;
struct snd_soc_acpi_mach *mach;
int ret;
card->dev = &pdev->dev;
card->topology_shortname_created = true;
mach = pdev->dev.platform_data;
ret = sof_nocodec_setup(card->dev, mach->mach_params.num_dai_drivers,
mach->mach_params.dai_drivers);
if (ret < 0)
return ret;
return devm_snd_soc_register_card(&pdev->dev, card);
}
static struct platform_driver sof_nocodec_audio = {
.probe = sof_nocodec_probe,
.driver = {
.name = "sof-nocodec",
.pm = &snd_soc_pm_ops,
},
};
module_platform_driver(sof_nocodec_audio)
MODULE_DESCRIPTION("ASoC sof nocodec");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("platform:sof-nocodec");
| linux-master | sound/soc/sof/nocodec.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
#include <linux/firmware.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc3-priv.h"
#include "ops.h"
static int ipc3_fw_ext_man_get_version(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
{
const struct sof_ext_man_fw_version *v =
container_of(hdr, struct sof_ext_man_fw_version, hdr);
memcpy(&sdev->fw_ready.version, &v->version, sizeof(v->version));
sdev->fw_ready.flags = v->flags;
/* log ABI versions and check FW compatibility */
return sof_ipc3_validate_fw_version(sdev);
}
static int ipc3_fw_ext_man_get_windows(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
{
const struct sof_ext_man_window *w;
w = container_of(hdr, struct sof_ext_man_window, hdr);
return sof_ipc3_get_ext_windows(sdev, &w->ipc_window.ext_hdr);
}
static int ipc3_fw_ext_man_get_cc_info(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
{
const struct sof_ext_man_cc_version *cc;
cc = container_of(hdr, struct sof_ext_man_cc_version, hdr);
return sof_ipc3_get_cc_info(sdev, &cc->cc_version.ext_hdr);
}
static int ipc3_fw_ext_man_get_dbg_abi_info(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
{
const struct ext_man_dbg_abi *dbg_abi =
container_of(hdr, struct ext_man_dbg_abi, hdr);
if (sdev->first_boot)
dev_dbg(sdev->dev,
"Firmware: DBG_ABI %d:%d:%d\n",
SOF_ABI_VERSION_MAJOR(dbg_abi->dbg_abi.abi_dbg_version),
SOF_ABI_VERSION_MINOR(dbg_abi->dbg_abi.abi_dbg_version),
SOF_ABI_VERSION_PATCH(dbg_abi->dbg_abi.abi_dbg_version));
return 0;
}
static int ipc3_fw_ext_man_get_config_data(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
{
const struct sof_ext_man_config_data *config =
container_of(hdr, struct sof_ext_man_config_data, hdr);
const struct sof_config_elem *elem;
int elems_counter;
int elems_size;
int ret = 0;
int i;
/* calculate elements counter */
elems_size = config->hdr.size - sizeof(struct sof_ext_man_elem_header);
elems_counter = elems_size / sizeof(struct sof_config_elem);
dev_dbg(sdev->dev, "manifest can hold up to %d config elements\n", elems_counter);
for (i = 0; i < elems_counter; ++i) {
elem = &config->elems[i];
dev_dbg(sdev->dev, "get index %d token %d val %d\n",
i, elem->token, elem->value);
switch (elem->token) {
case SOF_EXT_MAN_CONFIG_EMPTY:
/* unused memory space is zero filled - mapped to EMPTY elements */
break;
case SOF_EXT_MAN_CONFIG_IPC_MSG_SIZE:
/* TODO: use ipc msg size from config data */
break;
case SOF_EXT_MAN_CONFIG_MEMORY_USAGE_SCAN:
if (sdev->first_boot && elem->value)
ret = snd_sof_dbg_memory_info_init(sdev);
break;
default:
dev_info(sdev->dev,
"Unknown firmware configuration token %d value %d",
elem->token, elem->value);
break;
}
if (ret < 0) {
dev_err(sdev->dev,
"%s: processing failed for token %d value %#x, %d\n",
__func__, elem->token, elem->value, ret);
return ret;
}
}
return 0;
}
static ssize_t ipc3_fw_ext_man_size(struct snd_sof_dev *sdev, const struct firmware *fw)
{
const struct sof_ext_man_header *head;
head = (struct sof_ext_man_header *)fw->data;
/*
* assert fw size is big enough to contain extended manifest header,
* it prevents from reading unallocated memory from `head` in following
* step.
*/
if (fw->size < sizeof(*head))
return -EINVAL;
/*
* When fw points to extended manifest,
* then first u32 must be equal SOF_EXT_MAN_MAGIC_NUMBER.
*/
if (head->magic == SOF_EXT_MAN_MAGIC_NUMBER)
return head->full_size;
/* otherwise given fw don't have an extended manifest */
dev_dbg(sdev->dev, "Unexpected extended manifest magic number: %#x\n",
head->magic);
return 0;
}
static size_t sof_ipc3_fw_parse_ext_man(struct snd_sof_dev *sdev)
{
const struct firmware *fw = sdev->basefw.fw;
const struct sof_ext_man_elem_header *elem_hdr;
const struct sof_ext_man_header *head;
ssize_t ext_man_size;
ssize_t remaining;
uintptr_t iptr;
int ret = 0;
head = (struct sof_ext_man_header *)fw->data;
remaining = head->full_size - head->header_size;
ext_man_size = ipc3_fw_ext_man_size(sdev, fw);
/* Assert firmware starts with extended manifest */
if (ext_man_size <= 0)
return ext_man_size;
/* incompatible version */
if (SOF_EXT_MAN_VERSION_INCOMPATIBLE(SOF_EXT_MAN_VERSION,
head->header_version)) {
dev_err(sdev->dev,
"extended manifest version %#x differ from used %#x\n",
head->header_version, SOF_EXT_MAN_VERSION);
return -EINVAL;
}
/* get first extended manifest element header */
iptr = (uintptr_t)fw->data + head->header_size;
while (remaining > sizeof(*elem_hdr)) {
elem_hdr = (struct sof_ext_man_elem_header *)iptr;
dev_dbg(sdev->dev, "found sof_ext_man header type %d size %#x\n",
elem_hdr->type, elem_hdr->size);
if (elem_hdr->size < sizeof(*elem_hdr) ||
elem_hdr->size > remaining) {
dev_err(sdev->dev,
"invalid sof_ext_man header size, type %d size %#x\n",
elem_hdr->type, elem_hdr->size);
return -EINVAL;
}
/* process structure data */
switch (elem_hdr->type) {
case SOF_EXT_MAN_ELEM_FW_VERSION:
ret = ipc3_fw_ext_man_get_version(sdev, elem_hdr);
break;
case SOF_EXT_MAN_ELEM_WINDOW:
ret = ipc3_fw_ext_man_get_windows(sdev, elem_hdr);
break;
case SOF_EXT_MAN_ELEM_CC_VERSION:
ret = ipc3_fw_ext_man_get_cc_info(sdev, elem_hdr);
break;
case SOF_EXT_MAN_ELEM_DBG_ABI:
ret = ipc3_fw_ext_man_get_dbg_abi_info(sdev, elem_hdr);
break;
case SOF_EXT_MAN_ELEM_CONFIG_DATA:
ret = ipc3_fw_ext_man_get_config_data(sdev, elem_hdr);
break;
case SOF_EXT_MAN_ELEM_PLATFORM_CONFIG_DATA:
ret = snd_sof_dsp_parse_platform_ext_manifest(sdev, elem_hdr);
break;
default:
dev_info(sdev->dev,
"unknown sof_ext_man header type %d size %#x\n",
elem_hdr->type, elem_hdr->size);
break;
}
if (ret < 0) {
dev_err(sdev->dev,
"failed to parse sof_ext_man header type %d size %#x\n",
elem_hdr->type, elem_hdr->size);
return ret;
}
remaining -= elem_hdr->size;
iptr += elem_hdr->size;
}
if (remaining) {
dev_err(sdev->dev, "error: sof_ext_man header is inconsistent\n");
return -EINVAL;
}
return ext_man_size;
}
/* generic module parser for mmaped DSPs */
static int sof_ipc3_parse_module_memcpy(struct snd_sof_dev *sdev,
struct snd_sof_mod_hdr *module)
{
struct snd_sof_blk_hdr *block;
int count, ret;
u32 offset;
size_t remaining;
dev_dbg(sdev->dev, "new module size %#x blocks %#x type %#x\n",
module->size, module->num_blocks, module->type);
block = (struct snd_sof_blk_hdr *)((u8 *)module + sizeof(*module));
/* module->size doesn't include header size */
remaining = module->size;
for (count = 0; count < module->num_blocks; count++) {
/* check for wrap */
if (remaining < sizeof(*block)) {
dev_err(sdev->dev, "not enough data remaining\n");
return -EINVAL;
}
/* minus header size of block */
remaining -= sizeof(*block);
if (block->size == 0) {
dev_warn(sdev->dev,
"warning: block %d size zero\n", count);
dev_warn(sdev->dev, " type %#x offset %#x\n",
block->type, block->offset);
continue;
}
switch (block->type) {
case SOF_FW_BLK_TYPE_RSRVD0:
case SOF_FW_BLK_TYPE_ROM...SOF_FW_BLK_TYPE_RSRVD14:
continue; /* not handled atm */
case SOF_FW_BLK_TYPE_IRAM:
case SOF_FW_BLK_TYPE_DRAM:
case SOF_FW_BLK_TYPE_SRAM:
offset = block->offset;
break;
default:
dev_err(sdev->dev, "%s: bad type %#x for block %#x\n",
__func__, block->type, count);
return -EINVAL;
}
dev_dbg(sdev->dev, "block %d type %#x size %#x ==> offset %#x\n",
count, block->type, block->size, offset);
/* checking block->size to avoid unaligned access */
if (block->size % sizeof(u32)) {
dev_err(sdev->dev, "%s: invalid block size %#x\n",
__func__, block->size);
return -EINVAL;
}
ret = snd_sof_dsp_block_write(sdev, block->type, offset,
block + 1, block->size);
if (ret < 0) {
dev_err(sdev->dev, "%s: write to block type %#x failed\n",
__func__, block->type);
return ret;
}
if (remaining < block->size) {
dev_err(sdev->dev, "%s: not enough data remaining\n", __func__);
return -EINVAL;
}
/* minus body size of block */
remaining -= block->size;
/* next block */
block = (struct snd_sof_blk_hdr *)((u8 *)block + sizeof(*block)
+ block->size);
}
return 0;
}
static int sof_ipc3_load_fw_to_dsp(struct snd_sof_dev *sdev)
{
u32 payload_offset = sdev->basefw.payload_offset;
const struct firmware *fw = sdev->basefw.fw;
struct snd_sof_fw_header *header;
struct snd_sof_mod_hdr *module;
int (*load_module)(struct snd_sof_dev *sof_dev, struct snd_sof_mod_hdr *hdr);
size_t remaining;
int ret, count;
if (!fw)
return -EINVAL;
header = (struct snd_sof_fw_header *)(fw->data + payload_offset);
load_module = sof_ops(sdev)->load_module;
if (!load_module) {
dev_dbg(sdev->dev, "Using generic module loading\n");
load_module = sof_ipc3_parse_module_memcpy;
} else {
dev_dbg(sdev->dev, "Using custom module loading\n");
}
/* parse each module */
module = (struct snd_sof_mod_hdr *)(fw->data + payload_offset + sizeof(*header));
remaining = fw->size - sizeof(*header) - payload_offset;
/* check for wrap */
if (remaining > fw->size) {
dev_err(sdev->dev, "%s: fw size smaller than header size\n", __func__);
return -EINVAL;
}
for (count = 0; count < header->num_modules; count++) {
/* check for wrap */
if (remaining < sizeof(*module)) {
dev_err(sdev->dev, "%s: not enough data for a module\n",
__func__);
return -EINVAL;
}
/* minus header size of module */
remaining -= sizeof(*module);
/* module */
ret = load_module(sdev, module);
if (ret < 0) {
dev_err(sdev->dev, "%s: invalid module %d\n", __func__, count);
return ret;
}
if (remaining < module->size) {
dev_err(sdev->dev, "%s: not enough data remaining\n", __func__);
return -EINVAL;
}
/* minus body size of module */
remaining -= module->size;
module = (struct snd_sof_mod_hdr *)((u8 *)module +
sizeof(*module) + module->size);
}
return 0;
}
static int sof_ipc3_validate_firmware(struct snd_sof_dev *sdev)
{
u32 payload_offset = sdev->basefw.payload_offset;
const struct firmware *fw = sdev->basefw.fw;
struct snd_sof_fw_header *header;
size_t fw_size = fw->size - payload_offset;
if (fw->size <= payload_offset) {
dev_err(sdev->dev,
"firmware size must be greater than firmware offset\n");
return -EINVAL;
}
/* Read the header information from the data pointer */
header = (struct snd_sof_fw_header *)(fw->data + payload_offset);
/* verify FW sig */
if (strncmp(header->sig, SND_SOF_FW_SIG, SND_SOF_FW_SIG_SIZE) != 0) {
dev_err(sdev->dev, "invalid firmware signature\n");
return -EINVAL;
}
/* check size is valid */
if (fw_size != header->file_size + sizeof(*header)) {
dev_err(sdev->dev,
"invalid filesize mismatch got 0x%zx expected 0x%zx\n",
fw_size, header->file_size + sizeof(*header));
return -EINVAL;
}
dev_dbg(sdev->dev, "header size=0x%x modules=0x%x abi=0x%x size=%zu\n",
header->file_size, header->num_modules,
header->abi, sizeof(*header));
return 0;
}
const struct sof_ipc_fw_loader_ops ipc3_loader_ops = {
.validate = sof_ipc3_validate_firmware,
.parse_ext_manifest = sof_ipc3_fw_parse_ext_man,
.load_fw_to_dsp = sof_ipc3_load_fw_to_dsp,
};
| linux-master | sound/soc/sof/ipc3-loader.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2022 Intel Corporation. All rights reserved.
//
// Author: Keyon Jie <[email protected]>
//
#include <asm/unaligned.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/device.h>
#include <sound/memalloc.h>
#include <linux/module.h>
#include "sof-utils.h"
/*
* Generic buffer page table creation.
* Take the each physical page address and drop the least significant unused
* bits from each (based on PAGE_SIZE). Then pack valid page address bits
* into compressed page table.
*/
int snd_sof_create_page_table(struct device *dev,
struct snd_dma_buffer *dmab,
unsigned char *page_table, size_t size)
{
int i, pages;
pages = snd_sgbuf_aligned_pages(size);
dev_dbg(dev, "generating page table for %p size 0x%zx pages %d\n",
dmab->area, size, pages);
for (i = 0; i < pages; i++) {
/*
* The number of valid address bits for each page is 20.
* idx determines the byte position within page_table
* where the current page's address is stored
* in the compressed page_table.
* This can be calculated by multiplying the page number by 2.5.
*/
u32 idx = (5 * i) >> 1;
u32 pfn = snd_sgbuf_get_addr(dmab, i * PAGE_SIZE) >> PAGE_SHIFT;
u8 *pg_table;
pg_table = (u8 *)(page_table + idx);
/*
* pagetable compression:
* byte 0 byte 1 byte 2 byte 3 byte 4 byte 5
* ___________pfn 0__________ __________pfn 1___________ _pfn 2...
* .... .... .... .... .... .... .... .... .... .... ....
* It is created by:
* 1. set current location to 0, PFN index i to 0
* 2. put pfn[i] at current location in Little Endian byte order
* 3. calculate an intermediate value as
* x = (pfn[i+1] << 4) | (pfn[i] & 0xf)
* 4. put x at offset (current location + 2) in LE byte order
* 5. increment current location by 5 bytes, increment i by 2
* 6. continue to (2)
*/
if (i & 1)
put_unaligned_le32((pg_table[0] & 0xf) | pfn << 4,
pg_table);
else
put_unaligned_le32(pfn, pg_table);
}
return pages;
}
EXPORT_SYMBOL(snd_sof_create_page_table);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/sof-utils.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
// Generic IPC layer that can work over MMIO and SPI/I2C. PHY layer provided
// by platform driver code.
//
#include <linux/mutex.h>
#include <linux/types.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ops.h"
/**
* sof_ipc_send_msg - generic function to prepare and send one IPC message
* @sdev: pointer to SOF core device struct
* @msg_data: pointer to a message to send
* @msg_bytes: number of bytes in the message
* @reply_bytes: number of bytes available for the reply.
* The buffer for the reply data is not passed to this
* function, the available size is an information for the
* reply handling functions.
*
* On success the function returns 0, otherwise negative error number.
*
* Note: higher level sdev->ipc->tx_mutex must be held to make sure that
* transfers are synchronized.
*/
int sof_ipc_send_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
size_t reply_bytes)
{
struct snd_sof_ipc *ipc = sdev->ipc;
struct snd_sof_ipc_msg *msg;
int ret;
if (ipc->disable_ipc_tx || sdev->fw_state != SOF_FW_BOOT_COMPLETE)
return -ENODEV;
/*
* The spin-lock is needed to protect message objects against other
* atomic contexts.
*/
spin_lock_irq(&sdev->ipc_lock);
/* initialise the message */
msg = &ipc->msg;
/* attach message data */
msg->msg_data = msg_data;
msg->msg_size = msg_bytes;
msg->reply_size = reply_bytes;
msg->reply_error = 0;
sdev->msg = msg;
ret = snd_sof_dsp_send_msg(sdev, msg);
/* Next reply that we receive will be related to this message */
if (!ret)
msg->ipc_complete = false;
spin_unlock_irq(&sdev->ipc_lock);
return ret;
}
/* send IPC message from host to DSP */
int sof_ipc_tx_message(struct snd_sof_ipc *ipc, void *msg_data, size_t msg_bytes,
void *reply_data, size_t reply_bytes)
{
if (msg_bytes > ipc->max_payload_size ||
reply_bytes > ipc->max_payload_size)
return -ENOBUFS;
return ipc->ops->tx_msg(ipc->sdev, msg_data, msg_bytes, reply_data,
reply_bytes, false);
}
EXPORT_SYMBOL(sof_ipc_tx_message);
/* IPC set or get data from host to DSP */
int sof_ipc_set_get_data(struct snd_sof_ipc *ipc, void *msg_data,
size_t msg_bytes, bool set)
{
return ipc->ops->set_get_data(ipc->sdev, msg_data, msg_bytes, set);
}
EXPORT_SYMBOL(sof_ipc_set_get_data);
/*
* send IPC message from host to DSP without modifying the DSP state.
* This will be used for IPC's that can be handled by the DSP
* even in a low-power D0 substate.
*/
int sof_ipc_tx_message_no_pm(struct snd_sof_ipc *ipc, void *msg_data, size_t msg_bytes,
void *reply_data, size_t reply_bytes)
{
if (msg_bytes > ipc->max_payload_size ||
reply_bytes > ipc->max_payload_size)
return -ENOBUFS;
return ipc->ops->tx_msg(ipc->sdev, msg_data, msg_bytes, reply_data,
reply_bytes, true);
}
EXPORT_SYMBOL(sof_ipc_tx_message_no_pm);
/* Generic helper function to retrieve the reply */
void snd_sof_ipc_get_reply(struct snd_sof_dev *sdev)
{
/*
* Sometimes, there is unexpected reply ipc arriving. The reply
* ipc belongs to none of the ipcs sent from driver.
* In this case, the driver must ignore the ipc.
*/
if (!sdev->msg) {
dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
return;
}
sdev->msg->reply_error = sdev->ipc->ops->get_reply(sdev);
}
EXPORT_SYMBOL(snd_sof_ipc_get_reply);
/* handle reply message from DSP */
void snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id)
{
struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
if (msg->ipc_complete) {
dev_dbg(sdev->dev,
"no reply expected, received 0x%x, will be ignored",
msg_id);
return;
}
/* wake up and return the error if we have waiters on this message ? */
msg->ipc_complete = true;
wake_up(&msg->waitq);
}
EXPORT_SYMBOL(snd_sof_ipc_reply);
struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev)
{
struct snd_sof_ipc *ipc;
struct snd_sof_ipc_msg *msg;
const struct sof_ipc_ops *ops;
ipc = devm_kzalloc(sdev->dev, sizeof(*ipc), GFP_KERNEL);
if (!ipc)
return NULL;
mutex_init(&ipc->tx_mutex);
ipc->sdev = sdev;
msg = &ipc->msg;
/* indicate that we aren't sending a message ATM */
msg->ipc_complete = true;
init_waitqueue_head(&msg->waitq);
switch (sdev->pdata->ipc_type) {
#if defined(CONFIG_SND_SOC_SOF_IPC3)
case SOF_IPC:
ops = &ipc3_ops;
break;
#endif
#if defined(CONFIG_SND_SOC_SOF_INTEL_IPC4)
case SOF_INTEL_IPC4:
ops = &ipc4_ops;
break;
#endif
default:
dev_err(sdev->dev, "Not supported IPC version: %d\n",
sdev->pdata->ipc_type);
return NULL;
}
/* check for mandatory ops */
if (!ops->tx_msg || !ops->rx_msg || !ops->set_get_data || !ops->get_reply) {
dev_err(sdev->dev, "Missing IPC message handling ops\n");
return NULL;
}
if (!ops->fw_loader || !ops->fw_loader->validate ||
!ops->fw_loader->parse_ext_manifest) {
dev_err(sdev->dev, "Missing IPC firmware loading ops\n");
return NULL;
}
if (!ops->pcm) {
dev_err(sdev->dev, "Missing IPC PCM ops\n");
return NULL;
}
if (!ops->tplg || !ops->tplg->widget || !ops->tplg->control) {
dev_err(sdev->dev, "Missing IPC topology ops\n");
return NULL;
}
if (ops->fw_tracing && (!ops->fw_tracing->init || !ops->fw_tracing->suspend ||
!ops->fw_tracing->resume)) {
dev_err(sdev->dev, "Missing firmware tracing ops\n");
return NULL;
}
if (ops->init && ops->init(sdev))
return NULL;
ipc->ops = ops;
return ipc;
}
EXPORT_SYMBOL(snd_sof_ipc_init);
void snd_sof_ipc_free(struct snd_sof_dev *sdev)
{
struct snd_sof_ipc *ipc = sdev->ipc;
if (!ipc)
return;
/* disable sending of ipc's */
mutex_lock(&ipc->tx_mutex);
ipc->disable_ipc_tx = true;
mutex_unlock(&ipc->tx_mutex);
if (ipc->ops->exit)
ipc->ops->exit(sdev);
}
EXPORT_SYMBOL(snd_sof_ipc_free);
| linux-master | sound/soc/sof/ipc.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2019 Intel Corporation. All rights reserved.
//
// Author: Ranjani Sridharan <[email protected]>
//
#include <linux/bitfield.h>
#include <trace/events/sof.h>
#include "sof-audio.h"
#include "sof-of-dev.h"
#include "ops.h"
static bool is_virtual_widget(struct snd_sof_dev *sdev, struct snd_soc_dapm_widget *widget,
const char *func)
{
switch (widget->id) {
case snd_soc_dapm_out_drv:
case snd_soc_dapm_output:
case snd_soc_dapm_input:
dev_dbg(sdev->dev, "%s: %s is a virtual widget\n", func, widget->name);
return true;
default:
return false;
}
}
static void sof_reset_route_setup_status(struct snd_sof_dev *sdev, struct snd_sof_widget *widget)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_sof_route *sroute;
list_for_each_entry(sroute, &sdev->route_list, list)
if (sroute->src_widget == widget || sroute->sink_widget == widget) {
if (sroute->setup && tplg_ops && tplg_ops->route_free)
tplg_ops->route_free(sdev, sroute);
sroute->setup = false;
}
}
static int sof_widget_free_unlocked(struct snd_sof_dev *sdev,
struct snd_sof_widget *swidget)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_sof_widget *pipe_widget;
int err = 0;
int ret;
if (!swidget->private)
return 0;
trace_sof_widget_free(swidget);
/* only free when use_count is 0 */
if (--swidget->use_count)
return 0;
pipe_widget = swidget->spipe->pipe_widget;
/* reset route setup status for all routes that contain this widget */
sof_reset_route_setup_status(sdev, swidget);
/* free DAI config and continue to free widget even if it fails */
if (WIDGET_IS_DAI(swidget->id)) {
struct snd_sof_dai_config_data data;
unsigned int flags = SOF_DAI_CONFIG_FLAGS_HW_FREE;
data.dai_data = DMA_CHAN_INVALID;
if (tplg_ops && tplg_ops->dai_config) {
err = tplg_ops->dai_config(sdev, swidget, flags, &data);
if (err < 0)
dev_err(sdev->dev, "failed to free config for widget %s\n",
swidget->widget->name);
}
}
/* continue to disable core even if IPC fails */
if (tplg_ops && tplg_ops->widget_free) {
ret = tplg_ops->widget_free(sdev, swidget);
if (ret < 0 && !err)
err = ret;
}
/*
* disable widget core. continue to route setup status and complete flag
* even if this fails and return the appropriate error
*/
ret = snd_sof_dsp_core_put(sdev, swidget->core);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to disable target core: %d for widget %s\n",
swidget->core, swidget->widget->name);
if (!err)
err = ret;
}
/*
* free the scheduler widget (same as pipe_widget) associated with the current swidget.
* skip for static pipelines
*/
if (swidget->dynamic_pipeline_widget && swidget->id != snd_soc_dapm_scheduler) {
ret = sof_widget_free_unlocked(sdev, pipe_widget);
if (ret < 0 && !err)
err = ret;
}
/* clear pipeline complete */
if (swidget->id == snd_soc_dapm_scheduler)
swidget->spipe->complete = 0;
if (!err)
dev_dbg(sdev->dev, "widget %s freed\n", swidget->widget->name);
return err;
}
int sof_widget_free(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
int ret;
mutex_lock(&swidget->setup_mutex);
ret = sof_widget_free_unlocked(sdev, swidget);
mutex_unlock(&swidget->setup_mutex);
return ret;
}
EXPORT_SYMBOL(sof_widget_free);
static int sof_widget_setup_unlocked(struct snd_sof_dev *sdev,
struct snd_sof_widget *swidget)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
bool use_count_decremented = false;
int ret;
/* skip if there is no private data */
if (!swidget->private)
return 0;
trace_sof_widget_setup(swidget);
/* widget already set up */
if (++swidget->use_count > 1)
return 0;
/*
* The scheduler widget for a pipeline is not part of the connected DAPM
* widget list and it needs to be set up before the widgets in the pipeline
* are set up. The use_count for the scheduler widget is incremented for every
* widget in a given pipeline to ensure that it is freed only after the last
* widget in the pipeline is freed. Skip setting up scheduler widget for static pipelines.
*/
if (swidget->dynamic_pipeline_widget && swidget->id != snd_soc_dapm_scheduler) {
if (!swidget->spipe || !swidget->spipe->pipe_widget) {
dev_err(sdev->dev, "No pipeline set for %s\n", swidget->widget->name);
ret = -EINVAL;
goto use_count_dec;
}
ret = sof_widget_setup_unlocked(sdev, swidget->spipe->pipe_widget);
if (ret < 0)
goto use_count_dec;
}
/* enable widget core */
ret = snd_sof_dsp_core_get(sdev, swidget->core);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to enable target core for widget %s\n",
swidget->widget->name);
goto pipe_widget_free;
}
/* setup widget in the DSP */
if (tplg_ops && tplg_ops->widget_setup) {
ret = tplg_ops->widget_setup(sdev, swidget);
if (ret < 0)
goto core_put;
}
/* send config for DAI components */
if (WIDGET_IS_DAI(swidget->id)) {
unsigned int flags = SOF_DAI_CONFIG_FLAGS_HW_PARAMS;
/*
* The config flags saved during BE DAI hw_params will be used for IPC3. IPC4 does
* not use the flags argument.
*/
if (tplg_ops && tplg_ops->dai_config) {
ret = tplg_ops->dai_config(sdev, swidget, flags, NULL);
if (ret < 0)
goto widget_free;
}
}
/* restore kcontrols for widget */
if (tplg_ops && tplg_ops->control && tplg_ops->control->widget_kcontrol_setup) {
ret = tplg_ops->control->widget_kcontrol_setup(sdev, swidget);
if (ret < 0)
goto widget_free;
}
dev_dbg(sdev->dev, "widget %s setup complete\n", swidget->widget->name);
return 0;
widget_free:
/* widget use_count and core ref_count will both be decremented by sof_widget_free() */
sof_widget_free_unlocked(sdev, swidget);
use_count_decremented = true;
core_put:
if (!use_count_decremented)
snd_sof_dsp_core_put(sdev, swidget->core);
pipe_widget_free:
if (swidget->id != snd_soc_dapm_scheduler)
sof_widget_free_unlocked(sdev, swidget->spipe->pipe_widget);
use_count_dec:
if (!use_count_decremented)
swidget->use_count--;
return ret;
}
int sof_widget_setup(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
int ret;
mutex_lock(&swidget->setup_mutex);
ret = sof_widget_setup_unlocked(sdev, swidget);
mutex_unlock(&swidget->setup_mutex);
return ret;
}
EXPORT_SYMBOL(sof_widget_setup);
int sof_route_setup(struct snd_sof_dev *sdev, struct snd_soc_dapm_widget *wsource,
struct snd_soc_dapm_widget *wsink)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_sof_widget *src_widget = wsource->dobj.private;
struct snd_sof_widget *sink_widget = wsink->dobj.private;
struct snd_sof_route *sroute;
bool route_found = false;
/* ignore routes involving virtual widgets in topology */
if (is_virtual_widget(sdev, src_widget->widget, __func__) ||
is_virtual_widget(sdev, sink_widget->widget, __func__))
return 0;
/* find route matching source and sink widgets */
list_for_each_entry(sroute, &sdev->route_list, list)
if (sroute->src_widget == src_widget && sroute->sink_widget == sink_widget) {
route_found = true;
break;
}
if (!route_found) {
dev_err(sdev->dev, "error: cannot find SOF route for source %s -> %s sink\n",
wsource->name, wsink->name);
return -EINVAL;
}
/* nothing to do if route is already set up */
if (sroute->setup)
return 0;
if (tplg_ops && tplg_ops->route_setup) {
int ret = tplg_ops->route_setup(sdev, sroute);
if (ret < 0)
return ret;
}
sroute->setup = true;
return 0;
}
static int sof_setup_pipeline_connections(struct snd_sof_dev *sdev,
struct snd_soc_dapm_widget_list *list, int dir)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_soc_dapm_widget *widget;
struct snd_sof_route *sroute;
struct snd_soc_dapm_path *p;
int ret = 0;
int i;
/*
* Set up connections between widgets in the sink/source paths based on direction.
* Some non-SOF widgets exist in topology either for compatibility or for the
* purpose of connecting a pipeline from a host to a DAI in order to receive the DAPM
* events. But they are not handled by the firmware. So ignore them.
*/
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
for_each_dapm_widgets(list, i, widget) {
if (!widget->dobj.private)
continue;
snd_soc_dapm_widget_for_each_sink_path(widget, p) {
if (!widget_in_list(list, p->sink))
continue;
if (p->sink->dobj.private) {
ret = sof_route_setup(sdev, widget, p->sink);
if (ret < 0)
return ret;
}
}
}
} else {
for_each_dapm_widgets(list, i, widget) {
if (!widget->dobj.private)
continue;
snd_soc_dapm_widget_for_each_source_path(widget, p) {
if (!widget_in_list(list, p->source))
continue;
if (p->source->dobj.private) {
ret = sof_route_setup(sdev, p->source, widget);
if (ret < 0)
return ret;
}
}
}
}
/*
* The above loop handles connections between widgets that belong to the DAPM widget list.
* This is not sufficient to handle loopback cases between pipelines configured with
* different directions, e.g. a sidetone or an amplifier feedback connected to a speaker
* protection module.
*/
list_for_each_entry(sroute, &sdev->route_list, list) {
bool src_widget_in_dapm_list, sink_widget_in_dapm_list;
struct snd_sof_widget *swidget;
if (sroute->setup)
continue;
src_widget_in_dapm_list = widget_in_list(list, sroute->src_widget->widget);
sink_widget_in_dapm_list = widget_in_list(list, sroute->sink_widget->widget);
/*
* if both source and sink are in the DAPM list, the route must already have been
* set up above. And if neither are in the DAPM list, the route shouldn't be
* handled now.
*/
if (src_widget_in_dapm_list == sink_widget_in_dapm_list)
continue;
/*
* At this point either the source widget or the sink widget is in the DAPM list
* with a route that might need to be set up. Check the use_count of the widget
* that is not in the DAPM list to confirm if it is in use currently before setting
* up the route.
*/
if (src_widget_in_dapm_list)
swidget = sroute->sink_widget;
else
swidget = sroute->src_widget;
mutex_lock(&swidget->setup_mutex);
if (!swidget->use_count) {
mutex_unlock(&swidget->setup_mutex);
continue;
}
if (tplg_ops && tplg_ops->route_setup) {
/*
* this route will get freed when either the source widget or the sink
* widget is freed during hw_free
*/
ret = tplg_ops->route_setup(sdev, sroute);
if (!ret)
sroute->setup = true;
}
mutex_unlock(&swidget->setup_mutex);
if (ret < 0)
return ret;
}
return 0;
}
static void
sof_unprepare_widgets_in_path(struct snd_sof_dev *sdev, struct snd_soc_dapm_widget *widget,
struct snd_soc_dapm_widget_list *list)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_sof_widget *swidget = widget->dobj.private;
const struct sof_ipc_tplg_widget_ops *widget_ops;
struct snd_soc_dapm_path *p;
if (is_virtual_widget(sdev, widget, __func__))
return;
/* skip if the widget is in use or if it is already unprepared */
if (!swidget || !swidget->prepared || swidget->use_count > 0)
goto sink_unprepare;
widget_ops = tplg_ops ? tplg_ops->widget : NULL;
if (widget_ops && widget_ops[widget->id].ipc_unprepare)
/* unprepare the source widget */
widget_ops[widget->id].ipc_unprepare(swidget);
swidget->prepared = false;
sink_unprepare:
/* unprepare all widgets in the sink paths */
snd_soc_dapm_widget_for_each_sink_path(widget, p) {
if (!widget_in_list(list, p->sink))
continue;
if (!p->walking && p->sink->dobj.private) {
p->walking = true;
sof_unprepare_widgets_in_path(sdev, p->sink, list);
p->walking = false;
}
}
}
static int
sof_prepare_widgets_in_path(struct snd_sof_dev *sdev, struct snd_soc_dapm_widget *widget,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
struct snd_pcm_hw_params *pipeline_params, int dir,
struct snd_soc_dapm_widget_list *list)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_sof_widget *swidget = widget->dobj.private;
const struct sof_ipc_tplg_widget_ops *widget_ops;
struct snd_soc_dapm_path *p;
int ret;
if (is_virtual_widget(sdev, widget, __func__))
return 0;
widget_ops = tplg_ops ? tplg_ops->widget : NULL;
if (!widget_ops)
return 0;
if (!swidget || !widget_ops[widget->id].ipc_prepare || swidget->prepared)
goto sink_prepare;
/* prepare the source widget */
ret = widget_ops[widget->id].ipc_prepare(swidget, fe_params, platform_params,
pipeline_params, dir);
if (ret < 0) {
dev_err(sdev->dev, "failed to prepare widget %s\n", widget->name);
return ret;
}
swidget->prepared = true;
sink_prepare:
/* prepare all widgets in the sink paths */
snd_soc_dapm_widget_for_each_sink_path(widget, p) {
if (!widget_in_list(list, p->sink))
continue;
if (!p->walking && p->sink->dobj.private) {
p->walking = true;
ret = sof_prepare_widgets_in_path(sdev, p->sink, fe_params,
platform_params, pipeline_params, dir,
list);
p->walking = false;
if (ret < 0) {
/* unprepare the source widget */
if (widget_ops[widget->id].ipc_unprepare &&
swidget && swidget->prepared) {
widget_ops[widget->id].ipc_unprepare(swidget);
swidget->prepared = false;
}
return ret;
}
}
}
return 0;
}
/*
* free all widgets in the sink path starting from the source widget
* (DAI type for capture, AIF type for playback)
*/
static int sof_free_widgets_in_path(struct snd_sof_dev *sdev, struct snd_soc_dapm_widget *widget,
int dir, struct snd_sof_pcm *spcm)
{
struct snd_soc_dapm_widget_list *list = spcm->stream[dir].list;
struct snd_soc_dapm_path *p;
int err;
int ret = 0;
if (is_virtual_widget(sdev, widget, __func__))
return 0;
if (widget->dobj.private) {
err = sof_widget_free(sdev, widget->dobj.private);
if (err < 0)
ret = err;
}
/* free all widgets in the sink paths even in case of error to keep use counts balanced */
snd_soc_dapm_widget_for_each_sink_path(widget, p) {
if (!p->walking) {
if (!widget_in_list(list, p->sink))
continue;
p->walking = true;
err = sof_free_widgets_in_path(sdev, p->sink, dir, spcm);
if (err < 0)
ret = err;
p->walking = false;
}
}
return ret;
}
/*
* set up all widgets in the sink path starting from the source widget
* (DAI type for capture, AIF type for playback).
* The error path in this function ensures that all successfully set up widgets getting freed.
*/
static int sof_set_up_widgets_in_path(struct snd_sof_dev *sdev, struct snd_soc_dapm_widget *widget,
int dir, struct snd_sof_pcm *spcm)
{
struct snd_sof_pcm_stream_pipeline_list *pipeline_list = &spcm->stream[dir].pipeline_list;
struct snd_soc_dapm_widget_list *list = spcm->stream[dir].list;
struct snd_sof_widget *swidget = widget->dobj.private;
struct snd_sof_pipeline *spipe;
struct snd_soc_dapm_path *p;
int ret;
if (is_virtual_widget(sdev, widget, __func__))
return 0;
if (swidget) {
int i;
ret = sof_widget_setup(sdev, widget->dobj.private);
if (ret < 0)
return ret;
/* skip populating the pipe_widgets array if it is NULL */
if (!pipeline_list->pipelines)
goto sink_setup;
/*
* Add the widget's pipe_widget to the list of pipelines to be triggered if not
* already in the list. This will result in the pipelines getting added in the
* order source to sink.
*/
for (i = 0; i < pipeline_list->count; i++) {
spipe = pipeline_list->pipelines[i];
if (spipe == swidget->spipe)
break;
}
if (i == pipeline_list->count) {
pipeline_list->count++;
pipeline_list->pipelines[i] = swidget->spipe;
}
}
sink_setup:
snd_soc_dapm_widget_for_each_sink_path(widget, p) {
if (!p->walking) {
if (!widget_in_list(list, p->sink))
continue;
p->walking = true;
ret = sof_set_up_widgets_in_path(sdev, p->sink, dir, spcm);
p->walking = false;
if (ret < 0) {
if (swidget)
sof_widget_free(sdev, swidget);
return ret;
}
}
}
return 0;
}
static int
sof_walk_widgets_in_order(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params, int dir,
enum sof_widget_op op)
{
struct snd_soc_dapm_widget_list *list = spcm->stream[dir].list;
struct snd_soc_dapm_widget *widget;
char *str;
int ret = 0;
int i;
if (!list)
return 0;
for_each_dapm_widgets(list, i, widget) {
if (is_virtual_widget(sdev, widget, __func__))
continue;
/* starting widget for playback is AIF type */
if (dir == SNDRV_PCM_STREAM_PLAYBACK && widget->id != snd_soc_dapm_aif_in)
continue;
/* starting widget for capture is DAI type */
if (dir == SNDRV_PCM_STREAM_CAPTURE && widget->id != snd_soc_dapm_dai_out)
continue;
switch (op) {
case SOF_WIDGET_SETUP:
ret = sof_set_up_widgets_in_path(sdev, widget, dir, spcm);
str = "set up";
break;
case SOF_WIDGET_FREE:
ret = sof_free_widgets_in_path(sdev, widget, dir, spcm);
str = "free";
break;
case SOF_WIDGET_PREPARE:
{
struct snd_pcm_hw_params pipeline_params;
str = "prepare";
/*
* When walking the list of connected widgets, the pipeline_params for each
* widget is modified by the source widget in the path. Use a local
* copy of the runtime params as the pipeline_params so that the runtime
* params does not get overwritten.
*/
memcpy(&pipeline_params, fe_params, sizeof(*fe_params));
ret = sof_prepare_widgets_in_path(sdev, widget, fe_params, platform_params,
&pipeline_params, dir, list);
break;
}
case SOF_WIDGET_UNPREPARE:
sof_unprepare_widgets_in_path(sdev, widget, list);
break;
default:
dev_err(sdev->dev, "Invalid widget op %d\n", op);
return -EINVAL;
}
if (ret < 0) {
dev_err(sdev->dev, "Failed to %s connected widgets\n", str);
return ret;
}
}
return 0;
}
int sof_widget_list_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
int dir)
{
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
struct snd_soc_dapm_widget_list *list = spcm->stream[dir].list;
struct snd_soc_dapm_widget *widget;
int i, ret;
/* nothing to set up */
if (!list)
return 0;
/*
* Prepare widgets for set up. The prepare step is used to allocate memory, assign
* instance ID and pick the widget configuration based on the runtime PCM params.
*/
ret = sof_walk_widgets_in_order(sdev, spcm, fe_params, platform_params,
dir, SOF_WIDGET_PREPARE);
if (ret < 0)
return ret;
/* Set up is used to send the IPC to the DSP to create the widget */
ret = sof_walk_widgets_in_order(sdev, spcm, fe_params, platform_params,
dir, SOF_WIDGET_SETUP);
if (ret < 0) {
sof_walk_widgets_in_order(sdev, spcm, fe_params, platform_params,
dir, SOF_WIDGET_UNPREPARE);
return ret;
}
/*
* error in setting pipeline connections will result in route status being reset for
* routes that were successfully set up when the widgets are freed.
*/
ret = sof_setup_pipeline_connections(sdev, list, dir);
if (ret < 0)
goto widget_free;
/* complete pipelines */
for_each_dapm_widgets(list, i, widget) {
struct snd_sof_widget *swidget = widget->dobj.private;
struct snd_sof_widget *pipe_widget;
struct snd_sof_pipeline *spipe;
if (!swidget || sdev->dspless_mode_selected)
continue;
spipe = swidget->spipe;
if (!spipe) {
dev_err(sdev->dev, "no pipeline found for %s\n",
swidget->widget->name);
ret = -EINVAL;
goto widget_free;
}
pipe_widget = spipe->pipe_widget;
if (!pipe_widget) {
dev_err(sdev->dev, "error: no pipeline widget found for %s\n",
swidget->widget->name);
ret = -EINVAL;
goto widget_free;
}
if (spipe->complete)
continue;
if (tplg_ops && tplg_ops->pipeline_complete) {
spipe->complete = tplg_ops->pipeline_complete(sdev, pipe_widget);
if (spipe->complete < 0) {
ret = spipe->complete;
goto widget_free;
}
}
}
return 0;
widget_free:
sof_walk_widgets_in_order(sdev, spcm, fe_params, platform_params, dir,
SOF_WIDGET_FREE);
sof_walk_widgets_in_order(sdev, spcm, NULL, NULL, dir, SOF_WIDGET_UNPREPARE);
return ret;
}
int sof_widget_list_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm, int dir)
{
struct snd_sof_pcm_stream_pipeline_list *pipeline_list = &spcm->stream[dir].pipeline_list;
struct snd_soc_dapm_widget_list *list = spcm->stream[dir].list;
int ret;
/* nothing to free */
if (!list)
return 0;
/* send IPC to free widget in the DSP */
ret = sof_walk_widgets_in_order(sdev, spcm, NULL, NULL, dir, SOF_WIDGET_FREE);
/* unprepare the widget */
sof_walk_widgets_in_order(sdev, spcm, NULL, NULL, dir, SOF_WIDGET_UNPREPARE);
snd_soc_dapm_dai_free_widgets(&list);
spcm->stream[dir].list = NULL;
pipeline_list->count = 0;
return ret;
}
/*
* helper to determine if there are only D0i3 compatible
* streams active
*/
bool snd_sof_dsp_only_d0i3_compatible_stream_active(struct snd_sof_dev *sdev)
{
struct snd_pcm_substream *substream;
struct snd_sof_pcm *spcm;
bool d0i3_compatible_active = false;
int dir;
list_for_each_entry(spcm, &sdev->pcm_list, list) {
for_each_pcm_streams(dir) {
substream = spcm->stream[dir].substream;
if (!substream || !substream->runtime)
continue;
/*
* substream->runtime being not NULL indicates
* that the stream is open. No need to check the
* stream state.
*/
if (!spcm->stream[dir].d0i3_compatible)
return false;
d0i3_compatible_active = true;
}
}
return d0i3_compatible_active;
}
EXPORT_SYMBOL(snd_sof_dsp_only_d0i3_compatible_stream_active);
bool snd_sof_stream_suspend_ignored(struct snd_sof_dev *sdev)
{
struct snd_sof_pcm *spcm;
list_for_each_entry(spcm, &sdev->pcm_list, list) {
if (spcm->stream[SNDRV_PCM_STREAM_PLAYBACK].suspend_ignored ||
spcm->stream[SNDRV_PCM_STREAM_CAPTURE].suspend_ignored)
return true;
}
return false;
}
int sof_pcm_stream_free(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
struct snd_sof_pcm *spcm, int dir, bool free_widget_list)
{
const struct sof_ipc_pcm_ops *pcm_ops = sof_ipc_get_ops(sdev, pcm);
int ret;
if (spcm->prepared[substream->stream]) {
/* stop DMA first if needed */
if (pcm_ops && pcm_ops->platform_stop_during_hw_free)
snd_sof_pcm_platform_trigger(sdev, substream, SNDRV_PCM_TRIGGER_STOP);
/* Send PCM_FREE IPC to reset pipeline */
if (pcm_ops && pcm_ops->hw_free) {
ret = pcm_ops->hw_free(sdev->component, substream);
if (ret < 0)
return ret;
}
spcm->prepared[substream->stream] = false;
}
/* reset the DMA */
ret = snd_sof_pcm_platform_hw_free(sdev, substream);
if (ret < 0)
return ret;
/* free widget list */
if (free_widget_list) {
ret = sof_widget_list_free(sdev, spcm, dir);
if (ret < 0)
dev_err(sdev->dev, "failed to free widgets during suspend\n");
}
return ret;
}
/*
* Generic object lookup APIs.
*/
struct snd_sof_pcm *snd_sof_find_spcm_name(struct snd_soc_component *scomp,
const char *name)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_pcm *spcm;
list_for_each_entry(spcm, &sdev->pcm_list, list) {
/* match with PCM dai name */
if (strcmp(spcm->pcm.dai_name, name) == 0)
return spcm;
/* match with playback caps name if set */
if (*spcm->pcm.caps[0].name &&
!strcmp(spcm->pcm.caps[0].name, name))
return spcm;
/* match with capture caps name if set */
if (*spcm->pcm.caps[1].name &&
!strcmp(spcm->pcm.caps[1].name, name))
return spcm;
}
return NULL;
}
struct snd_sof_pcm *snd_sof_find_spcm_comp(struct snd_soc_component *scomp,
unsigned int comp_id,
int *direction)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_pcm *spcm;
int dir;
list_for_each_entry(spcm, &sdev->pcm_list, list) {
for_each_pcm_streams(dir) {
if (spcm->stream[dir].comp_id == comp_id) {
*direction = dir;
return spcm;
}
}
}
return NULL;
}
struct snd_sof_widget *snd_sof_find_swidget(struct snd_soc_component *scomp,
const char *name)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_widget *swidget;
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (strcmp(name, swidget->widget->name) == 0)
return swidget;
}
return NULL;
}
/* find widget by stream name and direction */
struct snd_sof_widget *
snd_sof_find_swidget_sname(struct snd_soc_component *scomp,
const char *pcm_name, int dir)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_widget *swidget;
enum snd_soc_dapm_type type;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
type = snd_soc_dapm_aif_in;
else
type = snd_soc_dapm_aif_out;
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (!strcmp(pcm_name, swidget->widget->sname) &&
swidget->id == type)
return swidget;
}
return NULL;
}
struct snd_sof_dai *snd_sof_find_dai(struct snd_soc_component *scomp,
const char *name)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct snd_sof_dai *dai;
list_for_each_entry(dai, &sdev->dai_list, list) {
if (dai->name && (strcmp(name, dai->name) == 0))
return dai;
}
return NULL;
}
static int sof_dai_get_clk(struct snd_soc_pcm_runtime *rtd, int clk_type)
{
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
struct snd_sof_dai *dai =
snd_sof_find_dai(component, (char *)rtd->dai_link->name);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
const struct sof_ipc_tplg_ops *tplg_ops = sof_ipc_get_ops(sdev, tplg);
/* use the tplg configured mclk if existed */
if (!dai)
return 0;
if (tplg_ops && tplg_ops->dai_get_clk)
return tplg_ops->dai_get_clk(sdev, dai, clk_type);
return 0;
}
/*
* Helper to get SSP MCLK from a pcm_runtime.
* Return 0 if not exist.
*/
int sof_dai_get_mclk(struct snd_soc_pcm_runtime *rtd)
{
return sof_dai_get_clk(rtd, SOF_DAI_CLK_INTEL_SSP_MCLK);
}
EXPORT_SYMBOL(sof_dai_get_mclk);
/*
* Helper to get SSP BCLK from a pcm_runtime.
* Return 0 if not exist.
*/
int sof_dai_get_bclk(struct snd_soc_pcm_runtime *rtd)
{
return sof_dai_get_clk(rtd, SOF_DAI_CLK_INTEL_SSP_BCLK);
}
EXPORT_SYMBOL(sof_dai_get_bclk);
static struct snd_sof_of_mach *sof_of_machine_select(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *sof_pdata = sdev->pdata;
const struct sof_dev_desc *desc = sof_pdata->desc;
struct snd_sof_of_mach *mach = desc->of_machines;
if (!mach)
return NULL;
for (; mach->compatible; mach++) {
if (of_machine_is_compatible(mach->compatible)) {
sof_pdata->tplg_filename = mach->sof_tplg_filename;
if (mach->fw_filename)
sof_pdata->fw_filename = mach->fw_filename;
return mach;
}
}
return NULL;
}
/*
* SOF Driver enumeration.
*/
int sof_machine_check(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *sof_pdata = sdev->pdata;
const struct sof_dev_desc *desc = sof_pdata->desc;
struct snd_soc_acpi_mach *mach;
if (!IS_ENABLED(CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE)) {
const struct snd_sof_of_mach *of_mach;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
goto nocodec;
/* find machine */
mach = snd_sof_machine_select(sdev);
if (mach) {
sof_pdata->machine = mach;
snd_sof_set_mach_params(mach, sdev);
return 0;
}
of_mach = sof_of_machine_select(sdev);
if (of_mach) {
sof_pdata->of_machine = of_mach;
return 0;
}
if (!IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC)) {
dev_err(sdev->dev, "error: no matching ASoC machine driver found - aborting probe\n");
return -ENODEV;
}
} else {
dev_warn(sdev->dev, "Force to use nocodec mode\n");
}
nocodec:
/* select nocodec mode */
dev_warn(sdev->dev, "Using nocodec machine driver\n");
mach = devm_kzalloc(sdev->dev, sizeof(*mach), GFP_KERNEL);
if (!mach)
return -ENOMEM;
mach->drv_name = "sof-nocodec";
if (!sof_pdata->tplg_filename)
sof_pdata->tplg_filename = desc->nocodec_tplg_filename;
sof_pdata->machine = mach;
snd_sof_set_mach_params(mach, sdev);
return 0;
}
EXPORT_SYMBOL(sof_machine_check);
int sof_machine_register(struct snd_sof_dev *sdev, void *pdata)
{
struct snd_sof_pdata *plat_data = pdata;
const char *drv_name;
const void *mach;
int size;
drv_name = plat_data->machine->drv_name;
mach = plat_data->machine;
size = sizeof(*plat_data->machine);
/* register machine driver, pass machine info as pdata */
plat_data->pdev_mach =
platform_device_register_data(sdev->dev, drv_name,
PLATFORM_DEVID_NONE, mach, size);
if (IS_ERR(plat_data->pdev_mach))
return PTR_ERR(plat_data->pdev_mach);
dev_dbg(sdev->dev, "created machine %s\n",
dev_name(&plat_data->pdev_mach->dev));
return 0;
}
EXPORT_SYMBOL(sof_machine_register);
void sof_machine_unregister(struct snd_sof_dev *sdev, void *pdata)
{
struct snd_sof_pdata *plat_data = pdata;
if (!IS_ERR_OR_NULL(plat_data->pdev_mach))
platform_device_unregister(plat_data->pdev_mach);
}
EXPORT_SYMBOL(sof_machine_unregister);
| linux-master | sound/soc/sof/sof-audio.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
#include <linux/firmware.h>
#include <sound/sof/ext_manifest4.h>
#include <sound/sof/ipc4/header.h>
#include <trace/events/sof.h>
#include "ipc4-priv.h"
#include "sof-audio.h"
#include "sof-priv.h"
#include "ops.h"
/* The module ID includes the id of the library it is part of at offset 12 */
#define SOF_IPC4_MOD_LIB_ID_SHIFT 12
static ssize_t sof_ipc4_fw_parse_ext_man(struct snd_sof_dev *sdev,
struct sof_ipc4_fw_library *fw_lib)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
const struct firmware *fw = fw_lib->sof_fw.fw;
struct sof_man4_fw_binary_header *fw_header;
struct sof_ext_manifest4_hdr *ext_man_hdr;
struct sof_man4_module_config *fm_config;
struct sof_ipc4_fw_module *fw_module;
struct sof_man4_module *fm_entry;
ssize_t remaining;
u32 fw_hdr_offset;
int i;
if (!ipc4_data) {
dev_err(sdev->dev, "%s: ipc4_data is not available\n", __func__);
return -EINVAL;
}
remaining = fw->size;
if (remaining <= sizeof(*ext_man_hdr)) {
dev_err(sdev->dev, "Firmware size is too small: %zu\n", remaining);
return -EINVAL;
}
ext_man_hdr = (struct sof_ext_manifest4_hdr *)fw->data;
/*
* At the start of the firmware image we must have an extended manifest.
* Verify that the magic number is correct.
*/
if (ext_man_hdr->id != SOF_EXT_MAN4_MAGIC_NUMBER) {
dev_err(sdev->dev,
"Unexpected extended manifest magic number: %#x\n",
ext_man_hdr->id);
return -EINVAL;
}
fw_hdr_offset = ipc4_data->manifest_fw_hdr_offset;
if (!fw_hdr_offset)
return -EINVAL;
if (remaining <= ext_man_hdr->len + fw_hdr_offset + sizeof(*fw_header)) {
dev_err(sdev->dev, "Invalid firmware size %zu, should be at least %zu\n",
remaining, ext_man_hdr->len + fw_hdr_offset + sizeof(*fw_header));
return -EINVAL;
}
fw_header = (struct sof_man4_fw_binary_header *)
(fw->data + ext_man_hdr->len + fw_hdr_offset);
remaining -= (ext_man_hdr->len + fw_hdr_offset);
if (remaining <= fw_header->len) {
dev_err(sdev->dev, "Invalid fw_header->len %u\n", fw_header->len);
return -EINVAL;
}
dev_info(sdev->dev, "Loaded firmware library: %s, version: %u.%u.%u.%u\n",
fw_header->name, fw_header->major_version, fw_header->minor_version,
fw_header->hotfix_version, fw_header->build_version);
dev_dbg(sdev->dev, "Header length: %u, module count: %u\n",
fw_header->len, fw_header->num_module_entries);
fw_lib->modules = devm_kmalloc_array(sdev->dev, fw_header->num_module_entries,
sizeof(*fw_module), GFP_KERNEL);
if (!fw_lib->modules)
return -ENOMEM;
fw_lib->name = fw_header->name;
fw_lib->num_modules = fw_header->num_module_entries;
fw_module = fw_lib->modules;
fm_entry = (struct sof_man4_module *)((u8 *)fw_header + fw_header->len);
remaining -= fw_header->len;
if (remaining < fw_header->num_module_entries * sizeof(*fm_entry)) {
dev_err(sdev->dev, "Invalid num_module_entries %u\n",
fw_header->num_module_entries);
return -EINVAL;
}
fm_config = (struct sof_man4_module_config *)
(fm_entry + fw_header->num_module_entries);
remaining -= (fw_header->num_module_entries * sizeof(*fm_entry));
for (i = 0; i < fw_header->num_module_entries; i++) {
memcpy(&fw_module->man4_module_entry, fm_entry, sizeof(*fm_entry));
if (fm_entry->cfg_count) {
if (remaining < (fm_entry->cfg_offset + fm_entry->cfg_count) *
sizeof(*fm_config)) {
dev_err(sdev->dev, "Invalid module cfg_offset %u\n",
fm_entry->cfg_offset);
return -EINVAL;
}
fw_module->fw_mod_cfg = &fm_config[fm_entry->cfg_offset];
dev_dbg(sdev->dev,
"module %s: UUID %pUL cfg_count: %u, bss_size: %#x\n",
fm_entry->name, &fm_entry->uuid, fm_entry->cfg_count,
fm_config[fm_entry->cfg_offset].is_bytes);
} else {
dev_dbg(sdev->dev, "module %s: UUID %pUL\n", fm_entry->name,
&fm_entry->uuid);
}
fw_module->man4_module_entry.id = i;
ida_init(&fw_module->m_ida);
fw_module->private = NULL;
fw_module++;
fm_entry++;
}
return ext_man_hdr->len;
}
static size_t sof_ipc4_fw_parse_basefw_ext_man(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_fw_library *fw_lib;
ssize_t payload_offset;
int ret;
fw_lib = devm_kzalloc(sdev->dev, sizeof(*fw_lib), GFP_KERNEL);
if (!fw_lib)
return -ENOMEM;
fw_lib->sof_fw.fw = sdev->basefw.fw;
payload_offset = sof_ipc4_fw_parse_ext_man(sdev, fw_lib);
if (payload_offset > 0) {
fw_lib->sof_fw.payload_offset = payload_offset;
/* basefw ID is 0 */
fw_lib->id = 0;
ret = xa_insert(&ipc4_data->fw_lib_xa, 0, fw_lib, GFP_KERNEL);
if (ret)
return ret;
}
return payload_offset;
}
static int sof_ipc4_load_library_by_uuid(struct snd_sof_dev *sdev,
unsigned long lib_id, const guid_t *uuid)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_fw_library *fw_lib;
const char *fw_filename;
ssize_t payload_offset;
int ret, i, err;
if (!sdev->pdata->fw_lib_prefix) {
dev_err(sdev->dev,
"Library loading is not supported due to not set library path\n");
return -EINVAL;
}
if (!ipc4_data->load_library) {
dev_err(sdev->dev, "Library loading is not supported on this platform\n");
return -EOPNOTSUPP;
}
fw_lib = devm_kzalloc(sdev->dev, sizeof(*fw_lib), GFP_KERNEL);
if (!fw_lib)
return -ENOMEM;
fw_filename = kasprintf(GFP_KERNEL, "%s/%pUL.bin",
sdev->pdata->fw_lib_prefix, uuid);
if (!fw_filename) {
ret = -ENOMEM;
goto free_fw_lib;
}
ret = request_firmware(&fw_lib->sof_fw.fw, fw_filename, sdev->dev);
if (ret < 0) {
dev_err(sdev->dev, "Library file '%s' is missing\n", fw_filename);
goto free_filename;
} else {
dev_dbg(sdev->dev, "Library file '%s' loaded\n", fw_filename);
}
payload_offset = sof_ipc4_fw_parse_ext_man(sdev, fw_lib);
if (payload_offset <= 0) {
if (!payload_offset)
ret = -EINVAL;
else
ret = payload_offset;
goto release;
}
fw_lib->sof_fw.payload_offset = payload_offset;
fw_lib->id = lib_id;
/* Fix up the module ID numbers within the library */
for (i = 0; i < fw_lib->num_modules; i++)
fw_lib->modules[i].man4_module_entry.id |= (lib_id << SOF_IPC4_MOD_LIB_ID_SHIFT);
/*
* Make sure that the DSP is booted and stays up while attempting the
* loading the library for the first time
*/
ret = pm_runtime_resume_and_get(sdev->dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(sdev->dev, "%s: pm_runtime resume failed: %d\n",
__func__, ret);
goto release;
}
ret = ipc4_data->load_library(sdev, fw_lib, false);
pm_runtime_mark_last_busy(sdev->dev);
err = pm_runtime_put_autosuspend(sdev->dev);
if (err < 0)
dev_err_ratelimited(sdev->dev, "%s: pm_runtime idle failed: %d\n",
__func__, err);
if (ret)
goto release;
ret = xa_insert(&ipc4_data->fw_lib_xa, lib_id, fw_lib, GFP_KERNEL);
if (unlikely(ret))
goto release;
kfree(fw_filename);
return 0;
release:
release_firmware(fw_lib->sof_fw.fw);
/* Allocated within sof_ipc4_fw_parse_ext_man() */
devm_kfree(sdev->dev, fw_lib->modules);
free_filename:
kfree(fw_filename);
free_fw_lib:
devm_kfree(sdev->dev, fw_lib);
return ret;
}
struct sof_ipc4_fw_module *sof_ipc4_find_module_by_uuid(struct snd_sof_dev *sdev,
const guid_t *uuid)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_fw_library *fw_lib;
unsigned long lib_id;
int i, ret;
if (guid_is_null(uuid))
return NULL;
xa_for_each(&ipc4_data->fw_lib_xa, lib_id, fw_lib) {
for (i = 0; i < fw_lib->num_modules; i++) {
if (guid_equal(uuid, &fw_lib->modules[i].man4_module_entry.uuid))
return &fw_lib->modules[i];
}
}
/*
* Do not attempt to load external library in case the maximum number of
* firmware libraries have been already loaded
*/
if ((lib_id + 1) == ipc4_data->max_libs_count) {
dev_err(sdev->dev,
"%s: Maximum allowed number of libraries reached (%u)\n",
__func__, ipc4_data->max_libs_count);
return NULL;
}
/* The module cannot be found, try to load it as a library */
ret = sof_ipc4_load_library_by_uuid(sdev, lib_id + 1, uuid);
if (ret)
return NULL;
/* Look for the module in the newly loaded library, it should be available now */
xa_for_each_start(&ipc4_data->fw_lib_xa, lib_id, fw_lib, lib_id) {
for (i = 0; i < fw_lib->num_modules; i++) {
if (guid_equal(uuid, &fw_lib->modules[i].man4_module_entry.uuid))
return &fw_lib->modules[i];
}
}
return NULL;
}
static int sof_ipc4_validate_firmware(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
u32 fw_hdr_offset = ipc4_data->manifest_fw_hdr_offset;
struct sof_man4_fw_binary_header *fw_header;
const struct firmware *fw = sdev->basefw.fw;
struct sof_ext_manifest4_hdr *ext_man_hdr;
ext_man_hdr = (struct sof_ext_manifest4_hdr *)fw->data;
fw_header = (struct sof_man4_fw_binary_header *)
(fw->data + ext_man_hdr->len + fw_hdr_offset);
/* TODO: Add firmware verification code here */
dev_dbg(sdev->dev, "Validated firmware version: %u.%u.%u.%u\n",
fw_header->major_version, fw_header->minor_version,
fw_header->hotfix_version, fw_header->build_version);
return 0;
}
int sof_ipc4_query_fw_configuration(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
const struct sof_ipc_ops *iops = sdev->ipc->ops;
struct sof_ipc4_fw_version *fw_ver;
struct sof_ipc4_tuple *tuple;
struct sof_ipc4_msg msg;
size_t offset = 0;
int ret;
/* Get the firmware configuration */
msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_FW_CONFIG);
msg.data_size = sdev->ipc->max_payload_size;
msg.data_ptr = kzalloc(msg.data_size, GFP_KERNEL);
if (!msg.data_ptr)
return -ENOMEM;
ret = iops->set_get_data(sdev, &msg, msg.data_size, false);
if (ret)
goto out;
while (offset < msg.data_size) {
tuple = (struct sof_ipc4_tuple *)((u8 *)msg.data_ptr + offset);
switch (tuple->type) {
case SOF_IPC4_FW_CFG_FW_VERSION:
fw_ver = (struct sof_ipc4_fw_version *)tuple->value;
dev_info(sdev->dev,
"Booted firmware version: %u.%u.%u.%u\n",
fw_ver->major, fw_ver->minor, fw_ver->hotfix,
fw_ver->build);
break;
case SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES:
trace_sof_ipc4_fw_config(sdev, "DL mailbox size", *tuple->value);
break;
case SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES:
trace_sof_ipc4_fw_config(sdev, "UL mailbox size", *tuple->value);
break;
case SOF_IPC4_FW_CFG_TRACE_LOG_BYTES:
trace_sof_ipc4_fw_config(sdev, "Trace log size", *tuple->value);
ipc4_data->mtrace_log_bytes = *tuple->value;
break;
case SOF_IPC4_FW_CFG_MAX_LIBS_COUNT:
trace_sof_ipc4_fw_config(sdev, "maximum number of libraries",
*tuple->value);
ipc4_data->max_libs_count = *tuple->value;
if (!ipc4_data->max_libs_count)
ipc4_data->max_libs_count = 1;
break;
case SOF_IPC4_FW_CFG_MAX_PPL_COUNT:
ipc4_data->max_num_pipelines = *tuple->value;
trace_sof_ipc4_fw_config(sdev, "Max PPL count %d",
ipc4_data->max_num_pipelines);
if (ipc4_data->max_num_pipelines <= 0) {
dev_err(sdev->dev, "Invalid max_num_pipelines %d",
ipc4_data->max_num_pipelines);
ret = -EINVAL;
goto out;
}
break;
default:
break;
}
offset += sizeof(*tuple) + tuple->size;
}
out:
kfree(msg.data_ptr);
return ret;
}
int sof_ipc4_reload_fw_libraries(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_fw_library *fw_lib;
unsigned long lib_id;
int ret = 0;
xa_for_each_start(&ipc4_data->fw_lib_xa, lib_id, fw_lib, 1) {
ret = ipc4_data->load_library(sdev, fw_lib, true);
if (ret) {
dev_err(sdev->dev, "%s: Failed to reload library: %s, %d\n",
__func__, fw_lib->name, ret);
break;
}
}
return ret;
}
/**
* sof_ipc4_update_cpc_from_manifest - Update the cpc in base config from manifest
* @sdev: SOF device
* @fw_module: pointer struct sof_ipc4_fw_module to parse
* @basecfg: Pointer to the base_config to update
*/
void sof_ipc4_update_cpc_from_manifest(struct snd_sof_dev *sdev,
struct sof_ipc4_fw_module *fw_module,
struct sof_ipc4_base_module_cfg *basecfg)
{
const struct sof_man4_module_config *fw_mod_cfg;
u32 cpc_pick = 0;
u32 max_cpc = 0;
const char *msg;
int i;
if (!fw_module->fw_mod_cfg) {
msg = "No mod_cfg available for CPC lookup in the firmware file's manifest";
goto no_cpc;
}
/*
* Find the best matching (highest) CPC value based on the module's
* IBS/OBS configuration inferred from the audio format selection.
*
* The CPC value in each module config entry has been measured and
* recorded as a IBS/OBS/CPC triplet and stored in the firmware file's
* manifest
*/
fw_mod_cfg = fw_module->fw_mod_cfg;
for (i = 0; i < fw_module->man4_module_entry.cfg_count; i++) {
if (basecfg->obs == fw_mod_cfg[i].obs &&
basecfg->ibs == fw_mod_cfg[i].ibs &&
cpc_pick < fw_mod_cfg[i].cpc)
cpc_pick = fw_mod_cfg[i].cpc;
if (max_cpc < fw_mod_cfg[i].cpc)
max_cpc = fw_mod_cfg[i].cpc;
}
basecfg->cpc = cpc_pick;
/* We have a matching configuration for CPC */
if (basecfg->cpc)
return;
/*
* No matching IBS/OBS found, the firmware manifest is missing
* information in the module's module configuration table.
*/
if (!max_cpc)
msg = "No CPC value available in the firmware file's manifest";
else if (!cpc_pick)
msg = "No CPC match in the firmware file's manifest";
no_cpc:
dev_warn(sdev->dev, "%s (UUID: %pUL): %s (ibs/obs: %u/%u)\n",
fw_module->man4_module_entry.name,
&fw_module->man4_module_entry.uuid, msg, basecfg->ibs,
basecfg->obs);
dev_warn_once(sdev->dev, "Please try to update the firmware.\n");
dev_warn_once(sdev->dev, "If the issue persists, file a bug at\n");
dev_warn_once(sdev->dev, "https://github.com/thesofproject/sof/issues/\n");
}
const struct sof_ipc_fw_loader_ops ipc4_loader_ops = {
.validate = sof_ipc4_validate_firmware,
.parse_ext_manifest = sof_ipc4_fw_parse_basefw_ext_man,
};
| linux-master | sound/soc/sof/ipc4-loader.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
//
#include <linux/bitfield.h>
#include <uapi/sound/sof/tokens.h>
#include <sound/pcm_params.h>
#include <sound/sof/ext_manifest4.h>
#include <sound/intel-nhlt.h>
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc4-priv.h"
#include "ipc4-topology.h"
#include "ops.h"
/*
* The ignore_cpc flag can be used to ignore the CPC value for all modules by
* using 0 instead.
* The CPC is sent to the firmware along with the SOF_IPC4_MOD_INIT_INSTANCE
* message and it is used for clock scaling.
* 0 as CPC value will instruct the firmware to use maximum frequency, thus
* deactivating the clock scaling.
*/
static bool ignore_cpc;
module_param_named(ipc4_ignore_cpc, ignore_cpc, bool, 0444);
MODULE_PARM_DESC(ipc4_ignore_cpc,
"Ignore CPC values. This option will disable clock scaling in firmware.");
#define SOF_IPC4_GAIN_PARAM_ID 0
#define SOF_IPC4_TPLG_ABI_SIZE 6
#define SOF_IPC4_CHAIN_DMA_BUF_SIZE_MS 2
static DEFINE_IDA(alh_group_ida);
static DEFINE_IDA(pipeline_ida);
static const struct sof_topology_token ipc4_sched_tokens[] = {
{SOF_TKN_SCHED_LP_MODE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pipeline, lp_mode)},
{SOF_TKN_SCHED_USE_CHAIN_DMA, SND_SOC_TPLG_TUPLE_TYPE_BOOL, get_token_u16,
offsetof(struct sof_ipc4_pipeline, use_chain_dma)},
{SOF_TKN_SCHED_CORE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pipeline, core_id)},
};
static const struct sof_topology_token pipeline_tokens[] = {
{SOF_TKN_SCHED_DYNAMIC_PIPELINE, SND_SOC_TPLG_TUPLE_TYPE_BOOL, get_token_u16,
offsetof(struct snd_sof_widget, dynamic_pipeline_widget)},
};
static const struct sof_topology_token ipc4_comp_tokens[] = {
{SOF_TKN_COMP_IS_PAGES, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_base_module_cfg, is_pages)},
};
static const struct sof_topology_token ipc4_in_audio_format_tokens[] = {
{SOF_TKN_CAVS_AUDIO_FORMAT_IN_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.sampling_frequency)},
{SOF_TKN_CAVS_AUDIO_FORMAT_IN_BIT_DEPTH, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.bit_depth)},
{SOF_TKN_CAVS_AUDIO_FORMAT_IN_CH_MAP, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.ch_map)},
{SOF_TKN_CAVS_AUDIO_FORMAT_IN_CH_CFG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.ch_cfg)},
{SOF_TKN_CAVS_AUDIO_FORMAT_IN_INTERLEAVING_STYLE, SND_SOC_TPLG_TUPLE_TYPE_WORD,
get_token_u32, offsetof(struct sof_ipc4_pin_format,
audio_fmt.interleaving_style)},
{SOF_TKN_CAVS_AUDIO_FORMAT_IN_FMT_CFG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.fmt_cfg)},
{SOF_TKN_CAVS_AUDIO_FORMAT_INPUT_PIN_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, pin_index)},
{SOF_TKN_CAVS_AUDIO_FORMAT_IBS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, buffer_size)},
};
static const struct sof_topology_token ipc4_out_audio_format_tokens[] = {
{SOF_TKN_CAVS_AUDIO_FORMAT_OUT_RATE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.sampling_frequency)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OUT_BIT_DEPTH, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.bit_depth)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CH_MAP, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.ch_map)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CH_CFG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.ch_cfg)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OUT_INTERLEAVING_STYLE, SND_SOC_TPLG_TUPLE_TYPE_WORD,
get_token_u32, offsetof(struct sof_ipc4_pin_format,
audio_fmt.interleaving_style)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OUT_FMT_CFG, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, audio_fmt.fmt_cfg)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OUTPUT_PIN_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, pin_index)},
{SOF_TKN_CAVS_AUDIO_FORMAT_OBS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_pin_format, buffer_size)},
};
static const struct sof_topology_token ipc4_copier_deep_buffer_tokens[] = {
{SOF_TKN_INTEL_COPIER_DEEP_BUFFER_DMA_MS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 0},
};
static const struct sof_topology_token ipc4_copier_tokens[] = {
{SOF_TKN_INTEL_COPIER_NODE_TYPE, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32, 0},
};
static const struct sof_topology_token ipc4_audio_fmt_num_tokens[] = {
{SOF_TKN_COMP_NUM_INPUT_AUDIO_FORMATS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_available_audio_format, num_input_formats)},
{SOF_TKN_COMP_NUM_OUTPUT_AUDIO_FORMATS, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_available_audio_format, num_output_formats)},
};
static const struct sof_topology_token dai_tokens[] = {
{SOF_TKN_DAI_TYPE, SND_SOC_TPLG_TUPLE_TYPE_STRING, get_token_dai_type,
offsetof(struct sof_ipc4_copier, dai_type)},
{SOF_TKN_DAI_INDEX, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_copier, dai_index)},
};
/* Component extended tokens */
static const struct sof_topology_token comp_ext_tokens[] = {
{SOF_TKN_COMP_UUID, SND_SOC_TPLG_TUPLE_TYPE_UUID, get_token_uuid,
offsetof(struct snd_sof_widget, uuid)},
{SOF_TKN_COMP_CORE_ID, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct snd_sof_widget, core)},
};
static const struct sof_topology_token gain_tokens[] = {
{SOF_TKN_GAIN_RAMP_TYPE, SND_SOC_TPLG_TUPLE_TYPE_WORD,
get_token_u32, offsetof(struct sof_ipc4_gain_data, curve_type)},
{SOF_TKN_GAIN_RAMP_DURATION,
SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_gain_data, curve_duration_l)},
{SOF_TKN_GAIN_VAL, SND_SOC_TPLG_TUPLE_TYPE_WORD,
get_token_u32, offsetof(struct sof_ipc4_gain_data, init_val)},
};
/* SRC */
static const struct sof_topology_token src_tokens[] = {
{SOF_TKN_SRC_RATE_OUT, SND_SOC_TPLG_TUPLE_TYPE_WORD, get_token_u32,
offsetof(struct sof_ipc4_src, sink_rate)},
};
static const struct sof_token_info ipc4_token_list[SOF_TOKEN_COUNT] = {
[SOF_DAI_TOKENS] = {"DAI tokens", dai_tokens, ARRAY_SIZE(dai_tokens)},
[SOF_PIPELINE_TOKENS] = {"Pipeline tokens", pipeline_tokens, ARRAY_SIZE(pipeline_tokens)},
[SOF_SCHED_TOKENS] = {"Scheduler tokens", ipc4_sched_tokens,
ARRAY_SIZE(ipc4_sched_tokens)},
[SOF_COMP_EXT_TOKENS] = {"Comp extended tokens", comp_ext_tokens,
ARRAY_SIZE(comp_ext_tokens)},
[SOF_COMP_TOKENS] = {"IPC4 Component tokens",
ipc4_comp_tokens, ARRAY_SIZE(ipc4_comp_tokens)},
[SOF_IN_AUDIO_FORMAT_TOKENS] = {"IPC4 Input Audio format tokens",
ipc4_in_audio_format_tokens, ARRAY_SIZE(ipc4_in_audio_format_tokens)},
[SOF_OUT_AUDIO_FORMAT_TOKENS] = {"IPC4 Output Audio format tokens",
ipc4_out_audio_format_tokens, ARRAY_SIZE(ipc4_out_audio_format_tokens)},
[SOF_COPIER_DEEP_BUFFER_TOKENS] = {"IPC4 Copier deep buffer tokens",
ipc4_copier_deep_buffer_tokens, ARRAY_SIZE(ipc4_copier_deep_buffer_tokens)},
[SOF_COPIER_TOKENS] = {"IPC4 Copier tokens", ipc4_copier_tokens,
ARRAY_SIZE(ipc4_copier_tokens)},
[SOF_AUDIO_FMT_NUM_TOKENS] = {"IPC4 Audio format number tokens",
ipc4_audio_fmt_num_tokens, ARRAY_SIZE(ipc4_audio_fmt_num_tokens)},
[SOF_GAIN_TOKENS] = {"Gain tokens", gain_tokens, ARRAY_SIZE(gain_tokens)},
[SOF_SRC_TOKENS] = {"SRC tokens", src_tokens, ARRAY_SIZE(src_tokens)},
};
static void sof_ipc4_dbg_audio_format(struct device *dev, struct sof_ipc4_pin_format *pin_fmt,
int num_formats)
{
int i;
for (i = 0; i < num_formats; i++) {
struct sof_ipc4_audio_format *fmt = &pin_fmt[i].audio_fmt;
dev_dbg(dev,
"Pin index #%d: %uHz, %ubit (ch_map %#x ch_cfg %u interleaving_style %u fmt_cfg %#x) buffer size %d\n",
pin_fmt[i].pin_index, fmt->sampling_frequency, fmt->bit_depth, fmt->ch_map,
fmt->ch_cfg, fmt->interleaving_style, fmt->fmt_cfg,
pin_fmt[i].buffer_size);
}
}
static const struct sof_ipc4_audio_format *
sof_ipc4_get_input_pin_audio_fmt(struct snd_sof_widget *swidget, int pin_index)
{
struct sof_ipc4_base_module_cfg_ext *base_cfg_ext;
struct sof_ipc4_process *process;
int i;
if (swidget->id != snd_soc_dapm_effect) {
struct sof_ipc4_base_module_cfg *base = swidget->private;
/* For non-process modules, base module config format is used for all input pins */
return &base->audio_fmt;
}
process = swidget->private;
base_cfg_ext = process->base_config_ext;
/*
* If there are multiple input formats available for a pin, the first available format
* is chosen.
*/
for (i = 0; i < base_cfg_ext->num_input_pin_fmts; i++) {
struct sof_ipc4_pin_format *pin_format = &base_cfg_ext->pin_formats[i];
if (pin_format->pin_index == pin_index)
return &pin_format->audio_fmt;
}
return NULL;
}
/**
* sof_ipc4_get_audio_fmt - get available audio formats from swidget->tuples
* @scomp: pointer to pointer to SOC component
* @swidget: pointer to struct snd_sof_widget containing tuples
* @available_fmt: pointer to struct sof_ipc4_available_audio_format being filling in
* @module_base_cfg: Pointer to the base_config in the module init IPC payload
*
* Return: 0 if successful
*/
static int sof_ipc4_get_audio_fmt(struct snd_soc_component *scomp,
struct snd_sof_widget *swidget,
struct sof_ipc4_available_audio_format *available_fmt,
struct sof_ipc4_base_module_cfg *module_base_cfg)
{
struct sof_ipc4_pin_format *in_format = NULL;
struct sof_ipc4_pin_format *out_format;
int ret;
ret = sof_update_ipc_object(scomp, available_fmt,
SOF_AUDIO_FMT_NUM_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*available_fmt), 1);
if (ret) {
dev_err(scomp->dev, "Failed to parse audio format token count\n");
return ret;
}
if (!available_fmt->num_input_formats && !available_fmt->num_output_formats) {
dev_err(scomp->dev, "No input/output pin formats set in topology\n");
return -EINVAL;
}
dev_dbg(scomp->dev,
"Number of input audio formats: %d. Number of output audio formats: %d\n",
available_fmt->num_input_formats, available_fmt->num_output_formats);
/* set is_pages in the module's base_config */
ret = sof_update_ipc_object(scomp, module_base_cfg, SOF_COMP_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*module_base_cfg), 1);
if (ret) {
dev_err(scomp->dev, "parse comp tokens for %s failed, error: %d\n",
swidget->widget->name, ret);
return ret;
}
dev_dbg(scomp->dev, "widget %s: is_pages: %d\n", swidget->widget->name,
module_base_cfg->is_pages);
if (available_fmt->num_input_formats) {
in_format = kcalloc(available_fmt->num_input_formats,
sizeof(*in_format), GFP_KERNEL);
if (!in_format)
return -ENOMEM;
available_fmt->input_pin_fmts = in_format;
ret = sof_update_ipc_object(scomp, in_format,
SOF_IN_AUDIO_FORMAT_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*in_format),
available_fmt->num_input_formats);
if (ret) {
dev_err(scomp->dev, "parse input audio fmt tokens failed %d\n", ret);
goto err_in;
}
dev_dbg(scomp->dev, "Input audio formats for %s\n", swidget->widget->name);
sof_ipc4_dbg_audio_format(scomp->dev, in_format,
available_fmt->num_input_formats);
}
if (available_fmt->num_output_formats) {
out_format = kcalloc(available_fmt->num_output_formats, sizeof(*out_format),
GFP_KERNEL);
if (!out_format) {
ret = -ENOMEM;
goto err_in;
}
ret = sof_update_ipc_object(scomp, out_format,
SOF_OUT_AUDIO_FORMAT_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*out_format),
available_fmt->num_output_formats);
if (ret) {
dev_err(scomp->dev, "parse output audio fmt tokens failed\n");
goto err_out;
}
available_fmt->output_pin_fmts = out_format;
dev_dbg(scomp->dev, "Output audio formats for %s\n", swidget->widget->name);
sof_ipc4_dbg_audio_format(scomp->dev, out_format,
available_fmt->num_output_formats);
}
return 0;
err_out:
kfree(out_format);
err_in:
kfree(in_format);
available_fmt->input_pin_fmts = NULL;
return ret;
}
/* release the memory allocated in sof_ipc4_get_audio_fmt */
static void sof_ipc4_free_audio_fmt(struct sof_ipc4_available_audio_format *available_fmt)
{
kfree(available_fmt->output_pin_fmts);
available_fmt->output_pin_fmts = NULL;
kfree(available_fmt->input_pin_fmts);
available_fmt->input_pin_fmts = NULL;
}
static void sof_ipc4_widget_free_comp_pipeline(struct snd_sof_widget *swidget)
{
kfree(swidget->private);
}
static int sof_ipc4_widget_set_module_info(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
swidget->module_info = sof_ipc4_find_module_by_uuid(sdev, &swidget->uuid);
if (swidget->module_info)
return 0;
dev_err(sdev->dev, "failed to find module info for widget %s with UUID %pUL\n",
swidget->widget->name, &swidget->uuid);
return -EINVAL;
}
static int sof_ipc4_widget_setup_msg(struct snd_sof_widget *swidget, struct sof_ipc4_msg *msg)
{
struct sof_ipc4_fw_module *fw_module;
uint32_t type;
int ret;
ret = sof_ipc4_widget_set_module_info(swidget);
if (ret)
return ret;
fw_module = swidget->module_info;
msg->primary = fw_module->man4_module_entry.id;
msg->primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_INIT_INSTANCE);
msg->primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg->primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg->extension = SOF_IPC4_MOD_EXT_CORE_ID(swidget->core);
type = (fw_module->man4_module_entry.type & SOF_IPC4_MODULE_DP) ? 1 : 0;
msg->extension |= SOF_IPC4_MOD_EXT_DOMAIN(type);
return 0;
}
static void sof_ipc4_widget_update_kcontrol_module_id(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_fw_module *fw_module = swidget->module_info;
struct snd_sof_control *scontrol;
/* update module ID for all kcontrols for this widget */
list_for_each_entry(scontrol, &sdev->kcontrol_list, list) {
if (scontrol->comp_id == swidget->comp_id) {
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct sof_ipc4_msg *msg = &cdata->msg;
msg->primary |= fw_module->man4_module_entry.id;
}
}
}
static int sof_ipc4_widget_setup_pcm(struct snd_sof_widget *swidget)
{
struct sof_ipc4_available_audio_format *available_fmt;
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc4_copier *ipc4_copier;
int node_type = 0;
int ret;
ipc4_copier = kzalloc(sizeof(*ipc4_copier), GFP_KERNEL);
if (!ipc4_copier)
return -ENOMEM;
swidget->private = ipc4_copier;
available_fmt = &ipc4_copier->available_fmt;
dev_dbg(scomp->dev, "Updating IPC structure for %s\n", swidget->widget->name);
ret = sof_ipc4_get_audio_fmt(scomp, swidget, available_fmt,
&ipc4_copier->data.base_config);
if (ret)
goto free_copier;
/*
* This callback is used by host copier and module-to-module copier,
* and only host copier needs to set gtw_cfg.
*/
if (!WIDGET_IS_AIF(swidget->id))
goto skip_gtw_cfg;
ret = sof_update_ipc_object(scomp, &node_type,
SOF_COPIER_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(node_type), 1);
if (ret) {
dev_err(scomp->dev, "parse host copier node type token failed %d\n",
ret);
goto free_available_fmt;
}
dev_dbg(scomp->dev, "host copier '%s' node_type %u\n", swidget->widget->name, node_type);
skip_gtw_cfg:
ipc4_copier->gtw_attr = kzalloc(sizeof(*ipc4_copier->gtw_attr), GFP_KERNEL);
if (!ipc4_copier->gtw_attr) {
ret = -ENOMEM;
goto free_available_fmt;
}
ipc4_copier->copier_config = (uint32_t *)ipc4_copier->gtw_attr;
ipc4_copier->data.gtw_cfg.config_length =
sizeof(struct sof_ipc4_gtw_attributes) >> 2;
switch (swidget->id) {
case snd_soc_dapm_aif_in:
case snd_soc_dapm_aif_out:
ipc4_copier->data.gtw_cfg.node_id = SOF_IPC4_NODE_TYPE(node_type);
break;
case snd_soc_dapm_buffer:
ipc4_copier->data.gtw_cfg.node_id = SOF_IPC4_INVALID_NODE_ID;
ipc4_copier->ipc_config_size = 0;
break;
default:
dev_err(scomp->dev, "invalid widget type %d\n", swidget->id);
ret = -EINVAL;
goto free_gtw_attr;
}
/* set up module info and message header */
ret = sof_ipc4_widget_setup_msg(swidget, &ipc4_copier->msg);
if (ret)
goto free_gtw_attr;
return 0;
free_gtw_attr:
kfree(ipc4_copier->gtw_attr);
free_available_fmt:
sof_ipc4_free_audio_fmt(available_fmt);
free_copier:
kfree(ipc4_copier);
swidget->private = NULL;
return ret;
}
static void sof_ipc4_widget_free_comp_pcm(struct snd_sof_widget *swidget)
{
struct sof_ipc4_copier *ipc4_copier = swidget->private;
struct sof_ipc4_available_audio_format *available_fmt;
if (!ipc4_copier)
return;
available_fmt = &ipc4_copier->available_fmt;
kfree(available_fmt->output_pin_fmts);
kfree(ipc4_copier->gtw_attr);
kfree(ipc4_copier);
swidget->private = NULL;
}
static int sof_ipc4_widget_setup_comp_dai(struct snd_sof_widget *swidget)
{
struct sof_ipc4_available_audio_format *available_fmt;
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dai *dai = swidget->private;
struct sof_ipc4_copier *ipc4_copier;
struct snd_sof_widget *pipe_widget;
struct sof_ipc4_pipeline *pipeline;
int node_type = 0;
int ret;
ipc4_copier = kzalloc(sizeof(*ipc4_copier), GFP_KERNEL);
if (!ipc4_copier)
return -ENOMEM;
available_fmt = &ipc4_copier->available_fmt;
dev_dbg(scomp->dev, "Updating IPC structure for %s\n", swidget->widget->name);
ret = sof_ipc4_get_audio_fmt(scomp, swidget, available_fmt,
&ipc4_copier->data.base_config);
if (ret)
goto free_copier;
ret = sof_update_ipc_object(scomp, &node_type,
SOF_COPIER_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(node_type), 1);
if (ret) {
dev_err(scomp->dev, "parse dai node type failed %d\n", ret);
goto free_available_fmt;
}
ret = sof_update_ipc_object(scomp, ipc4_copier,
SOF_DAI_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(u32), 1);
if (ret) {
dev_err(scomp->dev, "parse dai copier node token failed %d\n", ret);
goto free_available_fmt;
}
dev_dbg(scomp->dev, "dai %s node_type %u dai_type %u dai_index %d\n", swidget->widget->name,
node_type, ipc4_copier->dai_type, ipc4_copier->dai_index);
ipc4_copier->data.gtw_cfg.node_id = SOF_IPC4_NODE_TYPE(node_type);
pipe_widget = swidget->spipe->pipe_widget;
pipeline = pipe_widget->private;
if (pipeline->use_chain_dma && ipc4_copier->dai_type != SOF_DAI_INTEL_HDA) {
dev_err(scomp->dev,
"Bad DAI type '%d', Chained DMA is only supported by HDA DAIs (%d).\n",
ipc4_copier->dai_type, SOF_DAI_INTEL_HDA);
ret = -ENODEV;
goto free_available_fmt;
}
switch (ipc4_copier->dai_type) {
case SOF_DAI_INTEL_ALH:
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_alh_configuration_blob *blob;
struct snd_soc_dapm_path *p;
struct snd_sof_widget *w;
int src_num = 0;
snd_soc_dapm_widget_for_each_source_path(swidget->widget, p)
src_num++;
if (swidget->id == snd_soc_dapm_dai_in && src_num == 0) {
/*
* The blob will not be used if the ALH copier is playback direction
* and doesn't connect to any source.
* It is fine to call kfree(ipc4_copier->copier_config) since
* ipc4_copier->copier_config is null.
*/
ret = 0;
break;
}
blob = kzalloc(sizeof(*blob), GFP_KERNEL);
if (!blob) {
ret = -ENOMEM;
goto free_available_fmt;
}
list_for_each_entry(w, &sdev->widget_list, list) {
if (w->widget->sname &&
strcmp(w->widget->sname, swidget->widget->sname))
continue;
blob->alh_cfg.device_count++;
}
ipc4_copier->copier_config = (uint32_t *)blob;
ipc4_copier->data.gtw_cfg.config_length = sizeof(*blob) >> 2;
break;
}
case SOF_DAI_INTEL_SSP:
/* set SSP DAI index as the node_id */
ipc4_copier->data.gtw_cfg.node_id |=
SOF_IPC4_NODE_INDEX_INTEL_SSP(ipc4_copier->dai_index);
break;
case SOF_DAI_INTEL_DMIC:
/* set DMIC DAI index as the node_id */
ipc4_copier->data.gtw_cfg.node_id |=
SOF_IPC4_NODE_INDEX_INTEL_DMIC(ipc4_copier->dai_index);
break;
default:
ipc4_copier->gtw_attr = kzalloc(sizeof(*ipc4_copier->gtw_attr), GFP_KERNEL);
if (!ipc4_copier->gtw_attr) {
ret = -ENOMEM;
goto free_available_fmt;
}
ipc4_copier->copier_config = (uint32_t *)ipc4_copier->gtw_attr;
ipc4_copier->data.gtw_cfg.config_length =
sizeof(struct sof_ipc4_gtw_attributes) >> 2;
break;
}
dai->scomp = scomp;
dai->private = ipc4_copier;
/* set up module info and message header */
ret = sof_ipc4_widget_setup_msg(swidget, &ipc4_copier->msg);
if (ret)
goto free_copier_config;
return 0;
free_copier_config:
kfree(ipc4_copier->copier_config);
free_available_fmt:
sof_ipc4_free_audio_fmt(available_fmt);
free_copier:
kfree(ipc4_copier);
dai->private = NULL;
dai->scomp = NULL;
return ret;
}
static void sof_ipc4_widget_free_comp_dai(struct snd_sof_widget *swidget)
{
struct sof_ipc4_available_audio_format *available_fmt;
struct snd_sof_dai *dai = swidget->private;
struct sof_ipc4_copier *ipc4_copier;
if (!dai)
return;
if (!dai->private) {
kfree(dai);
swidget->private = NULL;
return;
}
ipc4_copier = dai->private;
available_fmt = &ipc4_copier->available_fmt;
kfree(available_fmt->output_pin_fmts);
if (ipc4_copier->dai_type != SOF_DAI_INTEL_SSP &&
ipc4_copier->dai_type != SOF_DAI_INTEL_DMIC)
kfree(ipc4_copier->copier_config);
kfree(dai->private);
kfree(dai);
swidget->private = NULL;
}
static int sof_ipc4_widget_setup_comp_pipeline(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc4_pipeline *pipeline;
int ret;
pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL);
if (!pipeline)
return -ENOMEM;
ret = sof_update_ipc_object(scomp, pipeline, SOF_SCHED_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*pipeline), 1);
if (ret) {
dev_err(scomp->dev, "parsing scheduler tokens failed\n");
goto err;
}
swidget->core = pipeline->core_id;
if (pipeline->use_chain_dma) {
dev_dbg(scomp->dev, "Set up chain DMA for %s\n", swidget->widget->name);
swidget->private = pipeline;
return 0;
}
/* parse one set of pipeline tokens */
ret = sof_update_ipc_object(scomp, swidget, SOF_PIPELINE_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*swidget), 1);
if (ret) {
dev_err(scomp->dev, "parsing pipeline tokens failed\n");
goto err;
}
/* TODO: Get priority from topology */
pipeline->priority = 0;
dev_dbg(scomp->dev, "pipeline '%s': id %d, pri %d, core_id %u, lp mode %d\n",
swidget->widget->name, swidget->pipeline_id,
pipeline->priority, pipeline->core_id, pipeline->lp_mode);
swidget->private = pipeline;
pipeline->msg.primary = SOF_IPC4_GLB_PIPE_PRIORITY(pipeline->priority);
pipeline->msg.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CREATE_PIPELINE);
pipeline->msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
pipeline->msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
pipeline->msg.extension = pipeline->lp_mode;
pipeline->msg.extension |= SOF_IPC4_GLB_PIPE_EXT_CORE_ID(pipeline->core_id);
pipeline->state = SOF_IPC4_PIPE_UNINITIALIZED;
return 0;
err:
kfree(pipeline);
return ret;
}
static int sof_ipc4_widget_setup_comp_pga(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc4_gain *gain;
int ret;
gain = kzalloc(sizeof(*gain), GFP_KERNEL);
if (!gain)
return -ENOMEM;
swidget->private = gain;
gain->data.channels = SOF_IPC4_GAIN_ALL_CHANNELS_MASK;
gain->data.init_val = SOF_IPC4_VOL_ZERO_DB;
ret = sof_ipc4_get_audio_fmt(scomp, swidget, &gain->available_fmt, &gain->base_config);
if (ret)
goto err;
ret = sof_update_ipc_object(scomp, &gain->data, SOF_GAIN_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(gain->data), 1);
if (ret) {
dev_err(scomp->dev, "Parsing gain tokens failed\n");
goto err;
}
dev_dbg(scomp->dev,
"pga widget %s: ramp type: %d, ramp duration %d, initial gain value: %#x\n",
swidget->widget->name, gain->data.curve_type, gain->data.curve_duration_l,
gain->data.init_val);
ret = sof_ipc4_widget_setup_msg(swidget, &gain->msg);
if (ret)
goto err;
sof_ipc4_widget_update_kcontrol_module_id(swidget);
return 0;
err:
sof_ipc4_free_audio_fmt(&gain->available_fmt);
kfree(gain);
swidget->private = NULL;
return ret;
}
static void sof_ipc4_widget_free_comp_pga(struct snd_sof_widget *swidget)
{
struct sof_ipc4_gain *gain = swidget->private;
if (!gain)
return;
sof_ipc4_free_audio_fmt(&gain->available_fmt);
kfree(swidget->private);
swidget->private = NULL;
}
static int sof_ipc4_widget_setup_comp_mixer(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc4_mixer *mixer;
int ret;
dev_dbg(scomp->dev, "Updating IPC structure for %s\n", swidget->widget->name);
mixer = kzalloc(sizeof(*mixer), GFP_KERNEL);
if (!mixer)
return -ENOMEM;
swidget->private = mixer;
ret = sof_ipc4_get_audio_fmt(scomp, swidget, &mixer->available_fmt,
&mixer->base_config);
if (ret)
goto err;
ret = sof_ipc4_widget_setup_msg(swidget, &mixer->msg);
if (ret)
goto err;
return 0;
err:
sof_ipc4_free_audio_fmt(&mixer->available_fmt);
kfree(mixer);
swidget->private = NULL;
return ret;
}
static int sof_ipc4_widget_setup_comp_src(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc4_src *src;
int ret;
dev_dbg(scomp->dev, "Updating IPC structure for %s\n", swidget->widget->name);
src = kzalloc(sizeof(*src), GFP_KERNEL);
if (!src)
return -ENOMEM;
swidget->private = src;
ret = sof_ipc4_get_audio_fmt(scomp, swidget, &src->available_fmt, &src->base_config);
if (ret)
goto err;
ret = sof_update_ipc_object(scomp, src, SOF_SRC_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(*src), 1);
if (ret) {
dev_err(scomp->dev, "Parsing SRC tokens failed\n");
goto err;
}
dev_dbg(scomp->dev, "SRC sink rate %d\n", src->sink_rate);
ret = sof_ipc4_widget_setup_msg(swidget, &src->msg);
if (ret)
goto err;
return 0;
err:
sof_ipc4_free_audio_fmt(&src->available_fmt);
kfree(src);
swidget->private = NULL;
return ret;
}
static void sof_ipc4_widget_free_comp_src(struct snd_sof_widget *swidget)
{
struct sof_ipc4_src *src = swidget->private;
if (!src)
return;
sof_ipc4_free_audio_fmt(&src->available_fmt);
kfree(swidget->private);
swidget->private = NULL;
}
static void sof_ipc4_widget_free_comp_mixer(struct snd_sof_widget *swidget)
{
struct sof_ipc4_mixer *mixer = swidget->private;
if (!mixer)
return;
sof_ipc4_free_audio_fmt(&mixer->available_fmt);
kfree(swidget->private);
swidget->private = NULL;
}
/*
* Add the process modules support. The process modules are defined as snd_soc_dapm_effect modules.
*/
static int sof_ipc4_widget_setup_comp_process(struct snd_sof_widget *swidget)
{
struct snd_soc_component *scomp = swidget->scomp;
struct sof_ipc4_fw_module *fw_module;
struct sof_ipc4_process *process;
void *cfg;
int ret;
process = kzalloc(sizeof(*process), GFP_KERNEL);
if (!process)
return -ENOMEM;
swidget->private = process;
ret = sof_ipc4_get_audio_fmt(scomp, swidget, &process->available_fmt,
&process->base_config);
if (ret)
goto err;
ret = sof_ipc4_widget_setup_msg(swidget, &process->msg);
if (ret)
goto err;
/* parse process init module payload config type from module info */
fw_module = swidget->module_info;
process->init_config = FIELD_GET(SOF_IPC4_MODULE_INIT_CONFIG_MASK,
fw_module->man4_module_entry.type);
process->ipc_config_size = sizeof(struct sof_ipc4_base_module_cfg);
/* allocate memory for base config extension if needed */
if (process->init_config == SOF_IPC4_MODULE_INIT_CONFIG_TYPE_BASE_CFG_WITH_EXT) {
struct sof_ipc4_base_module_cfg_ext *base_cfg_ext;
u32 ext_size = struct_size(base_cfg_ext, pin_formats,
swidget->num_input_pins + swidget->num_output_pins);
base_cfg_ext = kzalloc(ext_size, GFP_KERNEL);
if (!base_cfg_ext) {
ret = -ENOMEM;
goto free_available_fmt;
}
base_cfg_ext->num_input_pin_fmts = swidget->num_input_pins;
base_cfg_ext->num_output_pin_fmts = swidget->num_output_pins;
process->base_config_ext = base_cfg_ext;
process->base_config_ext_size = ext_size;
process->ipc_config_size += ext_size;
}
cfg = kzalloc(process->ipc_config_size, GFP_KERNEL);
if (!cfg) {
ret = -ENOMEM;
goto free_base_cfg_ext;
}
process->ipc_config_data = cfg;
sof_ipc4_widget_update_kcontrol_module_id(swidget);
return 0;
free_base_cfg_ext:
kfree(process->base_config_ext);
process->base_config_ext = NULL;
free_available_fmt:
sof_ipc4_free_audio_fmt(&process->available_fmt);
err:
kfree(process);
swidget->private = NULL;
return ret;
}
static void sof_ipc4_widget_free_comp_process(struct snd_sof_widget *swidget)
{
struct sof_ipc4_process *process = swidget->private;
if (!process)
return;
kfree(process->ipc_config_data);
kfree(process->base_config_ext);
sof_ipc4_free_audio_fmt(&process->available_fmt);
kfree(swidget->private);
swidget->private = NULL;
}
static void
sof_ipc4_update_resource_usage(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget,
struct sof_ipc4_base_module_cfg *base_config)
{
struct sof_ipc4_fw_module *fw_module = swidget->module_info;
struct snd_sof_widget *pipe_widget;
struct sof_ipc4_pipeline *pipeline;
int task_mem, queue_mem;
int ibs, bss, total;
ibs = base_config->ibs;
bss = base_config->is_pages;
task_mem = SOF_IPC4_PIPELINE_OBJECT_SIZE;
task_mem += SOF_IPC4_MODULE_INSTANCE_LIST_ITEM_SIZE + bss;
if (fw_module->man4_module_entry.type & SOF_IPC4_MODULE_LL) {
task_mem += SOF_IPC4_FW_ROUNDUP(SOF_IPC4_LL_TASK_OBJECT_SIZE);
task_mem += SOF_IPC4_FW_MAX_QUEUE_COUNT * SOF_IPC4_MODULE_INSTANCE_LIST_ITEM_SIZE;
task_mem += SOF_IPC4_LL_TASK_LIST_ITEM_SIZE;
} else {
task_mem += SOF_IPC4_FW_ROUNDUP(SOF_IPC4_DP_TASK_OBJECT_SIZE);
task_mem += SOF_IPC4_DP_TASK_LIST_SIZE;
}
ibs = SOF_IPC4_FW_ROUNDUP(ibs);
queue_mem = SOF_IPC4_FW_MAX_QUEUE_COUNT * (SOF_IPC4_DATA_QUEUE_OBJECT_SIZE + ibs);
total = SOF_IPC4_FW_PAGE(task_mem + queue_mem);
pipe_widget = swidget->spipe->pipe_widget;
pipeline = pipe_widget->private;
pipeline->mem_usage += total;
/* Update base_config->cpc from the module manifest */
sof_ipc4_update_cpc_from_manifest(sdev, fw_module, base_config);
if (ignore_cpc) {
dev_dbg(sdev->dev, "%s: ibs / obs: %u / %u, forcing cpc to 0 from %u\n",
swidget->widget->name, base_config->ibs, base_config->obs,
base_config->cpc);
base_config->cpc = 0;
} else {
dev_dbg(sdev->dev, "%s: ibs / obs / cpc: %u / %u / %u\n",
swidget->widget->name, base_config->ibs, base_config->obs,
base_config->cpc);
}
}
static int sof_ipc4_widget_assign_instance_id(struct snd_sof_dev *sdev,
struct snd_sof_widget *swidget)
{
struct sof_ipc4_fw_module *fw_module = swidget->module_info;
int max_instances = fw_module->man4_module_entry.instance_max_count;
swidget->instance_id = ida_alloc_max(&fw_module->m_ida, max_instances, GFP_KERNEL);
if (swidget->instance_id < 0) {
dev_err(sdev->dev, "failed to assign instance id for widget %s",
swidget->widget->name);
return swidget->instance_id;
}
return 0;
}
/* update hw_params based on the audio stream format */
static int sof_ipc4_update_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_hw_params *params,
struct sof_ipc4_audio_format *fmt)
{
snd_pcm_format_t snd_fmt;
struct snd_interval *i;
struct snd_mask *m;
int valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(fmt->fmt_cfg);
unsigned int channels, rate;
switch (valid_bits) {
case 16:
snd_fmt = SNDRV_PCM_FORMAT_S16_LE;
break;
case 24:
snd_fmt = SNDRV_PCM_FORMAT_S24_LE;
break;
case 32:
snd_fmt = SNDRV_PCM_FORMAT_S32_LE;
break;
default:
dev_err(sdev->dev, "invalid PCM valid_bits %d\n", valid_bits);
return -EINVAL;
}
m = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
snd_mask_none(m);
snd_mask_set_format(m, snd_fmt);
rate = fmt->sampling_frequency;
i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
i->min = rate;
i->max = rate;
channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(fmt->fmt_cfg);
i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
i->min = channels;
i->max = channels;
return 0;
}
static bool sof_ipc4_is_single_format(struct snd_sof_dev *sdev,
struct sof_ipc4_pin_format *pin_fmts, u32 pin_fmts_size)
{
struct sof_ipc4_audio_format *fmt;
u32 rate, channels, valid_bits;
int i;
fmt = &pin_fmts[0].audio_fmt;
rate = fmt->sampling_frequency;
channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(fmt->fmt_cfg);
valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(fmt->fmt_cfg);
/* check if all output formats in topology are the same */
for (i = 1; i < pin_fmts_size; i++) {
u32 _rate, _channels, _valid_bits;
fmt = &pin_fmts[i].audio_fmt;
_rate = fmt->sampling_frequency;
_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(fmt->fmt_cfg);
_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(fmt->fmt_cfg);
if (_rate != rate || _channels != channels || _valid_bits != valid_bits)
return false;
}
return true;
}
static int sof_ipc4_init_output_audio_fmt(struct snd_sof_dev *sdev,
struct sof_ipc4_base_module_cfg *base_config,
struct sof_ipc4_available_audio_format *available_fmt,
u32 out_ref_rate, u32 out_ref_channels,
u32 out_ref_valid_bits)
{
struct sof_ipc4_audio_format *out_fmt;
bool single_format;
int i;
if (!available_fmt->num_output_formats)
return -EINVAL;
single_format = sof_ipc4_is_single_format(sdev, available_fmt->output_pin_fmts,
available_fmt->num_output_formats);
/* pick the first format if there's only one available or if all formats are the same */
if (single_format) {
base_config->obs = available_fmt->output_pin_fmts[0].buffer_size;
return 0;
}
/*
* if there are multiple output formats, then choose the output format that matches
* the reference params
*/
for (i = 0; i < available_fmt->num_output_formats; i++) {
u32 _out_rate, _out_channels, _out_valid_bits;
out_fmt = &available_fmt->output_pin_fmts[i].audio_fmt;
_out_rate = out_fmt->sampling_frequency;
_out_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(out_fmt->fmt_cfg);
_out_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(out_fmt->fmt_cfg);
if (_out_rate == out_ref_rate && _out_channels == out_ref_channels &&
_out_valid_bits == out_ref_valid_bits) {
base_config->obs = available_fmt->output_pin_fmts[i].buffer_size;
return i;
}
}
return -EINVAL;
}
static int sof_ipc4_get_valid_bits(struct snd_sof_dev *sdev, struct snd_pcm_hw_params *params)
{
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
return 16;
case SNDRV_PCM_FORMAT_S24_LE:
return 24;
case SNDRV_PCM_FORMAT_S32_LE:
return 32;
default:
dev_err(sdev->dev, "invalid pcm frame format %d\n", params_format(params));
return -EINVAL;
}
}
static int sof_ipc4_init_input_audio_fmt(struct snd_sof_dev *sdev,
struct snd_sof_widget *swidget,
struct sof_ipc4_base_module_cfg *base_config,
struct snd_pcm_hw_params *params,
struct sof_ipc4_available_audio_format *available_fmt)
{
struct sof_ipc4_pin_format *pin_fmts = available_fmt->input_pin_fmts;
u32 pin_fmts_size = available_fmt->num_input_formats;
u32 valid_bits;
u32 channels;
u32 rate;
bool single_format;
int sample_valid_bits;
int i = 0;
if (!available_fmt->num_input_formats) {
dev_err(sdev->dev, "no input formats for %s\n", swidget->widget->name);
return -EINVAL;
}
single_format = sof_ipc4_is_single_format(sdev, available_fmt->input_pin_fmts,
available_fmt->num_input_formats);
if (single_format)
goto in_fmt;
sample_valid_bits = sof_ipc4_get_valid_bits(sdev, params);
if (sample_valid_bits < 0)
return sample_valid_bits;
/*
* Search supported input audio formats with pin index 0 to match rate, channels and
* sample_valid_bits from reference params
*/
for (i = 0; i < pin_fmts_size; i++) {
struct sof_ipc4_audio_format *fmt = &pin_fmts[i].audio_fmt;
if (pin_fmts[i].pin_index)
continue;
rate = fmt->sampling_frequency;
channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(fmt->fmt_cfg);
valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(fmt->fmt_cfg);
if (params_rate(params) == rate && params_channels(params) == channels &&
sample_valid_bits == valid_bits) {
dev_dbg(sdev->dev, "matched audio format index for %uHz, %ubit, %u channels: %d\n",
rate, valid_bits, channels, i);
break;
}
}
if (i == pin_fmts_size) {
dev_err(sdev->dev, "%s: Unsupported audio format: %uHz, %ubit, %u channels\n",
__func__, params_rate(params), sample_valid_bits, params_channels(params));
return -EINVAL;
}
in_fmt:
/* copy input format */
if (available_fmt->num_input_formats && i < available_fmt->num_input_formats) {
memcpy(&base_config->audio_fmt, &available_fmt->input_pin_fmts[i].audio_fmt,
sizeof(struct sof_ipc4_audio_format));
/* set base_cfg ibs/obs */
base_config->ibs = available_fmt->input_pin_fmts[i].buffer_size;
dev_dbg(sdev->dev, "Init input audio formats for %s\n", swidget->widget->name);
sof_ipc4_dbg_audio_format(sdev->dev, &available_fmt->input_pin_fmts[i], 1);
}
return i;
}
static void sof_ipc4_unprepare_copier_module(struct snd_sof_widget *swidget)
{
struct sof_ipc4_copier *ipc4_copier = NULL;
struct snd_sof_widget *pipe_widget;
struct sof_ipc4_pipeline *pipeline;
/* reset pipeline memory usage */
pipe_widget = swidget->spipe->pipe_widget;
pipeline = pipe_widget->private;
pipeline->mem_usage = 0;
if (WIDGET_IS_AIF(swidget->id) || swidget->id == snd_soc_dapm_buffer) {
if (pipeline->use_chain_dma) {
pipeline->msg.primary = 0;
pipeline->msg.extension = 0;
}
ipc4_copier = swidget->private;
} else if (WIDGET_IS_DAI(swidget->id)) {
struct snd_sof_dai *dai = swidget->private;
ipc4_copier = dai->private;
if (pipeline->use_chain_dma) {
pipeline->msg.primary = 0;
pipeline->msg.extension = 0;
}
if (ipc4_copier->dai_type == SOF_DAI_INTEL_ALH) {
struct sof_ipc4_copier_data *copier_data = &ipc4_copier->data;
struct sof_ipc4_alh_configuration_blob *blob;
unsigned int group_id;
blob = (struct sof_ipc4_alh_configuration_blob *)ipc4_copier->copier_config;
if (blob->alh_cfg.device_count > 1) {
group_id = SOF_IPC4_NODE_INDEX(ipc4_copier->data.gtw_cfg.node_id) -
ALH_MULTI_GTW_BASE;
ida_free(&alh_group_ida, group_id);
}
/* clear the node ID */
copier_data->gtw_cfg.node_id &= ~SOF_IPC4_NODE_INDEX_MASK;
}
}
if (ipc4_copier) {
kfree(ipc4_copier->ipc_config_data);
ipc4_copier->ipc_config_data = NULL;
ipc4_copier->ipc_config_size = 0;
}
}
#if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SND_INTEL_NHLT)
static int snd_sof_get_hw_config_params(struct snd_sof_dev *sdev, struct snd_sof_dai *dai,
int *sample_rate, int *channel_count, int *bit_depth)
{
struct snd_soc_tplg_hw_config *hw_config;
struct snd_sof_dai_link *slink;
bool dai_link_found = false;
bool hw_cfg_found = false;
int i;
/* get current hw_config from link */
list_for_each_entry(slink, &sdev->dai_link_list, list) {
if (!strcmp(slink->link->name, dai->name)) {
dai_link_found = true;
break;
}
}
if (!dai_link_found) {
dev_err(sdev->dev, "%s: no DAI link found for DAI %s\n", __func__, dai->name);
return -EINVAL;
}
for (i = 0; i < slink->num_hw_configs; i++) {
hw_config = &slink->hw_configs[i];
if (dai->current_config == le32_to_cpu(hw_config->id)) {
hw_cfg_found = true;
break;
}
}
if (!hw_cfg_found) {
dev_err(sdev->dev, "%s: no matching hw_config found for DAI %s\n", __func__,
dai->name);
return -EINVAL;
}
*bit_depth = le32_to_cpu(hw_config->tdm_slot_width);
*channel_count = le32_to_cpu(hw_config->tdm_slots);
*sample_rate = le32_to_cpu(hw_config->fsync_rate);
dev_dbg(sdev->dev, "sample rate: %d sample width: %d channels: %d\n",
*sample_rate, *bit_depth, *channel_count);
return 0;
}
static int snd_sof_get_nhlt_endpoint_data(struct snd_sof_dev *sdev, struct snd_sof_dai *dai,
struct snd_pcm_hw_params *params, u32 dai_index,
u32 linktype, u8 dir, u32 **dst, u32 *len)
{
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct nhlt_specific_cfg *cfg;
int sample_rate, channel_count;
int bit_depth, ret;
u32 nhlt_type;
/* convert to NHLT type */
switch (linktype) {
case SOF_DAI_INTEL_DMIC:
nhlt_type = NHLT_LINK_DMIC;
bit_depth = params_width(params);
channel_count = params_channels(params);
sample_rate = params_rate(params);
break;
case SOF_DAI_INTEL_SSP:
nhlt_type = NHLT_LINK_SSP;
ret = snd_sof_get_hw_config_params(sdev, dai, &sample_rate, &channel_count,
&bit_depth);
if (ret < 0)
return ret;
break;
default:
return 0;
}
dev_dbg(sdev->dev, "dai index %d nhlt type %d direction %d\n",
dai_index, nhlt_type, dir);
/* find NHLT blob with matching params */
cfg = intel_nhlt_get_endpoint_blob(sdev->dev, ipc4_data->nhlt, dai_index, nhlt_type,
bit_depth, bit_depth, channel_count, sample_rate,
dir, 0);
if (!cfg) {
dev_err(sdev->dev,
"no matching blob for sample rate: %d sample width: %d channels: %d\n",
sample_rate, bit_depth, channel_count);
return -EINVAL;
}
/* config length should be in dwords */
*len = cfg->size >> 2;
*dst = (u32 *)cfg->caps;
return 0;
}
#else
static int snd_sof_get_nhlt_endpoint_data(struct snd_sof_dev *sdev, struct snd_sof_dai *dai,
struct snd_pcm_hw_params *params, u32 dai_index,
u32 linktype, u8 dir, u32 **dst, u32 *len)
{
return 0;
}
#endif
static bool sof_ipc4_copier_is_single_format(struct snd_sof_dev *sdev,
struct sof_ipc4_pin_format *pin_fmts,
u32 pin_fmts_size)
{
struct sof_ipc4_audio_format *fmt;
u32 valid_bits;
int i;
fmt = &pin_fmts[0].audio_fmt;
valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(fmt->fmt_cfg);
/* check if all output formats in topology are the same */
for (i = 1; i < pin_fmts_size; i++) {
u32 _valid_bits;
fmt = &pin_fmts[i].audio_fmt;
_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(fmt->fmt_cfg);
if (_valid_bits != valid_bits)
return false;
}
return true;
}
static int
sof_ipc4_prepare_copier_module(struct snd_sof_widget *swidget,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
struct snd_pcm_hw_params *pipeline_params, int dir)
{
struct sof_ipc4_available_audio_format *available_fmt;
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_copier_data *copier_data;
struct snd_pcm_hw_params *ref_params;
struct sof_ipc4_copier *ipc4_copier;
struct snd_sof_dai *dai;
u32 gtw_cfg_config_length;
u32 dma_config_tlv_size = 0;
void **ipc_config_data;
int *ipc_config_size;
u32 **data;
int ipc_size, ret, out_ref_valid_bits;
u32 out_ref_rate, out_ref_channels;
u32 deep_buffer_dma_ms = 0;
int output_fmt_index;
bool single_output_format;
dev_dbg(sdev->dev, "copier %s, type %d", swidget->widget->name, swidget->id);
switch (swidget->id) {
case snd_soc_dapm_aif_in:
case snd_soc_dapm_aif_out:
{
struct sof_ipc4_gtw_attributes *gtw_attr;
struct snd_sof_widget *pipe_widget;
struct sof_ipc4_pipeline *pipeline;
/* parse the deep buffer dma size */
ret = sof_update_ipc_object(scomp, &deep_buffer_dma_ms,
SOF_COPIER_DEEP_BUFFER_TOKENS, swidget->tuples,
swidget->num_tuples, sizeof(u32), 1);
if (ret) {
dev_err(scomp->dev, "Failed to parse deep buffer dma size for %s\n",
swidget->widget->name);
return ret;
}
ipc4_copier = (struct sof_ipc4_copier *)swidget->private;
gtw_attr = ipc4_copier->gtw_attr;
copier_data = &ipc4_copier->data;
available_fmt = &ipc4_copier->available_fmt;
pipe_widget = swidget->spipe->pipe_widget;
pipeline = pipe_widget->private;
if (pipeline->use_chain_dma) {
u32 host_dma_id;
u32 fifo_size;
host_dma_id = platform_params->stream_tag - 1;
pipeline->msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(host_dma_id);
/* Set SCS bit for S16_LE format only */
if (params_format(fe_params) == SNDRV_PCM_FORMAT_S16_LE)
pipeline->msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK;
/*
* Despite its name the bitfield 'fifo_size' is used to define DMA buffer
* size. The expression calculates 2ms buffer size.
*/
fifo_size = DIV_ROUND_UP((SOF_IPC4_CHAIN_DMA_BUF_SIZE_MS *
params_rate(fe_params) *
params_channels(fe_params) *
params_physical_width(fe_params)), 8000);
pipeline->msg.extension |= SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(fifo_size);
/*
* Chain DMA does not support stream timestamping, set node_id to invalid
* to skip the code in sof_ipc4_get_stream_start_offset().
*/
copier_data->gtw_cfg.node_id = SOF_IPC4_INVALID_NODE_ID;
return 0;
}
/*
* Use the input_pin_fmts to match pcm params for playback and the output_pin_fmts
* for capture.
*/
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
ref_params = fe_params;
else
ref_params = pipeline_params;
copier_data->gtw_cfg.node_id &= ~SOF_IPC4_NODE_INDEX_MASK;
copier_data->gtw_cfg.node_id |=
SOF_IPC4_NODE_INDEX(platform_params->stream_tag - 1);
/* set gateway attributes */
gtw_attr->lp_buffer_alloc = pipeline->lp_mode;
break;
}
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
{
struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
if (pipeline->use_chain_dma)
return 0;
dai = swidget->private;
ipc4_copier = (struct sof_ipc4_copier *)dai->private;
copier_data = &ipc4_copier->data;
available_fmt = &ipc4_copier->available_fmt;
/*
* When there is format conversion within a pipeline, the number of supported
* output formats is typically limited to just 1 for the DAI copiers. But when there
* is no format conversion, the DAI copiers input format must match that of the
* FE hw_params for capture and the pipeline params for playback.
*/
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
ref_params = pipeline_params;
else
ref_params = fe_params;
ret = snd_sof_get_nhlt_endpoint_data(sdev, dai, fe_params, ipc4_copier->dai_index,
ipc4_copier->dai_type, dir,
&ipc4_copier->copier_config,
&copier_data->gtw_cfg.config_length);
if (ret < 0)
return ret;
break;
}
case snd_soc_dapm_buffer:
{
ipc4_copier = (struct sof_ipc4_copier *)swidget->private;
copier_data = &ipc4_copier->data;
available_fmt = &ipc4_copier->available_fmt;
ref_params = pipeline_params;
break;
}
default:
dev_err(sdev->dev, "unsupported type %d for copier %s",
swidget->id, swidget->widget->name);
return -EINVAL;
}
/* set input and output audio formats */
ret = sof_ipc4_init_input_audio_fmt(sdev, swidget, &copier_data->base_config, ref_params,
available_fmt);
if (ret < 0)
return ret;
/* set the reference params for output format selection */
single_output_format = sof_ipc4_copier_is_single_format(sdev,
available_fmt->output_pin_fmts,
available_fmt->num_output_formats);
switch (swidget->id) {
case snd_soc_dapm_aif_in:
case snd_soc_dapm_dai_out:
case snd_soc_dapm_buffer:
{
struct sof_ipc4_audio_format *in_fmt;
in_fmt = &available_fmt->input_pin_fmts[ret].audio_fmt;
out_ref_rate = in_fmt->sampling_frequency;
out_ref_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(in_fmt->fmt_cfg);
if (!single_output_format)
out_ref_valid_bits =
SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(in_fmt->fmt_cfg);
break;
}
case snd_soc_dapm_aif_out:
case snd_soc_dapm_dai_in:
out_ref_rate = params_rate(fe_params);
out_ref_channels = params_channels(fe_params);
if (!single_output_format) {
out_ref_valid_bits = sof_ipc4_get_valid_bits(sdev, fe_params);
if (out_ref_valid_bits < 0)
return out_ref_valid_bits;
}
break;
default:
/*
* Unsupported type should be caught by the former switch default
* case, this should never happen in reality.
*/
return -EINVAL;
}
/*
* if the output format is the same across all available output formats, choose
* that as the reference.
*/
if (single_output_format) {
struct sof_ipc4_audio_format *out_fmt;
out_fmt = &available_fmt->output_pin_fmts[0].audio_fmt;
out_ref_valid_bits =
SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(out_fmt->fmt_cfg);
}
dev_dbg(sdev->dev, "copier %s: reference output rate %d, channels %d valid_bits %d\n",
swidget->widget->name, out_ref_rate, out_ref_channels, out_ref_valid_bits);
output_fmt_index = sof_ipc4_init_output_audio_fmt(sdev, &copier_data->base_config,
available_fmt, out_ref_rate,
out_ref_channels, out_ref_valid_bits);
if (output_fmt_index < 0) {
dev_err(sdev->dev, "Failed to initialize output format for %s",
swidget->widget->name);
return output_fmt_index;
}
/*
* Set the output format. Current topology defines pin 0 input and output formats in pairs.
* This assumes that the pin 0 formats are defined before all other pins.
* So pick the output audio format with the same index as the chosen
* input format. This logic will need to be updated when the format definitions
* in topology change.
*/
memcpy(&copier_data->out_format,
&available_fmt->output_pin_fmts[output_fmt_index].audio_fmt,
sizeof(struct sof_ipc4_audio_format));
dev_dbg(sdev->dev, "Output audio format for %s\n", swidget->widget->name);
sof_ipc4_dbg_audio_format(sdev->dev, &available_fmt->output_pin_fmts[output_fmt_index], 1);
switch (swidget->id) {
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
{
/*
* Only SOF_DAI_INTEL_ALH needs copier_data to set blob.
* That's why only ALH dai's blob is set after sof_ipc4_init_input_audio_fmt
*/
if (ipc4_copier->dai_type == SOF_DAI_INTEL_ALH) {
struct sof_ipc4_alh_configuration_blob *blob;
struct sof_ipc4_copier_data *alh_data;
struct sof_ipc4_copier *alh_copier;
struct snd_sof_widget *w;
u32 ch_count = 0;
u32 ch_mask = 0;
u32 ch_map;
u32 step;
u32 mask;
int i;
blob = (struct sof_ipc4_alh_configuration_blob *)ipc4_copier->copier_config;
blob->gw_attr.lp_buffer_alloc = 0;
/* Get channel_mask from ch_map */
ch_map = copier_data->base_config.audio_fmt.ch_map;
for (i = 0; ch_map; i++) {
if ((ch_map & 0xf) != 0xf) {
ch_mask |= BIT(i);
ch_count++;
}
ch_map >>= 4;
}
step = ch_count / blob->alh_cfg.device_count;
mask = GENMASK(step - 1, 0);
/*
* Set each gtw_cfg.node_id to blob->alh_cfg.mapping[]
* for all widgets with the same stream name
*/
i = 0;
list_for_each_entry(w, &sdev->widget_list, list) {
if (w->widget->sname &&
strcmp(w->widget->sname, swidget->widget->sname))
continue;
dai = w->private;
alh_copier = (struct sof_ipc4_copier *)dai->private;
alh_data = &alh_copier->data;
blob->alh_cfg.mapping[i].device = alh_data->gtw_cfg.node_id;
/*
* Set the same channel mask for playback as the audio data is
* duplicated for all speakers. For capture, split the channels
* among the aggregated DAIs. For example, with 4 channels on 2
* aggregated DAIs, the channel_mask should be 0x3 and 0xc for the
* two DAI's.
* The channel masks used depend on the cpu_dais used in the
* dailink at the machine driver level, which actually comes from
* the tables in soc_acpi files depending on the _ADR and devID
* registers for each codec.
*/
if (w->id == snd_soc_dapm_dai_in)
blob->alh_cfg.mapping[i].channel_mask = ch_mask;
else
blob->alh_cfg.mapping[i].channel_mask = mask << (step * i);
i++;
}
if (blob->alh_cfg.device_count > 1) {
int group_id;
group_id = ida_alloc_max(&alh_group_ida, ALH_MULTI_GTW_COUNT - 1,
GFP_KERNEL);
if (group_id < 0)
return group_id;
/* add multi-gateway base */
group_id += ALH_MULTI_GTW_BASE;
copier_data->gtw_cfg.node_id &= ~SOF_IPC4_NODE_INDEX_MASK;
copier_data->gtw_cfg.node_id |= SOF_IPC4_NODE_INDEX(group_id);
}
}
}
}
/* modify the input params for the next widget */
ret = sof_ipc4_update_hw_params(sdev, pipeline_params, &copier_data->out_format);
if (ret)
return ret;
/*
* Set the gateway dma_buffer_size to 2ms buffer size to meet the FW expectation. In the
* deep buffer case, set the dma_buffer_size depending on the deep_buffer_dma_ms set
* in topology.
*/
switch (swidget->id) {
case snd_soc_dapm_dai_in:
copier_data->gtw_cfg.dma_buffer_size =
SOF_IPC4_MIN_DMA_BUFFER_SIZE * copier_data->base_config.ibs;
break;
case snd_soc_dapm_aif_in:
copier_data->gtw_cfg.dma_buffer_size =
max((u32)SOF_IPC4_MIN_DMA_BUFFER_SIZE, deep_buffer_dma_ms) *
copier_data->base_config.ibs;
break;
case snd_soc_dapm_dai_out:
case snd_soc_dapm_aif_out:
copier_data->gtw_cfg.dma_buffer_size =
SOF_IPC4_MIN_DMA_BUFFER_SIZE * copier_data->base_config.obs;
break;
default:
break;
}
data = &ipc4_copier->copier_config;
ipc_config_size = &ipc4_copier->ipc_config_size;
ipc_config_data = &ipc4_copier->ipc_config_data;
/* config_length is DWORD based */
gtw_cfg_config_length = copier_data->gtw_cfg.config_length * 4;
ipc_size = sizeof(*copier_data) + gtw_cfg_config_length;
if (ipc4_copier->dma_config_tlv.type == SOF_IPC4_GTW_DMA_CONFIG_ID &&
ipc4_copier->dma_config_tlv.length) {
dma_config_tlv_size = sizeof(ipc4_copier->dma_config_tlv) +
ipc4_copier->dma_config_tlv.dma_config.dma_priv_config_size;
/* paranoia check on TLV size/length */
if (dma_config_tlv_size != ipc4_copier->dma_config_tlv.length +
sizeof(uint32_t) * 2) {
dev_err(sdev->dev, "Invalid configuration, TLV size %d length %d\n",
dma_config_tlv_size, ipc4_copier->dma_config_tlv.length);
return -EINVAL;
}
ipc_size += dma_config_tlv_size;
/* we also need to increase the size at the gtw level */
copier_data->gtw_cfg.config_length += dma_config_tlv_size / 4;
}
dev_dbg(sdev->dev, "copier %s, IPC size is %d", swidget->widget->name, ipc_size);
*ipc_config_data = kzalloc(ipc_size, GFP_KERNEL);
if (!*ipc_config_data)
return -ENOMEM;
*ipc_config_size = ipc_size;
/* update pipeline memory usage */
sof_ipc4_update_resource_usage(sdev, swidget, &copier_data->base_config);
/* copy IPC data */
memcpy(*ipc_config_data, (void *)copier_data, sizeof(*copier_data));
if (gtw_cfg_config_length)
memcpy(*ipc_config_data + sizeof(*copier_data),
*data, gtw_cfg_config_length);
/* add DMA Config TLV, if configured */
if (dma_config_tlv_size)
memcpy(*ipc_config_data + sizeof(*copier_data) +
gtw_cfg_config_length,
&ipc4_copier->dma_config_tlv, dma_config_tlv_size);
/*
* Restore gateway config length now that IPC payload is prepared. This avoids
* counting the DMA CONFIG TLV multiple times
*/
copier_data->gtw_cfg.config_length = gtw_cfg_config_length / 4;
return 0;
}
static int sof_ipc4_prepare_gain_module(struct snd_sof_widget *swidget,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
struct snd_pcm_hw_params *pipeline_params, int dir)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_gain *gain = swidget->private;
struct sof_ipc4_available_audio_format *available_fmt = &gain->available_fmt;
struct sof_ipc4_audio_format *in_fmt;
u32 out_ref_rate, out_ref_channels, out_ref_valid_bits;
int ret;
ret = sof_ipc4_init_input_audio_fmt(sdev, swidget, &gain->base_config,
pipeline_params, available_fmt);
if (ret < 0)
return ret;
in_fmt = &available_fmt->input_pin_fmts[ret].audio_fmt;
out_ref_rate = in_fmt->sampling_frequency;
out_ref_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(in_fmt->fmt_cfg);
out_ref_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(in_fmt->fmt_cfg);
ret = sof_ipc4_init_output_audio_fmt(sdev, &gain->base_config, available_fmt,
out_ref_rate, out_ref_channels, out_ref_valid_bits);
if (ret < 0) {
dev_err(sdev->dev, "Failed to initialize output format for %s",
swidget->widget->name);
return ret;
}
/* update pipeline memory usage */
sof_ipc4_update_resource_usage(sdev, swidget, &gain->base_config);
return 0;
}
static int sof_ipc4_prepare_mixer_module(struct snd_sof_widget *swidget,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
struct snd_pcm_hw_params *pipeline_params, int dir)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_mixer *mixer = swidget->private;
struct sof_ipc4_available_audio_format *available_fmt = &mixer->available_fmt;
struct sof_ipc4_audio_format *in_fmt;
u32 out_ref_rate, out_ref_channels, out_ref_valid_bits;
int ret;
ret = sof_ipc4_init_input_audio_fmt(sdev, swidget, &mixer->base_config,
pipeline_params, available_fmt);
if (ret < 0)
return ret;
in_fmt = &available_fmt->input_pin_fmts[ret].audio_fmt;
out_ref_rate = in_fmt->sampling_frequency;
out_ref_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(in_fmt->fmt_cfg);
out_ref_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(in_fmt->fmt_cfg);
ret = sof_ipc4_init_output_audio_fmt(sdev, &mixer->base_config, available_fmt,
out_ref_rate, out_ref_channels, out_ref_valid_bits);
if (ret < 0) {
dev_err(sdev->dev, "Failed to initialize output format for %s",
swidget->widget->name);
return ret;
}
/* update pipeline memory usage */
sof_ipc4_update_resource_usage(sdev, swidget, &mixer->base_config);
return 0;
}
static int sof_ipc4_prepare_src_module(struct snd_sof_widget *swidget,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
struct snd_pcm_hw_params *pipeline_params, int dir)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_src *src = swidget->private;
struct sof_ipc4_available_audio_format *available_fmt = &src->available_fmt;
struct sof_ipc4_audio_format *out_audio_fmt;
struct sof_ipc4_audio_format *in_audio_fmt;
u32 out_ref_rate, out_ref_channels, out_ref_valid_bits;
int output_format_index, input_format_index;
input_format_index = sof_ipc4_init_input_audio_fmt(sdev, swidget, &src->base_config,
pipeline_params, available_fmt);
if (input_format_index < 0)
return input_format_index;
/*
* For playback, the SRC sink rate will be configured based on the requested output
* format, which is restricted to only deal with DAI's with a single format for now.
*/
if (dir == SNDRV_PCM_STREAM_PLAYBACK && available_fmt->num_output_formats > 1) {
dev_err(sdev->dev, "Invalid number of output formats: %d for SRC %s\n",
available_fmt->num_output_formats, swidget->widget->name);
return -EINVAL;
}
/*
* SRC does not perform format conversion, so the output channels and valid bit depth must
* be the same as that of the input.
*/
in_audio_fmt = &available_fmt->input_pin_fmts[input_format_index].audio_fmt;
out_ref_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(in_audio_fmt->fmt_cfg);
out_ref_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(in_audio_fmt->fmt_cfg);
/*
* For capture, the SRC module should convert the rate to match the rate requested by the
* PCM hw_params. Set the reference params based on the fe_params unconditionally as it
* will be ignored for playback anyway.
*/
out_ref_rate = params_rate(fe_params);
output_format_index = sof_ipc4_init_output_audio_fmt(sdev, &src->base_config,
available_fmt, out_ref_rate,
out_ref_channels, out_ref_valid_bits);
if (output_format_index < 0) {
dev_err(sdev->dev, "Failed to initialize output format for %s",
swidget->widget->name);
return output_format_index;
}
/* update pipeline memory usage */
sof_ipc4_update_resource_usage(sdev, swidget, &src->base_config);
out_audio_fmt = &available_fmt->output_pin_fmts[output_format_index].audio_fmt;
src->sink_rate = out_audio_fmt->sampling_frequency;
/* update pipeline_params for sink widgets */
return sof_ipc4_update_hw_params(sdev, pipeline_params, out_audio_fmt);
}
static int
sof_ipc4_process_set_pin_formats(struct snd_sof_widget *swidget, int pin_type)
{
struct sof_ipc4_process *process = swidget->private;
struct sof_ipc4_base_module_cfg_ext *base_cfg_ext = process->base_config_ext;
struct sof_ipc4_available_audio_format *available_fmt = &process->available_fmt;
struct sof_ipc4_pin_format *pin_format, *format_list_to_search;
struct snd_soc_component *scomp = swidget->scomp;
int num_pins, format_list_count;
int pin_format_offset = 0;
int i, j;
/* set number of pins, offset of pin format and format list to search based on pin type */
if (pin_type == SOF_PIN_TYPE_INPUT) {
num_pins = swidget->num_input_pins;
format_list_to_search = available_fmt->input_pin_fmts;
format_list_count = available_fmt->num_input_formats;
} else {
num_pins = swidget->num_output_pins;
pin_format_offset = swidget->num_input_pins;
format_list_to_search = available_fmt->output_pin_fmts;
format_list_count = available_fmt->num_output_formats;
}
for (i = pin_format_offset; i < num_pins + pin_format_offset; i++) {
pin_format = &base_cfg_ext->pin_formats[i];
/* Pin 0 audio formats are derived from the base config input/output format */
if (i == pin_format_offset) {
if (pin_type == SOF_PIN_TYPE_INPUT) {
pin_format->buffer_size = process->base_config.ibs;
pin_format->audio_fmt = process->base_config.audio_fmt;
} else {
pin_format->buffer_size = process->base_config.obs;
pin_format->audio_fmt = process->output_format;
}
continue;
}
/*
* For all other pins, find the pin formats from those set in topology. If there
* is more than one format specified for a pin, this will pick the first available
* one.
*/
for (j = 0; j < format_list_count; j++) {
struct sof_ipc4_pin_format *pin_format_item = &format_list_to_search[j];
if (pin_format_item->pin_index == i - pin_format_offset) {
*pin_format = *pin_format_item;
break;
}
}
if (j == format_list_count) {
dev_err(scomp->dev, "%s pin %d format not found for %s\n",
(pin_type == SOF_PIN_TYPE_INPUT) ? "input" : "output",
i - pin_format_offset, swidget->widget->name);
return -EINVAL;
}
}
return 0;
}
static int sof_ipc4_process_add_base_cfg_extn(struct snd_sof_widget *swidget)
{
int ret, i;
/* copy input and output pin formats */
for (i = 0; i <= SOF_PIN_TYPE_OUTPUT; i++) {
ret = sof_ipc4_process_set_pin_formats(swidget, i);
if (ret < 0)
return ret;
}
return 0;
}
static int sof_ipc4_prepare_process_module(struct snd_sof_widget *swidget,
struct snd_pcm_hw_params *fe_params,
struct snd_sof_platform_stream_params *platform_params,
struct snd_pcm_hw_params *pipeline_params, int dir)
{
struct snd_soc_component *scomp = swidget->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_process *process = swidget->private;
struct sof_ipc4_available_audio_format *available_fmt = &process->available_fmt;
struct sof_ipc4_audio_format *in_fmt;
u32 out_ref_rate, out_ref_channels, out_ref_valid_bits;
void *cfg = process->ipc_config_data;
int output_fmt_index;
int ret;
ret = sof_ipc4_init_input_audio_fmt(sdev, swidget, &process->base_config,
pipeline_params, available_fmt);
if (ret < 0)
return ret;
in_fmt = &available_fmt->input_pin_fmts[ret].audio_fmt;
out_ref_rate = in_fmt->sampling_frequency;
out_ref_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(in_fmt->fmt_cfg);
out_ref_valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(in_fmt->fmt_cfg);
output_fmt_index = sof_ipc4_init_output_audio_fmt(sdev, &process->base_config,
available_fmt, out_ref_rate,
out_ref_channels, out_ref_valid_bits);
if (output_fmt_index < 0 && available_fmt->num_output_formats) {
dev_err(sdev->dev, "Failed to initialize output format for %s",
swidget->widget->name);
return output_fmt_index;
}
/* copy Pin 0 output format */
if (available_fmt->num_output_formats &&
output_fmt_index < available_fmt->num_output_formats &&
!available_fmt->output_pin_fmts[output_fmt_index].pin_index) {
memcpy(&process->output_format,
&available_fmt->output_pin_fmts[output_fmt_index].audio_fmt,
sizeof(struct sof_ipc4_audio_format));
/* modify the pipeline params with the pin 0 output format */
ret = sof_ipc4_update_hw_params(sdev, pipeline_params, &process->output_format);
if (ret)
return ret;
}
/* update pipeline memory usage */
sof_ipc4_update_resource_usage(sdev, swidget, &process->base_config);
/* ipc_config_data is composed of the base_config followed by an optional extension */
memcpy(cfg, &process->base_config, sizeof(struct sof_ipc4_base_module_cfg));
cfg += sizeof(struct sof_ipc4_base_module_cfg);
if (process->init_config == SOF_IPC4_MODULE_INIT_CONFIG_TYPE_BASE_CFG_WITH_EXT) {
struct sof_ipc4_base_module_cfg_ext *base_cfg_ext = process->base_config_ext;
ret = sof_ipc4_process_add_base_cfg_extn(swidget);
if (ret < 0)
return ret;
memcpy(cfg, base_cfg_ext, process->base_config_ext_size);
}
return 0;
}
static int sof_ipc4_control_load_volume(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
struct sof_ipc4_control_data *control_data;
struct sof_ipc4_msg *msg;
int i;
scontrol->size = struct_size(control_data, chanv, scontrol->num_channels);
/* scontrol->ipc_control_data will be freed in sof_control_unload */
scontrol->ipc_control_data = kzalloc(scontrol->size, GFP_KERNEL);
if (!scontrol->ipc_control_data)
return -ENOMEM;
control_data = scontrol->ipc_control_data;
control_data->index = scontrol->index;
msg = &control_data->msg;
msg->primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_SET);
msg->primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg->primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg->extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_GAIN_PARAM_ID);
/* set default volume values to 0dB in control */
for (i = 0; i < scontrol->num_channels; i++) {
control_data->chanv[i].channel = i;
control_data->chanv[i].value = SOF_IPC4_VOL_ZERO_DB;
}
return 0;
}
static int sof_ipc4_control_load_bytes(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
struct sof_ipc4_control_data *control_data;
struct sof_ipc4_msg *msg;
int ret;
if (scontrol->max_size < (sizeof(*control_data) + sizeof(struct sof_abi_hdr))) {
dev_err(sdev->dev, "insufficient size for a bytes control %s: %zu.\n",
scontrol->name, scontrol->max_size);
return -EINVAL;
}
if (scontrol->priv_size > scontrol->max_size - sizeof(*control_data)) {
dev_err(sdev->dev, "scontrol %s bytes data size %zu exceeds max %zu.\n",
scontrol->name, scontrol->priv_size,
scontrol->max_size - sizeof(*control_data));
return -EINVAL;
}
scontrol->size = sizeof(struct sof_ipc4_control_data) + scontrol->priv_size;
scontrol->ipc_control_data = kzalloc(scontrol->max_size, GFP_KERNEL);
if (!scontrol->ipc_control_data)
return -ENOMEM;
control_data = scontrol->ipc_control_data;
control_data->index = scontrol->index;
if (scontrol->priv_size > 0) {
memcpy(control_data->data, scontrol->priv, scontrol->priv_size);
kfree(scontrol->priv);
scontrol->priv = NULL;
if (control_data->data->magic != SOF_IPC4_ABI_MAGIC) {
dev_err(sdev->dev, "Wrong ABI magic (%#x) for control: %s\n",
control_data->data->magic, scontrol->name);
ret = -EINVAL;
goto err;
}
/* TODO: check the ABI version */
if (control_data->data->size + sizeof(struct sof_abi_hdr) !=
scontrol->priv_size) {
dev_err(sdev->dev, "Control %s conflict in bytes %zu vs. priv size %zu.\n",
scontrol->name,
control_data->data->size + sizeof(struct sof_abi_hdr),
scontrol->priv_size);
ret = -EINVAL;
goto err;
}
}
msg = &control_data->msg;
msg->primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_SET);
msg->primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg->primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
return 0;
err:
kfree(scontrol->ipc_control_data);
scontrol->ipc_control_data = NULL;
return ret;
}
static int sof_ipc4_control_setup(struct snd_sof_dev *sdev, struct snd_sof_control *scontrol)
{
switch (scontrol->info_type) {
case SND_SOC_TPLG_CTL_VOLSW:
case SND_SOC_TPLG_CTL_VOLSW_SX:
case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
return sof_ipc4_control_load_volume(sdev, scontrol);
case SND_SOC_TPLG_CTL_BYTES:
return sof_ipc4_control_load_bytes(sdev, scontrol);
default:
break;
}
return 0;
}
static int sof_ipc4_widget_setup(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_pipeline *pipeline;
struct sof_ipc4_msg *msg;
void *ipc_data = NULL;
u32 ipc_size = 0;
int ret;
switch (swidget->id) {
case snd_soc_dapm_scheduler:
pipeline = swidget->private;
if (pipeline->use_chain_dma) {
dev_warn(sdev->dev, "use_chain_dma set for scheduler %s",
swidget->widget->name);
return 0;
}
dev_dbg(sdev->dev, "pipeline: %d memory pages: %d\n", swidget->pipeline_id,
pipeline->mem_usage);
msg = &pipeline->msg;
msg->primary |= pipeline->mem_usage;
swidget->instance_id = ida_alloc_max(&pipeline_ida, ipc4_data->max_num_pipelines,
GFP_KERNEL);
if (swidget->instance_id < 0) {
dev_err(sdev->dev, "failed to assign pipeline id for %s: %d\n",
swidget->widget->name, swidget->instance_id);
return swidget->instance_id;
}
msg->primary &= ~SOF_IPC4_GLB_PIPE_INSTANCE_MASK;
msg->primary |= SOF_IPC4_GLB_PIPE_INSTANCE_ID(swidget->instance_id);
break;
case snd_soc_dapm_aif_in:
case snd_soc_dapm_aif_out:
case snd_soc_dapm_buffer:
{
struct sof_ipc4_copier *ipc4_copier = swidget->private;
pipeline = pipe_widget->private;
if (pipeline->use_chain_dma)
return 0;
ipc_size = ipc4_copier->ipc_config_size;
ipc_data = ipc4_copier->ipc_config_data;
msg = &ipc4_copier->msg;
break;
}
case snd_soc_dapm_dai_in:
case snd_soc_dapm_dai_out:
{
struct snd_sof_dai *dai = swidget->private;
struct sof_ipc4_copier *ipc4_copier = dai->private;
pipeline = pipe_widget->private;
if (pipeline->use_chain_dma)
return 0;
ipc_size = ipc4_copier->ipc_config_size;
ipc_data = ipc4_copier->ipc_config_data;
msg = &ipc4_copier->msg;
break;
}
case snd_soc_dapm_pga:
{
struct sof_ipc4_gain *gain = swidget->private;
ipc_size = sizeof(struct sof_ipc4_base_module_cfg) +
sizeof(struct sof_ipc4_gain_data);
ipc_data = gain;
msg = &gain->msg;
break;
}
case snd_soc_dapm_mixer:
{
struct sof_ipc4_mixer *mixer = swidget->private;
ipc_size = sizeof(mixer->base_config);
ipc_data = &mixer->base_config;
msg = &mixer->msg;
break;
}
case snd_soc_dapm_src:
{
struct sof_ipc4_src *src = swidget->private;
ipc_size = sizeof(struct sof_ipc4_base_module_cfg) + sizeof(src->sink_rate);
ipc_data = src;
msg = &src->msg;
break;
}
case snd_soc_dapm_effect:
{
struct sof_ipc4_process *process = swidget->private;
if (!process->ipc_config_size) {
dev_err(sdev->dev, "module %s has no config data!\n",
swidget->widget->name);
return -EINVAL;
}
ipc_size = process->ipc_config_size;
ipc_data = process->ipc_config_data;
msg = &process->msg;
break;
}
default:
dev_err(sdev->dev, "widget type %d not supported", swidget->id);
return -EINVAL;
}
if (swidget->id != snd_soc_dapm_scheduler) {
ret = sof_ipc4_widget_assign_instance_id(sdev, swidget);
if (ret < 0) {
dev_err(sdev->dev, "failed to assign instance id for %s\n",
swidget->widget->name);
return ret;
}
msg->primary &= ~SOF_IPC4_MOD_INSTANCE_MASK;
msg->primary |= SOF_IPC4_MOD_INSTANCE(swidget->instance_id);
msg->extension &= ~SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK;
msg->extension |= ipc_size >> 2;
msg->extension &= ~SOF_IPC4_MOD_EXT_PPL_ID_MASK;
msg->extension |= SOF_IPC4_MOD_EXT_PPL_ID(pipe_widget->instance_id);
}
dev_dbg(sdev->dev, "Create widget %s instance %d - pipe %d - core %d\n",
swidget->widget->name, swidget->instance_id, swidget->pipeline_id, swidget->core);
msg->data_size = ipc_size;
msg->data_ptr = ipc_data;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, msg, ipc_size);
if (ret < 0) {
dev_err(sdev->dev, "failed to create module %s\n", swidget->widget->name);
if (swidget->id != snd_soc_dapm_scheduler) {
struct sof_ipc4_fw_module *fw_module = swidget->module_info;
ida_free(&fw_module->m_ida, swidget->instance_id);
} else {
ida_free(&pipeline_ida, swidget->instance_id);
}
}
return ret;
}
static int sof_ipc4_widget_free(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
struct sof_ipc4_fw_module *fw_module = swidget->module_info;
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
int ret = 0;
mutex_lock(&ipc4_data->pipeline_state_mutex);
/* freeing a pipeline frees all the widgets associated with it */
if (swidget->id == snd_soc_dapm_scheduler) {
struct sof_ipc4_pipeline *pipeline = swidget->private;
struct sof_ipc4_msg msg = {{ 0 }};
u32 header;
if (pipeline->use_chain_dma) {
dev_warn(sdev->dev, "use_chain_dma set for scheduler %s",
swidget->widget->name);
mutex_unlock(&ipc4_data->pipeline_state_mutex);
return 0;
}
header = SOF_IPC4_GLB_PIPE_INSTANCE_ID(swidget->instance_id);
header |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_DELETE_PIPELINE);
header |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
header |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
msg.primary = header;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
if (ret < 0)
dev_err(sdev->dev, "failed to free pipeline widget %s\n",
swidget->widget->name);
pipeline->mem_usage = 0;
pipeline->state = SOF_IPC4_PIPE_UNINITIALIZED;
ida_free(&pipeline_ida, swidget->instance_id);
swidget->instance_id = -EINVAL;
} else {
struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
if (!pipeline->use_chain_dma)
ida_free(&fw_module->m_ida, swidget->instance_id);
}
mutex_unlock(&ipc4_data->pipeline_state_mutex);
return ret;
}
static int sof_ipc4_get_queue_id(struct snd_sof_widget *src_widget,
struct snd_sof_widget *sink_widget, bool pin_type)
{
struct snd_sof_widget *current_swidget;
struct snd_soc_component *scomp;
struct ida *queue_ida;
const char *buddy_name;
char **pin_binding;
u32 num_pins;
int i;
if (pin_type == SOF_PIN_TYPE_OUTPUT) {
current_swidget = src_widget;
pin_binding = src_widget->output_pin_binding;
queue_ida = &src_widget->output_queue_ida;
num_pins = src_widget->num_output_pins;
buddy_name = sink_widget->widget->name;
} else {
current_swidget = sink_widget;
pin_binding = sink_widget->input_pin_binding;
queue_ida = &sink_widget->input_queue_ida;
num_pins = sink_widget->num_input_pins;
buddy_name = src_widget->widget->name;
}
scomp = current_swidget->scomp;
if (num_pins < 1) {
dev_err(scomp->dev, "invalid %s num_pins: %d for queue allocation for %s\n",
(pin_type == SOF_PIN_TYPE_OUTPUT ? "output" : "input"),
num_pins, current_swidget->widget->name);
return -EINVAL;
}
/* If there is only one input/output pin, queue id must be 0 */
if (num_pins == 1)
return 0;
/* Allocate queue ID from pin binding array if it is defined in topology. */
if (pin_binding) {
for (i = 0; i < num_pins; i++) {
if (!strcmp(pin_binding[i], buddy_name))
return i;
}
/*
* Fail if no queue ID found from pin binding array, so that we don't
* mixed use pin binding array and ida for queue ID allocation.
*/
dev_err(scomp->dev, "no %s queue id found from pin binding array for %s\n",
(pin_type == SOF_PIN_TYPE_OUTPUT ? "output" : "input"),
current_swidget->widget->name);
return -EINVAL;
}
/* If no pin binding array specified in topology, use ida to allocate one */
return ida_alloc_max(queue_ida, num_pins, GFP_KERNEL);
}
static void sof_ipc4_put_queue_id(struct snd_sof_widget *swidget, int queue_id,
bool pin_type)
{
struct ida *queue_ida;
char **pin_binding;
int num_pins;
if (pin_type == SOF_PIN_TYPE_OUTPUT) {
pin_binding = swidget->output_pin_binding;
queue_ida = &swidget->output_queue_ida;
num_pins = swidget->num_output_pins;
} else {
pin_binding = swidget->input_pin_binding;
queue_ida = &swidget->input_queue_ida;
num_pins = swidget->num_input_pins;
}
/* Nothing to free if queue ID is not allocated with ida. */
if (num_pins == 1 || pin_binding)
return;
ida_free(queue_ida, queue_id);
}
static int sof_ipc4_set_copier_sink_format(struct snd_sof_dev *sdev,
struct snd_sof_widget *src_widget,
struct snd_sof_widget *sink_widget,
int sink_id)
{
struct sof_ipc4_copier_config_set_sink_format format;
const struct sof_ipc_ops *iops = sdev->ipc->ops;
struct sof_ipc4_base_module_cfg *src_config;
const struct sof_ipc4_audio_format *pin_fmt;
struct sof_ipc4_fw_module *fw_module;
struct sof_ipc4_msg msg = {{ 0 }};
dev_dbg(sdev->dev, "%s set copier sink %d format\n",
src_widget->widget->name, sink_id);
if (WIDGET_IS_DAI(src_widget->id)) {
struct snd_sof_dai *dai = src_widget->private;
src_config = dai->private;
} else {
src_config = src_widget->private;
}
fw_module = src_widget->module_info;
format.sink_id = sink_id;
memcpy(&format.source_fmt, &src_config->audio_fmt, sizeof(format.source_fmt));
pin_fmt = sof_ipc4_get_input_pin_audio_fmt(sink_widget, sink_id);
if (!pin_fmt) {
dev_err(sdev->dev, "Unable to get pin %d format for %s",
sink_id, sink_widget->widget->name);
return -EINVAL;
}
memcpy(&format.sink_fmt, pin_fmt, sizeof(format.sink_fmt));
msg.data_size = sizeof(format);
msg.data_ptr = &format;
msg.primary = fw_module->man4_module_entry.id;
msg.primary |= SOF_IPC4_MOD_INSTANCE(src_widget->instance_id);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.extension =
SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_COPIER_MODULE_CFG_PARAM_SET_SINK_FORMAT);
return iops->set_get_data(sdev, &msg, msg.data_size, true);
}
static int sof_ipc4_route_setup(struct snd_sof_dev *sdev, struct snd_sof_route *sroute)
{
struct snd_sof_widget *src_widget = sroute->src_widget;
struct snd_sof_widget *sink_widget = sroute->sink_widget;
struct snd_sof_widget *src_pipe_widget = src_widget->spipe->pipe_widget;
struct snd_sof_widget *sink_pipe_widget = sink_widget->spipe->pipe_widget;
struct sof_ipc4_fw_module *src_fw_module = src_widget->module_info;
struct sof_ipc4_fw_module *sink_fw_module = sink_widget->module_info;
struct sof_ipc4_pipeline *src_pipeline = src_pipe_widget->private;
struct sof_ipc4_pipeline *sink_pipeline = sink_pipe_widget->private;
struct sof_ipc4_msg msg = {{ 0 }};
u32 header, extension;
int ret;
/* no route set up if chain DMA is used */
if (src_pipeline->use_chain_dma || sink_pipeline->use_chain_dma) {
if (!src_pipeline->use_chain_dma || !sink_pipeline->use_chain_dma) {
dev_err(sdev->dev,
"use_chain_dma must be set for both src %s and sink %s pipelines\n",
src_widget->widget->name, sink_widget->widget->name);
return -EINVAL;
}
return 0;
}
if (!src_fw_module || !sink_fw_module) {
dev_err(sdev->dev,
"cannot bind %s -> %s, no firmware module for: %s%s\n",
src_widget->widget->name, sink_widget->widget->name,
src_fw_module ? "" : " source",
sink_fw_module ? "" : " sink");
return -ENODEV;
}
sroute->src_queue_id = sof_ipc4_get_queue_id(src_widget, sink_widget,
SOF_PIN_TYPE_OUTPUT);
if (sroute->src_queue_id < 0) {
dev_err(sdev->dev, "failed to get queue ID for source widget: %s\n",
src_widget->widget->name);
return sroute->src_queue_id;
}
sroute->dst_queue_id = sof_ipc4_get_queue_id(src_widget, sink_widget,
SOF_PIN_TYPE_INPUT);
if (sroute->dst_queue_id < 0) {
dev_err(sdev->dev, "failed to get queue ID for sink widget: %s\n",
sink_widget->widget->name);
sof_ipc4_put_queue_id(src_widget, sroute->src_queue_id,
SOF_PIN_TYPE_OUTPUT);
return sroute->dst_queue_id;
}
/* Pin 0 format is already set during copier module init */
if (sroute->src_queue_id > 0 && WIDGET_IS_COPIER(src_widget->id)) {
ret = sof_ipc4_set_copier_sink_format(sdev, src_widget, sink_widget,
sroute->src_queue_id);
if (ret < 0) {
dev_err(sdev->dev, "failed to set sink format for %s source queue ID %d\n",
src_widget->widget->name, sroute->src_queue_id);
goto out;
}
}
dev_dbg(sdev->dev, "bind %s:%d -> %s:%d\n",
src_widget->widget->name, sroute->src_queue_id,
sink_widget->widget->name, sroute->dst_queue_id);
header = src_fw_module->man4_module_entry.id;
header |= SOF_IPC4_MOD_INSTANCE(src_widget->instance_id);
header |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_BIND);
header |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
header |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
extension = sink_fw_module->man4_module_entry.id;
extension |= SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(sink_widget->instance_id);
extension |= SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(sroute->dst_queue_id);
extension |= SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(sroute->src_queue_id);
msg.primary = header;
msg.extension = extension;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
if (ret < 0) {
dev_err(sdev->dev, "failed to bind modules %s:%d -> %s:%d\n",
src_widget->widget->name, sroute->src_queue_id,
sink_widget->widget->name, sroute->dst_queue_id);
goto out;
}
return ret;
out:
sof_ipc4_put_queue_id(src_widget, sroute->src_queue_id, SOF_PIN_TYPE_OUTPUT);
sof_ipc4_put_queue_id(sink_widget, sroute->dst_queue_id, SOF_PIN_TYPE_INPUT);
return ret;
}
static int sof_ipc4_route_free(struct snd_sof_dev *sdev, struct snd_sof_route *sroute)
{
struct snd_sof_widget *src_widget = sroute->src_widget;
struct snd_sof_widget *sink_widget = sroute->sink_widget;
struct sof_ipc4_fw_module *src_fw_module = src_widget->module_info;
struct sof_ipc4_fw_module *sink_fw_module = sink_widget->module_info;
struct sof_ipc4_msg msg = {{ 0 }};
struct snd_sof_widget *src_pipe_widget = src_widget->spipe->pipe_widget;
struct snd_sof_widget *sink_pipe_widget = sink_widget->spipe->pipe_widget;
struct sof_ipc4_pipeline *src_pipeline = src_pipe_widget->private;
struct sof_ipc4_pipeline *sink_pipeline = sink_pipe_widget->private;
u32 header, extension;
int ret = 0;
/* no route is set up if chain DMA is used */
if (src_pipeline->use_chain_dma || sink_pipeline->use_chain_dma)
return 0;
dev_dbg(sdev->dev, "unbind modules %s:%d -> %s:%d\n",
src_widget->widget->name, sroute->src_queue_id,
sink_widget->widget->name, sroute->dst_queue_id);
/*
* routes belonging to the same pipeline will be disconnected by the FW when the pipeline
* is freed. So avoid sending this IPC which will be ignored by the FW anyway.
*/
if (src_widget->spipe->pipe_widget == sink_widget->spipe->pipe_widget)
goto out;
header = src_fw_module->man4_module_entry.id;
header |= SOF_IPC4_MOD_INSTANCE(src_widget->instance_id);
header |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_UNBIND);
header |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
header |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
extension = sink_fw_module->man4_module_entry.id;
extension |= SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(sink_widget->instance_id);
extension |= SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(sroute->dst_queue_id);
extension |= SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(sroute->src_queue_id);
msg.primary = header;
msg.extension = extension;
ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
if (ret < 0)
dev_err(sdev->dev, "failed to unbind modules %s:%d -> %s:%d\n",
src_widget->widget->name, sroute->src_queue_id,
sink_widget->widget->name, sroute->dst_queue_id);
out:
sof_ipc4_put_queue_id(sink_widget, sroute->dst_queue_id, SOF_PIN_TYPE_INPUT);
sof_ipc4_put_queue_id(src_widget, sroute->src_queue_id, SOF_PIN_TYPE_OUTPUT);
return ret;
}
static int sof_ipc4_dai_config(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget,
unsigned int flags, struct snd_sof_dai_config_data *data)
{
struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
struct snd_sof_dai *dai = swidget->private;
struct sof_ipc4_gtw_attributes *gtw_attr;
struct sof_ipc4_copier_data *copier_data;
struct sof_ipc4_copier *ipc4_copier;
if (!dai || !dai->private) {
dev_err(sdev->dev, "Invalid DAI or DAI private data for %s\n",
swidget->widget->name);
return -EINVAL;
}
ipc4_copier = (struct sof_ipc4_copier *)dai->private;
copier_data = &ipc4_copier->data;
if (!data)
return 0;
switch (ipc4_copier->dai_type) {
case SOF_DAI_INTEL_HDA:
if (pipeline->use_chain_dma) {
pipeline->msg.primary &= ~SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK;
pipeline->msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(data->dai_data);
break;
}
gtw_attr = ipc4_copier->gtw_attr;
gtw_attr->lp_buffer_alloc = pipeline->lp_mode;
fallthrough;
case SOF_DAI_INTEL_ALH:
/*
* Do not clear the node ID when this op is invoked with
* SOF_DAI_CONFIG_FLAGS_HW_FREE. It is needed to free the group_ida during
* unprepare.
*/
if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) {
copier_data->gtw_cfg.node_id &= ~SOF_IPC4_NODE_INDEX_MASK;
copier_data->gtw_cfg.node_id |= SOF_IPC4_NODE_INDEX(data->dai_data);
}
break;
case SOF_DAI_INTEL_DMIC:
case SOF_DAI_INTEL_SSP:
/* nothing to do for SSP/DMIC */
break;
default:
dev_err(sdev->dev, "%s: unsupported dai type %d\n", __func__,
ipc4_copier->dai_type);
return -EINVAL;
}
return 0;
}
static int sof_ipc4_parse_manifest(struct snd_soc_component *scomp, int index,
struct snd_soc_tplg_manifest *man)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_manifest_tlv *manifest_tlv;
struct sof_manifest *manifest;
u32 size = le32_to_cpu(man->priv.size);
u8 *man_ptr = man->priv.data;
u32 len_check;
int i;
if (!size || size < SOF_IPC4_TPLG_ABI_SIZE) {
dev_err(scomp->dev, "%s: Invalid topology ABI size: %u\n",
__func__, size);
return -EINVAL;
}
manifest = (struct sof_manifest *)man_ptr;
dev_info(scomp->dev,
"Topology: ABI %d:%d:%d Kernel ABI %u:%u:%u\n",
le16_to_cpu(manifest->abi_major), le16_to_cpu(manifest->abi_minor),
le16_to_cpu(manifest->abi_patch),
SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
/* TODO: Add ABI compatibility check */
/* no more data after the ABI version */
if (size <= SOF_IPC4_TPLG_ABI_SIZE)
return 0;
manifest_tlv = manifest->items;
len_check = sizeof(struct sof_manifest);
for (i = 0; i < le16_to_cpu(manifest->count); i++) {
len_check += sizeof(struct sof_manifest_tlv) + le32_to_cpu(manifest_tlv->size);
if (len_check > size)
return -EINVAL;
switch (le32_to_cpu(manifest_tlv->type)) {
case SOF_MANIFEST_DATA_TYPE_NHLT:
/* no NHLT in BIOS, so use the one from topology manifest */
if (ipc4_data->nhlt)
break;
ipc4_data->nhlt = devm_kmemdup(sdev->dev, manifest_tlv->data,
le32_to_cpu(manifest_tlv->size), GFP_KERNEL);
if (!ipc4_data->nhlt)
return -ENOMEM;
break;
default:
dev_warn(scomp->dev, "Skipping unknown manifest data type %d\n",
manifest_tlv->type);
break;
}
man_ptr += sizeof(struct sof_manifest_tlv) + le32_to_cpu(manifest_tlv->size);
manifest_tlv = (struct sof_manifest_tlv *)man_ptr;
}
return 0;
}
static int sof_ipc4_dai_get_clk(struct snd_sof_dev *sdev, struct snd_sof_dai *dai, int clk_type)
{
struct sof_ipc4_copier *ipc4_copier = dai->private;
struct snd_soc_tplg_hw_config *hw_config;
struct snd_sof_dai_link *slink;
bool dai_link_found = false;
bool hw_cfg_found = false;
int i;
if (!ipc4_copier)
return 0;
list_for_each_entry(slink, &sdev->dai_link_list, list) {
if (!strcmp(slink->link->name, dai->name)) {
dai_link_found = true;
break;
}
}
if (!dai_link_found) {
dev_err(sdev->dev, "no DAI link found for DAI %s\n", dai->name);
return -EINVAL;
}
for (i = 0; i < slink->num_hw_configs; i++) {
hw_config = &slink->hw_configs[i];
if (dai->current_config == le32_to_cpu(hw_config->id)) {
hw_cfg_found = true;
break;
}
}
if (!hw_cfg_found) {
dev_err(sdev->dev, "no matching hw_config found for DAI %s\n", dai->name);
return -EINVAL;
}
switch (ipc4_copier->dai_type) {
case SOF_DAI_INTEL_SSP:
switch (clk_type) {
case SOF_DAI_CLK_INTEL_SSP_MCLK:
return le32_to_cpu(hw_config->mclk_rate);
case SOF_DAI_CLK_INTEL_SSP_BCLK:
return le32_to_cpu(hw_config->bclk_rate);
default:
dev_err(sdev->dev, "Invalid clk type for SSP %d\n", clk_type);
break;
}
break;
default:
dev_err(sdev->dev, "DAI type %d not supported yet!\n", ipc4_copier->dai_type);
break;
}
return -EINVAL;
}
static int sof_ipc4_tear_down_all_pipelines(struct snd_sof_dev *sdev, bool verify)
{
struct snd_sof_pcm *spcm;
int dir, ret;
/*
* This function is called during system suspend, we need to make sure
* that all streams have been freed up.
* Freeing might have been skipped when xrun happened just at the start
* of the suspend and it sent a SNDRV_PCM_TRIGGER_STOP to the active
* stream. This will call sof_pcm_stream_free() with
* free_widget_list = false which will leave the kernel and firmware out
* of sync during suspend/resume.
*
* This will also make sure that paused streams handled correctly.
*/
list_for_each_entry(spcm, &sdev->pcm_list, list) {
for_each_pcm_streams(dir) {
struct snd_pcm_substream *substream = spcm->stream[dir].substream;
if (!substream || !substream->runtime || spcm->stream[dir].suspend_ignored)
continue;
if (spcm->stream[dir].list) {
ret = sof_pcm_stream_free(sdev, substream, spcm, dir, true);
if (ret < 0)
return ret;
}
}
}
return 0;
}
static int sof_ipc4_link_setup(struct snd_sof_dev *sdev, struct snd_soc_dai_link *link)
{
if (link->no_pcm)
return 0;
/*
* set default trigger order for all links. Exceptions to
* the rule will be handled in sof_pcm_dai_link_fixup()
* For playback, the sequence is the following: start BE,
* start FE, stop FE, stop BE; for Capture the sequence is
* inverted start FE, start BE, stop BE, stop FE
*/
link->trigger[SNDRV_PCM_STREAM_PLAYBACK] = SND_SOC_DPCM_TRIGGER_POST;
link->trigger[SNDRV_PCM_STREAM_CAPTURE] = SND_SOC_DPCM_TRIGGER_PRE;
return 0;
}
static enum sof_tokens common_copier_token_list[] = {
SOF_COMP_TOKENS,
SOF_AUDIO_FMT_NUM_TOKENS,
SOF_IN_AUDIO_FORMAT_TOKENS,
SOF_OUT_AUDIO_FORMAT_TOKENS,
SOF_COPIER_DEEP_BUFFER_TOKENS,
SOF_COPIER_TOKENS,
SOF_COMP_EXT_TOKENS,
};
static enum sof_tokens pipeline_token_list[] = {
SOF_SCHED_TOKENS,
SOF_PIPELINE_TOKENS,
};
static enum sof_tokens dai_token_list[] = {
SOF_COMP_TOKENS,
SOF_AUDIO_FMT_NUM_TOKENS,
SOF_IN_AUDIO_FORMAT_TOKENS,
SOF_OUT_AUDIO_FORMAT_TOKENS,
SOF_COPIER_TOKENS,
SOF_DAI_TOKENS,
SOF_COMP_EXT_TOKENS,
};
static enum sof_tokens pga_token_list[] = {
SOF_COMP_TOKENS,
SOF_GAIN_TOKENS,
SOF_AUDIO_FMT_NUM_TOKENS,
SOF_IN_AUDIO_FORMAT_TOKENS,
SOF_OUT_AUDIO_FORMAT_TOKENS,
SOF_COMP_EXT_TOKENS,
};
static enum sof_tokens mixer_token_list[] = {
SOF_COMP_TOKENS,
SOF_AUDIO_FMT_NUM_TOKENS,
SOF_IN_AUDIO_FORMAT_TOKENS,
SOF_OUT_AUDIO_FORMAT_TOKENS,
SOF_COMP_EXT_TOKENS,
};
static enum sof_tokens src_token_list[] = {
SOF_COMP_TOKENS,
SOF_SRC_TOKENS,
SOF_AUDIO_FMT_NUM_TOKENS,
SOF_IN_AUDIO_FORMAT_TOKENS,
SOF_OUT_AUDIO_FORMAT_TOKENS,
SOF_COMP_EXT_TOKENS,
};
static enum sof_tokens process_token_list[] = {
SOF_COMP_TOKENS,
SOF_AUDIO_FMT_NUM_TOKENS,
SOF_IN_AUDIO_FORMAT_TOKENS,
SOF_OUT_AUDIO_FORMAT_TOKENS,
SOF_COMP_EXT_TOKENS,
};
static const struct sof_ipc_tplg_widget_ops tplg_ipc4_widget_ops[SND_SOC_DAPM_TYPE_COUNT] = {
[snd_soc_dapm_aif_in] = {sof_ipc4_widget_setup_pcm, sof_ipc4_widget_free_comp_pcm,
common_copier_token_list, ARRAY_SIZE(common_copier_token_list),
NULL, sof_ipc4_prepare_copier_module,
sof_ipc4_unprepare_copier_module},
[snd_soc_dapm_aif_out] = {sof_ipc4_widget_setup_pcm, sof_ipc4_widget_free_comp_pcm,
common_copier_token_list, ARRAY_SIZE(common_copier_token_list),
NULL, sof_ipc4_prepare_copier_module,
sof_ipc4_unprepare_copier_module},
[snd_soc_dapm_dai_in] = {sof_ipc4_widget_setup_comp_dai, sof_ipc4_widget_free_comp_dai,
dai_token_list, ARRAY_SIZE(dai_token_list), NULL,
sof_ipc4_prepare_copier_module,
sof_ipc4_unprepare_copier_module},
[snd_soc_dapm_dai_out] = {sof_ipc4_widget_setup_comp_dai, sof_ipc4_widget_free_comp_dai,
dai_token_list, ARRAY_SIZE(dai_token_list), NULL,
sof_ipc4_prepare_copier_module,
sof_ipc4_unprepare_copier_module},
[snd_soc_dapm_buffer] = {sof_ipc4_widget_setup_pcm, sof_ipc4_widget_free_comp_pcm,
common_copier_token_list, ARRAY_SIZE(common_copier_token_list),
NULL, sof_ipc4_prepare_copier_module,
sof_ipc4_unprepare_copier_module},
[snd_soc_dapm_scheduler] = {sof_ipc4_widget_setup_comp_pipeline,
sof_ipc4_widget_free_comp_pipeline,
pipeline_token_list, ARRAY_SIZE(pipeline_token_list), NULL,
NULL, NULL},
[snd_soc_dapm_pga] = {sof_ipc4_widget_setup_comp_pga, sof_ipc4_widget_free_comp_pga,
pga_token_list, ARRAY_SIZE(pga_token_list), NULL,
sof_ipc4_prepare_gain_module,
NULL},
[snd_soc_dapm_mixer] = {sof_ipc4_widget_setup_comp_mixer, sof_ipc4_widget_free_comp_mixer,
mixer_token_list, ARRAY_SIZE(mixer_token_list),
NULL, sof_ipc4_prepare_mixer_module,
NULL},
[snd_soc_dapm_src] = {sof_ipc4_widget_setup_comp_src, sof_ipc4_widget_free_comp_src,
src_token_list, ARRAY_SIZE(src_token_list),
NULL, sof_ipc4_prepare_src_module,
NULL},
[snd_soc_dapm_effect] = {sof_ipc4_widget_setup_comp_process,
sof_ipc4_widget_free_comp_process,
process_token_list, ARRAY_SIZE(process_token_list),
NULL, sof_ipc4_prepare_process_module,
NULL},
};
const struct sof_ipc_tplg_ops ipc4_tplg_ops = {
.widget = tplg_ipc4_widget_ops,
.token_list = ipc4_token_list,
.control_setup = sof_ipc4_control_setup,
.control = &tplg_ipc4_control_ops,
.widget_setup = sof_ipc4_widget_setup,
.widget_free = sof_ipc4_widget_free,
.route_setup = sof_ipc4_route_setup,
.route_free = sof_ipc4_route_free,
.dai_config = sof_ipc4_dai_config,
.parse_manifest = sof_ipc4_parse_manifest,
.dai_get_clk = sof_ipc4_dai_get_clk,
.tear_down_all_pipelines = sof_ipc4_tear_down_all_pipelines,
.link_setup = sof_ipc4_link_setup,
};
| linux-master | sound/soc/sof/ipc4-topology.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
//
#include "sof-priv.h"
#include "sof-audio.h"
#include "ipc4-priv.h"
#include "ipc4-topology.h"
static int sof_ipc4_set_get_kcontrol_data(struct snd_sof_control *scontrol,
bool set, bool lock)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
const struct sof_ipc_ops *iops = sdev->ipc->ops;
struct sof_ipc4_msg *msg = &cdata->msg;
struct snd_sof_widget *swidget;
bool widget_found = false;
int ret = 0;
/* find widget associated with the control */
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (swidget->comp_id == scontrol->comp_id) {
widget_found = true;
break;
}
}
if (!widget_found) {
dev_err(scomp->dev, "Failed to find widget for kcontrol %s\n", scontrol->name);
return -ENOENT;
}
if (lock)
mutex_lock(&swidget->setup_mutex);
else
lockdep_assert_held(&swidget->setup_mutex);
/*
* Volatile controls should always be part of static pipelines and the
* widget use_count would always be > 0 in this case. For the others,
* just return the cached value if the widget is not set up.
*/
if (!swidget->use_count)
goto unlock;
msg->primary &= ~SOF_IPC4_MOD_INSTANCE_MASK;
msg->primary |= SOF_IPC4_MOD_INSTANCE(swidget->instance_id);
ret = iops->set_get_data(sdev, msg, msg->data_size, set);
if (!set)
goto unlock;
/* It is a set-data operation, and we have a valid backup that we can restore */
if (ret < 0) {
if (!scontrol->old_ipc_control_data)
goto unlock;
/*
* Current ipc_control_data is not valid, we use the last known good
* configuration
*/
memcpy(scontrol->ipc_control_data, scontrol->old_ipc_control_data,
scontrol->max_size);
kfree(scontrol->old_ipc_control_data);
scontrol->old_ipc_control_data = NULL;
/* Send the last known good configuration to firmware */
ret = iops->set_get_data(sdev, msg, msg->data_size, set);
if (ret < 0)
goto unlock;
}
unlock:
if (lock)
mutex_unlock(&swidget->setup_mutex);
return ret;
}
static int
sof_ipc4_set_volume_data(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget,
struct snd_sof_control *scontrol, bool lock)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct sof_ipc4_gain *gain = swidget->private;
struct sof_ipc4_msg *msg = &cdata->msg;
struct sof_ipc4_gain_data data;
bool all_channels_equal = true;
u32 value;
int ret, i;
/* check if all channel values are equal */
value = cdata->chanv[0].value;
for (i = 1; i < scontrol->num_channels; i++) {
if (cdata->chanv[i].value != value) {
all_channels_equal = false;
break;
}
}
/*
* notify DSP with a single IPC message if all channel values are equal. Otherwise send
* a separate IPC for each channel.
*/
for (i = 0; i < scontrol->num_channels; i++) {
if (all_channels_equal) {
data.channels = SOF_IPC4_GAIN_ALL_CHANNELS_MASK;
data.init_val = cdata->chanv[0].value;
} else {
data.channels = cdata->chanv[i].channel;
data.init_val = cdata->chanv[i].value;
}
/* set curve type and duration from topology */
data.curve_duration_l = gain->data.curve_duration_l;
data.curve_duration_h = gain->data.curve_duration_h;
data.curve_type = gain->data.curve_type;
msg->data_ptr = &data;
msg->data_size = sizeof(data);
ret = sof_ipc4_set_get_kcontrol_data(scontrol, true, lock);
msg->data_ptr = NULL;
msg->data_size = 0;
if (ret < 0) {
dev_err(sdev->dev, "Failed to set volume update for %s\n",
scontrol->name);
return ret;
}
if (all_channels_equal)
break;
}
return 0;
}
static bool sof_ipc4_volume_put(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
unsigned int channels = scontrol->num_channels;
struct snd_sof_widget *swidget;
bool widget_found = false;
bool change = false;
unsigned int i;
int ret;
/* update each channel */
for (i = 0; i < channels; i++) {
u32 value = mixer_to_ipc(ucontrol->value.integer.value[i],
scontrol->volume_table, scontrol->max + 1);
change = change || (value != cdata->chanv[i].value);
cdata->chanv[i].channel = i;
cdata->chanv[i].value = value;
}
if (!pm_runtime_active(scomp->dev))
return change;
/* find widget associated with the control */
list_for_each_entry(swidget, &sdev->widget_list, list) {
if (swidget->comp_id == scontrol->comp_id) {
widget_found = true;
break;
}
}
if (!widget_found) {
dev_err(scomp->dev, "Failed to find widget for kcontrol %s\n", scontrol->name);
return false;
}
ret = sof_ipc4_set_volume_data(sdev, swidget, scontrol, true);
if (ret < 0)
return false;
return change;
}
static int sof_ipc4_volume_get(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
unsigned int channels = scontrol->num_channels;
unsigned int i;
for (i = 0; i < channels; i++)
ucontrol->value.integer.value[i] = ipc_to_mixer(cdata->chanv[i].value,
scontrol->volume_table,
scontrol->max + 1);
return 0;
}
static int sof_ipc4_set_get_bytes_data(struct snd_sof_dev *sdev,
struct snd_sof_control *scontrol,
bool set, bool lock)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct sof_abi_hdr *data = cdata->data;
struct sof_ipc4_msg *msg = &cdata->msg;
int ret = 0;
/* Send the new data to the firmware only if it is powered up */
if (set && !pm_runtime_active(sdev->dev))
return 0;
msg->extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(data->type);
msg->data_ptr = data->data;
msg->data_size = data->size;
ret = sof_ipc4_set_get_kcontrol_data(scontrol, set, lock);
if (ret < 0)
dev_err(sdev->dev, "Failed to %s for %s\n",
set ? "set bytes update" : "get bytes",
scontrol->name);
msg->data_ptr = NULL;
msg->data_size = 0;
return ret;
}
static int sof_ipc4_bytes_put(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_abi_hdr *data = cdata->data;
size_t size;
if (scontrol->max_size > sizeof(ucontrol->value.bytes.data)) {
dev_err_ratelimited(scomp->dev,
"data max %zu exceeds ucontrol data array size\n",
scontrol->max_size);
return -EINVAL;
}
/* scontrol->max_size has been verified to be >= sizeof(struct sof_abi_hdr) */
if (data->size > scontrol->max_size - sizeof(*data)) {
dev_err_ratelimited(scomp->dev,
"data size too big %u bytes max is %zu\n",
data->size, scontrol->max_size - sizeof(*data));
return -EINVAL;
}
size = data->size + sizeof(*data);
/* copy from kcontrol */
memcpy(data, ucontrol->value.bytes.data, size);
sof_ipc4_set_get_bytes_data(sdev, scontrol, true, true);
return 0;
}
static int sof_ipc4_bytes_get(struct snd_sof_control *scontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct sof_abi_hdr *data = cdata->data;
size_t size;
if (scontrol->max_size > sizeof(ucontrol->value.bytes.data)) {
dev_err_ratelimited(scomp->dev, "data max %zu exceeds ucontrol data array size\n",
scontrol->max_size);
return -EINVAL;
}
if (data->size > scontrol->max_size - sizeof(*data)) {
dev_err_ratelimited(scomp->dev,
"%u bytes of control data is invalid, max is %zu\n",
data->size, scontrol->max_size - sizeof(*data));
return -EINVAL;
}
size = data->size + sizeof(*data);
/* copy back to kcontrol */
memcpy(ucontrol->value.bytes.data, data, size);
return 0;
}
static int sof_ipc4_bytes_ext_put(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
struct snd_ctl_tlv __user *tlvd = (struct snd_ctl_tlv __user *)binary_data;
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
struct sof_abi_hdr *data = cdata->data;
struct sof_abi_hdr abi_hdr;
struct snd_ctl_tlv header;
/*
* The beginning of bytes data contains a header from where
* the length (as bytes) is needed to know the correct copy
* length of data from tlvd->tlv.
*/
if (copy_from_user(&header, tlvd, sizeof(struct snd_ctl_tlv)))
return -EFAULT;
/* make sure TLV info is consistent */
if (header.length + sizeof(struct snd_ctl_tlv) > size) {
dev_err_ratelimited(scomp->dev,
"Inconsistent TLV, data %d + header %zu > %d\n",
header.length, sizeof(struct snd_ctl_tlv), size);
return -EINVAL;
}
/* be->max is coming from topology */
if (header.length > scontrol->max_size) {
dev_err_ratelimited(scomp->dev,
"Bytes data size %d exceeds max %zu\n",
header.length, scontrol->max_size);
return -EINVAL;
}
/* Verify the ABI header first */
if (copy_from_user(&abi_hdr, tlvd->tlv, sizeof(abi_hdr)))
return -EFAULT;
if (abi_hdr.magic != SOF_IPC4_ABI_MAGIC) {
dev_err_ratelimited(scomp->dev, "Wrong ABI magic 0x%08x\n",
abi_hdr.magic);
return -EINVAL;
}
if (abi_hdr.size > scontrol->max_size - sizeof(abi_hdr)) {
dev_err_ratelimited(scomp->dev,
"%u bytes of control data is invalid, max is %zu\n",
abi_hdr.size, scontrol->max_size - sizeof(abi_hdr));
return -EINVAL;
}
if (!scontrol->old_ipc_control_data) {
/* Create a backup of the current, valid bytes control */
scontrol->old_ipc_control_data = kmemdup(scontrol->ipc_control_data,
scontrol->max_size, GFP_KERNEL);
if (!scontrol->old_ipc_control_data)
return -ENOMEM;
}
/* Copy the whole binary data which includes the ABI header and the payload */
if (copy_from_user(data, tlvd->tlv, header.length)) {
memcpy(scontrol->ipc_control_data, scontrol->old_ipc_control_data,
scontrol->max_size);
kfree(scontrol->old_ipc_control_data);
scontrol->old_ipc_control_data = NULL;
return -EFAULT;
}
return sof_ipc4_set_get_bytes_data(sdev, scontrol, true, true);
}
static int _sof_ipc4_bytes_ext_get(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size, bool from_dsp)
{
struct snd_ctl_tlv __user *tlvd = (struct snd_ctl_tlv __user *)binary_data;
struct sof_ipc4_control_data *cdata = scontrol->ipc_control_data;
struct snd_soc_component *scomp = scontrol->scomp;
struct sof_abi_hdr *data = cdata->data;
struct snd_ctl_tlv header;
size_t data_size;
/*
* Decrement the limit by ext bytes header size to ensure the user space
* buffer is not exceeded.
*/
if (size < sizeof(struct snd_ctl_tlv))
return -ENOSPC;
size -= sizeof(struct snd_ctl_tlv);
/* get all the component data from DSP */
if (from_dsp) {
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
int ret = sof_ipc4_set_get_bytes_data(sdev, scontrol, false, true);
if (ret < 0)
return ret;
/* Set the ABI magic (if the control is not initialized) */
data->magic = SOF_IPC4_ABI_MAGIC;
}
if (data->size > scontrol->max_size - sizeof(*data)) {
dev_err_ratelimited(scomp->dev,
"%u bytes of control data is invalid, max is %zu\n",
data->size, scontrol->max_size - sizeof(*data));
return -EINVAL;
}
data_size = data->size + sizeof(struct sof_abi_hdr);
/* make sure we don't exceed size provided by user space for data */
if (data_size > size)
return -ENOSPC;
header.numid = scontrol->comp_id;
header.length = data_size;
if (copy_to_user(tlvd, &header, sizeof(struct snd_ctl_tlv)))
return -EFAULT;
if (copy_to_user(tlvd->tlv, data, data_size))
return -EFAULT;
return 0;
}
static int sof_ipc4_bytes_ext_get(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
return _sof_ipc4_bytes_ext_get(scontrol, binary_data, size, false);
}
static int sof_ipc4_bytes_ext_volatile_get(struct snd_sof_control *scontrol,
const unsigned int __user *binary_data,
unsigned int size)
{
return _sof_ipc4_bytes_ext_get(scontrol, binary_data, size, true);
}
/* set up all controls for the widget */
static int sof_ipc4_widget_kcontrol_setup(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget)
{
struct snd_sof_control *scontrol;
int ret = 0;
list_for_each_entry(scontrol, &sdev->kcontrol_list, list) {
if (scontrol->comp_id == swidget->comp_id) {
switch (scontrol->info_type) {
case SND_SOC_TPLG_CTL_VOLSW:
case SND_SOC_TPLG_CTL_VOLSW_SX:
case SND_SOC_TPLG_CTL_VOLSW_XR_SX:
ret = sof_ipc4_set_volume_data(sdev, swidget,
scontrol, false);
break;
case SND_SOC_TPLG_CTL_BYTES:
ret = sof_ipc4_set_get_bytes_data(sdev, scontrol,
true, false);
break;
default:
break;
}
if (ret < 0) {
dev_err(sdev->dev,
"kcontrol %d set up failed for widget %s\n",
scontrol->comp_id, swidget->widget->name);
return ret;
}
}
}
return 0;
}
static int
sof_ipc4_set_up_volume_table(struct snd_sof_control *scontrol, int tlv[SOF_TLV_ITEMS], int size)
{
int i;
/* init the volume table */
scontrol->volume_table = kcalloc(size, sizeof(u32), GFP_KERNEL);
if (!scontrol->volume_table)
return -ENOMEM;
/* populate the volume table */
for (i = 0; i < size ; i++) {
u32 val = vol_compute_gain(i, tlv);
u64 q31val = ((u64)val) << 15; /* Can be over Q1.31, need to saturate */
scontrol->volume_table[i] = q31val > SOF_IPC4_VOL_ZERO_DB ?
SOF_IPC4_VOL_ZERO_DB : q31val;
}
return 0;
}
const struct sof_ipc_tplg_control_ops tplg_ipc4_control_ops = {
.volume_put = sof_ipc4_volume_put,
.volume_get = sof_ipc4_volume_get,
.bytes_put = sof_ipc4_bytes_put,
.bytes_get = sof_ipc4_bytes_get,
.bytes_ext_put = sof_ipc4_bytes_ext_put,
.bytes_ext_get = sof_ipc4_bytes_ext_get,
.bytes_ext_volatile_get = sof_ipc4_bytes_ext_volatile_get,
.widget_kcontrol_setup = sof_ipc4_widget_kcontrol_setup,
.set_up_volume_table = sof_ipc4_set_up_volume_table,
};
| linux-master | sound/soc/sof/ipc4-control.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
#include <sound/pcm_params.h>
#include <sound/sof/ipc4/header.h>
#include "sof-audio.h"
#include "sof-priv.h"
#include "ops.h"
#include "ipc4-priv.h"
#include "ipc4-topology.h"
#include "ipc4-fw-reg.h"
static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
struct ipc4_pipeline_set_state_data *trigger_list)
{
struct sof_ipc4_msg msg = {{ 0 }};
u32 primary, ipc_size;
/* trigger a single pipeline */
if (trigger_list->count == 1)
return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0],
state);
primary = state;
primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
msg.primary = primary;
/* trigger multiple pipelines with a single IPC */
msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
/* ipc_size includes the count and the pipeline IDs for the number of pipelines */
ipc_size = sizeof(u32) * (trigger_list->count + 1);
msg.data_size = ipc_size;
msg.data_ptr = trigger_list;
return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
}
int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state)
{
struct sof_ipc4_msg msg = {{ 0 }};
u32 primary;
dev_dbg(sdev->dev, "ipc4 set pipeline instance %d state %d", instance_id, state);
primary = state;
primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id);
primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
msg.primary = primary;
return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
}
EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
static void
sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
struct snd_sof_pipeline *spipe,
struct ipc4_pipeline_set_state_data *trigger_list)
{
struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
return;
switch (state) {
case SOF_IPC4_PIPE_RUNNING:
/*
* Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
* for the first time
*/
if (spipe->started_count == spipe->paused_count)
trigger_list->pipeline_instance_ids[trigger_list->count++] =
pipe_widget->instance_id;
break;
case SOF_IPC4_PIPE_RESET:
/* RESET if the pipeline is neither running nor paused */
if (!spipe->started_count && !spipe->paused_count)
trigger_list->pipeline_instance_ids[trigger_list->count++] =
pipe_widget->instance_id;
break;
case SOF_IPC4_PIPE_PAUSED:
/* Pause the pipeline only when its started_count is 1 more than paused_count */
if (spipe->paused_count == (spipe->started_count - 1))
trigger_list->pipeline_instance_ids[trigger_list->count++] =
pipe_widget->instance_id;
break;
default:
break;
}
}
static void
sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
struct snd_sof_pipeline *spipe,
struct ipc4_pipeline_set_state_data *trigger_list)
{
struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
int i;
if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
return;
/* set state for pipeline if it was just triggered */
for (i = 0; i < trigger_list->count; i++) {
if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) {
pipeline->state = state;
break;
}
}
switch (state) {
case SOF_IPC4_PIPE_PAUSED:
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/*
* increment paused_count if the PAUSED is the final state during
* the PAUSE trigger
*/
spipe->paused_count++;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
/*
* decrement started_count if PAUSED is the final state during the
* STOP trigger
*/
spipe->started_count--;
break;
default:
break;
}
break;
case SOF_IPC4_PIPE_RUNNING:
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/* decrement paused_count for RELEASE */
spipe->paused_count--;
break;
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
/* increment started_count for START/RESUME */
spipe->started_count++;
break;
default:
break;
}
break;
default:
break;
}
}
/*
* The picture below represents the pipeline state machine wrt PCM actions corresponding to the
* triggers and ioctls
* +---------------+
* | |
* | INIT |
* | |
* +-------+-------+
* |
* |
* | START
* |
* |
* +----------------+ +------v-------+ +-------------+
* | | START | | HW_FREE | |
* | RUNNING <-------------+ PAUSED +--------------> + RESET |
* | | PAUSE | | | |
* +------+---------+ RELEASE +---------+----+ +-------------+
* | ^
* | |
* | |
* | |
* | PAUSE |
* +---------------------------------+
* STOP/SUSPEND
*
* Note that during system suspend, the suspend trigger is followed by a hw_free in
* sof_pcm_trigger(). So, the final state during suspend would be RESET.
* Also, since the SOF driver doesn't support full resume, streams would be restarted with the
* prepare ioctl before the START trigger.
*/
/*
* Chained DMA is a special case where there is no processing on
* DSP. The samples are just moved over by host side DMA to a single
* buffer on DSP and directly from there to link DMA. However, the
* model on SOF driver has two notional pipelines, one at host DAI,
* and another at link DAI. They both shall have the use_chain_dma
* attribute.
*/
static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
int state, int cmd)
{
bool allocate, enable, set_fifo_size;
struct sof_ipc4_msg msg = {{ 0 }};
int i;
switch (state) {
case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
allocate = true;
enable = true;
/*
* SOF assumes creation of a new stream from the presence of fifo_size
* in the message, so we must leave it out in pause release case.
*/
if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
set_fifo_size = false;
else
set_fifo_size = true;
break;
case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
allocate = true;
enable = false;
set_fifo_size = false;
break;
case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
allocate = false;
enable = false;
set_fifo_size = false;
break;
default:
dev_err(sdev->dev, "Unexpected state %d", state);
return -EINVAL;
}
msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
/*
* To set-up the DMA chain, the host DMA ID and SCS setting
* are retrieved from the host pipeline configuration. Likewise
* the link DMA ID and fifo_size are retrieved from the link
* pipeline configuration.
*/
for (i = 0; i < pipeline_list->count; i++) {
struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
if (!pipeline->use_chain_dma) {
dev_err(sdev->dev,
"All pipelines in chained DMA stream should have use_chain_dma attribute set.");
return -EINVAL;
}
msg.primary |= pipeline->msg.primary;
/* Add fifo_size (actually DMA buffer size) field to the message */
if (set_fifo_size)
msg.extension |= pipeline->msg.extension;
}
if (allocate)
msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
if (enable)
msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
}
static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int state, int cmd)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct ipc4_pipeline_set_state_data *trigger_list;
struct snd_sof_widget *pipe_widget;
struct sof_ipc4_pipeline *pipeline;
struct snd_sof_pipeline *spipe;
struct snd_sof_pcm *spcm;
int ret;
int i;
dev_dbg(sdev->dev, "trigger cmd: %d state: %d\n", cmd, state);
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
pipeline_list = &spcm->stream[substream->stream].pipeline_list;
/* nothing to trigger if the list is empty */
if (!pipeline_list->pipelines || !pipeline_list->count)
return 0;
spipe = pipeline_list->pipelines[0];
pipe_widget = spipe->pipe_widget;
pipeline = pipe_widget->private;
/*
* If use_chain_dma attribute is set we proceed to chained DMA
* trigger function that handles the rest for the substream.
*/
if (pipeline->use_chain_dma)
return sof_ipc4_chain_dma_trigger(sdev, pipeline_list, state, cmd);
/* allocate memory for the pipeline data */
trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids,
pipeline_list->count), GFP_KERNEL);
if (!trigger_list)
return -ENOMEM;
mutex_lock(&ipc4_data->pipeline_state_mutex);
/*
* IPC4 requires pipelines to be triggered in order starting at the sink and
* walking all the way to the source. So traverse the pipeline_list in the order
* sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
* Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
* in the pipeline, the order of triggering between the left/right paths will be
* indeterministic. But the sink->source trigger order sink->source would still be
* guaranteed for each fork independently.
*/
if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
for (i = pipeline_list->count - 1; i >= 0; i--) {
spipe = pipeline_list->pipelines[i];
sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list);
}
else
for (i = 0; i < pipeline_list->count; i++) {
spipe = pipeline_list->pipelines[i];
sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list);
}
/* return if all pipelines are in the requested state already */
if (!trigger_list->count) {
ret = 0;
goto free;
}
/* no need to pause before reset or before pause release */
if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
goto skip_pause_transition;
/*
* set paused state for pipelines if the final state is PAUSED or when the pipeline
* is set to RUNNING for the first time after the PCM is started.
*/
ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
if (ret < 0) {
dev_err(sdev->dev, "failed to pause all pipelines\n");
goto free;
}
/* update PAUSED state for all pipelines just triggered */
for (i = 0; i < pipeline_list->count ; i++) {
spipe = pipeline_list->pipelines[i];
sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
trigger_list);
}
/* return if this is the final state */
if (state == SOF_IPC4_PIPE_PAUSED)
goto free;
skip_pause_transition:
/* else set the RUNNING/RESET state in the DSP */
ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
if (ret < 0) {
dev_err(sdev->dev, "failed to set final state %d for all pipelines\n", state);
goto free;
}
/* update RUNNING/RESET state for all pipelines that were just triggered */
for (i = 0; i < pipeline_list->count; i++) {
spipe = pipeline_list->pipelines[i];
sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
}
free:
mutex_unlock(&ipc4_data->pipeline_state_mutex);
kfree(trigger_list);
return ret;
}
static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
int state;
/* determine the pipeline state */
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
state = SOF_IPC4_PIPE_PAUSED;
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_START:
state = SOF_IPC4_PIPE_RUNNING;
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
state = SOF_IPC4_PIPE_PAUSED;
break;
default:
dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
return -EINVAL;
}
/* set the pipeline state */
return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
}
static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
/* command is not relevant with RESET, so just pass 0 */
return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
}
static void ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
struct snd_pcm_hw_params *params)
{
struct snd_sof_dai_link *slink;
struct snd_sof_dai *dai;
bool dai_link_found = false;
int i;
list_for_each_entry(slink, &sdev->dai_link_list, list) {
if (!strcmp(slink->link->name, link_name)) {
dai_link_found = true;
break;
}
}
if (!dai_link_found)
return;
for (i = 0; i < slink->num_hw_configs; i++) {
struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate)) {
/* set current config for all DAI's with matching name */
list_for_each_entry(dai, &sdev->dai_list, list)
if (!strcmp(slink->link->name, dai->name))
dai->current_config = le32_to_cpu(hw_config->id);
break;
}
}
}
/*
* Fixup DAI link parameters for sampling rate based on
* DAI copier configuration.
*/
static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
struct snd_pcm_hw_params *params,
struct sof_ipc4_copier *ipc4_copier)
{
struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
unsigned int fe_rate = params_rate(params);
bool fe_be_rate_match = false;
bool single_be_rate = true;
unsigned int be_rate;
int i;
/*
* Copier does not change sampling rate, so we
* need to only consider the input pin information.
*/
for (i = 0; i < num_input_formats; i++) {
unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
if (i == 0)
be_rate = val;
else if (val != be_rate)
single_be_rate = false;
if (val == fe_rate) {
fe_be_rate_match = true;
break;
}
}
/*
* If rate is different than FE rate, topology must
* contain an SRC. But we do require topology to
* define a single rate in the DAI copier config in
* this case (FE rate may be variable).
*/
if (!fe_be_rate_match) {
if (!single_be_rate) {
dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
return -EINVAL;
}
rate->min = be_rate;
rate->max = rate->min;
}
return 0;
}
static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sof_ipc4_copier *ipc4_copier;
bool use_chain_dma = false;
int dir;
if (!dai) {
dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
rtd->dai_link->name);
return -EINVAL;
}
ipc4_copier = dai->private;
if (!ipc4_copier) {
dev_err(component->dev, "%s: No private data found for DAI %s\n",
__func__, rtd->dai_link->name);
return -EINVAL;
}
for_each_pcm_streams(dir) {
struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
if (w) {
struct snd_sof_widget *swidget = w->dobj.private;
struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
if (pipeline->use_chain_dma)
use_chain_dma = true;
}
}
/* Chain DMA does not use copiers, so no fixup needed */
if (!use_chain_dma) {
int ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
if (ret)
return ret;
}
switch (ipc4_copier->dai_type) {
case SOF_DAI_INTEL_SSP:
ipc4_ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
break;
default:
break;
}
return 0;
}
static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
{
struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
int stream;
for_each_pcm_streams(stream) {
pipeline_list = &spcm->stream[stream].pipeline_list;
kfree(pipeline_list->pipelines);
pipeline_list->pipelines = NULL;
kfree(spcm->stream[stream].private);
spcm->stream[stream].private = NULL;
}
}
static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
{
struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
struct sof_ipc4_timestamp_info *stream_info;
bool support_info = true;
u32 abi_version;
u32 abi_offset;
int stream;
abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
sizeof(abi_version));
if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
support_info = false;
for_each_pcm_streams(stream) {
pipeline_list = &spcm->stream[stream].pipeline_list;
/* allocate memory for max number of pipeline IDs */
pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
sizeof(struct snd_sof_widget *), GFP_KERNEL);
if (!pipeline_list->pipelines) {
sof_ipc4_pcm_free(sdev, spcm);
return -ENOMEM;
}
if (!support_info)
continue;
stream_info = kzalloc(sizeof(*stream_info), GFP_KERNEL);
if (!stream_info) {
sof_ipc4_pcm_free(sdev, spcm);
return -ENOMEM;
}
spcm->stream[stream].private = stream_info;
}
return 0;
}
static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *spcm)
{
struct sof_ipc4_copier *host_copier = NULL;
struct sof_ipc4_copier *dai_copier = NULL;
struct sof_ipc4_llp_reading_slot llp_slot;
struct sof_ipc4_timestamp_info *info;
struct snd_soc_dapm_widget *widget;
struct snd_sof_dai *dai;
int i;
/* find host & dai to locate info in memory window */
for_each_dapm_widgets(spcm->list, i, widget) {
struct snd_sof_widget *swidget = widget->dobj.private;
if (!swidget)
continue;
if (WIDGET_IS_AIF(swidget->widget->id)) {
host_copier = swidget->private;
} else if (WIDGET_IS_DAI(swidget->widget->id)) {
dai = swidget->private;
dai_copier = dai->private;
}
}
/* both host and dai copier must be valid for time_info */
if (!host_copier || !dai_copier) {
dev_err(sdev->dev, "host or dai copier are not found\n");
return;
}
info = spcm->private;
info->host_copier = host_copier;
info->dai_copier = dai_copier;
info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_gpdma_reading_slots) +
sdev->fw_info_box.offset;
/* find llp slot used by current dai */
for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
break;
info->llp_offset += sizeof(llp_slot);
}
if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
return;
/* if no llp gpdma slot is used, check aggregated sdw slot */
info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_sndw_reading_slots) +
sdev->fw_info_box.offset;
for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
break;
info->llp_offset += sizeof(llp_slot);
}
if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
return;
/* check EVAD slot */
info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_evad_reading_slot) +
sdev->fw_info_box.offset;
sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id) {
dev_info(sdev->dev, "no llp found, fall back to default HDA path");
info->llp_offset = 0;
}
}
static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_sof_platform_stream_params *platform_params)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sof_ipc4_timestamp_info *time_info;
struct snd_sof_pcm *spcm;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return -EINVAL;
time_info = spcm->stream[substream->stream].private;
/* delay calculation is not supported by current fw_reg ABI */
if (!time_info)
return 0;
time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
time_info->llp_offset = 0;
sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
return 0;
}
static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream,
struct snd_sof_pcm_stream *stream,
struct sof_ipc4_timestamp_info *time_info)
{
struct sof_ipc4_copier *host_copier = time_info->host_copier;
struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
struct sof_ipc4_pipeline_registers ppl_reg;
u64 stream_start_position;
u32 dai_sample_size;
u32 ch, node_index;
u32 offset;
if (!host_copier || !dai_copier)
return -EINVAL;
if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID)
return -EINVAL;
node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
return -EINVAL;
stream_start_position = ppl_reg.stream_start_offset;
ch = dai_copier->data.out_format.fmt_cfg;
ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
/* convert offset to sample count */
do_div(stream_start_position, dai_sample_size);
time_info->stream_start_offset = stream_start_position;
return 0;
}
static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sof_ipc4_timestamp_info *time_info;
struct sof_ipc4_llp_reading_slot llp;
snd_pcm_uframes_t head_ptr, tail_ptr;
struct snd_sof_pcm_stream *stream;
struct snd_sof_pcm *spcm;
u64 tmp_ptr;
int ret;
spcm = snd_sof_find_spcm_dai(component, rtd);
if (!spcm)
return 0;
stream = &spcm->stream[substream->stream];
time_info = stream->private;
if (!time_info)
return 0;
/*
* stream_start_offset is updated to memory window by FW based on
* pipeline statistics and it may be invalid if host query happens before
* the statistics is complete. And it will not change after the first initiailization.
*/
if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
ret = sof_ipc4_get_stream_start_offset(sdev, substream, stream, time_info);
if (ret < 0)
return 0;
}
/*
* HDaudio links don't support the LLP counter reported by firmware
* the link position is read directly from hardware registers.
*/
if (!time_info->llp_offset) {
tmp_ptr = snd_sof_pcm_get_stream_position(sdev, component, substream);
if (!tmp_ptr)
return 0;
} else {
sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
tmp_ptr = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
}
/* In two cases dai dma position is not accurate
* (1) dai pipeline is started before host pipeline
* (2) multiple streams mixed into one. Each stream has the same dai dma position
*
* Firmware calculates correct stream_start_offset for all cases including above two.
* Driver subtracts stream_start_offset from dai dma position to get accurate one
*/
tmp_ptr -= time_info->stream_start_offset;
/* Calculate the delay taking into account that both pointer can wrap */
div64_u64_rem(tmp_ptr, substream->runtime->boundary, &tmp_ptr);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
head_ptr = substream->runtime->status->hw_ptr;
tail_ptr = tmp_ptr;
} else {
head_ptr = tmp_ptr;
tail_ptr = substream->runtime->status->hw_ptr;
}
if (head_ptr < tail_ptr)
return substream->runtime->boundary - tail_ptr + head_ptr;
return head_ptr - tail_ptr;
}
const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
.hw_params = sof_ipc4_pcm_hw_params,
.trigger = sof_ipc4_pcm_trigger,
.hw_free = sof_ipc4_pcm_hw_free,
.dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
.pcm_setup = sof_ipc4_pcm_setup,
.pcm_free = sof_ipc4_pcm_free,
.delay = sof_ipc4_pcm_delay,
.ipc_first_on_start = true,
.platform_stop_during_hw_free = true,
};
| linux-master | sound/soc/sof/ipc4-pcm.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright 2021-2022 NXP
//
// Author: Peng Zhang <[email protected]>
//
// Hardware interface for audio DSP on i.MX8ULP
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/firmware/imx/dsp.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/svc/misc.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include "../ops.h"
#include "../sof-of-dev.h"
#include "imx-common.h"
#define FSL_SIP_HIFI_XRDC 0xc200000e
/* SIM Domain register */
#define SYSCTRL0 0x8
#define EXECUTE_BIT BIT(13)
#define RESET_BIT BIT(16)
#define HIFI4_CLK_BIT BIT(17)
#define PB_CLK_BIT BIT(18)
#define PLAT_CLK_BIT BIT(19)
#define DEBUG_LOGIC_BIT BIT(25)
#define MBOX_OFFSET 0x800000
#define MBOX_SIZE 0x1000
static struct clk_bulk_data imx8ulp_dsp_clks[] = {
{ .id = "core" },
{ .id = "ipg" },
{ .id = "ocram" },
{ .id = "mu" },
};
struct imx8ulp_priv {
struct device *dev;
struct snd_sof_dev *sdev;
/* DSP IPC handler */
struct imx_dsp_ipc *dsp_ipc;
struct platform_device *ipc_dev;
struct regmap *regmap;
struct imx_clocks *clks;
};
static void imx8ulp_sim_lpav_start(struct imx8ulp_priv *priv)
{
/* Controls the HiFi4 DSP Reset: 1 in reset, 0 out of reset */
regmap_update_bits(priv->regmap, SYSCTRL0, RESET_BIT, 0);
/* Reset HiFi4 DSP Debug logic: 1 debug reset, 0 out of reset*/
regmap_update_bits(priv->regmap, SYSCTRL0, DEBUG_LOGIC_BIT, 0);
/* Stall HIFI4 DSP Execution: 1 stall, 0 run */
regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, 0);
}
static int imx8ulp_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MBOX_OFFSET;
}
static int imx8ulp_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MBOX_OFFSET;
}
static void imx8ulp_dsp_handle_reply(struct imx_dsp_ipc *ipc)
{
struct imx8ulp_priv *priv = imx_dsp_get_data(ipc);
unsigned long flags;
spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
snd_sof_ipc_process_reply(priv->sdev, 0);
spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
}
static void imx8ulp_dsp_handle_request(struct imx_dsp_ipc *ipc)
{
struct imx8ulp_priv *priv = imx_dsp_get_data(ipc);
u32 p; /* panic code */
/* Read the message from the debug box. */
sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
/* Check to see if the message is a panic code (0x0dead***) */
if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
snd_sof_dsp_panic(priv->sdev, p, true);
else
snd_sof_ipc_msgs_rx(priv->sdev);
}
static struct imx_dsp_ops dsp_ops = {
.handle_reply = imx8ulp_dsp_handle_reply,
.handle_request = imx8ulp_dsp_handle_request,
};
static int imx8ulp_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
msg->msg_size);
imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
return 0;
}
static int imx8ulp_run(struct snd_sof_dev *sdev)
{
struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
imx8ulp_sim_lpav_start(priv);
return 0;
}
static int imx8ulp_reset(struct snd_sof_dev *sdev)
{
struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
struct arm_smccc_res smc_resource;
/* HiFi4 Platform Clock Enable: 1 enabled, 0 disabled */
regmap_update_bits(priv->regmap, SYSCTRL0, PLAT_CLK_BIT, PLAT_CLK_BIT);
/* HiFi4 PBCLK clock enable: 1 enabled, 0 disabled */
regmap_update_bits(priv->regmap, SYSCTRL0, PB_CLK_BIT, PB_CLK_BIT);
/* HiFi4 Clock Enable: 1 enabled, 0 disabled */
regmap_update_bits(priv->regmap, SYSCTRL0, HIFI4_CLK_BIT, HIFI4_CLK_BIT);
regmap_update_bits(priv->regmap, SYSCTRL0, RESET_BIT, RESET_BIT);
usleep_range(1, 2);
/* Stall HIFI4 DSP Execution: 1 stall, 0 not stall */
regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, EXECUTE_BIT);
usleep_range(1, 2);
arm_smccc_smc(FSL_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &smc_resource);
return 0;
}
static int imx8ulp_probe(struct snd_sof_dev *sdev)
{
struct platform_device *pdev =
container_of(sdev->dev, struct platform_device, dev);
struct device_node *np = pdev->dev.of_node;
struct device_node *res_node;
struct resource *mmio;
struct imx8ulp_priv *priv;
struct resource res;
u32 base, size;
int ret = 0;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL);
if (!priv->clks)
return -ENOMEM;
sdev->num_cores = 1;
sdev->pdata->hw_pdata = priv;
priv->dev = sdev->dev;
priv->sdev = sdev;
/* System integration module(SIM) control dsp configuration */
priv->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,dsp-ctrl");
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
PLATFORM_DEVID_NONE,
pdev, sizeof(*pdev));
if (IS_ERR(priv->ipc_dev))
return PTR_ERR(priv->ipc_dev);
priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
if (!priv->dsp_ipc) {
/* DSP IPC driver not probed yet, try later */
ret = -EPROBE_DEFER;
dev_err(sdev->dev, "Failed to get drvdata\n");
goto exit_pdev_unregister;
}
imx_dsp_set_data(priv->dsp_ipc, priv);
priv->dsp_ipc->ops = &dsp_ops;
/* DSP base */
mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
ret = -EINVAL;
goto exit_pdev_unregister;
}
sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
base, size);
ret = -ENODEV;
goto exit_pdev_unregister;
}
sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
res_node = of_parse_phandle(np, "memory-reserved", 0);
if (!res_node) {
dev_err(&pdev->dev, "failed to get memory region node\n");
ret = -ENODEV;
goto exit_pdev_unregister;
}
ret = of_address_to_resource(res_node, 0, &res);
of_node_put(res_node);
if (ret) {
dev_err(&pdev->dev, "failed to get reserved region address\n");
goto exit_pdev_unregister;
}
sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
resource_size(&res));
if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
base, size);
ret = -ENOMEM;
goto exit_pdev_unregister;
}
sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = MBOX_OFFSET;
ret = of_reserved_mem_device_init(sdev->dev);
if (ret) {
dev_err(&pdev->dev, "failed to init reserved memory region %d\n", ret);
goto exit_pdev_unregister;
}
priv->clks->dsp_clks = imx8ulp_dsp_clks;
priv->clks->num_dsp_clks = ARRAY_SIZE(imx8ulp_dsp_clks);
ret = imx8_parse_clocks(sdev, priv->clks);
if (ret < 0)
goto exit_pdev_unregister;
ret = imx8_enable_clocks(sdev, priv->clks);
if (ret < 0)
goto exit_pdev_unregister;
return 0;
exit_pdev_unregister:
platform_device_unregister(priv->ipc_dev);
return ret;
}
static int imx8ulp_remove(struct snd_sof_dev *sdev)
{
struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
imx8_disable_clocks(sdev, priv->clks);
platform_device_unregister(priv->ipc_dev);
return 0;
}
/* on i.MX8 there is 1 to 1 match between type and BAR idx */
static int imx8ulp_get_bar_index(struct snd_sof_dev *sdev, u32 type)
{
return type;
}
static int imx8ulp_suspend(struct snd_sof_dev *sdev)
{
int i;
struct imx8ulp_priv *priv = (struct imx8ulp_priv *)sdev->pdata->hw_pdata;
/*Stall DSP, release in .run() */
regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, EXECUTE_BIT);
for (i = 0; i < DSP_MU_CHAN_NUM; i++)
imx_dsp_free_channel(priv->dsp_ipc, i);
imx8_disable_clocks(sdev, priv->clks);
return 0;
}
static int imx8ulp_resume(struct snd_sof_dev *sdev)
{
struct imx8ulp_priv *priv = (struct imx8ulp_priv *)sdev->pdata->hw_pdata;
int i;
imx8_enable_clocks(sdev, priv->clks);
for (i = 0; i < DSP_MU_CHAN_NUM; i++)
imx_dsp_request_channel(priv->dsp_ipc, i);
return 0;
}
static int imx8ulp_dsp_runtime_resume(struct snd_sof_dev *sdev)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D0,
.substate = 0,
};
imx8ulp_resume(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8ulp_dsp_runtime_suspend(struct snd_sof_dev *sdev)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D3,
.substate = 0,
};
imx8ulp_suspend(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8ulp_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = target_state,
.substate = 0,
};
if (!pm_runtime_suspended(sdev->dev))
imx8ulp_suspend(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8ulp_dsp_resume(struct snd_sof_dev *sdev)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D0,
.substate = 0,
};
imx8ulp_resume(sdev);
if (pm_runtime_suspended(sdev->dev)) {
pm_runtime_disable(sdev->dev);
pm_runtime_set_active(sdev->dev);
pm_runtime_mark_last_busy(sdev->dev);
pm_runtime_enable(sdev->dev);
pm_runtime_idle(sdev->dev);
}
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static struct snd_soc_dai_driver imx8ulp_dai[] = {
{
.name = "sai5",
.playback = {
.channels_min = 1,
.channels_max = 32,
},
.capture = {
.channels_min = 1,
.channels_max = 32,
},
},
{
.name = "sai6",
.playback = {
.channels_min = 1,
.channels_max = 32,
},
.capture = {
.channels_min = 1,
.channels_max = 32,
},
},
};
static int imx8ulp_dsp_set_power_state(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
sdev->dsp_power_state = *target_state;
return 0;
}
/* i.MX8 ops */
static struct snd_sof_dsp_ops sof_imx8ulp_ops = {
/* probe and remove */
.probe = imx8ulp_probe,
.remove = imx8ulp_remove,
/* DSP core boot */
.run = imx8ulp_run,
.reset = imx8ulp_reset,
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Module IO */
.read64 = sof_io_read64,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* ipc */
.send_msg = imx8ulp_send_msg,
.get_mailbox_offset = imx8ulp_get_mailbox_offset,
.get_window_offset = imx8ulp_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/* module loading */
.get_bar_index = imx8ulp_get_bar_index,
/* firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* Debug information */
.dbg_dump = imx8_dump,
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
/* DAI drivers */
.drv = imx8ulp_dai,
.num_drv = ARRAY_SIZE(imx8ulp_dai),
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
/* PM */
.runtime_suspend = imx8ulp_dsp_runtime_suspend,
.runtime_resume = imx8ulp_dsp_runtime_resume,
.suspend = imx8ulp_dsp_suspend,
.resume = imx8ulp_dsp_resume,
.set_power_state = imx8ulp_dsp_set_power_state,
};
static struct sof_dev_desc sof_of_imx8ulp_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "imx/sof",
},
.default_tplg_path = {
[SOF_IPC] = "imx/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-imx8ulp.ri",
},
.nocodec_tplg_filename = "sof-imx8ulp-nocodec.tplg",
.ops = &sof_imx8ulp_ops,
};
static const struct of_device_id sof_of_imx8ulp_ids[] = {
{ .compatible = "fsl,imx8ulp-dsp", .data = &sof_of_imx8ulp_desc},
{ }
};
MODULE_DEVICE_TABLE(of, sof_of_imx8ulp_ids);
/* DT driver definition */
static struct platform_driver snd_sof_of_imx8ulp_driver = {
.probe = sof_of_probe,
.remove = sof_of_remove,
.driver = {
.name = "sof-audio-of-imx8ulp",
.pm = &sof_of_pm,
.of_match_table = sof_of_imx8ulp_ids,
},
};
module_platform_driver(snd_sof_of_imx8ulp_driver);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/imx/imx8ulp.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright 2020 NXP
//
// Author: Daniel Baluta <[email protected]>
//
// Hardware interface for audio DSP on i.MX8M
#include <linux/bits.h>
#include <linux/firmware.h>
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include <linux/firmware/imx/dsp.h>
#include "../ops.h"
#include "../sof-of-dev.h"
#include "imx-common.h"
#define MBOX_OFFSET 0x800000
#define MBOX_SIZE 0x1000
static struct clk_bulk_data imx8m_dsp_clks[] = {
{ .id = "ipg" },
{ .id = "ocram" },
{ .id = "core" },
};
/* DAP registers */
#define IMX8M_DAP_DEBUG 0x28800000
#define IMX8M_DAP_DEBUG_SIZE (64 * 1024)
#define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
#define IMX8M_PWRCTL_CORERESET BIT(16)
/* DSP audio mix registers */
#define AudioDSP_REG0 0x100
#define AudioDSP_REG1 0x104
#define AudioDSP_REG2 0x108
#define AudioDSP_REG3 0x10c
#define AudioDSP_REG2_RUNSTALL BIT(5)
struct imx8m_priv {
struct device *dev;
struct snd_sof_dev *sdev;
/* DSP IPC handler */
struct imx_dsp_ipc *dsp_ipc;
struct platform_device *ipc_dev;
struct imx_clocks *clks;
void __iomem *dap;
struct regmap *regmap;
};
static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MBOX_OFFSET;
}
static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MBOX_OFFSET;
}
static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc)
{
struct imx8m_priv *priv = imx_dsp_get_data(ipc);
unsigned long flags;
spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
snd_sof_ipc_process_reply(priv->sdev, 0);
spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
}
static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc)
{
struct imx8m_priv *priv = imx_dsp_get_data(ipc);
u32 p; /* Panic code */
/* Read the message from the debug box. */
sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
/* Check to see if the message is a panic code (0x0dead***) */
if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
snd_sof_dsp_panic(priv->sdev, p, true);
else
snd_sof_ipc_msgs_rx(priv->sdev);
}
static struct imx_dsp_ops imx8m_dsp_ops = {
.handle_reply = imx8m_dsp_handle_reply,
.handle_request = imx8m_dsp_handle_request,
};
static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
struct imx8m_priv *priv = sdev->pdata->hw_pdata;
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
msg->msg_size);
imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
return 0;
}
/*
* DSP control.
*/
static int imx8m_run(struct snd_sof_dev *sdev)
{
struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
regmap_update_bits(priv->regmap, AudioDSP_REG2, AudioDSP_REG2_RUNSTALL, 0);
return 0;
}
static int imx8m_reset(struct snd_sof_dev *sdev)
{
struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
u32 pwrctl;
/* put DSP into reset and stall */
pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL);
pwrctl |= IMX8M_PWRCTL_CORERESET;
writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL);
/* keep reset asserted for 10 cycles */
usleep_range(1, 2);
regmap_update_bits(priv->regmap, AudioDSP_REG2,
AudioDSP_REG2_RUNSTALL, AudioDSP_REG2_RUNSTALL);
/* take the DSP out of reset and keep stalled for FW loading */
pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL);
pwrctl &= ~IMX8M_PWRCTL_CORERESET;
writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL);
return 0;
}
static int imx8m_probe(struct snd_sof_dev *sdev)
{
struct platform_device *pdev =
container_of(sdev->dev, struct platform_device, dev);
struct device_node *np = pdev->dev.of_node;
struct device_node *res_node;
struct resource *mmio;
struct imx8m_priv *priv;
struct resource res;
u32 base, size;
int ret = 0;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL);
if (!priv->clks)
return -ENOMEM;
sdev->num_cores = 1;
sdev->pdata->hw_pdata = priv;
priv->dev = sdev->dev;
priv->sdev = sdev;
priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
PLATFORM_DEVID_NONE,
pdev, sizeof(*pdev));
if (IS_ERR(priv->ipc_dev))
return PTR_ERR(priv->ipc_dev);
priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
if (!priv->dsp_ipc) {
/* DSP IPC driver not probed yet, try later */
ret = -EPROBE_DEFER;
dev_err(sdev->dev, "Failed to get drvdata\n");
goto exit_pdev_unregister;
}
imx_dsp_set_data(priv->dsp_ipc, priv);
priv->dsp_ipc->ops = &imx8m_dsp_ops;
/* DSP base */
mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
ret = -EINVAL;
goto exit_pdev_unregister;
}
priv->dap = devm_ioremap(sdev->dev, IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);
if (!priv->dap) {
dev_err(sdev->dev, "error: failed to map DAP debug memory area");
ret = -ENODEV;
goto exit_pdev_unregister;
}
sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
base, size);
ret = -ENODEV;
goto exit_pdev_unregister;
}
sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
res_node = of_parse_phandle(np, "memory-region", 0);
if (!res_node) {
dev_err(&pdev->dev, "failed to get memory region node\n");
ret = -ENODEV;
goto exit_pdev_unregister;
}
ret = of_address_to_resource(res_node, 0, &res);
of_node_put(res_node);
if (ret) {
dev_err(&pdev->dev, "failed to get reserved region address\n");
goto exit_pdev_unregister;
}
sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
resource_size(&res));
if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
base, size);
ret = -ENOMEM;
goto exit_pdev_unregister;
}
sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = MBOX_OFFSET;
priv->regmap = syscon_regmap_lookup_by_compatible("fsl,dsp-ctrl");
if (IS_ERR(priv->regmap)) {
dev_err(sdev->dev, "cannot find dsp-ctrl registers");
ret = PTR_ERR(priv->regmap);
goto exit_pdev_unregister;
}
/* init clocks info */
priv->clks->dsp_clks = imx8m_dsp_clks;
priv->clks->num_dsp_clks = ARRAY_SIZE(imx8m_dsp_clks);
ret = imx8_parse_clocks(sdev, priv->clks);
if (ret < 0)
goto exit_pdev_unregister;
ret = imx8_enable_clocks(sdev, priv->clks);
if (ret < 0)
goto exit_pdev_unregister;
return 0;
exit_pdev_unregister:
platform_device_unregister(priv->ipc_dev);
return ret;
}
static int imx8m_remove(struct snd_sof_dev *sdev)
{
struct imx8m_priv *priv = sdev->pdata->hw_pdata;
imx8_disable_clocks(sdev, priv->clks);
platform_device_unregister(priv->ipc_dev);
return 0;
}
/* on i.MX8 there is 1 to 1 match between type and BAR idx */
static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type)
{
/* Only IRAM and SRAM bars are valid */
switch (type) {
case SOF_FW_BLK_TYPE_IRAM:
case SOF_FW_BLK_TYPE_SRAM:
return type;
default:
return -EINVAL;
}
}
static struct snd_soc_dai_driver imx8m_dai[] = {
{
.name = "sai1",
.playback = {
.channels_min = 1,
.channels_max = 32,
},
.capture = {
.channels_min = 1,
.channels_max = 32,
},
},
{
.name = "sai3",
.playback = {
.channels_min = 1,
.channels_max = 32,
},
.capture = {
.channels_min = 1,
.channels_max = 32,
},
},
};
static int imx8m_dsp_set_power_state(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
sdev->dsp_power_state = *target_state;
return 0;
}
static int imx8m_resume(struct snd_sof_dev *sdev)
{
struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
int ret;
int i;
ret = imx8_enable_clocks(sdev, priv->clks);
if (ret < 0)
return ret;
for (i = 0; i < DSP_MU_CHAN_NUM; i++)
imx_dsp_request_channel(priv->dsp_ipc, i);
return 0;
}
static void imx8m_suspend(struct snd_sof_dev *sdev)
{
struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;
int i;
for (i = 0; i < DSP_MU_CHAN_NUM; i++)
imx_dsp_free_channel(priv->dsp_ipc, i);
imx8_disable_clocks(sdev, priv->clks);
}
static int imx8m_dsp_runtime_resume(struct snd_sof_dev *sdev)
{
int ret;
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D0,
};
ret = imx8m_resume(sdev);
if (ret < 0)
return ret;
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8m_dsp_runtime_suspend(struct snd_sof_dev *sdev)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D3,
};
imx8m_suspend(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8m_dsp_resume(struct snd_sof_dev *sdev)
{
int ret;
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D0,
};
ret = imx8m_resume(sdev);
if (ret < 0)
return ret;
if (pm_runtime_suspended(sdev->dev)) {
pm_runtime_disable(sdev->dev);
pm_runtime_set_active(sdev->dev);
pm_runtime_mark_last_busy(sdev->dev);
pm_runtime_enable(sdev->dev);
pm_runtime_idle(sdev->dev);
}
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8m_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = target_state,
};
if (!pm_runtime_suspended(sdev->dev))
imx8m_suspend(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
/* i.MX8 ops */
static struct snd_sof_dsp_ops sof_imx8m_ops = {
/* probe and remove */
.probe = imx8m_probe,
.remove = imx8m_remove,
/* DSP core boot */
.run = imx8m_run,
.reset = imx8m_reset,
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* ipc */
.send_msg = imx8m_send_msg,
.get_mailbox_offset = imx8m_get_mailbox_offset,
.get_window_offset = imx8m_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
.get_bar_index = imx8m_get_bar_index,
/* firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* Debug information */
.dbg_dump = imx8_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
/* DAI drivers */
.drv = imx8m_dai,
.num_drv = ARRAY_SIZE(imx8m_dai),
.suspend = imx8m_dsp_suspend,
.resume = imx8m_dsp_resume,
.runtime_suspend = imx8m_dsp_runtime_suspend,
.runtime_resume = imx8m_dsp_runtime_resume,
.set_power_state = imx8m_dsp_set_power_state,
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
};
static struct sof_dev_desc sof_of_imx8mp_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "imx/sof",
},
.default_tplg_path = {
[SOF_IPC] = "imx/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-imx8m.ri",
},
.nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
.ops = &sof_imx8m_ops,
};
static const struct of_device_id sof_of_imx8m_ids[] = {
{ .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc},
{ }
};
MODULE_DEVICE_TABLE(of, sof_of_imx8m_ids);
/* DT driver definition */
static struct platform_driver snd_sof_of_imx8m_driver = {
.probe = sof_of_probe,
.remove = sof_of_remove,
.driver = {
.name = "sof-audio-of-imx8m",
.pm = &sof_of_pm,
.of_match_table = sof_of_imx8m_ids,
},
};
module_platform_driver(snd_sof_of_imx8m_driver);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/imx/imx8m.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright 2020 NXP
//
// Common helpers for the audio DSP on i.MX8
#include <linux/module.h>
#include <sound/sof/xtensa.h>
#include "../ops.h"
#include "imx-common.h"
/**
* imx8_get_registers() - This function is called in case of DSP oops
* in order to gather information about the registers, filename and
* linenumber and stack.
* @sdev: SOF device
* @xoops: Stores information about registers.
* @panic_info: Stores information about filename and line number.
* @stack: Stores the stack dump.
* @stack_words: Size of the stack dump.
*/
void imx8_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* then get panic info */
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
xoops->arch_hdr.totalsize);
return;
}
offset += xoops->arch_hdr.totalsize;
sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
/* then get the stack */
offset += sizeof(*panic_info);
sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
}
/**
* imx8_dump() - This function is called when a panic message is
* received from the firmware.
* @sdev: SOF device
* @flags: parameter not used but required by ops prototype
*/
void imx8_dump(struct snd_sof_dev *sdev, u32 flags)
{
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[IMX8_STACK_DUMP_SIZE];
u32 status;
/* Get information about the panic status from the debug box area.
* Compute the trace point based on the status.
*/
sof_mailbox_read(sdev, sdev->debug_box.offset + 0x4, &status, 4);
/* Get information about the registers, the filename and line
* number and the stack.
*/
imx8_get_registers(sdev, &xoops, &panic_info, stack,
IMX8_STACK_DUMP_SIZE);
/* Print the information to the console */
sof_print_oops_and_stack(sdev, KERN_ERR, status, status, &xoops,
&panic_info, stack, IMX8_STACK_DUMP_SIZE);
}
EXPORT_SYMBOL(imx8_dump);
int imx8_parse_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks)
{
int ret;
ret = devm_clk_bulk_get(sdev->dev, clks->num_dsp_clks, clks->dsp_clks);
if (ret)
dev_err(sdev->dev, "Failed to request DSP clocks\n");
return ret;
}
EXPORT_SYMBOL(imx8_parse_clocks);
int imx8_enable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks)
{
return clk_bulk_prepare_enable(clks->num_dsp_clks, clks->dsp_clks);
}
EXPORT_SYMBOL(imx8_enable_clocks);
void imx8_disable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks)
{
clk_bulk_disable_unprepare(clks->num_dsp_clks, clks->dsp_clks);
}
EXPORT_SYMBOL(imx8_disable_clocks);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/imx/imx-common.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright 2019 NXP
//
// Author: Daniel Baluta <[email protected]>
//
// Hardware interface for audio DSP on i.MX8
#include <linux/firmware.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pm_domain.h>
#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/dsp.h>
#include <linux/firmware/imx/svc/misc.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include "../ops.h"
#include "../sof-of-dev.h"
#include "imx-common.h"
/* DSP memories */
#define IRAM_OFFSET 0x10000
#define IRAM_SIZE (2 * 1024)
#define DRAM0_OFFSET 0x0
#define DRAM0_SIZE (32 * 1024)
#define DRAM1_OFFSET 0x8000
#define DRAM1_SIZE (32 * 1024)
#define SYSRAM_OFFSET 0x18000
#define SYSRAM_SIZE (256 * 1024)
#define SYSROM_OFFSET 0x58000
#define SYSROM_SIZE (192 * 1024)
#define RESET_VECTOR_VADDR 0x596f8000
#define MBOX_OFFSET 0x800000
#define MBOX_SIZE 0x1000
/* DSP clocks */
static struct clk_bulk_data imx8_dsp_clks[] = {
{ .id = "ipg" },
{ .id = "ocram" },
{ .id = "core" },
};
struct imx8_priv {
struct device *dev;
struct snd_sof_dev *sdev;
/* DSP IPC handler */
struct imx_dsp_ipc *dsp_ipc;
struct platform_device *ipc_dev;
/* System Controller IPC handler */
struct imx_sc_ipc *sc_ipc;
/* Power domain handling */
int num_domains;
struct device **pd_dev;
struct device_link **link;
struct imx_clocks *clks;
};
static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MBOX_OFFSET;
}
static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MBOX_OFFSET;
}
static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc)
{
struct imx8_priv *priv = imx_dsp_get_data(ipc);
unsigned long flags;
spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
snd_sof_ipc_process_reply(priv->sdev, 0);
spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
}
static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc)
{
struct imx8_priv *priv = imx_dsp_get_data(ipc);
u32 p; /* panic code */
/* Read the message from the debug box. */
sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
/* Check to see if the message is a panic code (0x0dead***) */
if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
snd_sof_dsp_panic(priv->sdev, p, true);
else
snd_sof_ipc_msgs_rx(priv->sdev);
}
static struct imx_dsp_ops dsp_ops = {
.handle_reply = imx8_dsp_handle_reply,
.handle_request = imx8_dsp_handle_request,
};
static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
struct imx8_priv *priv = sdev->pdata->hw_pdata;
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
msg->msg_size);
imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
return 0;
}
/*
* DSP control.
*/
static int imx8x_run(struct snd_sof_dev *sdev)
{
struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
int ret;
ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
IMX_SC_C_OFS_SEL, 1);
if (ret < 0) {
dev_err(sdev->dev, "Error system address offset source select\n");
return ret;
}
ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
IMX_SC_C_OFS_AUDIO, 0x80);
if (ret < 0) {
dev_err(sdev->dev, "Error system address offset of AUDIO\n");
return ret;
}
ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
IMX_SC_C_OFS_PERIPH, 0x5A);
if (ret < 0) {
dev_err(sdev->dev, "Error system address offset of PERIPH %d\n",
ret);
return ret;
}
ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
IMX_SC_C_OFS_IRQ, 0x51);
if (ret < 0) {
dev_err(sdev->dev, "Error system address offset of IRQ\n");
return ret;
}
imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
RESET_VECTOR_VADDR);
return 0;
}
static int imx8_run(struct snd_sof_dev *sdev)
{
struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
int ret;
ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
IMX_SC_C_OFS_SEL, 0);
if (ret < 0) {
dev_err(sdev->dev, "Error system address offset source select\n");
return ret;
}
imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
RESET_VECTOR_VADDR);
return 0;
}
static int imx8_probe(struct snd_sof_dev *sdev)
{
struct platform_device *pdev =
container_of(sdev->dev, struct platform_device, dev);
struct device_node *np = pdev->dev.of_node;
struct device_node *res_node;
struct resource *mmio;
struct imx8_priv *priv;
struct resource res;
u32 base, size;
int ret = 0;
int i;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL);
if (!priv->clks)
return -ENOMEM;
sdev->num_cores = 1;
sdev->pdata->hw_pdata = priv;
priv->dev = sdev->dev;
priv->sdev = sdev;
/* power up device associated power domains */
priv->num_domains = of_count_phandle_with_args(np, "power-domains",
"#power-domain-cells");
if (priv->num_domains < 0) {
dev_err(sdev->dev, "no power-domains property in %pOF\n", np);
return priv->num_domains;
}
priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains,
sizeof(*priv->pd_dev), GFP_KERNEL);
if (!priv->pd_dev)
return -ENOMEM;
priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains,
sizeof(*priv->link), GFP_KERNEL);
if (!priv->link)
return -ENOMEM;
for (i = 0; i < priv->num_domains; i++) {
priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i);
if (IS_ERR(priv->pd_dev[i])) {
ret = PTR_ERR(priv->pd_dev[i]);
goto exit_unroll_pm;
}
priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i],
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
if (!priv->link[i]) {
ret = -ENOMEM;
dev_pm_domain_detach(priv->pd_dev[i], false);
goto exit_unroll_pm;
}
}
ret = imx_scu_get_handle(&priv->sc_ipc);
if (ret) {
dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n",
ret);
goto exit_unroll_pm;
}
priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
PLATFORM_DEVID_NONE,
pdev, sizeof(*pdev));
if (IS_ERR(priv->ipc_dev)) {
ret = PTR_ERR(priv->ipc_dev);
goto exit_unroll_pm;
}
priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
if (!priv->dsp_ipc) {
/* DSP IPC driver not probed yet, try later */
ret = -EPROBE_DEFER;
dev_err(sdev->dev, "Failed to get drvdata\n");
goto exit_pdev_unregister;
}
imx_dsp_set_data(priv->dsp_ipc, priv);
priv->dsp_ipc->ops = &dsp_ops;
/* DSP base */
mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
ret = -EINVAL;
goto exit_pdev_unregister;
}
sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
base, size);
ret = -ENODEV;
goto exit_pdev_unregister;
}
sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
res_node = of_parse_phandle(np, "memory-region", 0);
if (!res_node) {
dev_err(&pdev->dev, "failed to get memory region node\n");
ret = -ENODEV;
goto exit_pdev_unregister;
}
ret = of_address_to_resource(res_node, 0, &res);
of_node_put(res_node);
if (ret) {
dev_err(&pdev->dev, "failed to get reserved region address\n");
goto exit_pdev_unregister;
}
sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
resource_size(&res));
if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
base, size);
ret = -ENOMEM;
goto exit_pdev_unregister;
}
sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = MBOX_OFFSET;
/* init clocks info */
priv->clks->dsp_clks = imx8_dsp_clks;
priv->clks->num_dsp_clks = ARRAY_SIZE(imx8_dsp_clks);
ret = imx8_parse_clocks(sdev, priv->clks);
if (ret < 0)
goto exit_pdev_unregister;
ret = imx8_enable_clocks(sdev, priv->clks);
if (ret < 0)
goto exit_pdev_unregister;
return 0;
exit_pdev_unregister:
platform_device_unregister(priv->ipc_dev);
exit_unroll_pm:
while (--i >= 0) {
device_link_del(priv->link[i]);
dev_pm_domain_detach(priv->pd_dev[i], false);
}
return ret;
}
static int imx8_remove(struct snd_sof_dev *sdev)
{
struct imx8_priv *priv = sdev->pdata->hw_pdata;
int i;
imx8_disable_clocks(sdev, priv->clks);
platform_device_unregister(priv->ipc_dev);
for (i = 0; i < priv->num_domains; i++) {
device_link_del(priv->link[i]);
dev_pm_domain_detach(priv->pd_dev[i], false);
}
return 0;
}
/* on i.MX8 there is 1 to 1 match between type and BAR idx */
static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type)
{
/* Only IRAM and SRAM bars are valid */
switch (type) {
case SOF_FW_BLK_TYPE_IRAM:
case SOF_FW_BLK_TYPE_SRAM:
return type;
default:
return -EINVAL;
}
}
static void imx8_suspend(struct snd_sof_dev *sdev)
{
int i;
struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
for (i = 0; i < DSP_MU_CHAN_NUM; i++)
imx_dsp_free_channel(priv->dsp_ipc, i);
imx8_disable_clocks(sdev, priv->clks);
}
static int imx8_resume(struct snd_sof_dev *sdev)
{
struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
int ret;
int i;
ret = imx8_enable_clocks(sdev, priv->clks);
if (ret < 0)
return ret;
for (i = 0; i < DSP_MU_CHAN_NUM; i++)
imx_dsp_request_channel(priv->dsp_ipc, i);
return 0;
}
static int imx8_dsp_runtime_resume(struct snd_sof_dev *sdev)
{
int ret;
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D0,
};
ret = imx8_resume(sdev);
if (ret < 0)
return ret;
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8_dsp_runtime_suspend(struct snd_sof_dev *sdev)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D3,
};
imx8_suspend(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
{
const struct sof_dsp_power_state target_dsp_state = {
.state = target_state,
};
if (!pm_runtime_suspended(sdev->dev))
imx8_suspend(sdev);
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static int imx8_dsp_resume(struct snd_sof_dev *sdev)
{
int ret;
const struct sof_dsp_power_state target_dsp_state = {
.state = SOF_DSP_PM_D0,
};
ret = imx8_resume(sdev);
if (ret < 0)
return ret;
if (pm_runtime_suspended(sdev->dev)) {
pm_runtime_disable(sdev->dev);
pm_runtime_set_active(sdev->dev);
pm_runtime_mark_last_busy(sdev->dev);
pm_runtime_enable(sdev->dev);
pm_runtime_idle(sdev->dev);
}
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static struct snd_soc_dai_driver imx8_dai[] = {
{
.name = "esai0",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
{
.name = "sai1",
.playback = {
.channels_min = 1,
.channels_max = 32,
},
.capture = {
.channels_min = 1,
.channels_max = 32,
},
},
};
static int imx8_dsp_set_power_state(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
sdev->dsp_power_state = *target_state;
return 0;
}
/* i.MX8 ops */
static struct snd_sof_dsp_ops sof_imx8_ops = {
/* probe and remove */
.probe = imx8_probe,
.remove = imx8_remove,
/* DSP core boot */
.run = imx8_run,
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* ipc */
.send_msg = imx8_send_msg,
.get_mailbox_offset = imx8_get_mailbox_offset,
.get_window_offset = imx8_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
.get_bar_index = imx8_get_bar_index,
/* firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* Debug information */
.dbg_dump = imx8_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
/* DAI drivers */
.drv = imx8_dai,
.num_drv = ARRAY_SIZE(imx8_dai),
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
/* PM */
.runtime_suspend = imx8_dsp_runtime_suspend,
.runtime_resume = imx8_dsp_runtime_resume,
.suspend = imx8_dsp_suspend,
.resume = imx8_dsp_resume,
.set_power_state = imx8_dsp_set_power_state,
};
/* i.MX8X ops */
static struct snd_sof_dsp_ops sof_imx8x_ops = {
/* probe and remove */
.probe = imx8_probe,
.remove = imx8_remove,
/* DSP core boot */
.run = imx8x_run,
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* ipc */
.send_msg = imx8_send_msg,
.get_mailbox_offset = imx8_get_mailbox_offset,
.get_window_offset = imx8_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
.get_bar_index = imx8_get_bar_index,
/* firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* Debug information */
.dbg_dump = imx8_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
/* DAI drivers */
.drv = imx8_dai,
.num_drv = ARRAY_SIZE(imx8_dai),
/* PM */
.runtime_suspend = imx8_dsp_runtime_suspend,
.runtime_resume = imx8_dsp_runtime_resume,
.suspend = imx8_dsp_suspend,
.resume = imx8_dsp_resume,
.set_power_state = imx8_dsp_set_power_state,
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
};
static struct sof_dev_desc sof_of_imx8qxp_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "imx/sof",
},
.default_tplg_path = {
[SOF_IPC] = "imx/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-imx8x.ri",
},
.nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
.ops = &sof_imx8x_ops,
};
static struct sof_dev_desc sof_of_imx8qm_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "imx/sof",
},
.default_tplg_path = {
[SOF_IPC] = "imx/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-imx8.ri",
},
.nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
.ops = &sof_imx8_ops,
};
static const struct of_device_id sof_of_imx8_ids[] = {
{ .compatible = "fsl,imx8qxp-dsp", .data = &sof_of_imx8qxp_desc},
{ .compatible = "fsl,imx8qm-dsp", .data = &sof_of_imx8qm_desc},
{ }
};
MODULE_DEVICE_TABLE(of, sof_of_imx8_ids);
/* DT driver definition */
static struct platform_driver snd_sof_of_imx8_driver = {
.probe = sof_of_probe,
.remove = sof_of_remove,
.driver = {
.name = "sof-audio-of-imx8",
.pm = &sof_of_pm,
.of_match_table = sof_of_imx8_ids,
},
};
module_platform_driver(snd_sof_of_imx8_driver);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/imx/imx8.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <[email protected]>
// Ranjani Sridharan <[email protected]>
// Rander Wang <[email protected]>
// Keyon Jie <[email protected]>
//
/*
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <linux/moduleparam.h>
#include <sound/hda_register.h>
#include <sound/pcm_params.h>
#include <trace/events/sof_intel.h>
#include "../sof-audio.h"
#include "../ops.h"
#include "hda.h"
#define SDnFMT_BASE(x) ((x) << 14)
#define SDnFMT_MULT(x) (((x) - 1) << 11)
#define SDnFMT_DIV(x) (((x) - 1) << 8)
#define SDnFMT_BITS(x) ((x) << 4)
#define SDnFMT_CHAN(x) ((x) << 0)
static bool hda_always_enable_dmi_l1;
module_param_named(always_enable_dmi_l1, hda_always_enable_dmi_l1, bool, 0444);
MODULE_PARM_DESC(always_enable_dmi_l1, "SOF HDA always enable DMI l1");
static bool hda_disable_rewinds;
module_param_named(disable_rewinds, hda_disable_rewinds, bool, 0444);
MODULE_PARM_DESC(disable_rewinds, "SOF HDA disable rewinds");
u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate)
{
switch (rate) {
case 8000:
return SDnFMT_DIV(6);
case 9600:
return SDnFMT_DIV(5);
case 11025:
return SDnFMT_BASE(1) | SDnFMT_DIV(4);
case 16000:
return SDnFMT_DIV(3);
case 22050:
return SDnFMT_BASE(1) | SDnFMT_DIV(2);
case 32000:
return SDnFMT_DIV(3) | SDnFMT_MULT(2);
case 44100:
return SDnFMT_BASE(1);
case 48000:
return 0;
case 88200:
return SDnFMT_BASE(1) | SDnFMT_MULT(2);
case 96000:
return SDnFMT_MULT(2);
case 176400:
return SDnFMT_BASE(1) | SDnFMT_MULT(4);
case 192000:
return SDnFMT_MULT(4);
default:
dev_warn(sdev->dev, "can't find div rate %d using 48kHz\n",
rate);
return 0; /* use 48KHz if not found */
}
};
u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits)
{
switch (sample_bits) {
case 8:
return SDnFMT_BITS(0);
case 16:
return SDnFMT_BITS(1);
case 20:
return SDnFMT_BITS(2);
case 24:
return SDnFMT_BITS(3);
case 32:
return SDnFMT_BITS(4);
default:
dev_warn(sdev->dev, "can't find %d bits using 16bit\n",
sample_bits);
return SDnFMT_BITS(1); /* use 16bits format if not found */
}
};
int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_sof_platform_stream_params *platform_params)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct snd_dma_buffer *dmab;
int ret;
hstream->substream = substream;
dmab = substream->runtime->dma_buffer_p;
/*
* Use the codec required format val (which is link_bps adjusted) when
* the DSP is not in use
*/
if (!sdev->dspless_mode_selected) {
u32 rate = hda_dsp_get_mult_div(sdev, params_rate(params));
u32 bits = hda_dsp_get_bits(sdev, params_width(params));
hstream->format_val = rate | bits | (params_channels(params) - 1);
}
hstream->bufsize = params_buffer_bytes(params);
hstream->period_bytes = params_period_bytes(params);
hstream->no_period_wakeup =
(params->info & SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) &&
(params->flags & SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP);
ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, params);
if (ret < 0) {
dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret);
return ret;
}
/* enable SPIB when rewinds are disabled */
if (hda_disable_rewinds)
hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, 0);
else
hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
if (hda)
platform_params->no_ipc_position = hda->no_ipc_position;
platform_params->stream_tag = hstream->stream_tag;
return 0;
}
/* update SPIB register with appl position */
int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
ssize_t appl_pos, buf_size;
u32 spib;
appl_pos = frames_to_bytes(runtime, runtime->control->appl_ptr);
buf_size = frames_to_bytes(runtime, runtime->buffer_size);
spib = appl_pos % buf_size;
/* Allowable value for SPIB is 1 byte to max buffer size */
if (!spib)
spib = buf_size;
sof_io_write(sdev, hstream->spib_addr, spib);
return 0;
}
int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream, int cmd)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
}
snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *scomp = sdev->component;
struct hdac_stream *hstream = substream->runtime->private_data;
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct snd_sof_pcm *spcm;
snd_pcm_uframes_t pos;
spcm = snd_sof_find_spcm_dai(scomp, rtd);
if (!spcm) {
dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
rtd->dai_link->id);
return 0;
}
if (hda && !hda->no_ipc_position) {
/* read position from IPC position */
pos = spcm->stream[substream->stream].posn.host_posn;
goto found;
}
pos = hda_dsp_stream_get_position(hstream, substream->stream, true);
found:
pos = bytes_to_frames(substream->runtime, pos);
trace_sof_intel_hda_dsp_pcm(sdev, hstream, substream, pos);
return pos;
}
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_component *scomp = sdev->component;
struct hdac_ext_stream *dsp_stream;
struct snd_sof_pcm *spcm;
int direction = substream->stream;
u32 flags = 0;
spcm = snd_sof_find_spcm_dai(scomp, rtd);
if (!spcm) {
dev_err(sdev->dev, "error: can't find PCM with DAI ID %d\n", rtd->dai_link->id);
return -EINVAL;
}
/*
* if we want the .ack to work, we need to prevent the control from being mapped.
* The status can still be mapped.
*/
if (hda_disable_rewinds)
runtime->hw.info |= SNDRV_PCM_INFO_NO_REWINDS | SNDRV_PCM_INFO_SYNC_APPLPTR;
/*
* All playback streams are DMI L1 capable, capture streams need
* pause push/release to be disabled
*/
if (hda_always_enable_dmi_l1 && direction == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw.info &= ~SNDRV_PCM_INFO_PAUSE;
if (hda_always_enable_dmi_l1 ||
direction == SNDRV_PCM_STREAM_PLAYBACK ||
spcm->stream[substream->stream].d0i3_compatible)
flags |= SOF_HDA_STREAM_DMI_L1_COMPATIBLE;
dsp_stream = hda_dsp_stream_get(sdev, direction, flags);
if (!dsp_stream) {
dev_err(sdev->dev, "error: no stream available\n");
return -ENODEV;
}
/* minimum as per HDA spec */
snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
/* avoid circular buffer wrap in middle of period */
snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
/* Only S16 and S32 supported by HDA hardware when used without DSP */
if (sdev->dspless_mode_selected)
snd_pcm_hw_constraint_mask64(substream->runtime, SNDRV_PCM_HW_PARAM_FORMAT,
SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S32);
/* binding pcm substream to hda stream */
substream->runtime->private_data = &dsp_stream->hstream;
return 0;
}
int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
struct hdac_stream *hstream = substream->runtime->private_data;
int direction = substream->stream;
int ret;
ret = hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
if (ret) {
dev_dbg(sdev->dev, "stream %s not opened!\n", substream->name);
return -ENODEV;
}
/* unbinding pcm substream to hda stream */
substream->runtime->private_data = NULL;
return 0;
}
| linux-master | sound/soc/sof/intel/hda-pcm.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <[email protected]>
// Ranjani Sridharan <[email protected]>
// Rander Wang <[email protected]>
// Keyon Jie <[email protected]>
//
/*
* Hardware interface for audio DSP on Cannonlake.
*/
#include <sound/sof/ext_manifest4.h>
#include <sound/sof/ipc4/header.h>
#include <trace/events/sof_intel.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"
static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};
static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
irqreturn_t cnl_ipc4_irq_thread(int irq, void *context)
{
struct sof_ipc4_msg notification_data = {{ 0 }};
struct snd_sof_dev *sdev = context;
bool ack_received = false;
bool ipc_irq = false;
u32 hipcida, hipctdr;
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
/* DSP received the message */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCCTL,
CNL_DSP_REG_HIPCCTL_DONE, 0);
cnl_ipc_dsp_done(sdev);
ipc_irq = true;
ack_received = true;
}
if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
/* Message from DSP (reply or notification) */
u32 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCTDD);
u32 primary = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
u32 extension = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
if (primary & SOF_IPC4_MSG_DIR_MASK) {
/* Reply received */
if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
data->primary = primary;
data->extension = extension;
spin_lock_irq(&sdev->ipc_lock);
snd_sof_ipc_get_reply(sdev);
cnl_ipc_host_done(sdev);
snd_sof_ipc_reply(sdev, data->primary);
spin_unlock_irq(&sdev->ipc_lock);
} else {
dev_dbg_ratelimited(sdev->dev,
"IPC reply before FW_READY: %#x|%#x\n",
primary, extension);
}
} else {
/* Notification received */
notification_data.primary = primary;
notification_data.extension = extension;
sdev->ipc->msg.rx_data = ¬ification_data;
snd_sof_ipc_msgs_rx(sdev);
sdev->ipc->msg.rx_data = NULL;
/* Let DSP know that we have finished processing the message */
cnl_ipc_host_done(sdev);
}
ipc_irq = true;
}
if (!ipc_irq)
/* This interrupt is not shared so no need to return IRQ_NONE. */
dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
if (ack_received) {
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
if (hdev->delayed_ipc_tx_msg)
cnl_ipc4_send_msg(sdev, hdev->delayed_ipc_tx_msg);
}
return IRQ_HANDLED;
}
irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
u32 hipci;
u32 hipcida;
u32 hipctdr;
u32 hipctdd;
u32 msg;
u32 msg_ext;
bool ipc_irq = false;
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
/* reply message from DSP */
if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
trace_sof_intel_ipc_firmware_response(sdev, msg, msg_ext);
/* mask Done interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCCTL,
CNL_DSP_REG_HIPCCTL_DONE, 0);
if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
spin_lock_irq(&sdev->ipc_lock);
/* handle immediate reply from DSP core */
hda_dsp_ipc_get_reply(sdev);
snd_sof_ipc_reply(sdev, msg);
cnl_ipc_dsp_done(sdev);
spin_unlock_irq(&sdev->ipc_lock);
} else {
dev_dbg_ratelimited(sdev->dev, "IPC reply before FW_READY: %#x\n",
msg);
}
ipc_irq = true;
}
/* new message from DSP */
if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
trace_sof_intel_ipc_firmware_initiated(sdev, msg, msg_ext);
/* handle messages from DSP */
if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
bool non_recoverable = true;
/*
* This is a PANIC message!
*
* If it is arriving during firmware boot and it is not
* the last boot attempt then change the non_recoverable
* to false as the DSP might be able to boot in the next
* iteration(s)
*/
if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS &&
hda->boot_iteration < HDA_FW_BOOT_ATTEMPTS)
non_recoverable = false;
snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext),
non_recoverable);
} else {
snd_sof_ipc_msgs_rx(sdev);
}
cnl_ipc_host_done(sdev);
ipc_irq = true;
}
if (!ipc_irq) {
/*
* This interrupt is not shared so no need to return IRQ_NONE.
*/
dev_dbg_ratelimited(sdev->dev,
"nothing to do in IPC IRQ thread\n");
}
return IRQ_HANDLED;
}
static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
{
/*
* clear busy interrupt to tell dsp controller this
* interrupt has been accepted, not trigger it again
*/
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCTDR,
CNL_DSP_REG_HIPCTDR_BUSY,
CNL_DSP_REG_HIPCTDR_BUSY);
/*
* set done bit to ack dsp the msg has been
* processed and send reply msg to dsp
*/
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCTDA,
CNL_DSP_REG_HIPCTDA_DONE,
CNL_DSP_REG_HIPCTDA_DONE);
}
static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
{
/*
* set DONE bit - tell DSP we have received the reply msg
* from DSP, and processed it, don't send more reply to host
*/
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCIDA,
CNL_DSP_REG_HIPCIDA_DONE,
CNL_DSP_REG_HIPCIDA_DONE);
/* unmask Done interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
CNL_DSP_REG_HIPCCTL,
CNL_DSP_REG_HIPCCTL_DONE,
CNL_DSP_REG_HIPCCTL_DONE);
}
static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
u32 *dr, u32 *dd)
{
struct sof_ipc_pm_gate *pm_gate = msg->msg_data;
if (pm_gate->hdr.cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
/* send the compact message via the primary register */
*dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
/* send payload via the extended data register */
*dd = pm_gate->flags;
return true;
}
return false;
}
int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
struct sof_ipc4_msg *msg_data = msg->msg_data;
if (hda_ipc4_tx_is_busy(sdev)) {
hdev->delayed_ipc_tx_msg = msg;
return 0;
}
hdev->delayed_ipc_tx_msg = NULL;
/* send the message via mailbox */
if (msg_data->data_size)
sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
msg_data->data_size);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, msg_data->extension);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
msg_data->primary | CNL_DSP_REG_HIPCIDR_BUSY);
hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
return 0;
}
int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
struct sof_ipc_cmd_hdr *hdr;
u32 dr = 0;
u32 dd = 0;
/*
* Currently the only compact IPC supported is the PM_GATE
* IPC which is used for transitioning the DSP between the
* D0I0 and D0I3 states. And these are sent only during the
* set_power_state() op. Therefore, there will never be a case
* that a compact IPC results in the DSP exiting D0I3 without
* the host and FW being in sync.
*/
if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
/* send the message via IPC registers */
snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
dd);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
CNL_DSP_REG_HIPCIDR_BUSY | dr);
return 0;
}
/* send the message via mailbox */
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
msg->msg_size);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
CNL_DSP_REG_HIPCIDR_BUSY);
hdr = msg->msg_data;
/*
* Use mod_delayed_work() to schedule the delayed work
* to avoid scheduling multiple workqueue items when
* IPCs are sent at a high-rate. mod_delayed_work()
* modifies the timer if the work is pending.
* Also, a new delayed work should not be queued after the
* CTX_SAVE IPC, which is sent before the DSP enters D3.
*/
if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
mod_delayed_work(system_wq, &hdev->d0i3_work,
msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
return 0;
}
void cnl_ipc_dump(struct snd_sof_dev *sdev)
{
u32 hipcctl;
u32 hipcida;
u32 hipctdr;
hda_ipc_irq_dump(sdev);
/* read IPC status */
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev,
"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
hipcida, hipctdr, hipcctl);
}
void cnl_ipc4_dump(struct snd_sof_dev *sdev)
{
u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
hda_ipc_irq_dump(sdev);
hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD);
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDA);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev,
"Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
}
/* cannonlake ops */
struct snd_sof_dsp_ops sof_cnl_ops;
EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_cnl_ops_init(struct snd_sof_dev *sdev)
{
/* common defaults */
memcpy(&sof_cnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
/* probe/remove/shutdown */
sof_cnl_ops.shutdown = hda_dsp_shutdown;
/* ipc */
if (sdev->pdata->ipc_type == SOF_IPC) {
/* doorbell */
sof_cnl_ops.irq_thread = cnl_ipc_irq_thread;
/* ipc */
sof_cnl_ops.send_msg = cnl_ipc_send_msg;
/* debug */
sof_cnl_ops.ipc_dump = cnl_ipc_dump;
sof_cnl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
}
if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
struct sof_ipc4_fw_data *ipc4_data;
sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
if (!sdev->private)
return -ENOMEM;
ipc4_data = sdev->private;
ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_8;
/* External library loading support */
ipc4_data->load_library = hda_dsp_ipc4_load_library;
/* doorbell */
sof_cnl_ops.irq_thread = cnl_ipc4_irq_thread;
/* ipc */
sof_cnl_ops.send_msg = cnl_ipc4_send_msg;
/* debug */
sof_cnl_ops.ipc_dump = cnl_ipc4_dump;
sof_cnl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
}
/* set DAI driver ops */
hda_set_dai_drv_ops(sdev, &sof_cnl_ops);
/* debug */
sof_cnl_ops.debug_map = cnl_dsp_debugfs;
sof_cnl_ops.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs);
/* pre/post fw run */
sof_cnl_ops.post_fw_run = hda_dsp_post_fw_run;
/* firmware run */
sof_cnl_ops.run = hda_dsp_cl_boot_firmware;
/* dsp core get/put */
sof_cnl_ops.core_get = hda_dsp_core_get;
return 0;
};
EXPORT_SYMBOL_NS(sof_cnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc cnl_chip_info = {
/* Cannonlake */
.cores_num = 4,
.init_core_mask = 1,
.host_managed_cores_mask = GENMASK(3, 0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
.rom_init_timeout = 300,
.ssp_count = CNL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE,
.d0i3_offset = SOF_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_common,
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_8,
};
EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
/*
* JasperLake is technically derived from IceLake, and should be in
* described in icl.c. However since JasperLake was designed with
* two cores, it cannot support the IceLake-specific power-up sequences
* which rely on core3. To simplify, JasperLake uses the CannonLake ops and
* is described in cnl.c
*/
const struct sof_intel_dsp_desc jsl_chip_info = {
/* Jasperlake */
.cores_num = 2,
.init_core_mask = 1,
.host_managed_cores_mask = GENMASK(1, 0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
.rom_init_timeout = 300,
.ssp_count = ICL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE,
.d0i3_offset = SOF_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_common,
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_0,
};
EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
| linux-master | sound/soc/sof/intel/cnl.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2022 Intel Corporation. All rights reserved.
//
/*
* Hardware interface for audio DSP on Skylake and Kabylake.
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <sound/hdaudio_ext.h>
#include <sound/pcm_params.h>
#include <sound/sof.h>
#include <sound/sof/ext_manifest4.h>
#include "../sof-priv.h"
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "../sof-audio.h"
#define SRAM_MEMORY_WINDOW_BASE 0x8000
static const __maybe_unused struct snd_sof_debugfs_map skl_dsp_debugfs[] = {
{"hda", HDA_DSP_HDA_BAR, 0, 0x4000},
{"pp", HDA_DSP_PP_BAR, 0, 0x1000},
{"dsp", HDA_DSP_BAR, 0, 0x10000},
};
static int skl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return SRAM_MEMORY_WINDOW_BASE + (0x2000 * id);
}
static int skl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return SRAM_MEMORY_WINDOW_BASE + 0x1000;
}
/* skylake ops */
struct snd_sof_dsp_ops sof_skl_ops;
EXPORT_SYMBOL_NS(sof_skl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_skl_ops_init(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data;
/* common defaults */
memcpy(&sof_skl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
/* probe/remove/shutdown */
sof_skl_ops.shutdown = hda_dsp_shutdown;
sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
if (!sdev->private)
return -ENOMEM;
ipc4_data = sdev->private;
ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5;
ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_5;
sof_skl_ops.get_window_offset = skl_dsp_ipc_get_window_offset;
sof_skl_ops.get_mailbox_offset = skl_dsp_ipc_get_mailbox_offset;
/* doorbell */
sof_skl_ops.irq_thread = hda_dsp_ipc4_irq_thread;
/* ipc */
sof_skl_ops.send_msg = hda_dsp_ipc4_send_msg;
/* set DAI driver ops */
hda_set_dai_drv_ops(sdev, &sof_skl_ops);
/* debug */
sof_skl_ops.debug_map = skl_dsp_debugfs;
sof_skl_ops.debug_map_count = ARRAY_SIZE(skl_dsp_debugfs);
sof_skl_ops.ipc_dump = hda_ipc4_dump;
/* firmware run */
sof_skl_ops.run = hda_dsp_cl_boot_firmware_skl;
/* pre/post fw run */
sof_skl_ops.post_fw_run = hda_dsp_post_fw_run;
return 0;
};
EXPORT_SYMBOL_NS(sof_skl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc skl_chip_info = {
.cores_num = 2,
.init_core_mask = 1,
.host_managed_cores_mask = GENMASK(1, 0),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS_SKL,
.rom_init_timeout = 300,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_1_5,
};
EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
| linux-master | sound/soc/sof/intel/skl.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
/*
* Hardware interface for audio DSP on Atom devices
*/
#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/intel-dsp-config.h>
#include "../ops.h"
#include "shim.h"
#include "atom.h"
#include "../sof-acpi-dev.h"
#include "../sof-audio.h"
#include "../../intel/common/soc-intel-quirks.h"
static void atom_host_done(struct snd_sof_dev *sdev);
static void atom_dsp_done(struct snd_sof_dev *sdev);
/*
* Debug
*/
static void atom_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read regsisters */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
xoops->arch_hdr.totalsize);
return;
}
offset += xoops->arch_hdr.totalsize;
sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
/* then get the stack */
offset += sizeof(*panic_info);
sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
}
void atom_dump(struct snd_sof_dev *sdev, u32 flags)
{
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[STACK_DUMP_SIZE];
u64 status, panic, imrd, imrx;
/* now try generic SOF status messages */
status = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
panic = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
atom_get_registers(sdev, &xoops, &panic_info, stack,
STACK_DUMP_SIZE);
sof_print_oops_and_stack(sdev, KERN_ERR, status, panic, &xoops,
&panic_info, stack, STACK_DUMP_SIZE);
/* provide some context for firmware debug */
imrx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRX);
imrd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IMRD);
dev_err(sdev->dev,
"error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n",
(panic & SHIM_IPCX_BUSY) ? "yes" : "no",
(panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
dev_err(sdev->dev,
"error: mask host: pending %s complete %s raw 0x%llx\n",
(imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
(imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
dev_err(sdev->dev,
"error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n",
(status & SHIM_IPCD_BUSY) ? "yes" : "no",
(status & SHIM_IPCD_DONE) ? "yes" : "no", status);
dev_err(sdev->dev,
"error: mask DSP: pending %s complete %s raw 0x%llx\n",
(imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
(imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
}
EXPORT_SYMBOL_NS(atom_dump, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
/*
* IPC Doorbell IRQ handler and thread.
*/
irqreturn_t atom_irq_handler(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
u64 ipcx, ipcd;
int ret = IRQ_NONE;
ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
if (ipcx & SHIM_BYT_IPCX_DONE) {
/* reply message from DSP, Mask Done interrupt first */
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR,
SHIM_IMRX,
SHIM_IMRX_DONE,
SHIM_IMRX_DONE);
ret = IRQ_WAKE_THREAD;
}
if (ipcd & SHIM_BYT_IPCD_BUSY) {
/* new message from DSP, Mask Busy interrupt first */
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR,
SHIM_IMRX,
SHIM_IMRX_BUSY,
SHIM_IMRX_BUSY);
ret = IRQ_WAKE_THREAD;
}
return ret;
}
EXPORT_SYMBOL_NS(atom_irq_handler, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
irqreturn_t atom_irq_thread(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
u64 ipcx, ipcd;
ipcx = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCX);
ipcd = snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_IPCD);
/* reply message from DSP */
if (ipcx & SHIM_BYT_IPCX_DONE) {
spin_lock_irq(&sdev->ipc_lock);
/*
* handle immediate reply from DSP core. If the msg is
* found, set done bit in cmd_done which is called at the
* end of message processing function, else set it here
* because the done bit can't be set in cmd_done function
* which is triggered by msg
*/
snd_sof_ipc_process_reply(sdev, ipcx);
atom_dsp_done(sdev);
spin_unlock_irq(&sdev->ipc_lock);
}
/* new message from DSP */
if (ipcd & SHIM_BYT_IPCD_BUSY) {
/* Handle messages from DSP Core */
if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
snd_sof_dsp_panic(sdev, PANIC_OFFSET(ipcd) + MBOX_OFFSET,
true);
} else {
snd_sof_ipc_msgs_rx(sdev);
}
atom_host_done(sdev);
}
return IRQ_HANDLED;
}
EXPORT_SYMBOL_NS(atom_irq_thread, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
/* unmask and prepare to receive Done interrupt */
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX,
SHIM_IMRX_DONE, 0);
/* send the message */
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
msg->msg_size);
snd_sof_dsp_write64(sdev, DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
return 0;
}
EXPORT_SYMBOL_NS(atom_send_msg, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
int atom_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MBOX_OFFSET;
}
EXPORT_SYMBOL_NS(atom_get_mailbox_offset, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MBOX_OFFSET;
}
EXPORT_SYMBOL_NS(atom_get_window_offset, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
static void atom_host_done(struct snd_sof_dev *sdev)
{
/* clear BUSY bit and set DONE bit - accept new messages */
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCD,
SHIM_BYT_IPCD_BUSY |
SHIM_BYT_IPCD_DONE,
SHIM_BYT_IPCD_DONE);
/* unmask and prepare to receive next new message */
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IMRX,
SHIM_IMRX_BUSY, 0);
}
static void atom_dsp_done(struct snd_sof_dev *sdev)
{
/* clear DONE bit - tell DSP we have completed */
snd_sof_dsp_update_bits64_unlocked(sdev, DSP_BAR, SHIM_IPCX,
SHIM_BYT_IPCX_DONE, 0);
}
/*
* DSP control.
*/
int atom_run(struct snd_sof_dev *sdev)
{
int tries = 10;
/* release stall and wait to unstall */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
SHIM_BYT_CSR_STALL, 0x0);
while (tries--) {
if (!(snd_sof_dsp_read64(sdev, DSP_BAR, SHIM_CSR) &
SHIM_BYT_CSR_PWAITMODE))
break;
msleep(100);
}
if (tries < 0)
return -ENODEV;
/* return init core mask */
return 1;
}
EXPORT_SYMBOL_NS(atom_run, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
int atom_reset(struct snd_sof_dev *sdev)
{
/* put DSP into reset, set reset vector and stall */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
SHIM_BYT_CSR_STALL,
SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
SHIM_BYT_CSR_STALL);
usleep_range(10, 15);
/* take DSP out of reset and keep stalled for FW loading */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
SHIM_BYT_CSR_RST, 0);
return 0;
}
EXPORT_SYMBOL_NS(atom_reset, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
const char *sof_tplg_filename,
const char *ssp_str)
{
const char *tplg_filename = NULL;
const char *split_ext;
char *filename, *tmp;
filename = kstrdup(sof_tplg_filename, GFP_KERNEL);
if (!filename)
return NULL;
/* this assumes a .tplg extension */
tmp = filename;
split_ext = strsep(&tmp, ".");
if (split_ext)
tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
"%s-%s.tplg",
split_ext, ssp_str);
kfree(filename);
return tplg_filename;
}
struct snd_soc_acpi_mach *atom_machine_select(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *sof_pdata = sdev->pdata;
const struct sof_dev_desc *desc = sof_pdata->desc;
struct snd_soc_acpi_mach *mach;
struct platform_device *pdev;
const char *tplg_filename;
mach = snd_soc_acpi_find_machine(desc->machines);
if (!mach) {
dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
return NULL;
}
pdev = to_platform_device(sdev->dev);
if (soc_intel_is_byt_cr(pdev)) {
dev_dbg(sdev->dev,
"BYT-CR detected, SSP0 used instead of SSP2\n");
tplg_filename = fixup_tplg_name(sdev,
mach->sof_tplg_filename,
"ssp0");
} else {
tplg_filename = mach->sof_tplg_filename;
}
if (!tplg_filename) {
dev_dbg(sdev->dev,
"error: no topology filename\n");
return NULL;
}
sof_pdata->tplg_filename = tplg_filename;
mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
return mach;
}
EXPORT_SYMBOL_NS(atom_machine_select, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
/* Atom DAIs */
struct snd_soc_dai_driver atom_dai[] = {
{
.name = "ssp0-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
{
.name = "ssp1-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
{
.name = "ssp2-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
}
},
{
.name = "ssp3-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
{
.name = "ssp4-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
{
.name = "ssp5-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
};
EXPORT_SYMBOL_NS(atom_dai, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
void atom_set_mach_params(struct snd_soc_acpi_mach *mach,
struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_dev_desc *desc = pdata->desc;
struct snd_soc_acpi_mach_params *mach_params;
mach_params = &mach->mach_params;
mach_params->platform = dev_name(sdev->dev);
mach_params->num_dai_drivers = desc->ops->num_drv;
mach_params->dai_drivers = desc->ops->drv;
}
EXPORT_SYMBOL_NS(atom_set_mach_params, SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/intel/atom.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/module.h>
#include <linux/pci.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "../ops.h"
#include "../sof-pci-dev.h"
/* platform specific devices */
#include "hda.h"
static const struct sof_dev_desc tgl_desc = {
.machines = snd_soc_acpi_intel_tgl_machines,
.alt_machines = snd_soc_acpi_intel_tgl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &tgl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/tgl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/tgl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-tgl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc tglh_desc = {
.machines = snd_soc_acpi_intel_tgl_machines,
.alt_machines = snd_soc_acpi_intel_tgl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &tglh_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/tgl-h",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/tgl-h",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-tgl-h.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc ehl_desc = {
.machines = snd_soc_acpi_intel_ehl_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &ehl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/ehl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/ehl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-ehl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-ehl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc adls_desc = {
.machines = snd_soc_acpi_intel_adl_machines,
.alt_machines = snd_soc_acpi_intel_adl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &adls_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/adl-s",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/adl-s",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-adl-s.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-adl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc adl_desc = {
.machines = snd_soc_acpi_intel_adl_machines,
.alt_machines = snd_soc_acpi_intel_adl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &tgl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/adl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/adl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-adl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-adl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc adl_n_desc = {
.machines = snd_soc_acpi_intel_adl_machines,
.alt_machines = snd_soc_acpi_intel_adl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &tgl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/adl-n",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/adl-n",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-adl-n.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-adl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc rpls_desc = {
.machines = snd_soc_acpi_intel_rpl_machines,
.alt_machines = snd_soc_acpi_intel_rpl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &adls_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/rpl-s",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/rpl-s",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-rpl-s.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-rpl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc rpl_desc = {
.machines = snd_soc_acpi_intel_rpl_machines,
.alt_machines = snd_soc_acpi_intel_rpl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &tgl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/rpl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/rpl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-rpl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-rpl-nocodec.tplg",
.ops = &sof_tgl_ops,
.ops_init = sof_tgl_ops_init,
.ops_free = hda_ops_free,
};
/* PCI IDs */
static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, &tgl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_TGL_H, &tglh_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_EHL_0, &ehl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_EHL_3, &ehl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_S, &adls_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_S, &rpls_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_P, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, &rpl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, &rpl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_M, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_M, &rpl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, &rpl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_N, &adl_n_desc) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sof_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_sof_pci_intel_tgl_driver = {
.name = "sof-audio-pci-intel-tgl",
.id_table = sof_pci_ids,
.probe = hda_pci_intel_probe,
.remove = sof_pci_remove,
.shutdown = sof_pci_shutdown,
.driver = {
.pm = &sof_pci_pm,
},
};
module_pci_driver(snd_sof_pci_intel_tgl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
| linux-master | sound/soc/sof/intel/pci-tgl.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
// Authors: Ranjani Sridharan <[email protected]>
//
/*
* Hardware interface for audio DSP on Meteorlake.
*/
#include <linux/firmware.h>
#include <sound/sof/ipc4/header.h>
#include <trace/events/sof_intel.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"
#include "mtl.h"
static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = {
{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};
static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
{
/*
* clear busy interrupt to tell dsp controller this interrupt has been accepted,
* not trigger it again
*/
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,
MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY);
/*
* clear busy bit to ack dsp the msg has been processed and send reply msg to dsp
*/
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,
MTL_DSP_REG_HFIPCXTDA_BUSY, 0);
}
static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
{
/*
* set DONE bit - tell DSP we have received the reply msg from DSP, and processed it,
* don't send more reply to host
*/
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,
MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE);
/* unmask Done interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE);
}
/* Check if an IPC IRQ occurred */
bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
{
u32 irq_status;
u32 hfintipptr;
if (sdev->dspless_mode_selected)
return false;
/* read Interrupt IP Pointer */
hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC))
return true;
return false;
}
/* Check if an SDW IRQ occurred */
static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
{
u32 irq_status;
u32 hfintipptr;
/* read Interrupt IP Pointer */
hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW))
return true;
return false;
}
int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
struct sof_ipc4_msg *msg_data = msg->msg_data;
if (hda_ipc4_tx_is_busy(sdev)) {
hdev->delayed_ipc_tx_msg = msg;
return 0;
}
hdev->delayed_ipc_tx_msg = NULL;
/* send the message via mailbox */
if (msg_data->data_size)
sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
msg_data->data_size);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,
msg_data->extension);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,
msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY);
hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
return 0;
}
void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
if (sdev->dspless_mode_selected)
return;
/* enable IPC DONE and BUSY interrupts */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE,
MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE);
}
void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
if (sdev->dspless_mode_selected)
return;
/* disable IPC DONE and BUSY interrupts */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);
}
static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
{
u32 hipcie;
u32 mask;
u32 val;
int ret;
if (sdev->dspless_mode_selected)
return;
/* Enable/Disable SoundWire interrupt */
mask = MTL_DSP_REG_HfSNDWIE_IE_MASK;
if (enable)
val = mask;
else
val = 0;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val);
/* check if operation was successful */
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
(hipcie & mask) == val,
HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0)
dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n",
enable ? "enable" : "disable");
}
int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
{
u32 hfintipptr;
u32 irqinten;
u32 hipcie;
u32 mask;
u32 val;
int ret;
if (sdev->dspless_mode_selected)
return 0;
/* read Interrupt IP Pointer */
hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
/* Enable/Disable Host IPC and SOUNDWIRE */
mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
if (enable)
val = mask;
else
val = 0;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val);
/* check if operation was successful */
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
(irqinten & mask) == val,
HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n",
enable ? "enable" : "disable");
return ret;
}
/* Enable/Disable Host IPC interrupt*/
mask = MTL_DSP_REG_HfHIPCIE_IE_MASK;
if (enable)
val = mask;
else
val = 0;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val);
/* check if operation was successful */
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
(hipcie & mask) == val,
HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n",
enable ? "enable" : "disable");
return ret;
}
return ret;
}
/* pre fw run operations */
int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
u32 dsphfpwrsts;
u32 dsphfdsscs;
u32 cpa;
u32 pgs;
int ret;
/* Set the DSP subsystem power on */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK);
/* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
usleep_range(1000, 1010);
/* poll with timeout to check if operation successful */
cpa = MTL_HFDSSCS_CPA_MASK;
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
(dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev, "failed to enable DSP subsystem\n");
return ret;
}
/* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
usleep_range(1000, 1010);
/* poll with timeout to check if operation successful */
pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
(dsphfpwrsts & pgs) == pgs,
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0)
dev_err(sdev->dev, "failed to power up gated DSP domain\n");
/* if SoundWire is used, make sure it is not power-gated */
if (hdev->info.handle && hdev->info.link_mask > 0)
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));
return ret;
}
int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
{
int ret;
if (sdev->first_boot) {
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
ret = hda_sdw_startup(sdev);
if (ret < 0) {
dev_err(sdev->dev, "could not startup SoundWire links\n");
return ret;
}
/* Check if IMR boot is usable */
if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
hdev->imrboot_supported = true;
}
hda_sdw_int_enable(sdev, true);
return 0;
}
void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
u32 romdbgsts;
u32 romdbgerr;
u32 fwsts;
u32 fwlec;
fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY);
romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR);
dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec);
dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts,
romdbgerr);
romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3);
dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n",
romdbgsts & BIT(24) ? "" : " not");
}
static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
{
int val;
val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);
if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK)
return true;
return false;
}
static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
{
unsigned int cpa;
u32 dspcxctl;
int ret;
/* Only the primary core can be powered up by the host */
if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))
return 0;
/* Program the owner of the IP & shim registers (10: Host CPU) */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
MTL_DSP2CXCTL_PRIMARY_CORE_OSEL,
0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT);
/* enable SPA bit */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK,
MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK);
/* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
usleep_range(1000, 1010);
/* poll with timeout to check if operation successful */
cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK;
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
(dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",
__func__);
return ret;
}
/* set primary core mask and refcount to 1 */
sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE);
sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1;
return 0;
}
static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
{
u32 dspcxctl;
int ret;
/* Only the primary core can be powered down by the host */
if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))
return 0;
/* disable SPA bit */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0);
/* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
usleep_range(1000, 1010);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
!(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
if (ret < 0) {
dev_err(sdev->dev, "failed to power down primary core\n");
return ret;
}
sdev->enabled_cores_mask = 0;
sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0;
return 0;
}
int mtl_power_down_dsp(struct snd_sof_dev *sdev)
{
u32 dsphfdsscs, cpa;
int ret;
/* first power down core */
ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
if (ret) {
dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
return ret;
}
/* Set the DSP subsystem power down */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
MTL_HFDSSCS_SPA_MASK, 0);
/* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
usleep_range(1000, 1010);
/* poll with timeout to check if operation successful */
cpa = MTL_HFDSSCS_CPA_MASK;
dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
(dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
}
int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
unsigned int status;
u32 ipc_hdr;
int ret;
/* step 1: purge FW request */
ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
if (!imr_boot)
ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
/* step 2: power up primary core */
ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
if (ret < 0) {
if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev, "dsp core 0/1 power up failed\n");
goto err;
}
dev_dbg(sdev->dev, "Primary core power up successful\n");
/* step 3: wait for IPC DONE bit from ROM */
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status,
((status & chip->ipc_ack_mask) == chip->ipc_ack_mask),
HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_INIT_TIMEOUT_US);
if (ret < 0) {
if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev, "timeout waiting for purge IPC done\n");
goto err;
}
/* set DONE bit to clear the reply IPC message */
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask,
chip->ipc_ack_mask);
/* step 4: enable interrupts */
ret = mtl_enable_interrupts(sdev, true);
if (ret < 0) {
if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__);
goto err;
}
mtl_enable_ipc_interrupts(sdev);
/*
* ACE workaround: don't wait for ROM INIT.
* The platform cannot catch ROM_INIT_DONE because of a very short
* timing window. Follow the recommendations and skip this part.
*/
return 0;
err:
snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0);
mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
return ret;
}
irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
{
struct sof_ipc4_msg notification_data = {{ 0 }};
struct snd_sof_dev *sdev = context;
bool ack_received = false;
bool ipc_irq = false;
u32 hipcida;
u32 hipctdr;
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
/* reply message from DSP */
if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) {
/* DSP received the message */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
MTL_DSP_REG_HFIPCXCTL_DONE, 0);
mtl_ipc_dsp_done(sdev);
ipc_irq = true;
ack_received = true;
}
if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) {
/* Message from DSP (reply or notification) */
u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK;
/*
* ACE fw sends a new fw ipc message to host to
* notify the status of the last host ipc message
*/
if (primary & SOF_IPC4_MSG_DIR_MASK) {
/* Reply received */
if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
data->primary = primary;
data->extension = extension;
spin_lock_irq(&sdev->ipc_lock);
snd_sof_ipc_get_reply(sdev);
mtl_ipc_host_done(sdev);
snd_sof_ipc_reply(sdev, data->primary);
spin_unlock_irq(&sdev->ipc_lock);
} else {
dev_dbg_ratelimited(sdev->dev,
"IPC reply before FW_READY: %#x|%#x\n",
primary, extension);
}
} else {
/* Notification received */
notification_data.primary = primary;
notification_data.extension = extension;
sdev->ipc->msg.rx_data = ¬ification_data;
snd_sof_ipc_msgs_rx(sdev);
sdev->ipc->msg.rx_data = NULL;
mtl_ipc_host_done(sdev);
}
ipc_irq = true;
}
if (!ipc_irq) {
/* This interrupt is not shared so no need to return IRQ_NONE. */
dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
}
if (ack_received) {
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
if (hdev->delayed_ipc_tx_msg)
mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg);
}
return IRQ_HANDLED;
}
int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MTL_DSP_MBOX_UPLINK_OFFSET;
}
int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MTL_SRAM_WINDOW_OFFSET(id);
}
void mtl_ipc_dump(struct snd_sof_dev *sdev)
{
u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR);
hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY);
hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL);
dev_err(sdev->dev,
"Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
}
static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{
mtl_enable_sdw_irq(sdev, false);
mtl_disable_ipc_interrupts(sdev);
return mtl_enable_interrupts(sdev, false);
}
u64 mtl_dsp_get_stream_hda_link_position(struct snd_sof_dev *sdev,
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct hdac_stream *hstream = substream->runtime->private_data;
u32 llp_l, llp_u;
llp_l = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPL(hstream->index));
llp_u = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, MTL_PPLCLLPU(hstream->index));
return ((u64)llp_u << 32) | llp_l;
}
static int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
{
const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
if (core == SOF_DSP_PRIMARY_CORE)
return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
if (pm_ops->set_core_state)
return pm_ops->set_core_state(sdev, core, true);
return 0;
}
static int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
{
const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
int ret;
if (pm_ops->set_core_state) {
ret = pm_ops->set_core_state(sdev, core, false);
if (ret < 0)
return ret;
}
if (core == SOF_DSP_PRIMARY_CORE)
return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
return 0;
}
/* Meteorlake ops */
struct snd_sof_dsp_ops sof_mtl_ops;
EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_mtl_ops_init(struct snd_sof_dev *sdev)
{
struct sof_ipc4_fw_data *ipc4_data;
/* common defaults */
memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
/* shutdown */
sof_mtl_ops.shutdown = hda_dsp_shutdown;
/* doorbell */
sof_mtl_ops.irq_thread = mtl_ipc_irq_thread;
/* ipc */
sof_mtl_ops.send_msg = mtl_ipc_send_msg;
sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
/* debug */
sof_mtl_ops.debug_map = mtl_dsp_debugfs;
sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs);
sof_mtl_ops.dbg_dump = mtl_dsp_dump;
sof_mtl_ops.ipc_dump = mtl_ipc_dump;
/* pre/post fw run */
sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run;
/* parse platform specific extended manifest */
sof_mtl_ops.parse_platform_ext_manifest = NULL;
/* dsp core get/put */
sof_mtl_ops.core_get = mtl_dsp_core_get;
sof_mtl_ops.core_put = mtl_dsp_core_put;
sof_mtl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position;
sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
if (!sdev->private)
return -ENOMEM;
ipc4_data = sdev->private;
ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
/* External library loading support */
ipc4_data->load_library = hda_dsp_ipc4_load_library;
/* set DAI ops */
hda_set_dai_drv_ops(sdev, &sof_mtl_ops);
sof_mtl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
return 0;
};
EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc mtl_chip_info = {
.cores_num = 3,
.init_core_mask = BIT(0),
.host_managed_cores_mask = BIT(0),
.ipc_req = MTL_DSP_REG_HFIPCXIDR,
.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
.rom_status_reg = MTL_DSP_ROM_STS,
.rom_init_timeout = 300,
.ssp_count = MTL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE_ACE,
.sdw_alh_base = SDW_ALH_BASE_ACE,
.d0i3_offset = MTL_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_common,
.enable_sdw_irq = mtl_enable_sdw_irq,
.check_sdw_irq = mtl_dsp_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.check_ipc_irq = mtl_dsp_check_ipc_irq,
.cl_init = mtl_dsp_cl_init,
.power_down_dsp = mtl_power_down_dsp,
.disable_interrupts = mtl_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_ACE_1_0,
};
EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
| linux-master | sound/soc/sof/intel/mtl.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
/*
* Hardware interface for audio DSP on Broadwell
*/
#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/intel-dsp-config.h>
#include "../ops.h"
#include "shim.h"
#include "../sof-acpi-dev.h"
#include "../sof-audio.h"
/* BARs */
#define BDW_DSP_BAR 0
#define BDW_PCI_BAR 1
/*
* Debug
*/
/* DSP memories for BDW */
#define IRAM_OFFSET 0xA0000
#define BDW_IRAM_SIZE (10 * 32 * 1024)
#define DRAM_OFFSET 0x00000
#define BDW_DRAM_SIZE (20 * 32 * 1024)
#define SHIM_OFFSET 0xFB000
#define SHIM_SIZE 0x100
#define MBOX_OFFSET 0x9E000
#define MBOX_SIZE 0x1000
#define MBOX_DUMP_SIZE 0x30
#define EXCEPT_OFFSET 0x800
#define EXCEPT_MAX_HDR_SIZE 0x400
/* DSP peripherals */
#define DMAC0_OFFSET 0xFE000
#define DMAC1_OFFSET 0xFF000
#define DMAC_SIZE 0x420
#define SSP0_OFFSET 0xFC000
#define SSP1_OFFSET 0xFD000
#define SSP_SIZE 0x100
#define BDW_STACK_DUMP_SIZE 32
#define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF)
static const struct snd_sof_debugfs_map bdw_debugfs[] = {
{"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
};
static void bdw_host_done(struct snd_sof_dev *sdev);
static void bdw_dsp_done(struct snd_sof_dev *sdev);
/*
* DSP Control.
*/
static int bdw_run(struct snd_sof_dev *sdev)
{
/* set opportunistic mode on engine 0,1 for all channels */
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
SHIM_HMDC_HDDA_E0_ALLCH |
SHIM_HMDC_HDDA_E1_ALLCH, 0);
/* set DSP to RUN */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
SHIM_CSR_STALL, 0x0);
/* return init core mask */
return 1;
}
static int bdw_reset(struct snd_sof_dev *sdev)
{
/* put DSP into reset and stall */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
SHIM_CSR_RST | SHIM_CSR_STALL,
SHIM_CSR_RST | SHIM_CSR_STALL);
/* keep in reset for 10ms */
mdelay(10);
/* take DSP out of reset and keep stalled for FW loading */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
SHIM_CSR_RST | SHIM_CSR_STALL,
SHIM_CSR_STALL);
return 0;
}
static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)
{
int tries = 10;
u32 reg;
/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
PCI_VDRTCL2_DCLCGE |
PCI_VDRTCL2_DTCGE, 0);
/* Disable D3PG (VDRTCTL0.D3PGD = 1) */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD);
/* Set D0 state */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
PCI_PMCS_PS_MASK, 0);
/* check that ADSP shim is enabled */
while (tries--) {
reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)
& PCI_PMCS_PS_MASK;
if (reg == 0)
goto finish;
msleep(20);
}
return -ENODEV;
finish:
/*
* select SSP1 19.2MHz base clock, SSP clock 0,
* turn off Low Power Clock
*/
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 |
SHIM_CSR_LPCS, 0x0);
/* stall DSP core, set clk to 192/96Mhz */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
SHIM_CSR, SHIM_CSR_STALL |
SHIM_CSR_DCS_MASK,
SHIM_CSR_STALL |
SHIM_CSR_DCS(4));
/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
SHIM_CLKCTL_MASK |
SHIM_CLKCTL_DCPLCG |
SHIM_CLKCTL_SCOE0,
SHIM_CLKCTL_MASK |
SHIM_CLKCTL_DCPLCG |
SHIM_CLKCTL_SCOE0);
/* Stall and reset core, set CSR */
bdw_reset(sdev);
/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
PCI_VDRTCL2_DCLCGE |
PCI_VDRTCL2_DTCGE,
PCI_VDRTCL2_DCLCGE |
PCI_VDRTCL2_DTCGE);
usleep_range(50, 55);
/* switch on audio PLL */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
PCI_VDRTCL2_APLLSE_MASK, 0);
/*
* set default power gating control, enable power gating control for
* all blocks. that is, can't be accessed, please enable each block
* before accessing.
*/
snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
0xfffffffC, 0x0);
/* disable DMA finish function for SSP0 & SSP1 */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
SHIM_CSR2_SDFD_SSP1,
SHIM_CSR2_SDFD_SSP1);
/* set on-demond mode on engine 0,1 for all channels */
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
SHIM_HMDC_HDDA_E0_ALLCH |
SHIM_HMDC_HDDA_E1_ALLCH,
SHIM_HMDC_HDDA_E0_ALLCH |
SHIM_HMDC_HDDA_E1_ALLCH);
/* Enable Interrupt from both sides */
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
(SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);
snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
(SHIM_IMRD_DONE | SHIM_IMRD_BUSY |
SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);
/* clear IPC registers */
snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
return 0;
}
static void bdw_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
xoops->arch_hdr.totalsize);
return;
}
offset += xoops->arch_hdr.totalsize;
sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
/* then get the stack */
offset += sizeof(*panic_info);
sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
}
static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)
{
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[BDW_STACK_DUMP_SIZE];
u32 status, panic, imrx, imrd;
/* now try generic SOF status messages */
status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
bdw_get_registers(sdev, &xoops, &panic_info, stack,
BDW_STACK_DUMP_SIZE);
sof_print_oops_and_stack(sdev, KERN_ERR, status, panic, &xoops,
&panic_info, stack, BDW_STACK_DUMP_SIZE);
/* provide some context for firmware debug */
imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX);
imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD);
dev_err(sdev->dev,
"error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n",
(panic & SHIM_IPCX_BUSY) ? "yes" : "no",
(panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
dev_err(sdev->dev,
"error: mask host: pending %s complete %s raw 0x%8.8x\n",
(imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
(imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
dev_err(sdev->dev,
"error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n",
(status & SHIM_IPCD_BUSY) ? "yes" : "no",
(status & SHIM_IPCD_DONE) ? "yes" : "no", status);
dev_err(sdev->dev,
"error: mask DSP: pending %s complete %s raw 0x%8.8x\n",
(imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
(imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
}
/*
* IPC Doorbell IRQ handler and thread.
*/
static irqreturn_t bdw_irq_handler(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
u32 isr;
int ret = IRQ_NONE;
/* Interrupt arrived, check src */
isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
ret = IRQ_WAKE_THREAD;
return ret;
}
static irqreturn_t bdw_irq_thread(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
u32 ipcx, ipcd, imrx;
imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
/* reply message from DSP */
if (ipcx & SHIM_IPCX_DONE &&
!(imrx & SHIM_IMRX_DONE)) {
/* Mask Done interrupt before return */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
SHIM_IMRX, SHIM_IMRX_DONE,
SHIM_IMRX_DONE);
spin_lock_irq(&sdev->ipc_lock);
/*
* handle immediate reply from DSP core. If the msg is
* found, set done bit in cmd_done which is called at the
* end of message processing function, else set it here
* because the done bit can't be set in cmd_done function
* which is triggered by msg
*/
snd_sof_ipc_process_reply(sdev, ipcx);
bdw_dsp_done(sdev);
spin_unlock_irq(&sdev->ipc_lock);
}
ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
/* new message from DSP */
if (ipcd & SHIM_IPCD_BUSY &&
!(imrx & SHIM_IMRX_BUSY)) {
/* Mask Busy interrupt before return */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
SHIM_IMRX, SHIM_IMRX_BUSY,
SHIM_IMRX_BUSY);
/* Handle messages from DSP Core */
if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + MBOX_OFFSET,
true);
} else {
snd_sof_ipc_msgs_rx(sdev);
}
bdw_host_done(sdev);
}
return IRQ_HANDLED;
}
/*
* IPC Mailbox IO
*/
static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{
/* send the message */
sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
msg->msg_size);
snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
return 0;
}
static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev)
{
return MBOX_OFFSET;
}
static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{
return MBOX_OFFSET;
}
static void bdw_host_done(struct snd_sof_dev *sdev)
{
/* clear BUSY bit and set DONE bit - accept new messages */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
SHIM_IPCD_BUSY | SHIM_IPCD_DONE,
SHIM_IPCD_DONE);
/* unmask busy interrupt */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
SHIM_IMRX_BUSY, 0);
}
static void bdw_dsp_done(struct snd_sof_dev *sdev)
{
/* clear DONE bit - tell DSP we have completed */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
SHIM_IPCX_DONE, 0);
/* unmask Done interrupt */
snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
SHIM_IMRX_DONE, 0);
}
/*
* Probe and remove.
*/
static int bdw_probe(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_dev_desc *desc = pdata->desc;
struct platform_device *pdev =
container_of(sdev->dev, struct platform_device, dev);
const struct sof_intel_dsp_desc *chip;
struct resource *mmio;
u32 base, size;
int ret;
chip = get_chip_info(sdev->pdata);
if (!chip) {
dev_err(sdev->dev, "error: no such device supported\n");
return -EIO;
}
sdev->num_cores = chip->cores_num;
/* LPE base */
mmio = platform_get_resource(pdev, IORESOURCE_MEM,
desc->resindex_lpe_base);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
desc->resindex_lpe_base);
return -EINVAL;
}
dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[BDW_DSP_BAR]) {
dev_err(sdev->dev,
"error: failed to ioremap LPE base 0x%x size 0x%x\n",
base, size);
return -ENODEV;
}
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
/* TODO: add offsets */
sdev->mmio_bar = BDW_DSP_BAR;
sdev->mailbox_bar = BDW_DSP_BAR;
sdev->dsp_oops_offset = MBOX_OFFSET;
/* PCI base */
mmio = platform_get_resource(pdev, IORESOURCE_MEM,
desc->resindex_pcicfg_base);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
desc->resindex_pcicfg_base);
return -ENODEV;
}
dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[BDW_PCI_BAR]) {
dev_err(sdev->dev,
"error: failed to ioremap PCI base 0x%x size 0x%x\n",
base, size);
return -ENODEV;
}
dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);
/* register our IRQ */
sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
if (sdev->ipc_irq < 0)
return sdev->ipc_irq;
dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
bdw_irq_handler, bdw_irq_thread,
IRQF_SHARED, "AudioDSP", sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to register IRQ %d\n",
sdev->ipc_irq);
return ret;
}
/* enable the DSP SHIM */
ret = bdw_set_dsp_D0(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to set DSP D0\n");
return ret;
}
/* DSP DMA can only access low 31 bits of host memory */
ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
if (ret < 0) {
dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
return ret;
}
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = MBOX_OFFSET;
return ret;
}
static struct snd_soc_acpi_mach *bdw_machine_select(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *sof_pdata = sdev->pdata;
const struct sof_dev_desc *desc = sof_pdata->desc;
struct snd_soc_acpi_mach *mach;
mach = snd_soc_acpi_find_machine(desc->machines);
if (!mach) {
dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
return NULL;
}
sof_pdata->tplg_filename = mach->sof_tplg_filename;
mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
return mach;
}
static void bdw_set_mach_params(struct snd_soc_acpi_mach *mach,
struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_dev_desc *desc = pdata->desc;
struct snd_soc_acpi_mach_params *mach_params;
mach_params = &mach->mach_params;
mach_params->platform = dev_name(sdev->dev);
mach_params->num_dai_drivers = desc->ops->num_drv;
mach_params->dai_drivers = desc->ops->drv;
}
/* Broadwell DAIs */
static struct snd_soc_dai_driver bdw_dai[] = {
{
.name = "ssp0-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
{
.name = "ssp1-port",
.playback = {
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
},
},
};
/* broadwell ops */
static struct snd_sof_dsp_ops sof_bdw_ops = {
/*Device init */
.probe = bdw_probe,
/* DSP Core Control */
.run = bdw_run,
.reset = bdw_reset,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* ipc */
.send_msg = bdw_send_msg,
.get_mailbox_offset = bdw_get_mailbox_offset,
.get_window_offset = bdw_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
/* machine driver */
.machine_select = bdw_machine_select,
.machine_register = sof_machine_register,
.machine_unregister = sof_machine_unregister,
.set_mach_params = bdw_set_mach_params,
/* debug */
.debug_map = bdw_debugfs,
.debug_map_count = ARRAY_SIZE(bdw_debugfs),
.dbg_dump = bdw_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/*Firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* DAI drivers */
.drv = bdw_dai,
.num_drv = ARRAY_SIZE(bdw_dai),
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_BATCH,
.dsp_arch_ops = &sof_xtensa_arch_ops,
};
static const struct sof_intel_dsp_desc bdw_chip_info = {
.cores_num = 1,
.host_managed_cores_mask = 1,
.hw_ip_version = SOF_INTEL_BROADWELL,
};
static const struct sof_dev_desc sof_acpi_broadwell_desc = {
.machines = snd_soc_acpi_intel_broadwell_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = 1,
.resindex_imr_base = -1,
.irqindex_host_ipc = 0,
.chip_info = &bdw_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "intel/sof",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-bdw.ri",
},
.nocodec_tplg_filename = "sof-bdw-nocodec.tplg",
.ops = &sof_bdw_ops,
};
static const struct acpi_device_id sof_broadwell_match[] = {
{ "INT3438", (unsigned long)&sof_acpi_broadwell_desc },
{ }
};
MODULE_DEVICE_TABLE(acpi, sof_broadwell_match);
static int sof_broadwell_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct acpi_device_id *id;
const struct sof_dev_desc *desc;
int ret;
id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!id)
return -ENODEV;
ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
return -ENODEV;
}
desc = (const struct sof_dev_desc *)id->driver_data;
return sof_acpi_probe(pdev, desc);
}
/* acpi_driver definition */
static struct platform_driver snd_sof_acpi_intel_bdw_driver = {
.probe = sof_broadwell_probe,
.remove = sof_acpi_remove,
.driver = {
.name = "sof-audio-acpi-intel-bdw",
.pm = &sof_acpi_pm,
.acpi_match_table = sof_broadwell_match,
},
};
module_platform_driver(snd_sof_acpi_intel_bdw_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
| linux-master | sound/soc/sof/intel/bdw.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/module.h>
#include <linux/pci.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "../ops.h"
#include "atom.h"
#include "../sof-pci-dev.h"
#include "../sof-audio.h"
/* platform specific devices */
#include "shim.h"
static struct snd_soc_acpi_mach sof_tng_machines[] = {
{
.id = "INT343A",
.drv_name = "edison",
.sof_tplg_filename = "sof-byt.tplg",
},
{}
};
static const struct snd_sof_debugfs_map tng_debugfs[] = {
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
SOF_DEBUGFS_ACCESS_ALWAYS},
};
static int tangier_pci_probe(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_dev_desc *desc = pdata->desc;
struct pci_dev *pci = to_pci_dev(sdev->dev);
const struct sof_intel_dsp_desc *chip;
u32 base, size;
int ret;
chip = get_chip_info(sdev->pdata);
if (!chip) {
dev_err(sdev->dev, "error: no such device supported\n");
return -EIO;
}
sdev->num_cores = chip->cores_num;
/* DSP DMA can only access low 31 bits of host memory */
ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
if (ret < 0) {
dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
return ret;
}
/* LPE base */
base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
size = PCI_BAR_SIZE;
dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[DSP_BAR]) {
dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
base, size);
return -ENODEV;
}
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
/* IMR base - optional */
if (desc->resindex_imr_base == -1)
goto irq;
base = pci_resource_start(pci, desc->resindex_imr_base);
size = pci_resource_len(pci, desc->resindex_imr_base);
/* some BIOSes don't map IMR */
if (base == 0x55aa55aa || base == 0x0) {
dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
goto irq;
}
dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[IMR_BAR]) {
dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
base, size);
return -ENODEV;
}
dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
irq:
/* register our IRQ */
sdev->ipc_irq = pci->irq;
dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
atom_irq_handler, atom_irq_thread,
0, "AudioDSP", sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to register IRQ %d\n",
sdev->ipc_irq);
return ret;
}
/* enable BUSY and disable DONE Interrupt by default */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
SHIM_IMRX_DONE);
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = MBOX_OFFSET;
return ret;
}
struct snd_sof_dsp_ops sof_tng_ops = {
/* device init */
.probe = tangier_pci_probe,
/* DSP core boot / reset */
.run = atom_run,
.reset = atom_reset,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* doorbell */
.irq_handler = atom_irq_handler,
.irq_thread = atom_irq_thread,
/* ipc */
.send_msg = atom_send_msg,
.get_mailbox_offset = atom_get_mailbox_offset,
.get_window_offset = atom_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
/* machine driver */
.machine_select = atom_machine_select,
.machine_register = sof_machine_register,
.machine_unregister = sof_machine_unregister,
.set_mach_params = atom_set_mach_params,
/* debug */
.debug_map = tng_debugfs,
.debug_map_count = ARRAY_SIZE(tng_debugfs),
.dbg_dump = atom_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/*Firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* DAI drivers */
.drv = atom_dai,
.num_drv = 3, /* we have only 3 SSPs on byt*/
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_BATCH,
.dsp_arch_ops = &sof_xtensa_arch_ops,
};
const struct sof_intel_dsp_desc tng_chip_info = {
.cores_num = 1,
.host_managed_cores_mask = 1,
.hw_ip_version = SOF_INTEL_TANGIER,
};
static const struct sof_dev_desc tng_desc = {
.machines = sof_tng_machines,
.resindex_lpe_base = 3, /* IRAM, but subtract IRAM offset */
.resindex_pcicfg_base = -1,
.resindex_imr_base = 0,
.irqindex_host_ipc = -1,
.chip_info = &tng_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "intel/sof",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-byt.ri",
},
.nocodec_tplg_filename = "sof-byt.tplg",
.ops = &sof_tng_ops,
};
/* PCI IDs */
static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, SST_TNG, &tng_desc) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sof_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_sof_pci_intel_tng_driver = {
.name = "sof-audio-pci-intel-tng",
.id_table = sof_pci_ids,
.probe = sof_pci_probe,
.remove = sof_pci_remove,
.shutdown = sof_pci_shutdown,
.driver = {
.pm = &sof_pci_pm,
},
};
module_pci_driver(snd_sof_pci_intel_tng_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
| linux-master | sound/soc/sof/intel/pci-tng.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2021 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/module.h>
#include <linux/pci.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "../ops.h"
#include "../sof-pci-dev.h"
/* platform specific devices */
#include "hda.h"
static const struct sof_dev_desc bxt_desc = {
.machines = snd_soc_acpi_intel_bxt_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &apl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/apl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/apl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-apl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-apl-nocodec.tplg",
.ops = &sof_apl_ops,
.ops_init = sof_apl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc glk_desc = {
.machines = snd_soc_acpi_intel_glk_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &apl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/glk",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/glk",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-glk.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-glk-nocodec.tplg",
.ops = &sof_apl_ops,
.ops_init = sof_apl_ops_init,
.ops_free = hda_ops_free,
};
/* PCI IDs */
static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_APL, &bxt_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_GML, &glk_desc) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sof_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_sof_pci_intel_apl_driver = {
.name = "sof-audio-pci-intel-apl",
.id_table = sof_pci_ids,
.probe = hda_pci_intel_probe,
.remove = sof_pci_remove,
.shutdown = sof_pci_shutdown,
.driver = {
.pm = &sof_pci_pm,
},
};
module_pci_driver(snd_sof_pci_intel_apl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
| linux-master | sound/soc/sof/intel/pci-apl.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
/*
* Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
*/
#include <linux/module.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/intel-dsp-config.h>
#include "../ops.h"
#include "atom.h"
#include "shim.h"
#include "../sof-acpi-dev.h"
#include "../sof-audio.h"
#include "../../intel/common/soc-intel-quirks.h"
static const struct snd_sof_debugfs_map byt_debugfs[] = {
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
SOF_DEBUGFS_ACCESS_ALWAYS},
};
static const struct snd_sof_debugfs_map cht_debugfs[] = {
{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
SOF_DEBUGFS_ACCESS_ALWAYS},
{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
SOF_DEBUGFS_ACCESS_D0_ONLY},
{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
SOF_DEBUGFS_ACCESS_ALWAYS},
};
static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
{
/* Disable Interrupt from both sides */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);
/* Put DSP into reset, set reset vector */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
}
static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
{
byt_reset_dsp_disable_int(sdev);
return 0;
}
static int byt_resume(struct snd_sof_dev *sdev)
{
/* enable BUSY and disable DONE Interrupt by default */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
SHIM_IMRX_DONE);
return 0;
}
static int byt_remove(struct snd_sof_dev *sdev)
{
byt_reset_dsp_disable_int(sdev);
return 0;
}
static int byt_acpi_probe(struct snd_sof_dev *sdev)
{
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_dev_desc *desc = pdata->desc;
struct platform_device *pdev =
container_of(sdev->dev, struct platform_device, dev);
const struct sof_intel_dsp_desc *chip;
struct resource *mmio;
u32 base, size;
int ret;
chip = get_chip_info(sdev->pdata);
if (!chip) {
dev_err(sdev->dev, "error: no such device supported\n");
return -EIO;
}
sdev->num_cores = chip->cores_num;
/* DSP DMA can only access low 31 bits of host memory */
ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
if (ret < 0) {
dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
return ret;
}
/* LPE base */
mmio = platform_get_resource(pdev, IORESOURCE_MEM,
desc->resindex_lpe_base);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
desc->resindex_lpe_base);
return -EINVAL;
}
dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[DSP_BAR]) {
dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
base, size);
return -ENODEV;
}
dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
/* TODO: add offsets */
sdev->mmio_bar = DSP_BAR;
sdev->mailbox_bar = DSP_BAR;
/* IMR base - optional */
if (desc->resindex_imr_base == -1)
goto irq;
mmio = platform_get_resource(pdev, IORESOURCE_MEM,
desc->resindex_imr_base);
if (mmio) {
base = mmio->start;
size = resource_size(mmio);
} else {
dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
desc->resindex_imr_base);
return -ENODEV;
}
/* some BIOSes don't map IMR */
if (base == 0x55aa55aa || base == 0x0) {
dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
goto irq;
}
dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
if (!sdev->bar[IMR_BAR]) {
dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
base, size);
return -ENODEV;
}
dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
irq:
/* register our IRQ */
sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
if (sdev->ipc_irq < 0)
return sdev->ipc_irq;
dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
atom_irq_handler, atom_irq_thread,
IRQF_SHARED, "AudioDSP", sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to register IRQ %d\n",
sdev->ipc_irq);
return ret;
}
/* enable BUSY and disable DONE Interrupt by default */
snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
SHIM_IMRX_DONE);
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = MBOX_OFFSET;
return ret;
}
/* baytrail ops */
static struct snd_sof_dsp_ops sof_byt_ops = {
/* device init */
.probe = byt_acpi_probe,
.remove = byt_remove,
/* DSP core boot / reset */
.run = atom_run,
.reset = atom_reset,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* doorbell */
.irq_handler = atom_irq_handler,
.irq_thread = atom_irq_thread,
/* ipc */
.send_msg = atom_send_msg,
.get_mailbox_offset = atom_get_mailbox_offset,
.get_window_offset = atom_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
/* machine driver */
.machine_select = atom_machine_select,
.machine_register = sof_machine_register,
.machine_unregister = sof_machine_unregister,
.set_mach_params = atom_set_mach_params,
/* debug */
.debug_map = byt_debugfs,
.debug_map_count = ARRAY_SIZE(byt_debugfs),
.dbg_dump = atom_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/*Firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* PM */
.suspend = byt_suspend,
.resume = byt_resume,
/* DAI drivers */
.drv = atom_dai,
.num_drv = 3, /* we have only 3 SSPs on byt*/
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_BATCH,
.dsp_arch_ops = &sof_xtensa_arch_ops,
};
static const struct sof_intel_dsp_desc byt_chip_info = {
.cores_num = 1,
.host_managed_cores_mask = 1,
.hw_ip_version = SOF_INTEL_BAYTRAIL,
};
/* cherrytrail and braswell ops */
static struct snd_sof_dsp_ops sof_cht_ops = {
/* device init */
.probe = byt_acpi_probe,
.remove = byt_remove,
/* DSP core boot / reset */
.run = atom_run,
.reset = atom_reset,
/* Register IO uses direct mmio */
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
/* Mailbox IO */
.mailbox_read = sof_mailbox_read,
.mailbox_write = sof_mailbox_write,
/* doorbell */
.irq_handler = atom_irq_handler,
.irq_thread = atom_irq_thread,
/* ipc */
.send_msg = atom_send_msg,
.get_mailbox_offset = atom_get_mailbox_offset,
.get_window_offset = atom_get_window_offset,
.ipc_msg_data = sof_ipc_msg_data,
.set_stream_data_offset = sof_set_stream_data_offset,
/* machine driver */
.machine_select = atom_machine_select,
.machine_register = sof_machine_register,
.machine_unregister = sof_machine_unregister,
.set_mach_params = atom_set_mach_params,
/* debug */
.debug_map = cht_debugfs,
.debug_map_count = ARRAY_SIZE(cht_debugfs),
.dbg_dump = atom_dump,
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
/* stream callbacks */
.pcm_open = sof_stream_pcm_open,
.pcm_close = sof_stream_pcm_close,
/*Firmware loading */
.load_firmware = snd_sof_load_firmware_memcpy,
/* PM */
.suspend = byt_suspend,
.resume = byt_resume,
/* DAI drivers */
.drv = atom_dai,
/* all 6 SSPs may be available for cherrytrail */
.num_drv = 6,
/* ALSA HW info flags */
.hw_info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_BATCH,
.dsp_arch_ops = &sof_xtensa_arch_ops,
};
static const struct sof_intel_dsp_desc cht_chip_info = {
.cores_num = 1,
.host_managed_cores_mask = 1,
.hw_ip_version = SOF_INTEL_BAYTRAIL,
};
/* BYTCR uses different IRQ index */
static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
.machines = snd_soc_acpi_intel_baytrail_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = 1,
.resindex_imr_base = 2,
.irqindex_host_ipc = 0,
.chip_info = &byt_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "intel/sof",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-byt.ri",
},
.nocodec_tplg_filename = "sof-byt-nocodec.tplg",
.ops = &sof_byt_ops,
};
static const struct sof_dev_desc sof_acpi_baytrail_desc = {
.machines = snd_soc_acpi_intel_baytrail_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = 1,
.resindex_imr_base = 2,
.irqindex_host_ipc = 5,
.chip_info = &byt_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "intel/sof",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-byt.ri",
},
.nocodec_tplg_filename = "sof-byt-nocodec.tplg",
.ops = &sof_byt_ops,
};
static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
.machines = snd_soc_acpi_intel_cherrytrail_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = 1,
.resindex_imr_base = 2,
.irqindex_host_ipc = 5,
.chip_info = &cht_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = {
[SOF_IPC] = "intel/sof",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-cht.ri",
},
.nocodec_tplg_filename = "sof-cht-nocodec.tplg",
.ops = &sof_cht_ops,
};
static const struct acpi_device_id sof_baytrail_match[] = {
{ "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
{ "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
{ }
};
MODULE_DEVICE_TABLE(acpi, sof_baytrail_match);
static int sof_baytrail_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct sof_dev_desc *desc;
const struct acpi_device_id *id;
int ret;
id = acpi_match_device(dev->driver->acpi_match_table, dev);
if (!id)
return -ENODEV;
ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
return -ENODEV;
}
desc = (const struct sof_dev_desc *)id->driver_data;
if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev))
desc = &sof_acpi_baytrailcr_desc;
return sof_acpi_probe(pdev, desc);
}
/* acpi_driver definition */
static struct platform_driver snd_sof_acpi_intel_byt_driver = {
.probe = sof_baytrail_probe,
.remove = sof_acpi_remove,
.driver = {
.name = "sof-audio-acpi-intel-byt",
.pm = &sof_acpi_pm,
.acpi_match_table = sof_baytrail_match,
},
};
module_platform_driver(snd_sof_acpi_intel_byt_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
| linux-master | sound/soc/sof/intel/byt.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2023 Intel Corporation. All rights reserved.
//
// Author: Ranjani Sridharan <[email protected]>
//
#include <linux/module.h>
#include <linux/pci.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "../ops.h"
#include "../sof-pci-dev.h"
/* platform specific devices */
#include "hda.h"
#include "mtl.h"
static const struct sof_dev_desc lnl_desc = {
.use_acpi_target_states = true,
.machines = snd_soc_acpi_intel_lnl_machines,
.alt_machines = snd_soc_acpi_intel_lnl_sdw_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &lnl_chip_info,
.ipc_supported_mask = BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_INTEL_IPC4,
.dspless_mode_supported = true,
.default_fw_path = {
[SOF_INTEL_IPC4] = "intel/sof-ipc4/lnl",
},
.default_tplg_path = {
[SOF_INTEL_IPC4] = "intel/sof-ace-tplg",
},
.default_fw_filename = {
[SOF_INTEL_IPC4] = "sof-lnl.ri",
},
.nocodec_tplg_filename = "sof-lnl-nocodec.tplg",
.ops = &sof_lnl_ops,
.ops_init = sof_lnl_ops_init,
};
/* PCI IDs */
static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_LNL_P, &lnl_desc) }, /* LNL-P */
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sof_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_sof_pci_intel_lnl_driver = {
.name = "sof-audio-pci-intel-lnl",
.id_table = sof_pci_ids,
.probe = hda_pci_intel_probe,
.remove = sof_pci_remove,
.shutdown = sof_pci_shutdown,
.driver = {
.pm = &sof_pci_pm,
},
};
module_pci_driver(snd_sof_pci_intel_lnl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
| linux-master | sound/soc/sof/intel/pci-lnl.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Keyon Jie <[email protected]>
//
#include <linux/module.h>
#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>
#include <sound/hda_codec.h>
#include <sound/hda_i915.h>
#include <sound/sof.h>
#include "../ops.h"
#include "hda.h"
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
#include "../../codecs/hdac_hda.h"
#define CODEC_PROBE_RETRIES 3
#define IDISP_VID_INTEL 0x80860000
static int hda_codec_mask = -1;
module_param_named(codec_mask, hda_codec_mask, int, 0444);
MODULE_PARM_DESC(codec_mask, "SOF HDA codec mask for probing");
/* load the legacy HDA codec driver */
static int request_codec_module(struct hda_codec *codec)
{
#ifdef MODULE
char alias[MODULE_NAME_LEN];
const char *mod = NULL;
switch (codec->probe_id) {
case HDA_CODEC_ID_GENERIC:
#if IS_MODULE(CONFIG_SND_HDA_GENERIC)
mod = "snd-hda-codec-generic";
#endif
break;
default:
snd_hdac_codec_modalias(&codec->core, alias, sizeof(alias));
mod = alias;
break;
}
if (mod) {
dev_dbg(&codec->core.dev, "loading codec module: %s\n", mod);
request_module(mod);
}
#endif /* MODULE */
return device_attach(hda_codec_dev(codec));
}
static int hda_codec_load_module(struct hda_codec *codec)
{
int ret = request_codec_module(codec);
if (ret <= 0) {
codec->probe_id = HDA_CODEC_ID_GENERIC;
ret = request_codec_module(codec);
}
return ret;
}
/* enable controller wake up event for all codecs with jack connectors */
void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable)
{
struct hda_bus *hbus = sof_to_hbus(sdev);
struct hdac_bus *bus = sof_to_bus(sdev);
struct hda_codec *codec;
unsigned int mask = 0;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
if (enable) {
list_for_each_codec(codec, hbus)
if (codec->jacktbl.used)
mask |= BIT(codec->core.addr);
}
snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, mask);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_jack_wake_enable, SND_SOC_SOF_HDA_AUDIO_CODEC);
/* check jack status after resuming from suspend mode */
void hda_codec_jack_check(struct snd_sof_dev *sdev)
{
struct hda_bus *hbus = sof_to_hbus(sdev);
struct hda_codec *codec;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
list_for_each_codec(codec, hbus)
/*
* Wake up all jack-detecting codecs regardless whether an event
* has been recorded in STATESTS
*/
if (codec->jacktbl.used)
pm_request_resume(&codec->core.dev);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_jack_check, SND_SOC_SOF_HDA_AUDIO_CODEC);
#if IS_ENABLED(CONFIG_SND_HDA_GENERIC)
#define is_generic_config(bus) \
((bus)->modelname && !strcmp((bus)->modelname, "generic"))
#else
#define is_generic_config(x) 0
#endif
static struct hda_codec *hda_codec_device_init(struct hdac_bus *bus, int addr, int type)
{
struct hda_codec *codec;
int ret;
codec = snd_hda_codec_device_init(to_hda_bus(bus), addr, "ehdaudio%dD%d", bus->idx, addr);
if (IS_ERR(codec)) {
dev_err(bus->dev, "device init failed for hdac device\n");
return codec;
}
codec->core.type = type;
ret = snd_hdac_device_register(&codec->core);
if (ret) {
dev_err(bus->dev, "failed to register hdac device\n");
put_device(&codec->core.dev);
return ERR_PTR(ret);
}
return codec;
}
/* probe individual codec */
static int hda_codec_probe(struct snd_sof_dev *sdev, int address)
{
struct hdac_hda_priv *hda_priv;
struct hda_bus *hbus = sof_to_hbus(sdev);
struct hda_codec *codec;
u32 hda_cmd = (address << 28) | (AC_NODE_ROOT << 20) |
(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
u32 resp = -1;
int ret, retry = 0;
do {
mutex_lock(&hbus->core.cmd_mutex);
snd_hdac_bus_send_cmd(&hbus->core, hda_cmd);
snd_hdac_bus_get_response(&hbus->core, address, &resp);
mutex_unlock(&hbus->core.cmd_mutex);
} while (resp == -1 && retry++ < CODEC_PROBE_RETRIES);
if (resp == -1)
return -EIO;
dev_dbg(sdev->dev, "HDA codec #%d probed OK: response: %x\n",
address, resp);
hda_priv = devm_kzalloc(sdev->dev, sizeof(*hda_priv), GFP_KERNEL);
if (!hda_priv)
return -ENOMEM;
codec = hda_codec_device_init(&hbus->core, address, HDA_DEV_LEGACY);
ret = PTR_ERR_OR_ZERO(codec);
if (ret < 0)
return ret;
hda_priv->codec = codec;
dev_set_drvdata(&codec->core.dev, hda_priv);
if ((resp & 0xFFFF0000) == IDISP_VID_INTEL) {
if (!hbus->core.audio_component) {
dev_dbg(sdev->dev,
"iDisp hw present but no driver\n");
ret = -ENOENT;
goto out;
}
hda_priv->need_display_power = true;
}
if (is_generic_config(hbus))
codec->probe_id = HDA_CODEC_ID_GENERIC;
else
codec->probe_id = 0;
ret = hda_codec_load_module(codec);
/*
* handle ret==0 (no driver bound) as an error, but pass
* other return codes without modification
*/
if (ret == 0)
ret = -ENOENT;
out:
if (ret < 0) {
snd_hdac_device_unregister(&codec->core);
put_device(&codec->core.dev);
}
return ret;
}
/* Codec initialization */
void hda_codec_probe_bus(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
int i, ret;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* probe codecs in avail slots */
for (i = 0; i < HDA_MAX_CODECS; i++) {
if (!(bus->codec_mask & (1 << i)))
continue;
ret = hda_codec_probe(sdev, i);
if (ret < 0) {
dev_warn(bus->dev, "codec #%d probe error, ret: %d\n",
i, ret);
bus->codec_mask &= ~BIT(i);
}
}
}
EXPORT_SYMBOL_NS_GPL(hda_codec_probe_bus, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_check_for_state_change(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
unsigned int codec_mask;
codec_mask = snd_hdac_chip_readw(bus, STATESTS);
if (codec_mask) {
hda_codec_jack_check(sdev);
snd_hdac_chip_writew(bus, STATESTS, codec_mask);
}
}
EXPORT_SYMBOL_NS_GPL(hda_codec_check_for_state_change, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_detect_mask(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* Accept unsolicited responses */
snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
/* detect codecs */
if (!bus->codec_mask) {
bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
}
if (hda_codec_mask != -1) {
bus->codec_mask &= hda_codec_mask;
dev_dbg(bus->dev, "filtered codec_mask = 0x%lx\n",
bus->codec_mask);
}
}
EXPORT_SYMBOL_NS_GPL(hda_codec_detect_mask, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_init_cmd_io(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* initialize the codec command I/O */
snd_hdac_bus_init_cmd_io(bus);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_init_cmd_io, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* set up CORB/RIRB buffers if was on before suspend */
if (bus->cmd_dma_state)
snd_hdac_bus_init_cmd_io(bus);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_resume_cmd_io, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* initialize the codec command I/O */
snd_hdac_bus_stop_cmd_io(bus);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_stop_cmd_io, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* stop the CORB/RIRB DMA if it is On */
if (bus->cmd_dma_state)
snd_hdac_bus_stop_cmd_io(bus);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_suspend_cmd_io, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* clear rirb status */
snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_rirb_status_clear, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
snd_hdac_set_codec_wakeup(bus, status);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_set_codec_wakeup, SND_SOC_SOF_HDA_AUDIO_CODEC);
bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
bool active = false;
u32 rirb_status;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return false;
rirb_status = snd_hdac_chip_readb(bus, RIRBSTS);
if (rirb_status & RIRB_INT_MASK) {
/*
* Clearing the interrupt status here ensures
* that no interrupt gets masked after the RIRB
* wp is read in snd_hdac_bus_update_rirb.
*/
snd_hdac_chip_writeb(bus, RIRBSTS,
RIRB_INT_MASK);
active = true;
if (rirb_status & RIRB_INT_RESPONSE)
snd_hdac_bus_update_rirb(bus);
}
return active;
}
EXPORT_SYMBOL_NS_GPL(hda_codec_check_rirb_status, SND_SOC_SOF_HDA_AUDIO_CODEC);
void hda_codec_device_remove(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
/* codec removal, invoke bus_device_remove */
snd_hdac_ext_bus_device_remove(bus);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_device_remove, SND_SOC_SOF_HDA_AUDIO_CODEC);
#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return;
if (HDA_IDISP_CODEC(bus->codec_mask)) {
dev_dbg(bus->dev, "Turning i915 HDAC power %d\n", enable);
snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable);
}
}
EXPORT_SYMBOL_NS_GPL(hda_codec_i915_display_power, SND_SOC_SOF_HDA_AUDIO_CODEC_I915);
int hda_codec_i915_init(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
int ret;
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return 0;
/* i915 exposes a HDA codec for HDMI audio */
ret = snd_hdac_i915_init(bus);
if (ret < 0)
return ret;
/* codec_mask not yet known, power up for probe */
snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
return 0;
}
EXPORT_SYMBOL_NS_GPL(hda_codec_i915_init, SND_SOC_SOF_HDA_AUDIO_CODEC_I915);
int hda_codec_i915_exit(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) &&
sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC))
return 0;
if (!bus->audio_component)
return 0;
/* power down unconditionally */
snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
return snd_hdac_i915_exit(bus);
}
EXPORT_SYMBOL_NS_GPL(hda_codec_i915_exit, SND_SOC_SOF_HDA_AUDIO_CODEC_I915);
#endif
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/intel/hda-codec.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <[email protected]>
// Ranjani Sridharan <[email protected]>
// Rander Wang <[email protected]>
// Keyon Jie <[email protected]>
//
/*
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <linux/module.h>
#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>
#include <sound/hda-mlink.h>
#include <trace/events/sof_intel.h>
#include "../sof-audio.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
static bool hda_enable_trace_D0I3_S0;
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
MODULE_PARM_DESC(enable_trace_D0I3_S0,
"SOF HDA enable trace when the DSP is in D0I3 in S0");
#endif
/*
* DSP Core control.
*/
static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
{
u32 adspcs;
u32 reset;
int ret;
/* set reset bits for cores */
reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS,
reset, reset);
/* poll with timeout to check if operation successful */
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS, adspcs,
((adspcs & reset) == reset),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev,
"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
__func__);
return ret;
}
/* has core entered reset ? */
adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS);
if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
dev_err(sdev->dev,
"error: reset enter failed: core_mask %x adspcs 0x%x\n",
core_mask, adspcs);
ret = -EIO;
}
return ret;
}
static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
{
unsigned int crst;
u32 adspcs;
int ret;
/* clear reset bits for cores */
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS,
HDA_DSP_ADSPCS_CRST_MASK(core_mask),
0);
/* poll with timeout to check if operation successful */
crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS, adspcs,
!(adspcs & crst),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev,
"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
__func__);
return ret;
}
/* has core left reset ? */
adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS);
if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
dev_err(sdev->dev,
"error: reset leave failed: core_mask %x adspcs 0x%x\n",
core_mask, adspcs);
ret = -EIO;
}
return ret;
}
int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
{
/* stall core */
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS,
HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
/* set reset state */
return hda_dsp_core_reset_enter(sdev, core_mask);
}
bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
{
int val;
bool is_enable;
val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
#define MASK_IS_EQUAL(v, m, field) ({ \
u32 _m = field(m); \
((v) & _m) == _m; \
})
is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
!(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
!(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
#undef MASK_IS_EQUAL
dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
is_enable, core_mask);
return is_enable;
}
int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
{
int ret;
/* leave reset state */
ret = hda_dsp_core_reset_leave(sdev, core_mask);
if (ret < 0)
return ret;
/* run core */
dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS,
HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
0);
/* is core now running ? */
if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
hda_dsp_core_stall_reset(sdev, core_mask);
dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
core_mask);
ret = -EIO;
}
return ret;
}
/*
* Power Management.
*/
int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
unsigned int cpa;
u32 adspcs;
int ret;
/* restrict core_mask to host managed cores mask */
core_mask &= chip->host_managed_cores_mask;
/* return if core_mask is not valid */
if (!core_mask)
return 0;
/* update bits */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
HDA_DSP_ADSPCS_SPA_MASK(core_mask),
HDA_DSP_ADSPCS_SPA_MASK(core_mask));
/* poll with timeout to check if operation successful */
cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS, adspcs,
(adspcs & cpa) == cpa,
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_RESET_TIMEOUT_US);
if (ret < 0) {
dev_err(sdev->dev,
"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
__func__);
return ret;
}
/* did core power up ? */
adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS);
if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
dev_err(sdev->dev,
"error: power up core failed core_mask %xadspcs 0x%x\n",
core_mask, adspcs);
ret = -EIO;
}
return ret;
}
static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
{
u32 adspcs;
int ret;
/* update bits */
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS,
HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
HDA_DSP_REG_ADSPCS, adspcs,
!(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
if (ret < 0)
dev_err(sdev->dev,
"error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
__func__);
return ret;
}
int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
int ret;
/* restrict core_mask to host managed cores mask */
core_mask &= chip->host_managed_cores_mask;
/* return if core_mask is not valid or cores are already enabled */
if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
return 0;
/* power up */
ret = hda_dsp_core_power_up(sdev, core_mask);
if (ret < 0) {
dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
core_mask);
return ret;
}
return hda_dsp_core_run(sdev, core_mask);
}
int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
unsigned int core_mask)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
int ret;
/* restrict core_mask to host managed cores mask */
core_mask &= chip->host_managed_cores_mask;
/* return if core_mask is not valid */
if (!core_mask)
return 0;
/* place core in reset prior to power down */
ret = hda_dsp_core_stall_reset(sdev, core_mask);
if (ret < 0) {
dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
core_mask);
return ret;
}
/* power down core */
ret = hda_dsp_core_power_down(sdev, core_mask);
if (ret < 0) {
dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
core_mask, ret);
return ret;
}
/* make sure we are in OFF state */
if (hda_dsp_core_is_enabled(sdev, core_mask)) {
dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
core_mask, ret);
ret = -EIO;
}
return ret;
}
void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
if (sdev->dspless_mode_selected)
return;
/* enable IPC DONE and BUSY interrupts */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
/* enable IPC interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
}
void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
if (sdev->dspless_mode_selected)
return;
/* disable IPC interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
HDA_DSP_ADSPIC_IPC, 0);
/* disable IPC BUSY and DONE interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
}
static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
{
int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(pdata);
while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset) &
SOF_HDA_VS_D0I3C_CIP) {
if (!retry--)
return -ETIMEDOUT;
usleep_range(10, 15);
}
return 0;
}
static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
{
const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm);
if (pm_ops && pm_ops->set_pm_gate)
return pm_ops->set_pm_gate(sdev, flags);
return 0;
}
static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
{
struct snd_sof_pdata *pdata = sdev->pdata;
const struct sof_intel_dsp_desc *chip;
int ret;
u8 reg;
chip = get_chip_info(pdata);
/* Write to D0I3C after Command-In-Progress bit is cleared */
ret = hda_dsp_wait_d0i3c_done(sdev);
if (ret < 0) {
dev_err(sdev->dev, "CIP timeout before D0I3C update!\n");
return ret;
}
/* Update D0I3C register */
snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset,
SOF_HDA_VS_D0I3C_I3, value);
/*
* The value written to the D0I3C::I3 bit may not be taken into account immediately.
* A delay is recommended before checking if D0I3C::CIP is cleared
*/
usleep_range(30, 40);
/* Wait for cmd in progress to be cleared before exiting the function */
ret = hda_dsp_wait_d0i3c_done(sdev);
if (ret < 0) {
dev_err(sdev->dev, "CIP timeout after D0I3C update!\n");
return ret;
}
reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset);
/* Confirm d0i3 state changed with paranoia check */
if ((reg ^ value) & SOF_HDA_VS_D0I3C_I3) {
dev_err(sdev->dev, "failed to update D0I3C!\n");
return -EIO;
}
trace_sof_intel_D0I3C_updated(sdev, reg);
return 0;
}
/*
* d0i3 streaming is enabled if all the active streams can
* work in d0i3 state and playback is enabled
*/
static bool hda_dsp_d0i3_streaming_applicable(struct snd_sof_dev *sdev)
{
struct snd_pcm_substream *substream;
struct snd_sof_pcm *spcm;
bool playback_active = false;
int dir;
list_for_each_entry(spcm, &sdev->pcm_list, list) {
for_each_pcm_streams(dir) {
substream = spcm->stream[dir].substream;
if (!substream || !substream->runtime)
continue;
if (!spcm->stream[dir].d0i3_compatible)
return false;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
playback_active = true;
}
}
return playback_active;
}
static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
u32 flags = 0;
int ret;
u8 value = 0;
/*
* Sanity check for illegal state transitions
* The only allowed transitions are:
* 1. D3 -> D0I0
* 2. D0I0 -> D0I3
* 3. D0I3 -> D0I0
*/
switch (sdev->dsp_power_state.state) {
case SOF_DSP_PM_D0:
/* Follow the sequence below for D0 substate transitions */
break;
case SOF_DSP_PM_D3:
/* Follow regular flow for D3 -> D0 transition */
return 0;
default:
dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
sdev->dsp_power_state.state, target_state->state);
return -EINVAL;
}
/* Set flags and register value for D0 target substate */
if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
value = SOF_HDA_VS_D0I3C_I3;
/*
* Trace DMA need to be disabled when the DSP enters
* D0I3 for S0Ix suspend, but it can be kept enabled
* when the DSP enters D0I3 while the system is in S0
* for debug purpose.
*/
if (!sdev->fw_trace_is_supported ||
!hda_enable_trace_D0I3_S0 ||
sdev->system_suspend_target != SOF_SUSPEND_NONE)
flags = HDA_PM_NO_DMA_TRACE;
if (hda_dsp_d0i3_streaming_applicable(sdev))
flags |= HDA_PM_PG_STREAMING;
} else {
/* prevent power gating in D0I0 */
flags = HDA_PM_PPG;
}
/* update D0I3C register */
ret = hda_dsp_update_d0i3c_register(sdev, value);
if (ret < 0)
return ret;
/*
* Notify the DSP of the state change.
* If this IPC fails, revert the D0I3C register update in order
* to prevent partial state change.
*/
ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
if (ret < 0) {
dev_err(sdev->dev,
"error: PM_GATE ipc error %d\n", ret);
goto revert;
}
return ret;
revert:
/* fallback to the previous register value */
value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
/*
* This can fail but return the IPC error to signal that
* the state change failed.
*/
hda_dsp_update_d0i3c_register(sdev, value);
return ret;
}
/* helper to log DSP state */
static void hda_dsp_state_log(struct snd_sof_dev *sdev)
{
switch (sdev->dsp_power_state.state) {
case SOF_DSP_PM_D0:
switch (sdev->dsp_power_state.substate) {
case SOF_HDA_DSP_PM_D0I0:
dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
break;
case SOF_HDA_DSP_PM_D0I3:
dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
break;
default:
dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
sdev->dsp_power_state.substate);
break;
}
break;
case SOF_DSP_PM_D1:
dev_dbg(sdev->dev, "Current DSP power state: D1\n");
break;
case SOF_DSP_PM_D2:
dev_dbg(sdev->dev, "Current DSP power state: D2\n");
break;
case SOF_DSP_PM_D3:
dev_dbg(sdev->dev, "Current DSP power state: D3\n");
break;
default:
dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
sdev->dsp_power_state.state);
break;
}
}
/*
* All DSP power state transitions are initiated by the driver.
* If the requested state change fails, the error is simply returned.
* Further state transitions are attempted only when the set_power_save() op
* is called again either because of a new IPC sent to the DSP or
* during system suspend/resume.
*/
static int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
int ret = 0;
switch (target_state->state) {
case SOF_DSP_PM_D0:
ret = hda_dsp_set_D0_state(sdev, target_state);
break;
case SOF_DSP_PM_D3:
/* The only allowed transition is: D0I0 -> D3 */
if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
break;
dev_err(sdev->dev,
"error: transition from %d to %d not allowed\n",
sdev->dsp_power_state.state, target_state->state);
return -EINVAL;
default:
dev_err(sdev->dev, "error: target state unsupported %d\n",
target_state->state);
return -EINVAL;
}
if (ret < 0) {
dev_err(sdev->dev,
"failed to set requested target DSP state %d substate %d\n",
target_state->state, target_state->substate);
return ret;
}
sdev->dsp_power_state = *target_state;
hda_dsp_state_log(sdev);
return ret;
}
int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
/*
* When the DSP is already in D0I3 and the target state is D0I3,
* it could be the case that the DSP is in D0I3 during S0
* and the system is suspending to S0Ix. Therefore,
* hda_dsp_set_D0_state() must be called to disable trace DMA
* by sending the PM_GATE IPC to the FW.
*/
if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
sdev->system_suspend_target == SOF_SUSPEND_S0IX)
return hda_dsp_set_power_state(sdev, target_state);
/*
* For all other cases, return without doing anything if
* the DSP is already in the target state.
*/
if (target_state->state == sdev->dsp_power_state.state &&
target_state->substate == sdev->dsp_power_state.substate)
return 0;
return hda_dsp_set_power_state(sdev, target_state);
}
int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
const struct sof_dsp_power_state *target_state)
{
/* Return without doing anything if the DSP is already in the target state */
if (target_state->state == sdev->dsp_power_state.state &&
target_state->substate == sdev->dsp_power_state.substate)
return 0;
return hda_dsp_set_power_state(sdev, target_state);
}
/*
* Audio DSP states may transform as below:-
*
* Opportunistic D0I3 in S0
* Runtime +---------------------+ Delayed D0i3 work timeout
* suspend | +--------------------+
* +------------+ D0I0(active) | |
* | | <---------------+ |
* | +--------> | New IPC | |
* | |Runtime +--^--+---------^--+--+ (via mailbox) | |
* | |resume | | | | | |
* | | | | | | | |
* | | System| | | | | |
* | | resume| | S3/S0IX | | | |
* | | | | suspend | | S0IX | |
* | | | | | |suspend | |
* | | | | | | | |
* | | | | | | | |
* +-v---+-----------+--v-------+ | | +------+----v----+
* | | | +-----------> |
* | D3 (suspended) | | | D0I3 |
* | | +--------------+ |
* | | System resume | |
* +----------------------------+ +----------------+
*
* S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
* ignored the suspend trigger. Otherwise the DSP
* is in D3.
*/
static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
struct hdac_bus *bus = sof_to_bus(sdev);
int ret, j;
/*
* The memory used for IMR boot loses its content in deeper than S3 state
* We must not try IMR boot on next power up (as it will fail).
*
* In case of firmware crash or boot failure set the skip_imr_boot to true
* as well in order to try to re-load the firmware to do a 'cold' boot.
*/
if (sdev->system_suspend_target > SOF_SUSPEND_S3 ||
sdev->fw_state == SOF_FW_CRASHED ||
sdev->fw_state == SOF_FW_BOOT_FAILED)
hda->skip_imr_boot = true;
ret = chip->disable_interrupts(sdev);
if (ret < 0)
return ret;
hda_codec_jack_wake_enable(sdev, runtime_suspend);
/* power down all hda links */
hda_bus_ml_suspend(bus);
if (sdev->dspless_mode_selected)
goto skip_dsp;
ret = chip->power_down_dsp(sdev);
if (ret < 0) {
dev_err(sdev->dev, "failed to power down DSP during suspend\n");
return ret;
}
/* reset ref counts for all cores */
for (j = 0; j < chip->cores_num; j++)
sdev->dsp_core_ref_count[j] = 0;
/* disable ppcap interrupt */
hda_dsp_ctrl_ppcap_enable(sdev, false);
hda_dsp_ctrl_ppcap_int_enable(sdev, false);
skip_dsp:
/* disable hda bus irq and streams */
hda_dsp_ctrl_stop_chip(sdev);
/* disable LP retention mode */
snd_sof_pci_update_bits(sdev, PCI_PGCTL,
PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
/* reset controller */
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to reset controller during suspend\n");
return ret;
}
/* display codec can powered off after link reset */
hda_codec_i915_display_power(sdev, false);
return 0;
}
static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
{
int ret;
/* display codec must be powered before link reset */
hda_codec_i915_display_power(sdev, true);
/*
* clear TCSEL to clear playback on some HD Audio
* codecs. PCI TCSEL is defined in the Intel manuals.
*/
snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
/* reset and start hda controller */
ret = hda_dsp_ctrl_init_chip(sdev);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to start controller after resume\n");
goto cleanup;
}
/* check jack status */
if (runtime_resume) {
hda_codec_jack_wake_enable(sdev, false);
if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
hda_codec_jack_check(sdev);
}
if (!sdev->dspless_mode_selected) {
/* enable ppcap interrupt */
hda_dsp_ctrl_ppcap_enable(sdev, true);
hda_dsp_ctrl_ppcap_int_enable(sdev, true);
}
cleanup:
/* display codec can powered off after controller init */
hda_codec_i915_display_power(sdev, false);
return 0;
}
int hda_dsp_resume(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct hdac_bus *bus = sof_to_bus(sdev);
struct pci_dev *pci = to_pci_dev(sdev->dev);
const struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D0,
.substate = SOF_HDA_DSP_PM_D0I0,
};
int ret;
/* resume from D0I3 */
if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
ret = hda_bus_ml_resume(bus);
if (ret < 0) {
dev_err(sdev->dev,
"error %d in %s: failed to power up links",
ret, __func__);
return ret;
}
/* set up CORB/RIRB buffers if was on before suspend */
hda_codec_resume_cmd_io(sdev);
/* Set DSP power state */
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
if (ret < 0) {
dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
target_state.state, target_state.substate);
return ret;
}
/* restore L1SEN bit */
if (hda->l1_disabled)
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
HDA_VS_INTEL_EM2,
HDA_VS_INTEL_EM2_L1SEN, 0);
/* restore and disable the system wakeup */
pci_restore_state(pci);
disable_irq_wake(pci->irq);
return 0;
}
/* init hda controller. DSP cores will be powered up during fw boot */
ret = hda_resume(sdev, false);
if (ret < 0)
return ret;
return snd_sof_dsp_set_power_state(sdev, &target_state);
}
int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
{
const struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D0,
};
int ret;
/* init hda controller. DSP cores will be powered up during fw boot */
ret = hda_resume(sdev, true);
if (ret < 0)
return ret;
return snd_sof_dsp_set_power_state(sdev, &target_state);
}
int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
{
struct hdac_bus *hbus = sof_to_bus(sdev);
if (hbus->codec_powered) {
dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
(unsigned int)hbus->codec_powered);
return -EBUSY;
}
return 0;
}
int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D3,
};
int ret;
if (!sdev->dspless_mode_selected) {
/* cancel any attempt for DSP D0I3 */
cancel_delayed_work_sync(&hda->d0i3_work);
}
/* stop hda controller and power dsp off */
ret = hda_suspend(sdev, true);
if (ret < 0)
return ret;
return snd_sof_dsp_set_power_state(sdev, &target_state);
}
int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct hdac_bus *bus = sof_to_bus(sdev);
struct pci_dev *pci = to_pci_dev(sdev->dev);
const struct sof_dsp_power_state target_dsp_state = {
.state = target_state,
.substate = target_state == SOF_DSP_PM_D0 ?
SOF_HDA_DSP_PM_D0I3 : 0,
};
int ret;
if (!sdev->dspless_mode_selected) {
/* cancel any attempt for DSP D0I3 */
cancel_delayed_work_sync(&hda->d0i3_work);
}
if (target_state == SOF_DSP_PM_D0) {
/* Set DSP power state */
ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
if (ret < 0) {
dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
target_dsp_state.state,
target_dsp_state.substate);
return ret;
}
/* enable L1SEN to make sure the system can enter S0Ix */
if (hda->l1_disabled)
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN);
/* stop the CORB/RIRB DMA if it is On */
hda_codec_suspend_cmd_io(sdev);
/* no link can be powered in s0ix state */
ret = hda_bus_ml_suspend(bus);
if (ret < 0) {
dev_err(sdev->dev,
"error %d in %s: failed to power down links",
ret, __func__);
return ret;
}
/* enable the system waking up via IPC IRQ */
enable_irq_wake(pci->irq);
pci_save_state(pci);
return 0;
}
/* stop hda controller and power dsp off */
ret = hda_suspend(sdev, false);
if (ret < 0) {
dev_err(bus->dev, "error: suspending dsp\n");
return ret;
}
return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
}
static unsigned int hda_dsp_check_for_dma_streams(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct hdac_stream *s;
unsigned int active_streams = 0;
int sd_offset;
u32 val;
list_for_each_entry(s, &bus->stream_list, list) {
sd_offset = SOF_STREAM_SD_OFFSET(s);
val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
sd_offset);
if (val & SOF_HDA_SD_CTL_DMA_START)
active_streams |= BIT(s->index);
}
return active_streams;
}
static int hda_dsp_s5_quirk(struct snd_sof_dev *sdev)
{
int ret;
/*
* Do not assume a certain timing between the prior
* suspend flow, and running of this quirk function.
* This is needed if the controller was just put
* to reset before calling this function.
*/
usleep_range(500, 1000);
/*
* Take controller out of reset to flush DMA
* transactions.
*/
ret = hda_dsp_ctrl_link_reset(sdev, false);
if (ret < 0)
return ret;
usleep_range(500, 1000);
/* Restore state for shutdown, back to reset */
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0)
return ret;
return ret;
}
int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev)
{
unsigned int active_streams;
int ret, ret2;
/* check if DMA cleanup has been successful */
active_streams = hda_dsp_check_for_dma_streams(sdev);
sdev->system_suspend_target = SOF_SUSPEND_S3;
ret = snd_sof_suspend(sdev->dev);
if (active_streams) {
dev_warn(sdev->dev,
"There were active DSP streams (%#x) at shutdown, trying to recover\n",
active_streams);
ret2 = hda_dsp_s5_quirk(sdev);
if (ret2 < 0)
dev_err(sdev->dev, "shutdown recovery failed (%d)\n", ret2);
}
return ret;
}
int hda_dsp_shutdown(struct snd_sof_dev *sdev)
{
sdev->system_suspend_target = SOF_SUSPEND_S3;
return snd_sof_suspend(sdev->dev);
}
int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
{
int ret;
/* make sure all DAI resources are freed */
ret = hda_dsp_dais_suspend(sdev);
if (ret < 0)
dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__);
return ret;
}
void hda_dsp_d0i3_work(struct work_struct *work)
{
struct sof_intel_hda_dev *hdev = container_of(work,
struct sof_intel_hda_dev,
d0i3_work.work);
struct hdac_bus *bus = &hdev->hbus.core;
struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
struct sof_dsp_power_state target_state = {
.state = SOF_DSP_PM_D0,
.substate = SOF_HDA_DSP_PM_D0I3,
};
int ret;
/* DSP can enter D0I3 iff only D0I3-compatible streams are active */
if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
/* remain in D0I0 */
return;
/* This can fail but error cannot be propagated */
ret = snd_sof_dsp_set_power_state(sdev, &target_state);
if (ret < 0)
dev_err_ratelimited(sdev->dev,
"error: failed to set DSP state %d substate %d\n",
target_state.state, target_state.substate);
}
int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
{
const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
int ret, ret1;
/* power up core */
ret = hda_dsp_enable_core(sdev, BIT(core));
if (ret < 0) {
dev_err(sdev->dev, "failed to power up core %d with err: %d\n",
core, ret);
return ret;
}
/* No need to send IPC for primary core or if FW boot is not complete */
if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE)
return 0;
/* No need to continue the set_core_state ops is not available */
if (!pm_ops->set_core_state)
return 0;
/* Now notify DSP for secondary cores */
ret = pm_ops->set_core_state(sdev, core, true);
if (ret < 0) {
dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n",
core, ret);
goto power_down;
}
return ret;
power_down:
/* power down core if it is host managed and return the original error if this fails too */
ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core));
if (ret1 < 0)
dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1);
return ret;
}
int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{
hda_sdw_int_enable(sdev, false);
hda_dsp_ipc_int_disable(sdev);
return 0;
}
| linux-master | sound/soc/sof/intel/hda-dsp.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2020 Intel Corporation. All rights reserved.
//
// Author: Fred Oh <[email protected]>
//
/*
* Hardware interface for audio DSP on IceLake.
*/
#include <linux/kernel.h>
#include <linux/kconfig.h>
#include <linux/export.h>
#include <linux/bits.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"
#define ICL_DSP_HPRO_CORE_ID 3
static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = {
{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
};
static int icl_dsp_core_stall(struct snd_sof_dev *sdev, unsigned int core_mask)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
/* make sure core_mask in host managed cores */
core_mask &= chip->host_managed_cores_mask;
if (!core_mask) {
dev_err(sdev->dev, "error: core_mask is not in host managed cores\n");
return -EINVAL;
}
/* stall core */
snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
return 0;
}
/*
* post fw run operation for ICL.
* Core 3 will be powered up and in stall when HPRO is enabled
*/
static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
int ret;
if (sdev->first_boot) {
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
ret = hda_sdw_startup(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: could not startup SoundWire links\n");
return ret;
}
/* Check if IMR boot is usable */
if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT)
hdev->imrboot_supported = true;
}
hda_sdw_int_enable(sdev, true);
/*
* The recommended HW programming sequence for ICL is to
* power up core 3 and keep it in stall if HPRO is enabled.
*/
if (!hda->clk_config_lpro) {
ret = hda_dsp_enable_core(sdev, BIT(ICL_DSP_HPRO_CORE_ID));
if (ret < 0) {
dev_err(sdev->dev, "error: dsp core power up failed on core %d\n",
ICL_DSP_HPRO_CORE_ID);
return ret;
}
sdev->enabled_cores_mask |= BIT(ICL_DSP_HPRO_CORE_ID);
sdev->dsp_core_ref_count[ICL_DSP_HPRO_CORE_ID]++;
snd_sof_dsp_stall(sdev, BIT(ICL_DSP_HPRO_CORE_ID));
}
/* re-enable clock gating and power gating */
return hda_dsp_ctrl_clock_power_gating(sdev, true);
}
/* Icelake ops */
struct snd_sof_dsp_ops sof_icl_ops;
EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
int sof_icl_ops_init(struct snd_sof_dev *sdev)
{
/* common defaults */
memcpy(&sof_icl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
/* probe/remove/shutdown */
sof_icl_ops.shutdown = hda_dsp_shutdown;
if (sdev->pdata->ipc_type == SOF_IPC) {
/* doorbell */
sof_icl_ops.irq_thread = cnl_ipc_irq_thread;
/* ipc */
sof_icl_ops.send_msg = cnl_ipc_send_msg;
/* debug */
sof_icl_ops.ipc_dump = cnl_ipc_dump;
sof_icl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
}
if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
struct sof_ipc4_fw_data *ipc4_data;
sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
if (!sdev->private)
return -ENOMEM;
ipc4_data = sdev->private;
ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
/* External library loading support */
ipc4_data->load_library = hda_dsp_ipc4_load_library;
/* doorbell */
sof_icl_ops.irq_thread = cnl_ipc4_irq_thread;
/* ipc */
sof_icl_ops.send_msg = cnl_ipc4_send_msg;
/* debug */
sof_icl_ops.ipc_dump = cnl_ipc4_dump;
sof_icl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
}
/* debug */
sof_icl_ops.debug_map = icl_dsp_debugfs;
sof_icl_ops.debug_map_count = ARRAY_SIZE(icl_dsp_debugfs);
/* pre/post fw run */
sof_icl_ops.post_fw_run = icl_dsp_post_fw_run;
/* firmware run */
sof_icl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
sof_icl_ops.stall = icl_dsp_core_stall;
/* dsp core get/put */
sof_icl_ops.core_get = hda_dsp_core_get;
/* set DAI driver ops */
hda_set_dai_drv_ops(sdev, &sof_icl_ops);
return 0;
};
EXPORT_SYMBOL_NS(sof_icl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc icl_chip_info = {
/* Icelake */
.cores_num = 4,
.init_core_mask = 1,
.host_managed_cores_mask = GENMASK(3, 0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
.rom_init_timeout = 300,
.ssp_count = ICL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE,
.d0i3_offset = SOF_HDA_VS_D0I3C,
.read_sdw_lcount = hda_sdw_check_lcount_common,
.enable_sdw_irq = hda_common_enable_sdw_irq,
.check_sdw_irq = hda_common_check_sdw_irq,
.check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
.check_ipc_irq = hda_dsp_check_ipc_irq,
.cl_init = cl_dsp_init,
.power_down_dsp = hda_power_down_dsp,
.disable_interrupts = hda_dsp_disable_interrupts,
.hw_ip_version = SOF_INTEL_CAVS_2_0,
};
EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
| linux-master | sound/soc/sof/intel/icl.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <[email protected]>
// Ranjani Sridharan <[email protected]>
// Rander Wang <[email protected]>
// Keyon Jie <[email protected]>
//
/*
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>
#include <sound/sof.h>
#include <trace/events/sof_intel.h>
#include "../ops.h"
#include "../sof-audio.h"
#include "hda.h"
#define HDA_LTRP_GB_VALUE_US 95
static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream)
{
if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
return "Playback";
else
return "Capture";
}
static char *hda_hstream_dbg_get_stream_info_str(struct hdac_stream *hstream)
{
struct snd_soc_pcm_runtime *rtd;
if (hstream->substream)
rtd = asoc_substream_to_rtd(hstream->substream);
else if (hstream->cstream)
rtd = hstream->cstream->private_data;
else
/* Non audio DMA user, like dma-trace */
return kasprintf(GFP_KERNEL, "-- (%s, stream_tag: %u)",
hda_hstream_direction_str(hstream),
hstream->stream_tag);
return kasprintf(GFP_KERNEL, "dai_link \"%s\" (%s, stream_tag: %u)",
rtd->dai_link->name, hda_hstream_direction_str(hstream),
hstream->stream_tag);
}
/*
* set up one of BDL entries for a stream
*/
static int hda_setup_bdle(struct snd_sof_dev *sdev,
struct snd_dma_buffer *dmab,
struct hdac_stream *hstream,
struct sof_intel_dsp_bdl **bdlp,
int offset, int size, int ioc)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct sof_intel_dsp_bdl *bdl = *bdlp;
while (size > 0) {
dma_addr_t addr;
int chunk;
if (hstream->frags >= HDA_DSP_MAX_BDL_ENTRIES) {
dev_err(sdev->dev, "error: stream frags exceeded\n");
return -EINVAL;
}
addr = snd_sgbuf_get_addr(dmab, offset);
/* program BDL addr */
bdl->addr_l = cpu_to_le32(lower_32_bits(addr));
bdl->addr_h = cpu_to_le32(upper_32_bits(addr));
/* program BDL size */
chunk = snd_sgbuf_get_chunk_size(dmab, offset, size);
/* one BDLE should not cross 4K boundary */
if (bus->align_bdle_4k) {
u32 remain = 0x1000 - (offset & 0xfff);
if (chunk > remain)
chunk = remain;
}
bdl->size = cpu_to_le32(chunk);
/* only program IOC when the whole segment is processed */
size -= chunk;
bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01);
bdl++;
hstream->frags++;
offset += chunk;
}
*bdlp = bdl;
return offset;
}
/*
* set up Buffer Descriptor List (BDL) for host memory transfer
* BDL describes the location of the individual buffers and is little endian.
*/
int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
struct snd_dma_buffer *dmab,
struct hdac_stream *hstream)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct sof_intel_dsp_bdl *bdl;
int i, offset, period_bytes, periods;
int remain, ioc;
period_bytes = hstream->period_bytes;
dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
if (!period_bytes)
period_bytes = hstream->bufsize;
periods = hstream->bufsize / period_bytes;
dev_dbg(sdev->dev, "periods:%d\n", periods);
remain = hstream->bufsize % period_bytes;
if (remain)
periods++;
/* program the initial BDL entries */
bdl = (struct sof_intel_dsp_bdl *)hstream->bdl.area;
offset = 0;
hstream->frags = 0;
/*
* set IOC if don't use position IPC
* and period_wakeup needed.
*/
ioc = hda->no_ipc_position ?
!hstream->no_period_wakeup : 0;
for (i = 0; i < periods; i++) {
if (i == (periods - 1) && remain)
/* set the last small entry */
offset = hda_setup_bdle(sdev, dmab,
hstream, &bdl, offset,
remain, 0);
else
offset = hda_setup_bdle(sdev, dmab,
hstream, &bdl, offset,
period_bytes, ioc);
}
return offset;
}
int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
struct hdac_ext_stream *hext_stream,
int enable, u32 size)
{
struct hdac_stream *hstream = &hext_stream->hstream;
u32 mask;
if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
dev_err(sdev->dev, "error: address of spib capability is NULL\n");
return -EINVAL;
}
mask = (1 << hstream->index);
/* enable/disable SPIB for the stream */
snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask,
enable << hstream->index);
/* set the SPIB value */
sof_io_write(sdev, hstream->spib_addr, size);
return 0;
}
/* get next unused stream */
struct hdac_ext_stream *
hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags)
{
const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct hdac_bus *bus = sof_to_bus(sdev);
struct sof_intel_hda_stream *hda_stream;
struct hdac_ext_stream *hext_stream = NULL;
struct hdac_stream *s;
spin_lock_irq(&bus->reg_lock);
/* get an unused stream */
list_for_each_entry(s, &bus->stream_list, list) {
if (s->direction == direction && !s->opened) {
hext_stream = stream_to_hdac_ext_stream(s);
hda_stream = container_of(hext_stream,
struct sof_intel_hda_stream,
hext_stream);
/* check if the host DMA channel is reserved */
if (hda_stream->host_reserved)
continue;
s->opened = true;
break;
}
}
spin_unlock_irq(&bus->reg_lock);
/* stream found ? */
if (!hext_stream) {
dev_err(sdev->dev, "error: no free %s streams\n",
direction == SNDRV_PCM_STREAM_PLAYBACK ?
"playback" : "capture");
return hext_stream;
}
hda_stream->flags = flags;
/*
* Prevent DMI Link L1 entry for streams that don't support it.
* Workaround to address a known issue with host DMA that results
* in xruns during pause/release in capture scenarios. This is not needed for the ACE IP.
*/
if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 &&
!(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) {
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
HDA_VS_INTEL_EM2,
HDA_VS_INTEL_EM2_L1SEN, 0);
hda->l1_disabled = true;
}
return hext_stream;
}
/* free a stream */
int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag)
{
const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct hdac_bus *bus = sof_to_bus(sdev);
struct sof_intel_hda_stream *hda_stream;
struct hdac_ext_stream *hext_stream;
struct hdac_stream *s;
bool dmi_l1_enable = true;
bool found = false;
spin_lock_irq(&bus->reg_lock);
/*
* close stream matching the stream tag and check if there are any open streams
* that are DMI L1 incompatible.
*/
list_for_each_entry(s, &bus->stream_list, list) {
hext_stream = stream_to_hdac_ext_stream(s);
hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, hext_stream);
if (!s->opened)
continue;
if (s->direction == direction && s->stream_tag == stream_tag) {
s->opened = false;
found = true;
} else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) {
dmi_l1_enable = false;
}
}
spin_unlock_irq(&bus->reg_lock);
/* Enable DMI L1 if permitted */
if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && dmi_l1_enable) {
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN);
hda->l1_disabled = false;
}
if (!found) {
dev_err(sdev->dev, "%s: stream_tag %d not opened!\n",
__func__, stream_tag);
return -ENODEV;
}
return 0;
}
static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream)
{
int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
int timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
u32 val;
/* enter stream reset */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST,
SOF_STREAM_SD_OFFSET_CRST);
do {
val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
if (val & SOF_STREAM_SD_OFFSET_CRST)
break;
} while (--timeout);
if (timeout == 0) {
dev_err(sdev->dev, "timeout waiting for stream reset\n");
return -ETIMEDOUT;
}
timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
/* exit stream reset and wait to read a zero before reading any other register */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0);
/* wait for hardware to report that stream is out of reset */
udelay(3);
do {
val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
if ((val & SOF_STREAM_SD_OFFSET_CRST) == 0)
break;
} while (--timeout);
if (timeout == 0) {
dev_err(sdev->dev, "timeout waiting for stream to exit reset\n");
return -ETIMEDOUT;
}
return 0;
}
int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
struct hdac_ext_stream *hext_stream, int cmd)
{
struct hdac_stream *hstream = &hext_stream->hstream;
int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
int ret = 0;
u32 run;
/* cmd must be for audio stream */
switch (cmd) {
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (!sdev->dspless_mode_selected)
break;
fallthrough;
case SNDRV_PCM_TRIGGER_START:
if (hstream->running)
break;
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
1 << hstream->index,
1 << hstream->index);
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset,
SOF_HDA_SD_CTL_DMA_START |
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_SD_CTL_DMA_START |
SOF_HDA_CL_DMA_SD_INT_MASK);
ret = snd_sof_dsp_read_poll_timeout(sdev,
HDA_DSP_HDA_BAR,
sd_offset, run,
((run & dma_start) == dma_start),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_STREAM_RUN_TIMEOUT);
if (ret >= 0)
hstream->running = true;
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (!sdev->dspless_mode_selected)
break;
fallthrough;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset,
SOF_HDA_SD_CTL_DMA_START |
SOF_HDA_CL_DMA_SD_INT_MASK, 0x0);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
sd_offset, run,
!(run & dma_start),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_STREAM_RUN_TIMEOUT);
if (ret >= 0) {
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK);
hstream->running = false;
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
SOF_HDA_INTCTL,
1 << hstream->index, 0x0);
}
break;
default:
dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
return -EINVAL;
}
if (ret < 0) {
char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
dev_err(sdev->dev,
"%s: cmd %d on %s: timeout on STREAM_SD_OFFSET read\n",
__func__, cmd, stream_name ? stream_name : "unknown stream");
kfree(stream_name);
}
return ret;
}
/* minimal recommended programming for ICCMAX stream */
int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
struct snd_dma_buffer *dmab,
struct snd_pcm_hw_params *params)
{
struct hdac_stream *hstream = &hext_stream->hstream;
int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
int ret;
u32 mask = 0x1 << hstream->index;
if (!hext_stream) {
dev_err(sdev->dev, "error: no stream available\n");
return -ENODEV;
}
if (!dmab) {
dev_err(sdev->dev, "error: no dma buffer allocated!\n");
return -ENODEV;
}
if (hstream->posbuf)
*hstream->posbuf = 0;
/* reset BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
0x0);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
0x0);
hstream->frags = 0;
ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
if (ret < 0) {
dev_err(sdev->dev, "error: set up of BDL failed\n");
return ret;
}
/* program BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
(u32)hstream->bdl.addr);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
upper_32_bits(hstream->bdl.addr));
/* program cyclic buffer length */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
hstream->bufsize);
/* program last valid index */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
0xffff, (hstream->frags - 1));
/* decouple host and link DMA, enable DSP features */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
mask, mask);
/* Follow HW recommendation to set the guardband value to 95us during FW boot */
snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP,
HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
/* start DMA */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START);
return 0;
}
/*
* prepare for common hdac registers settings, for both code loader
* and normal stream.
*/
int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
struct hdac_ext_stream *hext_stream,
struct snd_dma_buffer *dmab,
struct snd_pcm_hw_params *params)
{
const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
struct hdac_bus *bus = sof_to_bus(sdev);
struct hdac_stream *hstream;
int sd_offset, ret;
u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
u32 mask;
u32 run;
if (!hext_stream) {
dev_err(sdev->dev, "error: no stream available\n");
return -ENODEV;
}
if (!dmab) {
dev_err(sdev->dev, "error: no dma buffer allocated!\n");
return -ENODEV;
}
hstream = &hext_stream->hstream;
sd_offset = SOF_STREAM_SD_OFFSET(hstream);
mask = BIT(hstream->index);
/* decouple host and link DMA if the DSP is used */
if (!sdev->dspless_mode_selected)
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
mask, mask);
/* clear stream status */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
SOF_HDA_CL_DMA_SD_INT_MASK |
SOF_HDA_SD_CTL_DMA_START, 0);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
sd_offset, run,
!(run & dma_start),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_STREAM_RUN_TIMEOUT);
if (ret < 0) {
char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
dev_err(sdev->dev,
"%s: on %s: timeout on STREAM_SD_OFFSET read1\n",
__func__, stream_name ? stream_name : "unknown stream");
kfree(stream_name);
return ret;
}
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_CL_DMA_SD_INT_MASK);
/* stream reset */
ret = hda_dsp_stream_reset(sdev, hstream);
if (ret < 0)
return ret;
if (hstream->posbuf)
*hstream->posbuf = 0;
/* reset BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
0x0);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
0x0);
/* clear stream status */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
SOF_HDA_CL_DMA_SD_INT_MASK |
SOF_HDA_SD_CTL_DMA_START, 0);
ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
sd_offset, run,
!(run & dma_start),
HDA_DSP_REG_POLL_INTERVAL_US,
HDA_DSP_STREAM_RUN_TIMEOUT);
if (ret < 0) {
char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
dev_err(sdev->dev,
"%s: on %s: timeout on STREAM_SD_OFFSET read1\n",
__func__, stream_name ? stream_name : "unknown stream");
kfree(stream_name);
return ret;
}
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_CL_DMA_SD_INT_MASK);
hstream->frags = 0;
ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
if (ret < 0) {
dev_err(sdev->dev, "error: set up of BDL failed\n");
return ret;
}
/* program stream tag to set up stream descriptor for DMA */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK,
hstream->stream_tag <<
SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT);
/* program cyclic buffer length */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
hstream->bufsize);
/*
* Recommended hardware programming sequence for HDAudio DMA format
* on earlier platforms - this is not needed on newer platforms
*
* 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit
* for corresponding stream index before the time of writing
* format to SDxFMT register.
* 2. Write SDxFMT
* 3. Set PPCTL.PROCEN bit for corresponding stream index to
* enable decoupled mode
*/
if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK))
/* couple host and link DMA, disable DSP features */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
mask, 0);
/* program stream format */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset +
SOF_HDA_ADSP_REG_SD_FORMAT,
0xffff, hstream->format_val);
if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK))
/* decouple host and link DMA, enable DSP features */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
mask, mask);
/* program last valid index */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
0xffff, (hstream->frags - 1));
/* program BDL address */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
(u32)hstream->bdl.addr);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
upper_32_bits(hstream->bdl.addr));
/* enable position buffer, if needed */
if (bus->use_posbuf && bus->posbuf.addr &&
!(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
& SOF_HDA_ADSP_DPLBASE_ENABLE)) {
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
upper_32_bits(bus->posbuf.addr));
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
(u32)bus->posbuf.addr |
SOF_HDA_ADSP_DPLBASE_ENABLE);
}
/* set interrupt enable bits */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_CL_DMA_SD_INT_MASK);
/* read FIFO size */
if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) {
hstream->fifo_size =
snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
sd_offset +
SOF_HDA_ADSP_REG_SD_FIFOSIZE);
hstream->fifo_size &= 0xffff;
hstream->fifo_size += 1;
} else {
hstream->fifo_size = 0;
}
return ret;
}
int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
struct hdac_stream *hstream = substream->runtime->private_data;
struct hdac_ext_stream *hext_stream = container_of(hstream,
struct hdac_ext_stream,
hstream);
int ret;
ret = hda_dsp_stream_reset(sdev, hstream);
if (ret < 0)
return ret;
if (!sdev->dspless_mode_selected) {
struct hdac_bus *bus = sof_to_bus(sdev);
u32 mask = BIT(hstream->index);
spin_lock_irq(&bus->reg_lock);
/* couple host and link DMA if link DMA channel is idle */
if (!hext_stream->link_locked)
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
SOF_HDA_REG_PP_PPCTL, mask, 0);
spin_unlock_irq(&bus->reg_lock);
}
hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
hstream->substream = NULL;
return 0;
}
bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
bool ret = false;
u32 status;
/* The function can be called at irq thread, so use spin_lock_irq */
spin_lock_irq(&bus->reg_lock);
status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
trace_sof_intel_hda_dsp_check_stream_irq(sdev, status);
/* if Register inaccessible, ignore it.*/
if (status != 0xffffffff)
ret = true;
spin_unlock_irq(&bus->reg_lock);
return ret;
}
static void
hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction)
{
u64 buffer_size = hstream->bufsize;
u64 prev_pos, pos, num_bytes;
div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos);
pos = hda_dsp_stream_get_position(hstream, direction, false);
if (pos < prev_pos)
num_bytes = (buffer_size - prev_pos) + pos;
else
num_bytes = pos - prev_pos;
hstream->curr_pos += num_bytes;
}
static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
{
struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
struct hdac_stream *s;
bool active = false;
u32 sd_status;
list_for_each_entry(s, &bus->stream_list, list) {
if (status & BIT(s->index) && s->opened) {
sd_status = readb(s->sd_addr + SOF_HDA_ADSP_REG_SD_STS);
trace_sof_intel_hda_dsp_stream_status(bus->dev, s, sd_status);
writeb(sd_status, s->sd_addr + SOF_HDA_ADSP_REG_SD_STS);
active = true;
if ((!s->substream && !s->cstream) ||
!s->running ||
(sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0)
continue;
/* Inform ALSA only in case not do that with IPC */
if (s->substream && sof_hda->no_ipc_position) {
snd_sof_pcm_period_elapsed(s->substream);
} else if (s->cstream) {
hda_dsp_compr_bytes_transferred(s, s->cstream->direction);
snd_compr_fragment_elapsed(s->cstream);
}
}
}
return active;
}
irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
struct hdac_bus *bus = sof_to_bus(sdev);
bool active;
u32 status;
int i;
/*
* Loop 10 times to handle missed interrupts caused by
* unsolicited responses from the codec
*/
for (i = 0, active = true; i < 10 && active; i++) {
spin_lock_irq(&bus->reg_lock);
status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
/* check streams */
active = hda_dsp_stream_check(bus, status);
/* check and clear RIRB interrupt */
if (status & AZX_INT_CTRL_EN) {
active |= hda_codec_check_rirb_status(sdev);
}
spin_unlock_irq(&bus->reg_lock);
}
return IRQ_HANDLED;
}
int hda_dsp_stream_init(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct hdac_ext_stream *hext_stream;
struct hdac_stream *hstream;
struct pci_dev *pci = to_pci_dev(sdev->dev);
struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
int sd_offset;
int i, num_playback, num_capture, num_total, ret;
u32 gcap;
gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
/* get stream count from GCAP */
num_capture = (gcap >> 8) & 0x0f;
num_playback = (gcap >> 12) & 0x0f;
num_total = num_playback + num_capture;
dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
num_playback, num_capture);
if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) {
dev_err(sdev->dev, "error: too many playback streams %d\n",
num_playback);
return -EINVAL;
}
if (num_capture >= SOF_HDA_CAPTURE_STREAMS) {
dev_err(sdev->dev, "error: too many capture streams %d\n",
num_playback);
return -EINVAL;
}
/*
* mem alloc for the position buffer
* TODO: check position buffer update
*/
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
SOF_HDA_DPIB_ENTRY_SIZE * num_total,
&bus->posbuf);
if (ret < 0) {
dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
return -ENOMEM;
}
/*
* mem alloc for the CORB/RIRB ringbuffers - this will be used only for
* HDAudio codecs
*/
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
PAGE_SIZE, &bus->rb);
if (ret < 0) {
dev_err(sdev->dev, "error: RB alloc failed\n");
return -ENOMEM;
}
/* create capture and playback streams */
for (i = 0; i < num_total; i++) {
struct sof_intel_hda_stream *hda_stream;
hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
GFP_KERNEL);
if (!hda_stream)
return -ENOMEM;
hda_stream->sdev = sdev;
hext_stream = &hda_stream->hext_stream;
if (sdev->bar[HDA_DSP_PP_BAR]) {
hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
SOF_HDA_PPLC_INTERVAL * i;
}
hstream = &hext_stream->hstream;
/* do we support SPIB */
if (sdev->bar[HDA_DSP_SPIB_BAR]) {
hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
SOF_HDA_SPIB_SPIB;
hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
SOF_HDA_SPIB_MAXFIFO;
}
hstream->bus = bus;
hstream->sd_int_sta_mask = 1 << i;
hstream->index = i;
sd_offset = SOF_STREAM_SD_OFFSET(hstream);
hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
hstream->opened = false;
hstream->running = false;
if (i < num_capture) {
hstream->stream_tag = i + 1;
hstream->direction = SNDRV_PCM_STREAM_CAPTURE;
} else {
hstream->stream_tag = i - num_capture + 1;
hstream->direction = SNDRV_PCM_STREAM_PLAYBACK;
}
/* mem alloc for stream BDL */
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
HDA_DSP_BDL_SIZE, &hstream->bdl);
if (ret < 0) {
dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
return -ENOMEM;
}
hstream->posbuf = (__le32 *)(bus->posbuf.area +
(hstream->index) * 8);
list_add_tail(&hstream->list, &bus->stream_list);
}
/* store total stream count (playback + capture) from GCAP */
sof_hda->stream_max = num_total;
return 0;
}
void hda_dsp_stream_free(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct hdac_stream *s, *_s;
struct hdac_ext_stream *hext_stream;
struct sof_intel_hda_stream *hda_stream;
/* free position buffer */
if (bus->posbuf.area)
snd_dma_free_pages(&bus->posbuf);
/* free CORB/RIRB buffer - only used for HDaudio codecs */
if (bus->rb.area)
snd_dma_free_pages(&bus->rb);
list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
/* TODO: decouple */
/* free bdl buffer */
if (s->bdl.area)
snd_dma_free_pages(&s->bdl);
list_del(&s->list);
hext_stream = stream_to_hdac_ext_stream(s);
hda_stream = container_of(hext_stream, struct sof_intel_hda_stream,
hext_stream);
devm_kfree(sdev->dev, hda_stream);
}
}
snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
int direction, bool can_sleep)
{
struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream);
struct snd_sof_dev *sdev = hda_stream->sdev;
snd_pcm_uframes_t pos;
switch (sof_hda_position_quirk) {
case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
/*
* This legacy code, inherited from the Skylake driver,
* mixes DPIB registers and DPIB DDR updates and
* does not seem to follow any known hardware recommendations.
* It's not clear e.g. why there is a different flow
* for capture and playback, the only information that matters is
* what traffic class is used, and on all SOF-enabled platforms
* only VC0 is supported so the work-around was likely not necessary
* and quite possibly wrong.
*/
/* DPIB/posbuf position mode:
* For Playback, Use DPIB register from HDA space which
* reflects the actual data transferred.
* For Capture, Use the position buffer for pointer, as DPIB
* is not accurate enough, its update may be completed
* earlier than the data written to DDR.
*/
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
AZX_REG_VS_SDXDPIB_XBASE +
(AZX_REG_VS_SDXDPIB_XINTERVAL *
hstream->index));
} else {
/*
* For capture stream, we need more workaround to fix the
* position incorrect issue:
*
* 1. Wait at least 20us before reading position buffer after
* the interrupt generated(IOC), to make sure position update
* happens on frame boundary i.e. 20.833uSec for 48KHz.
* 2. Perform a dummy Read to DPIB register to flush DMA
* position value.
* 3. Read the DMA Position from posbuf. Now the readback
* value should be >= period boundary.
*/
if (can_sleep)
usleep_range(20, 21);
snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
AZX_REG_VS_SDXDPIB_XBASE +
(AZX_REG_VS_SDXDPIB_XINTERVAL *
hstream->index));
pos = snd_hdac_stream_get_pos_posbuf(hstream);
}
break;
case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
/*
* In case VC1 traffic is disabled this is the recommended option
*/
pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
AZX_REG_VS_SDXDPIB_XBASE +
(AZX_REG_VS_SDXDPIB_XINTERVAL *
hstream->index));
break;
case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
/*
* This is the recommended option when VC1 is enabled.
* While this isn't needed for SOF platforms it's added for
* consistency and debug.
*/
pos = snd_hdac_stream_get_pos_posbuf(hstream);
break;
default:
dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
sof_hda_position_quirk);
pos = 0;
break;
}
if (pos >= hstream->bufsize)
pos = 0;
return pos;
}
| linux-master | sound/soc/sof/intel/hda-stream.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2022 Intel Corporation. All rights reserved.
//
/*
* Management of HDaudio multi-link (capabilities, power, coupling)
*/
#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>
#include <sound/hda-mlink.h>
#include <linux/bitfield.h>
#include <linux/module.h>
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_MLINK)
/* worst-case number of sublinks is used for sublink refcount array allocation only */
#define HDAML_MAX_SUBLINKS (AZX_ML_LCTL_CPA_SHIFT - AZX_ML_LCTL_SPA_SHIFT)
/**
* struct hdac_ext2_link - HDAudio extended+alternate link
*
* @hext_link: hdac_ext_link
* @alt: flag set for alternate extended links
* @intc: boolean for interrupt capable
* @ofls: boolean for offload support
* @lss: boolean for link synchronization capabilities
* @slcount: sublink count
* @elid: extended link ID (AZX_REG_ML_LEPTR_ID_ defines)
* @elver: extended link version
* @leptr: extended link pointer
* @eml_lock: mutual exclusion to access shared registers e.g. CPA/SPA bits
* in LCTL register
* @sublink_ref_count: array of refcounts, required to power-manage sublinks independently
* @base_ptr: pointer to shim/ip/shim_vs space
* @instance_offset: offset between each of @slcount instances managed by link
* @shim_offset: offset to SHIM register base
* @ip_offset: offset to IP register base
* @shim_vs_offset: offset to vendor-specific (VS) SHIM base
*/
struct hdac_ext2_link {
struct hdac_ext_link hext_link;
/* read directly from LCAP register */
bool alt;
bool intc;
bool ofls;
bool lss;
int slcount;
int elid;
int elver;
u32 leptr;
struct mutex eml_lock; /* prevent concurrent access to e.g. CPA/SPA */
int sublink_ref_count[HDAML_MAX_SUBLINKS];
/* internal values computed from LCAP contents */
void __iomem *base_ptr;
u32 instance_offset;
u32 shim_offset;
u32 ip_offset;
u32 shim_vs_offset;
};
#define hdac_ext_link_to_ext2(h) container_of(h, struct hdac_ext2_link, hext_link)
#define AZX_REG_SDW_INSTANCE_OFFSET 0x8000
#define AZX_REG_SDW_SHIM_OFFSET 0x0
#define AZX_REG_SDW_IP_OFFSET 0x100
#define AZX_REG_SDW_VS_SHIM_OFFSET 0x6000
#define AZX_REG_SDW_SHIM_PCMSyCM(y) (0x16 + 0x4 * (y))
/* only one instance supported */
#define AZX_REG_INTEL_DMIC_SHIM_OFFSET 0x0
#define AZX_REG_INTEL_DMIC_IP_OFFSET 0x100
#define AZX_REG_INTEL_DMIC_VS_SHIM_OFFSET 0x6000
#define AZX_REG_INTEL_SSP_INSTANCE_OFFSET 0x1000
#define AZX_REG_INTEL_SSP_SHIM_OFFSET 0x0
#define AZX_REG_INTEL_SSP_IP_OFFSET 0x100
#define AZX_REG_INTEL_SSP_VS_SHIM_OFFSET 0xC00
/* only one instance supported */
#define AZX_REG_INTEL_UAOL_SHIM_OFFSET 0x0
#define AZX_REG_INTEL_UAOL_IP_OFFSET 0x100
#define AZX_REG_INTEL_UAOL_VS_SHIM_OFFSET 0xC00
/* HDAML section - this part follows sequences in the hardware specification,
* including naming conventions and the use of the hdaml_ prefix.
* The code is intentionally minimal with limited dependencies on frameworks or
* helpers. Locking and scanning lists is handled at a higher level
*/
static int hdaml_lnk_enum(struct device *dev, struct hdac_ext2_link *h2link,
void __iomem *remap_addr, void __iomem *ml_addr, int link_idx)
{
struct hdac_ext_link *hlink = &h2link->hext_link;
u32 base_offset;
hlink->lcaps = readl(ml_addr + AZX_REG_ML_LCAP);
h2link->alt = FIELD_GET(AZX_ML_HDA_LCAP_ALT, hlink->lcaps);
/* handle alternate extensions */
if (!h2link->alt) {
h2link->slcount = 1;
/*
* LSDIID is initialized by hardware for HDaudio link,
* it needs to be setup by software for alternate links
*/
hlink->lsdiid = readw(ml_addr + AZX_REG_ML_LSDIID);
dev_dbg(dev, "Link %d: HDAudio - lsdiid=%d\n",
link_idx, hlink->lsdiid);
return 0;
}
h2link->intc = FIELD_GET(AZX_ML_HDA_LCAP_INTC, hlink->lcaps);
h2link->ofls = FIELD_GET(AZX_ML_HDA_LCAP_OFLS, hlink->lcaps);
h2link->lss = FIELD_GET(AZX_ML_HDA_LCAP_LSS, hlink->lcaps);
/* read slcount (increment due to zero-based hardware representation */
h2link->slcount = FIELD_GET(AZX_ML_HDA_LCAP_SLCOUNT, hlink->lcaps) + 1;
dev_dbg(dev, "Link %d: HDAudio extended - sublink count %d\n",
link_idx, h2link->slcount);
/* find IP ID and offsets */
h2link->leptr = readl(ml_addr + AZX_REG_ML_LEPTR);
h2link->elid = FIELD_GET(AZX_REG_ML_LEPTR_ID, h2link->leptr);
base_offset = FIELD_GET(AZX_REG_ML_LEPTR_PTR, h2link->leptr);
h2link->base_ptr = remap_addr + base_offset;
switch (h2link->elid) {
case AZX_REG_ML_LEPTR_ID_SDW:
h2link->instance_offset = AZX_REG_SDW_INSTANCE_OFFSET;
h2link->shim_offset = AZX_REG_SDW_SHIM_OFFSET;
h2link->ip_offset = AZX_REG_SDW_IP_OFFSET;
h2link->shim_vs_offset = AZX_REG_SDW_VS_SHIM_OFFSET;
dev_dbg(dev, "Link %d: HDAudio extended - SoundWire alternate link, leptr.ptr %#x\n",
link_idx, base_offset);
break;
case AZX_REG_ML_LEPTR_ID_INTEL_DMIC:
h2link->shim_offset = AZX_REG_INTEL_DMIC_SHIM_OFFSET;
h2link->ip_offset = AZX_REG_INTEL_DMIC_IP_OFFSET;
h2link->shim_vs_offset = AZX_REG_INTEL_DMIC_VS_SHIM_OFFSET;
dev_dbg(dev, "Link %d: HDAudio extended - INTEL DMIC alternate link, leptr.ptr %#x\n",
link_idx, base_offset);
break;
case AZX_REG_ML_LEPTR_ID_INTEL_SSP:
h2link->instance_offset = AZX_REG_INTEL_SSP_INSTANCE_OFFSET;
h2link->shim_offset = AZX_REG_INTEL_SSP_SHIM_OFFSET;
h2link->ip_offset = AZX_REG_INTEL_SSP_IP_OFFSET;
h2link->shim_vs_offset = AZX_REG_INTEL_SSP_VS_SHIM_OFFSET;
dev_dbg(dev, "Link %d: HDAudio extended - INTEL SSP alternate link, leptr.ptr %#x\n",
link_idx, base_offset);
break;
case AZX_REG_ML_LEPTR_ID_INTEL_UAOL:
h2link->shim_offset = AZX_REG_INTEL_UAOL_SHIM_OFFSET;
h2link->ip_offset = AZX_REG_INTEL_UAOL_IP_OFFSET;
h2link->shim_vs_offset = AZX_REG_INTEL_UAOL_VS_SHIM_OFFSET;
dev_dbg(dev, "Link %d: HDAudio extended - INTEL UAOL alternate link, leptr.ptr %#x\n",
link_idx, base_offset);
break;
default:
dev_err(dev, "Link %d: HDAudio extended - Unsupported alternate link, leptr.id=%#02x value\n",
link_idx, h2link->elid);
return -EINVAL;
}
return 0;
}
/*
* Hardware recommendations are to wait ~10us before checking any hardware transition
* reported by bits changing status.
* This value does not need to be super-precise, a slack of 5us is perfectly acceptable.
* The worst-case is about 1ms before reporting an issue
*/
#define HDAML_POLL_DELAY_MIN_US 10
#define HDAML_POLL_DELAY_SLACK_US 5
#define HDAML_POLL_DELAY_RETRY 100
static int check_sublink_power(u32 __iomem *lctl, int sublink, bool enabled)
{
int mask = BIT(sublink) << AZX_ML_LCTL_CPA_SHIFT;
int retry = HDAML_POLL_DELAY_RETRY;
u32 val;
usleep_range(HDAML_POLL_DELAY_MIN_US,
HDAML_POLL_DELAY_MIN_US + HDAML_POLL_DELAY_SLACK_US);
do {
val = readl(lctl);
if (enabled) {
if (val & mask)
return 0;
} else {
if (!(val & mask))
return 0;
}
usleep_range(HDAML_POLL_DELAY_MIN_US,
HDAML_POLL_DELAY_MIN_US + HDAML_POLL_DELAY_SLACK_US);
} while (--retry);
return -EIO;
}
static int hdaml_link_init(u32 __iomem *lctl, int sublink)
{
u32 val;
u32 mask = BIT(sublink) << AZX_ML_LCTL_SPA_SHIFT;
val = readl(lctl);
val |= mask;
writel(val, lctl);
return check_sublink_power(lctl, sublink, true);
}
static int hdaml_link_shutdown(u32 __iomem *lctl, int sublink)
{
u32 val;
u32 mask;
val = readl(lctl);
mask = BIT(sublink) << AZX_ML_LCTL_SPA_SHIFT;
val &= ~mask;
writel(val, lctl);
return check_sublink_power(lctl, sublink, false);
}
static void hdaml_link_enable_interrupt(u32 __iomem *lctl, bool enable)
{
u32 val;
val = readl(lctl);
if (enable)
val |= AZX_ML_LCTL_INTEN;
else
val &= ~AZX_ML_LCTL_INTEN;
writel(val, lctl);
}
static bool hdaml_link_check_interrupt(u32 __iomem *lctl)
{
u32 val;
val = readl(lctl);
return val & AZX_ML_LCTL_INTSTS;
}
static int hdaml_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
{
int timeout = HDAML_POLL_DELAY_RETRY;
u32 reg_read;
do {
reg_read = readl(base + offset);
if ((reg_read & mask) == target)
return 0;
timeout--;
usleep_range(HDAML_POLL_DELAY_MIN_US,
HDAML_POLL_DELAY_MIN_US + HDAML_POLL_DELAY_SLACK_US);
} while (timeout != 0);
return -EAGAIN;
}
static void hdaml_link_set_syncprd(u32 __iomem *lsync, u32 syncprd)
{
u32 val;
val = readl(lsync);
val &= ~AZX_REG_ML_LSYNC_SYNCPRD;
val |= (syncprd & AZX_REG_ML_LSYNC_SYNCPRD);
/*
* set SYNCPU but do not wait. The bit is cleared by hardware when
* the link becomes active.
*/
val |= AZX_REG_ML_LSYNC_SYNCPU;
writel(val, lsync);
}
static int hdaml_link_wait_syncpu(u32 __iomem *lsync)
{
return hdaml_wait_bit(lsync, 0, AZX_REG_ML_LSYNC_SYNCPU, 0);
}
static void hdaml_link_sync_arm(u32 __iomem *lsync, int sublink)
{
u32 val;
val = readl(lsync);
val |= (AZX_REG_ML_LSYNC_CMDSYNC << sublink);
writel(val, lsync);
}
static void hdaml_link_sync_go(u32 __iomem *lsync)
{
u32 val;
val = readl(lsync);
val |= AZX_REG_ML_LSYNC_SYNCGO;
writel(val, lsync);
}
static bool hdaml_link_check_cmdsync(u32 __iomem *lsync, u32 cmdsync_mask)
{
u32 val;
val = readl(lsync);
return !!(val & cmdsync_mask);
}
static u16 hdaml_link_get_lsdiid(u16 __iomem *lsdiid)
{
return readw(lsdiid);
}
static void hdaml_link_set_lsdiid(u16 __iomem *lsdiid, int dev_num)
{
u16 val;
val = readw(lsdiid);
val |= BIT(dev_num);
writew(val, lsdiid);
}
static void hdaml_shim_map_stream_ch(u16 __iomem *pcmsycm, int lchan, int hchan,
int stream_id, int dir)
{
u16 val;
val = readw(pcmsycm);
u16p_replace_bits(&val, lchan, GENMASK(3, 0));
u16p_replace_bits(&val, hchan, GENMASK(7, 4));
u16p_replace_bits(&val, stream_id, GENMASK(13, 8));
u16p_replace_bits(&val, dir, BIT(15));
writew(val, pcmsycm);
}
static void hdaml_lctl_offload_enable(u32 __iomem *lctl, bool enable)
{
u32 val = readl(lctl);
if (enable)
val |= AZX_ML_LCTL_OFLEN;
else
val &= ~AZX_ML_LCTL_OFLEN;
writel(val, lctl);
}
/* END HDAML section */
static int hda_ml_alloc_h2link(struct hdac_bus *bus, int index)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
int ret;
h2link = kzalloc(sizeof(*h2link), GFP_KERNEL);
if (!h2link)
return -ENOMEM;
/* basic initialization */
hlink = &h2link->hext_link;
hlink->index = index;
hlink->bus = bus;
hlink->ml_addr = bus->mlcap + AZX_ML_BASE + (AZX_ML_INTERVAL * index);
ret = hdaml_lnk_enum(bus->dev, h2link, bus->remap_addr, hlink->ml_addr, index);
if (ret < 0) {
kfree(h2link);
return ret;
}
mutex_init(&h2link->eml_lock);
list_add_tail(&hlink->list, &bus->hlink_list);
/*
* HDaudio regular links are powered-on by default, the
* refcount needs to be initialized.
*/
if (!h2link->alt)
hlink->ref_count = 1;
return 0;
}
int hda_bus_ml_init(struct hdac_bus *bus)
{
u32 link_count;
int ret;
int i;
if (!bus->mlcap)
return 0;
link_count = readl(bus->mlcap + AZX_REG_ML_MLCD) + 1;
dev_dbg(bus->dev, "HDAudio Multi-Link count: %d\n", link_count);
for (i = 0; i < link_count; i++) {
ret = hda_ml_alloc_h2link(bus, i);
if (ret < 0) {
hda_bus_ml_free(bus);
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_NS(hda_bus_ml_init, SND_SOC_SOF_HDA_MLINK);
void hda_bus_ml_free(struct hdac_bus *bus)
{
struct hdac_ext_link *hlink, *_h;
struct hdac_ext2_link *h2link;
if (!bus->mlcap)
return;
list_for_each_entry_safe(hlink, _h, &bus->hlink_list, list) {
list_del(&hlink->list);
h2link = hdac_ext_link_to_ext2(hlink);
mutex_destroy(&h2link->eml_lock);
kfree(h2link);
}
}
EXPORT_SYMBOL_NS(hda_bus_ml_free, SND_SOC_SOF_HDA_MLINK);
static struct hdac_ext2_link *
find_ext2_link(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext_link *hlink;
list_for_each_entry(hlink, &bus->hlink_list, list) {
struct hdac_ext2_link *h2link = hdac_ext_link_to_ext2(hlink);
if (h2link->alt == alt && h2link->elid == elid)
return h2link;
}
return NULL;
}
int hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext2_link *h2link;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return 0;
return h2link->slcount;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_get_count, SND_SOC_SOF_HDA_MLINK);
void hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return;
if (!h2link->intc)
return;
hlink = &h2link->hext_link;
mutex_lock(&h2link->eml_lock);
hdaml_link_enable_interrupt(hlink->ml_addr + AZX_REG_ML_LCTL, enable);
mutex_unlock(&h2link->eml_lock);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_enable_interrupt, SND_SOC_SOF_HDA_MLINK);
bool hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return false;
if (!h2link->intc)
return false;
hlink = &h2link->hext_link;
return hdaml_link_check_interrupt(hlink->ml_addr + AZX_REG_ML_LCTL);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_check_interrupt, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return 0;
if (!h2link->lss)
return 0;
hlink = &h2link->hext_link;
hdaml_link_set_syncprd(hlink->ml_addr + AZX_REG_ML_LSYNC, syncprd);
return 0;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_set_syncprd_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd)
{
return hdac_bus_eml_set_syncprd_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW, syncprd);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_set_syncprd_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return 0;
if (!h2link->lss)
return 0;
hlink = &h2link->hext_link;
return hdaml_link_wait_syncpu(hlink->ml_addr + AZX_REG_ML_LSYNC);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_wait_syncpu_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus)
{
return hdac_bus_eml_wait_syncpu_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_wait_syncpu_unlocked, SND_SOC_SOF_HDA_MLINK);
void hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return;
if (!h2link->lss)
return;
hlink = &h2link->hext_link;
hdaml_link_sync_arm(hlink->ml_addr + AZX_REG_ML_LSYNC, sublink);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sync_arm_unlocked, SND_SOC_SOF_HDA_MLINK);
void hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink)
{
hdac_bus_eml_sync_arm_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW, sublink);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_sync_arm_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return 0;
if (!h2link->lss)
return 0;
hlink = &h2link->hext_link;
hdaml_link_sync_go(hlink->ml_addr + AZX_REG_ML_LSYNC);
return 0;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sync_go_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus)
{
return hdac_bus_eml_sync_go_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_sync_go_unlocked, SND_SOC_SOF_HDA_MLINK);
bool hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
u32 cmdsync_mask;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return 0;
if (!h2link->lss)
return 0;
hlink = &h2link->hext_link;
cmdsync_mask = GENMASK(AZX_REG_ML_LSYNC_CMDSYNC_SHIFT + h2link->slcount - 1,
AZX_REG_ML_LSYNC_CMDSYNC_SHIFT);
return hdaml_link_check_cmdsync(hlink->ml_addr + AZX_REG_ML_LSYNC,
cmdsync_mask);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_check_cmdsync_unlocked, SND_SOC_SOF_HDA_MLINK);
bool hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus)
{
return hdac_bus_eml_check_cmdsync_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_check_cmdsync_unlocked, SND_SOC_SOF_HDA_MLINK);
static int hdac_bus_eml_power_up_base(struct hdac_bus *bus, bool alt, int elid, int sublink,
bool eml_lock)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
int ret = 0;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return -ENODEV;
if (sublink >= h2link->slcount)
return -EINVAL;
hlink = &h2link->hext_link;
if (eml_lock)
mutex_lock(&h2link->eml_lock);
if (!alt) {
if (++hlink->ref_count > 1)
goto skip_init;
} else {
if (++h2link->sublink_ref_count[sublink] > 1)
goto skip_init;
}
ret = hdaml_link_init(hlink->ml_addr + AZX_REG_ML_LCTL, sublink);
skip_init:
if (eml_lock)
mutex_unlock(&h2link->eml_lock);
return ret;
}
int hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink)
{
return hdac_bus_eml_power_up_base(bus, alt, elid, sublink, true);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_power_up, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink)
{
return hdac_bus_eml_power_up_base(bus, alt, elid, sublink, false);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_power_up_unlocked, SND_SOC_SOF_HDA_MLINK);
static int hdac_bus_eml_power_down_base(struct hdac_bus *bus, bool alt, int elid, int sublink,
bool eml_lock)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
int ret = 0;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return -ENODEV;
if (sublink >= h2link->slcount)
return -EINVAL;
hlink = &h2link->hext_link;
if (eml_lock)
mutex_lock(&h2link->eml_lock);
if (!alt) {
if (--hlink->ref_count > 0)
goto skip_shutdown;
} else {
if (--h2link->sublink_ref_count[sublink] > 0)
goto skip_shutdown;
}
ret = hdaml_link_shutdown(hlink->ml_addr + AZX_REG_ML_LCTL, sublink);
skip_shutdown:
if (eml_lock)
mutex_unlock(&h2link->eml_lock);
return ret;
}
int hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink)
{
return hdac_bus_eml_power_down_base(bus, alt, elid, sublink, true);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_power_down, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink)
{
return hdac_bus_eml_power_down_base(bus, alt, elid, sublink, false);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_power_down_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink)
{
return hdac_bus_eml_power_up_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW, sublink);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_power_up_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink)
{
return hdac_bus_eml_power_down_unlocked(bus, true, AZX_REG_ML_LEPTR_ID_SDW, sublink);
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_power_down_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
if (!h2link)
return -ENODEV;
hlink = &h2link->hext_link;
*lsdiid = hdaml_link_get_lsdiid(hlink->ml_addr + AZX_REG_ML_LSDIID_OFFSET(sublink));
return 0;
} EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_get_lsdiid_unlocked, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
if (!h2link)
return -ENODEV;
hlink = &h2link->hext_link;
mutex_lock(&h2link->eml_lock);
hdaml_link_set_lsdiid(hlink->ml_addr + AZX_REG_ML_LSDIID_OFFSET(sublink), dev_num);
mutex_unlock(&h2link->eml_lock);
return 0;
} EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_set_lsdiid, SND_SOC_SOF_HDA_MLINK);
/*
* the 'y' parameter comes from the PCMSyCM hardware register naming. 'y' refers to the
* PDI index, i.e. the FIFO used for RX or TX
*/
int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y,
int channel_mask, int stream_id, int dir)
{
struct hdac_ext2_link *h2link;
u16 __iomem *pcmsycm;
int hchan;
int lchan;
u16 val;
h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
if (!h2link)
return -ENODEV;
pcmsycm = h2link->base_ptr + h2link->shim_offset +
h2link->instance_offset * sublink +
AZX_REG_SDW_SHIM_PCMSyCM(y);
if (channel_mask) {
hchan = __fls(channel_mask);
lchan = __ffs(channel_mask);
} else {
hchan = 0;
lchan = 0;
}
mutex_lock(&h2link->eml_lock);
hdaml_shim_map_stream_ch(pcmsycm, lchan, hchan,
stream_id, dir);
mutex_unlock(&h2link->eml_lock);
val = readw(pcmsycm);
dev_dbg(bus->dev, "sublink %d channel_mask %#x stream_id %d dir %d pcmscm %#x\n",
sublink, channel_mask, stream_id, dir, val);
return 0;
} EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_map_stream_ch, SND_SOC_SOF_HDA_MLINK);
void hda_bus_ml_put_all(struct hdac_bus *bus)
{
struct hdac_ext_link *hlink;
list_for_each_entry(hlink, &bus->hlink_list, list) {
struct hdac_ext2_link *h2link = hdac_ext_link_to_ext2(hlink);
if (!h2link->alt)
snd_hdac_ext_bus_link_put(bus, hlink);
}
}
EXPORT_SYMBOL_NS(hda_bus_ml_put_all, SND_SOC_SOF_HDA_MLINK);
void hda_bus_ml_reset_losidv(struct hdac_bus *bus)
{
struct hdac_ext_link *hlink;
/* Reset stream-to-link mapping */
list_for_each_entry(hlink, &bus->hlink_list, list)
writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
}
EXPORT_SYMBOL_NS(hda_bus_ml_reset_losidv, SND_SOC_SOF_HDA_MLINK);
int hda_bus_ml_resume(struct hdac_bus *bus)
{
struct hdac_ext_link *hlink;
int ret;
/* power up links that were active before suspend */
list_for_each_entry(hlink, &bus->hlink_list, list) {
struct hdac_ext2_link *h2link = hdac_ext_link_to_ext2(hlink);
if (!h2link->alt && hlink->ref_count) {
ret = snd_hdac_ext_bus_link_power_up(hlink);
if (ret < 0)
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_NS(hda_bus_ml_resume, SND_SOC_SOF_HDA_MLINK);
int hda_bus_ml_suspend(struct hdac_bus *bus)
{
struct hdac_ext_link *hlink;
int ret;
list_for_each_entry(hlink, &bus->hlink_list, list) {
struct hdac_ext2_link *h2link = hdac_ext_link_to_ext2(hlink);
if (!h2link->alt) {
ret = snd_hdac_ext_bus_link_power_down(hlink);
if (ret < 0)
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_NS(hda_bus_ml_suspend, SND_SOC_SOF_HDA_MLINK);
struct mutex *hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid)
{
struct hdac_ext2_link *h2link;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return NULL;
return &h2link->eml_lock;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_get_mutex, SND_SOC_SOF_HDA_MLINK);
struct hdac_ext_link *hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus)
{
struct hdac_ext2_link *h2link;
h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_SSP);
if (!h2link)
return NULL;
return &h2link->hext_link;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_ssp_get_hlink, SND_SOC_SOF_HDA_MLINK);
struct hdac_ext_link *hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus)
{
struct hdac_ext2_link *h2link;
h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_DMIC);
if (!h2link)
return NULL;
return &h2link->hext_link;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_dmic_get_hlink, SND_SOC_SOF_HDA_MLINK);
struct hdac_ext_link *hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus)
{
struct hdac_ext2_link *h2link;
h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
if (!h2link)
return NULL;
return &h2link->hext_link;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_get_hlink, SND_SOC_SOF_HDA_MLINK);
int hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable)
{
struct hdac_ext2_link *h2link;
struct hdac_ext_link *hlink;
h2link = find_ext2_link(bus, alt, elid);
if (!h2link)
return -ENODEV;
if (!h2link->ofls)
return 0;
hlink = &h2link->hext_link;
mutex_lock(&h2link->eml_lock);
hdaml_lctl_offload_enable(hlink->ml_addr + AZX_REG_ML_LCTL, enable);
mutex_unlock(&h2link->eml_lock);
return 0;
}
EXPORT_SYMBOL_NS(hdac_bus_eml_enable_offload, SND_SOC_SOF_HDA_MLINK);
#endif
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/sof/intel/hda-mlink.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <[email protected]>
// Ranjani Sridharan <[email protected]>
// Rander Wang <[email protected]>
// Keyon Jie <[email protected]>
//
/*
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <sound/hdaudio_ext.h>
#include "../ops.h"
#include "hda.h"
static int hda_dsp_trace_prepare(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct hdac_ext_stream *hext_stream = hda->dtrace_stream;
struct hdac_stream *hstream = &hext_stream->hstream;
int ret;
hstream->period_bytes = 0;/* initialize period_bytes */
hstream->bufsize = dmab->bytes;
ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL);
if (ret < 0)
dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret);
return ret;
}
int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
struct sof_ipc_dma_trace_params_ext *dtrace_params)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
int ret;
hda->dtrace_stream = hda_dsp_stream_get(sdev, SNDRV_PCM_STREAM_CAPTURE,
SOF_HDA_STREAM_DMI_L1_COMPATIBLE);
if (!hda->dtrace_stream) {
dev_err(sdev->dev,
"error: no available capture stream for DMA trace\n");
return -ENODEV;
}
dtrace_params->stream_tag = hda->dtrace_stream->hstream.stream_tag;
/*
* initialize capture stream, set BDL address and return corresponding
* stream tag which will be sent to the firmware by IPC message.
*/
ret = hda_dsp_trace_prepare(sdev, dmab);
if (ret < 0) {
dev_err(sdev->dev, "error: hdac trace init failed: %d\n", ret);
hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_CAPTURE,
dtrace_params->stream_tag);
hda->dtrace_stream = NULL;
dtrace_params->stream_tag = 0;
}
return ret;
}
int hda_dsp_trace_release(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
struct hdac_stream *hstream;
if (hda->dtrace_stream) {
hstream = &hda->dtrace_stream->hstream;
hda_dsp_stream_put(sdev,
SNDRV_PCM_STREAM_CAPTURE,
hstream->stream_tag);
hda->dtrace_stream = NULL;
return 0;
}
dev_dbg(sdev->dev, "DMA trace stream is not opened!\n");
return -ENODEV;
}
int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
return hda_dsp_stream_trigger(sdev, hda->dtrace_stream, cmd);
}
| linux-master | sound/soc/sof/intel/hda-trace.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Author: Liam Girdwood <[email protected]>
//
#include <linux/module.h>
#include <linux/pci.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/sof.h>
#include "../ops.h"
#include "../sof-pci-dev.h"
/* platform specific devices */
#include "hda.h"
static const struct sof_dev_desc cnl_desc = {
.machines = snd_soc_acpi_intel_cnl_machines,
.alt_machines = snd_soc_acpi_intel_cnl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &cnl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/cnl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/cnl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-cnl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-cnl-nocodec.tplg",
.ops = &sof_cnl_ops,
.ops_init = sof_cnl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc cfl_desc = {
.machines = snd_soc_acpi_intel_cfl_machines,
.alt_machines = snd_soc_acpi_intel_cfl_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &cnl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/cnl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/cnl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-cfl.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-cnl-nocodec.tplg",
.ops = &sof_cnl_ops,
.ops_init = sof_cnl_ops_init,
.ops_free = hda_ops_free,
};
static const struct sof_dev_desc cml_desc = {
.machines = snd_soc_acpi_intel_cml_machines,
.alt_machines = snd_soc_acpi_intel_cml_sdw_machines,
.use_acpi_target_states = true,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.chip_info = &cnl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.dspless_mode_supported = true, /* Only supported for HDaudio */
.default_fw_path = {
[SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/cnl",
},
.default_lib_path = {
[SOF_INTEL_IPC4] = "intel/avs-lib/cnl",
},
.default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
},
.default_fw_filename = {
[SOF_IPC] = "sof-cml.ri",
[SOF_INTEL_IPC4] = "dsp_basefw.bin",
},
.nocodec_tplg_filename = "sof-cnl-nocodec.tplg",
.ops = &sof_cnl_ops,
.ops_init = sof_cnl_ops_init,
.ops_free = hda_ops_free,
};
/* PCI IDs */
static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, &cnl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_CNL_H, &cfl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_CML_LP, &cml_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_CML_H, &cml_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_CML_S, &cml_desc) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, sof_pci_ids);
/* pci_driver definition */
static struct pci_driver snd_sof_pci_intel_cnl_driver = {
.name = "sof-audio-pci-intel-cnl",
.id_table = sof_pci_ids,
.probe = hda_pci_intel_probe,
.remove = sof_pci_remove,
.shutdown = sof_pci_shutdown,
.driver = {
.pm = &sof_pci_pm,
},
};
module_pci_driver(snd_sof_pci_intel_cnl_driver);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HDA_COMMON);
MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
| linux-master | sound/soc/sof/intel/pci-cnl.c |
Subsets and Splits