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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, Martin Botka <[email protected]>
* Copyright (c) 2020, Konrad Dybcio <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/clk.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_DSI0PLL_BYTE,
P_DSI0PLL,
P_DSI1PLL_BYTE,
P_DSI1PLL,
P_GPLL0,
P_GPLL0_DIV,
P_MMPLL0,
P_MMPLL10,
P_MMPLL3,
P_MMPLL4,
P_MMPLL5,
P_MMPLL6,
P_MMPLL7,
P_MMPLL8,
P_SLEEP_CLK,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV,
};
static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL4, 2 },
{ P_MMPLL7, 3 },
{ P_MMPLL8, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
/* Voteable PLL */
static struct clk_alpha_pll mmpll0 = {
.offset = 0xc000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1f0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll mmpll6 = {
.offset = 0xf0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1f0,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "mmpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
/* APSS controlled PLLs */
static struct pll_vco vco[] = {
{ 1000000000, 2000000000, 0 },
{ 750000000, 1500000000, 1 },
{ 500000000, 1000000000, 2 },
{ 250000000, 500000000, 3 },
};
static struct pll_vco mmpll3_vco[] = {
{ 750000000, 1500000000, 1 },
};
static const struct alpha_pll_config mmpll10_config = {
.l = 0x1e,
.config_ctl_val = 0x00004289,
.main_output_mask = 0x1,
};
static struct clk_alpha_pll mmpll10 = {
.offset = 0x190,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mmpll10",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct alpha_pll_config mmpll3_config = {
.l = 0x2e,
.config_ctl_val = 0x4001055b,
.vco_val = 0x1 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
static struct clk_alpha_pll mmpll3 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll3_vco,
.num_vco = ARRAY_SIZE(mmpll3_vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mmpll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct alpha_pll_config mmpll4_config = {
.l = 0x28,
.config_ctl_val = 0x4001055b,
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
static struct clk_alpha_pll mmpll4 = {
.offset = 0x50,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = vco,
.num_vco = ARRAY_SIZE(vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mmpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct alpha_pll_config mmpll5_config = {
.l = 0x2a,
.config_ctl_val = 0x4001055b,
.alpha_hi = 0xf8,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
static struct clk_alpha_pll mmpll5 = {
.offset = 0xa0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = vco,
.num_vco = ARRAY_SIZE(vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mmpll5",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct alpha_pll_config mmpll7_config = {
.l = 0x32,
.config_ctl_val = 0x4001055b,
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
static struct clk_alpha_pll mmpll7 = {
.offset = 0x140,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = vco,
.num_vco = ARRAY_SIZE(vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mmpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct alpha_pll_config mmpll8_config = {
.l = 0x30,
.alpha_hi = 0x70,
.alpha_en_mask = BIT(24),
.config_ctl_val = 0x4001055b,
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
static struct clk_alpha_pll mmpll8 = {
.offset = 0x1c0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = vco,
.num_vco = ARRAY_SIZE(vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mmpll8",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .hw = &mmpll8.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_dsibyte_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 },
};
static const struct clk_parent_data mmcc_xo_dsibyte[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte" },
};
static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL4, 2 },
{ P_MMPLL7, 3 },
{ P_MMPLL10, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .hw = &mmpll10.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL4, 1 },
{ P_MMPLL7, 2 },
{ P_MMPLL10, 3 },
{ P_SLEEP_CLK, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll4.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .hw = &mmpll10.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL7, 2 },
{ P_MMPLL10, 3 },
{ P_SLEEP_CLK, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .hw = &mmpll10.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmcc_xo_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_dplink_dpvco_map[] = {
{ P_XO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV, 2 },
};
static const struct clk_parent_data mmcc_xo_dplink_dpvco[] = {
{ .fw_name = "xo" },
{ .fw_name = "dp_link_2x_clk_divsel_five" },
{ .fw_name = "dp_vco_divided_clk_src_mux" },
};
static const struct parent_map mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL5, 2 },
{ P_MMPLL7, 3 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll5.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 },
};
static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pll" },
{ .fw_name = "dsi1pll" },
};
static const struct parent_map mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL4, 2 },
{ P_MMPLL7, 3 },
{ P_MMPLL10, 4 },
{ P_MMPLL6, 5 },
{ P_GPLL0, 6 },
};
static const struct clk_parent_data mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .hw = &mmpll10.clkr.hw },
{ .hw = &mmpll6.clkr.hw },
{ .fw_name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll0_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div" },
};
static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL4, 2 },
{ P_MMPLL7, 3 },
{ P_MMPLL10, 4 },
{ P_GPLL0, 5 },
{ P_MMPLL6, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .hw = &mmpll7.clkr.hw },
{ .hw = &mmpll10.clkr.hw },
{ .fw_name = "gpll0" },
{ .hw = &mmpll6.clkr.hw },
};
static const struct parent_map mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL8, 2 },
{ P_MMPLL3, 3 },
{ P_MMPLL6, 4 },
{ P_GPLL0, 5 },
{ P_MMPLL7, 6 },
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll8.clkr.hw },
{ .hw = &mmpll3.clkr.hw },
{ .hw = &mmpll6.clkr.hw },
{ .fw_name = "gpll0" },
{ .hw = &mmpll7.clkr.hw },
};
static const struct freq_tbl ftbl_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
F(80800000, P_MMPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 ahb_clk_src = {
.cmd_rcgr = 0x5000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_gpll0_gpll0_div_map,
.freq_tbl = ftbl_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ahb_clk_src",
.parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x2120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x2140,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0_DIV, 10, 1, 5),
F(12000000, P_GPLL0_DIV, 10, 2, 5),
F(13043478, P_GPLL0_DIV, 1, 1, 23),
F(24000000, P_GPLL0_DIV, 1, 2, 25),
F(50000000, P_GPLL0_DIV, 6, 0, 0),
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x3420,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x3450,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(37500000, P_GPLL0_DIV, 8, 0, 0),
F(50000000, P_GPLL0_DIV, 6, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x3300,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(120000000, P_GPLL0, 5, 0, 0),
F(256000000, P_MMPLL4, 3, 0, 0),
F(384000000, P_MMPLL4, 2, 0, 0),
F(480000000, P_MMPLL7, 2, 0, 0),
F(540000000, P_MMPLL6, 2, 0, 0),
F(576000000, P_MMPLL10, 1, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x3640,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map,
.freq_tbl = ftbl_cpp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(310000000, P_MMPLL8, 3, 0, 0),
F(404000000, P_MMPLL0, 2, 0, 0),
F(465000000, P_MMPLL8, 2, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x3090,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(269333333, P_MMPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x3000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x3100,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x3030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3160,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x3060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi3_clk_src = {
.cmd_rcgr = 0x31c0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csiphy_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(269333333, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL7, 3, 0, 0),
{ }
};
static struct clk_rcg2 csiphy_clk_src = {
.cmd_rcgr = 0x3800,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csiphy_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 dp_aux_clk_src = {
.cmd_rcgr = 0x2260,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_aux_clk_src",
.parent_data = mmcc_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
{ }
};
static struct clk_rcg2 dp_crypto_clk_src = {
.cmd_rcgr = 0x2220,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dplink_dpvco_map,
.freq_tbl = ftbl_dp_crypto_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_crypto_clk_src",
.parent_data = mmcc_xo_dplink_dpvco,
.num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_gtc_clk_src[] = {
F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 dp_gtc_clk_src = {
.cmd_rcgr = 0x2280,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_dp_gtc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_gtc_clk_src",
.parent_data = mmcc_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_link_clk_src[] = {
F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
{ }
};
static struct clk_rcg2 dp_link_clk_src = {
.cmd_rcgr = 0x2200,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_dplink_dpvco_map,
.freq_tbl = ftbl_dp_link_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_link_clk_src",
.parent_data = mmcc_xo_dplink_dpvco,
.num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 dp_pixel_clk_src = {
.cmd_rcgr = 0x2240,
.mnd_width = 16,
.hid_width = 5,
.parent_map = mmcc_xo_dplink_dpvco_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_pixel_clk_src",
.parent_data = mmcc_xo_dplink_dpvco,
.num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco),
.ops = &clk_dp_ops,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x2160,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x2180,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(66666667, P_GPLL0_DIV, 4.5, 0, 0),
F(133333333, P_GPLL0, 4.5, 0, 0),
F(219428571, P_MMPLL4, 3.5, 0, 0),
F(320000000, P_MMPLL7, 3, 0, 0),
F(480000000, P_MMPLL7, 2, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x3500,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_jpeg0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mclk0_clk_src[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0_DIV, 10, 1, 5),
F(8000000, P_GPLL0_DIV, 1, 2, 75),
F(9600000, P_XO, 2, 0, 0),
F(16666667, P_GPLL0_DIV, 2, 1, 9),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_MMPLL10, 1, 1, 24),
F(33333333, P_GPLL0_DIV, 1, 1, 9),
F(48000000, P_GPLL0, 1, 2, 25),
F(66666667, P_GPLL0, 1, 1, 9),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x3360,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x3390,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x33c0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x33f0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(150000000, P_GPLL0_DIV, 2, 0, 0),
F(171428571, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(275000000, P_MMPLL5, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(330000000, P_MMPLL5, 2.5, 0, 0),
F(412500000, P_MMPLL5, 2, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x2040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x2000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = mmcc_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = mmcc_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static const struct freq_tbl ftbl_rot_clk_src[] = {
F(171428571, P_GPLL0, 3.5, 0, 0),
F(275000000, P_MMPLL5, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(330000000, P_MMPLL5, 2.5, 0, 0),
F(412500000, P_MMPLL5, 2, 0, 0),
{ }
};
static struct clk_rcg2 rot_clk_src = {
.cmd_rcgr = 0x21a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
.freq_tbl = ftbl_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rot_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe0_clk_src[] = {
F(120000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(256000000, P_MMPLL4, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(404000000, P_MMPLL0, 2, 0, 0),
F(480000000, P_MMPLL7, 2, 0, 0),
F(540000000, P_MMPLL6, 2, 0, 0),
F(576000000, P_MMPLL10, 1, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x3600,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
.freq_tbl = ftbl_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
.num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x3620,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
.freq_tbl = ftbl_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
.num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_video_core_clk_src[] = {
F(133333333, P_GPLL0, 4.5, 0, 0),
F(269333333, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL7, 3, 0, 0),
F(404000000, P_MMPLL0, 2, 0, 0),
F(441600000, P_MMPLL3, 2, 0, 0),
F(518400000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_core_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_core_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x2080,
.mnd_width = 0,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = mmcc_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch bimc_smmu_ahb_clk = {
.halt_reg = 0xe004,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0xe004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "bimc_smmu_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch bimc_smmu_axi_clk = {
.halt_reg = 0xe008,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0xe008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "bimc_smmu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ahb_clk = {
.halt_reg = 0x348c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x348c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x348c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_ahb_clk = {
.halt_reg = 0x3348,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_clk = {
.halt_reg = 0x3344,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_clk",
.parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_ahb_clk = {
.halt_reg = 0x36b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_axi_clk = {
.halt_reg = 0x36c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_clk = {
.halt_reg = 0x36b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_clk",
.parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_vbif_ahb_clk = {
.halt_reg = 0x36c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_vbif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_ahb_clk = {
.halt_reg = 0x30bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_clk = {
.halt_reg = 0x30b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0phytimer_clk = {
.halt_reg = 0x3024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0pix_clk = {
.halt_reg = 0x30e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0rdi_clk = {
.halt_reg = 0x30d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_ahb_clk = {
.halt_reg = 0x3128,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_clk = {
.halt_reg = 0x3124,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1phytimer_clk = {
.halt_reg = 0x3054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1pix_clk = {
.halt_reg = 0x3154,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1rdi_clk = {
.halt_reg = 0x3144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_ahb_clk = {
.halt_reg = 0x3188,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_clk = {
.halt_reg = 0x3184,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2phytimer_clk = {
.halt_reg = 0x3084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2pix_clk = {
.halt_reg = 0x31b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2rdi_clk = {
.halt_reg = 0x31a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_ahb_clk = {
.halt_reg = 0x31e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_clk = {
.halt_reg = 0x31e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3pix_clk = {
.halt_reg = 0x3214,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3rdi_clk = {
.halt_reg = 0x3204,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe0_clk = {
.halt_reg = 0x3704,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe1_clk = {
.halt_reg = 0x3714,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3714,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csiphy0_clk = {
.halt_reg = 0x3740,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3740,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy0_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csiphy1_clk = {
.halt_reg = 0x3744,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3744,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy1_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csiphy2_clk = {
.halt_reg = 0x3748,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3748,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy2_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cphy_csid0_clk = {
.halt_reg = 0x3730,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3730,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid0_clk",
.parent_hws = (const struct clk_hw *[]){ &camss_csiphy0_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cphy_csid1_clk = {
.halt_reg = 0x3734,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3734,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid1_clk",
.parent_hws = (const struct clk_hw *[]){ &camss_csiphy1_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cphy_csid2_clk = {
.halt_reg = 0x3738,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3738,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid2_clk",
.parent_hws = (const struct clk_hw *[]){ &camss_csiphy2_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cphy_csid3_clk = {
.halt_reg = 0x373c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x373c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid3_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp0_clk = {
.halt_reg = 0x3444,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3444,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
.parent_hws = (const struct clk_hw *[]){ &camss_gp0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp1_clk = {
.halt_reg = 0x3474,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3474,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
.parent_hws = (const struct clk_hw *[]){ &camss_gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ispif_ahb_clk = {
.halt_reg = 0x3224,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg0_clk = {
.halt_reg = 0x35a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x35a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg0_clk",
.parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x35b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_axi_clk = {
.halt_reg = 0x35b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x35b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch throttle_camss_axi_clk = {
.halt_reg = 0x3c3c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c3c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "throttle_camss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk0_clk = {
.halt_reg = 0x3384,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3384,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk1_clk = {
.halt_reg = 0x33b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk2_clk = {
.halt_reg = 0x33e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk3_clk = {
.halt_reg = 0x3414,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_micro_ahb_clk = {
.halt_reg = 0x3494,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3494,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_top_ahb_clk = {
.halt_reg = 0x3484,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_ahb_clk = {
.halt_reg = 0x3668,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3668,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_clk = {
.halt_reg = 0x36a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_stream_clk = {
.halt_reg = 0x3720,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3720,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_stream_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe1_ahb_clk = {
.halt_reg = 0x3678,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3678,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe1_clk = {
.halt_reg = 0x36ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe1_stream_clk = {
.halt_reg = 0x3724,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3724,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_stream_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vbif_ahb_clk = {
.halt_reg = 0x36b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vbif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vbif_axi_clk = {
.halt_reg = 0x36bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vbif_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch csiphy_ahb2crif_clk = {
.halt_reg = 0x374c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x374c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x374c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "csiphy_ahb2crif_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x8a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_axi_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(171428571, P_GPLL0, 3.5, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(323200000, P_MMPLL0, 2.5, 0, 0),
F(406000000, P_MMPLL0, 2, 0, 0),
{ }
};
/* RO to linux */
static struct clk_rcg2 axi_clk_src = {
.cmd_rcgr = 0xd000,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "axi_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch mdss_axi_clk = {
.halt_reg = 0x2310,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch throttle_mdss_axi_clk = {
.halt_reg = 0x246c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x246c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x246c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "throttle_mdss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte0_clk = {
.halt_reg = 0x233c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x233c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div mdss_byte0_intf_div_clk = {
.reg = 0x237c,
.shift = 0,
.width = 2,
/*
* NOTE: Op does not work for div-3. Current assumption is that div-3
* is not a recommended setting for this divider.
*/
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_intf_div_clk",
.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
},
};
static struct clk_branch mdss_byte0_intf_clk = {
.halt_reg = 0x2374,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2374,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw *[]){ &mdss_byte0_intf_div_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte1_clk = {
.halt_reg = 0x2340,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2340,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div mdss_byte1_intf_div_clk = {
.reg = 0x2380,
.shift = 0,
.width = 2,
/*
* NOTE: Op does not work for div-3. Current assumption is that div-3
* is not a recommended setting for this divider.
*/
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_intf_div_clk",
.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
},
};
static struct clk_branch mdss_byte1_intf_clk = {
.halt_reg = 0x2378,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2378,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw *[]){ &mdss_byte1_intf_div_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_dp_aux_clk = {
.halt_reg = 0x2364,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2364,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_dp_crypto_clk = {
.halt_reg = 0x235c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x235c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_dp_gtc_clk = {
.halt_reg = 0x2368,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2368,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_gtc_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_gtc_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_dp_link_clk = {
.halt_reg = 0x2354,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2354,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_link_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Reset state of MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */
static struct clk_branch mdss_dp_link_intf_clk = {
.halt_reg = 0x2358,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2358,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_dp_pixel_clk = {
.halt_reg = 0x2360,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2360,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc0_clk = {
.halt_reg = 0x2344,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
.parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc1_clk = {
.halt_reg = 0x2348,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
.parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_dp_ahb_clk = {
.halt_reg = 0x230c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x230c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_dp_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_clk = {
.halt_reg = 0x231c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x231c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk0_clk = {
.halt_reg = 0x2314,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
.parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk1_clk = {
.halt_reg = 0x2318,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
.parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_rot_clk = {
.halt_reg = 0x2350,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2350,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_rot_clk",
.parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_vsync_clk = {
.halt_reg = 0x2328,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
.parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mnoc_ahb_clk = {
.halt_reg = 0x5024,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mnoc_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch misc_ahb_clk = {
.halt_reg = 0x328,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x328,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "misc_ahb_clk",
/*
* Dependency to be enabled before the branch is
* enabled.
*/
.parent_hws = (const struct clk_hw *[]){ &mnoc_ahb_clk.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch misc_cxo_clk = {
.halt_reg = 0x324,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "misc_cxo_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch snoc_dvm_axi_clk = {
.halt_reg = 0xe040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "snoc_dvm_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_ahb_clk = {
.halt_reg = 0x1030,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_axi_clk = {
.halt_reg = 0x1034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch throttle_video_axi_clk = {
.halt_reg = 0x118c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x118c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x118c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "throttle_video_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_core_clk = {
.halt_reg = 0x1028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_core_clk",
.parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_subcore0_clk = {
.halt_reg = 0x1048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_subcore0_clk",
.parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int[]){ 0x1028, 0x1034, 0x1048 },
.cxc_count = 3,
.pd = {
.name = "venus",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x1040,
.pd = {
.name = "venus_core0",
},
.parent = &venus_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x2304,
.pd = {
.name = "mdss",
},
.cxcs = (unsigned int []){ 0x2040 },
.cxc_count = 1,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_top_gdsc = {
.gdscr = 0x34a0,
.pd = {
.name = "camss_top",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe0_gdsc = {
.gdscr = 0x3664,
.pd = {
.name = "camss_vfe0",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe1_gdsc = {
.gdscr = 0x3674,
.pd = {
.name = "camss_vfe1_gdsc",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_cpp_gdsc = {
.gdscr = 0x36d4,
.pd = {
.name = "camss_cpp",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
/* This GDSC seems to hang the whole multimedia subsystem.
static struct gdsc bimc_smmu_gdsc = {
.gdscr = 0xe020,
.gds_hw_ctrl = 0xe024,
.pd = {
.name = "bimc_smmu",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &bimc_smmu_gdsc.pd,
.flags = HW_CTRL,
};
*/
static struct clk_regmap *mmcc_660_clocks[] = {
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
[CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
[DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
[DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
[DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr,
[DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
[DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[MMPLL0_PLL] = &mmpll0.clkr,
[MMPLL10_PLL] = &mmpll10.clkr,
[MMPLL3_PLL] = &mmpll3.clkr,
[MMPLL4_PLL] = &mmpll4.clkr,
[MMPLL5_PLL] = &mmpll5.clkr,
[MMPLL6_PLL] = &mmpll6.clkr,
[MMPLL7_PLL] = &mmpll7.clkr,
[MMPLL8_PLL] = &mmpll8.clkr,
[BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
[BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
[CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
[CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
[CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
[CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
[CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
[CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
[CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
[CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
[CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
[CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
[CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
[CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
[CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
[CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
[CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
[CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
[CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
[CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
[CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
[CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
[CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
[CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
[CSIPHY_AHB2CRIF_CLK] = &csiphy_ahb2crif_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
[MDSS_BYTE0_INTF_DIV_CLK] = &mdss_byte0_intf_div_clk.clkr,
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
[MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
[MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
[MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
[MDSS_DP_GTC_CLK] = &mdss_dp_gtc_clk.clkr,
[MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
[MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
[MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
[MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
[MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MISC_AHB_CLK] = &misc_ahb_clk.clkr,
[MISC_CXO_CLK] = &misc_cxo_clk.clkr,
[MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
[SNOC_DVM_AXI_CLK] = &snoc_dvm_axi_clk.clkr,
[THROTTLE_CAMSS_AXI_CLK] = &throttle_camss_axi_clk.clkr,
[THROTTLE_MDSS_AXI_CLK] = &throttle_mdss_axi_clk.clkr,
[THROTTLE_VIDEO_AXI_CLK] = &throttle_video_axi_clk.clkr,
[VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
[VIDEO_AXI_CLK] = &video_axi_clk.clkr,
[VIDEO_CORE_CLK] = &video_core_clk.clkr,
[VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[ROT_CLK_SRC] = &rot_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[MDSS_BYTE1_INTF_DIV_CLK] = &mdss_byte1_intf_div_clk.clkr,
[AXI_CLK_SRC] = &axi_clk_src.clkr,
};
static struct gdsc *mmcc_sdm660_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_TOP_GDSC] = &camss_top_gdsc,
[CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
[CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
[CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
};
static const struct qcom_reset_map mmcc_660_resets[] = {
[CAMSS_MICRO_BCR] = { 0x3490 },
};
static const struct regmap_config mmcc_660_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x40000,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_660_desc = {
.config = &mmcc_660_regmap_config,
.clks = mmcc_660_clocks,
.num_clks = ARRAY_SIZE(mmcc_660_clocks),
.resets = mmcc_660_resets,
.num_resets = ARRAY_SIZE(mmcc_660_resets),
.gdscs = mmcc_sdm660_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_sdm660_gdscs),
};
static const struct of_device_id mmcc_660_match_table[] = {
{ .compatible = "qcom,mmcc-sdm660" },
{ .compatible = "qcom,mmcc-sdm630", .data = (void *)1UL },
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
static void sdm630_clock_override(void)
{
/* SDM630 has only one DSI */
mmcc_660_desc.clks[BYTE1_CLK_SRC] = NULL;
mmcc_660_desc.clks[MDSS_BYTE1_CLK] = NULL;
mmcc_660_desc.clks[MDSS_BYTE1_INTF_DIV_CLK] = NULL;
mmcc_660_desc.clks[MDSS_BYTE1_INTF_CLK] = NULL;
mmcc_660_desc.clks[ESC1_CLK_SRC] = NULL;
mmcc_660_desc.clks[MDSS_ESC1_CLK] = NULL;
mmcc_660_desc.clks[PCLK1_CLK_SRC] = NULL;
mmcc_660_desc.clks[MDSS_PCLK1_CLK] = NULL;
}
static int mmcc_660_probe(struct platform_device *pdev)
{
const struct of_device_id *id;
struct regmap *regmap;
bool is_sdm630;
id = of_match_device(mmcc_660_match_table, &pdev->dev);
if (!id)
return -ENODEV;
is_sdm630 = !!(id->data);
regmap = qcom_cc_map(pdev, &mmcc_660_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (is_sdm630)
sdm630_clock_override();
clk_alpha_pll_configure(&mmpll3, regmap, &mmpll3_config);
clk_alpha_pll_configure(&mmpll4, regmap, &mmpll4_config);
clk_alpha_pll_configure(&mmpll5, regmap, &mmpll5_config);
clk_alpha_pll_configure(&mmpll7, regmap, &mmpll7_config);
clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config);
clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config);
return qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
}
static struct platform_driver mmcc_660_driver = {
.probe = mmcc_660_probe,
.driver = {
.name = "mmcc-sdm660",
.of_match_table = mmcc_660_match_table,
},
};
module_platform_driver(mmcc_660_driver);
MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 MMCC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/mmcc-sdm660.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_VIDEO_PLL0_OUT_MAIN,
/* P_VIDEO_PLL0_OUT_EVEN, */
/* P_VIDEO_PLL0_OUT_ODD, */
};
static const struct alpha_pll_config video_pll0_config = {
.l = 0x10,
.alpha = 0xaaab,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
/* { P_VIDEO_PLL0_OUT_EVEN, 2 }, */
/* { P_VIDEO_PLL0_OUT_ODD, 3 }, */
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
/* { .name = "video_pll0_out_even" }, */
/* { .name = "video_pll0_out_odd" }, */
};
static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_venus_clk_src = {
.cmd_rcgr = 0x7f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_venus_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch video_cc_apb_clk = {
.halt_reg = 0x990,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x990,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_at_clk = {
.halt_reg = 0x9f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_qdss_trig_clk = {
.halt_reg = 0x970,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x970,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_qdss_trig_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
.halt_reg = 0x9d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_qdss_tsctr_div8_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_vcodec0_axi_clk = {
.halt_reg = 0x930,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x930,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_vcodec0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_vcodec0_core_clk = {
.halt_reg = 0x890,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x890,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_vcodec0_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_vcodec1_axi_clk = {
.halt_reg = 0x950,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x950,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_vcodec1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_vcodec1_core_clk = {
.halt_reg = 0x8d0,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_vcodec1_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ahb_clk = {
.halt_reg = 0x9b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ctl_axi_clk = {
.halt_reg = 0x910,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x910,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ctl_core_clk = {
.halt_reg = 0x850,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x850,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ctl_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x814,
.pd = {
.name = "venus_gdsc",
},
.cxcs = (unsigned int []){ 0x850, 0x910 },
.cxc_count = 2,
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc vcodec0_gdsc = {
.gdscr = 0x874,
.pd = {
.name = "vcodec0_gdsc",
},
.cxcs = (unsigned int []){ 0x890, 0x930 },
.cxc_count = 2,
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec1_gdsc = {
.gdscr = 0x8b4,
.pd = {
.name = "vcodec1_gdsc",
},
.cxcs = (unsigned int []){ 0x8d0, 0x950 },
.cxc_count = 2,
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sdm845_clocks[] = {
[VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
[VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
[VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
[VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
[VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
[VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
[VIDEO_PLL0] = &video_pll0.clkr,
};
static struct gdsc *video_cc_sdm845_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VCODEC0_GDSC] = &vcodec0_gdsc,
[VCODEC1_GDSC] = &vcodec1_gdsc,
};
static const struct regmap_config video_cc_sdm845_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xb90,
.fast_io = true,
};
static const struct qcom_cc_desc video_cc_sdm845_desc = {
.config = &video_cc_sdm845_regmap_config,
.clks = video_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
.gdscs = video_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
};
static const struct of_device_id video_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
static int video_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
}
static struct platform_driver video_cc_sdm845_driver = {
.probe = video_cc_sdm845_probe,
.driver = {
.name = "sdm845-videocc",
.of_match_table = video_cc_sdm845_match_table,
},
};
static int __init video_cc_sdm845_init(void)
{
return platform_driver_register(&video_cc_sdm845_driver);
}
subsys_initcall(video_cc_sdm845_init);
static void __exit video_cc_sdm845_exit(void)
{
platform_driver_unregister(&video_cc_sdm845_driver);
}
module_exit(video_cc_sdm845_exit);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/videocc-sdm845.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/types.h>
#define REG_DIV_CTL1 0x43
#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0)
#define REG_EN_CTL 0x46
#define REG_EN_MASK BIT(7)
struct clkdiv {
struct regmap *regmap;
u16 base;
spinlock_t lock;
struct clk_hw hw;
unsigned int cxo_period_ns;
};
static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
{
return container_of(hw, struct clkdiv, hw);
}
static inline unsigned int div_factor_to_div(unsigned int div_factor)
{
if (!div_factor)
div_factor = 1;
return 1 << (div_factor - 1);
}
static inline unsigned int div_to_div_factor(unsigned int div)
{
return min(ilog2(div) + 1, 7);
}
static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
{
unsigned int val = 0;
regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
return val & REG_EN_MASK;
}
static int
__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
unsigned int div_factor)
{
int ret;
unsigned int ns = clkdiv->cxo_period_ns;
unsigned int div = div_factor_to_div(div_factor);
ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
REG_EN_MASK, enable ? REG_EN_MASK : 0);
if (ret)
return ret;
if (enable)
ndelay((2 + 3 * div) * ns);
else
ndelay(3 * div * ns);
return 0;
}
static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
{
unsigned int div_factor;
regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
}
static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
{
struct clkdiv *clkdiv = to_clkdiv(hw);
unsigned long flags;
int ret;
spin_lock_irqsave(&clkdiv->lock, flags);
ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
spin_unlock_irqrestore(&clkdiv->lock, flags);
return ret;
}
static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
{
struct clkdiv *clkdiv = to_clkdiv(hw);
unsigned long flags;
spin_lock_irqsave(&clkdiv->lock, flags);
spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
spin_unlock_irqrestore(&clkdiv->lock, flags);
}
static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned int div, div_factor;
div = DIV_ROUND_UP(*parent_rate, rate);
div_factor = div_to_div_factor(div);
div = div_factor_to_div(div_factor);
return *parent_rate / div;
}
static unsigned long
clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clkdiv *clkdiv = to_clkdiv(hw);
unsigned int div_factor;
regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
return parent_rate / div_factor_to_div(div_factor);
}
static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clkdiv *clkdiv = to_clkdiv(hw);
unsigned int div_factor = div_to_div_factor(parent_rate / rate);
unsigned long flags;
bool enabled;
int ret;
spin_lock_irqsave(&clkdiv->lock, flags);
enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
if (enabled) {
ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
if (ret)
goto unlock;
}
ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
DIV_CTL1_DIV_FACTOR_MASK, div_factor);
if (ret)
goto unlock;
if (enabled)
ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
div_factor);
unlock:
spin_unlock_irqrestore(&clkdiv->lock, flags);
return ret;
}
static const struct clk_ops clk_spmi_pmic_div_ops = {
.enable = clk_spmi_pmic_div_enable,
.disable = clk_spmi_pmic_div_disable,
.set_rate = clk_spmi_pmic_div_set_rate,
.recalc_rate = clk_spmi_pmic_div_recalc_rate,
.round_rate = clk_spmi_pmic_div_round_rate,
};
struct spmi_pmic_div_clk_cc {
int nclks;
struct clkdiv clks[] __counted_by(nclks);
};
static struct clk_hw *
spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
{
struct spmi_pmic_div_clk_cc *cc = data;
int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
if (idx < 0 || idx >= cc->nclks) {
pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
__func__, clkspec->args[0], cc->nclks);
return ERR_PTR(-EINVAL);
}
return &cc->clks[idx].hw;
}
static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
{
struct spmi_pmic_div_clk_cc *cc;
struct clk_init_data init = {};
struct clkdiv *clkdiv;
struct clk *cxo;
struct regmap *regmap;
struct device *dev = &pdev->dev;
struct device_node *of_node = dev->of_node;
struct clk_parent_data parent_data = { .index = 0, };
int nclks, i, ret, cxo_hz;
char name[20];
u32 start;
ret = of_property_read_u32(of_node, "reg", &start);
if (ret < 0) {
dev_err(dev, "reg property reading failed\n");
return ret;
}
regmap = dev_get_regmap(dev->parent, NULL);
if (!regmap) {
dev_err(dev, "Couldn't get parent's regmap\n");
return -EINVAL;
}
ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
if (ret < 0) {
dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
ret);
return ret;
}
if (!nclks)
return -EINVAL;
cc = devm_kzalloc(dev, struct_size(cc, clks, nclks), GFP_KERNEL);
if (!cc)
return -ENOMEM;
cc->nclks = nclks;
cxo = clk_get(dev, "xo");
if (IS_ERR(cxo)) {
ret = PTR_ERR(cxo);
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to get xo clock\n");
return ret;
}
cxo_hz = clk_get_rate(cxo);
clk_put(cxo);
init.name = name;
init.parent_data = &parent_data;
init.num_parents = 1;
init.ops = &clk_spmi_pmic_div_ops;
for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
snprintf(name, sizeof(name), "div_clk%d", i + 1);
spin_lock_init(&clkdiv[i].lock);
clkdiv[i].base = start + i * 0x100;
clkdiv[i].regmap = regmap;
clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
clkdiv[i].hw.init = &init;
ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
if (ret)
return ret;
}
return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc);
}
static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
{ .compatible = "qcom,spmi-clkdiv" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
static struct platform_driver spmi_pmic_clkdiv_driver = {
.driver = {
.name = "qcom,spmi-pmic-clkdiv",
.of_match_table = spmi_pmic_clkdiv_match_table,
},
.probe = spmi_pmic_clkdiv_probe,
};
module_platform_driver(spmi_pmic_clkdiv_driver);
MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/clk-spmi-pmic-div.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Ltd.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_AHB_CLK,
DT_SLEEP_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
DT_DSI1_PHY_PLL_OUT_BYTECLK,
DT_DSI1_PHY_PLL_OUT_DSICLK,
DT_DP0_PHY_PLL_LINK_CLK,
DT_DP0_PHY_PLL_VCO_DIV_CLK,
DT_DP1_PHY_PLL_LINK_CLK,
DT_DP1_PHY_PLL_VCO_DIV_CLK,
DT_DP2_PHY_PLL_LINK_CLK,
DT_DP2_PHY_PLL_VCO_DIV_CLK,
DT_DP3_PHY_PLL_LINK_CLK,
DT_DP3_PHY_PLL_VCO_DIV_CLK,
};
#define DISP_CC_MISC_CMD 0xF000
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DISP_CC_PLL1_OUT_EVEN,
P_DISP_CC_PLL1_OUT_MAIN,
P_DP0_PHY_PLL_LINK_CLK,
P_DP0_PHY_PLL_VCO_DIV_CLK,
P_DP1_PHY_PLL_LINK_CLK,
P_DP1_PHY_PLL_VCO_DIV_CLK,
P_DP2_PHY_PLL_LINK_CLK,
P_DP2_PHY_PLL_VCO_DIV_CLK,
P_DP3_PHY_PLL_LINK_CLK,
P_DP3_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_BYTECLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
P_SLEEP_CLK,
};
static struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0xD,
.alpha = 0x6492,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32AA299C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_reset_lucid_evo_ops,
},
},
};
static const struct alpha_pll_config disp_cc_pll1_config = {
.l = 0x1F,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32AA299C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll disp_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_reset_lucid_evo_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
};
static const struct clk_parent_data disp_cc_parent_data_1_ao[] = {
{ .index = DT_BI_TCXO_AO },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP1_PHY_PLL_LINK_CLK, 2 },
{ P_DP2_PHY_PLL_LINK_CLK, 3 },
{ P_DP3_PHY_PLL_LINK_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP1_PHY_PLL_LINK_CLK },
{ .index = DT_DP2_PHY_PLL_LINK_CLK },
{ .index = DT_DP3_PHY_PLL_LINK_CLK },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll1.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_7[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_7[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x8324,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x8134,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.cmd_rcgr = 0x8150,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
.cmd_rcgr = 0x81ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x819c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
.cmd_rcgr = 0x81bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
.cmd_rcgr = 0x81d4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
.cmd_rcgr = 0x8254,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.cmd_rcgr = 0x8234,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
.cmd_rcgr = 0x8204,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
.cmd_rcgr = 0x821c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
.cmd_rcgr = 0x82bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.cmd_rcgr = 0x826c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
.cmd_rcgr = 0x828c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
.cmd_rcgr = 0x82a4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
.cmd_rcgr = 0x8308,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.cmd_rcgr = 0x82ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
.cmd_rcgr = 0x82d4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x816c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.cmd_rcgr = 0x8184,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x80ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x80bc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.cmd_rcgr = 0x80d4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x8104,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x811c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_sleep_clk_src = {
.cmd_rcgr = 0xe060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_xo_clk_src = {
.cmd_rcgr = 0xe044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_xo_clk_src",
.parent_data = disp_cc_parent_data_1_ao,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x814c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.reg = 0x8168,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
.reg = 0x81b4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
.reg = 0x824c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
.reg = 0x8284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
.reg = 0x8304,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb1_clk = {
.halt_reg = 0xa020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_ahb1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x80a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x8028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x802c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte1_clk = {
.halt_reg = 0x8030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.halt_reg = 0x8034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
.halt_reg = 0x8058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
.halt_reg = 0x804c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x804c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
.halt_reg = 0x8040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
.halt_reg = 0x8048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
.halt_reg = 0x8050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
.halt_reg = 0x8054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
.halt_reg = 0x8044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
.halt_reg = 0x8074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
.halt_reg = 0x8070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
.halt_reg = 0x806c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x806c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
.halt_reg = 0x805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
.halt_reg = 0x8060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
.halt_reg = 0x8068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
.halt_reg = 0x808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
.halt_reg = 0x8088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
.halt_reg = 0x8080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
.halt_reg = 0x8084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
.halt_reg = 0x8078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
.halt_reg = 0x807c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x807c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
.halt_reg = 0x809c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x809c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
.halt_reg = 0x80a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
.halt_reg = 0x8094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
.halt_reg = 0x8098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x8038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc1_clk = {
.halt_reg = 0x803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp1_clk = {
.halt_reg = 0xa004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
.halt_reg = 0xa014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x801c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x801c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0xc004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xc004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x8004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk1_clk = {
.halt_reg = 0x8008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot1_clk = {
.halt_reg = 0xa00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rot1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x8014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0xc00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0xc008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync1_clk = {
.halt_reg = 0xa01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_vsync1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x8024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0xe078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x9000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc mdss_int2_gdsc = {
.gdscr = 0xb000,
.pd = {
.name = "mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8450_clocks[] = {
[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
[DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
};
static const struct qcom_reset_map disp_cc_sm8450_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
};
static struct gdsc *disp_cc_sm8450_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
};
static const struct regmap_config disp_cc_sm8450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x11008,
.fast_io = true,
};
static struct qcom_cc_desc disp_cc_sm8450_desc = {
.config = &disp_cc_sm8450_regmap_config,
.clks = disp_cc_sm8450_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm8450_clocks),
.resets = disp_cc_sm8450_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm8450_resets),
.gdscs = disp_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs),
};
static const struct of_device_id disp_cc_sm8450_match_table[] = {
{ .compatible = "qcom,sm8450-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);
static int disp_cc_sm8450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto err_put_rpm;
}
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/*
* Keep clocks always enabled:
* disp_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap);
if (ret)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static struct platform_driver disp_cc_sm8450_driver = {
.probe = disp_cc_sm8450_probe,
.driver = {
.name = "disp_cc-sm8450",
.of_match_table = disp_cc_sm8450_match_table,
},
};
static int __init disp_cc_sm8450_init(void)
{
return platform_driver_register(&disp_cc_sm8450_driver);
}
subsys_initcall(disp_cc_sm8450_init);
static void __exit disp_cc_sm8450_exit(void)
{
platform_driver_unregister(&disp_cc_sm8450_driver);
}
module_exit(disp_cc_sm8450_exit);
MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/dispcc-sm8450.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <asm/div64.h>
#include "clk-pll.h"
#include "common.h"
#define PLL_OUTCTRL BIT(0)
#define PLL_BYPASSNL BIT(1)
#define PLL_RESET_N BIT(2)
static int clk_pll_enable(struct clk_hw *hw)
{
struct clk_pll *pll = to_clk_pll(hw);
int ret;
u32 mask, val;
mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
if (ret)
return ret;
/* Skip if already enabled or in FSM mode */
if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
return 0;
/* Disable PLL bypass mode. */
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
PLL_BYPASSNL);
if (ret)
return ret;
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe.
*/
udelay(10);
/* De-assert active-low PLL reset. */
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
PLL_RESET_N);
if (ret)
return ret;
/* Wait until PLL is locked. */
udelay(50);
/* Enable PLL output. */
return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
PLL_OUTCTRL);
}
static void clk_pll_disable(struct clk_hw *hw)
{
struct clk_pll *pll = to_clk_pll(hw);
u32 mask;
u32 val;
regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
/* Skip if in FSM mode */
if (val & PLL_VOTE_FSM_ENA)
return;
mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
}
static unsigned long
clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
u32 l, m, n, config;
unsigned long rate;
u64 tmp;
regmap_read(pll->clkr.regmap, pll->l_reg, &l);
regmap_read(pll->clkr.regmap, pll->m_reg, &m);
regmap_read(pll->clkr.regmap, pll->n_reg, &n);
l &= 0x3ff;
m &= 0x7ffff;
n &= 0x7ffff;
rate = parent_rate * l;
if (n) {
tmp = parent_rate;
tmp *= m;
do_div(tmp, n);
rate += tmp;
}
if (pll->post_div_width) {
regmap_read(pll->clkr.regmap, pll->config_reg, &config);
config >>= pll->post_div_shift;
config &= BIT(pll->post_div_width) - 1;
rate /= config + 1;
}
return rate;
}
static const
struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
{
if (!f)
return NULL;
for (; f->freq; f++)
if (rate <= f->freq)
return f;
return NULL;
}
static int
clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct clk_pll *pll = to_clk_pll(hw);
const struct pll_freq_tbl *f;
f = find_freq(pll->freq_tbl, req->rate);
if (!f)
req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
else
req->rate = f->freq;
return 0;
}
static int
clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
const struct pll_freq_tbl *f;
bool enabled;
u32 mode;
u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
f = find_freq(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
enabled = (mode & enable_mask) == enable_mask;
if (enabled)
clk_pll_disable(hw);
regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
if (enabled)
clk_pll_enable(hw);
return 0;
}
const struct clk_ops clk_pll_ops = {
.enable = clk_pll_enable,
.disable = clk_pll_disable,
.recalc_rate = clk_pll_recalc_rate,
.determine_rate = clk_pll_determine_rate,
.set_rate = clk_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_pll_ops);
static int wait_for_pll(struct clk_pll *pll)
{
u32 val;
int count;
int ret;
const char *name = clk_hw_get_name(&pll->clkr.hw);
/* Wait for pll to enable. */
for (count = 200; count > 0; count--) {
ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
if (ret)
return ret;
if (val & BIT(pll->status_bit))
return 0;
udelay(1);
}
WARN(1, "%s didn't enable after voting for it!\n", name);
return -ETIMEDOUT;
}
static int clk_pll_vote_enable(struct clk_hw *hw)
{
int ret;
struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw));
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll(p);
}
const struct clk_ops clk_pll_vote_ops = {
.enable = clk_pll_vote_enable,
.disable = clk_disable_regmap,
};
EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config)
{
u32 val;
u32 mask;
regmap_write(regmap, pll->l_reg, config->l);
regmap_write(regmap, pll->m_reg, config->m);
regmap_write(regmap, pll->n_reg, config->n);
val = config->vco_val;
val |= config->pre_div_val;
val |= config->post_div_val;
val |= config->mn_ena_mask;
val |= config->main_output_mask;
val |= config->aux_output_mask;
mask = config->vco_mask;
mask |= config->pre_div_mask;
mask |= config->post_div_mask;
mask |= config->mn_ena_mask;
mask |= config->main_output_mask;
mask |= config->aux_output_mask;
regmap_update_bits(regmap, pll->config_reg, mask, val);
}
void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config, bool fsm_mode)
{
clk_pll_configure(pll, regmap, config);
if (fsm_mode)
qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
}
EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
const struct pll_config *config, bool fsm_mode)
{
clk_pll_configure(pll, regmap, config);
if (fsm_mode)
qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
}
EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
static int clk_pll_sr2_enable(struct clk_hw *hw)
{
struct clk_pll *pll = to_clk_pll(hw);
int ret;
u32 mode;
ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
if (ret)
return ret;
/* Disable PLL bypass mode. */
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
PLL_BYPASSNL);
if (ret)
return ret;
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe.
*/
udelay(10);
/* De-assert active-low PLL reset. */
ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
PLL_RESET_N);
if (ret)
return ret;
ret = wait_for_pll(pll);
if (ret)
return ret;
/* Enable PLL output. */
return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
PLL_OUTCTRL);
}
static int
clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
{
struct clk_pll *pll = to_clk_pll(hw);
const struct pll_freq_tbl *f;
bool enabled;
u32 mode;
u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
f = find_freq(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
enabled = (mode & enable_mask) == enable_mask;
if (enabled)
clk_pll_disable(hw);
regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
if (enabled)
clk_pll_sr2_enable(hw);
return 0;
}
const struct clk_ops clk_pll_sr2_ops = {
.enable = clk_pll_sr2_enable,
.disable = clk_pll_disable,
.set_rate = clk_pll_sr2_set_rate,
.recalc_rate = clk_pll_recalc_rate,
.determine_rate = clk_pll_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);
| linux-master | drivers/clk/qcom/clk-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*x
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/clk.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_MMPLL0,
P_GPLL0,
P_GPLL0_DIV,
P_MMPLL1,
P_MMPLL9,
P_MMPLL2,
P_MMPLL8,
P_MMPLL3,
P_DSI0PLL,
P_DSI1PLL,
P_MMPLL5,
P_HDMIPLL,
P_DSI0PLL_BYTE,
P_DSI1PLL_BYTE,
P_MMPLL4,
};
static struct clk_fixed_factor gpll0_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_div",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "gpll0", .name = "gpll0" },
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct pll_vco mmpll_p_vco[] = {
{ 250000000, 500000000, 3 },
{ 500000000, 1000000000, 2 },
{ 1000000000, 1500000000, 1 },
{ 1500000000, 2000000000, 0 },
};
static struct pll_vco mmpll_gfx_vco[] = {
{ 400000000, 1000000000, 2 },
{ 1000000000, 1500000000, 1 },
{ 1500000000, 2000000000, 0 },
};
static struct pll_vco mmpll_t_vco[] = {
{ 500000000, 1500000000, 0 },
};
static struct clk_alpha_pll mmpll0_early = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
.enable_reg = 0x100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv mmpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
.parent_hws = (const struct clk_hw*[]){
&mmpll0_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll1_early = {
.offset = 0x30,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
.enable_reg = 0x100,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "mmpll1_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
}
},
};
static struct clk_alpha_pll_postdiv mmpll1 = {
.offset = 0x30,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
.parent_hws = (const struct clk_hw*[]){
&mmpll1_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll2_early = {
.offset = 0x4100,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_gfx_vco,
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll2 = {
.offset = 0x4100,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2",
.parent_hws = (const struct clk_hw*[]){
&mmpll2_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll3_early = {
.offset = 0x60,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll3 = {
.offset = 0x60,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
.parent_hws = (const struct clk_hw*[]){
&mmpll3_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll4_early = {
.offset = 0x90,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll4 = {
.offset = 0x90,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
.parent_hws = (const struct clk_hw*[]){
&mmpll4_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll5_early = {
.offset = 0xc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll5 = {
.offset = 0xc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5",
.parent_hws = (const struct clk_hw*[]){
&mmpll5_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll8_early = {
.offset = 0x4130,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_gfx_vco,
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll8_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll8 = {
.offset = 0x4130,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll8",
.parent_hws = (const struct clk_hw*[]){
&mmpll8_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll9_early = {
.offset = 0x4200,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll9_early",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll9 = {
.offset = 0x4200,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll9",
.parent_hws = (const struct clk_hw*[]){
&mmpll9_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct parent_map mmss_xo_hdmi_map[] = {
{ P_XO, 0 },
{ P_HDMIPLL, 1 }
};
static const struct clk_parent_data mmss_xo_hdmi[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "hdmipll", .name = "hdmipll" }
};
static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" }
};
static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_dsibyte_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 }
};
static const struct clk_parent_data mmss_xo_dsibyte[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }
};
static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll1.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL3, 3 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll3.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL5, 2 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll5.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL4, 3 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL9, 2 },
{ P_MMPLL2, 3 },
{ P_MMPLL8, 4 },
{ P_GPLL0, 5 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll9.clkr.hw },
{ .hw = &mmpll2.clkr.hw },
{ .hw = &mmpll8.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL9, 2 },
{ P_MMPLL2, 3 },
{ P_MMPLL8, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll9.clkr.hw },
{ .hw = &mmpll2.clkr.hw },
{ .hw = &mmpll8.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_MMPLL4, 3 },
{ P_MMPLL3, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 }
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll1.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .hw = &mmpll3.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .hw = &gpll0_div.hw }
};
static const struct freq_tbl ftbl_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
F(80000000, P_MMPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 ahb_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
.freq_tbl = ftbl_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ahb_clk_src",
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_axi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(75000000, P_GPLL0_DIV, 4, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 axi_clk_src = {
.cmd_rcgr = 0x5040,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
.freq_tbl = ftbl_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "axi_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 maxi_clk_src = {
.cmd_rcgr = 0x5090,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
.freq_tbl = ftbl_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "maxi_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2_gfx3d gfx3d_clk_src = {
.rcg = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0),
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
.hws = (struct clk_hw*[]) {
&mmpll9.clkr.hw,
&mmpll2.clkr.hw,
&mmpll8.clkr.hw
},
};
static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 rbbmtimer_clk_src = {
.cmd_rcgr = 0x4090,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
.freq_tbl = ftbl_rbbmtimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 isense_clk_src = {
.cmd_rcgr = 0x4010,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "isense_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_clk_src = {
.cmd_rcgr = 0x4060,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
.freq_tbl = ftbl_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_video_core_clk_src[] = {
F(75000000, P_GPLL0_DIV, 4, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(346666667, P_MMPLL3, 3, 0, 0),
F(520000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_core_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_core_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 video_subcore0_clk_src = {
.cmd_rcgr = 0x1060,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_subcore0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 video_subcore1_clk_src = {
.cmd_rcgr = 0x1080,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_subcore1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x2000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = mmss_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = mmss_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(85714286, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(171428571, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(275000000, P_MMPLL5, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(330000000, P_MMPLL5, 2.5, 0, 0),
F(412500000, P_MMPLL5, 2, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x2040,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
static struct clk_rcg2 extpclk_clk_src = {
.cmd_rcgr = 0x2060,
.hid_width = 5,
.parent_map = mmss_xo_hdmi_map,
.freq_tbl = extpclk_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
.parent_data = mmss_xo_hdmi,
.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x2080,
.hid_width = 5,
.parent_map = mmss_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = mmss_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hdmi_clk_src = {
.cmd_rcgr = 0x2100,
.hid_width = 5,
.parent_map = mmss_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mdss_hdmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
.parent_data = mmss_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x2120,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x2140,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x2160,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x2180,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0_DIV, 10, 1, 5),
F(12000000, P_GPLL0_DIV, 1, 1, 25),
F(13000000, P_GPLL0_DIV, 2, 13, 150),
F(24000000, P_GPLL0_DIV, 1, 2, 25),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x3420,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x3450,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mclk0_clk_src[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0_DIV, 10, 1, 5),
F(8000000, P_GPLL0_DIV, 1, 2, 75),
F(9600000, P_XO, 2, 0, 0),
F(16666667, P_GPLL0_DIV, 2, 1, 9),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0_DIV, 1, 2, 25),
F(33333333, P_GPLL0_DIV, 1, 1, 9),
F(48000000, P_GPLL0, 1, 2, 25),
F(66666667, P_GPLL0, 1, 1, 9),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x3360,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x3390,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x33c0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x33f0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x3300,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(266666667, P_MMPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x3030,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x3060,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL4, 3, 0, 0),
F(384000000, P_MMPLL4, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 csiphy0_3p_clk_src = {
.cmd_rcgr = 0x3240,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphy0_3p_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csiphy0_3p_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csiphy1_3p_clk_src = {
.cmd_rcgr = 0x3260,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphy0_3p_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csiphy1_3p_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csiphy2_3p_clk_src = {
.cmd_rcgr = 0x3280,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphy0_3p_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csiphy2_3p_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(75000000, P_GPLL0_DIV, 4, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(228571429, P_MMPLL0, 3.5, 0, 0),
F(266666667, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x3500,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_jpeg0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
F(75000000, P_GPLL0_DIV, 4, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(228571429, P_MMPLL0, 3.5, 0, 0),
F(266666667, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg2_clk_src = {
.cmd_rcgr = 0x3540,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_jpeg2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg_dma_clk_src = {
.cmd_rcgr = 0x3560,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_jpeg0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg_dma_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe0_clk_src[] = {
F(75000000, P_GPLL0_DIV, 4, 0, 0),
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x3600,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x3620,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(640000000, P_MMPLL4, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x3640,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_cpp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(266666667, P_MMPLL0, 3, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x3090,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x3100,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3160,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi3_clk_src = {
.cmd_rcgr = 0x31c0,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_fd_core_clk_src[] = {
F(100000000, P_GPLL0_DIV, 3, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 fd_core_clk_src = {
.cmd_rcgr = 0x3b00,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
.freq_tbl = ftbl_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "fd_core_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch mmss_mmagic_ahb_clk = {
.halt_reg = 0x5024,
.clkr = {
.enable_reg = 0x5024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmagic_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
.halt_reg = 0x5054,
.clkr = {
.enable_reg = 0x5054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmagic_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_misc_ahb_clk = {
.halt_reg = 0x5018,
.clkr = {
.enable_reg = 0x5018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_misc_cxo_clk = {
.halt_reg = 0x5014,
.clkr = {
.enable_reg = 0x5014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_cxo_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_mmagic_maxi_clk = {
.halt_reg = 0x5074,
.clkr = {
.enable_reg = 0x5074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmagic_maxi_clk",
.parent_hws = (const struct clk_hw*[]){
&maxi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_camss_axi_clk = {
.halt_reg = 0x3c44,
.clkr = {
.enable_reg = 0x3c44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_camss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
.halt_reg = 0x3c48,
.clkr = {
.enable_reg = 0x3c48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_camss_noc_cfg_ahb_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_vfe_ahb_clk = {
.halt_reg = 0x3c04,
.clkr = {
.enable_reg = 0x3c04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_vfe_axi_clk = {
.halt_reg = 0x3c08,
.clkr = {
.enable_reg = 0x3c08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_cpp_ahb_clk = {
.halt_reg = 0x3c14,
.clkr = {
.enable_reg = 0x3c14,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_cpp_axi_clk = {
.halt_reg = 0x3c18,
.clkr = {
.enable_reg = 0x3c18,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_cpp_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_jpeg_ahb_clk = {
.halt_reg = 0x3c24,
.clkr = {
.enable_reg = 0x3c24,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_jpeg_axi_clk = {
.halt_reg = 0x3c28,
.clkr = {
.enable_reg = 0x3c28,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_jpeg_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_mdss_axi_clk = {
.halt_reg = 0x2474,
.clkr = {
.enable_reg = 0x2474,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
.halt_reg = 0x2478,
.clkr = {
.enable_reg = 0x2478,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_mdss_noc_cfg_ahb_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_rot_ahb_clk = {
.halt_reg = 0x2444,
.clkr = {
.enable_reg = 0x2444,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_rot_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_rot_axi_clk = {
.halt_reg = 0x2448,
.clkr = {
.enable_reg = 0x2448,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_rot_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_mdp_ahb_clk = {
.halt_reg = 0x2454,
.clkr = {
.enable_reg = 0x2454,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_mdp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_mdp_axi_clk = {
.halt_reg = 0x2458,
.clkr = {
.enable_reg = 0x2458,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_mdp_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_video_axi_clk = {
.halt_reg = 0x1194,
.clkr = {
.enable_reg = 0x1194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_video_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
.halt_reg = 0x1198,
.clkr = {
.enable_reg = 0x1198,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_video_noc_cfg_ahb_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_video_ahb_clk = {
.halt_reg = 0x1174,
.clkr = {
.enable_reg = 0x1174,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_video_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch smmu_video_axi_clk = {
.halt_reg = 0x1178,
.clkr = {
.enable_reg = 0x1178,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "smmu_video_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
.halt_reg = 0x5298,
.clkr = {
.enable_reg = 0x5298,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmagic_bimc_noc_cfg_ahb_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_gx_gfx3d_clk = {
.halt_reg = 0x4028,
.clkr = {
.enable_reg = 0x4028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.rcg.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_gx_rbbmtimer_clk = {
.halt_reg = 0x40b0,
.clkr = {
.enable_reg = 0x40b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_gx_rbbmtimer_clk",
.parent_hws = (const struct clk_hw*[]){
&rbbmtimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_ahb_clk = {
.halt_reg = 0x403c,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_aon_isense_clk = {
.halt_reg = 0x4044,
.clkr = {
.enable_reg = 0x4044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_aon_isense_clk",
.parent_hws = (const struct clk_hw*[]){
&isense_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vmem_maxi_clk = {
.halt_reg = 0x1204,
.clkr = {
.enable_reg = 0x1204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vmem_maxi_clk",
.parent_hws = (const struct clk_hw*[]){
&maxi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vmem_ahb_clk = {
.halt_reg = 0x1208,
.clkr = {
.enable_reg = 0x1208,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vmem_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_rbcpr_clk = {
.halt_reg = 0x4084,
.clkr = {
.enable_reg = 0x4084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&rbcpr_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_rbcpr_ahb_clk = {
.halt_reg = 0x4088,
.clkr = {
.enable_reg = 0x4088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_core_clk = {
.halt_reg = 0x1028,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_axi_clk = {
.halt_reg = 0x1034,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_maxi_clk = {
.halt_reg = 0x1038,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_maxi_clk",
.parent_hws = (const struct clk_hw*[]){
&maxi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_ahb_clk = {
.halt_reg = 0x1030,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_subcore0_clk = {
.halt_reg = 0x1048,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_subcore0_clk",
.parent_hws = (const struct clk_hw*[]){
&video_subcore0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_subcore1_clk = {
.halt_reg = 0x104c,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_subcore1_clk",
.parent_hws = (const struct clk_hw*[]){
&video_subcore1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_ahb_clk = {
.halt_reg = 0x230c,
.clkr = {
.enable_reg = 0x230c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_axi_clk = {
.halt_reg = 0x2310,
.clkr = {
.enable_reg = 0x2310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk0_clk = {
.halt_reg = 0x2314,
.clkr = {
.enable_reg = 0x2314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk1_clk = {
.halt_reg = 0x2318,
.clkr = {
.enable_reg = 0x2318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_clk = {
.halt_reg = 0x231c,
.clkr = {
.enable_reg = 0x231c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_extpclk_clk = {
.halt_reg = 0x2324,
.clkr = {
.enable_reg = 0x2324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
.parent_hws = (const struct clk_hw*[]){
&extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_vsync_clk = {
.halt_reg = 0x2328,
.clkr = {
.enable_reg = 0x2328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_clk = {
.halt_reg = 0x2338,
.clkr = {
.enable_reg = 0x2338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
.parent_hws = (const struct clk_hw*[]){
&hdmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte0_clk = {
.halt_reg = 0x233c,
.clkr = {
.enable_reg = 0x233c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte1_clk = {
.halt_reg = 0x2340,
.clkr = {
.enable_reg = 0x2340,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&byte1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc0_clk = {
.halt_reg = 0x2344,
.clkr = {
.enable_reg = 0x2344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc1_clk = {
.halt_reg = 0x2348,
.clkr = {
.enable_reg = 0x2348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&esc1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_top_ahb_clk = {
.halt_reg = 0x3484,
.clkr = {
.enable_reg = 0x3484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ahb_clk = {
.halt_reg = 0x348c,
.clkr = {
.enable_reg = 0x348c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_micro_ahb_clk = {
.halt_reg = 0x3494,
.clkr = {
.enable_reg = 0x3494,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp0_clk = {
.halt_reg = 0x3444,
.clkr = {
.enable_reg = 0x3444,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp1_clk = {
.halt_reg = 0x3474,
.clkr = {
.enable_reg = 0x3474,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk0_clk = {
.halt_reg = 0x3384,
.clkr = {
.enable_reg = 0x3384,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk1_clk = {
.halt_reg = 0x33b4,
.clkr = {
.enable_reg = 0x33b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk2_clk = {
.halt_reg = 0x33e4,
.clkr = {
.enable_reg = 0x33e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk3_clk = {
.halt_reg = 0x3414,
.clkr = {
.enable_reg = 0x3414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_clk = {
.halt_reg = 0x3344,
.clkr = {
.enable_reg = 0x3344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_ahb_clk = {
.halt_reg = 0x3348,
.clkr = {
.enable_reg = 0x3348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0phytimer_clk = {
.halt_reg = 0x3024,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1phytimer_clk = {
.halt_reg = 0x3054,
.clkr = {
.enable_reg = 0x3054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2phytimer_clk = {
.halt_reg = 0x3084,
.clkr = {
.enable_reg = 0x3084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csiphy0_3p_clk = {
.halt_reg = 0x3234,
.clkr = {
.enable_reg = 0x3234,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy0_3p_clk",
.parent_hws = (const struct clk_hw*[]){
&csiphy0_3p_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csiphy1_3p_clk = {
.halt_reg = 0x3254,
.clkr = {
.enable_reg = 0x3254,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy1_3p_clk",
.parent_hws = (const struct clk_hw*[]){
&csiphy1_3p_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csiphy2_3p_clk = {
.halt_reg = 0x3274,
.clkr = {
.enable_reg = 0x3274,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy2_3p_clk",
.parent_hws = (const struct clk_hw*[]){
&csiphy2_3p_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg0_clk = {
.halt_reg = 0x35a8,
.clkr = {
.enable_reg = 0x35a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg2_clk = {
.halt_reg = 0x35b0,
.clkr = {
.enable_reg = 0x35b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg2_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_dma_clk = {
.halt_reg = 0x35c0,
.clkr = {
.enable_reg = 0x35c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_dma_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg_dma_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
.clkr = {
.enable_reg = 0x35b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_axi_clk = {
.halt_reg = 0x35b8,
.clkr = {
.enable_reg = 0x35b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_ahb_clk = {
.halt_reg = 0x36b8,
.clkr = {
.enable_reg = 0x36b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_axi_clk = {
.halt_reg = 0x36bc,
.clkr = {
.enable_reg = 0x36bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_clk = {
.halt_reg = 0x36a8,
.clkr = {
.enable_reg = 0x36a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_stream_clk = {
.halt_reg = 0x3720,
.clkr = {
.enable_reg = 0x3720,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_stream_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_ahb_clk = {
.halt_reg = 0x3668,
.clkr = {
.enable_reg = 0x3668,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe1_clk = {
.halt_reg = 0x36ac,
.clkr = {
.enable_reg = 0x36ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe1_stream_clk = {
.halt_reg = 0x3724,
.clkr = {
.enable_reg = 0x3724,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_stream_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe1_ahb_clk = {
.halt_reg = 0x3678,
.clkr = {
.enable_reg = 0x3678,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe0_clk = {
.halt_reg = 0x3704,
.clkr = {
.enable_reg = 0x3704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe1_clk = {
.halt_reg = 0x3714,
.clkr = {
.enable_reg = 0x3714,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_vbif_ahb_clk = {
.halt_reg = 0x36c8,
.clkr = {
.enable_reg = 0x36c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_vbif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_axi_clk = {
.halt_reg = 0x36c4,
.clkr = {
.enable_reg = 0x36c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_clk = {
.halt_reg = 0x36b0,
.clkr = {
.enable_reg = 0x36b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_ahb_clk = {
.halt_reg = 0x36b4,
.clkr = {
.enable_reg = 0x36b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_clk = {
.halt_reg = 0x30b4,
.clkr = {
.enable_reg = 0x30b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_ahb_clk = {
.halt_reg = 0x30bc,
.clkr = {
.enable_reg = 0x30bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0phy_clk = {
.halt_reg = 0x30c4,
.clkr = {
.enable_reg = 0x30c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0rdi_clk = {
.halt_reg = 0x30d4,
.clkr = {
.enable_reg = 0x30d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0pix_clk = {
.halt_reg = 0x30e4,
.clkr = {
.enable_reg = 0x30e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_clk = {
.halt_reg = 0x3124,
.clkr = {
.enable_reg = 0x3124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_ahb_clk = {
.halt_reg = 0x3128,
.clkr = {
.enable_reg = 0x3128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1phy_clk = {
.halt_reg = 0x3134,
.clkr = {
.enable_reg = 0x3134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1rdi_clk = {
.halt_reg = 0x3144,
.clkr = {
.enable_reg = 0x3144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1pix_clk = {
.halt_reg = 0x3154,
.clkr = {
.enable_reg = 0x3154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_clk = {
.halt_reg = 0x3184,
.clkr = {
.enable_reg = 0x3184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_ahb_clk = {
.halt_reg = 0x3188,
.clkr = {
.enable_reg = 0x3188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2phy_clk = {
.halt_reg = 0x3194,
.clkr = {
.enable_reg = 0x3194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2rdi_clk = {
.halt_reg = 0x31a4,
.clkr = {
.enable_reg = 0x31a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2pix_clk = {
.halt_reg = 0x31b4,
.clkr = {
.enable_reg = 0x31b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_clk = {
.halt_reg = 0x31e4,
.clkr = {
.enable_reg = 0x31e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_ahb_clk = {
.halt_reg = 0x31e8,
.clkr = {
.enable_reg = 0x31e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3phy_clk = {
.halt_reg = 0x31f4,
.clkr = {
.enable_reg = 0x31f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3rdi_clk = {
.halt_reg = 0x3204,
.clkr = {
.enable_reg = 0x3204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3pix_clk = {
.halt_reg = 0x3214,
.clkr = {
.enable_reg = 0x3214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ispif_ahb_clk = {
.halt_reg = 0x3224,
.clkr = {
.enable_reg = 0x3224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_core_clk = {
.halt_reg = 0x3b68,
.clkr = {
.enable_reg = 0x3b68,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_core_clk",
.parent_hws = (const struct clk_hw*[]){
&fd_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_core_uar_clk = {
.halt_reg = 0x3b6c,
.clkr = {
.enable_reg = 0x3b6c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_core_uar_clk",
.parent_hws = (const struct clk_hw*[]){
&fd_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_ahb_clk = {
.halt_reg = 0x3ba74,
.clkr = {
.enable_reg = 0x3ba74,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *mmcc_msm8996_hws[] = {
&gpll0_div.hw,
};
static struct gdsc mmagic_bimc_gdsc = {
.gdscr = 0x529c,
.pd = {
.name = "mmagic_bimc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = ALWAYS_ON,
};
static struct gdsc mmagic_video_gdsc = {
.gdscr = 0x119c,
.gds_hw_ctrl = 0x120c,
.pd = {
.name = "mmagic_video",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc mmagic_mdss_gdsc = {
.gdscr = 0x247c,
.gds_hw_ctrl = 0x2480,
.pd = {
.name = "mmagic_mdss",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc mmagic_camss_gdsc = {
.gdscr = 0x3c4c,
.gds_hw_ctrl = 0x3c50,
.pd = {
.name = "mmagic_camss",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc venus_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
.cxc_count = 3,
.pd = {
.name = "venus",
},
.parent = &mmagic_video_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x1040,
.cxcs = (unsigned int []){ 0x1048 },
.cxc_count = 1,
.pd = {
.name = "venus_core0",
},
.parent = &venus_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc venus_core1_gdsc = {
.gdscr = 0x1044,
.cxcs = (unsigned int []){ 0x104c },
.cxc_count = 1,
.pd = {
.name = "venus_core1",
},
.parent = &venus_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc camss_gdsc = {
.gdscr = 0x34a0,
.cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
.cxc_count = 2,
.pd = {
.name = "camss",
},
.parent = &mmagic_camss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe0_gdsc = {
.gdscr = 0x3664,
.cxcs = (unsigned int []){ 0x36a8 },
.cxc_count = 1,
.pd = {
.name = "vfe0",
},
.parent = &camss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe1_gdsc = {
.gdscr = 0x3674,
.cxcs = (unsigned int []){ 0x36ac },
.cxc_count = 1,
.pd = {
.name = "vfe1",
},
.parent = &camss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x35a4,
.cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
.cxc_count = 4,
.pd = {
.name = "jpeg",
},
.parent = &camss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc cpp_gdsc = {
.gdscr = 0x36d4,
.cxcs = (unsigned int []){ 0x36b0 },
.cxc_count = 1,
.pd = {
.name = "cpp",
},
.parent = &camss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc fd_gdsc = {
.gdscr = 0x3b64,
.cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
.cxc_count = 2,
.pd = {
.name = "fd",
},
.parent = &camss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x2304,
.cxcs = (unsigned int []){ 0x2310, 0x231c },
.cxc_count = 2,
.pd = {
.name = "mdss",
},
.parent = &mmagic_mdss_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gpu_gdsc = {
.gdscr = 0x4034,
.gds_hw_ctrl = 0x4038,
.pd = {
.name = "gpu",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x4024,
.clamp_io_ctrl = 0x4300,
.cxcs = (unsigned int []){ 0x4028 },
.cxc_count = 1,
.pd = {
.name = "gpu_gx",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &gpu_gdsc.pd,
.flags = CLAMP_IO,
.supply = "vdd-gfx",
};
static struct clk_regmap *mmcc_msm8996_clocks[] = {
[MMPLL0_EARLY] = &mmpll0_early.clkr,
[MMPLL0_PLL] = &mmpll0.clkr,
[MMPLL1_EARLY] = &mmpll1_early.clkr,
[MMPLL1_PLL] = &mmpll1.clkr,
[MMPLL2_EARLY] = &mmpll2_early.clkr,
[MMPLL2_PLL] = &mmpll2.clkr,
[MMPLL3_EARLY] = &mmpll3_early.clkr,
[MMPLL3_PLL] = &mmpll3.clkr,
[MMPLL4_EARLY] = &mmpll4_early.clkr,
[MMPLL4_PLL] = &mmpll4.clkr,
[MMPLL5_EARLY] = &mmpll5_early.clkr,
[MMPLL5_PLL] = &mmpll5.clkr,
[MMPLL8_EARLY] = &mmpll8_early.clkr,
[MMPLL8_PLL] = &mmpll8.clkr,
[MMPLL9_EARLY] = &mmpll9_early.clkr,
[MMPLL9_PLL] = &mmpll9.clkr,
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
[AXI_CLK_SRC] = &axi_clk_src.clkr,
[MAXI_CLK_SRC] = &maxi_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[ISENSE_CLK_SRC] = &isense_clk_src.clkr,
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
[VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
[VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
[VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
[CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
[CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
[JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
[MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
[MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
[MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
[MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
[MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
[SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
[SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
[SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
[SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
[SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
[SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
[MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
[MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
[SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
[SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
[SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
[SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
[MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
[MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
[SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
[SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
[MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
[GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
[GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
[GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
[GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
[VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
[VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
[MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
[MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
[VIDEO_CORE_CLK] = &video_core_clk.clkr,
[VIDEO_AXI_CLK] = &video_axi_clk.clkr,
[VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
[VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
[VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
[VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
[CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
[CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
[CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
[CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
[CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
[CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
[CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
[CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
[CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
[CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
[CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
[CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
[CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
[CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
[CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
[CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
[CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
[CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
[CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
[CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
[CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
[CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
[CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
[CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[FD_CORE_CLK] = &fd_core_clk.clkr,
[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
[FD_AHB_CLK] = &fd_ahb_clk.clkr,
};
static struct gdsc *mmcc_msm8996_gdscs[] = {
[MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
[MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
[MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
[MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
[VENUS_GDSC] = &venus_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
[CAMSS_GDSC] = &camss_gdsc,
[VFE0_GDSC] = &vfe0_gdsc,
[VFE1_GDSC] = &vfe1_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[CPP_GDSC] = &cpp_gdsc,
[FD_GDSC] = &fd_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[GPU_GDSC] = &gpu_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct qcom_reset_map mmcc_msm8996_resets[] = {
[MMAGICAHB_BCR] = { 0x5020 },
[MMAGIC_CFG_BCR] = { 0x5050 },
[MISC_BCR] = { 0x5010 },
[BTO_BCR] = { 0x5030 },
[MMAGICAXI_BCR] = { 0x5060 },
[MMAGICMAXI_BCR] = { 0x5070 },
[DSA_BCR] = { 0x50a0 },
[MMAGIC_CAMSS_BCR] = { 0x3c40 },
[THROTTLE_CAMSS_BCR] = { 0x3c30 },
[SMMU_VFE_BCR] = { 0x3c00 },
[SMMU_CPP_BCR] = { 0x3c10 },
[SMMU_JPEG_BCR] = { 0x3c20 },
[MMAGIC_MDSS_BCR] = { 0x2470 },
[THROTTLE_MDSS_BCR] = { 0x2460 },
[SMMU_ROT_BCR] = { 0x2440 },
[SMMU_MDP_BCR] = { 0x2450 },
[MMAGIC_VIDEO_BCR] = { 0x1190 },
[THROTTLE_VIDEO_BCR] = { 0x1180 },
[SMMU_VIDEO_BCR] = { 0x1170 },
[MMAGIC_BIMC_BCR] = { 0x5290 },
[GPU_GX_BCR] = { 0x4020 },
[GPU_BCR] = { 0x4030 },
[GPU_AON_BCR] = { 0x4040 },
[VMEM_BCR] = { 0x1200 },
[MMSS_RBCPR_BCR] = { 0x4080 },
[VIDEO_BCR] = { 0x1020 },
[MDSS_BCR] = { 0x2300 },
[CAMSS_TOP_BCR] = { 0x3480 },
[CAMSS_AHB_BCR] = { 0x3488 },
[CAMSS_MICRO_BCR] = { 0x3490 },
[CAMSS_CCI_BCR] = { 0x3340 },
[CAMSS_PHY0_BCR] = { 0x3020 },
[CAMSS_PHY1_BCR] = { 0x3050 },
[CAMSS_PHY2_BCR] = { 0x3080 },
[CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
[CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
[CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
[CAMSS_JPEG_BCR] = { 0x35a0 },
[CAMSS_VFE_BCR] = { 0x36a0 },
[CAMSS_VFE0_BCR] = { 0x3660 },
[CAMSS_VFE1_BCR] = { 0x3670 },
[CAMSS_CSI_VFE0_BCR] = { 0x3700 },
[CAMSS_CSI_VFE1_BCR] = { 0x3710 },
[CAMSS_CPP_TOP_BCR] = { 0x36c0 },
[CAMSS_CPP_BCR] = { 0x36d0 },
[CAMSS_CSI0_BCR] = { 0x30b0 },
[CAMSS_CSI0RDI_BCR] = { 0x30d0 },
[CAMSS_CSI0PIX_BCR] = { 0x30e0 },
[CAMSS_CSI1_BCR] = { 0x3120 },
[CAMSS_CSI1RDI_BCR] = { 0x3140 },
[CAMSS_CSI1PIX_BCR] = { 0x3150 },
[CAMSS_CSI2_BCR] = { 0x3180 },
[CAMSS_CSI2RDI_BCR] = { 0x31a0 },
[CAMSS_CSI2PIX_BCR] = { 0x31b0 },
[CAMSS_CSI3_BCR] = { 0x31e0 },
[CAMSS_CSI3RDI_BCR] = { 0x3200 },
[CAMSS_CSI3PIX_BCR] = { 0x3210 },
[CAMSS_ISPIF_BCR] = { 0x3220 },
[FD_BCR] = { 0x3b60 },
[MMSS_SPDM_RM_BCR] = { 0x300 },
};
static const struct regmap_config mmcc_msm8996_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xb008,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_msm8996_desc = {
.config = &mmcc_msm8996_regmap_config,
.clks = mmcc_msm8996_clocks,
.num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
.resets = mmcc_msm8996_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
.gdscs = mmcc_msm8996_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
.clk_hws = mmcc_msm8996_hws,
.num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
};
static const struct of_device_id mmcc_msm8996_match_table[] = {
{ .compatible = "qcom,mmcc-msm8996" },
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
static int mmcc_msm8996_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Disable the AHB DCD */
regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
/* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
regmap_update_bits(regmap, 0x5054, BIT(15), 0);
return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
}
static struct platform_driver mmcc_msm8996_driver = {
.probe = mmcc_msm8996_probe,
.driver = {
.name = "mmcc-msm8996",
.of_match_table = mmcc_msm8996_match_table,
},
};
module_platform_driver(mmcc_msm8996_driver);
MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mmcc-msm8996");
| linux-master | drivers/clk/qcom/mmcc-msm8996.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
enum {
P_XO,
P_APSS_PLL_EARLY,
};
static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
{ .fw_name = "xo" },
{ .fw_name = "pll" },
};
static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
{ P_XO, 0 },
{ P_APSS_PLL_EARLY, 5 },
};
static struct clk_rcg2 apcs_alias0_clk_src = {
.cmd_rcgr = 0x0050,
.hid_width = 5,
.parent_map = parents_apcs_alias0_clk_src_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apcs_alias0_clk_src",
.parent_data = parents_apcs_alias0_clk_src,
.num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
.ops = &clk_rcg2_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_branch apcs_alias0_core_clk = {
.halt_reg = 0x0058,
.clkr = {
.enable_reg = 0x0058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "apcs_alias0_core_clk",
.parent_hws = (const struct clk_hw *[]){
&apcs_alias0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static const struct regmap_config apss_ipq6018_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1000,
.fast_io = true,
};
static struct clk_regmap *apss_ipq6018_clks[] = {
[APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
[APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
};
static const struct qcom_cc_desc apss_ipq6018_desc = {
.config = &apss_ipq6018_regmap_config,
.clks = apss_ipq6018_clks,
.num_clks = ARRAY_SIZE(apss_ipq6018_clks),
};
static int apss_ipq6018_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
return -ENODEV;
return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
}
static struct platform_driver apss_ipq6018_driver = {
.probe = apss_ipq6018_probe,
.driver = {
.name = "qcom,apss-ipq6018-clk",
},
};
module_platform_driver(apss_ipq6018_driver);
MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/apss-ipq6018.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,camcc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL0_OUT_MAIN,
P_CAM_CC_PLL0_OUT_ODD,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_AUX2,
P_CAM_CC_PLL2_OUT_EARLY,
P_CAM_CC_PLL3_OUT_EVEN,
P_CAM_CC_PLL4_OUT_EVEN,
P_CAM_CC_PLL5_OUT_EVEN,
P_CAM_CC_PLL6_OUT_EVEN,
P_CAM_CC_PLL6_OUT_MAIN,
P_CAM_CC_PLL6_OUT_ODD,
P_SLEEP_CLK,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct pll_vco zonda_vco[] = {
{ 595200000UL, 3600000000UL, 0 },
};
/* 1200MHz Configuration */
static const struct alpha_pll_config cam_cc_pll0_config = {
.l = 0x3E,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00003101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
{ 0x3, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
.offset = 0x0,
.post_div_shift = 12,
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
/* 600MHz Configuration */
static const struct alpha_pll_config cam_cc_pll1_config = {
.l = 0x1F,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
/* 1440MHz Configuration */
static const struct alpha_pll_config cam_cc_pll2_config = {
.l = 0x4B,
.alpha = 0x0,
.config_ctl_val = 0x08200800,
.config_ctl_hi_val = 0x05022011,
.config_ctl_hi1_val = 0x08000000,
.user_ctl_val = 0x00000301,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = zonda_vco,
.num_vco = ARRAY_SIZE(zonda_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_zonda_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = {
{ 0x3, 4 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
.offset = 0x2000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll2_out_aux,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_aux",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_zonda_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = {
{ 0x3, 4 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = {
.offset = 0x2000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll2_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_aux2",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_zonda_ops,
},
};
/* 760MHz Configuration */
static const struct alpha_pll_config cam_cc_pll3_config = {
.l = 0x27,
.alpha = 0x9555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.offset = 0x3000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
/* 760MHz Configuration */
static const struct alpha_pll_config cam_cc_pll4_config = {
.l = 0x27,
.alpha = 0x9555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
.offset = 0x4000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll4_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll4_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
/* 760MHz Configuration */
static const struct alpha_pll_config cam_cc_pll5_config = {
.l = 0x27,
.alpha = 0x9555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll5 = {
.offset = 0x5000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll5",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
.offset = 0x5000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll5_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll5_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll5.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
/* 960MHz Configuration */
static const struct alpha_pll_config cam_cc_pll6_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00003101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll6 = {
.offset = 0x6000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
.offset = 0x6000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll6_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = {
{ 0x3, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = {
.offset = 0x6000,
.post_div_shift = 12,
.post_div_table = post_div_table_cam_cc_pll6_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll6_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL6_OUT_EVEN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL6_OUT_MAIN, 4 },
{ P_CAM_CC_PLL6_OUT_EVEN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll6.clkr.hw },
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_AUX2, 3 },
{ P_CAM_CC_PLL2_OUT_EARLY, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll2_out_aux2.clkr.hw },
{ .hw = &cam_cc_pll2.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL6_OUT_EVEN, 5 },
{ P_CAM_CC_PLL6_OUT_ODD, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
{ .hw = &cam_cc_pll6_out_odd.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll5_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
};
static const struct clk_parent_data cam_cc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_8[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_8[] = {
{ .fw_name = "sleep_clk" },
};
static const struct parent_map cam_cc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_ODD, 4, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x7010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0),
F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
.cmd_rcgr = 0xc124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0xc0e0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.cmd_rcgr = 0xc0fc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0xa064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0xe0ac,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0xe0d0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0xe0f4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0xe11c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
.cmd_rcgr = 0xe140,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi4phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x703c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0xc0b8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(380000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(510000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0xa010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(380000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(510000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0xb010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.cmd_rcgr = 0xa03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.cmd_rcgr = 0xb03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(380000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(510000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_2_clk_src = {
.cmd_rcgr = 0xb07c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_6,
.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_clk_src",
.parent_data = cam_cc_parent_data_6,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = {
.cmd_rcgr = 0xb0a8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_csid_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = {
.cmd_rcgr = 0xc004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = {
.cmd_rcgr = 0xc020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_csid_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = {
.cmd_rcgr = 0xc048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = {
.cmd_rcgr = 0xc064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_csid_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(430000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.cmd_rcgr = 0x8010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_7,
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_data = cam_cc_parent_data_7,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0xc08c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_lrme_clk_src = {
.cmd_rcgr = 0xc150,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_lrme_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 75),
F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
F(34285714, P_CAM_CC_PLL2_OUT_EARLY, 2, 1, 21),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0xe000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0xe01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0xe038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0xe054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.cmd_rcgr = 0xe070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
.cmd_rcgr = 0xe08c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk5_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sleep_clk_src = {
.cmd_rcgr = 0xc1c0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_8,
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_sleep_clk_src",
.parent_data = cam_cc_parent_data_8,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x7058,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_xo_clk_src = {
.cmd_rcgr = 0xc1a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_9,
.freq_tbl = ftbl_cam_cc_xo_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_xo_clk_src",
.parent_data = cam_cc_parent_data_9_ao,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x7070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_areg_clk = {
.halt_reg = 0x7054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_areg_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_axi_clk = {
.halt_reg = 0x7038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x7028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_clk = {
.halt_reg = 0xc140,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc140,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
.halt_reg = 0xc148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc148,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_dcd_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0xc0f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0f8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_1_clk = {
.halt_reg = 0xc114,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_core_ahb_clk = {
.halt_reg = 0xc1a0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xc1a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_core_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0xc11c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc11c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0xe0c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe0c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0xe0e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe0e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0xe10c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe10c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0xe134,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi4phytimer_clk = {
.halt_reg = 0xe158,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe158,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi4phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi4phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0xe0c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe0c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0xe0ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe0ec,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0xe110,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0xe138,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe138,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy4_clk = {
.halt_reg = 0xe15c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe15c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_gdsc_clk = {
.halt_reg = 0xc1bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc1bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_gdsc_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_ahb_clk = {
.halt_reg = 0xc0d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0d8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0xc0d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_axi_clk = {
.halt_reg = 0xa080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0xa028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
.halt_reg = 0xa07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_csid_clk = {
.halt_reg = 0xa054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_dsp_clk = {
.halt_reg = 0xa038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_dsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_axi_clk = {
.halt_reg = 0xb068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
.halt_reg = 0xb064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_csid_clk = {
.halt_reg = 0xb054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_dsp_clk = {
.halt_reg = 0xb038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_dsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_axi_clk = {
.halt_reg = 0xb0d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_clk = {
.halt_reg = 0xb094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_cphy_rx_clk = {
.halt_reg = 0xb0d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_csid_clk = {
.halt_reg = 0xb0c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_dsp_clk = {
.halt_reg = 0xb0a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_dsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_0_clk = {
.halt_reg = 0xc01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = {
.halt_reg = 0xc040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_0_csid_clk = {
.halt_reg = 0xc038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_1_clk = {
.halt_reg = 0xc060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = {
.halt_reg = 0xc084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_1_csid_clk = {
.halt_reg = 0xc07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_ahb_clk = {
.halt_reg = 0x8040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_areg_clk = {
.halt_reg = 0x803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_areg_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_axi_clk = {
.halt_reg = 0x8038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_clk = {
.halt_reg = 0x8028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0xc0a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_lrme_clk = {
.halt_reg = 0xc168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_lrme_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0xe018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0xe034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0xe050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0xe06c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe06c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk4_clk = {
.halt_reg = 0xe088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk5_clk = {
.halt_reg = 0xe0a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sleep_clk = {
.halt_reg = 0xc1d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc1d8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc cam_cc_titan_top_gdsc = {
.gdscr = 0xc194,
.pd = {
.name = "cam_cc_titan_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_bps_gdsc = {
.gdscr = 0x7004,
.pd = {
.name = "cam_cc_bps_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ife_0_gdsc = {
.gdscr = 0xa004,
.pd = {
.name = "cam_cc_ife_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ife_1_gdsc = {
.gdscr = 0xb004,
.pd = {
.name = "cam_cc_ife_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ife_2_gdsc = {
.gdscr = 0xb070,
.pd = {
.name = "cam_cc_ife_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc cam_cc_ipe_0_gdsc = {
.gdscr = 0x8004,
.pd = {
.name = "cam_cc_ipe_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *cam_cc_sc7280_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
[CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr,
[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
[CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr,
[CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr,
[CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr,
[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
[CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr,
[CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr,
[CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr,
[CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr,
[CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr,
[CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr,
[CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr,
[CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr,
[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr,
[CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
[CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr,
[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
};
static struct gdsc *cam_cc_sc7280_gdscs[] = {
[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
[CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
[CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
[CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
[CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
[CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
};
static const struct regmap_config cam_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xf00c,
.fast_io = true,
};
static const struct qcom_cc_desc cam_cc_sc7280_desc = {
.config = &cam_cc_sc7280_regmap_config,
.clks = cam_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sc7280_clocks),
.gdscs = cam_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sc7280_gdscs),
};
static const struct of_device_id cam_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sc7280_match_table);
static int cam_cc_sc7280_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &cam_cc_sc7280_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap);
}
static struct platform_driver cam_cc_sc7280_driver = {
.probe = cam_cc_sc7280_probe,
.driver = {
.name = "cam_cc-sc7280",
.of_match_table = cam_cc_sc7280_match_table,
},
};
static int __init cam_cc_sc7280_init(void)
{
return platform_driver_register(&cam_cc_sc7280_driver);
}
subsys_initcall(cam_cc_sc7280_init);
static void __exit cam_cc_sc7280_exit(void)
{
platform_driver_unregister(&cam_cc_sc7280_driver);
}
module_exit(cam_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/camcc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
.halt_reg = 0x0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_top_cc_lpi_q6_axim_hs_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_core_clk = {
.halt_reg = 0x20,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_xo_clk = {
.halt_reg = 0x38,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x38,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_sleep_clk = {
.halt_reg = 0x3c,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct regmap_config lpass_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
[LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
&lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
};
static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
.config = &lpass_regmap_config,
.clks = lpass_cc_top_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
};
static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
};
static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
.config = &lpass_regmap_config,
.clks = lpass_qdsp6ss_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
};
static int lpass_cc_sc7280_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, "iface");
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire iface clock\n");
goto err_destroy_pm_clk;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
goto err_destroy_pm_clk;
if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
lpass_regmap_config.name = "qdsp6ss";
lpass_regmap_config.max_register = 0x3f;
desc = &lpass_qdsp6ss_sc7280_desc;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
goto err_put_rpm;
}
lpass_regmap_config.name = "top_cc";
lpass_regmap_config.max_register = 0x4;
desc = &lpass_cc_top_sc7280_desc;
ret = qcom_cc_probe_by_index(pdev, 1, desc);
if (ret)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
err_destroy_pm_clk:
pm_clk_destroy(&pdev->dev);
return ret;
}
static const struct of_device_id lpass_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpasscc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);
static struct platform_driver lpass_cc_sc7280_driver = {
.probe = lpass_cc_sc7280_probe,
.driver = {
.name = "sc7280-lpasscc",
.of_match_table = lpass_cc_sc7280_match_table,
},
};
static int __init lpass_cc_sc7280_init(void)
{
return platform_driver_register(&lpass_cc_sc7280_driver);
}
subsys_initcall(lpass_cc_sc7280_init);
static void __exit lpass_cc_sc7280_exit(void)
{
platform_driver_unregister(&lpass_cc_sc7280_driver);
}
module_exit(lpass_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/lpasscc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/export.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/delay.h>
#include "reset.h"
static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
{
struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
rcdev->ops->assert(rcdev, id);
fsleep(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
rcdev->ops->deassert(rcdev, id);
return 0;
}
static int
qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
u32 mask;
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, mask);
}
static int
qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
u32 mask;
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, 0);
}
const struct reset_control_ops qcom_reset_ops = {
.reset = qcom_reset,
.assert = qcom_reset_assert,
.deassert = qcom_reset_deassert,
};
EXPORT_SYMBOL_GPL(qcom_reset_ops);
| linux-master | drivers/clk/qcom/reset.c |
// SPDX-License-Identifier: GPL-2.0
/*
* LPASS Audio CC and Always ON CC Glitch Free Mux clock driver
*
* Copyright (c) 2020 Linaro Ltd.
* Author: Srinivas Kandagatla <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
struct lpass_gfm {
struct device *dev;
void __iomem *base;
};
struct clk_gfm {
unsigned int mux_reg;
unsigned int mux_mask;
struct clk_hw hw;
struct lpass_gfm *priv;
void __iomem *gfm_mux;
};
#define to_clk_gfm(_hw) container_of(_hw, struct clk_gfm, hw)
static u8 clk_gfm_get_parent(struct clk_hw *hw)
{
struct clk_gfm *clk = to_clk_gfm(hw);
return readl(clk->gfm_mux) & clk->mux_mask;
}
static int clk_gfm_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_gfm *clk = to_clk_gfm(hw);
unsigned int val;
val = readl(clk->gfm_mux);
if (index)
val |= clk->mux_mask;
else
val &= ~clk->mux_mask;
writel(val, clk->gfm_mux);
return 0;
}
static const struct clk_ops clk_gfm_ops = {
.get_parent = clk_gfm_get_parent,
.set_parent = clk_gfm_set_parent,
.determine_rate = __clk_mux_determine_rate,
};
static struct clk_gfm lpass_gfm_va_mclk = {
.mux_reg = 0x20000,
.mux_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "VA_MCLK",
.ops = &clk_gfm_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.num_parents = 2,
.parent_data = (const struct clk_parent_data[]){
{
.index = 0,
.fw_name = "LPASS_CLK_ID_TX_CORE_MCLK",
}, {
.index = 1,
.fw_name = "LPASS_CLK_ID_VA_CORE_MCLK",
},
},
},
};
static struct clk_gfm lpass_gfm_tx_npl = {
.mux_reg = 0x20000,
.mux_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "TX_NPL",
.ops = &clk_gfm_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.parent_data = (const struct clk_parent_data[]){
{
.index = 0,
.fw_name = "LPASS_CLK_ID_TX_CORE_NPL_MCLK",
}, {
.index = 1,
.fw_name = "LPASS_CLK_ID_VA_CORE_2X_MCLK",
},
},
.num_parents = 2,
},
};
static struct clk_gfm lpass_gfm_wsa_mclk = {
.mux_reg = 0x220d8,
.mux_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "WSA_MCLK",
.ops = &clk_gfm_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.parent_data = (const struct clk_parent_data[]){
{
.index = 0,
.fw_name = "LPASS_CLK_ID_TX_CORE_MCLK",
}, {
.index = 1,
.fw_name = "LPASS_CLK_ID_WSA_CORE_MCLK",
},
},
.num_parents = 2,
},
};
static struct clk_gfm lpass_gfm_wsa_npl = {
.mux_reg = 0x220d8,
.mux_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "WSA_NPL",
.ops = &clk_gfm_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.parent_data = (const struct clk_parent_data[]){
{
.index = 0,
.fw_name = "LPASS_CLK_ID_TX_CORE_NPL_MCLK",
}, {
.index = 1,
.fw_name = "LPASS_CLK_ID_WSA_CORE_NPL_MCLK",
},
},
.num_parents = 2,
},
};
static struct clk_gfm lpass_gfm_rx_mclk_mclk2 = {
.mux_reg = 0x240d8,
.mux_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "RX_MCLK_MCLK2",
.ops = &clk_gfm_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.parent_data = (const struct clk_parent_data[]){
{
.index = 0,
.fw_name = "LPASS_CLK_ID_TX_CORE_MCLK",
}, {
.index = 1,
.fw_name = "LPASS_CLK_ID_RX_CORE_MCLK",
},
},
.num_parents = 2,
},
};
static struct clk_gfm lpass_gfm_rx_npl = {
.mux_reg = 0x240d8,
.mux_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "RX_NPL",
.ops = &clk_gfm_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.parent_data = (const struct clk_parent_data[]){
{
.index = 0,
.fw_name = "LPASS_CLK_ID_TX_CORE_NPL_MCLK",
}, {
.index = 1,
.fw_name = "LPASS_CLK_ID_RX_CORE_NPL_MCLK",
},
},
.num_parents = 2,
},
};
static struct clk_gfm *aoncc_gfm_clks[] = {
[LPASS_CDC_VA_MCLK] = &lpass_gfm_va_mclk,
[LPASS_CDC_TX_NPL] = &lpass_gfm_tx_npl,
};
static struct clk_hw_onecell_data aoncc_hw_onecell_data = {
.hws = {
[LPASS_CDC_VA_MCLK] = &lpass_gfm_va_mclk.hw,
[LPASS_CDC_TX_NPL] = &lpass_gfm_tx_npl.hw,
},
.num = ARRAY_SIZE(aoncc_gfm_clks),
};
static struct clk_gfm *audiocc_gfm_clks[] = {
[LPASS_CDC_WSA_NPL] = &lpass_gfm_wsa_npl,
[LPASS_CDC_WSA_MCLK] = &lpass_gfm_wsa_mclk,
[LPASS_CDC_RX_NPL] = &lpass_gfm_rx_npl,
[LPASS_CDC_RX_MCLK_MCLK2] = &lpass_gfm_rx_mclk_mclk2,
};
static struct clk_hw_onecell_data audiocc_hw_onecell_data = {
.hws = {
[LPASS_CDC_WSA_NPL] = &lpass_gfm_wsa_npl.hw,
[LPASS_CDC_WSA_MCLK] = &lpass_gfm_wsa_mclk.hw,
[LPASS_CDC_RX_NPL] = &lpass_gfm_rx_npl.hw,
[LPASS_CDC_RX_MCLK_MCLK2] = &lpass_gfm_rx_mclk_mclk2.hw,
},
.num = ARRAY_SIZE(audiocc_gfm_clks),
};
struct lpass_gfm_data {
struct clk_hw_onecell_data *onecell_data;
struct clk_gfm **gfm_clks;
};
static struct lpass_gfm_data audiocc_data = {
.onecell_data = &audiocc_hw_onecell_data,
.gfm_clks = audiocc_gfm_clks,
};
static struct lpass_gfm_data aoncc_data = {
.onecell_data = &aoncc_hw_onecell_data,
.gfm_clks = aoncc_gfm_clks,
};
static int lpass_gfm_clk_driver_probe(struct platform_device *pdev)
{
const struct lpass_gfm_data *data;
struct device *dev = &pdev->dev;
struct clk_gfm *gfm;
struct lpass_gfm *cc;
int err, i;
data = of_device_get_match_data(dev);
if (!data)
return -EINVAL;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
cc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(cc->base))
return PTR_ERR(cc->base);
err = devm_pm_runtime_enable(dev);
if (err)
return err;
err = devm_pm_clk_create(dev);
if (err)
return err;
err = of_pm_clk_add_clks(dev);
if (err < 0) {
dev_dbg(dev, "Failed to get lpass core voting clocks\n");
return err;
}
for (i = 0; i < data->onecell_data->num; i++) {
if (!data->gfm_clks[i])
continue;
gfm = data->gfm_clks[i];
gfm->priv = cc;
gfm->gfm_mux = cc->base;
gfm->gfm_mux = gfm->gfm_mux + data->gfm_clks[i]->mux_reg;
err = devm_clk_hw_register(dev, &data->gfm_clks[i]->hw);
if (err)
return err;
}
err = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
data->onecell_data);
if (err)
return err;
return 0;
}
static const struct of_device_id lpass_gfm_clk_match_table[] = {
{
.compatible = "qcom,sm8250-lpass-aoncc",
.data = &aoncc_data,
},
{
.compatible = "qcom,sm8250-lpass-audiocc",
.data = &audiocc_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpass_gfm_clk_match_table);
static const struct dev_pm_ops lpass_gfm_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver lpass_gfm_clk_driver = {
.probe = lpass_gfm_clk_driver_probe,
.driver = {
.name = "lpass-gfm-clk",
.of_match_table = lpass_gfm_clk_match_table,
.pm = &lpass_gfm_pm_ops,
},
};
module_platform_driver(lpass_gfm_clk_driver);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/lpass-gfm-sm8250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-hfpll.h"
#include "reset.h"
static const struct clk_parent_data gcc_pxo[] = {
{ .fw_name = "pxo", .name = "pxo" },
};
static struct clk_pll pll0 = {
.l_reg = 0x30c4,
.m_reg = 0x30c8,
.n_reg = 0x30cc,
.config_reg = 0x30d4,
.mode_reg = 0x30c0,
.status_reg = 0x30d8,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll0",
.parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll0_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pll0_vote",
.parent_hws = (const struct clk_hw*[]){
&pll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll pll3 = {
.l_reg = 0x3164,
.m_reg = 0x3168,
.n_reg = 0x316c,
.config_reg = 0x3174,
.mode_reg = 0x3160,
.status_reg = 0x3178,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll3",
.parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll4_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pll4_vote",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pll4", .name = "pll4",
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll pll8 = {
.l_reg = 0x3144,
.m_reg = 0x3148,
.n_reg = 0x314c,
.config_reg = 0x3154,
.mode_reg = 0x3140,
.status_reg = 0x3158,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
.parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll8_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
.parent_hws = (const struct clk_hw*[]){
&pll8.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct hfpll_data hfpll0_data = {
.mode_reg = 0x3200,
.l_reg = 0x3208,
.m_reg = 0x320c,
.n_reg = 0x3210,
.config_reg = 0x3204,
.status_reg = 0x321c,
.config_val = 0x7845c665,
.droop_reg = 0x3214,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll0 = {
.d = &hfpll0_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll0",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
};
static struct hfpll_data hfpll1_data = {
.mode_reg = 0x3240,
.l_reg = 0x3248,
.m_reg = 0x324c,
.n_reg = 0x3250,
.config_reg = 0x3244,
.status_reg = 0x325c,
.config_val = 0x7845c665,
.droop_reg = 0x3314,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll1 = {
.d = &hfpll1_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll1",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
};
static struct hfpll_data hfpll_l2_data = {
.mode_reg = 0x3300,
.l_reg = 0x3308,
.m_reg = 0x330c,
.n_reg = 0x3310,
.config_reg = 0x3304,
.status_reg = 0x331c,
.config_val = 0x7845c665,
.droop_reg = 0x3314,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll_l2 = {
.d = &hfpll_l2_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll_l2",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
};
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
.n_reg = 0x31cc,
.config_reg = 0x31d4,
.mode_reg = 0x31c0,
.status_reg = 0x31d8,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll14",
.parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll14_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "pll14_vote",
.parent_hws = (const struct clk_hw*[]){
&pll14.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
#define NSS_PLL_RATE(f, _l, _m, _n, i) \
{ \
.freq = f, \
.l = _l, \
.m = _m, \
.n = _n, \
.ibits = i, \
}
static struct pll_freq_tbl pll18_freq_tbl[] = {
NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
};
static struct clk_pll pll18 = {
.l_reg = 0x31a4,
.m_reg = 0x31a8,
.n_reg = 0x31ac,
.config_reg = 0x31b4,
.mode_reg = 0x31a0,
.status_reg = 0x31b8,
.status_bit = 16,
.post_div_shift = 16,
.post_div_width = 1,
.freq_tbl = pll18_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll18",
.parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_pll pll11 = {
.l_reg = 0x3184,
.m_reg = 0x3188,
.n_reg = 0x318c,
.config_reg = 0x3194,
.mode_reg = 0x3180,
.status_reg = 0x3198,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll11",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
enum {
P_PXO,
P_PLL8,
P_PLL3,
P_PLL0,
P_CXO,
P_PLL14,
P_PLL18,
P_PLL11,
};
static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 }
};
static const struct clk_parent_data gcc_pxo_pll8[] = {
{ .fw_name = "pxo", .name = "pxo" },
{ .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_CXO, 5 }
};
static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
{ .fw_name = "pxo", .name = "pxo" },
{ .hw = &pll8_vote.hw },
{ .fw_name = "cxo", .name = "cxo" },
};
static const struct parent_map gcc_pxo_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL3, 1 }
};
static const struct parent_map gcc_pxo_pll3_sata_map[] = {
{ P_PXO, 0 },
{ P_PLL3, 6 }
};
static const struct clk_parent_data gcc_pxo_pll3[] = {
{ .fw_name = "pxo", .name = "pxo" },
{ .hw = &pll3.clkr.hw },
};
static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_PLL0, 2 }
};
static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
{ .fw_name = "pxo", .name = "pxo" },
{ .hw = &pll8_vote.hw },
{ .hw = &pll0_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 4 },
{ P_PLL0, 2 },
{ P_PLL14, 5 },
{ P_PLL18, 1 }
};
static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
{ .fw_name = "pxo", .name = "pxo" },
{ .hw = &pll8_vote.hw },
{ .hw = &pll0_vote.hw },
{ .hw = &pll14.clkr.hw },
{ .hw = &pll18.clkr.hw },
};
static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 4 },
{ P_PLL0, 2 },
{ P_PLL14, 5 },
{ P_PLL18, 1 },
{ P_PLL11, 3 },
};
static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
{ .fw_name = "pxo" },
{ .hw = &pll8_vote.hw },
{ .hw = &pll0_vote.hw },
{ .hw = &pll14.clkr.hw },
{ .hw = &pll18.clkr.hw },
{ .hw = &pll11.clkr.hw },
};
static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
{ P_PXO, 0 },
{ P_PLL3, 6 },
{ P_PLL0, 2 },
{ P_PLL14, 5 },
{ P_PLL18, 1 },
{ P_PLL11, 3 },
};
static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
{ .fw_name = "pxo" },
{ .hw = &pll3.clkr.hw },
{ .hw = &pll0_vote.hw },
{ .hw = &pll14.clkr.hw },
{ .hw = &pll18.clkr.hw },
{ .hw = &pll11.clkr.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
{ 14745600, P_PLL8, 2, 48, 625 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 32000000, P_PLL8, 4, 1, 3 },
{ 40000000, P_PLL8, 1, 5, 48 },
{ 46400000, P_PLL8, 1, 29, 240 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ 56000000, P_PLL8, 1, 7, 48 },
{ 58982400, P_PLL8, 1, 96, 625 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ }
};
static struct clk_rcg gsbi1_uart_src = {
.ns_reg = 0x29d4,
.md_reg = 0x29d0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_uart_src = {
.ns_reg = 0x29f4,
.md_reg = 0x29f0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_uart_src = {
.ns_reg = 0x2a34,
.md_reg = 0x2a30,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_uart_src = {
.ns_reg = 0x2a54,
.md_reg = 0x2a50,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi6_uart_src = {
.ns_reg = 0x2a74,
.md_reg = 0x2a70,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a74,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi6_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2a74,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi7_uart_src = {
.ns_reg = 0x2a94,
.md_reg = 0x2a90,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a94,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi7_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2a94,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 1100000, P_PXO, 1, 2, 49 },
{ 5400000, P_PXO, 1, 1, 5 },
{ 10800000, P_PXO, 1, 2, 5 },
{ 15060000, P_PLL8, 1, 2, 51 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 25000000, P_PXO, 1, 0, 0 },
{ 25600000, P_PLL8, 1, 1, 15 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ }
};
static struct clk_rcg gsbi1_qup_src = {
.ns_reg = 0x29cc,
.md_reg = 0x29c8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_qup_src = {
.ns_reg = 0x29ec,
.md_reg = 0x29e8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_qup_src = {
.ns_reg = 0x2a2c,
.md_reg = 0x2a28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch gsbi4_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_rcg gsbi5_qup_src = {
.ns_reg = 0x2a4c,
.md_reg = 0x2a48,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi6_qup_src = {
.ns_reg = 0x2a6c,
.md_reg = 0x2a68,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a6c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch gsbi6_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x2a6c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi7_qup_src = {
.ns_reg = 0x2a8c,
.md_reg = 0x2a88,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a8c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi7_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2a8c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch gsbi1_h_clk = {
.hwcg_reg = 0x29c0,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x29c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi2_h_clk = {
.hwcg_reg = 0x29e0,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x29e0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi4_h_clk = {
.hwcg_reg = 0x2a20,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2a20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch gsbi5_h_clk = {
.hwcg_reg = 0x2a40,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x2a40,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi6_h_clk = {
.hwcg_reg = 0x2a60,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2a60,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi7_h_clk = {
.hwcg_reg = 0x2a80,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2a80,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_h_clk",
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_gp[] = {
{ 12500000, P_PXO, 2, 0, 0 },
{ 25000000, P_PXO, 1, 0, 0 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ 76800000, P_PLL8, 1, 1, 5 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 128000000, P_PLL8, 3, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
{ }
};
static struct clk_rcg gp0_src = {
.ns_reg = 0x2d24,
.md_reg = 0x2d00,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
}
};
static struct clk_branch gp0_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&gp0_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp1_src = {
.ns_reg = 0x2d44,
.md_reg = 0x2d40,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp1_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp2_src = {
.ns_reg = 0x2d64,
.md_reg = 0x2d60,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp2_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pmem_clk = {
.hwcg_reg = 0x25a0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x25a0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pmem_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg prng_src = {
.ns_reg = 0x2e80,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.clkr = {
.enable_reg = 0x2e80,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch prng_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
.parent_hws = (const struct clk_hw*[]){
&prng_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_sdc[] = {
{ 200000, P_PXO, 2, 2, 125 },
{ 400000, P_PLL8, 4, 1, 240 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 17070000, P_PLL8, 1, 2, 45 },
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ 64000000, P_PLL8, 3, 1, 2 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
{ }
};
static struct clk_rcg sdc1_src = {
.ns_reg = 0x282c,
.md_reg = 0x2828,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_floor_ops,
},
}
};
static struct clk_branch sdc1_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc3_src = {
.ns_reg = 0x286c,
.md_reg = 0x2868,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x286c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc3_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x286c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc3_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc3_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch sdc1_h_clk = {
.hwcg_reg = 0x2820,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2820,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc3_h_clk = {
.hwcg_reg = 0x2860,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x2860,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_tsif_ref[] = {
{ 105000, P_PXO, 1, 1, 256 },
{ }
};
static struct clk_rcg tsif_ref_src = {
.ns_reg = 0x2710,
.md_reg = 0x270c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_tsif_ref,
.clkr = {
.enable_reg = 0x2710,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch tsif_ref_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2710,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch tsif_h_clk = {
.hwcg_reg = 0x2700,
.hwcg_bit = 6,
.halt_reg = 0x2fd4,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2700,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "tsif_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dma_bam_h_clk = {
.hwcg_reg = 0x25c0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x25c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "dma_bam_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_clk = {
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "adm0_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_pbus_clk = {
.hwcg_reg = 0x2208,
.hwcg_bit = 6,
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "adm0_pbus_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb0_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb0_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb1_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_ssbi2_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "pmic_ssbi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch rpm_msg_ram_h_clk = {
.hwcg_reg = 0x27e0,
.hwcg_bit = 6,
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "rpm_msg_ram_h_clk",
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_pcie_ref[] = {
{ 100000000, P_PLL3, 12, 0, 0 },
{ }
};
static struct clk_rcg pcie_ref_src = {
.ns_reg = 0x3860,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll3_map,
},
.freq_tbl = clk_tbl_pcie_ref,
.clkr = {
.enable_reg = 0x3860,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src",
.parent_data = gcc_pxo_pll3,
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch pcie_ref_src_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 30,
.clkr = {
.enable_reg = 0x3860,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_ref_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pcie_a_clk = {
.halt_reg = 0x2fc0,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x22c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie_aux_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x22c8,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_aux_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x22cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie_phy_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 29,
.clkr = {
.enable_reg = 0x22d0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_phy_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg pcie1_ref_src = {
.ns_reg = 0x3aa0,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll3_map,
},
.freq_tbl = clk_tbl_pcie_ref,
.clkr = {
.enable_reg = 0x3aa0,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src",
.parent_data = gcc_pxo_pll3,
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch pcie1_ref_src_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x3aa0,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie1_ref_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pcie1_a_clk = {
.halt_reg = 0x2fc0,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x3a80,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie1_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie1_aux_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 28,
.clkr = {
.enable_reg = 0x3a88,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie1_aux_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie1_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x3a8c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie1_phy_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x3a90,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie1_phy_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg pcie2_ref_src = {
.ns_reg = 0x3ae0,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll3_map,
},
.freq_tbl = clk_tbl_pcie_ref,
.clkr = {
.enable_reg = 0x3ae0,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src",
.parent_data = gcc_pxo_pll3,
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch pcie2_ref_src_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x3ae0,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie2_ref_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pcie2_a_clk = {
.halt_reg = 0x2fc0,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x3ac0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie2_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie2_aux_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 25,
.clkr = {
.enable_reg = 0x3ac8,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie2_aux_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie2_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x3acc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie2_phy_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x3ad0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie2_phy_clk",
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_sata_ref[] = {
{ 100000000, P_PLL3, 12, 0, 0 },
{ }
};
static struct clk_rcg sata_ref_src = {
.ns_reg = 0x2c08,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll3_sata_map,
},
.freq_tbl = clk_tbl_sata_ref,
.clkr = {
.enable_reg = 0x2c08,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "sata_ref_src",
.parent_data = gcc_pxo_pll3,
.num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch sata_rxoob_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x2c0c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_rxoob_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_ref_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch sata_pmalive_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2c10,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_ref_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch sata_phy_ref_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2c14,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_phy_ref_clk",
.parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sata_a_clk = {
.halt_reg = 0x2fc0,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2c20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sata_h_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x2c00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sfab_sata_s_h_clk = {
.halt_reg = 0x2fc4,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2480,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sfab_sata_s_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sata_phy_cfg_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2c40,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_phy_cfg_clk",
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_usb30_master[] = {
{ 125000000, P_PLL0, 1, 5, 32 },
{ }
};
static struct clk_rcg usb30_master_clk_src = {
.ns_reg = 0x3b2c,
.md_reg = 0x3b28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb30_master,
.clkr = {
.enable_reg = 0x3b2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
.parent_data = gcc_pxo_pll8_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch usb30_0_branch_clk = {
.halt_reg = 0x2fc4,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x3b24,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_0_branch_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb30_1_branch_clk = {
.halt_reg = 0x2fc4,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x3b34,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_1_branch_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb30_utmi[] = {
{ 60000000, P_PLL8, 1, 5, 32 },
{ }
};
static struct clk_rcg usb30_utmi_clk = {
.ns_reg = 0x3b44,
.md_reg = 0x3b40,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb30_utmi,
.clkr = {
.enable_reg = 0x3b44,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
.parent_data = gcc_pxo_pll8_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch usb30_0_utmi_clk_ctl = {
.halt_reg = 0x2fc4,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x3b48,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_0_utmi_clk_ctl",
.parent_hws = (const struct clk_hw*[]){
&usb30_utmi_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb30_1_utmi_clk_ctl = {
.halt_reg = 0x2fc4,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x3b4c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_1_utmi_clk_ctl",
.parent_hws = (const struct clk_hw*[]){
&usb30_utmi_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb[] = {
{ 60000000, P_PLL8, 1, 5, 32 },
{ }
};
static struct clk_rcg usb_hs1_xcvr_clk_src = {
.ns_reg = 0x290C,
.md_reg = 0x2908,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch usb_hs1_xcvr_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs1_xcvr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_hs1_h_clk = {
.hwcg_reg = 0x2900,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x2900,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg usb_fs1_xcvr_clk_src = {
.ns_reg = 0x2968,
.md_reg = 0x2964,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch usb_fs1_xcvr_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_fs1_sys_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x296c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_sys_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_fs1_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2960,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ebi2_clk = {
.hwcg_reg = 0x3b00,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x3b00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ebi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ebi2_aon_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x3b00,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "ebi2_always_on_clk",
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_gmac[] = {
{ 133000000, P_PLL0, 1, 50, 301 },
{ 266000000, P_PLL0, 1, 127, 382 },
{ }
};
static struct clk_dyn_rcg gmac_core1_src = {
.ns_reg[0] = 0x3cac,
.ns_reg[1] = 0x3cb0,
.md_reg[0] = 0x3ca4,
.md_reg[1] = 0x3ca8,
.bank_reg = 0x3ca0,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_gmac,
.clkr = {
.enable_reg = 0x3ca0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch gmac_core1_clk = {
.halt_reg = 0x3c20,
.halt_bit = 4,
.hwcg_reg = 0x3cb4,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x3cb4,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_clk",
.parent_hws = (const struct clk_hw*[]){
&gmac_core1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_dyn_rcg gmac_core2_src = {
.ns_reg[0] = 0x3ccc,
.ns_reg[1] = 0x3cd0,
.md_reg[0] = 0x3cc4,
.md_reg[1] = 0x3cc8,
.bank_reg = 0x3ca0,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_gmac,
.clkr = {
.enable_reg = 0x3cc0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch gmac_core2_clk = {
.halt_reg = 0x3c20,
.halt_bit = 5,
.hwcg_reg = 0x3cd4,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x3cd4,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_clk",
.parent_hws = (const struct clk_hw*[]){
&gmac_core2_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_dyn_rcg gmac_core3_src = {
.ns_reg[0] = 0x3cec,
.ns_reg[1] = 0x3cf0,
.md_reg[0] = 0x3ce4,
.md_reg[1] = 0x3ce8,
.bank_reg = 0x3ce0,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_gmac,
.clkr = {
.enable_reg = 0x3ce0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch gmac_core3_clk = {
.halt_reg = 0x3c20,
.halt_bit = 6,
.hwcg_reg = 0x3cf4,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x3cf4,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_clk",
.parent_hws = (const struct clk_hw*[]){
&gmac_core3_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_dyn_rcg gmac_core4_src = {
.ns_reg[0] = 0x3d0c,
.ns_reg[1] = 0x3d10,
.md_reg[0] = 0x3d04,
.md_reg[1] = 0x3d08,
.bank_reg = 0x3d00,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_gmac,
.clkr = {
.enable_reg = 0x3d00,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch gmac_core4_clk = {
.halt_reg = 0x3c20,
.halt_bit = 7,
.hwcg_reg = 0x3d14,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x3d14,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_clk",
.parent_hws = (const struct clk_hw*[]){
&gmac_core4_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_nss_tcm[] = {
{ 266000000, P_PLL0, 3, 0, 0 },
{ 400000000, P_PLL0, 2, 0, 0 },
{ }
};
static struct clk_dyn_rcg nss_tcm_src = {
.ns_reg[0] = 0x3dc4,
.ns_reg[1] = 0x3dc8,
.bank_reg = 0x3dc0,
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_nss_tcm,
.clkr = {
.enable_reg = 0x3dc0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch nss_tcm_clk = {
.halt_reg = 0x3c20,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x3dd0,
.enable_mask = BIT(6) | BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_clk",
.parent_hws = (const struct clk_hw*[]){
&nss_tcm_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
{ 110000000, P_PLL18, 1, 1, 5 },
{ 275000000, P_PLL18, 2, 0, 0 },
{ 550000000, P_PLL18, 1, 0, 0 },
{ 733000000, P_PLL18, 1, 0, 0 },
{ }
};
static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
{ 110000000, P_PLL18, 1, 1, 5 },
{ 275000000, P_PLL18, 2, 0, 0 },
{ 600000000, P_PLL18, 1, 0, 0 },
{ 800000000, P_PLL18, 1, 0, 0 },
{ }
};
static struct clk_dyn_rcg ubi32_core1_src_clk = {
.ns_reg[0] = 0x3d2c,
.ns_reg[1] = 0x3d30,
.md_reg[0] = 0x3d24,
.md_reg[1] = 0x3d28,
.bank_reg = 0x3d20,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.mux_sel_bit = 0,
/* nss freq table is selected based on the SoC compatible */
.clkr = {
.enable_reg = 0x3d20,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ubi32_core1_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
},
};
static struct clk_dyn_rcg ubi32_core2_src_clk = {
.ns_reg[0] = 0x3d4c,
.ns_reg[1] = 0x3d50,
.md_reg[0] = 0x3d44,
.md_reg[1] = 0x3d48,
.bank_reg = 0x3d40,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.mux_sel_bit = 0,
/* nss freq table is selected based on the SoC compatible */
.clkr = {
.enable_reg = 0x3d40,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ubi32_core2_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
},
};
static const struct freq_tbl clk_tbl_ce5_core[] = {
{ 150000000, P_PLL3, 8, 1, 1 },
{ 213200000, P_PLL11, 5, 1, 1 },
{ }
};
static struct clk_dyn_rcg ce5_core_src = {
.ns_reg[0] = 0x36C4,
.ns_reg[1] = 0x36C8,
.bank_reg = 0x36C0,
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_ce5_core,
.clkr = {
.enable_reg = 0x36C0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ce5_core_src",
.parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
.num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch ce5_core_clk = {
.halt_reg = 0x2FDC,
.halt_bit = 5,
.hwcg_reg = 0x36CC,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x36CC,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce5_core_clk",
.parent_hws = (const struct clk_hw*[]){
&ce5_core_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
{ 160000000, P_PLL0, 5, 1, 1 },
{ 213200000, P_PLL11, 5, 1, 1 },
{ }
};
static struct clk_dyn_rcg ce5_a_clk_src = {
.ns_reg[0] = 0x3d84,
.ns_reg[1] = 0x3d88,
.bank_reg = 0x3d80,
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_ce5_a_clk,
.clkr = {
.enable_reg = 0x3d80,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ce5_a_clk_src",
.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch ce5_a_clk = {
.halt_reg = 0x3c20,
.halt_bit = 12,
.hwcg_reg = 0x3d8c,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x3d8c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce5_a_clk",
.parent_hws = (const struct clk_hw*[]){
&ce5_a_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
{ 160000000, P_PLL0, 5, 1, 1 },
{ 213200000, P_PLL11, 5, 1, 1 },
{ }
};
static struct clk_dyn_rcg ce5_h_clk_src = {
.ns_reg[0] = 0x3c64,
.ns_reg[1] = 0x3c68,
.bank_reg = 0x3c60,
.s[0] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
},
.p[0] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.p[1] = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.mux_sel_bit = 0,
.freq_tbl = clk_tbl_ce5_h_clk,
.clkr = {
.enable_reg = 0x3c60,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ce5_h_clk_src",
.parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch ce5_h_clk = {
.halt_reg = 0x3c20,
.halt_bit = 11,
.hwcg_reg = 0x3c6c,
.hwcg_bit = 6,
.clkr = {
.enable_reg = 0x3c6c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce5_h_clk",
.parent_hws = (const struct clk_hw*[]){
&ce5_h_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
[PLL3] = &pll3.clkr,
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
[PLL11] = &pll11.clkr,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[PLL18] = &pll18.clkr,
[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
[GP0_SRC] = &gp0_src.clkr,
[GP0_CLK] = &gp0_clk.clkr,
[GP1_SRC] = &gp1_src.clkr,
[GP1_CLK] = &gp1_clk.clkr,
[GP2_SRC] = &gp2_src.clkr,
[GP2_CLK] = &gp2_clk.clkr,
[PMEM_A_CLK] = &pmem_clk.clkr,
[PRNG_SRC] = &prng_src.clkr,
[PRNG_CLK] = &prng_clk.clkr,
[SDC1_SRC] = &sdc1_src.clkr,
[SDC1_CLK] = &sdc1_clk.clkr,
[SDC3_SRC] = &sdc3_src.clkr,
[SDC3_CLK] = &sdc3_clk.clkr,
[TSIF_REF_SRC] = &tsif_ref_src.clkr,
[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
[TSIF_H_CLK] = &tsif_h_clk.clkr,
[SDC1_H_CLK] = &sdc1_h_clk.clkr,
[SDC3_H_CLK] = &sdc3_h_clk.clkr,
[ADM0_CLK] = &adm0_clk.clkr,
[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
[PCIE_A_CLK] = &pcie_a_clk.clkr,
[PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
[PCIE_H_CLK] = &pcie_h_clk.clkr,
[PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
[SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
[SATA_H_CLK] = &sata_h_clk.clkr,
[SATA_CLK_SRC] = &sata_ref_src.clkr,
[SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
[SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
[SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
[SATA_A_CLK] = &sata_a_clk.clkr,
[SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
[PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
[PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
[PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
[PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
[PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
[PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
[PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
[PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
[PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
[PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
[PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
[PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
[PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
[PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
[USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
[USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
[USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
[USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
[USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
[USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
[EBI2_CLK] = &ebi2_clk.clkr,
[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
[GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
[GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
[GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
[GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
[GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
[GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
[GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
[GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
[UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
[NSSTCM_CLK] = &nss_tcm_clk.clkr,
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
[CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
[CE5_A_CLK] = &ce5_a_clk.clkr,
[CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
[CE5_H_CLK] = &ce5_h_clk.clkr,
[CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
[CE5_CORE_CLK] = &ce5_core_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
[QDSS_STM_RESET] = { 0x2060, 6 },
[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
[AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
[AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
[AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
[SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
[ADM0_C2_RESET] = { 0x220c, 4 },
[ADM0_C1_RESET] = { 0x220c, 3 },
[ADM0_C0_RESET] = { 0x220c, 2 },
[ADM0_PBUS_RESET] = { 0x220c, 1 },
[ADM0_RESET] = { 0x220c, 0 },
[QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
[QDSS_POR_RESET] = { 0x2260, 4 },
[QDSS_TSCTR_RESET] = { 0x2260, 3 },
[QDSS_HRESET_RESET] = { 0x2260, 2 },
[QDSS_AXI_RESET] = { 0x2260, 1 },
[QDSS_DBG_RESET] = { 0x2260, 0 },
[SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
[SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
[PCIE_EXT_RESET] = { 0x22dc, 6 },
[PCIE_PHY_RESET] = { 0x22dc, 5 },
[PCIE_PCI_RESET] = { 0x22dc, 4 },
[PCIE_POR_RESET] = { 0x22dc, 3 },
[PCIE_HCLK_RESET] = { 0x22dc, 2 },
[PCIE_ACLK_RESET] = { 0x22dc, 0 },
[SFAB_LPASS_RESET] = { 0x23a0, 7 },
[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
[SFAB_SATA_S_RESET] = { 0x2480, 7 },
[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
[DFAB_SWAY0_RESET] = { 0x2540, 7 },
[DFAB_SWAY1_RESET] = { 0x2544, 7 },
[DFAB_ARB0_RESET] = { 0x2560, 7 },
[DFAB_ARB1_RESET] = { 0x2564, 7 },
[PPSS_PROC_RESET] = { 0x2594, 1 },
[PPSS_RESET] = { 0x2594, 0 },
[DMA_BAM_RESET] = { 0x25c0, 7 },
[SPS_TIC_H_RESET] = { 0x2600, 7 },
[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
[TSIF_H_RESET] = { 0x2700, 7 },
[CE1_H_RESET] = { 0x2720, 7 },
[CE1_CORE_RESET] = { 0x2724, 7 },
[CE1_SLEEP_RESET] = { 0x2728, 7 },
[CE2_H_RESET] = { 0x2740, 7 },
[CE2_CORE_RESET] = { 0x2744, 7 },
[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
[RPM_PROC_RESET] = { 0x27c0, 7 },
[PMIC_SSBI2_RESET] = { 0x280c, 12 },
[SDC1_RESET] = { 0x2830, 0 },
[SDC2_RESET] = { 0x2850, 0 },
[SDC3_RESET] = { 0x2870, 0 },
[SDC4_RESET] = { 0x2890, 0 },
[USB_HS1_RESET] = { 0x2910, 0 },
[USB_HSIC_RESET] = { 0x2934, 0 },
[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
[USB_FS1_RESET] = { 0x2974, 0 },
[GSBI1_RESET] = { 0x29dc, 0 },
[GSBI2_RESET] = { 0x29fc, 0 },
[GSBI3_RESET] = { 0x2a1c, 0 },
[GSBI4_RESET] = { 0x2a3c, 0 },
[GSBI5_RESET] = { 0x2a5c, 0 },
[GSBI6_RESET] = { 0x2a7c, 0 },
[GSBI7_RESET] = { 0x2a9c, 0 },
[SPDM_RESET] = { 0x2b6c, 0 },
[SEC_CTRL_RESET] = { 0x2b80, 7 },
[TLMM_H_RESET] = { 0x2ba0, 7 },
[SFAB_SATA_M_RESET] = { 0x2c18, 0 },
[SATA_RESET] = { 0x2c1c, 0 },
[TSSC_RESET] = { 0x2ca0, 7 },
[PDM_RESET] = { 0x2cc0, 12 },
[MPM_H_RESET] = { 0x2da0, 7 },
[MPM_RESET] = { 0x2da4, 0 },
[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
[PRNG_RESET] = { 0x2e80, 12 },
[SFAB_CE3_M_RESET] = { 0x36c8, 1 },
[SFAB_CE3_S_RESET] = { 0x36c8, 0 },
[CE3_SLEEP_RESET] = { 0x36d0, 7 },
[PCIE_1_M_RESET] = { 0x3a98, 1 },
[PCIE_1_S_RESET] = { 0x3a98, 0 },
[PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
[PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
[PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
[PCIE_1_POR_RESET] = { 0x3a9c, 3 },
[PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
[PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
[PCIE_2_M_RESET] = { 0x3ad8, 1 },
[PCIE_2_S_RESET] = { 0x3ad8, 0 },
[PCIE_2_EXT_RESET] = { 0x3adc, 6 },
[PCIE_2_PHY_RESET] = { 0x3adc, 5 },
[PCIE_2_PCI_RESET] = { 0x3adc, 4 },
[PCIE_2_POR_RESET] = { 0x3adc, 3 },
[PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
[PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
[SFAB_USB30_S_RESET] = { 0x3b54, 1 },
[SFAB_USB30_M_RESET] = { 0x3b54, 0 },
[USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
[USB30_0_MASTER_RESET] = { 0x3b50, 4 },
[USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
[USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
[USB30_0_POWERON_RESET] = { 0x3b50, 1 },
[USB30_0_PHY_RESET] = { 0x3b50, 0 },
[USB30_1_MASTER_RESET] = { 0x3b58, 4 },
[USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
[USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
[USB30_1_POWERON_RESET] = { 0x3b58, 1 },
[USB30_1_PHY_RESET] = { 0x3b58, 0 },
[NSSFB0_RESET] = { 0x3b60, 6 },
[NSSFB1_RESET] = { 0x3b60, 7 },
[UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
[UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
[UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
[UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
[UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
[UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
[UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
[UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
[GMAC_CORE1_RESET] = { 0x3cbc, 0 },
[GMAC_CORE2_RESET] = { 0x3cdc, 0 },
[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
[GMAC_AHB_RESET] = { 0x3e24, 0 },
[CRYPTO_ENG1_RESET] = { 0x3e00, 0},
[CRYPTO_ENG2_RESET] = { 0x3e04, 0},
[CRYPTO_ENG3_RESET] = { 0x3e08, 0},
[CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
[CRYPTO_AHB_RESET] = { 0x3e10, 0},
[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
[NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
[NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
[NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
[NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
[NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
[NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
[NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
[NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
[NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
[NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
[NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
[NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
[NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
[NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
[NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
[NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
[NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
[NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
[NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
[NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
[NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
[NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
[NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
[NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
[NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
[NSS_SRDS_N_RESET] = { 0x3b60, 28 },
};
static const struct regmap_config gcc_ipq806x_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x3e40,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_ipq806x_desc = {
.config = &gcc_ipq806x_regmap_config,
.clks = gcc_ipq806x_clks,
.num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
.resets = gcc_ipq806x_resets,
.num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
};
static const struct of_device_id gcc_ipq806x_match_table[] = {
{ .compatible = "qcom,gcc-ipq8064" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
static int gcc_ipq806x_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
int ret;
ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
if (ret)
return ret;
ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
if (ret)
return ret;
if (of_machine_is_compatible("qcom,ipq8065")) {
ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
} else {
ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
}
ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
if (ret)
return ret;
regmap = dev_get_regmap(dev, NULL);
if (!regmap)
return -ENODEV;
/* Setup PLL18 static bits */
regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
regmap_write(regmap, 0x31b0, 0x3080);
/* Set GMAC footswitch sleep/wakeup values */
regmap_write(regmap, 0x3cb8, 8);
regmap_write(regmap, 0x3cd8, 8);
regmap_write(regmap, 0x3cf8, 8);
regmap_write(regmap, 0x3d18, 8);
return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
}
static struct platform_driver gcc_ipq806x_driver = {
.probe = gcc_ipq806x_probe,
.driver = {
.name = "gcc-ipq806x",
.of_match_table = gcc_ipq806x_match_table,
},
};
static int __init gcc_ipq806x_init(void)
{
return platform_driver_register(&gcc_ipq806x_driver);
}
core_initcall(gcc_ipq806x_init);
static void __exit gcc_ipq806x_exit(void)
{
platform_driver_unregister(&gcc_ipq806x_driver);
}
module_exit(gcc_ipq806x_exit);
MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-ipq806x");
| linux-master | drivers/clk/qcom/gcc-ipq806x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_GCC_GPU_GPLL0_CLK_SRC,
P_GCC_GPU_GPLL0_DIV_CLK_SRC,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
/* 500MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1A,
.alpha = 0xAAA,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src", },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src", },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(150000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 2, 0, 0),
F(240000000, P_GCC_GPU_GPLL0_CLK_SRC, 2.5, 0, 0),
F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x117c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x11c0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x11bc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x1178,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1178,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x1204,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x802c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x8030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x8030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | RETAIN_FF_ENABLE,
};
static struct gdsc *gpu_cc_sc7180_gdscs[] = {
[GPU_CC_CX_GDSC] = &cx_gdsc,
[GPU_CC_GX_GDSC] = &gx_gdsc,
};
static struct clk_regmap *gpu_cc_sc7280_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
};
static const struct regmap_config gpu_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8030,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
.config = &gpu_cc_sc7280_regmap_config,
.clks = gpu_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
.gdscs = gpu_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
};
static const struct of_device_id gpu_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sc7280_match_table);
static int gpu_cc_sc7280_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sc7280_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep the clocks always-ON
* GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK
*/
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13));
return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap);
}
static struct platform_driver gpu_cc_sc7280_driver = {
.probe = gpu_cc_sc7280_probe,
.driver = {
.name = "gpu_cc-sc7280",
.of_match_table = gpu_cc_sc7280_match_table,
},
};
static int __init gpu_cc_sc7280_init(void)
{
return platform_driver_register(&gpu_cc_sc7280_driver);
}
subsys_initcall(gpu_cc_sc7280_init);
static void __exit gpu_cc_sc7280_exit(void)
{
platform_driver_unregister(&gpu_cc_sc7280_driver);
}
module_exit(gpu_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI GPU_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_AUD_REF_CLK,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x13000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_AUD_REF_CLK, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_7_ao[] = {
{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static const struct clk_parent_data gcc_parent_data_8_ao[] = {
{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_7_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_7_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
.cmd_rcgr = 0x4815c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk_src",
.parent_data = gcc_parent_data_8_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = {
.cmd_rcgr = 0x4815c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk_src",
.parent_data = gcc_parent_data_8_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b028,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d028,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
.cmd_rcgr = 0x6f014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qspi_core_clk_src = {
.cmd_rcgr = 0x4b008,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qspi_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17164,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x17294,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x173c4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x174f4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17754,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17884,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18018,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x18868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x26028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x26010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
F(105495, P_BI_TCXO, 2, 1, 91),
{ }
};
static struct clk_rcg2 gcc_tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x7501c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x7505c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x75090,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x75074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x7701c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x7705c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x77090,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x10018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x10030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf05c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x1005c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
.cmd_rcgr = 0x7a030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_vsensor_clk_src = {
.cmd_rcgr = 0x7a018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_vsensor_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_vsensor_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x90014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x82028,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x82028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x82024,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x82024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x8201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x82020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x82020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apc_vs_clk = {
.halt_reg = 0x7a050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_apc_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0xb008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_axi_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0xb02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x4100c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4100c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x41008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x41004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x502c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x5030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/*
* The source clock frequencies are different for SDM670; define a child clock
* pointing to the source clock that uses SDM670 frequencies.
*/
static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x44038,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x44038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0xb00c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb00c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_axi_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0xb030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x71004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_vs_clk = {
.halt_reg = 0x7a04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_axis2_clk = {
.halt_reg = 0x8a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_axis2_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x8a000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_gpll0_div_clk_src",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_mfab_axis_clk = {
.halt_reg = 0x8a004,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x8a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mfab_axis_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
.halt_reg = 0x8a154,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8a154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_memnoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a150,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_vs_clk = {
.halt_reg = 0x7a048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_clk = {
.halt_reg = 0x8c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_clkref_clk = {
.halt_reg = 0x8c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_refgen_clk = {
.halt_reg = 0x6f02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_ahb_clk = {
.halt_reg = 0xb014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0xb018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_ahb_clk = {
.halt_reg = 0xb010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
.halt_reg = 0x4b000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_core_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qspi_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x17160,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x17290,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x173c0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x174f0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x17620,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x17750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x17880,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x183a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x18734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x18864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x26004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/*
* The source clock frequencies are different for SDM670; define a child clock
* pointing to the source clock that uses SDM670 frequencies.
*/
static struct clk_branch gcc_sdm670_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdm670_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x414c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x7500c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7500c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_clkref_clk = {
.halt_reg = 0x8c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x7508c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7508c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7508c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x750a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x75054,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75054,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x7700c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x7708c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7708c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7708c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x770a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x77014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77054,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77054,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x1000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x10014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_clkref_clk = {
.halt_reg = 0x8c028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x1004c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1004c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x10050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x10054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x6a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vdda_vs_clk = {
.halt_reg = 0x7a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vdda_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vddcx_vs_clk = {
.halt_reg = 0x7a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vddcx_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vddmx_vs_clk = {
.halt_reg = 0x7a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vddmx_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0xb004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vs_ctrl_ahb_clk = {
.halt_reg = 0x7a014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7a014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vs_ctrl_clk = {
.halt_reg = 0x7a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vs_ctrl_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_dvm_bus_clk = {
.halt_reg = 0x48190,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48190,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_dvm_bus_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_gnoc_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x48004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_gnoc_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
/* TODO: Remove after DTS updated to protect these */
#ifdef CONFIG_SDM_LPASSCC_845
static struct clk_branch gcc_lpass_q6_axi_clk = {
.halt_reg = 0x47000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_sway_clk = {
.halt_reg = 0x47008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_sway_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
#endif
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
.gdscr = 0x7d030,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
.gdscr = 0x7d03c,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
.gdscr = 0x7d034,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
.gdscr = 0x7d038,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d040,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0x7d048,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
.gdscr = 0x7d044,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sdm670_clocks[] = {
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr,
[GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
[GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
[GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] =
&gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
[GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
[GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
[GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
[GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
[GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL6] = &gpll6.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
};
static struct clk_regmap *gcc_sdm845_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
[GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
[GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] =
&gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
[GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
[GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
[GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
[GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
[GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
#ifdef CONFIG_SDM_LPASSCC_845
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
#endif
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
};
static struct gdsc *gcc_sdm670_gdscs[] = {
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
};
static struct gdsc *gcc_sdm845_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
};
static const struct regmap_config gcc_sdm845_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x182090,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sdm670_desc = {
.config = &gcc_sdm845_regmap_config,
.clks = gcc_sdm670_clocks,
.num_clks = ARRAY_SIZE(gcc_sdm670_clocks),
/* Snapdragon 670 can function without its own exclusive resets. */
.resets = gcc_sdm845_resets,
.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
.gdscs = gcc_sdm670_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
};
static const struct qcom_cc_desc gcc_sdm845_desc = {
.config = &gcc_sdm845_regmap_config,
.clks = gcc_sdm845_clocks,
.num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
.resets = gcc_sdm845_resets,
.num_resets = ARRAY_SIZE(gcc_sdm845_resets),
.gdscs = gcc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
};
static const struct of_device_id gcc_sdm845_match_table[] = {
{ .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc },
{ .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
};
static int gcc_sdm845_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *gcc_desc;
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
gcc_desc = of_device_get_match_data(&pdev->dev);
return qcom_cc_really_probe(pdev, gcc_desc, regmap);
}
static struct platform_driver gcc_sdm845_driver = {
.probe = gcc_sdm845_probe,
.driver = {
.name = "gcc-sdm845",
.of_match_table = gcc_sdm845_match_table,
},
};
static int __init gcc_sdm845_init(void)
{
return platform_driver_register(&gcc_sdm845_driver);
}
core_initcall(gcc_sdm845_init);
static void __exit gcc_sdm845_exit(void)
{
platform_driver_unregister(&gcc_sdm845_driver);
}
module_exit(gcc_sdm845_exit);
MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-sdm845");
| linux-master | drivers/clk/qcom/gcc-sdm845.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/reset/qcom,mmcc-msm8960.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
enum {
P_PXO,
P_PLL8,
P_PLL2,
P_PLL3,
P_PLL15,
P_HDMI_PLL,
P_DSI1_PLL_DSICLK,
P_DSI2_PLL_DSICLK,
P_DSI1_PLL_BYTECLK,
P_DSI2_PLL_BYTECLK,
};
#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
static struct clk_pll pll2 = {
.l_reg = 0x320,
.m_reg = 0x324,
.n_reg = 0x328,
.config_reg = 0x32c,
.mode_reg = 0x31c,
.status_reg = 0x334,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll2",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_pll pll15 = {
.l_reg = 0x33c,
.m_reg = 0x340,
.n_reg = 0x344,
.config_reg = 0x348,
.mode_reg = 0x338,
.status_reg = 0x350,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll15",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static const struct pll_config pll15_config = {
.l = 33,
.m = 1,
.n = 3,
.vco_val = 0x2 << 16,
.vco_mask = 0x3 << 16,
.pre_div_val = 0x0,
.pre_div_mask = BIT(19),
.post_div_val = 0x0,
.post_div_mask = 0x3 << 20,
.mn_ena_mask = BIT(22),
.main_output_mask = BIT(23),
};
static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 }
};
static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .hw = &pll2.clkr.hw },
};
static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL3, 3 }
};
static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .hw = &pll2.clkr.hw },
{ .hw = &pll15.clkr.hw },
};
static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL15, 3 }
};
static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .hw = &pll2.clkr.hw },
{ .fw_name = "pll3", .name = "pll3" },
};
static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
{ P_PXO, 0 },
{ P_DSI2_PLL_DSICLK, 1 },
{ P_DSI1_PLL_DSICLK, 3 },
};
static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "dsi2pll", .name = "dsi2pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
{ P_PXO, 0 },
{ P_DSI1_PLL_BYTECLK, 1 },
{ P_DSI2_PLL_BYTECLK, 2 },
};
static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
{ .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
};
static struct freq_tbl clk_tbl_cam[] = {
{ 6000000, P_PLL8, 4, 1, 16 },
{ 8000000, P_PLL8, 4, 1, 12 },
{ 12000000, P_PLL8, 4, 1, 8 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 19200000, P_PLL8, 4, 1, 5 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 32000000, P_PLL8, 4, 1, 3 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 64000000, P_PLL8, 3, 1, 2 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 128000000, P_PLL8, 3, 0, 0 },
{ }
};
static struct clk_rcg camclk0_src = {
.ns_reg = 0x0148,
.md_reg = 0x0144,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 8,
.reset_in_cc = true,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_cam,
.clkr = {
.enable_reg = 0x0140,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "camclk0_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch camclk0_clk = {
.halt_reg = 0x01e8,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x0140,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&camclk0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg camclk1_src = {
.ns_reg = 0x015c,
.md_reg = 0x0158,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 8,
.reset_in_cc = true,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_cam,
.clkr = {
.enable_reg = 0x0154,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "camclk1_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch camclk1_clk = {
.halt_reg = 0x01e8,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x0154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&camclk1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg camclk2_src = {
.ns_reg = 0x0228,
.md_reg = 0x0224,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 8,
.reset_in_cc = true,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_cam,
.clkr = {
.enable_reg = 0x0220,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "camclk2_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch camclk2_clk = {
.halt_reg = 0x01e8,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x0220,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&camclk2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static struct freq_tbl clk_tbl_csi[] = {
{ 27000000, P_PXO, 1, 0, 0 },
{ 85330000, P_PLL8, 1, 2, 9 },
{ 177780000, P_PLL2, 1, 2, 9 },
{ }
};
static struct clk_rcg csi0_src = {
.ns_reg = 0x0048,
.md_reg = 0x0044,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_csi,
.clkr = {
.enable_reg = 0x0040,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi0_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch csi0_clk = {
.halt_reg = 0x01cc,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x0040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csi0_src.clkr.hw
},
.num_parents = 1,
.name = "csi0_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch csi0_phy_clk = {
.halt_reg = 0x01e8,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x0040,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csi0_src.clkr.hw
},
.num_parents = 1,
.name = "csi0_phy_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg csi1_src = {
.ns_reg = 0x0010,
.md_reg = 0x0028,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_csi,
.clkr = {
.enable_reg = 0x0024,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi1_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch csi1_clk = {
.halt_reg = 0x01cc,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x0024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csi1_src.clkr.hw
},
.num_parents = 1,
.name = "csi1_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch csi1_phy_clk = {
.halt_reg = 0x01e8,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x0024,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csi1_src.clkr.hw
},
.num_parents = 1,
.name = "csi1_phy_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg csi2_src = {
.ns_reg = 0x0234,
.md_reg = 0x022c,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_csi,
.clkr = {
.enable_reg = 0x022c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi2_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch csi2_clk = {
.halt_reg = 0x01cc,
.halt_bit = 29,
.clkr = {
.enable_reg = 0x022c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csi2_src.clkr.hw
},
.num_parents = 1,
.name = "csi2_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch csi2_phy_clk = {
.halt_reg = 0x01e8,
.halt_bit = 29,
.clkr = {
.enable_reg = 0x022c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csi2_src.clkr.hw
},
.num_parents = 1,
.name = "csi2_phy_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
struct clk_pix_rdi {
u32 s_reg;
u32 s_mask;
u32 s2_reg;
u32 s2_mask;
struct clk_regmap clkr;
};
#define to_clk_pix_rdi(_hw) \
container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
{
int i;
int ret = 0;
u32 val;
struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
int num_parents = clk_hw_get_num_parents(hw);
/*
* These clocks select three inputs via two muxes. One mux selects
* between csi0 and csi1 and the second mux selects between that mux's
* output and csi2. The source and destination selections for each
* mux must be clocking for the switch to succeed so just turn on
* all three sources because it's easier than figuring out what source
* needs to be on at what time.
*/
for (i = 0; i < num_parents; i++) {
struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
ret = clk_prepare_enable(p->clk);
if (ret)
goto err;
}
if (index == 2)
val = rdi->s2_mask;
else
val = 0;
regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
/*
* Wait at least 6 cycles of slowest clock
* for the glitch-free MUX to fully switch sources.
*/
udelay(1);
if (index == 1)
val = rdi->s_mask;
else
val = 0;
regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
/*
* Wait at least 6 cycles of slowest clock
* for the glitch-free MUX to fully switch sources.
*/
udelay(1);
err:
for (i--; i >= 0; i--) {
struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
clk_disable_unprepare(p->clk);
}
return ret;
}
static u8 pix_rdi_get_parent(struct clk_hw *hw)
{
u32 val;
struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
if (val & rdi->s2_mask)
return 2;
regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
if (val & rdi->s_mask)
return 1;
return 0;
}
static const struct clk_ops clk_ops_pix_rdi = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.set_parent = pix_rdi_set_parent,
.get_parent = pix_rdi_get_parent,
.determine_rate = __clk_mux_determine_rate,
};
static const struct clk_hw *pix_rdi_parents[] = {
&csi0_clk.clkr.hw,
&csi1_clk.clkr.hw,
&csi2_clk.clkr.hw,
};
static struct clk_pix_rdi csi_pix_clk = {
.s_reg = 0x0058,
.s_mask = BIT(25),
.s2_reg = 0x0238,
.s2_mask = BIT(13),
.clkr = {
.enable_reg = 0x0058,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "csi_pix_clk",
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
};
static struct clk_pix_rdi csi_pix1_clk = {
.s_reg = 0x0238,
.s_mask = BIT(8),
.s2_reg = 0x0238,
.s2_mask = BIT(9),
.clkr = {
.enable_reg = 0x0238,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "csi_pix1_clk",
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
};
static struct clk_pix_rdi csi_rdi_clk = {
.s_reg = 0x0058,
.s_mask = BIT(12),
.s2_reg = 0x0238,
.s2_mask = BIT(12),
.clkr = {
.enable_reg = 0x0058,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "csi_rdi_clk",
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
};
static struct clk_pix_rdi csi_rdi1_clk = {
.s_reg = 0x0238,
.s_mask = BIT(0),
.s2_reg = 0x0238,
.s2_mask = BIT(1),
.clkr = {
.enable_reg = 0x0238,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csi_rdi1_clk",
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
};
static struct clk_pix_rdi csi_rdi2_clk = {
.s_reg = 0x0238,
.s_mask = BIT(4),
.s2_reg = 0x0238,
.s2_mask = BIT(5),
.clkr = {
.enable_reg = 0x0238,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "csi_rdi2_clk",
.parent_hws = pix_rdi_parents,
.num_parents = ARRAY_SIZE(pix_rdi_parents),
.ops = &clk_ops_pix_rdi,
},
},
};
static struct freq_tbl clk_tbl_csiphytimer[] = {
{ 85330000, P_PLL8, 1, 2, 9 },
{ 177780000, P_PLL2, 1, 2, 9 },
{ }
};
static struct clk_rcg csiphytimer_src = {
.ns_reg = 0x0168,
.md_reg = 0x0164,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 8,
.reset_in_cc = true,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_csiphytimer,
.clkr = {
.enable_reg = 0x0160,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "csiphytimer_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch csiphy0_timer_clk = {
.halt_reg = 0x01e8,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x0160,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csiphytimer_src.clkr.hw,
},
.num_parents = 1,
.name = "csiphy0_timer_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch csiphy1_timer_clk = {
.halt_reg = 0x01e8,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x0160,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csiphytimer_src.clkr.hw,
},
.num_parents = 1,
.name = "csiphy1_timer_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch csiphy2_timer_clk = {
.halt_reg = 0x01e8,
.halt_bit = 30,
.clkr = {
.enable_reg = 0x0160,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&csiphytimer_src.clkr.hw,
},
.num_parents = 1,
.name = "csiphy2_timer_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_gfx2d[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
F_MN( 64000000, P_PLL8, 1, 6),
F_MN( 76800000, P_PLL8, 1, 5),
F_MN( 96000000, P_PLL8, 1, 4),
F_MN(128000000, P_PLL8, 1, 3),
F_MN(145455000, P_PLL2, 2, 11),
F_MN(160000000, P_PLL2, 1, 5),
F_MN(177778000, P_PLL2, 2, 9),
F_MN(200000000, P_PLL2, 1, 4),
F_MN(228571000, P_PLL2, 2, 7),
{ }
};
static struct clk_dyn_rcg gfx2d0_src = {
.ns_reg[0] = 0x0070,
.ns_reg[1] = 0x0070,
.md_reg[0] = 0x0064,
.md_reg[1] = 0x0068,
.bank_reg = 0x0060,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 25,
.mnctr_mode_shift = 9,
.n_val_shift = 20,
.m_val_shift = 4,
.width = 4,
},
.mn[1] = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 24,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 4,
.width = 4,
},
.s[0] = {
.src_sel_shift = 3,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.mux_sel_bit = 11,
.freq_tbl = clk_tbl_gfx2d,
.clkr = {
.enable_reg = 0x0060,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx2d0_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch gfx2d0_clk = {
.halt_reg = 0x01c8,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x0060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx2d0_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx2d0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_dyn_rcg gfx2d1_src = {
.ns_reg[0] = 0x007c,
.ns_reg[1] = 0x007c,
.md_reg[0] = 0x0078,
.md_reg[1] = 0x006c,
.bank_reg = 0x0074,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 25,
.mnctr_mode_shift = 9,
.n_val_shift = 20,
.m_val_shift = 4,
.width = 4,
},
.mn[1] = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 24,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 4,
.width = 4,
},
.s[0] = {
.src_sel_shift = 3,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.mux_sel_bit = 11,
.freq_tbl = clk_tbl_gfx2d,
.clkr = {
.enable_reg = 0x0074,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx2d1_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch gfx2d1_clk = {
.halt_reg = 0x01c8,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x0074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx2d1_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx2d1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_gfx3d[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
F_MN( 64000000, P_PLL8, 1, 6),
F_MN( 76800000, P_PLL8, 1, 5),
F_MN( 96000000, P_PLL8, 1, 4),
F_MN(128000000, P_PLL8, 1, 3),
F_MN(145455000, P_PLL2, 2, 11),
F_MN(160000000, P_PLL2, 1, 5),
F_MN(177778000, P_PLL2, 2, 9),
F_MN(200000000, P_PLL2, 1, 4),
F_MN(228571000, P_PLL2, 2, 7),
F_MN(266667000, P_PLL2, 1, 3),
F_MN(300000000, P_PLL3, 1, 4),
F_MN(320000000, P_PLL2, 2, 5),
F_MN(400000000, P_PLL2, 1, 2),
{ }
};
static struct freq_tbl clk_tbl_gfx3d_8064[] = {
F_MN( 27000000, P_PXO, 0, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
F_MN( 64000000, P_PLL8, 1, 6),
F_MN( 76800000, P_PLL8, 1, 5),
F_MN( 96000000, P_PLL8, 1, 4),
F_MN(128000000, P_PLL8, 1, 3),
F_MN(145455000, P_PLL2, 2, 11),
F_MN(160000000, P_PLL2, 1, 5),
F_MN(177778000, P_PLL2, 2, 9),
F_MN(192000000, P_PLL8, 1, 2),
F_MN(200000000, P_PLL2, 1, 4),
F_MN(228571000, P_PLL2, 2, 7),
F_MN(266667000, P_PLL2, 1, 3),
F_MN(320000000, P_PLL2, 2, 5),
F_MN(400000000, P_PLL2, 1, 2),
F_MN(450000000, P_PLL15, 1, 2),
{ }
};
static struct clk_dyn_rcg gfx3d_src = {
.ns_reg[0] = 0x008c,
.ns_reg[1] = 0x008c,
.md_reg[0] = 0x0084,
.md_reg[1] = 0x0088,
.bank_reg = 0x0080,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 25,
.mnctr_mode_shift = 9,
.n_val_shift = 18,
.m_val_shift = 4,
.width = 4,
},
.mn[1] = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 24,
.mnctr_mode_shift = 6,
.n_val_shift = 14,
.m_val_shift = 4,
.width = 4,
},
.s[0] = {
.src_sel_shift = 3,
.parent_map = mmcc_pxo_pll8_pll2_pll3_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_pll3_map,
},
.mux_sel_bit = 11,
.freq_tbl = clk_tbl_gfx3d,
.clkr = {
.enable_reg = 0x0080,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_src",
.parent_data = mmcc_pxo_pll8_pll2_pll3,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3),
.ops = &clk_dyn_rcg_ops,
},
},
};
static const struct clk_init_data gfx3d_8064_init = {
.name = "gfx3d_src",
.parent_data = mmcc_pxo_pll8_pll2_pll15,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15),
.ops = &clk_dyn_rcg_ops,
};
static struct clk_branch gfx3d_clk = {
.halt_reg = 0x01c8,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x0080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_vcap[] = {
F_MN( 27000000, P_PXO, 0, 0),
F_MN( 54860000, P_PLL8, 1, 7),
F_MN( 64000000, P_PLL8, 1, 6),
F_MN( 76800000, P_PLL8, 1, 5),
F_MN(128000000, P_PLL8, 1, 3),
F_MN(160000000, P_PLL2, 1, 5),
F_MN(200000000, P_PLL2, 1, 4),
{ }
};
static struct clk_dyn_rcg vcap_src = {
.ns_reg[0] = 0x021c,
.ns_reg[1] = 0x021c,
.md_reg[0] = 0x01ec,
.md_reg[1] = 0x0218,
.bank_reg = 0x0178,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 23,
.mnctr_mode_shift = 9,
.n_val_shift = 18,
.m_val_shift = 4,
.width = 4,
},
.mn[1] = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 22,
.mnctr_mode_shift = 6,
.n_val_shift = 14,
.m_val_shift = 4,
.width = 4,
},
.s[0] = {
.src_sel_shift = 3,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.mux_sel_bit = 11,
.freq_tbl = clk_tbl_vcap,
.clkr = {
.enable_reg = 0x0178,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vcap_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch vcap_clk = {
.halt_reg = 0x0240,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x0178,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vcap_clk",
.parent_hws = (const struct clk_hw*[]){
&vcap_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch vcap_npl_clk = {
.halt_reg = 0x0240,
.halt_bit = 25,
.clkr = {
.enable_reg = 0x0178,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "vcap_npl_clk",
.parent_hws = (const struct clk_hw*[]){
&vcap_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_ijpeg[] = {
{ 27000000, P_PXO, 1, 0, 0 },
{ 36570000, P_PLL8, 1, 2, 21 },
{ 54860000, P_PLL8, 7, 0, 0 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 109710000, P_PLL8, 1, 2, 7 },
{ 128000000, P_PLL8, 3, 0, 0 },
{ 153600000, P_PLL8, 1, 2, 5 },
{ 200000000, P_PLL2, 4, 0, 0 },
{ 228571000, P_PLL2, 1, 2, 7 },
{ 266667000, P_PLL2, 1, 1, 3 },
{ 320000000, P_PLL2, 1, 2, 5 },
{ }
};
static struct clk_rcg ijpeg_src = {
.ns_reg = 0x00a0,
.md_reg = 0x009c,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 12,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_ijpeg,
.clkr = {
.enable_reg = 0x0098,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "ijpeg_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch ijpeg_clk = {
.halt_reg = 0x01c8,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x0098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ijpeg_clk",
.parent_hws = (const struct clk_hw*[]){
&ijpeg_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_jpegd[] = {
{ 64000000, P_PLL8, 6 },
{ 76800000, P_PLL8, 5 },
{ 96000000, P_PLL8, 4 },
{ 160000000, P_PLL2, 5 },
{ 200000000, P_PLL2, 4 },
{ }
};
static struct clk_rcg jpegd_src = {
.ns_reg = 0x00ac,
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_jpegd,
.clkr = {
.enable_reg = 0x00a4,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "jpegd_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch jpegd_clk = {
.halt_reg = 0x01c8,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x00a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "jpegd_clk",
.parent_hws = (const struct clk_hw*[]){
&jpegd_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_mdp[] = {
{ 9600000, P_PLL8, 1, 1, 40 },
{ 13710000, P_PLL8, 1, 1, 28 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 29540000, P_PLL8, 1, 1, 13 },
{ 34910000, P_PLL8, 1, 1, 11 },
{ 38400000, P_PLL8, 1, 1, 10 },
{ 59080000, P_PLL8, 1, 2, 13 },
{ 76800000, P_PLL8, 1, 1, 5 },
{ 85330000, P_PLL8, 1, 2, 9 },
{ 96000000, P_PLL8, 1, 1, 4 },
{ 128000000, P_PLL8, 1, 1, 3 },
{ 160000000, P_PLL2, 1, 1, 5 },
{ 177780000, P_PLL2, 1, 2, 9 },
{ 200000000, P_PLL2, 1, 1, 4 },
{ 228571000, P_PLL2, 1, 2, 7 },
{ 266667000, P_PLL2, 1, 1, 3 },
{ }
};
static struct clk_dyn_rcg mdp_src = {
.ns_reg[0] = 0x00d0,
.ns_reg[1] = 0x00d0,
.md_reg[0] = 0x00c4,
.md_reg[1] = 0x00c8,
.bank_reg = 0x00c0,
.mn[0] = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 31,
.mnctr_mode_shift = 9,
.n_val_shift = 22,
.m_val_shift = 8,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 30,
.mnctr_mode_shift = 6,
.n_val_shift = 14,
.m_val_shift = 8,
.width = 8,
},
.s[0] = {
.src_sel_shift = 3,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.mux_sel_bit = 11,
.freq_tbl = clk_tbl_mdp,
.clkr = {
.enable_reg = 0x00c0,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "mdp_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch mdp_clk = {
.halt_reg = 0x01d0,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x00c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdp_lut_clk = {
.halt_reg = 0x01e8,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x016c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&mdp_src.clkr.hw
},
.num_parents = 1,
.name = "mdp_lut_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdp_vsync_clk = {
.halt_reg = 0x01cc,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x0058,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "mdp_vsync_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.ops = &clk_branch_ops
},
},
};
static struct freq_tbl clk_tbl_rot[] = {
{ 27000000, P_PXO, 1 },
{ 29540000, P_PLL8, 13 },
{ 32000000, P_PLL8, 12 },
{ 38400000, P_PLL8, 10 },
{ 48000000, P_PLL8, 8 },
{ 54860000, P_PLL8, 7 },
{ 64000000, P_PLL8, 6 },
{ 76800000, P_PLL8, 5 },
{ 96000000, P_PLL8, 4 },
{ 100000000, P_PLL2, 8 },
{ 114290000, P_PLL2, 7 },
{ 133330000, P_PLL2, 6 },
{ 160000000, P_PLL2, 5 },
{ 200000000, P_PLL2, 4 },
{ }
};
static struct clk_dyn_rcg rot_src = {
.ns_reg[0] = 0x00e8,
.ns_reg[1] = 0x00e8,
.bank_reg = 0x00e8,
.p[0] = {
.pre_div_shift = 22,
.pre_div_width = 4,
},
.p[1] = {
.pre_div_shift = 26,
.pre_div_width = 4,
},
.s[0] = {
.src_sel_shift = 16,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.s[1] = {
.src_sel_shift = 19,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.mux_sel_bit = 30,
.freq_tbl = clk_tbl_rot,
.clkr = {
.enable_reg = 0x00e0,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "rot_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch rot_clk = {
.halt_reg = 0x01d0,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x00e0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "rot_clk",
.parent_hws = (const struct clk_hw*[]){
&rot_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct parent_map mmcc_pxo_hdmi_map[] = {
{ P_PXO, 0 },
{ P_HDMI_PLL, 3 }
};
static const struct clk_parent_data mmcc_pxo_hdmi[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "hdmipll", .name = "hdmi_pll" },
};
static struct freq_tbl clk_tbl_tv[] = {
{ .src = P_HDMI_PLL, .pre_div = 1 },
{ }
};
static struct clk_rcg tv_src = {
.ns_reg = 0x00f4,
.md_reg = 0x00f0,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_hdmi_map,
},
.freq_tbl = clk_tbl_tv,
.clkr = {
.enable_reg = 0x00ec,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "tv_src",
.parent_data = mmcc_pxo_hdmi,
.num_parents = ARRAY_SIZE(mmcc_pxo_hdmi),
.ops = &clk_rcg_bypass_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch tv_enc_clk = {
.halt_reg = 0x01d4,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x00ec,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "tv_enc_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch tv_dac_clk = {
.halt_reg = 0x01d4,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x00ec,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "tv_dac_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdp_tv_clk = {
.halt_reg = 0x01d4,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x00ec,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "mdp_tv_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch hdmi_tv_clk = {
.halt_reg = 0x01d4,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x00ec,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "hdmi_tv_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch rgb_tv_clk = {
.halt_reg = 0x0240,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x0124,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "rgb_tv_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch npl_tv_clk = {
.halt_reg = 0x0240,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x0124,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&tv_src.clkr.hw,
},
.num_parents = 1,
.name = "npl_tv_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch hdmi_app_clk = {
.halt_reg = 0x01cc,
.halt_bit = 25,
.clkr = {
.enable_reg = 0x005c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "pxo", .name = "pxo_board" },
},
.num_parents = 1,
.name = "hdmi_app_clk",
.ops = &clk_branch_ops,
},
},
};
static struct freq_tbl clk_tbl_vcodec[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 32000000, P_PLL8, 1, 12),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54860000, P_PLL8, 1, 7),
F_MN( 96000000, P_PLL8, 1, 4),
F_MN(133330000, P_PLL2, 1, 6),
F_MN(200000000, P_PLL2, 1, 4),
F_MN(228570000, P_PLL2, 2, 7),
F_MN(266670000, P_PLL2, 1, 3),
{ }
};
static struct clk_dyn_rcg vcodec_src = {
.ns_reg[0] = 0x0100,
.ns_reg[1] = 0x0100,
.md_reg[0] = 0x00fc,
.md_reg[1] = 0x0128,
.bank_reg = 0x00f8,
.mn[0] = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 31,
.mnctr_mode_shift = 6,
.n_val_shift = 11,
.m_val_shift = 8,
.width = 8,
},
.mn[1] = {
.mnctr_en_bit = 10,
.mnctr_reset_bit = 30,
.mnctr_mode_shift = 11,
.n_val_shift = 19,
.m_val_shift = 8,
.width = 8,
},
.s[0] = {
.src_sel_shift = 27,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.s[1] = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.mux_sel_bit = 13,
.freq_tbl = clk_tbl_vcodec,
.clkr = {
.enable_reg = 0x00f8,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vcodec_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_dyn_rcg_ops,
},
},
};
static struct clk_branch vcodec_clk = {
.halt_reg = 0x01d0,
.halt_bit = 29,
.clkr = {
.enable_reg = 0x00f8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vcodec_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_vpe[] = {
{ 27000000, P_PXO, 1 },
{ 34909000, P_PLL8, 11 },
{ 38400000, P_PLL8, 10 },
{ 64000000, P_PLL8, 6 },
{ 76800000, P_PLL8, 5 },
{ 96000000, P_PLL8, 4 },
{ 100000000, P_PLL2, 8 },
{ 160000000, P_PLL2, 5 },
{ }
};
static struct clk_rcg vpe_src = {
.ns_reg = 0x0118,
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_vpe,
.clkr = {
.enable_reg = 0x0110,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vpe_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch vpe_clk = {
.halt_reg = 0x01c8,
.halt_bit = 28,
.clkr = {
.enable_reg = 0x0110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpe_clk",
.parent_hws = (const struct clk_hw*[]){
&vpe_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_vfe[] = {
{ 13960000, P_PLL8, 1, 2, 55 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 36570000, P_PLL8, 1, 2, 21 },
{ 38400000, P_PLL8, 2, 1, 5 },
{ 45180000, P_PLL8, 1, 2, 17 },
{ 48000000, P_PLL8, 2, 1, 4 },
{ 54860000, P_PLL8, 1, 1, 7 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ 76800000, P_PLL8, 1, 1, 5 },
{ 96000000, P_PLL8, 2, 1, 2 },
{ 109710000, P_PLL8, 1, 2, 7 },
{ 128000000, P_PLL8, 1, 1, 3 },
{ 153600000, P_PLL8, 1, 2, 5 },
{ 200000000, P_PLL2, 2, 1, 2 },
{ 228570000, P_PLL2, 1, 2, 7 },
{ 266667000, P_PLL2, 1, 1, 3 },
{ 320000000, P_PLL2, 1, 2, 5 },
{ }
};
static struct clk_rcg vfe_src = {
.ns_reg = 0x0108,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 10,
.pre_div_width = 1,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_pll8_pll2_map,
},
.freq_tbl = clk_tbl_vfe,
.clkr = {
.enable_reg = 0x0104,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "vfe_src",
.parent_data = mmcc_pxo_pll8_pll2,
.num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch vfe_clk = {
.halt_reg = 0x01cc,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x0104,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vfe_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch vfe_csi_clk = {
.halt_reg = 0x01cc,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x0104,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&vfe_src.clkr.hw
},
.num_parents = 1,
.name = "vfe_csi_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gmem_axi_clk = {
.halt_reg = 0x01d8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gmem_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ijpeg_axi_clk = {
.hwcg_reg = 0x0018,
.hwcg_bit = 11,
.halt_reg = 0x01d8,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "ijpeg_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch mmss_imem_axi_clk = {
.hwcg_reg = 0x0018,
.hwcg_bit = 15,
.halt_reg = 0x01d8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "mmss_imem_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch jpegd_axi_clk = {
.halt_reg = 0x01d8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "jpegd_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vcodec_axi_b_clk = {
.hwcg_reg = 0x0114,
.hwcg_bit = 22,
.halt_reg = 0x01e8,
.halt_bit = 25,
.clkr = {
.enable_reg = 0x0114,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "vcodec_axi_b_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vcodec_axi_a_clk = {
.hwcg_reg = 0x0114,
.hwcg_bit = 24,
.halt_reg = 0x01e8,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x0114,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "vcodec_axi_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vcodec_axi_clk = {
.hwcg_reg = 0x0018,
.hwcg_bit = 13,
.halt_reg = 0x01d8,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "vcodec_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vfe_axi_clk = {
.halt_reg = 0x01d8,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "vfe_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch mdp_axi_clk = {
.hwcg_reg = 0x0018,
.hwcg_bit = 16,
.halt_reg = 0x01d8,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x0018,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "mdp_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch rot_axi_clk = {
.hwcg_reg = 0x0020,
.hwcg_bit = 25,
.halt_reg = 0x01d8,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x0020,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "rot_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vcap_axi_clk = {
.halt_reg = 0x0240,
.halt_bit = 20,
.hwcg_reg = 0x0244,
.hwcg_bit = 11,
.clkr = {
.enable_reg = 0x0244,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "vcap_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vpe_axi_clk = {
.hwcg_reg = 0x0020,
.hwcg_bit = 27,
.halt_reg = 0x01d8,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x0020,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "vpe_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gfx3d_axi_clk = {
.hwcg_reg = 0x0244,
.hwcg_bit = 24,
.halt_reg = 0x0240,
.halt_bit = 30,
.clkr = {
.enable_reg = 0x0244,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_axi_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch amp_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "amp_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch csi_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "csi_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dsi_m_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "dsi_m_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dsi_s_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 20,
.halt_reg = 0x01dc,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "dsi_s_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dsi2_m_ahb_clk = {
.halt_reg = 0x01d8,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "dsi2_m_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dsi2_s_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 15,
.halt_reg = 0x01dc,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "dsi2_s_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg dsi1_src = {
.ns_reg = 0x0054,
.md_reg = 0x0050,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi2_dsi1_map,
},
.clkr = {
.enable_reg = 0x004c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_src",
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch dsi1_clk = {
.halt_reg = 0x01d0,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x004c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi1_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi2_src = {
.ns_reg = 0x012c,
.md_reg = 0x00a8,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 14,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi2_dsi1_map,
},
.clkr = {
.enable_reg = 0x003c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_src",
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch dsi2_clk = {
.halt_reg = 0x01d0,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x003c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi2_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi1_byte_src = {
.ns_reg = 0x00b0,
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
},
.clkr = {
.enable_reg = 0x0090,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_byte_src",
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch dsi1_byte_clk = {
.halt_reg = 0x01cc,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x0090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi1_byte_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi1_byte_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi2_byte_src = {
.ns_reg = 0x012c,
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
},
.clkr = {
.enable_reg = 0x0130,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_byte_src",
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_bypass2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch dsi2_byte_clk = {
.halt_reg = 0x01cc,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x00b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi2_byte_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi2_byte_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi1_esc_src = {
.ns_reg = 0x0011c,
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
},
.clkr = {
.enable_reg = 0x00cc,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_esc_src",
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_esc_ops,
},
},
};
static struct clk_branch dsi1_esc_clk = {
.halt_reg = 0x01e8,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x00cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi1_esc_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi1_esc_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi2_esc_src = {
.ns_reg = 0x0150,
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
},
.clkr = {
.enable_reg = 0x013c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_esc_src",
.parent_data = mmcc_pxo_dsi1_dsi2_byte,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
.ops = &clk_rcg_esc_ops,
},
},
};
static struct clk_branch dsi2_esc_clk = {
.halt_reg = 0x01e8,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x013c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "dsi2_esc_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi2_esc_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi1_pixel_src = {
.ns_reg = 0x0138,
.md_reg = 0x0134,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi2_dsi1_map,
},
.clkr = {
.enable_reg = 0x0130,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi1_pixel_src",
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_pixel_ops,
},
},
};
static struct clk_branch dsi1_pixel_clk = {
.halt_reg = 0x01d0,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x0130,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdp_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi1_pixel_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg dsi2_pixel_src = {
.ns_reg = 0x00e4,
.md_reg = 0x00b8,
.mn = {
.mnctr_en_bit = 5,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 6,
.n_val_shift = 16,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 12,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = mmcc_pxo_dsi2_dsi1_map,
},
.clkr = {
.enable_reg = 0x0094,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_pixel_src",
.parent_data = mmcc_pxo_dsi2_dsi1,
.num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
.ops = &clk_rcg_pixel_ops,
},
},
};
static struct clk_branch dsi2_pixel_clk = {
.halt_reg = 0x01d0,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x0094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdp_pclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&dsi2_pixel_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gfx2d0_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 28,
.halt_reg = 0x01dc,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gfx2d0_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gfx2d1_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 29,
.halt_reg = 0x01dc,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gfx2d1_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gfx3d_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 27,
.halt_reg = 0x01dc,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch hdmi_m_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 21,
.halt_reg = 0x01dc,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "hdmi_m_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch hdmi_s_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 22,
.halt_reg = 0x01dc,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "hdmi_s_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ijpeg_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "ijpeg_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch mmss_imem_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 12,
.halt_reg = 0x01dc,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "mmss_imem_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch jpegd_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "jpegd_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch mdp_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "mdp_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch rot_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "rot_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch smmu_ahb_clk = {
.hwcg_reg = 0x0008,
.hwcg_bit = 26,
.halt_reg = 0x01dc,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "smmu_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch tv_enc_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "tv_enc_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vcap_ahb_clk = {
.halt_reg = 0x0240,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x0248,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "vcap_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vcodec_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 26,
.halt_reg = 0x01dc,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "vcodec_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vfe_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "vfe_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch vpe_ahb_clk = {
.halt_reg = 0x01dc,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x0008,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "vpe_ahb_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_regmap *mmcc_msm8960_clks[] = {
[TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
[AMP_AHB_CLK] = &_ahb_clk.clkr,
[DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
[JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
[GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
[DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
[DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
[VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
[SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
[HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
[VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
[ROT_AHB_CLK] = &rot_ahb_clk.clkr,
[VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
[MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
[DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
[CSI_AHB_CLK] = &csi_ahb_clk.clkr,
[MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
[IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
[HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
[GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
[GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
[JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
[GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
[MDP_AXI_CLK] = &mdp_axi_clk.clkr,
[MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
[IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
[GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
[VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
[VFE_AXI_CLK] = &vfe_axi_clk.clkr,
[VPE_AXI_CLK] = &vpe_axi_clk.clkr,
[ROT_AXI_CLK] = &rot_axi_clk.clkr,
[VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
[VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
[CSI0_SRC] = &csi0_src.clkr,
[CSI0_CLK] = &csi0_clk.clkr,
[CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
[CSI1_SRC] = &csi1_src.clkr,
[CSI1_CLK] = &csi1_clk.clkr,
[CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
[CSI2_SRC] = &csi2_src.clkr,
[CSI2_CLK] = &csi2_clk.clkr,
[CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
[DSI_SRC] = &dsi1_src.clkr,
[DSI_CLK] = &dsi1_clk.clkr,
[CSI_PIX_CLK] = &csi_pix_clk.clkr,
[CSI_RDI_CLK] = &csi_rdi_clk.clkr,
[MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
[HDMI_APP_CLK] = &hdmi_app_clk.clkr,
[CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
[CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
[CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
[GFX2D0_SRC] = &gfx2d0_src.clkr,
[GFX2D0_CLK] = &gfx2d0_clk.clkr,
[GFX2D1_SRC] = &gfx2d1_src.clkr,
[GFX2D1_CLK] = &gfx2d1_clk.clkr,
[GFX3D_SRC] = &gfx3d_src.clkr,
[GFX3D_CLK] = &gfx3d_clk.clkr,
[IJPEG_SRC] = &ijpeg_src.clkr,
[IJPEG_CLK] = &ijpeg_clk.clkr,
[JPEGD_SRC] = &jpegd_src.clkr,
[JPEGD_CLK] = &jpegd_clk.clkr,
[MDP_SRC] = &mdp_src.clkr,
[MDP_CLK] = &mdp_clk.clkr,
[MDP_LUT_CLK] = &mdp_lut_clk.clkr,
[DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
[DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
[DSI2_SRC] = &dsi2_src.clkr,
[DSI2_CLK] = &dsi2_clk.clkr,
[DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
[DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
[DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
[DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
[DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
[DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
[DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
[DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
[ROT_SRC] = &rot_src.clkr,
[ROT_CLK] = &rot_clk.clkr,
[TV_ENC_CLK] = &tv_enc_clk.clkr,
[TV_DAC_CLK] = &tv_dac_clk.clkr,
[HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
[MDP_TV_CLK] = &mdp_tv_clk.clkr,
[TV_SRC] = &tv_src.clkr,
[VCODEC_SRC] = &vcodec_src.clkr,
[VCODEC_CLK] = &vcodec_clk.clkr,
[VFE_SRC] = &vfe_src.clkr,
[VFE_CLK] = &vfe_clk.clkr,
[VFE_CSI_CLK] = &vfe_csi_clk.clkr,
[VPE_SRC] = &vpe_src.clkr,
[VPE_CLK] = &vpe_clk.clkr,
[DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
[DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
[CAMCLK0_SRC] = &camclk0_src.clkr,
[CAMCLK0_CLK] = &camclk0_clk.clkr,
[CAMCLK1_SRC] = &camclk1_src.clkr,
[CAMCLK1_CLK] = &camclk1_clk.clkr,
[CAMCLK2_SRC] = &camclk2_src.clkr,
[CAMCLK2_CLK] = &camclk2_clk.clkr,
[CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
[CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
[CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
[CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
[PLL2] = &pll2.clkr,
};
static const struct qcom_reset_map mmcc_msm8960_resets[] = {
[VPE_AXI_RESET] = { 0x0208, 15 },
[IJPEG_AXI_RESET] = { 0x0208, 14 },
[MPD_AXI_RESET] = { 0x0208, 13 },
[VFE_AXI_RESET] = { 0x0208, 9 },
[SP_AXI_RESET] = { 0x0208, 8 },
[VCODEC_AXI_RESET] = { 0x0208, 7 },
[ROT_AXI_RESET] = { 0x0208, 6 },
[VCODEC_AXI_A_RESET] = { 0x0208, 5 },
[VCODEC_AXI_B_RESET] = { 0x0208, 4 },
[FAB_S3_AXI_RESET] = { 0x0208, 3 },
[FAB_S2_AXI_RESET] = { 0x0208, 2 },
[FAB_S1_AXI_RESET] = { 0x0208, 1 },
[FAB_S0_AXI_RESET] = { 0x0208 },
[SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
[SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
[SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
[SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
[SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
[SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
[SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
[SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
[SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
[SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
[SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
[SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
[APU_AHB_RESET] = { 0x020c, 18 },
[CSI_AHB_RESET] = { 0x020c, 17 },
[TV_ENC_AHB_RESET] = { 0x020c, 15 },
[VPE_AHB_RESET] = { 0x020c, 14 },
[FABRIC_AHB_RESET] = { 0x020c, 13 },
[GFX2D0_AHB_RESET] = { 0x020c, 12 },
[GFX2D1_AHB_RESET] = { 0x020c, 11 },
[GFX3D_AHB_RESET] = { 0x020c, 10 },
[HDMI_AHB_RESET] = { 0x020c, 9 },
[MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
[IJPEG_AHB_RESET] = { 0x020c, 7 },
[DSI_M_AHB_RESET] = { 0x020c, 6 },
[DSI_S_AHB_RESET] = { 0x020c, 5 },
[JPEGD_AHB_RESET] = { 0x020c, 4 },
[MDP_AHB_RESET] = { 0x020c, 3 },
[ROT_AHB_RESET] = { 0x020c, 2 },
[VCODEC_AHB_RESET] = { 0x020c, 1 },
[VFE_AHB_RESET] = { 0x020c, 0 },
[DSI2_M_AHB_RESET] = { 0x0210, 31 },
[DSI2_S_AHB_RESET] = { 0x0210, 30 },
[CSIPHY2_RESET] = { 0x0210, 29 },
[CSI_PIX1_RESET] = { 0x0210, 28 },
[CSIPHY0_RESET] = { 0x0210, 27 },
[CSIPHY1_RESET] = { 0x0210, 26 },
[DSI2_RESET] = { 0x0210, 25 },
[VFE_CSI_RESET] = { 0x0210, 24 },
[MDP_RESET] = { 0x0210, 21 },
[AMP_RESET] = { 0x0210, 20 },
[JPEGD_RESET] = { 0x0210, 19 },
[CSI1_RESET] = { 0x0210, 18 },
[VPE_RESET] = { 0x0210, 17 },
[MMSS_FABRIC_RESET] = { 0x0210, 16 },
[VFE_RESET] = { 0x0210, 15 },
[GFX2D0_RESET] = { 0x0210, 14 },
[GFX2D1_RESET] = { 0x0210, 13 },
[GFX3D_RESET] = { 0x0210, 12 },
[HDMI_RESET] = { 0x0210, 11 },
[MMSS_IMEM_RESET] = { 0x0210, 10 },
[IJPEG_RESET] = { 0x0210, 9 },
[CSI0_RESET] = { 0x0210, 8 },
[DSI_RESET] = { 0x0210, 7 },
[VCODEC_RESET] = { 0x0210, 6 },
[MDP_TV_RESET] = { 0x0210, 4 },
[MDP_VSYNC_RESET] = { 0x0210, 3 },
[ROT_RESET] = { 0x0210, 2 },
[TV_HDMI_RESET] = { 0x0210, 1 },
[TV_ENC_RESET] = { 0x0210 },
[CSI2_RESET] = { 0x0214, 2 },
[CSI_RDI1_RESET] = { 0x0214, 1 },
[CSI_RDI2_RESET] = { 0x0214 },
};
static struct clk_regmap *mmcc_apq8064_clks[] = {
[AMP_AHB_CLK] = &_ahb_clk.clkr,
[DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
[JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
[DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
[DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
[VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
[SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
[HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
[VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
[ROT_AHB_CLK] = &rot_ahb_clk.clkr,
[VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
[MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
[DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
[CSI_AHB_CLK] = &csi_ahb_clk.clkr,
[MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
[IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
[HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
[GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
[JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
[GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
[MDP_AXI_CLK] = &mdp_axi_clk.clkr,
[MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
[IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
[GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
[VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
[VFE_AXI_CLK] = &vfe_axi_clk.clkr,
[VPE_AXI_CLK] = &vpe_axi_clk.clkr,
[ROT_AXI_CLK] = &rot_axi_clk.clkr,
[VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
[VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
[CSI0_SRC] = &csi0_src.clkr,
[CSI0_CLK] = &csi0_clk.clkr,
[CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
[CSI1_SRC] = &csi1_src.clkr,
[CSI1_CLK] = &csi1_clk.clkr,
[CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
[CSI2_SRC] = &csi2_src.clkr,
[CSI2_CLK] = &csi2_clk.clkr,
[CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
[DSI_SRC] = &dsi1_src.clkr,
[DSI_CLK] = &dsi1_clk.clkr,
[CSI_PIX_CLK] = &csi_pix_clk.clkr,
[CSI_RDI_CLK] = &csi_rdi_clk.clkr,
[MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
[HDMI_APP_CLK] = &hdmi_app_clk.clkr,
[CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
[CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
[CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
[GFX3D_SRC] = &gfx3d_src.clkr,
[GFX3D_CLK] = &gfx3d_clk.clkr,
[IJPEG_SRC] = &ijpeg_src.clkr,
[IJPEG_CLK] = &ijpeg_clk.clkr,
[JPEGD_SRC] = &jpegd_src.clkr,
[JPEGD_CLK] = &jpegd_clk.clkr,
[MDP_SRC] = &mdp_src.clkr,
[MDP_CLK] = &mdp_clk.clkr,
[MDP_LUT_CLK] = &mdp_lut_clk.clkr,
[DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
[DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
[DSI2_SRC] = &dsi2_src.clkr,
[DSI2_CLK] = &dsi2_clk.clkr,
[DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
[DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
[DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
[DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
[DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
[DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
[DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
[DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
[ROT_SRC] = &rot_src.clkr,
[ROT_CLK] = &rot_clk.clkr,
[TV_DAC_CLK] = &tv_dac_clk.clkr,
[HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
[MDP_TV_CLK] = &mdp_tv_clk.clkr,
[TV_SRC] = &tv_src.clkr,
[VCODEC_SRC] = &vcodec_src.clkr,
[VCODEC_CLK] = &vcodec_clk.clkr,
[VFE_SRC] = &vfe_src.clkr,
[VFE_CLK] = &vfe_clk.clkr,
[VFE_CSI_CLK] = &vfe_csi_clk.clkr,
[VPE_SRC] = &vpe_src.clkr,
[VPE_CLK] = &vpe_clk.clkr,
[DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
[DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
[CAMCLK0_SRC] = &camclk0_src.clkr,
[CAMCLK0_CLK] = &camclk0_clk.clkr,
[CAMCLK1_SRC] = &camclk1_src.clkr,
[CAMCLK1_CLK] = &camclk1_clk.clkr,
[CAMCLK2_SRC] = &camclk2_src.clkr,
[CAMCLK2_CLK] = &camclk2_clk.clkr,
[CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
[CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
[CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
[CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
[PLL2] = &pll2.clkr,
[RGB_TV_CLK] = &rgb_tv_clk.clkr,
[NPL_TV_CLK] = &npl_tv_clk.clkr,
[VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
[VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
[VCAP_SRC] = &vcap_src.clkr,
[VCAP_CLK] = &vcap_clk.clkr,
[VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
[PLL15] = &pll15.clkr,
};
static const struct qcom_reset_map mmcc_apq8064_resets[] = {
[GFX3D_AXI_RESET] = { 0x0208, 17 },
[VCAP_AXI_RESET] = { 0x0208, 16 },
[VPE_AXI_RESET] = { 0x0208, 15 },
[IJPEG_AXI_RESET] = { 0x0208, 14 },
[MPD_AXI_RESET] = { 0x0208, 13 },
[VFE_AXI_RESET] = { 0x0208, 9 },
[SP_AXI_RESET] = { 0x0208, 8 },
[VCODEC_AXI_RESET] = { 0x0208, 7 },
[ROT_AXI_RESET] = { 0x0208, 6 },
[VCODEC_AXI_A_RESET] = { 0x0208, 5 },
[VCODEC_AXI_B_RESET] = { 0x0208, 4 },
[FAB_S3_AXI_RESET] = { 0x0208, 3 },
[FAB_S2_AXI_RESET] = { 0x0208, 2 },
[FAB_S1_AXI_RESET] = { 0x0208, 1 },
[FAB_S0_AXI_RESET] = { 0x0208 },
[SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
[SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
[SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
[SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
[SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
[SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
[SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
[SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
[SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
[SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
[APU_AHB_RESET] = { 0x020c, 18 },
[CSI_AHB_RESET] = { 0x020c, 17 },
[TV_ENC_AHB_RESET] = { 0x020c, 15 },
[VPE_AHB_RESET] = { 0x020c, 14 },
[FABRIC_AHB_RESET] = { 0x020c, 13 },
[GFX3D_AHB_RESET] = { 0x020c, 10 },
[HDMI_AHB_RESET] = { 0x020c, 9 },
[MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
[IJPEG_AHB_RESET] = { 0x020c, 7 },
[DSI_M_AHB_RESET] = { 0x020c, 6 },
[DSI_S_AHB_RESET] = { 0x020c, 5 },
[JPEGD_AHB_RESET] = { 0x020c, 4 },
[MDP_AHB_RESET] = { 0x020c, 3 },
[ROT_AHB_RESET] = { 0x020c, 2 },
[VCODEC_AHB_RESET] = { 0x020c, 1 },
[VFE_AHB_RESET] = { 0x020c, 0 },
[SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
[VCAP_AHB_RESET] = { 0x0200, 2 },
[DSI2_M_AHB_RESET] = { 0x0200, 1 },
[DSI2_S_AHB_RESET] = { 0x0200, 0 },
[CSIPHY2_RESET] = { 0x0210, 31 },
[CSI_PIX1_RESET] = { 0x0210, 30 },
[CSIPHY0_RESET] = { 0x0210, 29 },
[CSIPHY1_RESET] = { 0x0210, 28 },
[CSI_RDI_RESET] = { 0x0210, 27 },
[CSI_PIX_RESET] = { 0x0210, 26 },
[DSI2_RESET] = { 0x0210, 25 },
[VFE_CSI_RESET] = { 0x0210, 24 },
[MDP_RESET] = { 0x0210, 21 },
[AMP_RESET] = { 0x0210, 20 },
[JPEGD_RESET] = { 0x0210, 19 },
[CSI1_RESET] = { 0x0210, 18 },
[VPE_RESET] = { 0x0210, 17 },
[MMSS_FABRIC_RESET] = { 0x0210, 16 },
[VFE_RESET] = { 0x0210, 15 },
[GFX3D_RESET] = { 0x0210, 12 },
[HDMI_RESET] = { 0x0210, 11 },
[MMSS_IMEM_RESET] = { 0x0210, 10 },
[IJPEG_RESET] = { 0x0210, 9 },
[CSI0_RESET] = { 0x0210, 8 },
[DSI_RESET] = { 0x0210, 7 },
[VCODEC_RESET] = { 0x0210, 6 },
[MDP_TV_RESET] = { 0x0210, 4 },
[MDP_VSYNC_RESET] = { 0x0210, 3 },
[ROT_RESET] = { 0x0210, 2 },
[TV_HDMI_RESET] = { 0x0210, 1 },
[VCAP_NPL_RESET] = { 0x0214, 4 },
[VCAP_RESET] = { 0x0214, 3 },
[CSI2_RESET] = { 0x0214, 2 },
[CSI_RDI1_RESET] = { 0x0214, 1 },
[CSI_RDI2_RESET] = { 0x0214 },
};
static const struct regmap_config mmcc_msm8960_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x334,
.fast_io = true,
};
static const struct regmap_config mmcc_apq8064_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x350,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_msm8960_desc = {
.config = &mmcc_msm8960_regmap_config,
.clks = mmcc_msm8960_clks,
.num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
.resets = mmcc_msm8960_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
};
static const struct qcom_cc_desc mmcc_apq8064_desc = {
.config = &mmcc_apq8064_regmap_config,
.clks = mmcc_apq8064_clks,
.num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
.resets = mmcc_apq8064_resets,
.num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
};
static const struct of_device_id mmcc_msm8960_match_table[] = {
{ .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
{ .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
static int mmcc_msm8960_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct regmap *regmap;
bool is_8064;
struct device *dev = &pdev->dev;
match = of_match_device(mmcc_msm8960_match_table, dev);
if (!match)
return -EINVAL;
is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
if (is_8064) {
gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
}
regmap = qcom_cc_map(pdev, match->data);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
return qcom_cc_really_probe(pdev, match->data, regmap);
}
static struct platform_driver mmcc_msm8960_driver = {
.probe = mmcc_msm8960_probe,
.driver = {
.name = "mmcc-msm8960",
.of_match_table = mmcc_msm8960_match_table,
},
};
module_platform_driver(mmcc_msm8960_driver);
MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mmcc-msm8960");
| linux-master | drivers/clk/qcom/mmcc-msm8960.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, Linaro Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_EVEN,
P_GPLL5_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.clkr = {
.enable_reg = 0x6d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_lucid_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.post_div_shift = 8,
.post_div_table = post_div_table_lucid_even,
.num_post_div = ARRAY_SIZE(post_div_table_lucid_even),
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.clkr = {
.enable_reg = 0x6d000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4_out_even = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.post_div_shift = 8,
.post_div_table = post_div_table_lucid_even,
.num_post_div = ARRAY_SIZE(post_div_table_lucid_even),
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gpll5 = {
.offset = 0x74000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.clkr = {
.enable_reg = 0x6d000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll5",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parents_0_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_EVEN, 2 },
{ P_GPLL5_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4_out_even.clkr.hw },
{ .hw = &gpll5.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_EVEN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4_out_even.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x11024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_BI_TCXO, 10, 1, 2),
F(4800000, P_BI_TCXO, 4, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x1100c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x13024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x1300c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x15024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x1500c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x17024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x1700c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x1200c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x1800c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x24010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0_ao,
.num_parents = ARRAY_SIZE(gcc_parents_0_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
.cmd_rcgr = 0x2402c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk_src",
.parent_data = gcc_parents_0_ao,
.num_parents = ARRAY_SIZE(gcc_parents_0_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_clk_src[] = {
F(2500000, P_BI_TCXO, 1, 25, 192),
F(5000000, P_BI_TCXO, 1, 25, 96),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac_clk_src = {
.cmd_rcgr = 0x47020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_emac_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac_ptp_clk_src = {
.cmd_rcgr = 0x47038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_emac_ptp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x2b004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x2c004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x2d004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
.cmd_rcgr = 0x37034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_phy_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
.cmd_rcgr = 0x37050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_rchng_phy_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x19010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0xf00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_master_clk_src = {
.cmd_rcgr = 0xb024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0xb03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
F(1000000, P_BI_TCXO, 1, 5, 96),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
.cmd_rcgr = 0xb064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ahb_pcie_link_clk = {
.halt_reg = 0x22004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x22004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb_pcie_link_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x10004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x11008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x11004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x13008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x15008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x15004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x12004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x18004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1c004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1c004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x2100c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2100c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x21008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x24008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x24008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_rbcpr_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_axi_clk = {
.halt_reg = 0x4701c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_ptp_clk = {
.halt_reg = 0x47018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_ptp_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_emac_ptp_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_rgmii_clk = {
.halt_reg = 0x47010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_rgmii_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_emac_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_slave_ahb_clk = {
.halt_reg = 0x47014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_slave_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x2b000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x2c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x2d000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_clk = {
.halt_reg = 0x88004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x88004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_aux_clk = {
.halt_reg = 0x37024,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_cfg_ahb_clk = {
.halt_reg = 0x3701c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_mstr_axi_clk = {
.halt_reg = 0x37018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_pipe_clk = {
.halt_reg = 0x3702c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rchng_phy_clk = {
.halt_reg = 0x37020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_rchng_phy_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_rchng_phy_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_sleep_clk = {
.halt_reg = 0x37028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_sleep_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_aux_phy_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_slv_axi_clk = {
.halt_reg = 0x37014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x37014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
.halt_reg = 0x37010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x1900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x19004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x19004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x19004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x19008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x19008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0xf008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0xf004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0xb010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mstr_axi_clk = {
.halt_reg = 0xb014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_slv_ahb_clk = {
.halt_reg = 0xb018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0xb058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0xb05c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb05c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x88000,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x88000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0xe004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xe004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_pcie_link_clk = {
.halt_reg = 0x22008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x22008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_pcie_link_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb30_gdsc = {
.gdscr = 0x0b004,
.pd = {
.name = "usb30_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_gdsc = {
.gdscr = 0x37004,
.pd = {
.name = "pcie_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc emac_gdsc = {
.gdscr = 0x47004,
.pd = {
.name = "emac_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_sdx55_clocks[] = {
[GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] =
&gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] =
&gcc_blsp1_qup1_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] =
&gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] =
&gcc_blsp1_qup2_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] =
&gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] =
&gcc_blsp1_qup3_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] =
&gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] =
&gcc_blsp1_qup4_spi_apps_clk_src.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
[GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr,
[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
[GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
[GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
[GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
[GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
[GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
[GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
[GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
[GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
[GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
[GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
[GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
[GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
[GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
[GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
[GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
[GPLL5] = &gpll5.clkr,
};
static const struct qcom_reset_map gcc_sdx55_resets[] = {
[GCC_EMAC_BCR] = { 0x47000 },
[GCC_PCIE_BCR] = { 0x37000 },
[GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
[GCC_PCIE_PHY_BCR] = { 0x39000 },
[GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
[GCC_QUSB2PHY_BCR] = { 0xd000 },
[GCC_USB30_BCR] = { 0xb000 },
[GCC_USB3_PHY_BCR] = { 0xc000 },
[GCC_USB3PHY_PHY_BCR] = { 0xc004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
};
static struct gdsc *gcc_sdx55_gdscs[] = {
[USB30_GDSC] = &usb30_gdsc,
[PCIE_GDSC] = &pcie_gdsc,
[EMAC_GDSC] = &emac_gdsc,
};
static const struct regmap_config gcc_sdx55_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9b040,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sdx55_desc = {
.config = &gcc_sdx55_regmap_config,
.clks = gcc_sdx55_clocks,
.num_clks = ARRAY_SIZE(gcc_sdx55_clocks),
.resets = gcc_sdx55_resets,
.num_resets = ARRAY_SIZE(gcc_sdx55_resets),
.gdscs = gcc_sdx55_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs),
};
static const struct of_device_id gcc_sdx55_match_table[] = {
{ .compatible = "qcom,gcc-sdx55" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table);
static int gcc_sdx55_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sdx55_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Keep the clocks always-ON as they are critical to the functioning
* of the system:
* GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
*/
regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap);
}
static struct platform_driver gcc_sdx55_driver = {
.probe = gcc_sdx55_probe,
.driver = {
.name = "gcc-sdx55",
.of_match_table = gcc_sdx55_match_table,
},
};
static int __init gcc_sdx55_init(void)
{
return platform_driver_register(&gcc_sdx55_driver);
}
subsys_initcall(gcc_sdx55_init);
static void __exit gcc_sdx55_exit(void)
{
platform_driver_unregister(&gcc_sdx55_driver);
}
module_exit(gcc_sdx55_exit);
MODULE_DESCRIPTION("QTI GCC SDX55 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sdx55.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
/*
* Each of the CPU clusters (Power and Perf) on msm8996 are
* clocked via 2 PLLs, a primary and alternate. There are also
* 2 Mux'es, a primary and secondary all connected together
* as shown below
*
* +-------+
* XO | |
* +------------------>0 |
* SYS_APCS_AUX | |
* +------------------>3 |
* | |
* PLL/2 | SMUX +----+
* +------->1 | |
* | | | |
* | +-------+ | +-------+
* | +---->0 |
* | | |
* +---------------+ | +----------->1 | CPU clk
* |Primary PLL +----+ PLL_EARLY | | +------>
* | +------+-----------+ +------>2 PMUX |
* +---------------+ | | | |
* | +------+ | +-->3 |
* +--^+ ACD +-----+ | +-------+
* +---------------+ +------+ |
* |Alt PLL | |
* | +---------------------------+
* +---------------+ PLL_EARLY
*
* The primary PLL is what drives the CPU clk, except for times
* when we are reprogramming the PLL itself (for rate changes) when
* we temporarily switch to an alternate PLL.
*
* The primary PLL operates on a single VCO range, between 600MHz
* and 3GHz. However the CPUs do support OPPs with frequencies
* between 300MHz and 600MHz. In order to support running the CPUs
* at those frequencies we end up having to lock the PLL at twice
* the rate and drive the CPU clk via the PLL/2 output and SMUX.
*
* So for frequencies above 600MHz we follow the following path
* Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
* and for frequencies between 300MHz and 600MHz we follow
* Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
*
* ACD stands for Adaptive Clock Distribution and is used to
* detect voltage droops.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <soc/qcom/kryo-l2-accessors.h>
#include <asm/cputype.h>
#include "clk-alpha-pll.h"
#include "clk-regmap.h"
#include "clk-regmap-mux.h"
enum _pmux_input {
SMUX_INDEX = 0,
PLL_INDEX,
ACD_INDEX,
ALT_INDEX,
NUM_OF_PMUX_INPUTS
};
#define DIV_2_THRESHOLD 600000000
#define PWRCL_REG_OFFSET 0x0
#define PERFCL_REG_OFFSET 0x80000
#define MUX_OFFSET 0x40
#define CLK_CTL_OFFSET 0x44
#define CLK_CTL_AUTO_CLK_SEL BIT(8)
#define ALT_PLL_OFFSET 0x100
#define SSSCTL_OFFSET 0x160
#define PSCTL_OFFSET 0x164
#define PMUX_MASK 0x3
#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)
#define MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \
FIELD_PREP(MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03)
static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL_U] = 0x1c,
[PLL_OFF_TEST_CTL] = 0x20,
[PLL_OFF_TEST_CTL_U] = 0x24,
[PLL_OFF_STATUS] = 0x28,
};
static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x18,
[PLL_OFF_TEST_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x28,
};
/* PLLs */
static const struct alpha_pll_config hfpll_config = {
.l = 54,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x006,
.test_ctl_val = 0x1c000000,
.test_ctl_hi_val = 0x00004000,
.pre_div_mask = BIT(12),
.post_div_mask = 0x3 << 8,
.post_div_val = 0x1 << 8,
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
};
static const struct clk_parent_data pll_parent[] = {
{ .fw_name = "xo" },
};
static struct clk_alpha_pll pwrcl_pll = {
.offset = PWRCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "pwrcl_pll",
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
static struct clk_alpha_pll perfcl_pll = {
.offset = PERFCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "perfcl_pll",
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
static struct clk_fixed_factor pwrcl_pll_postdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "pwrcl_pll_postdiv",
.parent_data = &(const struct clk_parent_data){
.hw = &pwrcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor perfcl_pll_postdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "perfcl_pll_postdiv",
.parent_data = &(const struct clk_parent_data){
.hw = &perfcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor perfcl_pll_acd = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "perfcl_pll_acd",
.parent_data = &(const struct clk_parent_data){
.hw = &perfcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor pwrcl_pll_acd = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "pwrcl_pll_acd",
.parent_data = &(const struct clk_parent_data){
.hw = &pwrcl_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct pll_vco alt_pll_vco_modes[] = {
VCO(3, 250000000, 500000000),
VCO(2, 500000000, 750000000),
VCO(1, 750000000, 1000000000),
VCO(0, 1000000000, 2150400000),
};
static const struct alpha_pll_config altpll_config = {
.l = 16,
.vco_val = 0x3 << 20,
.vco_mask = 0x3 << 20,
.config_ctl_val = 0x4001051b,
.post_div_mask = 0x3 << 8,
.post_div_val = 0x1 << 8,
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
};
static struct clk_alpha_pll pwrcl_alt_pll = {
.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_alt_pll",
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
static struct clk_alpha_pll perfcl_alt_pll = {
.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_alt_pll",
.parent_data = pll_parent,
.num_parents = ARRAY_SIZE(pll_parent),
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
struct clk_cpu_8996_pmux {
u32 reg;
struct notifier_block nb;
struct clk_regmap clkr;
};
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data);
#define to_clk_cpu_8996_pmux_nb(_nb) \
container_of(_nb, struct clk_cpu_8996_pmux, nb)
static inline struct clk_cpu_8996_pmux *to_clk_cpu_8996_pmux_hw(struct clk_hw *hw)
{
return container_of(to_clk_regmap(hw), struct clk_cpu_8996_pmux, clkr);
}
static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw);
u32 val;
regmap_read(clkr->regmap, cpuclk->reg, &val);
return FIELD_GET(PMUX_MASK, val);
}
static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw);
u32 val;
val = FIELD_PREP(PMUX_MASK, index);
return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val);
}
static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw *parent;
if (req->rate < (DIV_2_THRESHOLD / 2))
return -EINVAL;
if (req->rate < DIV_2_THRESHOLD)
parent = clk_hw_get_parent_by_index(hw, SMUX_INDEX);
else
parent = clk_hw_get_parent_by_index(hw, ACD_INDEX);
if (!parent)
return -EINVAL;
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
req->best_parent_hw = parent;
return 0;
}
static const struct clk_ops clk_cpu_8996_pmux_ops = {
.set_parent = clk_cpu_8996_pmux_set_parent,
.get_parent = clk_cpu_8996_pmux_get_parent,
.determine_rate = clk_cpu_8996_pmux_determine_rate,
};
static const struct parent_map smux_parent_map[] = {
{ .cfg = 0, }, /* xo */
{ .cfg = 1, }, /* pll */
{ .cfg = 3, }, /* sys_apcs_aux */
};
static const struct clk_parent_data pwrcl_smux_parents[] = {
{ .fw_name = "xo" },
{ .hw = &pwrcl_pll_postdiv.hw },
{ .fw_name = "sys_apcs_aux" },
};
static const struct clk_parent_data perfcl_smux_parents[] = {
{ .fw_name = "xo" },
{ .hw = &perfcl_pll_postdiv.hw },
{ .fw_name = "sys_apcs_aux" },
};
static struct clk_regmap_mux pwrcl_smux = {
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.parent_map = smux_parent_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_smux",
.parent_data = pwrcl_smux_parents,
.num_parents = ARRAY_SIZE(pwrcl_smux_parents),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap_mux perfcl_smux = {
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.parent_map = smux_parent_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_smux",
.parent_data = perfcl_smux_parents,
.num_parents = ARRAY_SIZE(perfcl_smux_parents),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_hw *pwrcl_pmux_parents[] = {
[SMUX_INDEX] = &pwrcl_smux.clkr.hw,
[PLL_INDEX] = &pwrcl_pll.clkr.hw,
[ACD_INDEX] = &pwrcl_pll_acd.hw,
[ALT_INDEX] = &pwrcl_alt_pll.clkr.hw,
};
static const struct clk_hw *perfcl_pmux_parents[] = {
[SMUX_INDEX] = &perfcl_smux.clkr.hw,
[PLL_INDEX] = &perfcl_pll.clkr.hw,
[ACD_INDEX] = &perfcl_pll_acd.hw,
[ALT_INDEX] = &perfcl_alt_pll.clkr.hw,
};
static struct clk_cpu_8996_pmux pwrcl_pmux = {
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_pmux",
.parent_hws = pwrcl_pmux_parents,
.num_parents = ARRAY_SIZE(pwrcl_pmux_parents),
.ops = &clk_cpu_8996_pmux_ops,
/* CPU clock is critical and should never be gated */
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
};
static struct clk_cpu_8996_pmux perfcl_pmux = {
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_pmux",
.parent_hws = perfcl_pmux_parents,
.num_parents = ARRAY_SIZE(perfcl_pmux_parents),
.ops = &clk_cpu_8996_pmux_ops,
/* CPU clock is critical and should never be gated */
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
};
static const struct regmap_config cpu_msm8996_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80210,
.fast_io = true,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
static struct clk_hw *cpu_msm8996_hw_clks[] = {
&pwrcl_pll_postdiv.hw,
&perfcl_pll_postdiv.hw,
&pwrcl_pll_acd.hw,
&perfcl_pll_acd.hw,
};
static struct clk_regmap *cpu_msm8996_clks[] = {
&pwrcl_pll.clkr,
&perfcl_pll.clkr,
&pwrcl_alt_pll.clkr,
&perfcl_alt_pll.clkr,
&pwrcl_smux.clkr,
&perfcl_smux.clkr,
&pwrcl_pmux.clkr,
&perfcl_pmux.clkr,
};
static void qcom_cpu_clk_msm8996_acd_init(struct regmap *regmap);
static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
struct regmap *regmap)
{
int i, ret;
/* Select GPLL0 for 300MHz for both clusters */
regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc);
regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc);
/* Ensure write goes through before PLLs are reconfigured */
udelay(5);
/* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */
regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET,
MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
regmap_update_bits(regmap, PERFCL_REG_OFFSET + MUX_OFFSET,
MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
/* Wait for PLL(s) to lock */
udelay(50);
/* Enable auto clock selection for both clusters */
regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET,
CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
regmap_update_bits(regmap, PERFCL_REG_OFFSET + CLK_CTL_OFFSET,
CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
/* Ensure write goes through before muxes are switched */
udelay(5);
qcom_cpu_clk_msm8996_acd_init(regmap);
/* Pulse swallower and soft-start settings */
regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
regmap_write(regmap, PERFCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
/* Switch clusters to use the ACD leg */
regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32);
regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x32);
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) {
ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);
if (ret)
return ret;
}
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
if (ret)
return ret;
}
/* Enable alt PLLs */
clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
devm_clk_notifier_register(dev, pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
devm_clk_notifier_register(dev, perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
return ret;
}
#define CPU_CLUSTER_AFFINITY_MASK 0xf00
#define PWRCL_AFFINITY_MASK 0x000
#define PERFCL_AFFINITY_MASK 0x100
#define L2ACDCR_REG 0x580ULL
#define L2ACDTD_REG 0x581ULL
#define L2ACDDVMRC_REG 0x584ULL
#define L2ACDSSCR_REG 0x589ULL
static DEFINE_SPINLOCK(qcom_clk_acd_lock);
static void qcom_cpu_clk_msm8996_acd_init(struct regmap *regmap)
{
u64 hwid;
u32 val;
unsigned long flags;
spin_lock_irqsave(&qcom_clk_acd_lock, flags);
val = kryo_l2_get_indirect_reg(L2ACDTD_REG);
if (val == 0x00006a11)
goto out;
kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11);
kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f);
kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
hwid = read_cpuid_mpidr();
if ((hwid & CPU_CLUSTER_AFFINITY_MASK) == PWRCL_AFFINITY_MASK)
regmap_write(regmap, PWRCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
else
regmap_write(regmap, PERFCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);
out:
spin_unlock_irqrestore(&qcom_clk_acd_lock, flags);
}
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb);
struct clk_notifier_data *cnd = data;
switch (event) {
case PRE_RATE_CHANGE:
qcom_cpu_clk_msm8996_acd_init(cpuclk->clkr.regmap);
/*
* Avoid overvolting. clk_core_set_rate_nolock() walks from top
* to bottom, so it will change the rate of the PLL before
* chaging the parent of PMUX. This can result in pmux getting
* clocked twice the expected rate.
*
* Manually switch to PLL/2 here.
*/
if (cnd->new_rate < DIV_2_THRESHOLD &&
cnd->old_rate > DIV_2_THRESHOLD)
clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, SMUX_INDEX);
break;
case ABORT_RATE_CHANGE:
/* Revert manual change */
if (cnd->new_rate < DIV_2_THRESHOLD &&
cnd->old_rate > DIV_2_THRESHOLD)
clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX);
break;
default:
break;
}
return NOTIFY_OK;
};
static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
{
static void __iomem *base;
struct regmap *regmap;
struct clk_hw_onecell_data *data;
struct device *dev = &pdev->dev;
int ret;
data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->num = 2;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
if (ret)
return ret;
data->hws[0] = &pwrcl_pmux.clkr.hw;
data->hws[1] = &perfcl_pmux.clkr.hw;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
}
static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
{ .compatible = "qcom,msm8996-apcc" },
{}
};
MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table);
static struct platform_driver qcom_cpu_clk_msm8996_driver = {
.probe = qcom_cpu_clk_msm8996_driver_probe,
.driver = {
.name = "qcom-msm8996-apcc",
.of_match_table = qcom_cpu_clk_msm8996_match_table,
},
};
module_platform_driver(qcom_cpu_clk_msm8996_driver);
MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/clk-cpu-8996.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
static struct clk_parent_data pxo_parent_data = {
.fw_name = "pxo", .name = "pxo_board",
};
static struct clk_pll pll4 = {
.l_reg = 0x4,
.m_reg = 0x8,
.n_reg = 0xc,
.config_reg = 0x14,
.mode_reg = 0x0,
.status_reg = 0x18,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll4",
.parent_data = &pxo_parent_data,
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
enum {
P_PXO,
P_PLL4,
};
static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PXO, 0 },
{ P_PLL4, 2 }
};
static struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_osr_492[] = {
{ 512000, P_PLL4, 4, 1, 240 },
{ 768000, P_PLL4, 4, 1, 160 },
{ 1024000, P_PLL4, 4, 1, 120 },
{ 1536000, P_PLL4, 4, 1, 80 },
{ 2048000, P_PLL4, 4, 1, 60 },
{ 3072000, P_PLL4, 4, 1, 40 },
{ 4096000, P_PLL4, 4, 1, 30 },
{ 6144000, P_PLL4, 4, 1, 20 },
{ 8192000, P_PLL4, 4, 1, 15 },
{ 12288000, P_PLL4, 4, 1, 10 },
{ 24576000, P_PLL4, 4, 1, 5 },
{ 27000000, P_PXO, 1, 0, 0 },
{ }
};
static struct freq_tbl clk_tbl_aif_osr_393[] = {
{ 512000, P_PLL4, 4, 1, 192 },
{ 768000, P_PLL4, 4, 1, 128 },
{ 1024000, P_PLL4, 4, 1, 96 },
{ 1536000, P_PLL4, 4, 1, 64 },
{ 2048000, P_PLL4, 4, 1, 48 },
{ 3072000, P_PLL4, 4, 1, 32 },
{ 4096000, P_PLL4, 4, 1, 24 },
{ 6144000, P_PLL4, 4, 1, 16 },
{ 8192000, P_PLL4, 4, 1, 12 },
{ 12288000, P_PLL4, 4, 1, 8 },
{ 24576000, P_PLL4, 4, 1, 4 },
{ 27000000, P_PXO, 1, 0, 0 },
{ }
};
#define CLK_AIF_OSR_SRC(prefix, _ns, _md) \
static struct clk_rcg prefix##_osr_src = { \
.ns_reg = _ns, \
.md_reg = _md, \
.mn = { \
.mnctr_en_bit = 8, \
.mnctr_reset_bit = 7, \
.mnctr_mode_shift = 5, \
.n_val_shift = 24, \
.m_val_shift = 8, \
.width = 8, \
}, \
.p = { \
.pre_div_shift = 3, \
.pre_div_width = 2, \
}, \
.s = { \
.src_sel_shift = 0, \
.parent_map = lcc_pxo_pll4_map, \
}, \
.freq_tbl = clk_tbl_aif_osr_393, \
.clkr = { \
.enable_reg = _ns, \
.enable_mask = BIT(9), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_src", \
.parent_data = lcc_pxo_pll4, \
.num_parents = ARRAY_SIZE(lcc_pxo_pll4), \
.ops = &clk_rcg_ops, \
.flags = CLK_SET_RATE_GATE, \
}, \
}, \
}; \
#define CLK_AIF_OSR_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_osr_clk = { \
.halt_reg = hr, \
.halt_bit = 1, \
.halt_check = BRANCH_HALT_ENABLE, \
.clkr = { \
.enable_reg = _ns, \
.enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_osr_clk", \
.parent_hws = (const struct clk_hw*[]){ \
&prefix##_osr_src.clkr.hw, \
}, \
.num_parents = 1, \
.ops = &clk_branch_ops, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
}; \
#define CLK_AIF_OSR_DIV_CLK(prefix, _ns, _width) \
static struct clk_regmap_div prefix##_div_clk = { \
.reg = _ns, \
.shift = 10, \
.width = _width, \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_div_clk", \
.parent_hws = (const struct clk_hw*[]){ \
&prefix##_osr_src.clkr.hw, \
}, \
.num_parents = 1, \
.ops = &clk_regmap_div_ops, \
}, \
}, \
}; \
#define CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, en_bit) \
static struct clk_branch prefix##_bit_div_clk = { \
.halt_reg = hr, \
.halt_bit = 0, \
.halt_check = BRANCH_HALT_ENABLE, \
.clkr = { \
.enable_reg = _ns, \
.enable_mask = BIT(en_bit), \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_div_clk", \
.parent_hws = (const struct clk_hw*[]){ \
&prefix##_div_clk.clkr.hw, \
}, \
.num_parents = 1, \
.ops = &clk_branch_ops, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
}; \
#define CLK_AIF_OSR_BIT_CLK(prefix, _ns, _shift) \
static struct clk_regmap_mux prefix##_bit_clk = { \
.reg = _ns, \
.shift = _shift, \
.width = 1, \
.clkr = { \
.hw.init = &(struct clk_init_data){ \
.name = #prefix "_bit_clk", \
.parent_data = (const struct clk_parent_data[]){ \
{ .hw = &prefix##_bit_div_clk.clkr.hw, }, \
{ .fw_name = #prefix "_codec_clk", \
.name = #prefix "_codec_clk", }, \
}, \
.num_parents = 2, \
.ops = &clk_regmap_mux_closest_ops, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}, \
};
CLK_AIF_OSR_SRC(mi2s, 0x48, 0x4c)
CLK_AIF_OSR_CLK(mi2s, 0x48, 0x50, 17)
CLK_AIF_OSR_DIV_CLK(mi2s, 0x48, 4)
CLK_AIF_OSR_BIT_DIV_CLK(mi2s, 0x48, 0x50, 15)
CLK_AIF_OSR_BIT_CLK(mi2s, 0x48, 14)
#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
CLK_AIF_OSR_SRC(prefix, _ns, _md) \
CLK_AIF_OSR_CLK(prefix, _ns, hr, 21) \
CLK_AIF_OSR_DIV_CLK(prefix, _ns, 8) \
CLK_AIF_OSR_BIT_DIV_CLK(prefix, _ns, hr, 19) \
CLK_AIF_OSR_BIT_CLK(prefix, _ns, 18)
CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
static struct freq_tbl clk_tbl_pcm_492[] = {
{ 256000, P_PLL4, 4, 1, 480 },
{ 512000, P_PLL4, 4, 1, 240 },
{ 768000, P_PLL4, 4, 1, 160 },
{ 1024000, P_PLL4, 4, 1, 120 },
{ 1536000, P_PLL4, 4, 1, 80 },
{ 2048000, P_PLL4, 4, 1, 60 },
{ 3072000, P_PLL4, 4, 1, 40 },
{ 4096000, P_PLL4, 4, 1, 30 },
{ 6144000, P_PLL4, 4, 1, 20 },
{ 8192000, P_PLL4, 4, 1, 15 },
{ 12288000, P_PLL4, 4, 1, 10 },
{ 24576000, P_PLL4, 4, 1, 5 },
{ 27000000, P_PXO, 1, 0, 0 },
{ }
};
static struct freq_tbl clk_tbl_pcm_393[] = {
{ 256000, P_PLL4, 4, 1, 384 },
{ 512000, P_PLL4, 4, 1, 192 },
{ 768000, P_PLL4, 4, 1, 128 },
{ 1024000, P_PLL4, 4, 1, 96 },
{ 1536000, P_PLL4, 4, 1, 64 },
{ 2048000, P_PLL4, 4, 1, 48 },
{ 3072000, P_PLL4, 4, 1, 32 },
{ 4096000, P_PLL4, 4, 1, 24 },
{ 6144000, P_PLL4, 4, 1, 16 },
{ 8192000, P_PLL4, 4, 1, 12 },
{ 12288000, P_PLL4, 4, 1, 8 },
{ 24576000, P_PLL4, 4, 1, 4 },
{ 27000000, P_PXO, 1, 0, 0 },
{ }
};
static struct clk_rcg pcm_src = {
.ns_reg = 0x54,
.md_reg = 0x58,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_pcm_393,
.clkr = {
.enable_reg = 0x54,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcm_src",
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch pcm_clk_out = {
.halt_reg = 0x5c,
.halt_bit = 0,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x54,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcm_clk_out",
.parent_hws = (const struct clk_hw*[]){
&pcm_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_mux pcm_clk = {
.reg = 0x54,
.shift = 10,
.width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcm_clk",
.parent_data = (const struct clk_parent_data[]){
{ .hw = &pcm_clk_out.clkr.hw },
{ .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
},
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg slimbus_src = {
.ns_reg = 0xcc,
.md_reg = 0xd0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_aif_osr_393,
.clkr = {
.enable_reg = 0xcc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "slimbus_src",
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch audio_slimbus_clk = {
.halt_reg = 0xd4,
.halt_bit = 0,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0xcc,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "audio_slimbus_clk",
.parent_hws = (const struct clk_hw*[]){
&slimbus_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch sps_slimbus_clk = {
.halt_reg = 0xd4,
.halt_bit = 1,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0xcc,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "sps_slimbus_clk",
.parent_hws = (const struct clk_hw*[]){
&slimbus_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap *lcc_msm8960_clks[] = {
[PLL4] = &pll4.clkr,
[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
[PCM_SRC] = &pcm_src.clkr,
[PCM_CLK_OUT] = &pcm_clk_out.clkr,
[PCM_CLK] = &pcm_clk.clkr,
[SLIMBUS_SRC] = &slimbus_src.clkr,
[AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
[SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
[CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
[CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
[CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
[CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
[CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
[SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
[SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
[SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
[SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
[SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
[CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
[CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
[CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
[CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
[CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
[SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
[SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
[SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
[SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
[SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
};
static const struct regmap_config lcc_msm8960_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xfc,
.fast_io = true,
};
static const struct qcom_cc_desc lcc_msm8960_desc = {
.config = &lcc_msm8960_regmap_config,
.clks = lcc_msm8960_clks,
.num_clks = ARRAY_SIZE(lcc_msm8960_clks),
};
static const struct of_device_id lcc_msm8960_match_table[] = {
{ .compatible = "qcom,lcc-msm8960" },
{ .compatible = "qcom,lcc-apq8064" },
{ .compatible = "qcom,lcc-mdm9615" },
{ }
};
MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
static int lcc_msm8960_probe(struct platform_device *pdev)
{
u32 val;
struct regmap *regmap;
/* patch for the cxo <-> pxo difference */
if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) {
pxo_parent_data.fw_name = "cxo";
pxo_parent_data.name = "cxo_board";
lcc_pxo_pll4[0].fw_name = "cxo";
lcc_pxo_pll4[0].name = "cxo_board";
}
regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Use the correct frequency plan depending on speed of PLL4 */
regmap_read(regmap, 0x4, &val);
if (val == 0x12) {
slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
pcm_src.freq_tbl = clk_tbl_pcm_492;
}
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
}
static struct platform_driver lcc_msm8960_driver = {
.probe = lcc_msm8960_probe,
.driver = {
.name = "lcc-msm8960",
.of_match_table = lcc_msm8960_match_table,
},
};
module_platform_driver(lcc_msm8960_driver);
MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:lcc-msm8960");
| linux-master | drivers/clk/qcom/lcc-msm8960.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm SDX55 APCS clock controller driver
*
* Copyright (c) 2020, Linaro Limited
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "clk-regmap.h"
#include "clk-regmap-mux-div.h"
static const u32 apcs_mux_clk_parent_map[] = { 0, 1, 5 };
static const struct clk_parent_data pdata[] = {
{ .fw_name = "ref" },
{ .fw_name = "aux" },
{ .fw_name = "pll" },
};
/*
* We use the notifier function for switching to a temporary safe configuration
* (mux and divider), while the A7 PLL is reconfigured.
*/
static int a7cc_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
int ret = 0;
struct clk_regmap_mux_div *md = container_of(nb,
struct clk_regmap_mux_div,
clk_nb);
if (event == PRE_RATE_CHANGE)
/* set the mux and divider to safe frequency (400mhz) */
ret = mux_div_set_src_div(md, 1, 2);
return notifier_from_errno(ret);
}
static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct device *cpu_dev;
struct clk_regmap_mux_div *a7cc;
struct regmap *regmap;
struct clk_init_data init = { };
int ret;
regmap = dev_get_regmap(parent, NULL);
if (!regmap) {
dev_err(dev, "Failed to get parent regmap\n");
return -ENODEV;
}
a7cc = devm_kzalloc(dev, sizeof(*a7cc), GFP_KERNEL);
if (!a7cc)
return -ENOMEM;
init.name = "a7mux";
init.parent_data = pdata;
init.num_parents = ARRAY_SIZE(pdata);
init.ops = &clk_regmap_mux_div_ops;
a7cc->clkr.hw.init = &init;
a7cc->clkr.regmap = regmap;
a7cc->reg_offset = 0x8;
a7cc->hid_width = 5;
a7cc->hid_shift = 0;
a7cc->src_width = 3;
a7cc->src_shift = 8;
a7cc->parent_map = apcs_mux_clk_parent_map;
a7cc->pclk = devm_clk_get(parent, "pll");
if (IS_ERR(a7cc->pclk))
return dev_err_probe(dev, PTR_ERR(a7cc->pclk),
"Failed to get PLL clk\n");
a7cc->clk_nb.notifier_call = a7cc_notifier_cb;
ret = clk_notifier_register(a7cc->pclk, &a7cc->clk_nb);
if (ret)
return dev_err_probe(dev, ret,
"Failed to register clock notifier\n");
ret = devm_clk_register_regmap(dev, &a7cc->clkr);
if (ret) {
dev_err_probe(dev, ret, "Failed to register regmap clock\n");
goto err;
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&a7cc->clkr.hw);
if (ret) {
dev_err_probe(dev, ret, "Failed to add clock provider\n");
goto err;
}
platform_set_drvdata(pdev, a7cc);
/*
* Attach the power domain to cpudev. Since there is no dedicated driver
* for CPUs and the SDX55 platform lacks hardware specific CPUFreq
* driver, there seems to be no better place to do this. So do it here!
*/
cpu_dev = get_cpu_device(0);
dev_pm_domain_attach(cpu_dev, true);
return 0;
err:
clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
return ret;
}
static void qcom_apcs_sdx55_clk_remove(struct platform_device *pdev)
{
struct device *cpu_dev = get_cpu_device(0);
struct clk_regmap_mux_div *a7cc = platform_get_drvdata(pdev);
clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
dev_pm_domain_detach(cpu_dev, true);
}
static struct platform_driver qcom_apcs_sdx55_clk_driver = {
.probe = qcom_apcs_sdx55_clk_probe,
.remove_new = qcom_apcs_sdx55_clk_remove,
.driver = {
.name = "qcom-sdx55-acps-clk",
},
};
module_platform_driver(qcom_apcs_sdx55_clk_driver);
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm SDX55 APCS clock driver");
| linux-master | drivers/clk/qcom/apcs-sdx55.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6375-dispcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_DISP_GPLL0_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
};
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_EVEN,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GCC_DISP_GPLL0_CLK,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 615MHz */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x20,
.alpha = 0x800,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .index = DT_GCC_DISP_GPLL0_CLK },
{ .hw = &disp_cc_pll0.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_DISP_GPLL0_CLK },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x115c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x10c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x10e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
F(373500000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x107c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x1064,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x1094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x10ac,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x10dc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x104c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x102c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x1030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x1034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x1010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x1020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x1168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x1018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x1028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_xo_clk = {
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x1004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct clk_regmap *disp_cc_sm6375_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
};
static const struct qcom_reset_map disp_cc_sm6375_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
};
static struct gdsc *disp_cc_sm6375_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static const struct regmap_config disp_cc_sm6375_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm6375_desc = {
.config = &disp_cc_sm6375_regmap_config,
.clks = disp_cc_sm6375_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6375_clocks),
.resets = disp_cc_sm6375_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm6375_resets),
.gdscs = disp_cc_sm6375_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6375_gdscs),
};
static const struct of_device_id disp_cc_sm6375_match_table[] = {
{ .compatible = "qcom,sm6375-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm6375_match_table);
static int disp_cc_sm6375_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &disp_cc_sm6375_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap);
}
static struct platform_driver disp_cc_sm6375_driver = {
.probe = disp_cc_sm6375_probe,
.driver = {
.name = "disp_cc-sm6375",
.of_match_table = disp_cc_sm6375_match_table,
},
};
static int __init disp_cc_sm6375_init(void)
{
return platform_driver_register(&disp_cc_sm6375_driver);
}
subsys_initcall(disp_cc_sm6375_init);
static void __exit disp_cc_sm6375_exit(void)
{
platform_driver_unregister(&disp_cc_sm6375_driver);
}
module_exit(disp_cc_sm6375_exit);
MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/dispcc-sm6375.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#define CX_GMU_CBCR_SLEEP_MASK 0xF
#define CX_GMU_CBCR_SLEEP_SHIFT 4
#define CX_GMU_CBCR_WAKE_MASK 0xF
#define CX_GMU_CBCR_WAKE_SHIFT 8
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.clk_dis_wait_val = 8,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO,
};
static struct gdsc *gpu_cc_sc7180_gdscs[] = {
[CX_GDSC] = &cx_gdsc,
[GX_GDSC] = &gx_gdsc,
};
static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
};
static const struct regmap_config gpu_cc_sc7180_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8008,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
.config = &gpu_cc_sc7180_regmap_config,
.clks = gpu_cc_sc7180_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
.gdscs = gpu_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
};
static const struct of_device_id gpu_cc_sc7180_match_table[] = {
{ .compatible = "qcom,sc7180-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
static int gpu_cc_sc7180_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config gpu_cc_pll_config = {};
unsigned int value, mask;
regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* 360MHz Configuration */
gpu_cc_pll_config.l = 0x12;
gpu_cc_pll_config.alpha = 0xc000;
gpu_cc_pll_config.config_ctl_val = 0x20485699;
gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
gpu_cc_pll_config.user_ctl_val = 0x00000001;
gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
}
static struct platform_driver gpu_cc_sc7180_driver = {
.probe = gpu_cc_sc7180_probe,
.driver = {
.name = "sc7180-gpucc",
.of_match_table = gpu_cc_sc7180_match_table,
},
};
static int __init gpu_cc_sc7180_init(void)
{
return platform_driver_register(&gpu_cc_sc7180_driver);
}
subsys_initcall(gpu_cc_sc7180_init);
static void __exit gpu_cc_sc7180_exit(void)
{
platform_driver_unregister(&gpu_cc_sc7180_driver);
}
module_exit(gpu_cc_sc7180_exit);
MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sc7180.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm APCS clock controller driver
*
* Copyright (c) 2017, Linaro Limited
* Author: Georgi Djakov <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "clk-regmap.h"
#include "clk-regmap-mux-div.h"
static const u32 gpll0_a53cc_map[] = { 4, 5 };
static const struct clk_parent_data pdata[] = {
{ .fw_name = "aux", .name = "gpll0_vote", },
{ .fw_name = "pll", .name = "a53pll", },
};
/*
* We use the notifier function for switching to a temporary safe configuration
* (mux and divider), while the A53 PLL is reconfigured.
*/
static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
int ret = 0;
struct clk_regmap_mux_div *md = container_of(nb,
struct clk_regmap_mux_div,
clk_nb);
if (event == PRE_RATE_CHANGE)
/* set the mux and divider to safe frequency (400mhz) */
ret = mux_div_set_src_div(md, 4, 3);
return notifier_from_errno(ret);
}
static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct device_node *np = parent->of_node;
struct clk_regmap_mux_div *a53cc;
struct regmap *regmap;
struct clk_init_data init = { };
int ret = -ENODEV;
regmap = dev_get_regmap(parent, NULL);
if (!regmap) {
dev_err(dev, "failed to get regmap: %d\n", ret);
return ret;
}
a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL);
if (!a53cc)
return -ENOMEM;
/* Use an unique name by appending parent's @unit-address */
init.name = devm_kasprintf(dev, GFP_KERNEL, "a53mux%s",
strchrnul(np->full_name, '@'));
if (!init.name)
return -ENOMEM;
init.parent_data = pdata;
init.num_parents = ARRAY_SIZE(pdata);
init.ops = &clk_regmap_mux_div_ops;
init.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT;
a53cc->clkr.hw.init = &init;
a53cc->clkr.regmap = regmap;
a53cc->reg_offset = 0x50;
a53cc->hid_width = 5;
a53cc->hid_shift = 0;
a53cc->src_width = 3;
a53cc->src_shift = 8;
a53cc->parent_map = gpll0_a53cc_map;
a53cc->pclk = devm_clk_get(parent, NULL);
if (IS_ERR(a53cc->pclk)) {
ret = PTR_ERR(a53cc->pclk);
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to get clk: %d\n", ret);
return ret;
}
a53cc->clk_nb.notifier_call = a53cc_notifier_cb;
ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
if (ret) {
dev_err(dev, "failed to register clock notifier: %d\n", ret);
return ret;
}
ret = devm_clk_register_regmap(dev, &a53cc->clkr);
if (ret) {
dev_err(dev, "failed to register regmap clock: %d\n", ret);
goto err;
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&a53cc->clkr.hw);
if (ret) {
dev_err(dev, "failed to add clock provider: %d\n", ret);
goto err;
}
platform_set_drvdata(pdev, a53cc);
return 0;
err:
clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
return ret;
}
static void qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
{
struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
}
static struct platform_driver qcom_apcs_msm8916_clk_driver = {
.probe = qcom_apcs_msm8916_clk_probe,
.remove_new = qcom_apcs_msm8916_clk_remove,
.driver = {
.name = "qcom-apcs-msm8916-clk",
},
};
module_platform_driver(qcom_apcs_msm8916_clk_driver);
MODULE_AUTHOR("Georgi Djakov <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");
| linux-master | drivers/clk/qcom/apcs-msm8916.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_XO,
DT_SLEEP_CLK,
DT_PCIE_0_PIPE_CLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_HDMI_PHY_PLL_CLK,
};
enum {
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
P_GPLL1_OUT_MAIN,
P_GPLL3_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_AUX,
P_HDMI_PHY_PLL_CLK,
P_PCIE_0_PIPE_CLK,
P_SLEEP_CLK,
P_XO,
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_XO, .name = "xo-board" },
};
static struct clk_fixed_factor cxo = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "cxo",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll0_sleep_clk_src = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45008,
.enable_mask = BIT(23),
.enable_is_inverted = true,
.hw.init = &(struct clk_init_data){
.name = "gpll0_sleep_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll0_out_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_FSM_MODE,
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll0_ao_out_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_FSM_MODE,
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_ao_out_main",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_IS_CRITICAL,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll gpll1_out_main = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_out_main",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
};
/* 930MHz configuration */
static const struct alpha_pll_config gpll3_config = {
.l = 48,
.alpha = 0x0,
.alpha_en_mask = BIT(24),
.post_div_mask = 0xf << 8,
.post_div_val = 0x1 << 8,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
.config_ctl_val = 0x4001055b,
};
static const struct pll_vco gpll3_vco[] = {
{ 700000000, 1400000000, 0 },
};
static struct clk_alpha_pll gpll3_out_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpll3_vco,
.num_vco = ARRAY_SIZE(gpll3_vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll4_out_main = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_pll gpll6 = {
.l_reg = 0x37004,
.m_reg = 0x37008,
.n_reg = 0x3700C,
.config_reg = 0x37014,
.mode_reg = 0x37000,
.status_reg = 0x3701C,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll6_out_aux = {
.enable_reg = 0x45000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_aux",
.parent_hws = (const struct clk_hw*[]) {
&gpll6.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_ao_0[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_ao_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_AUX, 2 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_XO, 0 },
{ P_GPLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll1_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL3_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll3_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_HDMI_PHY_PLL_CLK, 1 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
{ P_GPLL6_OUT_AUX, 3 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
{ .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 1 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_XO, 0 },
{ P_PCIE_0_PIPE_CLK, 1 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_XO, 0 },
};
static const struct clk_parent_data gcc_parent_data_15[] = {
{ .index = DT_XO, .name = "xo-board" },
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_16[] = {
{ .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_apss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_parent_data_ao_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_ao_0),
.flags = CLK_IS_CRITICAL,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
.cmd_rcgr = 0x602c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
.cmd_rcgr = 0x6034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x200c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x3000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0_OUT_MAIN, 1, 3, 160),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(30000000, P_GPLL0_OUT_MAIN, 1, 3, 80),
{ }
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x3014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x4000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x4024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x5000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x5024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
{ }
};
static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
.cmd_rcgr = 0x600c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart0_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x2044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x3034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x4014,
.mnd_width = 16,
.hid_width = 5,
.cfg_off = 0x20,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
.cmd_rcgr = 0xc00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
.cmd_rcgr = 0xc024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
.cmd_rcgr = 0xc044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart0_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_emac_clk_src[] = {
F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50),
F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 emac_clk_src = {
.cmd_rcgr = 0x4e01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_emac_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 emac_ptp_clk_src = {
.cmd_rcgr = 0x4e014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_emac_ptp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_ptp_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_esc0_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x8004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x9004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0xa004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 hdmi_app_clk_src = {
.cmd_rcgr = 0x4d0e4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_app_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 hdmi_pclk_clk_src = {
.cmd_rcgr = 0x4d0dc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_pclk_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
F(1200000, P_XO, 16, 0, 0),
{ }
};
static struct clk_rcg2 pcie_0_aux_clk_src = {
.cmd_rcgr = 0x3e024,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 pcie_0_pipe_clk_src = {
.cmd_rcgr = 0x3e01c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_pcie_0_pipe_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_13,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_14,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 usb20_mock_utmi_clk_src = {
.cmd_rcgr = 0x41048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_mock_utmi_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x39028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x3901c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x3903c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_usb_hs_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_15,
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = gcc_parent_data_15,
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cdsp_bimc_clk_src = {
.cmd_rcgr = 0x5e010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_16,
.freq_tbl = ftbl_cdsp_bimc_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cdsp_bimc_clk_src",
.parent_data = gcc_parent_data_16,
.num_parents = ARRAY_SIZE(gcc_parent_data_16),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&apss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x5b004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x59034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
.parent_hws = (const struct clk_hw*[]) {
&gcc_apss_tcu_clk.clkr.hw,
},
},
},
};
static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x59030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_cdsp_clk = {
.halt_reg = 0x31030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_cdsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cdsp_bimc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_mdss_clk = {
.halt_reg = 0x31038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_mdss_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_clk = {
.halt_reg = 0x77004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x77004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_xo_clk = {
.halt_reg = 0x77008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x77008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
.halt_reg = 0x6028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup0_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup0_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
.halt_reg = 0x6024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup0_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup0_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x3010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x4020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x5020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart0_apps_clk = {
.halt_reg = 0x6004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart0_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart0_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x302c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0xb008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
.halt_reg = 0xc008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup0_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup0_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
.halt_reg = 0xc004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup0_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup0_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart0_apps_clk = {
.halt_reg = 0xc03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart0_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_uart0_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_axi_clk = {
.halt_reg = 0x4e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_ptp_clk = {
.halt_reg = 0x4e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_ptp_clk",
.parent_hws = (const struct clk_hw*[]) {
&emac_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_rgmii_clk = {
.halt_reg = 0x4e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_rgmii_clk",
.parent_hws = (const struct clk_hw*[]) {
&emac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_slave_ahb_clk = {
.halt_reg = 0x4e00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_slave_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_geni_ir_s_clk = {
.halt_reg = 0xf008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_geni_ir_s_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_geni_ir_h_clk = {
.halt_reg = 0xf004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_geni_ir_h_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tcu_clk = {
.halt_reg = 0x12020,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4500C,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tbu_clk = {
.halt_reg = 0x12010,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4500C,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cdsp_tbu_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x13020,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cdsp_tbu_clk",
.parent_hws = (const struct clk_hw*[]) {
&cdsp_bimc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x8000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x9000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0xa000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]) {
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]) {
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_hdmi_app_clk = {
.halt_reg = 0x4d0d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0d8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_hdmi_app_clk",
.parent_hws = (const struct clk_hw*[]) {
&hdmi_app_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
.halt_reg = 0x4d0d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_hdmi_pclk_clk",
.parent_hws = (const struct clk_hw*[]) {
&hdmi_pclk_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4d088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]) {
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x3e014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x3e008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x3e018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x3e00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x3e010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcnoc_usb2_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcnoc_usb2_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcnoc_usb3_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcnoc_usb3_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
/* PWM clks do not have XO as parent as src clk is a balance root */
static struct clk_branch gcc_pwm0_xo512_clk = {
.halt_reg = 0x44018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x44018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pwm0_xo512_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pwm1_xo512_clk = {
.halt_reg = 0x49004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pwm1_xo512_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pwm2_xo512_clk = {
.halt_reg = 0x4a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pwm2_xo512_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qdss_dap_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x5d014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
.halt_reg = 0x5e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cdsp_cfg_ahb_cbcr",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x3600C,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_clk = {
.halt_reg = 0x26014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
.halt_reg = 0x4100C,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4100C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_mock_utmi_clk = {
.halt_reg = 0x41044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x3900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x39014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x39010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x39044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x39018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
.halt_reg = 0x41030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_phy_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wdsp_q6ss_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wdsp_q6ss_axim_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.pd = {
.name = "mdss",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gdsc = {
.gdscr = 0x5901c,
.pd = {
.name = "oxili",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_hw *gcc_qcs404_hws[] = {
&cxo.hw,
};
static struct clk_regmap *gcc_qcs404_clocks[] = {
[GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
[GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
[GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
[GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
[GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
[GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
[GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
[GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
[GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
[GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
[GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
[GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
[GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
[GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
[GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
[GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
[GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
[GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
[GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
[GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
[GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
[GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
[GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
[GCC_GPLL6] = &gpll6.clkr,
[GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
[GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
[GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
[GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
[GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
[GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
[GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
[GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
&gcc_usb_hs_inactivity_timers_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
[GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
[GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
};
static struct gdsc *gcc_qcs404_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
[OXILI_GDSC] = &oxili_gdsc,
};
static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_GENI_IR_BCR] = { 0x0F000 },
[GCC_CDSP_RESTART] = { 0x18000 },
[GCC_USB_HS_BCR] = { 0x41000 },
[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
[GCC_QUSB2_PHY_BCR] = { 0x4103c },
[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
[GCC_USB3_PHY_BCR] = { 0x39004 },
[GCC_USB_30_BCR] = { 0x39000 },
[GCC_USB3PHY_PHY_BCR] = { 0x39008 },
[GCC_PCIE_0_BCR] = { 0x3e000 },
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
[GCC_EMAC_BCR] = { 0x4e000 },
[GCC_WDSP_RESTART] = {0x19000},
};
static const struct regmap_config gcc_qcs404_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x7f000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_qcs404_desc = {
.config = &gcc_qcs404_regmap_config,
.clks = gcc_qcs404_clocks,
.num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
.resets = gcc_qcs404_resets,
.num_resets = ARRAY_SIZE(gcc_qcs404_resets),
.clk_hws = gcc_qcs404_hws,
.num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
.gdscs = gcc_qcs404_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs),
};
static const struct of_device_id gcc_qcs404_match_table[] = {
{ .compatible = "qcom,gcc-qcs404" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
static int gcc_qcs404_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
}
static struct platform_driver gcc_qcs404_driver = {
.probe = gcc_qcs404_probe,
.driver = {
.name = "gcc-qcs404",
.of_match_table = gcc_qcs404_match_table,
},
};
static int __init gcc_qcs404_init(void)
{
return platform_driver_register(&gcc_qcs404_driver);
}
core_initcall(gcc_qcs404_init);
static void __exit gcc_qcs404_exit(void)
{
platform_driver_unregister(&gcc_qcs404_driver);
}
module_exit(gcc_qcs404_exit);
MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-qcs404.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <soc/qcom/cmd-db.h>
#include <soc/qcom/rpmh.h>
#include <soc/qcom/tcs.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#define CLK_RPMH_ARC_EN_OFFSET 0
#define CLK_RPMH_VRM_EN_OFFSET 4
/**
* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
* @unit: divisor used to convert Hz value to an RPMh msg
* @width: multiplier used to convert Hz value to an RPMh msg
* @vcd: virtual clock domain that this bcm belongs to
* @reserved: reserved to pad the struct
*/
struct bcm_db {
__le32 unit;
__le16 width;
u8 vcd;
u8 reserved;
};
/**
* struct clk_rpmh - individual rpmh clock data structure
* @hw: handle between common and hardware-specific interfaces
* @res_name: resource name for the rpmh clock
* @div: clock divider to compute the clock rate
* @res_addr: base address of the rpmh resource within the RPMh
* @res_on_val: rpmh clock enable value
* @state: rpmh clock requested state
* @aggr_state: rpmh clock aggregated state
* @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
* @valid_state_mask: mask to determine the state of the rpmh clock
* @unit: divisor to convert rate to rpmh msg in magnitudes of Khz
* @dev: device to which it is attached
* @peer: pointer to the clock rpmh sibling
*/
struct clk_rpmh {
struct clk_hw hw;
const char *res_name;
u8 div;
u32 res_addr;
u32 res_on_val;
u32 state;
u32 aggr_state;
u32 last_sent_aggr_state;
u32 valid_state_mask;
u32 unit;
struct device *dev;
struct clk_rpmh *peer;
};
struct clk_rpmh_desc {
struct clk_hw **clks;
size_t num_clks;
};
static DEFINE_MUTEX(rpmh_clk_lock);
#define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \
_res_en_offset, _res_on, _div) \
static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \
static struct clk_rpmh clk_rpmh_##_clk_name = { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
.peer = &clk_rpmh_##_clk_name##_ao, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE) | \
BIT(RPMH_SLEEP_STATE)), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_ops, \
.name = #_name, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}; \
static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
.peer = &clk_rpmh_##_clk_name, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE)), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_ops, \
.name = #_name "_ao", \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}
#define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \
__DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
#define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \
__DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
static struct clk_rpmh clk_rpmh_##_name = { \
.res_name = _res_name, \
.valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
.div = 1, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_bcm_ops, \
.name = #_name, \
}, \
}
static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
{
return container_of(_hw, struct clk_rpmh, hw);
}
static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
{
return (c->last_sent_aggr_state & BIT(state))
!= (c->aggr_state & BIT(state));
}
static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state,
struct tcs_cmd *cmd, bool wait)
{
if (wait)
return rpmh_write(c->dev, state, cmd, 1);
return rpmh_write_async(c->dev, state, cmd, 1);
}
static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
{
struct tcs_cmd cmd = { 0 };
u32 cmd_state, on_val;
enum rpmh_state state = RPMH_SLEEP_STATE;
int ret;
bool wait;
cmd.addr = c->res_addr;
cmd_state = c->aggr_state;
on_val = c->res_on_val;
for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
if (has_state_changed(c, state)) {
if (cmd_state & BIT(state))
cmd.data = on_val;
wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE;
ret = clk_rpmh_send(c, state, &cmd, wait);
if (ret) {
dev_err(c->dev, "set %s state of %s failed: (%d)\n",
!state ? "sleep" :
state == RPMH_WAKE_ONLY_STATE ?
"wake" : "active", c->res_name, ret);
return ret;
}
}
}
c->last_sent_aggr_state = c->aggr_state;
c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
return 0;
}
/*
* Update state and aggregate state values based on enable value.
*/
static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
bool enable)
{
int ret;
c->state = enable ? c->valid_state_mask : 0;
c->aggr_state = c->state | c->peer->state;
c->peer->aggr_state = c->aggr_state;
ret = clk_rpmh_send_aggregate_command(c);
if (!ret)
return 0;
if (ret && enable)
c->state = 0;
else if (ret)
c->state = c->valid_state_mask;
WARN(1, "clk: %s failed to %s\n", c->res_name,
enable ? "enable" : "disable");
return ret;
}
static int clk_rpmh_prepare(struct clk_hw *hw)
{
struct clk_rpmh *c = to_clk_rpmh(hw);
int ret = 0;
mutex_lock(&rpmh_clk_lock);
ret = clk_rpmh_aggregate_state_send_command(c, true);
mutex_unlock(&rpmh_clk_lock);
return ret;
}
static void clk_rpmh_unprepare(struct clk_hw *hw)
{
struct clk_rpmh *c = to_clk_rpmh(hw);
mutex_lock(&rpmh_clk_lock);
clk_rpmh_aggregate_state_send_command(c, false);
mutex_unlock(&rpmh_clk_lock);
};
static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct clk_rpmh *r = to_clk_rpmh(hw);
/*
* RPMh clocks have a fixed rate. Return static rate.
*/
return prate / r->div;
}
static const struct clk_ops clk_rpmh_ops = {
.prepare = clk_rpmh_prepare,
.unprepare = clk_rpmh_unprepare,
.recalc_rate = clk_rpmh_recalc_rate,
};
static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
{
struct tcs_cmd cmd = { 0 };
u32 cmd_state;
int ret = 0;
mutex_lock(&rpmh_clk_lock);
if (enable) {
cmd_state = 1;
if (c->aggr_state)
cmd_state = c->aggr_state;
} else {
cmd_state = 0;
}
if (c->last_sent_aggr_state != cmd_state) {
cmd.addr = c->res_addr;
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
/*
* Send only an active only state request. RPMh continues to
* use the active state when we're in sleep/wake state as long
* as the sleep/wake state has never been set.
*/
ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
if (ret) {
dev_err(c->dev, "set active state of %s failed: (%d)\n",
c->res_name, ret);
} else {
c->last_sent_aggr_state = cmd_state;
}
}
mutex_unlock(&rpmh_clk_lock);
return ret;
}
static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
{
struct clk_rpmh *c = to_clk_rpmh(hw);
return clk_rpmh_bcm_send_cmd(c, true);
}
static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
{
struct clk_rpmh *c = to_clk_rpmh(hw);
clk_rpmh_bcm_send_cmd(c, false);
}
static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rpmh *c = to_clk_rpmh(hw);
c->aggr_state = rate / c->unit;
/*
* Since any non-zero value sent to hw would result in enabling the
* clock, only send the value if the clock has already been prepared.
*/
if (clk_hw_is_prepared(hw))
clk_rpmh_bcm_send_cmd(c, true);
return 0;
}
static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
return rate;
}
static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct clk_rpmh *c = to_clk_rpmh(hw);
return c->aggr_state * c->unit;
}
static const struct clk_ops clk_rpmh_bcm_ops = {
.prepare = clk_rpmh_bcm_prepare,
.unprepare = clk_rpmh_bcm_unprepare,
.set_rate = clk_rpmh_bcm_set_rate,
.round_rate = clk_rpmh_round_rate,
.recalc_rate = clk_rpmh_bcm_recalc_rate,
};
/* Resource name must match resource id present in cmd-db */
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1);
DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1);
DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);
DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);
DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
DEFINE_CLK_RPMH_BCM(ipa, "IP0");
DEFINE_CLK_RPMH_BCM(pka, "PKA0");
DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
.clks = sdm845_rpmh_clocks,
.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
};
static struct clk_hw *sa8775p_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sa8775p = {
.clks = sa8775p_rpmh_clocks,
.num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks),
};
static struct clk_hw *sdm670_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
.clks = sdm670_rpmh_clocks,
.num_clks = ARRAY_SIZE(sdm670_rpmh_clocks),
};
static struct clk_hw *sdx55_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
.clks = sdx55_rpmh_clocks,
.num_clks = ARRAY_SIZE(sdx55_rpmh_clocks),
};
static struct clk_hw *sm8150_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
.clks = sm8150_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
};
static struct clk_hw *sc7180_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
.clks = sc7180_rpmh_clocks,
.num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
};
static struct clk_hw *sc8180x_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
.clks = sc8180x_rpmh_clocks,
.num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks),
};
static struct clk_hw *sm8250_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
.clks = sm8250_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
};
static struct clk_hw *sm8350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw,
[RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
.clks = sm8350_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
};
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
.clks = sc8280xp_rpmh_clocks,
.num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks),
};
static struct clk_hw *sm8450_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
.clks = sm8450_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
};
static struct clk_hw *sm8550_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
.clks = sm8550_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
.clks = sc7280_rpmh_clocks,
.num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
};
static struct clk_hw *sm6350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw,
[RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw,
[RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
.clks = sm6350_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
};
static struct clk_hw *sdx65_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
.clks = sdx65_rpmh_clocks,
.num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
};
static struct clk_hw *qdu1000_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
.clks = qdu1000_rpmh_clocks,
.num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks),
};
static struct clk_hw *sdx75_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx75 = {
.clks = sdx75_rpmh_clocks,
.num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct clk_rpmh_desc *rpmh = data;
unsigned int idx = clkspec->args[0];
if (idx >= rpmh->num_clks) {
pr_err("%s: invalid index %u\n", __func__, idx);
return ERR_PTR(-EINVAL);
}
return rpmh->clks[idx];
}
static int clk_rpmh_probe(struct platform_device *pdev)
{
struct clk_hw **hw_clks;
struct clk_rpmh *rpmh_clk;
const struct clk_rpmh_desc *desc;
int ret, i;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -ENODEV;
hw_clks = desc->clks;
for (i = 0; i < desc->num_clks; i++) {
const char *name;
u32 res_addr;
size_t aux_data_len;
const struct bcm_db *data;
if (!hw_clks[i])
continue;
name = hw_clks[i]->init->name;
rpmh_clk = to_clk_rpmh(hw_clks[i]);
res_addr = cmd_db_read_addr(rpmh_clk->res_name);
if (!res_addr) {
dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
rpmh_clk->res_name);
return -ENODEV;
}
data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
if (IS_ERR(data)) {
ret = PTR_ERR(data);
dev_err(&pdev->dev,
"error reading RPMh aux data for %s (%d)\n",
rpmh_clk->res_name, ret);
return ret;
}
/* Convert unit from Khz to Hz */
if (aux_data_len == sizeof(*data))
rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
rpmh_clk->res_addr += res_addr;
rpmh_clk->dev = &pdev->dev;
ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
if (ret) {
dev_err(&pdev->dev, "failed to register %s\n", name);
return ret;
}
}
/* typecast to silence compiler warning */
ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
(void *)desc);
if (ret) {
dev_err(&pdev->dev, "Failed to add clock provider\n");
return ret;
}
dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
return 0;
}
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
{ .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p},
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
{ .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
{ .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670},
{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
{ .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65},
{ .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75},
{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
{ .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
{ }
};
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
static struct platform_driver clk_rpmh_driver = {
.probe = clk_rpmh_probe,
.driver = {
.name = "clk-rpmh",
.of_match_table = clk_rpmh_match_table,
},
};
static int __init clk_rpmh_init(void)
{
return platform_driver_register(&clk_rpmh_driver);
}
core_initcall(clk_rpmh_init);
static void __exit clk_rpmh_exit(void)
{
platform_driver_unregister(&clk_rpmh_driver);
}
module_exit(clk_rpmh_exit);
MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/clk-rpmh.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,dispcc-sm6350.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_EVEN,
P_DISP_CC_PLL0_OUT_MAIN,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GCC_DISP_GPLL0_CLK,
};
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x3a,
.alpha = 0x5555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000002,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_phy_pll_link_clk" },
{ .fw_name = "dp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk" },
{ .hw = &disp_cc_pll0.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_clk" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
};
static const struct parent_map disp_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x115c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x10c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_byte2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x10dc,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_regmap_div_ro_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.cmd_rcgr = 0x1144,
.mnd_width = 0,
.hid_width = 5,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.cmd_rcgr = 0x1114,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x10f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.cmd_rcgr = 0x112c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x10e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x107c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x1064,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x1094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x10ac,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
.reg = 0x1110,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x104c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x102c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x1030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.halt_reg = 0x1048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
.halt_reg = 0x1040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_clk = {
.halt_reg = 0x1038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x103c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x103c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.halt_reg = 0x1044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x1034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x1010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x1020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x100c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x1018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x1028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0x5004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_xo_clk = {
.halt_reg = 0x5008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x1004,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm6350_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
&disp_cc_mdss_dp_link_div_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
};
static struct gdsc *disp_cc_sm6350_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static const struct regmap_config disp_cc_sm6350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm6350_desc = {
.config = &disp_cc_sm6350_regmap_config,
.clks = disp_cc_sm6350_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6350_clocks),
.gdscs = disp_cc_sm6350_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6350_gdscs),
};
static const struct of_device_id disp_cc_sm6350_match_table[] = {
{ .compatible = "qcom,sm6350-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm6350_match_table);
static int disp_cc_sm6350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &disp_cc_sm6350_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap);
}
static struct platform_driver disp_cc_sm6350_driver = {
.probe = disp_cc_sm6350_probe,
.driver = {
.name = "disp_cc-sm6350",
.of_match_table = disp_cc_sm6350_match_table,
},
};
static int __init disp_cc_sm6350_init(void)
{
return platform_driver_register(&disp_cc_sm6350_driver);
}
subsys_initcall(disp_cc_sm6350_init);
static void __exit disp_cc_sm6350_exit(void)
{
platform_driver_unregister(&disp_cc_sm6350_driver);
}
module_exit(disp_cc_sm6350_exit);
MODULE_DESCRIPTION("QTI DISP_CC SM6350 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/dispcc-sm6350.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, AngeloGioacchino Del Regno
* <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gpucc-sdm660.h>
#include "clk-alpha-pll.h"
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_GPU_XO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_PLL0_PLL_OUT_MAIN,
P_GPU_PLL1_PLL_OUT_MAIN,
};
static struct clk_branch gpucc_cxo_clk = {
.halt_reg = 0x1020,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct pll_vco gpu_vco[] = {
{ 1000000000, 2000000000, 0 },
{ 500000000, 1000000000, 2 },
{ 250000000, 500000000, 3 },
};
static struct clk_alpha_pll gpu_pll0_pll_out_main = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpu_vco,
.num_vco = ARRAY_SIZE(gpu_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_pll0_pll_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpucc_cxo_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll gpu_pll1_pll_out_main = {
.offset = 0x40,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpu_vco,
.num_vco = ARRAY_SIZE(gpu_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_pll1_pll_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpucc_cxo_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static const struct parent_map gpucc_parent_map_1[] = {
{ P_GPU_XO, 0 },
{ P_GPU_PLL0_PLL_OUT_MAIN, 1 },
{ P_GPU_PLL1_PLL_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpucc_parent_data_1[] = {
{ .hw = &gpucc_cxo_clk.clkr.hw },
{ .hw = &gpu_pll0_pll_out_main.clkr.hw },
{ .hw = &gpu_pll1_pll_out_main.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk" },
};
static struct clk_rcg2_gfx3d gfx3d_clk_src = {
.div = 2,
.rcg = {
.cmd_rcgr = 0x1070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = gpucc_parent_data_1,
.num_parents = ARRAY_SIZE(gpucc_parent_data_1),
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
},
},
.hws = (struct clk_hw*[]){
&gpucc_cxo_clk.clkr.hw,
&gpu_pll0_pll_out_main.clkr.hw,
&gpu_pll1_pll_out_main.clkr.hw,
}
};
static struct clk_branch gpucc_gfx3d_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1098,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.rcg.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct parent_map gpucc_parent_map_0[] = {
{ P_GPU_XO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpucc_parent_data_0[] = {
{ .hw = &gpucc_cxo_clk.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk" },
{ .fw_name = "gcc_gpu_gpll0_div_clk" },
};
static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
F(19200000, P_GPU_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 rbbmtimer_clk_src = {
.cmd_rcgr = 0x10b0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_0,
.freq_tbl = ftbl_rbbmtimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_data = gpucc_parent_data_0,
.num_parents = ARRAY_SIZE(gpucc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
F(19200000, P_GPU_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_clk_src = {
.cmd_rcgr = 0x1030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_0,
.freq_tbl = ftbl_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
.parent_data = gpucc_parent_data_0,
.num_parents = ARRAY_SIZE(gpucc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpucc_rbbmtimer_clk = {
.halt_reg = 0x10d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_rbbmtimer_clk",
.parent_hws = (const struct clk_hw*[]){
&rbbmtimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_rbcpr_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x1004,
.gds_hw_ctrl = 0x1008,
.pd = {
.name = "gpu_cx",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x1094,
.clamp_io_ctrl = 0x130,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.cxcs = (unsigned int []){ 0x1098 },
.cxc_count = 1,
.pd = {
.name = "gpu_gx",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET,
.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
};
static struct gdsc *gpucc_sdm660_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct qcom_reset_map gpucc_sdm660_resets[] = {
[GPU_CX_BCR] = { 0x1000 },
[RBCPR_BCR] = { 0x1050 },
[GPU_GX_BCR] = { 0x1090 },
[SPDM_BCR] = { 0x10E0 },
};
static struct clk_regmap *gpucc_sdm660_clocks[] = {
[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr,
[GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr,
[GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr,
};
static const struct regmap_config gpucc_660_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9034,
.fast_io = true,
};
static const struct qcom_cc_desc gpucc_sdm660_desc = {
.config = &gpucc_660_regmap_config,
.clks = gpucc_sdm660_clocks,
.num_clks = ARRAY_SIZE(gpucc_sdm660_clocks),
.resets = gpucc_sdm660_resets,
.num_resets = ARRAY_SIZE(gpucc_sdm660_resets),
.gdscs = gpucc_sdm660_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs),
};
static const struct of_device_id gpucc_sdm660_match_table[] = {
{ .compatible = "qcom,gpucc-sdm660" },
{ .compatible = "qcom,gpucc-sdm630" },
{ }
};
MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table);
static int gpucc_sdm660_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config gpu_pll_config = {
.config_ctl_val = 0x4001055b,
.alpha = 0xaaaaab00,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = 0x1,
};
regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* 800MHz configuration for GPU PLL0 */
gpu_pll_config.l = 0x29;
gpu_pll_config.alpha_hi = 0xaa;
clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config);
/* 740MHz configuration for GPU PLL1 */
gpu_pll_config.l = 0x26;
gpu_pll_config.alpha_hi = 0x8a;
clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap);
}
static struct platform_driver gpucc_sdm660_driver = {
.probe = gpucc_sdm660_probe,
.driver = {
.name = "gpucc-sdm660",
.of_match_table = gpucc_sdm660_match_table,
},
};
module_platform_driver(gpucc_sdm660_driver);
MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sdm660.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD,
P_SLEEP_CLK,
};
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = {
.l = 0x20,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000000,
.user_ctl_val = 0x00005105,
.user_ctl_hi_val = 0x00004805,
};
static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_CAL_L_VAL] = 0x8,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_USER_CTL_U] = 0x10,
[PLL_OFF_USER_CTL_U1] = 0x14,
[PLL_OFF_CONFIG_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL_U] = 0x1C,
[PLL_OFF_CONFIG_CTL_U1] = 0x20,
[PLL_OFF_TEST_CTL] = 0x24,
[PLL_OFF_TEST_CTL_U] = 0x28,
[PLL_OFF_STATUS] = 0x30,
[PLL_OFF_OPMODE] = 0x38,
[PLL_OFF_FRAC] = 0x40,
},
};
static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
.offset = 0x1000,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "lpass_lpaaudio_dig_pll",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct clk_div_table
post_div_table_lpass_lpaaudio_dig_pll_out_odd[] = {
{ 0x5, 5 },
{ }
};
static struct clk_alpha_pll_postdiv lpass_lpaaudio_dig_pll_out_odd = {
.offset = 0x1000,
.post_div_shift = 12,
.post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
.num_post_div =
ARRAY_SIZE(post_div_table_lpass_lpaaudio_dig_pll_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "lpass_lpaaudio_dig_pll_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&lpass_lpaaudio_dig_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct parent_map lpass_core_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5 },
};
static const struct clk_parent_data lpass_core_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &lpass_lpaaudio_dig_pll_out_odd.clkr.hw },
};
static const struct parent_map lpass_core_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};
static struct clk_rcg2 core_clk_src = {
.cmd_rcgr = 0x1d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.name = "core_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ext_mclk0_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_ext_lpaif_clk_src[] = {
F(256000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 32),
F(512000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 16),
F(768000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 16),
F(1024000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 8),
F(1536000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 8),
F(2048000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 4),
F(3072000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 4),
F(4096000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 2),
F(6144000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 2),
F(8192000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(12288000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24576000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5, 0, 0),
{ }
};
static struct clk_rcg2 ext_mclk0_clk_src = {
.cmd_rcgr = 0x20000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_ext_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ext_mclk0_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpaif_pri_clk_src = {
.cmd_rcgr = 0x10000,
.mnd_width = 16,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_ext_lpaif_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "lpaif_pri_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpaif_sec_clk_src = {
.cmd_rcgr = 0x11000,
.mnd_width = 16,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_ext_lpaif_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "lpaif_sec_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch lpass_audio_core_ext_mclk0_clk = {
.halt_reg = 0x20014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x20014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_audio_core_ext_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&ext_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_core_lpaif_pri_ibit_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x10018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_audio_core_lpaif_pri_ibit_clk",
.parent_hws = (const struct clk_hw*[]) {
&lpaif_pri_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_core_lpaif_sec_ibit_clk = {
.halt_reg = 0x11018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x11018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x11018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_audio_core_lpaif_sec_ibit_clk",
.parent_hws = (const struct clk_hw*[]) {
&lpaif_sec_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_core_sysnoc_mport_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x23000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x23000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_audio_core_sysnoc_mport_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = {
[EXT_MCLK0_CLK_SRC] = &ext_mclk0_clk_src.clkr,
[LPAIF_PRI_CLK_SRC] = &lpaif_pri_clk_src.clkr,
[LPAIF_SEC_CLK_SRC] = &lpaif_sec_clk_src.clkr,
[CORE_CLK_SRC] = &core_clk_src.clkr,
[LPASS_AUDIO_CORE_EXT_MCLK0_CLK] = &lpass_audio_core_ext_mclk0_clk.clkr,
[LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK] =
&lpass_audio_core_lpaif_pri_ibit_clk.clkr,
[LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK] =
&lpass_audio_core_lpaif_sec_ibit_clk.clkr,
[LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK] =
&lpass_audio_core_sysnoc_mport_core_clk.clkr,
[LPASS_LPAAUDIO_DIG_PLL] = &lpass_lpaaudio_dig_pll.clkr,
[LPASS_LPAAUDIO_DIG_PLL_OUT_ODD] = &lpass_lpaaudio_dig_pll_out_odd.clkr,
};
static struct gdsc lpass_pdc_hm_gdsc = {
.gdscr = 0x3090,
.pd = {
.name = "lpass_pdc_hm_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc lpass_audio_hm_gdsc = {
.gdscr = 0x9090,
.pd = {
.name = "lpass_audio_hm_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc lpass_core_hm_gdsc = {
.gdscr = 0x0,
.pd = {
.name = "lpass_core_hm_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc *lpass_core_hm_sc7180_gdscs[] = {
[LPASS_CORE_HM_GDSCR] = &lpass_core_hm_gdsc,
};
static struct gdsc *lpass_audio_hm_sc7180_gdscs[] = {
[LPASS_PDC_HM_GDSCR] = &lpass_pdc_hm_gdsc,
[LPASS_AUDIO_HM_GDSCR] = &lpass_audio_hm_gdsc,
};
static struct regmap_config lpass_core_cc_sc7180_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static const struct qcom_cc_desc lpass_core_hm_sc7180_desc = {
.config = &lpass_core_cc_sc7180_regmap_config,
.gdscs = lpass_core_hm_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7180_gdscs),
};
static const struct qcom_cc_desc lpass_core_cc_sc7180_desc = {
.config = &lpass_core_cc_sc7180_regmap_config,
.clks = lpass_core_cc_sc7180_clocks,
.num_clks = ARRAY_SIZE(lpass_core_cc_sc7180_clocks),
};
static const struct qcom_cc_desc lpass_audio_hm_sc7180_desc = {
.config = &lpass_core_cc_sc7180_regmap_config,
.gdscs = lpass_audio_hm_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(lpass_audio_hm_sc7180_gdscs),
};
static int lpass_setup_runtime_pm(struct platform_device *pdev)
{
int ret;
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, "iface");
if (ret < 0)
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return pm_runtime_resume_and_get(&pdev->dev);
}
static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
struct regmap *regmap;
int ret;
ret = lpass_setup_runtime_pm(pdev);
if (ret)
return ret;
lpass_core_cc_sc7180_regmap_config.name = "lpass_audio_cc";
desc = &lpass_audio_hm_sc7180_desc;
ret = qcom_cc_probe_by_index(pdev, 1, desc);
if (ret)
goto exit;
lpass_core_cc_sc7180_regmap_config.name = "lpass_core_cc";
regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto exit;
}
/*
* Keep the CLK always-ON
* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK
*/
regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0));
/* PLL settings */
regmap_write(regmap, 0x1008, 0x20);
regmap_update_bits(regmap, 0x1014, BIT(0), BIT(0));
clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap,
&lpass_lpaaudio_dig_pll_config);
ret = qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
pm_runtime_mark_last_busy(&pdev->dev);
exit:
pm_runtime_put_autosuspend(&pdev->dev);
return ret;
}
static int lpass_hm_core_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
int ret;
ret = lpass_setup_runtime_pm(pdev);
if (ret)
return ret;
lpass_core_cc_sc7180_regmap_config.name = "lpass_hm_core";
desc = &lpass_core_hm_sc7180_desc;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
return ret;
}
static const struct of_device_id lpass_hm_sc7180_match_table[] = {
{
.compatible = "qcom,sc7180-lpasshm",
},
{ }
};
MODULE_DEVICE_TABLE(of, lpass_hm_sc7180_match_table);
static const struct of_device_id lpass_core_cc_sc7180_match_table[] = {
{
.compatible = "qcom,sc7180-lpasscorecc",
},
{ }
};
MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7180_match_table);
static const struct dev_pm_ops lpass_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver lpass_core_cc_sc7180_driver = {
.probe = lpass_core_cc_sc7180_probe,
.driver = {
.name = "lpass_core_cc-sc7180",
.of_match_table = lpass_core_cc_sc7180_match_table,
.pm = &lpass_pm_ops,
},
};
static struct platform_driver lpass_hm_sc7180_driver = {
.probe = lpass_hm_core_probe,
.driver = {
.name = "lpass_hm-sc7180",
.of_match_table = lpass_hm_sc7180_match_table,
.pm = &lpass_pm_ops,
},
};
static int __init lpass_sc7180_init(void)
{
int ret;
ret = platform_driver_register(&lpass_core_cc_sc7180_driver);
if (ret)
return ret;
ret = platform_driver_register(&lpass_hm_sc7180_driver);
if (ret) {
platform_driver_unregister(&lpass_core_cc_sc7180_driver);
return ret;
}
return 0;
}
subsys_initcall(lpass_sc7180_init);
static void __exit lpass_sc7180_exit(void)
{
platform_driver_unregister(&lpass_hm_sc7180_driver);
platform_driver_unregister(&lpass_core_cc_sc7180_driver);
}
module_exit(lpass_sc7180_exit);
MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/lpasscorecc-sc7180.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/reset/qcom,gcc-msm8660.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
static struct clk_pll pll8 = {
.l_reg = 0x3144,
.m_reg = 0x3148,
.n_reg = 0x314c,
.config_reg = 0x3154,
.mode_reg = 0x3140,
.status_reg = 0x3158,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll8_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
.parent_hws = (const struct clk_hw*[]){
&pll8.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
enum {
P_PXO,
P_PLL8,
P_CXO,
};
static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 }
};
static const struct clk_parent_data gcc_pxo_pll8[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_CXO, 5 }
};
static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
{ .fw_name = "cxo", .name = "cxo_board" },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
{ 14745600, P_PLL8, 2, 48, 625 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 32000000, P_PLL8, 4, 1, 3 },
{ 40000000, P_PLL8, 1, 5, 48 },
{ 46400000, P_PLL8, 1, 29, 240 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ 56000000, P_PLL8, 1, 7, 48 },
{ 58982400, P_PLL8, 1, 96, 625 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ }
};
static struct clk_rcg gsbi1_uart_src = {
.ns_reg = 0x29d4,
.md_reg = 0x29d0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_uart_src = {
.ns_reg = 0x29f4,
.md_reg = 0x29f0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi3_uart_src = {
.ns_reg = 0x2a14,
.md_reg = 0x2a10,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a14,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi3_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x2a14,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi3_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_uart_src = {
.ns_reg = 0x2a34,
.md_reg = 0x2a30,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_uart_src = {
.ns_reg = 0x2a54,
.md_reg = 0x2a50,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi6_uart_src = {
.ns_reg = 0x2a74,
.md_reg = 0x2a70,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a74,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi6_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2a74,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi7_uart_src = {
.ns_reg = 0x2a94,
.md_reg = 0x2a90,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a94,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi7_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2a94,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi8_uart_src = {
.ns_reg = 0x2ab4,
.md_reg = 0x2ab0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2ab4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi8_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x2ab4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi8_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi9_uart_src = {
.ns_reg = 0x2ad4,
.md_reg = 0x2ad0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2ad4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi9_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x2ad4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi9_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi10_uart_src = {
.ns_reg = 0x2af4,
.md_reg = 0x2af0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2af4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi10_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x2af4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi10_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi11_uart_src = {
.ns_reg = 0x2b14,
.md_reg = 0x2b10,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2b14,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi11_uart_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x2b14,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi11_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi12_uart_src = {
.ns_reg = 0x2b34,
.md_reg = 0x2b30,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2b34,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi12_uart_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x2b34,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi12_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 1100000, P_PXO, 1, 2, 49 },
{ 5400000, P_PXO, 1, 1, 5 },
{ 10800000, P_PXO, 1, 2, 5 },
{ 15060000, P_PLL8, 1, 2, 51 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 25600000, P_PLL8, 1, 1, 15 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ }
};
static struct clk_rcg gsbi1_qup_src = {
.ns_reg = 0x29cc,
.md_reg = 0x29c8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_qup_src = {
.ns_reg = 0x29ec,
.md_reg = 0x29e8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi3_qup_src = {
.ns_reg = 0x2a0c,
.md_reg = 0x2a08,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a0c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi3_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x2a0c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi3_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_qup_src = {
.ns_reg = 0x2a2c,
.md_reg = 0x2a28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_qup_src = {
.ns_reg = 0x2a4c,
.md_reg = 0x2a48,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi6_qup_src = {
.ns_reg = 0x2a6c,
.md_reg = 0x2a68,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a6c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi6_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x2a6c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi7_qup_src = {
.ns_reg = 0x2a8c,
.md_reg = 0x2a88,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a8c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi7_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2a8c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi8_qup_src = {
.ns_reg = 0x2aac,
.md_reg = 0x2aa8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2aac,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi8_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x2aac,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi8_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi9_qup_src = {
.ns_reg = 0x2acc,
.md_reg = 0x2ac8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2acc,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi9_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x2acc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi9_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi10_qup_src = {
.ns_reg = 0x2aec,
.md_reg = 0x2ae8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2aec,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi10_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x2aec,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi10_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi11_qup_src = {
.ns_reg = 0x2b0c,
.md_reg = 0x2b08,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2b0c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi11_qup_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2b0c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi11_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi12_qup_src = {
.ns_reg = 0x2b2c,
.md_reg = 0x2b28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2b2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi12_qup_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2b2c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi12_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_gp[] = {
{ 9600000, P_CXO, 2, 0, 0 },
{ 13500000, P_PXO, 2, 0, 0 },
{ 19200000, P_CXO, 1, 0, 0 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ 76800000, P_PLL8, 1, 1, 5 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 128000000, P_PLL8, 3, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
{ }
};
static struct clk_rcg gp0_src = {
.ns_reg = 0x2d24,
.md_reg = 0x2d00,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
}
};
static struct clk_branch gp0_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&gp0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp1_src = {
.ns_reg = 0x2d44,
.md_reg = 0x2d40,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp1_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp2_src = {
.ns_reg = 0x2d64,
.md_reg = 0x2d60,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp2_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pmem_clk = {
.hwcg_reg = 0x25a0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x25a0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pmem_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg prng_src = {
.ns_reg = 0x2e80,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.clkr.hw = {
.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch prng_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
.parent_hws = (const struct clk_hw*[]){
&prng_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_sdc[] = {
{ 144000, P_PXO, 3, 2, 125 },
{ 400000, P_PLL8, 4, 1, 240 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 17070000, P_PLL8, 1, 2, 45 },
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ }
};
static struct clk_rcg sdc1_src = {
.ns_reg = 0x282c,
.md_reg = 0x2828,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc1_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc2_src = {
.ns_reg = 0x284c,
.md_reg = 0x2848,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x284c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc2_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x284c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc2_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc3_src = {
.ns_reg = 0x286c,
.md_reg = 0x2868,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x286c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc3_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x286c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc3_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc3_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc4_src = {
.ns_reg = 0x288c,
.md_reg = 0x2888,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x288c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc4_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc4_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x288c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc4_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc4_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc5_src = {
.ns_reg = 0x28ac,
.md_reg = 0x28a8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x28ac,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc5_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc5_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x28ac,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc5_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc5_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_tsif_ref[] = {
{ 105000, P_PXO, 1, 1, 256 },
{ }
};
static struct clk_rcg tsif_ref_src = {
.ns_reg = 0x2710,
.md_reg = 0x270c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_tsif_ref,
.clkr = {
.enable_reg = 0x2710,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch tsif_ref_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2710,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb[] = {
{ 60000000, P_PLL8, 1, 5, 32 },
{ }
};
static struct clk_rcg usb_hs1_xcvr_src = {
.ns_reg = 0x290c,
.md_reg = 0x2908,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hs1_xcvr_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs1_xcvr_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_fs1_xcvr_fs_src = {
.ns_reg = 0x2968,
.md_reg = 0x2964,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_fs1_xcvr_fs_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_fs1_system_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x296c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_fs1_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_fs2_xcvr_fs_src = {
.ns_reg = 0x2988,
.md_reg = 0x2984,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2988,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_fs2_xcvr_fs_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2988,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs2_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_fs2_system_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x298c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs2_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gsbi1_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x29c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi2_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x29e0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi3_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x2a00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi4_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2a20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi5_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x2a40,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi6_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2a60,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi7_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2a80,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi8_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2aa0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi9_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2ac0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi10_h_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x2ae0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi11_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2b00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi12_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2b20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch tsif_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2700,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "tsif_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_fs1_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x2960,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_fs2_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2980,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hs1_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x2900,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc1_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2820,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc2_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x2840,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc3_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x2860,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc4_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x2880,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc4_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc5_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x28a0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc5_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ebi2_2x_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2660,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ebi2_2x_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ebi2_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2664,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ebi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_clk = {
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "adm0_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_pbus_clk = {
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "adm0_pbus_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm1_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 12,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "adm1_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm1_pbus_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 11,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "adm1_pbus_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch modem_ahb1_h_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "modem_ahb1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch modem_ahb2_h_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 7,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "modem_ahb2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb0_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb0_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb1_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_ssbi2_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "pmic_ssbi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch rpm_msg_ram_h_clk = {
.hwcg_reg = 0x27e0,
.hwcg_bit = 6,
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "rpm_msg_ram_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_regmap *gcc_msm8660_clks[] = {
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
[GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
[GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
[GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
[GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
[GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
[GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
[GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
[GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
[GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
[GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
[GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
[GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
[GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
[GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
[GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
[GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
[GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
[GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
[GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
[GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
[GP0_SRC] = &gp0_src.clkr,
[GP0_CLK] = &gp0_clk.clkr,
[GP1_SRC] = &gp1_src.clkr,
[GP1_CLK] = &gp1_clk.clkr,
[GP2_SRC] = &gp2_src.clkr,
[GP2_CLK] = &gp2_clk.clkr,
[PMEM_CLK] = &pmem_clk.clkr,
[PRNG_SRC] = &prng_src.clkr,
[PRNG_CLK] = &prng_clk.clkr,
[SDC1_SRC] = &sdc1_src.clkr,
[SDC1_CLK] = &sdc1_clk.clkr,
[SDC2_SRC] = &sdc2_src.clkr,
[SDC2_CLK] = &sdc2_clk.clkr,
[SDC3_SRC] = &sdc3_src.clkr,
[SDC3_CLK] = &sdc3_clk.clkr,
[SDC4_SRC] = &sdc4_src.clkr,
[SDC4_CLK] = &sdc4_clk.clkr,
[SDC5_SRC] = &sdc5_src.clkr,
[SDC5_CLK] = &sdc5_clk.clkr,
[TSIF_REF_SRC] = &tsif_ref_src.clkr,
[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
[USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
[USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
[USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
[USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
[USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
[GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
[GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
[GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
[GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
[GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
[TSIF_H_CLK] = &tsif_h_clk.clkr,
[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
[USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
[SDC1_H_CLK] = &sdc1_h_clk.clkr,
[SDC2_H_CLK] = &sdc2_h_clk.clkr,
[SDC3_H_CLK] = &sdc3_h_clk.clkr,
[SDC4_H_CLK] = &sdc4_h_clk.clkr,
[SDC5_H_CLK] = &sdc5_h_clk.clkr,
[EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
[EBI2_CLK] = &ebi2_clk.clkr,
[ADM0_CLK] = &adm0_clk.clkr,
[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
[ADM1_CLK] = &adm1_clk.clkr,
[ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
[MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
[MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8660_resets[] = {
[AFAB_CORE_RESET] = { 0x2080, 7 },
[SCSS_SYS_RESET] = { 0x20b4, 1 },
[SCSS_SYS_POR_RESET] = { 0x20b4 },
[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
[AFAB_SMPSS_M0_RESET] = { 0x20b8 },
[AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
[SFAB_CORE_RESET] = { 0x2120, 7 },
[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
[SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
[ADM0_C2_RESET] = { 0x220c, 4 },
[ADM0_C1_RESET] = { 0x220c, 3 },
[ADM0_C0_RESET] = { 0x220c, 2 },
[ADM0_PBUS_RESET] = { 0x220c, 1 },
[ADM0_RESET] = { 0x220c },
[SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
[SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
[SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
[MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
[ADM1_C3_RESET] = { 0x226c, 5 },
[ADM1_C2_RESET] = { 0x226c, 4 },
[ADM1_C1_RESET] = { 0x226c, 3 },
[ADM1_C0_RESET] = { 0x226c, 2 },
[ADM1_PBUS_RESET] = { 0x226c, 1 },
[ADM1_RESET] = { 0x226c },
[IMEM0_RESET] = { 0x2280, 7 },
[SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
[DFAB_CORE_RESET] = { 0x24ac, 7 },
[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
[DFAB_SWAY0_RESET] = { 0x2540, 7 },
[DFAB_SWAY1_RESET] = { 0x2544, 7 },
[DFAB_ARB0_RESET] = { 0x2560, 7 },
[DFAB_ARB1_RESET] = { 0x2564, 7 },
[PPSS_PROC_RESET] = { 0x2594, 1 },
[PPSS_RESET] = { 0x2594 },
[PMEM_RESET] = { 0x25a0, 7 },
[DMA_BAM_RESET] = { 0x25c0, 7 },
[SIC_RESET] = { 0x25e0, 7 },
[SPS_TIC_RESET] = { 0x2600, 7 },
[CFBP0_RESET] = { 0x2650, 7 },
[CFBP1_RESET] = { 0x2654, 7 },
[CFBP2_RESET] = { 0x2658, 7 },
[EBI2_RESET] = { 0x2664, 7 },
[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
[CFPB_MASTER_RESET] = { 0x26a0, 7 },
[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
[CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
[TSIF_RESET] = { 0x2700, 7 },
[CE1_RESET] = { 0x2720, 7 },
[CE2_RESET] = { 0x2740, 7 },
[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
[RPM_PROC_RESET] = { 0x27c0, 7 },
[RPM_BUS_RESET] = { 0x27c4, 7 },
[RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
[PMIC_ARB0_RESET] = { 0x2800, 7 },
[PMIC_ARB1_RESET] = { 0x2804, 7 },
[PMIC_SSBI2_RESET] = { 0x280c, 12 },
[SDC1_RESET] = { 0x2830 },
[SDC2_RESET] = { 0x2850 },
[SDC3_RESET] = { 0x2870 },
[SDC4_RESET] = { 0x2890 },
[SDC5_RESET] = { 0x28b0 },
[USB_HS1_RESET] = { 0x2910 },
[USB_HS2_XCVR_RESET] = { 0x2934, 1 },
[USB_HS2_RESET] = { 0x2934 },
[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
[USB_FS1_RESET] = { 0x2974 },
[USB_FS2_XCVR_RESET] = { 0x2994, 1 },
[USB_FS2_RESET] = { 0x2994 },
[GSBI1_RESET] = { 0x29dc },
[GSBI2_RESET] = { 0x29fc },
[GSBI3_RESET] = { 0x2a1c },
[GSBI4_RESET] = { 0x2a3c },
[GSBI5_RESET] = { 0x2a5c },
[GSBI6_RESET] = { 0x2a7c },
[GSBI7_RESET] = { 0x2a9c },
[GSBI8_RESET] = { 0x2abc },
[GSBI9_RESET] = { 0x2adc },
[GSBI10_RESET] = { 0x2afc },
[GSBI11_RESET] = { 0x2b1c },
[GSBI12_RESET] = { 0x2b3c },
[SPDM_RESET] = { 0x2b6c },
[SEC_CTRL_RESET] = { 0x2b80, 7 },
[TLMM_H_RESET] = { 0x2ba0, 7 },
[TLMM_RESET] = { 0x2ba4, 7 },
[MARRM_PWRON_RESET] = { 0x2bd4, 1 },
[MARM_RESET] = { 0x2bd4 },
[MAHB1_RESET] = { 0x2be4, 7 },
[SFAB_MSS_S_RESET] = { 0x2c00, 7 },
[MAHB2_RESET] = { 0x2c20, 7 },
[MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
[MODEM_RESET] = { 0x2c48 },
[SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
[SFAB_MSS_MDM0_RESET] = { 0x2c4c },
[MSS_SLP_RESET] = { 0x2c60, 7 },
[MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
[MSS_WDOG_RESET] = { 0x2c68 },
[TSSC_RESET] = { 0x2ca0, 7 },
[PDM_RESET] = { 0x2cc0, 12 },
[SCSS_CORE0_RESET] = { 0x2d60, 1 },
[SCSS_CORE0_POR_RESET] = { 0x2d60 },
[SCSS_CORE1_RESET] = { 0x2d80, 1 },
[SCSS_CORE1_POR_RESET] = { 0x2d80 },
[MPM_RESET] = { 0x2da4, 1 },
[EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
[EBI1_RESET] = { 0x2dec, 7 },
[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
[USB_PHY0_RESET] = { 0x2e20 },
[USB_PHY1_RESET] = { 0x2e40 },
[PRNG_RESET] = { 0x2e80, 12 },
};
static const struct regmap_config gcc_msm8660_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x363c,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8660_desc = {
.config = &gcc_msm8660_regmap_config,
.clks = gcc_msm8660_clks,
.num_clks = ARRAY_SIZE(gcc_msm8660_clks),
.resets = gcc_msm8660_resets,
.num_resets = ARRAY_SIZE(gcc_msm8660_resets),
};
static const struct of_device_id gcc_msm8660_match_table[] = {
{ .compatible = "qcom,gcc-msm8660" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
static int gcc_msm8660_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gcc_msm8660_desc);
}
static struct platform_driver gcc_msm8660_driver = {
.probe = gcc_msm8660_probe,
.driver = {
.name = "gcc-msm8660",
.of_match_table = gcc_msm8660_match_table,
},
};
static int __init gcc_msm8660_init(void)
{
return platform_driver_register(&gcc_msm8660_driver);
}
core_initcall(gcc_msm8660_init);
static void __exit gcc_msm8660_exit(void)
{
platform_driver_unregister(&gcc_msm8660_driver);
}
module_exit(gcc_msm8660_exit);
MODULE_DESCRIPTION("GCC MSM 8660 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8660");
| linux-master | drivers/clk/qcom/gcc-msm8660.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-mdm9607.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-alpha-pll.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_BIMC,
P_GPLL0,
P_GPLL1,
P_GPLL2,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data)
{
.name = "gpll0_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
.n_reg = 0x2000c,
.config_reg = 0x20010,
.mode_reg = 0x20000,
.status_reg = 0x2001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "sleep_clk" },
};
static struct clk_alpha_pll gpll2_early = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(3), /* Yeah, apparently it's not 2 */
.hw.init = &(struct clk_init_data)
{
.name = "gpll2_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll2",
.parent_hws = (const struct clk_hw *[]){ &gpll2_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
{ P_GPLL2, 3 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_apss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_pll bimc_pll = {
.l_reg = 0x23004,
.m_reg = 0x23008,
.n_reg = 0x2300c,
.config_reg = 0x23010,
.mode_reg = 0x23000,
.status_reg = 0x2301c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap bimc_pll_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
.parent_hws = (const struct clk_hw *[]){ &bimc_pll.clkr.hw },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_BIMC, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &bimc_pll_vote.hw },
};
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x200c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x3014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x4024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x5024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x6000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x6024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x7000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x7024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
F(3686400, P_GPLL0, 1, 72, 15625),
F(7372800, P_GPLL0, 1, 144, 15625),
F(14745600, P_GPLL0, 1, 288, 15625),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x2044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x3034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x4044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x5044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x6044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x6044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_crypto_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x8004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
F(155000000, P_GPLL2, 6, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 apss_tcu_clk_src = {
.cmd_rcgr = 0x1207c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_gpll2_map,
.freq_tbl = ftbl_gcc_apss_tcu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_gpll2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(57140000, P_GPLL0, 14, 0, 0),
F(69565000, P_GPLL0, 11.5, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(177778000, P_GPLL0, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_hsic_clk_src[] = {
F(480000000, P_GPLL2, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_clk_src = {
.cmd_rcgr = 0x3d018,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.freq_tbl = ftbl_usb_hsic_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_clk_src",
.parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_hsic_io_cal_clk_src[] = {
F(9600000, P_XO, 2, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
.cmd_rcgr = 0x3d030,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb_hsic_io_cal_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_io_cal_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_hsic_system_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(57140000, P_GPLL0, 14, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(177778000, P_GPLL0, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_system_clk_src = {
.cmd_rcgr = 0x3d000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb_hsic_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x1004,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2008,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x2004,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x3010,
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x300c,
.clkr = {
.enable_reg = 0x300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x4020,
.clkr = {
.enable_reg = 0x4020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x401c,
.clkr = {
.enable_reg = 0x401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x5020,
.clkr = {
.enable_reg = 0x5020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x501c,
.clkr = {
.enable_reg = 0x501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x6020,
.clkr = {
.enable_reg = 0x6020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x601c,
.clkr = {
.enable_reg = 0x601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x7020,
.clkr = {
.enable_reg = 0x7020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x701c,
.clkr = {
.enable_reg = 0x701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x203c,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x302c,
.clkr = {
.enable_reg = 0x302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x403c,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x503c,
.clkr = {
.enable_reg = 0x503c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x603c,
.clkr = {
.enable_reg = 0x603c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x703c,
.clkr = {
.enable_reg = 0x703c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]){ &crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 bimc_ddr_clk_src = {
.cmd_rcgr = 0x32004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = 3,
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
.parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qdss_dap_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
.halt_reg = 0x41030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x41008,
.clkr = {
.enable_reg = 0x41008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gcc_mdm9607_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[GPLL2] = &gpll2.clkr,
[GPLL2_EARLY] = &gpll2_early.clkr,
[BIMC_PLL] = &bimc_pll.clkr,
[BIMC_PLL_VOTE] = &bimc_pll_vote,
[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
[GCC_USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
[GCC_USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
[GCC_USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
};
static const struct qcom_reset_map gcc_mdm9607_resets[] = {
[USB_HS_HSIC_BCR] = { 0x3d05c },
[GCC_MSS_RESTART] = { 0x3e000 },
[USB_HS_BCR] = { 0x41000 },
[USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
[QUSB2_PHY_BCR] = { 0x4103c },
};
static const struct regmap_config gcc_mdm9607_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_mdm9607_desc = {
.config = &gcc_mdm9607_regmap_config,
.clks = gcc_mdm9607_clocks,
.num_clks = ARRAY_SIZE(gcc_mdm9607_clocks),
.resets = gcc_mdm9607_resets,
.num_resets = ARRAY_SIZE(gcc_mdm9607_resets),
};
static const struct of_device_id gcc_mdm9607_match_table[] = {
{ .compatible = "qcom,gcc-mdm9607" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table);
static int gcc_mdm9607_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_mdm9607_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Vote for GPLL0 to turn on. Needed by acpuclock. */
regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
}
static struct platform_driver gcc_mdm9607_driver = {
.probe = gcc_mdm9607_probe,
.driver = {
.name = "gcc-mdm9607",
.of_match_table = gcc_mdm9607_match_table,
},
};
static int __init gcc_mdm9607_init(void)
{
return platform_driver_register(&gcc_mdm9607_driver);
}
core_initcall(gcc_mdm9607_init);
static void __exit gcc_mdm9607_exit(void)
{
platform_driver_unregister(&gcc_mdm9607_driver);
}
module_exit(gcc_mdm9607_exit);
MODULE_DESCRIPTION("Qualcomm GCC mdm9607 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-mdm9607.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
};
static struct pll_vco disp_cc_pll_vco[] = {
{ 500000000, 1000000000, 2 },
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = disp_cc_pll_vco,
.num_vco = ARRAY_SIZE(disp_cc_pll_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
/* 768MHz configuration */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x28,
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_phy_pll_link_clk" },
{ .fw_name = "dp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x2154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x20bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.cmd_rcgr = 0x213c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.cmd_rcgr = 0x210c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x20f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.cmd_rcgr = 0x2124,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x20d8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x2074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x205c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x208c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x20a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
.halt_reg = 0x2038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_clk = {
.halt_reg = 0x2030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x2034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x2018,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x2018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x2010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_xo_clk = {
.halt_reg = 0x604c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x604c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct clk_regmap *disp_cc_sm6125_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
};
static struct gdsc *disp_cc_sm6125_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static const struct regmap_config disp_cc_sm6125_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm6125_desc = {
.config = &disp_cc_sm6125_regmap_config,
.clks = disp_cc_sm6125_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
.gdscs = disp_cc_sm6125_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
};
static const struct of_device_id disp_cc_sm6125_match_table[] = {
{ .compatible = "qcom,sm6125-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm6125_match_table);
static int disp_cc_sm6125_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &disp_cc_sm6125_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap);
}
static struct platform_driver disp_cc_sm6125_driver = {
.probe = disp_cc_sm6125_probe,
.driver = {
.name = "disp_cc-sm6125",
.of_match_table = disp_cc_sm6125_match_table,
},
};
static int __init disp_cc_sm6125_init(void)
{
return platform_driver_register(&disp_cc_sm6125_driver);
}
subsys_initcall(disp_cc_sm6125_init);
static void __exit disp_cc_sm6125_exit(void)
{
platform_driver_unregister(&disp_cc_sm6125_driver);
}
module_exit(disp_cc_sm6125_exit);
MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/dispcc-sm6125.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-alpha-pll.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
#define GCC_MMSS_MISC 0x0902C
#define GCC_GPU_MISC 0x71028
static struct pll_vco fabia_vco[] = {
{ 250000000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0_out_main = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0_out_odd = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0_out_test = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_test",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll1_out_even = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1_out_main = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_main",
.parent_hws = (const struct clk_hw*[]) {
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1_out_odd = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1_out_test = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1_out_test",
.parent_hws = (const struct clk_hw*[]) {
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll2 = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll2_out_even = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll2_out_main = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_main",
.parent_hws = (const struct clk_hw*[]) {
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll2_out_odd = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll2_out_test = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2_out_test",
.parent_hws = (const struct clk_hw*[]) {
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll3_out_even = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll3_out_main = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
.parent_hws = (const struct clk_hw*[]) {
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll3_out_odd = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll3_out_test = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_test",
.parent_hws = (const struct clk_hw*[]) {
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
},
};
static struct clk_alpha_pll_postdiv gpll4_out_even = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll4_out_main = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
.parent_hws = (const struct clk_hw*[]) {
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll4_out_odd = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpll4_out_test = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_test",
.parent_hws = (const struct clk_hw*[]) {
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
enum {
P_AUD_REF_CLK,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_PLL0_EARLY_DIV_CLK_SRC,
P_SLEEP_CLK,
P_XO,
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_PLL0_EARLY_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_PLL0_EARLY_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "xo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_AUD_REF_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .fw_name = "aud_ref_clk" },
};
static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x19020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x1900c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x1b020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x1b00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x1d020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x1d00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x1f020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x1f00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x21020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x2100c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x23020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x2300c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x1a00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x1c00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x26020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x28020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x2800c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x2a020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x2a00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x2c020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x2c00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x2e020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x2e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x30020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x3000c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x2700c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x2900c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.cmd_rcgr = 0x2b00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 hmss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_hmss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_ahb_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hmss_rbcpr_clk_src = {
.cmd_rcgr = 0x48044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_hmss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_rbcpr_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(1010526, P_XO, 1, 1, 19),
{ }
};
static struct clk_rcg2 pcie_aux_clk_src = {
.cmd_rcgr = 0x6c000,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_pcie_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x14010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 sdcc4_apps_clk_src = {
.cmd_rcgr = 0x16010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
F(105495, P_XO, 1, 1, 182),
{ }
};
static struct clk_rcg2 tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 ufs_axi_clk_src = {
.cmd_rcgr = 0x75018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_ufs_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 ufs_unipro_core_clk_src = {
.cmd_rcgr = 0x76028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_ufs_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0xf014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0xf028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_hmss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
F(1200000, P_XO, 16, 0, 0),
{ }
};
static struct clk_rcg2 usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x5000c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre1_noc_xo_clk = {
.halt_reg = 0x8202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre1_noc_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre1_ufs_axi_clk = {
.halt_reg = 0x82028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x82028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre1_ufs_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre1_usb3_axi_clk = {
.halt_reg = 0x82024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x82024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre1_usb3_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
.halt_reg = 0x48090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_qdss_tsctr_div2_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
.halt_reg = 0x48094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_qdss_tsctr_div8_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_hmss_axi_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_hmss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
.halt_reg = 0x4401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_mss_q6_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
.halt_reg = 0x8a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mnoc_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_div_clk",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_out_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_clk",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_out_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_gpll0_div_clk_src",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_out_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_out_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x19008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x19008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x19004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x19004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x1b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x1b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x1d008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x21008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x23008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x23004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x1a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x1c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x25004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x26004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x28004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x2a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x2a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x2c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x2c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.halt_reg = 0x2e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.halt_reg = 0x2e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.halt_reg = 0x30008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.halt_reg = 0x30004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_sleep_clk = {
.halt_reg = 0x25008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x27004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x29004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.halt_reg = 0x2b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
.halt_reg = 0x5018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x46040,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x46040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_bimc_gfx_clk = {
.halt_reg = 0x71010,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_bimc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_bimc_gfx_src_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
/*
* The GPU IOMMU depends on this clock and hypervisor
* will crash the SoC if this clock goes down, due to
* secure contexts protection.
*/
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&hmss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_at_clk = {
.halt_reg = 0x48010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_rbcpr_clk",
.parent_hws = (const struct clk_hw *[]) {
&hmss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_trig_clk = {
.halt_reg = 0x4800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_trig_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 hmss_gpll0_clk_src = {
.cmd_rcgr = 0x4805c,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_hmss_gpll0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "hmss_gpll0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_noc_cfg_ahb_clk",
.ops = &clk_branch2_ops,
/*
* Any access to mmss depends on this clock.
* Gating this clock has been shown to crash the system
* when mmssnoc_axi_rpm_clk is inited in rpmcc.
*/
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_branch gcc_mmss_qm_ahb_clk = {
.halt_reg = 0x9030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_qm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_qm_core_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_qm_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
.halt_reg = 0x9000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_sys_noc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_at_clk = {
.halt_reg = 0x8a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6b014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6b010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6b00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6b018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]) {
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw *[]) {
&tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ahb_clk = {
.halt_reg = 0x7500c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_axi_clk = {
.halt_reg = 0x75008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ice_core_clk = {
.halt_reg = 0x7600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ice_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_aux_clk = {
.halt_reg = 0x76040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x76040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_aux_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.halt_reg = 0x75014,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.halt_reg = 0x7605c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7605c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_unipro_core_clk = {
.halt_reg = 0x76008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x76008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]) {
&ufs_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0xf008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0xf00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x50000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hdmi_clkref_clk = {
.halt_reg = 0x88000,
.clkr = {
.enable_reg = 0x88000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hdmi_clkref_clk",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_clkref_clk = {
.halt_reg = 0x88004,
.clkr = {
.enable_reg = 0x88004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_clkref_clk",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_clkref_clk = {
.halt_reg = 0x88008,
.clkr = {
.enable_reg = 0x88008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_clkref_clk",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_clkref_clk = {
.halt_reg = 0x8800c,
.clkr = {
.enable_reg = 0x8800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_clkref_clk",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx1_usb2_clkref_clk = {
.halt_reg = 0x88014,
.clkr = {
.enable_reg = 0x88014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx1_usb2_clkref_clk",
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xo" },
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_im_sleep_clk = {
.halt_reg = 0x4300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_im_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch aggre2_snoc_north_axi_clk = {
.halt_reg = 0x83010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x83010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "aggre2_snoc_north_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ssc_xo_clk = {
.halt_reg = 0x63018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x63018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "ssc_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ssc_cnoc_ahbs_clk = {
.halt_reg = 0x6300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "ssc_cnoc_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc ufs_gdsc = {
.gdscr = 0x75004,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "ufs_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc usb_30_gdsc = {
.gdscr = 0xf004,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "usb_30_gdsc",
},
/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_msm8998_clocks[] = {
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
[GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
[GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
[GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
[GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
[GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
[GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
[GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
[GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
[GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
[GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
[GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
[GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
[GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
[GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
[GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
[GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
[GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
[GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
[GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
[GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
[GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
[GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
[GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
[GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
[GPLL2] = &gpll2.clkr,
[GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
[GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
[GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
[GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
[GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
[GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
[GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
[GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
[GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
[HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
[HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
[UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
[GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
[GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,
[AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
[SSC_XO] = &ssc_xo_clk.clkr,
[SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[UFS_GDSC] = &ufs_gdsc,
[USB_30_GDSC] = &usb_30_gdsc,
};
static const struct qcom_reset_map gcc_msm8998_resets[] = {
[GCC_BLSP1_QUP1_BCR] = { 0x19000 },
[GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
[GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
[GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
[GCC_BLSP1_QUP5_BCR] = { 0x21000 },
[GCC_BLSP1_QUP6_BCR] = { 0x23000 },
[GCC_BLSP2_QUP1_BCR] = { 0x26000 },
[GCC_BLSP2_QUP2_BCR] = { 0x28000 },
[GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
[GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
[GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
[GCC_BLSP2_QUP6_BCR] = { 0x30000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_UFS_BCR] = { 0x75000 },
[GCC_USB_30_BCR] = { 0xf000 },
[GCC_SYSTEM_NOC_BCR] = { 0x4000 },
[GCC_CONFIG_NOC_BCR] = { 0x5000 },
[GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
[GCC_IMEM_BCR] = { 0x8000 },
[GCC_PIMEM_BCR] = { 0xa000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_QDSS_BCR] = { 0xc000 },
[GCC_WCSS_BCR] = { 0x11000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_BLSP1_BCR] = { 0x17000 },
[GCC_BLSP1_UART1_BCR] = { 0x1a000 },
[GCC_BLSP1_UART2_BCR] = { 0x1c000 },
[GCC_BLSP1_UART3_BCR] = { 0x1e000 },
[GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
[GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
[GCC_BLSP2_BCR] = { 0x25000 },
[GCC_BLSP2_UART1_BCR] = { 0x27000 },
[GCC_BLSP2_UART2_BCR] = { 0x29000 },
[GCC_BLSP2_UART3_BCR] = { 0x2b000 },
[GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_TSIF_0_RESET] = { 0x36024 },
[GCC_TSIF_1_RESET] = { 0x36028 },
[GCC_TCSR_BCR] = { 0x37000 },
[GCC_BOOT_ROM_BCR] = { 0x38000 },
[GCC_MSG_RAM_BCR] = { 0x39000 },
[GCC_TLMM_BCR] = { 0x3a000 },
[GCC_MPM_BCR] = { 0x3b000 },
[GCC_SEC_CTRL_BCR] = { 0x3d000 },
[GCC_SPMI_BCR] = { 0x3f000 },
[GCC_SPDM_BCR] = { 0x40000 },
[GCC_CE1_BCR] = { 0x41000 },
[GCC_BIMC_BCR] = { 0x44000 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
[GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
[GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
[GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
[GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
[GCC_APB2JTAG_BCR] = { 0x4c000 },
[GCC_RBCPR_CX_BCR] = { 0x4e000 },
[GCC_RBCPR_MX_BCR] = { 0x4f000 },
[GCC_USB3_PHY_BCR] = { 0x50020 },
[GCC_USB3PHY_PHY_BCR] = { 0x50024 },
[GCC_USB3_DP_PHY_BCR] = { 0x50028 },
[GCC_SSC_BCR] = { 0x63000 },
[GCC_SSC_RESET] = { 0x63020 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_SPSS_BCR] = { 0x72000 },
[GCC_OBT_ODT_BCR] = { 0x73000 },
[GCC_MSS_RESTART] = { 0x79000 },
[GCC_VS_BCR] = { 0x7a000 },
[GCC_MSS_VS_RESET] = { 0x7a100 },
[GCC_GPU_VS_RESET] = { 0x7a104 },
[GCC_APC0_VS_RESET] = { 0x7a108 },
[GCC_APC1_VS_RESET] = { 0x7a10c },
[GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
[GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
[GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
[GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
[GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
[GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
[GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
[GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
[GCC_AGGRE1_NOC_BCR] = { 0x82000 },
[GCC_AGGRE2_NOC_BCR] = { 0x83000 },
[GCC_DCC_BCR] = { 0x84000 },
[GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
[GCC_IPA_BCR] = { 0x89000 },
[GCC_GLM_BCR] = { 0x8b000 },
[GCC_SKL_BCR] = { 0x8c000 },
[GCC_MSMPU_BCR] = { 0x8d000 },
};
static const struct regmap_config gcc_msm8998_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8f000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8998_desc = {
.config = &gcc_msm8998_regmap_config,
.clks = gcc_msm8998_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
.resets = gcc_msm8998_resets,
.num_resets = ARRAY_SIZE(gcc_msm8998_resets),
.gdscs = gcc_msm8998_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
};
static int gcc_msm8998_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
* turned off by hardware during certain apps low power modes.
*/
ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
if (ret)
return ret;
/* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
regmap_write(regmap, GCC_MMSS_MISC, 0x10003);
regmap_write(regmap, GCC_GPU_MISC, 0x10003);
return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
}
static const struct of_device_id gcc_msm8998_match_table[] = {
{ .compatible = "qcom,gcc-msm8998" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
static struct platform_driver gcc_msm8998_driver = {
.probe = gcc_msm8998_probe,
.driver = {
.name = "gcc-msm8998",
.of_match_table = gcc_msm8998_match_table,
},
};
static int __init gcc_msm8998_init(void)
{
return platform_driver_register(&gcc_msm8998_driver);
}
core_initcall(gcc_msm8998_init);
static void __exit gcc_msm8998_exit(void)
{
platform_driver_unregister(&gcc_msm8998_driver);
}
module_exit(gcc_msm8998_exit);
MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8998");
| linux-master | drivers/clk/qcom/gcc-msm8998.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_MMPLL0,
P_EDPLINK,
P_MMPLL1,
P_HDMIPLL,
P_GPLL0,
P_EDPVCO,
P_GPLL1,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_MMPLL2,
P_MMPLL3,
P_DSI1PLL,
P_DSI1PLL_BYTE,
};
static struct clk_pll mmpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
.n_reg = 0x000c,
.config_reg = 0x0014,
.mode_reg = 0x0000,
.status_reg = 0x001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap mmpll0_vote = {
.enable_reg = 0x0100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&mmpll0.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll mmpll1 = {
.l_reg = 0x0044,
.m_reg = 0x0048,
.n_reg = 0x004c,
.config_reg = 0x0050,
.mode_reg = 0x0040,
.status_reg = 0x005c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap mmpll1_vote = {
.enable_reg = 0x0100,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "mmpll1_vote",
.parent_hws = (const struct clk_hw*[]){
&mmpll1.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll mmpll2 = {
.l_reg = 0x4104,
.m_reg = 0x4108,
.n_reg = 0x410c,
.config_reg = 0x4110,
.mode_reg = 0x4100,
.status_reg = 0x411c,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_pll mmpll3 = {
.l_reg = 0x0084,
.m_reg = 0x0088,
.n_reg = 0x008c,
.config_reg = 0x0090,
.mode_reg = 0x0080,
.status_reg = 0x009c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .hw = &mmpll1_vote.hw },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
};
static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_HDMIPLL, 4 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 2 },
{ P_DSI1PLL, 3 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL3, 3 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .hw = &mmpll1_vote.hw },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
{ .hw = &mmpll3.clkr.hw },
};
static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_GPLL1, 4 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .hw = &mmpll1_vote.hw },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
{ .fw_name = "gpll1_vote", .name = "gpll1_vote" },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_EDPVCO, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 }
};
static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
};
static struct clk_rcg2 mmss_ahb_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_ahb_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(266666666, P_MMPLL0, 3, 0, 0),
{ }
};
static struct freq_tbl ftbl_mmss_axi_clk[] = {
F( 19200000, P_XO, 1, 0, 0),
F( 37500000, P_GPLL0, 16, 0, 0),
F( 50000000, P_GPLL0, 12, 0, 0),
F( 75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(291750000, P_MMPLL1, 4, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(466800000, P_MMPLL1, 2.5, 0, 0),
};
static struct clk_rcg2 mmss_axi_clk_src = {
.cmd_rcgr = 0x5040,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mmss_axi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_axi_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_ocmemnoc_clk[] = {
F( 19200000, P_XO, 1, 0, 0),
F( 37500000, P_GPLL0, 16, 0, 0),
F( 50000000, P_GPLL0, 12, 0, 0),
F( 75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(291750000, P_MMPLL1, 4, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
};
static struct clk_rcg2 ocmemnoc_clk_src = {
.cmd_rcgr = 0x5090,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_ocmemnoc_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x3090,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x3100,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3160,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi3_clk_src = {
.cmd_rcgr = 0x31c0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(80000000, P_GPLL0, 7.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(109090000, P_GPLL0, 5.5, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(80000000, P_GPLL0, 7.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(109090000, P_GPLL0, 5.5, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(465000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x3600,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x3620,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(92310000, P_GPLL0, 6.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_MMPLL0, 6, 0, 0),
F(177780000, P_MMPLL0, 4.5, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(85710000, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_MMPLL0, 6, 0, 0),
F(160000000, P_MMPLL0, 5, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x2040,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
.freq_tbl = ftbl_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x3500,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg1_clk_src = {
.cmd_rcgr = 0x3520,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg1_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg2_clk_src = {
.cmd_rcgr = 0x3540,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x2000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
F(66700000, P_GPLL0, 9, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_MMPLL0, 6, 0, 0),
F(160000000, P_MMPLL0, 5, 0, 0),
{ }
};
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_MMPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(465000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
.freq_tbl = ftbl_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x3300,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_cci_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0, 10, 1, 10),
F(12000000, P_GPLL0, 10, 1, 5),
F(13000000, P_GPLL0, 4, 13, 150),
F(24000000, P_GPLL0, 5, 1, 5),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x3420,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x3450,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = mmcc_xo_mmpll0_1_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(66670000, P_GPLL0, 9, 0, 0),
{ }
};
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(8000000, P_GPLL0, 15, 1, 5),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 12.5, 1, 3),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_MMPLL0, 5, 1, 5),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(64000000, P_MMPLL0, 12.5, 0, 0),
F(66670000, P_GPLL0, 9, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x3360,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x3390,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x33c0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x33f0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x3030,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x3060,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(465000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x3640,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_camss_vfe_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl byte_freq_tbl[] = {
{ .src = P_DSI0PLL_BYTE },
{ }
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x2120,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.freq_tbl = byte_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x2140,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.freq_tbl = byte_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 edpaux_clk_src = {
.cmd_rcgr = 0x20e0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mdss_edpaux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edpaux_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_edplink_clk[] = {
F(135000000, P_EDPLINK, 2, 0, 0),
F(270000000, P_EDPLINK, 11, 0, 0),
{ }
};
static struct clk_rcg2 edplink_clk_src = {
.cmd_rcgr = 0x20c0,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.freq_tbl = ftbl_mdss_edplink_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edplink_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl edp_pixel_freq_tbl[] = {
{ .src = P_EDPVCO },
{ }
};
static struct clk_rcg2 edppixel_clk_src = {
.cmd_rcgr = 0x20a0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_map,
.freq_tbl = edp_pixel_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "edppixel_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
.ops = &clk_edp_pixel_ops,
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x2160,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x2180,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
static struct clk_rcg2 extpclk_clk_src = {
.cmd_rcgr = 0x2060,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.freq_tbl = extpclk_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hdmi_clk_src = {
.cmd_rcgr = 0x2100,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mdss_hdmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x2080,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch camss_cci_cci_ahb_clk = {
.halt_reg = 0x3348,
.clkr = {
.enable_reg = 0x3348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_cci_clk = {
.halt_reg = 0x3344,
.clkr = {
.enable_reg = 0x3344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_ahb_clk = {
.halt_reg = 0x30bc,
.clkr = {
.enable_reg = 0x30bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_clk = {
.halt_reg = 0x30b4,
.clkr = {
.enable_reg = 0x30b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0phy_clk = {
.halt_reg = 0x30c4,
.clkr = {
.enable_reg = 0x30c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0pix_clk = {
.halt_reg = 0x30e4,
.clkr = {
.enable_reg = 0x30e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0rdi_clk = {
.halt_reg = 0x30d4,
.clkr = {
.enable_reg = 0x30d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_ahb_clk = {
.halt_reg = 0x3128,
.clkr = {
.enable_reg = 0x3128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_clk = {
.halt_reg = 0x3124,
.clkr = {
.enable_reg = 0x3124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1phy_clk = {
.halt_reg = 0x3134,
.clkr = {
.enable_reg = 0x3134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1pix_clk = {
.halt_reg = 0x3154,
.clkr = {
.enable_reg = 0x3154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1rdi_clk = {
.halt_reg = 0x3144,
.clkr = {
.enable_reg = 0x3144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_ahb_clk = {
.halt_reg = 0x3188,
.clkr = {
.enable_reg = 0x3188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_clk = {
.halt_reg = 0x3184,
.clkr = {
.enable_reg = 0x3184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2phy_clk = {
.halt_reg = 0x3194,
.clkr = {
.enable_reg = 0x3194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2pix_clk = {
.halt_reg = 0x31b4,
.clkr = {
.enable_reg = 0x31b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2rdi_clk = {
.halt_reg = 0x31a4,
.clkr = {
.enable_reg = 0x31a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_ahb_clk = {
.halt_reg = 0x31e8,
.clkr = {
.enable_reg = 0x31e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_clk = {
.halt_reg = 0x31e4,
.clkr = {
.enable_reg = 0x31e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3phy_clk = {
.halt_reg = 0x31f4,
.clkr = {
.enable_reg = 0x31f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3pix_clk = {
.halt_reg = 0x3214,
.clkr = {
.enable_reg = 0x3214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3rdi_clk = {
.halt_reg = 0x3204,
.clkr = {
.enable_reg = 0x3204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe0_clk = {
.halt_reg = 0x3704,
.clkr = {
.enable_reg = 0x3704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe1_clk = {
.halt_reg = 0x3714,
.clkr = {
.enable_reg = 0x3714,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp0_clk = {
.halt_reg = 0x3444,
.clkr = {
.enable_reg = 0x3444,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp1_clk = {
.halt_reg = 0x3474,
.clkr = {
.enable_reg = 0x3474,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ispif_ahb_clk = {
.halt_reg = 0x3224,
.clkr = {
.enable_reg = 0x3224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg0_clk = {
.halt_reg = 0x35a8,
.clkr = {
.enable_reg = 0x35a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg1_clk = {
.halt_reg = 0x35ac,
.clkr = {
.enable_reg = 0x35ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg1_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg2_clk = {
.halt_reg = 0x35b0,
.clkr = {
.enable_reg = 0x35b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg2_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
.clkr = {
.enable_reg = 0x35b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_axi_clk = {
.halt_reg = 0x35b8,
.clkr = {
.enable_reg = 0x35b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
.halt_reg = 0x35bc,
.clkr = {
.enable_reg = 0x35bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk0_clk = {
.halt_reg = 0x3384,
.clkr = {
.enable_reg = 0x3384,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk1_clk = {
.halt_reg = 0x33b4,
.clkr = {
.enable_reg = 0x33b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk2_clk = {
.halt_reg = 0x33e4,
.clkr = {
.enable_reg = 0x33e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk3_clk = {
.halt_reg = 0x3414,
.clkr = {
.enable_reg = 0x3414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_micro_ahb_clk = {
.halt_reg = 0x3494,
.clkr = {
.enable_reg = 0x3494,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy0_csi0phytimer_clk = {
.halt_reg = 0x3024,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy0_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy1_csi1phytimer_clk = {
.halt_reg = 0x3054,
.clkr = {
.enable_reg = 0x3054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy1_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy2_csi2phytimer_clk = {
.halt_reg = 0x3084,
.clkr = {
.enable_reg = 0x3084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy2_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_top_ahb_clk = {
.halt_reg = 0x3484,
.clkr = {
.enable_reg = 0x3484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_ahb_clk = {
.halt_reg = 0x36b4,
.clkr = {
.enable_reg = 0x36b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_clk = {
.halt_reg = 0x36b0,
.clkr = {
.enable_reg = 0x36b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe0_clk = {
.halt_reg = 0x36a8,
.clkr = {
.enable_reg = 0x36a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe1_clk = {
.halt_reg = 0x36ac,
.clkr = {
.enable_reg = 0x36ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_ahb_clk = {
.halt_reg = 0x36b8,
.clkr = {
.enable_reg = 0x36b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_axi_clk = {
.halt_reg = 0x36bc,
.clkr = {
.enable_reg = 0x36bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
.halt_reg = 0x36c0,
.clkr = {
.enable_reg = 0x36c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_axi_clk = {
.halt_reg = 0x2310,
.clkr = {
.enable_reg = 0x2310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte0_clk = {
.halt_reg = 0x233c,
.clkr = {
.enable_reg = 0x233c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte1_clk = {
.halt_reg = 0x2340,
.clkr = {
.enable_reg = 0x2340,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&byte1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_edpaux_clk = {
.halt_reg = 0x2334,
.clkr = {
.enable_reg = 0x2334,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edpaux_clk",
.parent_hws = (const struct clk_hw*[]){
&edpaux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_edplink_clk = {
.halt_reg = 0x2330,
.clkr = {
.enable_reg = 0x2330,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edplink_clk",
.parent_hws = (const struct clk_hw*[]){
&edplink_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_edppixel_clk = {
.halt_reg = 0x232c,
.clkr = {
.enable_reg = 0x232c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edppixel_clk",
.parent_hws = (const struct clk_hw*[]){
&edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc0_clk = {
.halt_reg = 0x2344,
.clkr = {
.enable_reg = 0x2344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc1_clk = {
.halt_reg = 0x2348,
.clkr = {
.enable_reg = 0x2348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&esc1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_extpclk_clk = {
.halt_reg = 0x2324,
.clkr = {
.enable_reg = 0x2324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
.parent_hws = (const struct clk_hw*[]){
&extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_ahb_clk = {
.halt_reg = 0x230c,
.clkr = {
.enable_reg = 0x230c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_clk = {
.halt_reg = 0x2338,
.clkr = {
.enable_reg = 0x2338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
.parent_hws = (const struct clk_hw*[]){
&hdmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_clk = {
.halt_reg = 0x231c,
.clkr = {
.enable_reg = 0x231c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_lut_clk = {
.halt_reg = 0x2320,
.clkr = {
.enable_reg = 0x2320,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk0_clk = {
.halt_reg = 0x2314,
.clkr = {
.enable_reg = 0x2314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk1_clk = {
.halt_reg = 0x2318,
.clkr = {
.enable_reg = 0x2318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_vsync_clk = {
.halt_reg = 0x2328,
.clkr = {
.enable_reg = 0x2328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_misc_ahb_clk = {
.halt_reg = 0x502c,
.clkr = {
.enable_reg = 0x502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_mmssnoc_ahb_clk = {
.halt_reg = 0x5024,
.clkr = {
.enable_reg = 0x5024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
.halt_reg = 0x5028,
.clkr = {
.enable_reg = 0x5028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_bto_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch mmss_mmssnoc_axi_clk = {
.halt_reg = 0x506c,
.clkr = {
.enable_reg = 0x506c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_s0_axi_clk = {
.halt_reg = 0x5064,
.clkr = {
.enable_reg = 0x5064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_s0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch ocmemcx_ahb_clk = {
.halt_reg = 0x405c,
.clkr = {
.enable_reg = 0x405c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ocmemcx_ocmemnoc_clk = {
.halt_reg = 0x4058,
.clkr = {
.enable_reg = 0x4058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ocmemnoc_clk = {
.halt_reg = 0x50b4,
.clkr = {
.enable_reg = 0x50b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxili_gfx3d_clk = {
.halt_reg = 0x4028,
.clkr = {
.enable_reg = 0x4028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_gfx3d_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxilicx_ahb_clk = {
.halt_reg = 0x403c,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxilicx_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxilicx_axi_clk = {
.halt_reg = 0x4038,
.clkr = {
.enable_reg = 0x4038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxilicx_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_ahb_clk = {
.halt_reg = 0x1030,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_axi_clk = {
.halt_reg = 0x1034,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_ocmemnoc_clk = {
.halt_reg = 0x1038,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_vcodec0_clk = {
.halt_reg = 0x1028,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct pll_config mmpll1_config = {
.l = 60,
.m = 25,
.n = 32,
.vco_val = 0x0,
.vco_mask = 0x3 << 20,
.pre_div_val = 0x0,
.pre_div_mask = 0x7 << 12,
.post_div_val = 0x0,
.post_div_mask = 0x3 << 8,
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
};
static struct pll_config mmpll3_config = {
.l = 48,
.m = 7,
.n = 16,
.vco_val = 0x0,
.vco_mask = 0x3 << 20,
.pre_div_val = 0x0,
.pre_div_mask = 0x7 << 12,
.post_div_val = 0x0,
.post_div_mask = 0x3 << 8,
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
};
static struct gdsc venus0_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int []){ 0x1028 },
.cxc_count = 1,
.resets = (unsigned int []){ VENUS0_RESET },
.reset_count = 1,
.pd = {
.name = "venus0",
},
.pwrsts = PWRSTS_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x2304,
.cxcs = (unsigned int []){ 0x231c, 0x2320 },
.cxc_count = 2,
.pd = {
.name = "mdss",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_jpeg_gdsc = {
.gdscr = 0x35a4,
.cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
.cxc_count = 3,
.pd = {
.name = "camss_jpeg",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe_gdsc = {
.gdscr = 0x36a4,
.cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
.cxc_count = 5,
.pd = {
.name = "camss_vfe",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gdsc = {
.gdscr = 0x4024,
.cxcs = (unsigned int []){ 0x4028 },
.cxc_count = 1,
.pd = {
.name = "oxili",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxilicx_gdsc = {
.gdscr = 0x4034,
.pd = {
.name = "oxilicx",
},
.parent = &oxili_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_cx_gdsc_msm8226 = {
.gdscr = 0x4034,
.cxcs = (unsigned int []){ 0x4028 },
.cxc_count = 1,
.pd = {
.name = "oxili_cx",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *mmcc_msm8226_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
[MMPLL0] = &mmpll0.clkr,
[MMPLL0_VOTE] = &mmpll0_vote,
[MMPLL1] = &mmpll1.clkr,
[MMPLL1_VOTE] = &mmpll1_vote,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
};
static const struct qcom_reset_map mmcc_msm8226_resets[] = {
[SPDM_RESET] = { 0x0200 },
[SPDM_RM_RESET] = { 0x0300 },
[VENUS0_RESET] = { 0x1020 },
[MDSS_RESET] = { 0x2300 },
};
static struct gdsc *mmcc_msm8226_gdscs[] = {
[VENUS0_GDSC] = &venus0_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
[OXILICX_GDSC] = &oxili_cx_gdsc_msm8226,
};
static const struct regmap_config mmcc_msm8226_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5104,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_msm8226_desc = {
.config = &mmcc_msm8226_regmap_config,
.clks = mmcc_msm8226_clocks,
.num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
.resets = mmcc_msm8226_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
.gdscs = mmcc_msm8226_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
};
static struct clk_regmap *mmcc_msm8974_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
[OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
[MMPLL0] = &mmpll0.clkr,
[MMPLL0_VOTE] = &mmpll0_vote,
[MMPLL1] = &mmpll1.clkr,
[MMPLL1_VOTE] = &mmpll1_vote,
[MMPLL2] = &mmpll2.clkr,
[MMPLL3] = &mmpll3.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
[EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
[EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
[CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
[CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
[CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
[CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
[CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
[CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
[MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
[MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
[MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
[VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
};
static const struct qcom_reset_map mmcc_msm8974_resets[] = {
[SPDM_RESET] = { 0x0200 },
[SPDM_RM_RESET] = { 0x0300 },
[VENUS0_RESET] = { 0x1020 },
[MDSS_RESET] = { 0x2300 },
[CAMSS_PHY0_RESET] = { 0x3020 },
[CAMSS_PHY1_RESET] = { 0x3050 },
[CAMSS_PHY2_RESET] = { 0x3080 },
[CAMSS_CSI0_RESET] = { 0x30b0 },
[CAMSS_CSI0PHY_RESET] = { 0x30c0 },
[CAMSS_CSI0RDI_RESET] = { 0x30d0 },
[CAMSS_CSI0PIX_RESET] = { 0x30e0 },
[CAMSS_CSI1_RESET] = { 0x3120 },
[CAMSS_CSI1PHY_RESET] = { 0x3130 },
[CAMSS_CSI1RDI_RESET] = { 0x3140 },
[CAMSS_CSI1PIX_RESET] = { 0x3150 },
[CAMSS_CSI2_RESET] = { 0x3180 },
[CAMSS_CSI2PHY_RESET] = { 0x3190 },
[CAMSS_CSI2RDI_RESET] = { 0x31a0 },
[CAMSS_CSI2PIX_RESET] = { 0x31b0 },
[CAMSS_CSI3_RESET] = { 0x31e0 },
[CAMSS_CSI3PHY_RESET] = { 0x31f0 },
[CAMSS_CSI3RDI_RESET] = { 0x3200 },
[CAMSS_CSI3PIX_RESET] = { 0x3210 },
[CAMSS_ISPIF_RESET] = { 0x3220 },
[CAMSS_CCI_RESET] = { 0x3340 },
[CAMSS_MCLK0_RESET] = { 0x3380 },
[CAMSS_MCLK1_RESET] = { 0x33b0 },
[CAMSS_MCLK2_RESET] = { 0x33e0 },
[CAMSS_MCLK3_RESET] = { 0x3410 },
[CAMSS_GP0_RESET] = { 0x3440 },
[CAMSS_GP1_RESET] = { 0x3470 },
[CAMSS_TOP_RESET] = { 0x3480 },
[CAMSS_MICRO_RESET] = { 0x3490 },
[CAMSS_JPEG_RESET] = { 0x35a0 },
[CAMSS_VFE_RESET] = { 0x36a0 },
[CAMSS_CSI_VFE0_RESET] = { 0x3700 },
[CAMSS_CSI_VFE1_RESET] = { 0x3710 },
[OXILI_RESET] = { 0x4020 },
[OXILICX_RESET] = { 0x4030 },
[OCMEMCX_RESET] = { 0x4050 },
[MMSS_RBCRP_RESET] = { 0x4080 },
[MMSSNOCAHB_RESET] = { 0x5020 },
[MMSSNOCAXI_RESET] = { 0x5060 },
[OCMEMNOC_RESET] = { 0x50b0 },
};
static struct gdsc *mmcc_msm8974_gdscs[] = {
[VENUS0_GDSC] = &venus0_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
[OXILI_GDSC] = &oxili_gdsc,
[OXILICX_GDSC] = &oxilicx_gdsc,
};
static const struct regmap_config mmcc_msm8974_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5104,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_msm8974_desc = {
.config = &mmcc_msm8974_regmap_config,
.clks = mmcc_msm8974_clocks,
.num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
.resets = mmcc_msm8974_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
.gdscs = mmcc_msm8974_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
};
static const struct of_device_id mmcc_msm8974_match_table[] = {
{ .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
{ .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
static void msm8226_clock_override(void)
{
mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
}
static int mmcc_msm8974_probe(struct platform_device *pdev)
{
struct regmap *regmap;
const struct qcom_cc_desc *desc;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (desc == &mmcc_msm8974_desc) {
clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
} else {
msm8226_clock_override();
}
return qcom_cc_really_probe(pdev, desc, regmap);
}
static struct platform_driver mmcc_msm8974_driver = {
.probe = mmcc_msm8974_probe,
.driver = {
.name = "mmcc-msm8974",
.of_match_table = mmcc_msm8974_match_table,
},
};
module_platform_driver(mmcc_msm8974_driver);
MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mmcc-msm8974");
| linux-master | drivers/clk/qcom/mmcc-msm8974.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include "clk-alpha-pll.h"
#include "common.h"
#define PLL_MODE(p) ((p)->offset + 0x0)
# define PLL_OUTCTRL BIT(0)
# define PLL_BYPASSNL BIT(1)
# define PLL_RESET_N BIT(2)
# define PLL_OFFLINE_REQ BIT(7)
# define PLL_LOCK_COUNT_SHIFT 8
# define PLL_LOCK_COUNT_MASK 0x3f
# define PLL_BIAS_COUNT_SHIFT 14
# define PLL_BIAS_COUNT_MASK 0x3f
# define PLL_VOTE_FSM_ENA BIT(20)
# define PLL_FSM_ENA BIT(20)
# define PLL_VOTE_FSM_RESET BIT(21)
# define PLL_UPDATE BIT(22)
# define PLL_UPDATE_BYPASS BIT(23)
# define PLL_FSM_LEGACY_MODE BIT(24)
# define PLL_OFFLINE_ACK BIT(28)
# define ALPHA_PLL_ACK_LATCH BIT(29)
# define PLL_ACTIVE_FLAG BIT(30)
# define PLL_LOCK_DET BIT(31)
#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
# define PLL_POST_DIV_SHIFT 8
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
# define PLL_ALPHA_EN BIT(24)
# define PLL_ALPHA_MODE BIT(25)
# define PLL_VCO_SHIFT 20
# define PLL_VCO_MASK 0x3
#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_USER_CTL] = 0x10,
[PLL_OFF_USER_CTL_U] = 0x14,
[PLL_OFF_CONFIG_CTL] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x14,
[PLL_OFF_CONFIG_CTL_U] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_USER_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_FABIA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_USER_CTL_U] = 0x10,
[PLL_OFF_CONFIG_CTL] = 0x14,
[PLL_OFF_CONFIG_CTL_U] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_STATUS] = 0x24,
[PLL_OFF_OPMODE] = 0x2c,
[PLL_OFF_FRAC] = 0x38,
},
[CLK_ALPHA_PLL_TYPE_TRION] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_CAL_L_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_USER_CTL_U] = 0x10,
[PLL_OFF_USER_CTL_U1] = 0x14,
[PLL_OFF_CONFIG_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL_U1] = 0x20,
[PLL_OFF_TEST_CTL] = 0x24,
[PLL_OFF_TEST_CTL_U] = 0x28,
[PLL_OFF_TEST_CTL_U1] = 0x2c,
[PLL_OFF_STATUS] = 0x30,
[PLL_OFF_OPMODE] = 0x38,
[PLL_OFF_ALPHA_VAL] = 0x40,
},
[CLK_ALPHA_PLL_TYPE_AGERA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_CONFIG_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL_U] = 0x14,
[PLL_OFF_TEST_CTL] = 0x18,
[PLL_OFF_TEST_CTL_U] = 0x1c,
[PLL_OFF_STATUS] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_CONFIG_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL_U] = 0x14,
[PLL_OFF_CONFIG_CTL_U1] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_TEST_CTL_U1] = 0x24,
[PLL_OFF_OPMODE] = 0x28,
[PLL_OFF_STATUS] = 0x38,
},
[CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
[PLL_OFF_TEST_CTL] = 0x2c,
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATE] = 0x08,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
[PLL_OFF_TEST_CTL] = 0x2c,
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U2] = 0x38,
},
[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x14,
[PLL_OFF_USER_CTL_U] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1c,
[PLL_OFF_CONFIG_CTL_U] = 0x20,
[PLL_OFF_CONFIG_CTL_U1] = 0x24,
[PLL_OFF_TEST_CTL] = 0x28,
[PLL_OFF_TEST_CTL_U] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x24,
},
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
[PLL_OFF_TEST_CTL] = 0x10,
[PLL_OFF_TEST_CTL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1C,
[PLL_OFF_STATUS] = 0x20,
},
[CLK_ALPHA_PLL_TYPE_STROMER] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0xff,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_USER_CTL] = 0x08,
[PLL_OFF_USER_CTL_U] = 0x0c,
[PLL_OFF_CONFIG_CTL] = 0x10,
[PLL_OFF_TEST_CTL] = 0x14,
[PLL_OFF_TEST_CTL_U] = 0x18,
[PLL_OFF_STATUS] = 0x1c,
[PLL_OFF_ALPHA_VAL] = 0x24,
[PLL_OFF_ALPHA_VAL_U] = 0x28,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
/*
* Even though 40 bits are present, use only 32 for ease of calculation.
*/
#define ALPHA_REG_BITWIDTH 40
#define ALPHA_REG_16BIT_WIDTH 16
#define ALPHA_BITWIDTH 32U
#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
#define ALPHA_PLL_STATUS_REG_SHIFT 8
#define PLL_HUAYRA_M_WIDTH 8
#define PLL_HUAYRA_M_SHIFT 8
#define PLL_HUAYRA_M_MASK 0xff
#define PLL_HUAYRA_N_SHIFT 0
#define PLL_HUAYRA_N_MASK 0xff
#define PLL_HUAYRA_ALPHA_WIDTH 16
#define PLL_STANDBY 0x0
#define PLL_RUN 0x1
#define PLL_OUT_MASK 0x7
#define PLL_RATE_MARGIN 500
/* TRION PLL specific settings and offsets */
#define TRION_PLL_CAL_VAL 0x44
#define TRION_PCAL_DONE BIT(26)
/* LUCID PLL specific settings and offsets */
#define LUCID_PCAL_DONE BIT(27)
/* LUCID 5LPE PLL specific settings and offsets */
#define LUCID_5LPE_PCAL_DONE BIT(11)
#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
/* LUCID EVO PLL specific settings and offsets */
#define LUCID_EVO_PCAL_NOT_DONE BIT(8)
#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
/* ZONDA PLL specific */
#define ZONDA_PLL_OUT_MASK 0xf
#define ZONDA_STAY_IN_CFA BIT(16)
#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll, clkr)
#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll_postdiv, clkr)
static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
const char *action)
{
u32 val;
int count;
int ret;
const char *name = clk_hw_get_name(&pll->clkr.hw);
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
for (count = 200; count > 0; count--) {
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
if (inverse && !(val & mask))
return 0;
else if ((val & mask) == mask)
return 0;
udelay(1);
}
WARN(1, "%s failed to %s!\n", name, action);
return -ETIMEDOUT;
}
#define wait_for_pll_enable_active(pll) \
wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
#define wait_for_pll_enable_lock(pll) \
wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
#define wait_for_zonda_pll_freq_lock(pll) \
wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
#define wait_for_pll_disable(pll) \
wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
#define wait_for_pll_offline(pll) \
wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
#define wait_for_pll_update(pll) \
wait_for_pll(pll, PLL_UPDATE, 1, "update")
#define wait_for_pll_update_ack_set(pll) \
wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
#define wait_for_pll_update_ack_clear(pll) \
wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
unsigned int val)
{
if (val)
regmap_write(regmap, reg, val);
}
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, mask;
regmap_write(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
if (pll_has_64bit_config(pll))
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
if (pll_alpha_width(pll) > 32)
regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
val = config->main_output_mask;
val |= config->aux_output_mask;
val |= config->aux2_output_mask;
val |= config->early_output_mask;
val |= config->pre_div_val;
val |= config->post_div_val;
val |= config->vco_val;
val |= config->alpha_en_mask;
val |= config->alpha_mode_mask;
mask = config->main_output_mask;
mask |= config->aux_output_mask;
mask |= config->aux2_output_mask;
mask |= config->early_output_mask;
mask |= config->pre_div_mask;
mask |= config->post_div_mask;
mask |= config->vco_mask;
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
if (config->test_ctl_mask)
regmap_update_bits(regmap, PLL_TEST_CTL(pll),
config->test_ctl_mask,
config->test_ctl_val);
else
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
if (config->test_ctl_hi_mask)
regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_mask,
config->test_ctl_hi_val);
else
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
if (pll->flags & SUPPORTS_FSM_MODE)
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
}
EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
val |= PLL_FSM_ENA;
if (pll->flags & SUPPORTS_OFFLINE_REQ)
val &= ~PLL_OFFLINE_REQ;
ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
if (ret)
return ret;
/* Make sure enable request goes through before waiting for update */
mb();
return wait_for_pll_enable_active(pll);
}
static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return;
if (pll->flags & SUPPORTS_OFFLINE_REQ) {
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
if (ret)
return;
ret = wait_for_pll_offline(pll);
if (ret)
return;
}
/* Disable hwfsm */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_FSM_ENA, 0);
if (ret)
return;
wait_for_pll_disable(pll);
}
static int pll_is_enabled(struct clk_hw *hw, u32 mask)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
return !!(val & mask);
}
static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
{
return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
}
static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
{
return pll_is_enabled(hw, PLL_LOCK_DET);
}
static int clk_alpha_pll_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, mask;
mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_active(pll);
}
/* Skip if already enabled */
if ((val & mask) == mask)
return 0;
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_BYPASSNL, PLL_BYPASSNL);
if (ret)
return ret;
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset.
*/
mb();
udelay(5);
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_OUTCTRL, PLL_OUTCTRL);
/* Ensure that the write above goes through before returning. */
mb();
return ret;
}
static void clk_alpha_pll_disable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, mask;
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & PLL_VOTE_FSM_ENA) {
clk_disable_regmap(hw);
return;
}
mask = PLL_OUTCTRL;
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
/* Delay of 2 output clock ticks required until output is disabled */
mb();
udelay(1);
mask = PLL_RESET_N | PLL_BYPASSNL;
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
}
static unsigned long
alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
{
return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
}
static unsigned long
alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
u32 alpha_width)
{
u64 remainder;
u64 quotient;
quotient = rate;
remainder = do_div(quotient, prate);
*l = quotient;
if (!remainder) {
*a = 0;
return rate;
}
/* Upper ALPHA_BITWIDTH bits of Alpha */
quotient = remainder << ALPHA_SHIFT(alpha_width);
remainder = do_div(quotient, prate);
if (remainder)
quotient++;
*a = quotient;
return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
}
static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
{
const struct pll_vco *v = pll->vco_table;
const struct pll_vco *end = v + pll->num_vco;
for (; v < end; v++)
if (rate >= v->min_freq && rate <= v->max_freq)
return v;
return NULL;
}
static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
u32 l, low, high, ctl;
u64 a = 0, prate = parent_rate;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 alpha_width = pll_alpha_width(pll);
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
if (ctl & PLL_ALPHA_EN) {
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
if (alpha_width > 32) {
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
&high);
a = (u64)high << 32 | low;
} else {
a = low & GENMASK(alpha_width - 1, 0);
}
if (alpha_width > ALPHA_BITWIDTH)
a >>= alpha_width - ALPHA_BITWIDTH;
}
return alpha_pll_calc_rate(prate, l, a, alpha_width);
}
static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
{
int ret;
u32 mode;
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
/* Latch the input to the PLL */
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
PLL_UPDATE);
/* Wait for 2 reference cycle before checking ACK bit */
udelay(1);
/*
* PLL will latch the new L, Alpha and freq control word.
* PLL will respond by raising PLL_ACK_LATCH output when new programming
* has been latched in and PLL is being updated. When
* UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
* automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
*/
if (mode & PLL_UPDATE_BYPASS) {
ret = wait_for_pll_update_ack_set(pll);
if (ret)
return ret;
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
} else {
ret = wait_for_pll_update(pll);
if (ret)
return ret;
}
ret = wait_for_pll_update_ack_clear(pll);
if (ret)
return ret;
/* Wait for PLL output to stabilize */
udelay(10);
return 0;
}
static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
int (*is_enabled)(struct clk_hw *))
{
if (!is_enabled(&pll->clkr.hw) ||
!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
return 0;
return __clk_alpha_pll_update_latch(pll);
}
static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate,
int (*is_enabled)(struct clk_hw *))
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
const struct pll_vco *vco;
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
vco = alpha_pll_find_vco(pll, rate);
if (pll->vco_table && !vco) {
pr_err("%s: alpha pll not in a valid vco range\n",
clk_hw_get_name(hw));
return -EINVAL;
}
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
if (alpha_width > ALPHA_BITWIDTH)
a <<= alpha_width - ALPHA_BITWIDTH;
if (alpha_width > 32)
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
if (vco) {
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_VCO_MASK << PLL_VCO_SHIFT,
vco->val << PLL_VCO_SHIFT);
}
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_ALPHA_EN, PLL_ALPHA_EN);
return clk_alpha_pll_update_latch(pll, is_enabled);
}
static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
return __clk_alpha_pll_set_rate(hw, rate, prate,
clk_alpha_pll_is_enabled);
}
static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
return __clk_alpha_pll_set_rate(hw, rate, prate,
clk_alpha_pll_hwfsm_is_enabled);
}
static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
unsigned long min_freq, max_freq;
rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
}
static unsigned long
alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
{
/*
* a contains 16 bit alpha_val in two’s complement number in the range
* of [-0.5, 0.5).
*/
if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
l -= 1;
return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
}
static unsigned long
alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
u32 *l, u32 *a)
{
u64 remainder;
u64 quotient;
quotient = rate;
remainder = do_div(quotient, prate);
*l = quotient;
if (!remainder) {
*a = 0;
return rate;
}
quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
remainder = do_div(quotient, prate);
if (remainder)
quotient++;
/*
* alpha_val should be in two’s complement number in the range
* of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
* since alpha value will be subtracted in this case.
*/
if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
*l += 1;
*a = quotient;
return alpha_huayra_pll_calc_rate(prate, *l, *a);
}
static unsigned long
alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
u64 rate = parent_rate, tmp;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha = 0, ctl, alpha_m, alpha_n;
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
if (ctl & PLL_ALPHA_EN) {
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
/*
* Depending upon alpha_mode, it can be treated as M/N value or
* as a two’s complement number. When alpha_mode=1,
* pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
*
* Fout=FIN*(L+(M/N))
*
* M is a signed number (-128 to 127) and N is unsigned
* (0 to 255). M/N has to be within +/-0.5.
*
* When alpha_mode=0, it is a two’s complement number in the
* range [-0.5, 0.5).
*
* Fout=FIN*(L+(alpha_val)/2^16)
*
* where alpha_val is two’s complement number.
*/
if (!(ctl & PLL_ALPHA_MODE))
return alpha_huayra_pll_calc_rate(rate, l, alpha);
alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
rate *= l;
tmp = parent_rate;
if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
tmp *= alpha_m;
do_div(tmp, alpha_n);
rate -= tmp;
} else {
tmp *= alpha_m;
do_div(tmp, alpha_n);
rate += tmp;
}
return rate;
}
return alpha_huayra_pll_calc_rate(rate, l, alpha);
}
static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, a, ctl, cur_alpha = 0;
rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
if (ctl & PLL_ALPHA_EN)
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
/*
* Huayra PLL supports PLL dynamic programming. User can change L_VAL,
* without having to go through the power on sequence.
*/
if (clk_alpha_pll_is_enabled(hw)) {
if (cur_alpha != a) {
pr_err("%s: clock needs to be gated\n",
clk_hw_get_name(hw));
return -EBUSY;
}
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
/* Ensure that the write above goes to detect L val change. */
mb();
return wait_for_pll_enable_lock(pll);
}
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
if (a == 0)
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_ALPHA_EN, 0x0);
else
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
return 0;
}
static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
u32 l, a;
return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
}
static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
struct regmap *regmap)
{
u32 mode_val, opmode_val;
int ret;
ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
if (ret)
return 0;
return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
}
static int clk_trion_pll_is_enabled(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
return trion_pll_is_enabled(pll, pll->clkr.regmap);
}
static int clk_trion_pll_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;
ret = regmap_read(regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_active(pll);
}
/* Set operation mode to RUN */
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Enable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
/* Enable the global PLL outputs */
return regmap_update_bits(regmap, PLL_MODE(pll),
PLL_OUTCTRL, PLL_OUTCTRL);
}
static void clk_trion_pll_disable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;
ret = regmap_read(regmap, PLL_MODE(pll), &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & PLL_VOTE_FSM_ENA) {
clk_disable_regmap(hw);
return;
}
/* Disable the global PLL output */
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return;
/* Disable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, frac, alpha_width = pll_alpha_width(pll);
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}
const struct clk_ops clk_alpha_pll_fixed_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
const struct clk_ops clk_alpha_pll_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_alpha_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
const struct clk_ops clk_alpha_pll_huayra_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_huayra_recalc_rate,
.round_rate = alpha_pll_huayra_round_rate,
.set_rate = alpha_pll_huayra_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
const struct clk_ops clk_alpha_pll_hwfsm_ops = {
.enable = clk_alpha_pll_hwfsm_enable,
.disable = clk_alpha_pll_hwfsm_disable,
.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_alpha_pll_hwfsm_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
.enable = clk_trion_pll_enable,
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 ctl;
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
ctl >>= PLL_POST_DIV_SHIFT;
ctl &= PLL_POST_DIV_MASK(pll);
return parent_rate >> fls(ctl);
}
static const struct clk_div_table clk_alpha_div_table[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ 0xf, 16 },
{ }
};
static const struct clk_div_table clk_alpha_2bit_div_table[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ }
};
static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
const struct clk_div_table *table;
if (pll->width == 2)
table = clk_alpha_2bit_div_table;
else
table = clk_alpha_div_table;
return divider_round_rate(hw, rate, prate, table,
pll->width, CLK_DIVIDER_POWER_OF_TWO);
}
static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 ctl, div;
regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
ctl >>= PLL_POST_DIV_SHIFT;
ctl &= BIT(pll->width) - 1;
div = 1 << fls(ctl);
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
return DIV_ROUND_UP_ULL((u64)*prate, div);
}
static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
int div;
/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
div << PLL_POST_DIV_SHIFT);
}
const struct clk_ops clk_alpha_pll_postdiv_ops = {
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_round_rate,
.set_rate = clk_alpha_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
.round_rate = clk_alpha_pll_postdiv_round_ro_rate,
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, mask;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
if (config->post_div_mask) {
mask = config->post_div_mask;
val = config->post_div_val;
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
}
if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
PLL_FSM_LEGACY_MODE);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
PLL_UPDATE_BYPASS);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
static int alpha_pll_fabia_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, opmode_val;
struct regmap *regmap = pll->clkr.regmap;
ret = regmap_read(regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_active(pll);
}
ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
if (ret)
return ret;
/* Skip If PLL is already running */
if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
return 0;
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return ret;
ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
if (ret)
return ret;
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
PLL_RESET_N);
if (ret)
return ret;
ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
if (ret)
return ret;
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
PLL_OUTCTRL);
}
static void alpha_pll_fabia_disable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
struct regmap *regmap = pll->clkr.regmap;
ret = regmap_read(regmap, PLL_MODE(pll), &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & PLL_FSM_ENA) {
clk_disable_regmap(hw);
return;
}
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return;
/* Disable main outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL in STANDBY */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
}
static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, frac, alpha_width = pll_alpha_width(pll);
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}
/*
* Due to limited number of bits for fractional rate programming, the
* rounded up rate could be marginally higher than the requested rate.
*/
static int alpha_pll_check_rate_margin(struct clk_hw *hw,
unsigned long rrate, unsigned long rate)
{
unsigned long rate_margin = rate + PLL_RATE_MARGIN;
if (rrate > rate_margin || rrate < rate) {
pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
clk_hw_get_name(hw), rrate, rate, rate_margin);
return -EINVAL;
}
return 0;
}
static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha_width = pll_alpha_width(pll);
unsigned long rrate;
int ret;
u64 a;
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
ret = alpha_pll_check_rate_margin(hw, rrate, rate);
if (ret < 0)
return ret;
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
return __clk_alpha_pll_update_latch(pll);
}
static int alpha_pll_fabia_prepare(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
const struct pll_vco *vco;
struct clk_hw *parent_hw;
unsigned long cal_freq, rrate;
u32 cal_l, val, alpha_width = pll_alpha_width(pll);
const char *name = clk_hw_get_name(hw);
u64 a;
int ret;
/* Check if calibration needs to be done i.e. PLL is in reset */
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
/* Return early if calibration is not needed. */
if (val & PLL_RESET_N)
return 0;
vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
if (!vco) {
pr_err("%s: alpha pll not in a valid vco range\n", name);
return -EINVAL;
}
cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
pll->vco_table[0].max_freq) * 54, 100);
parent_hw = clk_hw_get_parent(hw);
if (!parent_hw)
return -EINVAL;
rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
&cal_l, &a, alpha_width);
ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
if (ret < 0)
return ret;
/* Setup PLL for calibration frequency */
regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
/* Bringup the PLL at calibration frequency */
ret = clk_alpha_pll_enable(hw);
if (ret) {
pr_err("%s: alpha pll calibration failed\n", name);
return ret;
}
clk_alpha_pll_disable(hw);
return 0;
}
const struct clk_ops clk_alpha_pll_fabia_ops = {
.prepare = alpha_pll_fabia_prepare,
.enable = alpha_pll_fabia_enable,
.disable = alpha_pll_fabia_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.set_rate = alpha_pll_fabia_set_rate,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
.enable = alpha_pll_fabia_enable,
.disable = alpha_pll_fabia_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 i, div = 1, val;
int ret;
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
if (ret)
return ret;
val >>= pll->post_div_shift;
val &= BIT(pll->width) - 1;
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].val == val) {
div = pll->post_div_table[i].div;
break;
}
}
return (parent_rate / div);
}
static unsigned long
clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 i, div = 1, val;
regmap_read(regmap, PLL_USER_CTL(pll), &val);
val >>= pll->post_div_shift;
val &= PLL_POST_DIV_MASK(pll);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].val == val) {
div = pll->post_div_table[i].div;
break;
}
}
return (parent_rate / div);
}
static long
clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
return divider_round_rate(hw, rate, prate, pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
};
static int
clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
struct regmap *regmap = pll->clkr.regmap;
int i, val = 0, div;
div = DIV_ROUND_UP_ULL(parent_rate, rate);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].div == div) {
val = pll->post_div_table[i].val;
break;
}
}
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
val << PLL_POST_DIV_SHIFT);
}
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
.round_rate = clk_trion_pll_postdiv_round_rate,
.set_rate = clk_trion_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
return divider_round_rate(hw, rate, prate, pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
}
static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
int i, val = 0, div, ret;
/*
* If the PLL is in FSM mode, then treat set_rate callback as a
* no-operation.
*/
ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
if (val & PLL_VOTE_FSM_ENA)
return 0;
div = DIV_ROUND_UP_ULL(parent_rate, rate);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].div == div) {
val = pll->post_div_table[i].val;
break;
}
}
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
(BIT(pll->width) - 1) << pll->post_div_shift,
val << pll->post_div_shift);
}
const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
/**
* clk_trion_pll_configure - configure the trion pll
*
* @pll: clk alpha pll
* @regmap: register map
* @config: configuration to apply for pll
*/
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
/*
* If the bootloader left the PLL enabled it's likely that there are
* RCGs that will lock up if we disable the PLL below.
*/
if (trion_pll_is_enabled(pll, regmap)) {
pr_debug("Trion PLL is already enabled, skipping configuration\n");
return;
}
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
config->test_ctl_hi1_val);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
PLL_UPDATE_BYPASS);
/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Set operation mode to OFF */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
/* Place the PLL in STANDBY mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
/*
* The TRION PLL requires a power-on self-calibration which happens when the
* PLL comes out of reset. Calibrate in case it is not completed.
*/
static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
int ret;
/* Return early if calibration is not needed. */
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
if (val & pcal_done)
return 0;
/* On/off to calibrate */
ret = clk_trion_pll_enable(hw);
if (!ret)
clk_trion_pll_disable(hw);
return ret;
}
static int alpha_pll_trion_prepare(struct clk_hw *hw)
{
return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
}
static int alpha_pll_lucid_prepare(struct clk_hw *hw)
{
return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
}
static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate, u32 latch_bit, u32 latch_ack)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long rrate;
u32 val, l, alpha_width = pll_alpha_width(pll);
u64 a;
int ret;
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
ret = alpha_pll_check_rate_margin(hw, rrate, rate);
if (ret < 0)
return ret;
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
/* Latch the PLL input */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
if (ret)
return ret;
/* Wait for 2 reference cycles before checking the ACK bit. */
udelay(1);
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (!(val & latch_ack)) {
pr_err("Lucid PLL latch failed. Output may be unstable!\n");
return -EINVAL;
}
/* Return the latch input to 0 */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
if (ret)
return ret;
if (clk_hw_is_enabled(hw)) {
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
}
/* Wait for PLL output to stabilize */
udelay(100);
return 0;
}
static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
}
const struct clk_ops clk_alpha_pll_trion_ops = {
.prepare = alpha_pll_trion_prepare,
.enable = clk_trion_pll_enable,
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_trion_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
const struct clk_ops clk_alpha_pll_lucid_ops = {
.prepare = alpha_pll_lucid_prepare,
.enable = clk_trion_pll_enable,
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_trion_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
}
EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha_width = pll_alpha_width(pll);
int ret;
unsigned long rrate;
u64 a;
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
ret = alpha_pll_check_rate_margin(hw, rrate, rate);
if (ret < 0)
return ret;
/* change L_VAL without having to go through the power on sequence */
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
if (clk_hw_is_enabled(hw))
return wait_for_pll_enable_lock(pll);
return 0;
}
const struct clk_ops clk_alpha_pll_agera_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = alpha_pll_fabia_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_alpha_pll_agera_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
int ret;
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_lock(pll);
}
/* Check if PLL is already enabled, return if enabled */
ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
if (ret < 0)
return ret;
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Enable the PLL outputs */
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
/* Enable the global PLL outputs */
return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
}
static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val;
int ret;
ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
clk_disable_regmap(hw);
return;
}
/* Disable the global PLL output */
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return;
/* Disable the PLL outputs */
ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
}
/*
* The Lucid 5LPE PLL requires a power-on self-calibration which happens
* when the PLL comes out of reset. Calibrate in case it is not completed.
*/
static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct clk_hw *p;
u32 val = 0;
int ret;
/* Return early if calibration is not needed. */
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (val & LUCID_5LPE_PCAL_DONE)
return 0;
p = clk_hw_get_parent(hw);
if (!p)
return -EINVAL;
ret = alpha_pll_lucid_5lpe_enable(hw);
if (ret)
return ret;
alpha_pll_lucid_5lpe_disable(hw);
return 0;
}
static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
return __alpha_pll_trion_set_rate(hw, rate, prate,
LUCID_5LPE_PLL_LATCH_INPUT,
LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
}
static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate,
unsigned long enable_vote_run)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
struct regmap *regmap = pll->clkr.regmap;
int i, val, div, ret;
u32 mask;
/*
* If the PLL is in FSM mode, then treat set_rate callback as a
* no-operation.
*/
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
if (ret)
return ret;
if (val & enable_vote_run)
return 0;
if (!pll->post_div_table) {
pr_err("Missing the post_div_table for the %s PLL\n",
clk_hw_get_name(&pll->clkr.hw));
return -EINVAL;
}
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
for (i = 0; i < pll->num_post_div; i++) {
if (pll->post_div_table[i].div == div) {
val = pll->post_div_table[i].val;
break;
}
}
mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
mask, val << pll->post_div_shift);
}
static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
}
const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
.prepare = alpha_pll_lucid_5lpe_prepare,
.enable = alpha_pll_lucid_5lpe_enable,
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
.enable = alpha_pll_lucid_5lpe_enable,
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Set operation mode to OFF */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
/* Place the PLL in STANDBY mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
static int clk_zonda_pll_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;
regmap_read(regmap, PLL_MODE(pll), &val);
/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_active(pll);
}
/* Get the PLL out of bypass mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
/*
* H/W requires a 1us delay between disabling the bypass and
* de-asserting the reset.
*/
udelay(1);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
/* Set operation mode to RUN */
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
regmap_read(regmap, PLL_TEST_CTL(pll), &val);
/* If cfa mode then poll for freq lock */
if (val & ZONDA_STAY_IN_CFA)
ret = wait_for_zonda_pll_freq_lock(pll);
else
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Enable the PLL outputs */
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
/* Enable the global PLL outputs */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
return 0;
}
static void clk_zonda_pll_disable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
regmap_read(regmap, PLL_MODE(pll), &val);
/* If in FSM mode, just unvote it */
if (val & PLL_VOTE_FSM_ENA) {
clk_disable_regmap(hw);
return;
}
/* Disable the global PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Disable the PLL outputs */
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
/* Put the PLL in bypass and reset */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
/* Place the PLL mode in OFF state */
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
}
static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long rrate;
u32 test_ctl_val;
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
int ret;
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
ret = alpha_pll_check_rate_margin(hw, rrate, rate);
if (ret < 0)
return ret;
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
/* Wait before polling for the frequency latch */
udelay(5);
/* Read stay in cfa mode */
regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
/* If cfa mode then poll for freq lock */
if (test_ctl_val & ZONDA_STAY_IN_CFA)
ret = wait_for_zonda_pll_freq_lock(pll);
else
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Wait for PLL output to stabilize */
udelay(100);
return 0;
}
const struct clk_ops clk_alpha_pll_zonda_ops = {
.enable = clk_zonda_pll_enable,
.disable = clk_zonda_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_zonda_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 lval = config->l;
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Set operation mode to STANDBY and de-assert the reset */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_lock(pll);
}
/* Check if PLL is already enabled */
ret = trion_pll_is_enabled(pll, regmap);
if (ret < 0) {
return ret;
} else if (ret) {
pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
return 0;
}
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
/* Set operation mode to RUN */
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;
/* Enable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
/* Enable the global PLL outputs */
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
if (ret)
return ret;
/* Ensure that the write above goes through before returning. */
mb();
return ret;
}
static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;
ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
clk_disable_regmap(hw);
return;
}
/* Disable the global PLL output */
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return;
/* Disable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
if (reset)
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
}
static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct clk_hw *p;
u32 val = 0;
int ret;
/* Return early if calibration is not needed. */
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (!(val & LUCID_EVO_PCAL_NOT_DONE))
return 0;
p = clk_hw_get_parent(hw);
if (!p)
return -EINVAL;
ret = alpha_pll_lucid_evo_enable(hw);
if (ret)
return ret;
_alpha_pll_lucid_evo_disable(hw, reset);
return 0;
}
static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
{
_alpha_pll_lucid_evo_disable(hw, false);
}
static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
{
return _alpha_pll_lucid_evo_prepare(hw, false);
}
static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
{
_alpha_pll_lucid_evo_disable(hw, true);
}
static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
{
return _alpha_pll_lucid_evo_prepare(hw, true);
}
static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 l, frac;
regmap_read(regmap, PLL_L_VAL(pll), &l);
l &= LUCID_EVO_PLL_L_VAL_MASK;
regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
}
static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
}
const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
.enable = alpha_pll_lucid_evo_enable,
.disable = alpha_pll_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
.prepare = alpha_pll_lucid_evo_prepare,
.enable = alpha_pll_lucid_evo_enable,
.disable = alpha_pll_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
.prepare = alpha_pll_reset_lucid_evo_prepare,
.enable = alpha_pll_lucid_evo_enable,
.disable = alpha_pll_reset_lucid_evo_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = alpha_pll_lucid_5lpe_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll),
PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
PLL_RESET_N | PLL_BYPASSNL);
}
EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l;
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
return parent_rate * l;
}
static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long min_freq, max_freq;
u32 l;
u64 a;
rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
}
const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
.enable = alpha_pll_lucid_5lpe_enable,
.disable = alpha_pll_lucid_5lpe_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_rivian_evo_pll_recalc_rate,
.round_rate = clk_rivian_evo_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, val_u, mask, mask_u;
regmap_write(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
if (pll_has_64bit_config(pll))
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
if (pll_alpha_width(pll) > 32)
regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
val = config->main_output_mask;
val |= config->aux_output_mask;
val |= config->aux2_output_mask;
val |= config->early_output_mask;
val |= config->pre_div_val;
val |= config->post_div_val;
val |= config->vco_val;
val |= config->alpha_en_mask;
val |= config->alpha_mode_mask;
mask = config->main_output_mask;
mask |= config->aux_output_mask;
mask |= config->aux2_output_mask;
mask |= config->early_output_mask;
mask |= config->pre_div_mask;
mask |= config->post_div_mask;
mask |= config->vco_mask;
mask |= config->alpha_en_mask;
mask |= config->alpha_mode_mask;
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
/* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
val_u |= config->lock_det;
mask_u = config->status_mask;
mask_u |= config->lock_det;
regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
if (pll->flags & SUPPORTS_FSM_MODE)
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
}
EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
u32 l;
u64 a;
req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
&l, &a, ALPHA_REG_BITWIDTH);
return 0;
}
static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
int ret;
u32 l;
u64 a;
rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
a >> ALPHA_BITWIDTH);
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_ALPHA_EN, PLL_ALPHA_EN);
if (!clk_hw_is_enabled(hw))
return 0;
/*
* Stromer PLL supports Dynamic programming.
* It allows the PLL frequency to be changed on-the-fly without first
* execution of a shutdown procedure followed by a bring up procedure.
*/
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
PLL_UPDATE);
ret = wait_for_pll_update(pll);
if (ret)
return ret;
return wait_for_pll_enable_lock(pll);
}
const struct clk_ops clk_alpha_pll_stromer_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.determine_rate = clk_alpha_pll_stromer_determine_rate,
.set_rate = clk_alpha_pll_stromer_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
| linux-master | drivers/clk/qcom/clk-alpha-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_SLEEP_CLK,
P_VIDEO_PLL0_OUT_EVEN,
};
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 400MHz Configuration */
static const struct alpha_pll_config video_pll0_config = {
.l = 0x14,
.alpha = 0xD555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_EVEN, 3 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .fw_name = "sleep_clk" },
};
static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
F(133333333, P_VIDEO_PLL0_OUT_EVEN, 3, 0, 0),
F(240000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
F(335000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
F(424000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
F(460000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_iris_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_iris_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_iris_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_sleep_clk_src = {
.cmd_rcgr = 0x701c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_sleep_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch video_cc_iris_ahb_clk = {
.halt_reg = 0x5004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_iris_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_axi_clk = {
.halt_reg = 0x800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_core_clk = {
.halt_reg = 0x3010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvsc_core_clk = {
.halt_reg = 0x2014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvsc_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvsc_ctl_axi_clk = {
.halt_reg = 0x8004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvsc_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_sleep_clk = {
.halt_reg = 0x7034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ahb_clk = {
.halt_reg = 0x801c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x801c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mvs0_gdsc = {
.gdscr = 0x3004,
.pd = {
.name = "mvs0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc mvsc_gdsc = {
.gdscr = 0x2004,
.pd = {
.name = "mvsc_gdsc",
},
.flags = RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sc7280_clocks[] = {
[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
[VIDEO_CC_MVS0_AXI_CLK] = &video_cc_mvs0_axi_clk.clkr,
[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
[VIDEO_CC_MVSC_CTL_AXI_CLK] = &video_cc_mvsc_ctl_axi_clk.clkr,
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
[VIDEO_PLL0] = &video_pll0.clkr,
};
static struct gdsc *video_cc_sc7280_gdscs[] = {
[MVS0_GDSC] = &mvs0_gdsc,
[MVSC_GDSC] = &mvsc_gdsc,
};
static const struct regmap_config video_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xb000,
.fast_io = true,
};
static const struct qcom_cc_desc video_cc_sc7280_desc = {
.config = &video_cc_sc7280_regmap_config,
.clks = video_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(video_cc_sc7280_clocks),
.gdscs = video_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sc7280_gdscs),
};
static const struct of_device_id video_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sc7280_match_table);
static int video_cc_sc7280_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &video_cc_sc7280_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
return qcom_cc_really_probe(pdev, &video_cc_sc7280_desc, regmap);
}
static struct platform_driver video_cc_sc7280_driver = {
.probe = video_cc_sc7280_probe,
.driver = {
.name = "video_cc-sc7280",
.of_match_table = video_cc_sc7280_match_table,
},
};
static int __init video_cc_sc7280_init(void)
{
return platform_driver_register(&video_cc_sc7280_driver);
}
subsys_initcall(video_cc_sc7280_init);
static void __exit video_cc_sc7280_exit(void)
{
platform_driver_unregister(&video_cc_sc7280_driver);
}
module_exit(video_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI VIDEO_CC sc7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/videocc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
};
static struct clk_branch tcsr_pcie_0_clkref_en = {
.halt_reg = 0x15100,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x15100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
.halt_reg = 0x15114,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x15114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_pcie_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_ufs_clkref_en = {
.halt_reg = 0x15110,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x15110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_ufs_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_ufs_pad_clkref_en = {
.halt_reg = 0x15104,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x15104,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_ufs_pad_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_clkref_en = {
.halt_reg = 0x15118,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x15118,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_clkref_en = {
.halt_reg = 0x15108,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x15108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_usb3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_sm8550_clocks[] = {
[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
[TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr,
[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
};
static const struct regmap_config tcsr_cc_sm8550_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x2f000,
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_sm8550_desc = {
.config = &tcsr_cc_sm8550_regmap_config,
.clks = tcsr_cc_sm8550_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_sm8550_clocks),
};
static const struct of_device_id tcsr_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-tcsr" },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table);
static int tcsr_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap);
}
static struct platform_driver tcsr_cc_sm8550_driver = {
.probe = tcsr_cc_sm8550_probe,
.driver = {
.name = "tcsr_cc-sm8550",
.of_match_table = tcsr_cc_sm8550_match_table,
},
};
static int __init tcsr_cc_sm8550_init(void)
{
return platform_driver_register(&tcsr_cc_sm8550_driver);
}
subsys_initcall(tcsr_cc_sm8550_init);
static void __exit tcsr_cc_sm8550_exit(void)
{
platform_driver_unregister(&tcsr_cc_sm8550_driver);
}
module_exit(tcsr_cc_sm8550_exit);
MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/tcsrcc-sm8550.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "reset.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_XO,
DT_SLEEP_CLK,
DT_BIAS_PLL_UBI_NC_CLK,
DT_PCIE30_PHY0_PIPE_CLK,
DT_PCIE30_PHY1_PIPE_CLK,
DT_PCIE30_PHY2_PIPE_CLK,
DT_PCIE30_PHY3_PIPE_CLK,
DT_USB3PHY_0_CC_PIPE_CLK,
};
enum {
P_XO,
P_PCIE30_PHY0_PIPE,
P_PCIE30_PHY1_PIPE,
P_PCIE30_PHY2_PIPE,
P_PCIE30_PHY3_PIPE,
P_USB3PHY_0_PIPE,
P_GPLL0,
P_GPLL0_DIV2,
P_GPLL0_OUT_AUX,
P_GPLL2,
P_GPLL4,
P_PI_SLEEP,
P_BIAS_PLL_UBI_NC_CLK,
};
static const struct parent_map gcc_xo_map[] = {
{ P_XO, 0 },
};
static const struct clk_parent_data gcc_xo_data[] = {
{ .index = DT_XO },
};
static const struct clk_parent_data gcc_sleep_clk_data[] = {
{ .index = DT_SLEEP_CLK },
};
static struct clk_alpha_pll gpll0_main = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpll0_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll0_out_main_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(const struct clk_init_data) {
.name = "gpll0_out_main_div2",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gpll4_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]) {
&gpll4_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gpll2_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll2",
.parent_hws = (const struct clk_hw *[]) {
&gpll2_main.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_branch gcc_sleep_clk_src = {
.halt_reg = 0x3400c,
.clkr = {
.enable_reg = 0x3400c,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sleep_clk_src",
.parent_data = gcc_sleep_clk_data,
.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
{ P_GPLL0, 5 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
{ P_PI_SLEEP, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
{ P_PI_SLEEP, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .index = DT_BIAS_PLL_UBI_NC_CLK },
};
static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
{ P_BIAS_PLL_UBI_NC_CLK, 3 },
};
static const struct clk_parent_data
gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map
gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_PI_SLEEP, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data
gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL4, 1 },
{ P_GPLL0, 3 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
{ .index = DT_USB3PHY_0_CC_PIPE_CLK },
{ .index = DT_XO },
};
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
{ P_USB3PHY_0_PIPE, 0 },
{ P_XO, 2 },
};
static const struct clk_parent_data
gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
{ .index = DT_XO},
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL4, 1 },
{ P_GPLL0, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL4, 3 },
{ P_PI_SLEEP, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_GPLL2, 3 },
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x2400c,
.freq_tbl = ftbl_apss_ahb_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
F(533000000, P_GPLL0, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 apss_axi_clk_src = {
.cmd_rcgr = 0x24004,
.freq_tbl = ftbl_apss_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "apss_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
F(9600000, P_XO, 2.5, 0, 0),
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x02018,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 2, 5),
F(4800000, P_XO, 5, 0, 0),
F(9600000, P_XO, 2, 4, 5),
F(16000000, P_GPLL0, 10, 1, 5),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02004,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03018,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03004,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04018,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04004,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05018,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05004,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x06018,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x06004,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x07018,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x07004,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x0202c,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x0302c,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x0402c,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x0502c,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x0602c,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x0702c,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_crypto_clk_src = {
.cmd_rcgr = 0x16004,
.freq_tbl = ftbl_gcc_crypto_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_crypto_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1600c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x24018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&apss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x2401c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_apss_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&apss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2024,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02020,
.clkr = {
.enable_reg = 0x02020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03024,
.clkr = {
.enable_reg = 0x03024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x03020,
.clkr = {
.enable_reg = 0x03020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04024,
.clkr = {
.enable_reg = 0x04024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x04020,
.clkr = {
.enable_reg = 0x04020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05024,
.clkr = {
.enable_reg = 0x05024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup4_i2c_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x05020,
.clkr = {
.enable_reg = 0x05020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup4_spi_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x06024,
.clkr = {
.enable_reg = 0x06024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup5_i2c_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x06020,
.clkr = {
.enable_reg = 0x06020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup5_spi_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x07024,
.clkr = {
.enable_reg = 0x07024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup6_i2c_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x07020,
.clkr = {
.enable_reg = 0x07020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup6_spi_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x02040,
.clkr = {
.enable_reg = 0x02040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart1_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x03040,
.clkr = {
.enable_reg = 0x03040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart2_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x04054,
.clkr = {
.enable_reg = 0x04054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart3_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x05040,
.clkr = {
.enable_reg = 0x05040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart4_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x06040,
.clkr = {
.enable_reg = 0x06040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart5_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x07040,
.clkr = {
.enable_reg = 0x07040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart6_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static struct clk_rcg2 pcie0_axi_m_clk_src = {
.cmd_rcgr = 0x28018,
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie0_axi_m_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie0_axi_m_clk = {
.halt_reg = 0x28038,
.clkr = {
.enable_reg = 0x28038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
.halt_reg = 0x2e07c,
.clkr = {
.enable_reg = 0x2e07c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_anoc_pcie0_1lane_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie1_axi_m_clk_src = {
.cmd_rcgr = 0x29018,
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie1_axi_m_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie1_axi_m_clk = {
.halt_reg = 0x29038,
.clkr = {
.enable_reg = 0x29038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
.halt_reg = 0x2e08c,
.clkr = {
.enable_reg = 0x2e08c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_anoc_pcie1_1lane_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
F(342857143, P_GPLL4, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 pcie2_axi_m_clk_src = {
.cmd_rcgr = 0x2a018,
.freq_tbl = ftbl_pcie2_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie2_axi_m_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie2_axi_m_clk = {
.halt_reg = 0x2a038,
.clkr = {
.enable_reg = 0x2a038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie2_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
.halt_reg = 0x2e080,
.clkr = {
.enable_reg = 0x2e080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_anoc_pcie2_2lane_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie2_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie3_axi_m_clk_src = {
.cmd_rcgr = 0x2b018,
.freq_tbl = ftbl_pcie2_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie3_axi_m_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie3_axi_m_clk = {
.halt_reg = 0x2b038,
.clkr = {
.enable_reg = 0x2b038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie3_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
.halt_reg = 0x2e090,
.clkr = {
.enable_reg = 0x2e090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_anoc_pcie3_2lane_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie3_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie0_axi_s_clk_src = {
.cmd_rcgr = 0x28020,
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie0_axi_s_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie0_axi_s_clk = {
.halt_reg = 0x2803c,
.clkr = {
.enable_reg = 0x2803c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_axi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
.halt_reg = 0x28040,
.clkr = {
.enable_reg = 0x28040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
.halt_reg = 0x2e048,
.clkr = {
.enable_reg = 0x2e048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie0_1lane_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie1_axi_s_clk_src = {
.cmd_rcgr = 0x29020,
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie1_axi_s_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie1_axi_s_clk = {
.halt_reg = 0x2903c,
.clkr = {
.enable_reg = 0x2903c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_axi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
.halt_reg = 0x29040,
.clkr = {
.enable_reg = 0x29040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
.halt_reg = 0x2e04c,
.clkr = {
.enable_reg = 0x2e04c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie1_1lane_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie2_axi_s_clk_src = {
.cmd_rcgr = 0x2a020,
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie2_axi_s_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie2_axi_s_clk = {
.halt_reg = 0x2a03c,
.clkr = {
.enable_reg = 0x2a03c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_axi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie2_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
.halt_reg = 0x2a040,
.clkr = {
.enable_reg = 0x2a040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie2_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
.halt_reg = 0x2e050,
.clkr = {
.enable_reg = 0x2e050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie2_2lane_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie2_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie3_axi_s_clk_src = {
.cmd_rcgr = 0x2b020,
.freq_tbl = ftbl_pcie0_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie3_axi_s_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie3_axi_s_clk = {
.halt_reg = 0x2b03c,
.clkr = {
.enable_reg = 0x2b03c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3_axi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie3_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
.halt_reg = 0x2b040,
.clkr = {
.enable_reg = 0x2b040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie3_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
.halt_reg = 0x2e054,
.clkr = {
.enable_reg = 0x2e054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_2lane_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie3_axi_s_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
.reg = 0x28064,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "pcie0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE30_PHY0_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "pcie1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE30_PHY1_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "pcie2_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE30_PHY2_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
.reg = 0x2b064,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "pcie3_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE30_PHY3_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcie0_rchng_clk_src = {
.cmd_rcgr = 0x28028,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie0_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie0_rchng_clk = {
.halt_reg = 0x28028,
.clkr = {
.enable_reg = 0x28028,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_rchng_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_rchng_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie1_rchng_clk_src = {
.cmd_rcgr = 0x29028,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie1_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie1_rchng_clk = {
.halt_reg = 0x29028,
.clkr = {
.enable_reg = 0x29028,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_rchng_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_rchng_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie2_rchng_clk_src = {
.cmd_rcgr = 0x2a028,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie2_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie2_rchng_clk = {
.halt_reg = 0x2a028,
.clkr = {
.enable_reg = 0x2a028,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_rchng_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie2_rchng_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie3_rchng_clk_src = {
.cmd_rcgr = 0x2b028,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie3_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie3_rchng_clk = {
.halt_reg = 0x2b028,
.clkr = {
.enable_reg = 0x2b028,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3_rchng_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie3_rchng_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(20000000, P_GPLL0, 10, 1, 4),
{ }
};
static struct clk_rcg2 pcie_aux_clk_src = {
.cmd_rcgr = 0x28004,
.freq_tbl = ftbl_pcie_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcie_aux_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie0_aux_clk = {
.halt_reg = 0x28034,
.clkr = {
.enable_reg = 0x28034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_aux_clk = {
.halt_reg = 0x29034,
.clkr = {
.enable_reg = 0x29034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2_aux_clk = {
.halt_reg = 0x2a034,
.clkr = {
.enable_reg = 0x2a034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3_aux_clk = {
.halt_reg = 0x2b034,
.clkr = {
.enable_reg = 0x2b034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb0_aux_clk_src = {
.cmd_rcgr = 0x2c018,
.freq_tbl = ftbl_usb_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "usb0_aux_clk_src",
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_usb0_aux_clk = {
.halt_reg = 0x2c048,
.clkr = {
.enable_reg = 0x2c048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x2c004,
.freq_tbl = ftbl_usb0_master_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "usb0_master_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_usb0_master_clk = {
.halt_reg = 0x2c044,
.clkr = {
.enable_reg = 0x2c044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_master_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_usb_clk = {
.halt_reg = 0x2e058,
.clkr = {
.enable_reg = 0x2e058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_usb_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_anoc_usb_axi_clk = {
.halt_reg = 0x2e084,
.clkr = {
.enable_reg = 0x2e084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_anoc_usb_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(60000000, P_GPLL4, 10, 1, 2),
{ }
};
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x2c02c,
.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
.reg = 0x2c040,
.shift = 0,
.width = 2,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "usb0_mock_utmi_div_clk_src",
.parent_data = &(const struct clk_parent_data) {
.hw = &usb0_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_usb0_mock_utmi_clk = {
.halt_reg = 0x2c04c,
.clkr = {
.enable_reg = 0x2c04c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_mock_utmi_div_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x2C074,
.shift = 8,
.width = 2,
.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "usb0_pipe_clk_src",
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_branch gcc_usb0_pipe_clk = {
.halt_reg = 0x2c054,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2c054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_pipe_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_sleep_clk = {
.halt_reg = 0x2c058,
.clkr = {
.enable_reg = 0x2c058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_sleep_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
F(24000000, P_GPLL2, 12, 1, 4),
F(48000000, P_GPLL2, 12, 1, 2),
F(96000000, P_GPLL2, 12, 0, 0),
F(177777778, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL2, 6, 0, 0),
F(384000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x33004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x3302c,
.clkr = {
.enable_reg = 0x3302c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc1_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
F(150000000, P_GPLL4, 8, 0, 0),
F(300000000, P_GPLL4, 4, 0, 0),
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x33018,
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x33030,
.clkr = {
.enable_reg = 0x33030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc1_ice_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x31004,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.flags = CLK_IS_CRITICAL,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16010,
.clkr = {
.enable_reg = 0x16010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16014,
.clkr = {
.enable_reg = 0x16014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nsscfg_clk = {
.halt_reg = 0x1702c,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nsscfg_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_nsscc_clk = {
.halt_reg = 0x17030,
.clkr = {
.enable_reg = 0x17030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_nsscc_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nsscc_clk = {
.halt_reg = 0x17034,
.clkr = {
.enable_reg = 0x17034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nsscc_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
.halt_reg = 0x17080,
.clkr = {
.enable_reg = 0x17080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_pcnoc_1_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_ahb_clk = {
.halt_reg = 0x2d064,
.clkr = {
.enable_reg = 0x2d064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_dap_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_cfg_ahb_clk = {
.halt_reg = 0x2d068,
.clkr = {
.enable_reg = 0x2d068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_ahb_clk = {
.halt_reg = 0x32010,
.clkr = {
.enable_reg = 0x32010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_clk = {
.halt_reg = 0x32014,
.clkr = {
.enable_reg = 0x32014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio_ahb_clk = {
.halt_reg = 0x17040,
.clkr = {
.enable_reg = 0x17040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_mdio_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_ahb_clk = {
.halt_reg = 0x1704c,
.clkr = {
.enable_reg = 0x1704c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy0_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_ahb_clk = {
.halt_reg = 0x1705c,
.clkr = {
.enable_reg = 0x1705c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy2_ahb_clk = {
.halt_reg = 0x1706c,
.clkr = {
.enable_reg = 0x1706c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy2_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
.halt_reg = 0x3a004,
.clkr = {
.enable_reg = 0x3a004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cmn_12gpll_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_apu_clk = {
.halt_reg = 0x3a00c,
.clkr = {
.enable_reg = 0x3a00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cmn_12gpll_apu_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_ahb_clk = {
.halt_reg = 0x28030,
.clkr = {
.enable_reg = 0x28030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_ahb_clk = {
.halt_reg = 0x29030,
.clkr = {
.enable_reg = 0x29030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2_ahb_clk = {
.halt_reg = 0x2a030,
.clkr = {
.enable_reg = 0x2a030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3_ahb_clk = {
.halt_reg = 0x2b030,
.clkr = {
.enable_reg = 0x2b030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
.halt_reg = 0x2c05c,
.clkr = {
.enable_reg = 0x2c05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x33034,
.clkr = {
.enable_reg = 0x33034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(342850000, P_GPLL4, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x2e004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.flags = CLK_IS_CRITICAL,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_q6ss_boot_clk = {
.halt_reg = 0x25080,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x25080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_boot_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_snoc_clk = {
.halt_reg = 0x17028,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_snoc_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_snoc_1_clk = {
.halt_reg = 0x1707c,
.clkr = {
.enable_reg = 0x1707c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_snoc_1_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_etr_usb_clk = {
.halt_reg = 0x2d060,
.clkr = {
.enable_reg = 0x2d060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_etr_usb_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 wcss_ahb_clk_src = {
.cmd_rcgr = 0x25030,
.freq_tbl = ftbl_wcss_ahb_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "wcss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_q6_ahb_clk = {
.halt_reg = 0x25014,
.clkr = {
.enable_reg = 0x25014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_ahb_s_clk = {
.halt_reg = 0x25018,
.clkr = {
.enable_reg = 0x25018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_ahb_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_ecahb_clk = {
.halt_reg = 0x25058,
.clkr = {
.enable_reg = 0x25058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_ecahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_acmt_clk = {
.halt_reg = 0x2505c,
.clkr = {
.enable_reg = 0x2505c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_acmt_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
.halt_reg = 0x2e030,
.clkr = {
.enable_reg = 0x2e030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_wcss_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 wcss_axi_m_clk_src = {
.cmd_rcgr = 0x25078,
.freq_tbl = ftbl_wcss_axi_m_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "wcss_axi_m_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
.halt_reg = 0x2e0a8,
.clkr = {
.enable_reg = 0x2e0a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_anoc_wcss_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_axi_m_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static struct clk_rcg2 qdss_at_clk_src = {
.cmd_rcgr = 0x2d004,
.freq_tbl = ftbl_qdss_at_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "qdss_at_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_q6ss_atbm_clk = {
.halt_reg = 0x2501c,
.clkr = {
.enable_reg = 0x2501c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_atbm_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
.halt_reg = 0x2503c,
.clkr = {
.enable_reg = 0x2503c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_atb_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_atb_clk = {
.halt_reg = 0x17014,
.clkr = {
.enable_reg = 0x17014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_atb_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_at_clk = {
.halt_reg = 0x2d038,
.clkr = {
.enable_reg = 0x2d038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_at_clk = {
.halt_reg = 0x2e038,
.clkr = {
.enable_reg = 0x2e038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcnoc_at_clk = {
.halt_reg = 0x31024,
.clkr = {
.enable_reg = 0x31024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcnoc_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
.mult = 1,
.div = 6,
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eud_at_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_usb0_eud_at_clk = {
.halt_reg = 0x30004,
.clkr = {
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_eud_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_eud_at_div_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_eud_at_clk = {
.halt_reg = 0x2d06c,
.clkr = {
.enable_reg = 0x2d06c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_eud_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_eud_at_div_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 qdss_stm_clk_src = {
.cmd_rcgr = 0x2d00c,
.freq_tbl = ftbl_qdss_stm_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "qdss_stm_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_qdss_stm_clk = {
.halt_reg = 0x2d03c,
.clkr = {
.enable_reg = 0x2d03c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_stm_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_stm_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
.halt_reg = 0x2e034,
.clkr = {
.enable_reg = 0x2e034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_qdss_stm_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_stm_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
F(300000000, P_GPLL4, 4, 0, 0),
{ }
};
static struct clk_rcg2 qdss_traceclkin_clk_src = {
.cmd_rcgr = 0x2d014,
.freq_tbl = ftbl_qdss_traceclkin_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "qdss_traceclkin_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_qdss_traceclkin_clk = {
.halt_reg = 0x2d040,
.clkr = {
.enable_reg = 0x2d040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_traceclkin_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_traceclkin_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
F(600000000, P_GPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 qdss_tsctr_clk_src = {
.cmd_rcgr = 0x2d01c,
.freq_tbl = ftbl_qdss_tsctr_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "qdss_tsctr_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
.mult = 1,
.div = 2,
.hw.init = &(const struct clk_init_data) {
.name = "qdss_tsctr_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_q6_tsctr_1to2_clk = {
.halt_reg = 0x25020,
.clkr = {
.enable_reg = 0x25020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_tsctr_1to2_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div2_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
.halt_reg = 0x25040,
.clkr = {
.enable_reg = 0x25040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_nts_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div2_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_tsctr_div2_clk = {
.halt_reg = 0x2d044,
.clkr = {
.enable_reg = 0x2d044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div2_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div2_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 uniphy_sys_clk_src = {
.cmd_rcgr = 0x17090,
.freq_tbl = ftbl_uniphy_sys_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "uniphy_sys_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_ts_clk_src = {
.cmd_rcgr = 0x17088,
.freq_tbl = ftbl_uniphy_sys_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "nss_ts_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_qdss_ts_clk = {
.halt_reg = 0x2d078,
.clkr = {
.enable_reg = 0x2d078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_ts_clk",
.parent_hws = (const struct clk_hw *[]) {
&nss_ts_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor qdss_dap_sync_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(const struct clk_init_data) {
.name = "qdss_dap_sync_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_qdss_tsctr_div4_clk = {
.halt_reg = 0x2d04c,
.clkr = {
.enable_reg = 0x2d04c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div4_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
.mult = 1,
.div = 8,
.hw.init = &(const struct clk_init_data) {
.name = "qdss_tsctr_div8_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_nss_ts_clk = {
.halt_reg = 0x17018,
.clkr = {
.enable_reg = 0x17018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nss_ts_clk",
.parent_hws = (const struct clk_hw *[]) {
&nss_ts_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_tsctr_div8_clk = {
.halt_reg = 0x2d050,
.clkr = {
.enable_reg = 0x2d050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div8_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div8_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
.mult = 1,
.div = 16,
.hw.init = &(const struct clk_init_data) {
.name = "qdss_tsctr_div16_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_qdss_tsctr_div16_clk = {
.halt_reg = 0x2d054,
.clkr = {
.enable_reg = 0x2d054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div16_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div16_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_pclkdbg_clk = {
.halt_reg = 0x25024,
.clkr = {
.enable_reg = 0x25024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_pclkdbg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_trig_clk = {
.halt_reg = 0x25068,
.clkr = {
.enable_reg = 0x25068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_trig_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
.halt_reg = 0x25038,
.clkr = {
.enable_reg = 0x25038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_apb_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
.halt_reg = 0x25044,
.clkr = {
.enable_reg = 0x25044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_dapbus_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x2d058,
.clkr = {
.enable_reg = 0x2d058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_dap_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_apb2jtag_clk = {
.halt_reg = 0x2d05c,
.clkr = {
.enable_reg = 0x2d05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_apb2jtag_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
.mult = 1,
.div = 3,
.hw.init = &(const struct clk_init_data) {
.name = "qdss_tsctr_div3_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_qdss_tsctr_div3_clk = {
.halt_reg = 0x2d048,
.clkr = {
.enable_reg = 0x2d048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div3_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div3_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 qpic_io_macro_clk_src = {
.cmd_rcgr = 0x32004,
.freq_tbl = ftbl_qpic_io_macro_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "qpic_io_macro_clk_src",
.parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_qpic_io_macro_clk = {
.halt_reg = 0x3200c,
.clkr = {
.enable_reg = 0x3200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qpic_io_macro_clk",
.parent_hws = (const struct clk_hw *[]){
&qpic_io_macro_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
F(533333333, P_GPLL0, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 q6_axi_clk_src = {
.cmd_rcgr = 0x25004,
.freq_tbl = ftbl_q6_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "q6_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_q6_axim_clk = {
.halt_reg = 0x2500c,
.clkr = {
.enable_reg = 0x2500c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_axim_clk",
.parent_hws = (const struct clk_hw *[]) {
&q6_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_q6_tbu_clk = {
.halt_reg = 0x12050,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb00c,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_q6_tbu_clk",
.parent_hws = (const struct clk_hw *[]) {
&q6_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mem_noc_q6_axi_clk = {
.halt_reg = 0x19010,
.clkr = {
.enable_reg = 0x19010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_mem_noc_q6_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&q6_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
F(342857143, P_GPLL4, 3.5, 0, 0),
{ }
};
static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
{ P_BIAS_PLL_UBI_NC_CLK, 4 },
};
static struct clk_rcg2 q6_axim2_clk_src = {
.cmd_rcgr = 0x25028,
.freq_tbl = ftbl_q6_axim2_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "q6_axim2_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
F(533333333, P_GPLL0, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x17004,
.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "nssnoc_memnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_nssnoc_memnoc_clk = {
.halt_reg = 0x17024,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_memnoc_clk",
.parent_hws = (const struct clk_hw *[]) {
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
.halt_reg = 0x17084,
.clkr = {
.enable_reg = 0x17084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_mem_noc_1_clk",
.parent_hws = (const struct clk_hw *[]) {
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_tbu_clk = {
.halt_reg = 0x12040,
.clkr = {
.enable_reg = 0xb00c,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nss_tbu_clk",
.parent_hws = (const struct clk_hw *[]) {
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mem_noc_nssnoc_clk = {
.halt_reg = 0x19014,
.clkr = {
.enable_reg = 0x19014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_mem_noc_nssnoc_clk",
.parent_hws = (const struct clk_hw *[]) {
&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
F(133333333, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 lpass_axim_clk_src = {
.cmd_rcgr = 0x2700c,
.freq_tbl = ftbl_lpass_axim_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_axim_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpass_sway_clk_src = {
.cmd_rcgr = 0x27004,
.freq_tbl = ftbl_lpass_axim_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_sway_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 adss_pwm_clk_src = {
.cmd_rcgr = 0x1c004,
.freq_tbl = ftbl_adss_pwm_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "adss_pwm_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_adss_pwm_clk = {
.halt_reg = 0x1c00c,
.clkr = {
.enable_reg = 0x1c00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_adss_pwm_clk",
.parent_hws = (const struct clk_hw *[]) {
&adss_pwm_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x8004,
.freq_tbl = ftbl_gp1_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x9004,
.freq_tbl = ftbl_gp1_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0xa004,
.freq_tbl = ftbl_gp1_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_xo_clk_src = {
.halt_reg = 0x34004,
.clkr = {
.enable_reg = 0x34004,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
.halt_reg = 0x17074,
.clkr = {
.enable_reg = 0x17074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_xo_dcd_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_clk = {
.halt_reg = 0x34018,
.clkr = {
.enable_reg = 0x34018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_sys_clk = {
.halt_reg = 0x17048,
.clkr = {
.enable_reg = 0x17048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy0_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&uniphy_sys_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_sys_clk = {
.halt_reg = 0x17058,
.clkr = {
.enable_reg = 0x17058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy1_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&uniphy_sys_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy2_sys_clk = {
.halt_reg = 0x17068,
.clkr = {
.enable_reg = 0x17068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy2_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&uniphy_sys_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_sys_clk = {
.halt_reg = 0x3a008,
.clkr = {
.enable_reg = 0x3a008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cmn_12gpll_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&uniphy_sys_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
.halt_reg = 0x1701c,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_qosgen_ref_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_div4_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
.halt_reg = 0x17020,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_timeout_ref_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_div4_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_div4_clk = {
.halt_reg = 0x3401c,
.clkr = {
.enable_reg = 0x3401c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_div4_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_div4_clk_src.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *gcc_ipq9574_hws[] = {
&gpll0_out_main_div2.hw,
&gcc_xo_div4_clk_src.hw,
&qdss_dap_sync_clk_src.hw,
&qdss_tsctr_div2_clk_src.hw,
&qdss_tsctr_div8_clk_src.hw,
&qdss_tsctr_div16_clk_src.hw,
&qdss_tsctr_div3_clk_src.hw,
&gcc_eud_at_div_clk_src.hw,
};
static struct clk_regmap *gcc_ipq9574_clks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL4_MAIN] = &gpll4_main.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL2_MAIN] = &gpll2_main.clkr,
[GPLL2] = &gpll2.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
[GCC_XO_CLK] = &gcc_xo_clk.clkr,
[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
[GCC_ADSS_BCR] = { 0x1c000, 0 },
[GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
[GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
[GCC_ANOC_BCR] = { 0x2e074, 0 },
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
[GCC_BLSP1_BCR] = { 0x01000, 0 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
[GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
[GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
[GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
[GCC_CRYPTO_BCR] = { 0x16000, 0 },
[GCC_DCC_BCR] = { 0x35000, 0 },
[GCC_DDRSS_BCR] = { 0x11000, 0 },
[GCC_IMEM_BCR] = { 0x0e000, 0 },
[GCC_LPASS_BCR] = { 0x27000, 0 },
[GCC_MDIO_BCR] = { 0x1703c, 0 },
[GCC_MPM_BCR] = { 0x37000, 0 },
[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
[GCC_NSS_BCR] = { 0x17000, 0 },
[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 },
[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 },
[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
[GCC_NSSCC_ARES] = { 0x17038, 8 },
[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
[GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
[GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
[GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
[GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
[GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
[GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
[GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
[GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
[GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
[GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
[GCC_PCIE0_BCR] = { 0x28000, 0 },
[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
[GCC_PCIE1_BCR] = { 0x29000, 0 },
[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
[GCC_PCIE2_BCR] = { 0x2a000, 0 },
[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
[GCC_PCIE3_BCR] = { 0x2b000, 0 },
[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
[GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
[GCC_PCNOC_BCR] = { 0x31000, 0 },
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
[GCC_PRNG_BCR] = { 0x13020, 0 },
[GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
[GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
[GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
[GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
[GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
[GCC_QDSS_BCR] = { 0x2d000, 0 },
[GCC_QPIC_BCR] = { 0x32000, 0 },
[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
[GCC_QPIC_ARES] = { 0x3201c, 0 },
[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
[GCC_RBCPR_BCR] = { 0x39000, 0 },
[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
[GCC_SDCC_BCR] = { 0x33000, 0 },
[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
[GCC_SNOC_BCR] = { 0x2e000, 0 },
[GCC_SPDM_BCR] = { 0x36000, 0 },
[GCC_TCSR_BCR] = { 0x3d000, 0 },
[GCC_TLMM_BCR] = { 0x3e000, 0 },
[GCC_TME_BCR] = { 0x10000, 0 },
[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
[GCC_USB_BCR] = { 0x2c000, 0 },
[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
[GCC_WCSSAON_RESET] = { 0x25074, 0 },
[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
[GCC_WCSS_BCR] = { 0x18004, 0 },
[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
};
static const struct of_device_id gcc_ipq9574_match_table[] = {
{ .compatible = "qcom,ipq9574-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
static const struct regmap_config gcc_ipq9574_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x7fffc,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_ipq9574_desc = {
.config = &gcc_ipq9574_regmap_config,
.clks = gcc_ipq9574_clks,
.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
.resets = gcc_ipq9574_resets,
.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
.clk_hws = gcc_ipq9574_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
};
static int gcc_ipq9574_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
}
static struct platform_driver gcc_ipq9574_driver = {
.probe = gcc_ipq9574_probe,
.driver = {
.name = "qcom,gcc-ipq9574",
.of_match_table = gcc_ipq9574_match_table,
},
};
static int __init gcc_ipq9574_init(void)
{
return platform_driver_register(&gcc_ipq9574_driver);
}
core_initcall(gcc_ipq9574_init);
static void __exit gcc_ipq9574_exit(void)
{
platform_driver_unregister(&gcc_ipq9574_driver);
}
module_exit(gcc_ipq9574_exit);
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-ipq9574.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL0_EARLY_DIV,
P_SLEEP_CLK,
P_GPLL4,
P_AUD_REF_CLK,
};
static struct clk_fixed_factor xo = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "xo",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0x00000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll0_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_early_div",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static struct clk_branch gcc_mmss_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_div_clk",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_gpll0_div_clk",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops
},
},
};
static struct clk_alpha_pll gpll4_early = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_hws = (const struct clk_hw*[]){
&gpll4_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gcc_sleep_clk_map[] = {
{ P_SLEEP_CLK, 5 }
};
static const struct clk_parent_data gcc_sleep_clk[] = {
{ .fw_name = "sleep_clk", .name = "sleep_clk" }
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .hw = &gpll0.clkr.hw }
};
static const struct parent_map gcc_xo_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 5 }
};
static const struct clk_parent_data gcc_xo_sleep_clk[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" }
};
static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_EARLY_DIV, 6 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw }
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw }
};
static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_AUD_REF_CLK, 2 }
};
static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
};
static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_EARLY_DIV, 6 }
};
static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .hw = &gpll0_early_div.hw }
};
static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 },
{ P_GPLL0_EARLY_DIV, 6 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
{ .fw_name = "cxo", .name = "xo_board" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_early_div.hw }
};
static const struct freq_tbl ftbl_system_noc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 system_noc_clk_src = {
.cmd_rcgr = 0x0401c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_system_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_config_noc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 config_noc_clk_src = {
.cmd_rcgr = 0x0500c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_config_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "config_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 periph_noc_clk_src = {
.cmd_rcgr = 0x06014,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_periph_noc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "periph_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(120000000, P_GPLL0, 5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x0f014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x0f028,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
F(1200000, P_XO, 16, 0, 0),
{ }
};
static struct clk_rcg2 usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x5000c,
.hid_width = 5,
.parent_map = gcc_xo_sleep_clk_map,
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_data = gcc_xo_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
F(120000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 usb20_master_clk_src = {
.cmd_rcgr = 0x12010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_usb20_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_master_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb20_mock_utmi_clk_src = {
.cmd_rcgr = 0x12024,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(96000000, P_GPLL4, 4, 0, 0),
F(192000000, P_GPLL4, 2, 0, 0),
F(384000000, P_GPLL4, 1, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x13010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
.ops = &clk_rcg2_floor_ops,
},
};
static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x13024,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x14010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc3_apps_clk_src = {
.cmd_rcgr = 0x15010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 sdcc4_apps_clk_src = {
.cmd_rcgr = 0x16010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x1900c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x19020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 96, 15625),
F(7372800, P_GPLL0, 1, 192, 15625),
F(14745600, P_GPLL0, 1, 384, 15625),
F(16000000, P_GPLL0, 5, 2, 15),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_GPLL0, 1, 4, 75),
F(40000000, P_GPLL0, 15, 0, 0),
F(46400000, P_GPLL0, 1, 29, 375),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(51200000, P_GPLL0, 1, 32, 375),
F(56000000, P_GPLL0, 1, 7, 75),
F(58982400, P_GPLL0, 1, 1536, 15625),
F(60000000, P_GPLL0, 10, 0, 0),
F(63157895, P_GPLL0, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x1a00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x1b00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x1b020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x1c00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x1d00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x1d020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x1f00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x1f020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x2000c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x2100c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x21020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x2200c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x2300c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x23020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x2400c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x26020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x2700c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x2800c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x28020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x2900c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x2a00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x2a020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.cmd_rcgr = 0x2b00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x2c00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x2c020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.cmd_rcgr = 0x2d00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x2e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x2e020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.cmd_rcgr = 0x2f00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x3000c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x30020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.cmd_rcgr = 0x3100c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
F(105495, P_XO, 1, 1, 182),
{ }
};
static struct clk_rcg2 tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_aud_ref_clk_map,
.freq_tbl = ftbl_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
.parent_data = gcc_xo_gpll0_aud_ref_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_sleep_clk_src = {
.cmd_rcgr = 0x43014,
.hid_width = 5,
.parent_map = gcc_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sleep_clk_src",
.parent_data = gcc_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 hmss_rbcpr_clk_src = {
.cmd_rcgr = 0x48040,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_rbcpr_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 hmss_gpll0_clk_src = {
.cmd_rcgr = 0x48058,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_gpll0_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(1010526, P_XO, 1, 1, 19),
{ }
};
static struct clk_rcg2 pcie_aux_clk_src = {
.cmd_rcgr = 0x6c000,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_sleep_clk_map,
.freq_tbl = ftbl_pcie_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_aux_clk_src",
.parent_data = gcc_xo_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 ufs_axi_clk_src = {
.cmd_rcgr = 0x75024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_ufs_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 ufs_ice_core_clk_src = {
.cmd_rcgr = 0x76014,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_ufs_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_ice_core_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(256000000, P_GPLL4, 1.5, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 qspi_ser_clk_src = {
.cmd_rcgr = 0x8b00c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
.freq_tbl = ftbl_qspi_ser_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "qspi_ser_clk_src",
.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
.halt_reg = 0x0f03c,
.clkr = {
.enable_reg = 0x0f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
.halt_reg = 0x75038,
.clkr = {
.enable_reg = 0x75038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
.halt_reg = 0x6010,
.clkr = {
.enable_reg = 0x6010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_periph_noc_usb20_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.halt_reg = 0x9008,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_noc_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_bimc_gfx_clk = {
.halt_reg = 0x9010,
.clkr = {
.enable_reg = 0x9010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_bimc_gfx_clk",
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x0f008,
.clkr = {
.enable_reg = 0x0f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x0f00c,
.clkr = {
.enable_reg = 0x0f00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x0f010,
.clkr = {
.enable_reg = 0x0f010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x50000,
.clkr = {
.enable_reg = 0x50000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x12004,
.clkr = {
.enable_reg = 0x12004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_master_clk",
.parent_hws = (const struct clk_hw*[]){
&usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_sleep_clk = {
.halt_reg = 0x12008,
.clkr = {
.enable_reg = 0x12008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_mock_utmi_clk = {
.halt_reg = 0x1200c,
.clkr = {
.enable_reg = 0x1200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x13004,
.clkr = {
.enable_reg = 0x13004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x13008,
.clkr = {
.enable_reg = 0x13008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x13038,
.clkr = {
.enable_reg = 0x13038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_apps_clk = {
.halt_reg = 0x15004,
.clkr = {
.enable_reg = 0x15004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_ahb_clk = {
.halt_reg = 0x15008,
.clkr = {
.enable_reg = 0x15008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x19004,
.clkr = {
.enable_reg = 0x19004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x19008,
.clkr = {
.enable_reg = 0x19008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x1a004,
.clkr = {
.enable_reg = 0x1a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x1b004,
.clkr = {
.enable_reg = 0x1b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x1b008,
.clkr = {
.enable_reg = 0x1b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x1c004,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x1d004,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x1d008,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x1e004,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x1f004,
.clkr = {
.enable_reg = 0x1f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x1f008,
.clkr = {
.enable_reg = 0x1f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x20004,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x21004,
.clkr = {
.enable_reg = 0x21004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x21008,
.clkr = {
.enable_reg = 0x21008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x22004,
.clkr = {
.enable_reg = 0x22004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x23004,
.clkr = {
.enable_reg = 0x23004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x23008,
.clkr = {
.enable_reg = 0x23008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x24004,
.clkr = {
.enable_reg = 0x24004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x25004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_sleep_clk = {
.halt_reg = 0x25008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x26004,
.clkr = {
.enable_reg = 0x26004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x26008,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x27004,
.clkr = {
.enable_reg = 0x27004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x28004,
.clkr = {
.enable_reg = 0x28004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x28008,
.clkr = {
.enable_reg = 0x28008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x29004,
.clkr = {
.enable_reg = 0x29004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x2a004,
.clkr = {
.enable_reg = 0x2a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x2a008,
.clkr = {
.enable_reg = 0x2a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.halt_reg = 0x2b004,
.clkr = {
.enable_reg = 0x2b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x2c004,
.clkr = {
.enable_reg = 0x2c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x2c008,
.clkr = {
.enable_reg = 0x2c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart4_apps_clk = {
.halt_reg = 0x2d004,
.clkr = {
.enable_reg = 0x2d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.halt_reg = 0x2e004,
.clkr = {
.enable_reg = 0x2e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.halt_reg = 0x2e008,
.clkr = {
.enable_reg = 0x2e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart5_apps_clk = {
.halt_reg = 0x2f004,
.clkr = {
.enable_reg = 0x2f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.halt_reg = 0x30004,
.clkr = {
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.halt_reg = 0x30008,
.clkr = {
.enable_reg = 0x30008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart6_apps_clk = {
.halt_reg = 0x31004,
.clkr = {
.enable_reg = 0x31004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x46018,
.clkr = {
.enable_reg = 0x46018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_rbcpr_clk = {
.halt_reg = 0x4800c,
.clkr = {
.enable_reg = 0x4800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&hmss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b008,
.clkr = {
.enable_reg = 0x6b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b00c,
.clkr = {
.enable_reg = 0x6b00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b010,
.clkr = {
.enable_reg = 0x6b010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b014,
.clkr = {
.enable_reg = 0x6b014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6b018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x6d008,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x6d00c,
.clkr = {
.enable_reg = 0x6d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x6d010,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x6d014,
.clkr = {
.enable_reg = 0x6d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x6d018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6d018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_axi_clk = {
.halt_reg = 0x6e008,
.clkr = {
.enable_reg = 0x6e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
.halt_reg = 0x6e00c,
.clkr = {
.enable_reg = 0x6e00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
.halt_reg = 0x6e010,
.clkr = {
.enable_reg = 0x6e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_aux_clk = {
.halt_reg = 0x6e014,
.clkr = {
.enable_reg = 0x6e014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x6e018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x6e018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
.halt_reg = 0x6f004,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f008,
.clkr = {
.enable_reg = 0x6f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_axi_clk = {
.halt_reg = 0x75008,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ahb_clk = {
.halt_reg = 0x7500c,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
.mult = 1,
.div = 16,
.hw.init = &(struct clk_init_data){
.name = "ufs_tx_cfg_clk_src",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_ufs_tx_cfg_clk = {
.halt_reg = 0x75010,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_cfg_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_tx_cfg_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
.mult = 1,
.div = 16,
.hw.init = &(struct clk_init_data){
.name = "ufs_rx_cfg_clk_src",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
.halt_reg = 0x7d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "hlos1_vote_lpass_core_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
.halt_reg = 0x7d014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "hlos1_vote_lpass_adsp_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_cfg_clk = {
.halt_reg = 0x75014,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_cfg_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_rx_cfg_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.halt_reg = 0x7501c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.halt_reg = 0x75020,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "ufs_ice_core_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&ufs_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_ufs_unipro_core_clk = {
.halt_reg = 0x7600c,
.clkr = {
.enable_reg = 0x7600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_ice_core_postdiv_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ice_core_clk = {
.halt_reg = 0x76010,
.clkr = {
.enable_reg = 0x76010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_sys_clk_core_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x76030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_sys_clk_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x76034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_clk_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre0_snoc_axi_clk = {
.halt_reg = 0x81008,
.clkr = {
.enable_reg = 0x81008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_snoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
.halt_reg = 0x8100c,
.clkr = {
.enable_reg = 0x8100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_cnoc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_aggre0_axi_clk = {
.halt_reg = 0x81014,
.clkr = {
.enable_reg = 0x81014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_aggre0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
.halt_reg = 0x81018,
.clkr = {
.enable_reg = 0x81018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_aggre0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre2_ufs_axi_clk = {
.halt_reg = 0x83014,
.clkr = {
.enable_reg = 0x83014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre2_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre2_usb3_axi_clk = {
.halt_reg = 0x83018,
.clkr = {
.enable_reg = 0x83018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre2_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_ahb_clk = {
.halt_reg = 0x84004,
.clkr = {
.enable_reg = 0x84004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
.halt_reg = 0x85000,
.clkr = {
.enable_reg = 0x85000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_ahb_clk = {
.halt_reg = 0x8b004,
.clkr = {
.enable_reg = 0x8b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_ser_clk = {
.halt_reg = 0x8b008,
.clkr = {
.enable_reg = 0x8b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_ser_clk",
.parent_hws = (const struct clk_hw*[]){
&qspi_ser_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_clkref_clk = {
.halt_reg = 0x8800C,
.clkr = {
.enable_reg = 0x8800C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hdmi_clkref_clk = {
.halt_reg = 0x88000,
.clkr = {
.enable_reg = 0x88000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hdmi_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_edp_clkref_clk = {
.halt_reg = 0x88004,
.clkr = {
.enable_reg = 0x88004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_edp_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_clkref_clk = {
.halt_reg = 0x88008,
.clkr = {
.enable_reg = 0x88008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_clkref_clk = {
.halt_reg = 0x88010,
.clkr = {
.enable_reg = 0x88010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx2_usb2_clkref_clk = {
.halt_reg = 0x88014,
.clkr = {
.enable_reg = 0x88014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx2_usb2_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx1_usb2_clkref_clk = {
.halt_reg = 0x88018,
.clkr = {
.enable_reg = 0x88018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx1_usb2_clkref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
.halt_reg = 0x8a004,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mnoc_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a024,
.clkr = {
.enable_reg = 0x8a024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x8a028,
.clkr = {
.enable_reg = 0x8a028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *gcc_msm8996_hws[] = {
&xo.hw,
&gpll0_early_div.hw,
&ufs_tx_cfg_clk_src.hw,
&ufs_rx_cfg_clk_src.hw,
&ufs_ice_core_postdiv_clk_src.hw,
};
static struct gdsc aggre0_noc_gdsc = {
.gdscr = 0x81004,
.gds_hw_ctrl = 0x81028,
.pd = {
.name = "aggre0_noc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | ALWAYS_ON,
};
static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
.gdscr = 0x7d024,
.pd = {
.name = "hlos1_vote_aggre0_noc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
.gdscr = 0x7d034,
.pd = {
.name = "hlos1_vote_lpass_adsp",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_lpass_core_gdsc = {
.gdscr = 0x7d038,
.pd = {
.name = "hlos1_vote_lpass_core",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc usb30_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30",
},
/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc pcie0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie1_gdsc = {
.gdscr = 0x6d004,
.pd = {
.name = "pcie1",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie2_gdsc = {
.gdscr = 0x6e004,
.pd = {
.name = "pcie2",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8996_clocks[] = {
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL4] = &gpll4.clkr,
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
[USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
[USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
[UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
[QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
[GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
[GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
[GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
[GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
[GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
[GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
[GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
[GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
[GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
[GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
[GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
[GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
[GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
[GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
[GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
};
static struct gdsc *gcc_msm8996_gdscs[] = {
[AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
[HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
[HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
[HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
[USB30_GDSC] = &usb30_gdsc,
[PCIE0_GDSC] = &pcie0_gdsc,
[PCIE1_GDSC] = &pcie1_gdsc,
[PCIE2_GDSC] = &pcie2_gdsc,
[UFS_GDSC] = &ufs_gdsc,
};
static const struct qcom_reset_map gcc_msm8996_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x4000 },
[GCC_CONFIG_NOC_BCR] = { 0x5000 },
[GCC_PERIPH_NOC_BCR] = { 0x6000 },
[GCC_IMEM_BCR] = { 0x8000 },
[GCC_MMSS_BCR] = { 0x9000 },
[GCC_PIMEM_BCR] = { 0x0a000 },
[GCC_QDSS_BCR] = { 0x0c000 },
[GCC_USB_30_BCR] = { 0x0f000 },
[GCC_USB_20_BCR] = { 0x12000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
[GCC_USB3_PHY_BCR] = { 0x50020 },
[GCC_USB3PHY_PHY_BCR] = { 0x50024 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_SDCC1_BCR] = { 0x13000 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC3_BCR] = { 0x15000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_BLSP1_BCR] = { 0x17000 },
[GCC_BLSP1_QUP1_BCR] = { 0x19000 },
[GCC_BLSP1_UART1_BCR] = { 0x1a000 },
[GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
[GCC_BLSP1_UART2_BCR] = { 0x1c000 },
[GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
[GCC_BLSP1_UART3_BCR] = { 0x1e000 },
[GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
[GCC_BLSP1_UART4_BCR] = { 0x20000 },
[GCC_BLSP1_QUP5_BCR] = { 0x21000 },
[GCC_BLSP1_UART5_BCR] = { 0x22000 },
[GCC_BLSP1_QUP6_BCR] = { 0x23000 },
[GCC_BLSP1_UART6_BCR] = { 0x24000 },
[GCC_BLSP2_BCR] = { 0x25000 },
[GCC_BLSP2_QUP1_BCR] = { 0x26000 },
[GCC_BLSP2_UART1_BCR] = { 0x27000 },
[GCC_BLSP2_QUP2_BCR] = { 0x28000 },
[GCC_BLSP2_UART2_BCR] = { 0x29000 },
[GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
[GCC_BLSP2_UART3_BCR] = { 0x2b000 },
[GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
[GCC_BLSP2_UART4_BCR] = { 0x2d000 },
[GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
[GCC_BLSP2_UART5_BCR] = { 0x2f000 },
[GCC_BLSP2_QUP6_BCR] = { 0x30000 },
[GCC_BLSP2_UART6_BCR] = { 0x31000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_TCSR_BCR] = { 0x37000 },
[GCC_BOOT_ROM_BCR] = { 0x38000 },
[GCC_MSG_RAM_BCR] = { 0x39000 },
[GCC_TLMM_BCR] = { 0x3a000 },
[GCC_MPM_BCR] = { 0x3b000 },
[GCC_SEC_CTRL_BCR] = { 0x3d000 },
[GCC_SPMI_BCR] = { 0x3f000 },
[GCC_SPDM_BCR] = { 0x40000 },
[GCC_CE1_BCR] = { 0x41000 },
[GCC_BIMC_BCR] = { 0x44000 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
[GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
[GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
[GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
[GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
[GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
[GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
[GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
[GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
[GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
[GCC_APB2JTAG_BCR] = { 0x4c000 },
[GCC_RBCPR_CX_BCR] = { 0x4e000 },
[GCC_RBCPR_MX_BCR] = { 0x4f000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_1_BCR] = { 0x6d000 },
[GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
[GCC_PCIE_2_BCR] = { 0x6e000 },
[GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
[GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
[GCC_DCD_BCR] = { 0x70000 },
[GCC_OBT_ODT_BCR] = { 0x73000 },
[GCC_UFS_BCR] = { 0x75000 },
[GCC_SSC_BCR] = { 0x63000 },
[GCC_VS_BCR] = { 0x7a000 },
[GCC_AGGRE0_NOC_BCR] = { 0x81000 },
[GCC_AGGRE1_NOC_BCR] = { 0x82000 },
[GCC_AGGRE2_NOC_BCR] = { 0x83000 },
[GCC_DCC_BCR] = { 0x84000 },
[GCC_IPA_BCR] = { 0x89000 },
[GCC_QSPI_BCR] = { 0x8b000 },
[GCC_SKL_BCR] = { 0x8c000 },
[GCC_MSMPU_BCR] = { 0x8d000 },
[GCC_MSS_Q6_BCR] = { 0x8e000 },
[GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
[GCC_MSS_RESTART] = { 0x8f008 },
};
static const struct regmap_config gcc_msm8996_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8f010,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8996_desc = {
.config = &gcc_msm8996_regmap_config,
.clks = gcc_msm8996_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
.resets = gcc_msm8996_resets,
.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
.gdscs = gcc_msm8996_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
.clk_hws = gcc_msm8996_hws,
.num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
};
static const struct of_device_id gcc_msm8996_match_table[] = {
{ .compatible = "qcom,gcc-msm8996" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
static int gcc_msm8996_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
* turned off by hardware during certain apps low power modes.
*/
regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
}
static struct platform_driver gcc_msm8996_driver = {
.probe = gcc_msm8996_probe,
.driver = {
.name = "gcc-msm8996",
.of_match_table = gcc_msm8996_match_table,
},
};
static int __init gcc_msm8996_init(void)
{
return platform_driver_register(&gcc_msm8996_driver);
}
core_initcall(gcc_msm8996_init);
static void __exit gcc_msm8996_exit(void)
{
platform_driver_unregister(&gcc_msm8996_driver);
}
module_exit(gcc_msm8996_exit);
MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8996");
| linux-master | drivers/clk/qcom/gcc-msm8996.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN,
P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC,
P_LPASS_CORE_CC_DIG_PLL_OUT_ODD,
};
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 614.4MHz configuration */
static const struct alpha_pll_config lpass_core_cc_dig_pll_config = {
.l = 0x20,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0xB2923BBC,
.user_ctl_val = 0x00005100,
.user_ctl_hi_val = 0x00050805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll lpass_core_cc_dig_pll = {
.offset = 0x1000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "lpass_core_cc_dig_pll",
.parent_data = &(const struct clk_parent_data){
.index = 0,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_lpass_core_cc_dig_pll_out_odd[] = {
{ 0x5, 5 },
{ }
};
static struct clk_alpha_pll_postdiv lpass_core_cc_dig_pll_out_odd = {
.offset = 0x1000,
.post_div_shift = 12,
.post_div_table = post_div_table_lpass_core_cc_dig_pll_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_lpass_core_cc_dig_pll_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "lpass_core_cc_dig_pll_out_odd",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_dig_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_regmap_div lpass_core_cc_dig_pll_out_main_div_clk_src = {
.reg = 0x1054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "lpass_core_cc_dig_pll_out_main_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_dig_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static const struct parent_map lpass_core_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5 },
};
static const struct clk_parent_data lpass_core_cc_parent_data_0[] = {
{ .index = 0 },
{ .hw = &lpass_core_cc_dig_pll_out_odd.clkr.hw },
};
static const struct parent_map lpass_core_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 1 },
{ P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 2 },
};
static const struct clk_parent_data lpass_core_cc_parent_data_ao_2[] = {
{ .index = 1 },
{ .hw = &lpass_core_cc_dig_pll.clkr.hw },
{ .hw = &lpass_core_cc_dig_pll_out_main_div_clk_src.clkr.hw },
};
static const struct freq_tbl ftbl_lpass_core_cc_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(51200000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 6, 0, 0),
F(102400000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC, 3, 0, 0),
F(204800000, P_LPASS_CORE_CC_DIG_PLL_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 lpass_core_cc_core_clk_src = {
.cmd_rcgr = 0x1d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_2,
.freq_tbl = ftbl_lpass_core_cc_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_core_clk_src",
.parent_data = lpass_core_cc_parent_data_ao_2,
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_ao_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_lpass_core_cc_ext_if0_clk_src[] = {
F(256000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 32),
F(512000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 16),
F(768000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 16),
F(1024000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 8),
F(1536000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 8),
F(2048000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 4),
F(3072000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 4),
F(4096000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 1, 2),
F(6144000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 1, 2),
F(8192000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 15, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(12288000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 10, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24576000, P_LPASS_CORE_CC_DIG_PLL_OUT_ODD, 5, 0, 0),
{ }
};
static struct clk_rcg2 lpass_core_cc_ext_if0_clk_src = {
.cmd_rcgr = 0x10000,
.mnd_width = 16,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_if0_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
.cmd_rcgr = 0x11000,
.mnd_width = 16,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_if1_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
.cmd_rcgr = 0x20000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_core_cc_parent_map_0,
.freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_mclk0_clk_src",
.parent_data = lpass_core_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch lpass_core_cc_core_clk = {
.halt_reg = 0x1f000,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1f000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_core_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch lpass_core_cc_ext_if0_ibit_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_if0_ibit_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_ext_if0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_core_cc_ext_if1_ibit_clk = {
.halt_reg = 0x11018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_if1_ibit_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_ext_if1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_core_cc_lpm_core_clk = {
.halt_reg = 0x1e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_lpm_core_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_lpm_mem0_core_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
.halt_reg = 0x20014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_ext_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x23000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_core_cc_sysnoc_mport_core_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_core_cc_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc lpass_core_cc_lpass_core_hm_gdsc = {
.gdscr = 0x0,
.pd = {
.name = "lpass_core_cc_lpass_core_hm_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
[LPASS_CORE_CC_CORE_CLK] = &lpass_core_cc_core_clk.clkr,
[LPASS_CORE_CC_CORE_CLK_SRC] = &lpass_core_cc_core_clk_src.clkr,
[LPASS_CORE_CC_DIG_PLL] = &lpass_core_cc_dig_pll.clkr,
[LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC] =
&lpass_core_cc_dig_pll_out_main_div_clk_src.clkr,
[LPASS_CORE_CC_DIG_PLL_OUT_ODD] = &lpass_core_cc_dig_pll_out_odd.clkr,
[LPASS_CORE_CC_EXT_IF0_CLK_SRC] = &lpass_core_cc_ext_if0_clk_src.clkr,
[LPASS_CORE_CC_EXT_IF0_IBIT_CLK] = &lpass_core_cc_ext_if0_ibit_clk.clkr,
[LPASS_CORE_CC_EXT_IF1_CLK_SRC] = &lpass_core_cc_ext_if1_clk_src.clkr,
[LPASS_CORE_CC_EXT_IF1_IBIT_CLK] = &lpass_core_cc_ext_if1_ibit_clk.clkr,
[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
[LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
[LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
};
static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static const struct qcom_cc_desc lpass_core_cc_sc7280_desc = {
.config = &lpass_core_cc_sc7280_regmap_config,
.clks = lpass_core_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_core_cc_sc7280_clocks),
};
static const struct of_device_id lpass_core_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpasscorecc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7280_match_table);
static struct gdsc *lpass_core_hm_sc7280_gdscs[] = {
[LPASS_CORE_CC_LPASS_CORE_HM_GDSC] = &lpass_core_cc_lpass_core_hm_gdsc,
};
static const struct qcom_cc_desc lpass_core_hm_sc7280_desc = {
.config = &lpass_core_cc_sc7280_regmap_config,
.gdscs = lpass_core_hm_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7280_gdscs),
};
static int lpass_core_cc_sc7280_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
struct regmap *regmap;
lpass_core_cc_sc7280_regmap_config.name = "lpass_core_cc";
lpass_core_cc_sc7280_regmap_config.max_register = 0x4f004;
desc = &lpass_core_cc_sc7280_desc;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config);
return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap);
}
static struct platform_driver lpass_core_cc_sc7280_driver = {
.probe = lpass_core_cc_sc7280_probe,
.driver = {
.name = "lpass_core_cc-sc7280",
.of_match_table = lpass_core_cc_sc7280_match_table,
},
};
static int lpass_hm_core_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
lpass_core_cc_sc7280_regmap_config.name = "lpass_hm_core";
lpass_core_cc_sc7280_regmap_config.max_register = 0x24;
desc = &lpass_core_hm_sc7280_desc;
return qcom_cc_probe_by_index(pdev, 0, desc);
}
static const struct of_device_id lpass_hm_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpasshm" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_hm_sc7280_match_table);
static struct platform_driver lpass_hm_sc7280_driver = {
.probe = lpass_hm_core_probe,
.driver = {
.name = "lpass_hm-sc7280",
.of_match_table = lpass_hm_sc7280_match_table,
},
};
static int __init lpass_core_cc_sc7280_init(void)
{
int ret;
ret = platform_driver_register(&lpass_hm_sc7280_driver);
if (ret)
return ret;
return platform_driver_register(&lpass_core_cc_sc7280_driver);
}
subsys_initcall(lpass_core_cc_sc7280_init);
static void __exit lpass_core_cc_sc7280_exit(void)
{
platform_driver_unregister(&lpass_core_cc_sc7280_driver);
platform_driver_unregister(&lpass_hm_sc7280_driver);
}
module_exit(lpass_core_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/lpasscorecc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
static struct clk_branch lpass_q6ss_ahbm_aon_clk = {
.halt_reg = 0x12000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x12000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbm_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_q6ss_ahbs_aon_clk = {
.halt_reg = 0x1f000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x1f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbs_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_core_clk = {
.halt_reg = 0x20,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x20,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_xo_clk = {
.halt_reg = 0x38,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x38,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_qdsp6ss_sleep_clk = {
.halt_reg = 0x3c,
/* CLK_OFF would not toggle until LPASS is out of reset */
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_qdsp6ss_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct regmap_config lpass_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static struct clk_regmap *lpass_cc_sdm845_clocks[] = {
[LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr,
[LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr,
};
static const struct qcom_cc_desc lpass_cc_sdm845_desc = {
.config = &lpass_regmap_config,
.clks = lpass_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks),
};
static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = {
[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
};
static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
.config = &lpass_regmap_config,
.clks = lpass_qdsp6ss_sdm845_clocks,
.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
};
static int lpass_cc_sdm845_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
int ret;
lpass_regmap_config.name = "cc";
desc = &lpass_cc_sdm845_desc;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
return ret;
lpass_regmap_config.name = "qdsp6ss";
desc = &lpass_qdsp6ss_sdm845_desc;
return qcom_cc_probe_by_index(pdev, 1, desc);
}
static const struct of_device_id lpass_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-lpasscc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table);
static struct platform_driver lpass_cc_sdm845_driver = {
.probe = lpass_cc_sdm845_probe,
.driver = {
.name = "sdm845-lpasscc",
.of_match_table = lpass_cc_sdm845_match_table,
},
};
static int __init lpass_cc_sdm845_init(void)
{
return platform_driver_register(&lpass_cc_sdm845_driver);
}
subsys_initcall(lpass_cc_sdm845_init);
static void __exit lpass_cc_sdm845_exit(void)
{
platform_driver_unregister(&lpass_cc_sdm845_driver);
}
module_exit(lpass_cc_sdm845_exit);
MODULE_DESCRIPTION("QTI LPASS_CC SDM845 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/lpasscc-sdm845.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
static const struct clk_parent_data aux_parents[] = {
{ .fw_name = "pll8_vote", .name = "pll8_vote" },
{ .fw_name = "pxo", .name = "pxo_board" },
};
static const u32 aux_parent_map[] = {
3,
0,
};
static const struct of_device_id kpss_xcc_match_table[] = {
{ .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
{ .compatible = "qcom,kpss-gcc" },
{}
};
MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
static int kpss_xcc_driver_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *id;
void __iomem *base;
struct clk_hw *hw;
const char *name;
id = of_match_device(kpss_xcc_match_table, dev);
if (!id)
return -ENODEV;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
if (id->data) {
if (of_property_read_string_index(dev->of_node,
"clock-output-names",
0, &name))
return -ENODEV;
base += 0x14;
} else {
name = "acpu_l2_aux";
base += 0x28;
}
hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
ARRAY_SIZE(aux_parents), 0,
base, 0, 0x3,
0, aux_parent_map, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
return 0;
}
static struct platform_driver kpss_xcc_driver = {
.probe = kpss_xcc_driver_probe,
.driver = {
.name = "kpss-xcc",
.of_match_table = kpss_xcc_match_table,
},
};
module_platform_driver(kpss_xcc_driver);
MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:kpss-xcc");
| linux-master | drivers/clk/qcom/kpss-xcc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016, Linaro Limited
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/mfd/qcom_rpm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
#define QCOM_RPM_SCALING_ENABLE_ID 0x2
#define QCOM_RPM_XO_MODE_ON 0x2
static const struct clk_parent_data gcc_pxo[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
};
static const struct clk_parent_data gcc_cxo[] = {
{ .fw_name = "cxo", .name = "cxo_board" },
};
#define DEFINE_CLK_RPM(_name, r_id) \
static struct clk_rpm clk_rpm_##_name##_a_clk; \
static struct clk_rpm clk_rpm_##_name##_clk = { \
.rpm_clk_id = (r_id), \
.peer = &clk_rpm_##_name##_a_clk, \
.rate = INT_MAX, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_ops, \
.name = #_name "_clk", \
.parent_data = gcc_pxo, \
.num_parents = ARRAY_SIZE(gcc_pxo), \
}, \
}; \
static struct clk_rpm clk_rpm_##_name##_a_clk = { \
.rpm_clk_id = (r_id), \
.peer = &clk_rpm_##_name##_clk, \
.active_only = true, \
.rate = INT_MAX, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_ops, \
.name = #_name "_a_clk", \
.parent_data = gcc_pxo, \
.num_parents = ARRAY_SIZE(gcc_pxo), \
}, \
}
#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \
static struct clk_rpm clk_rpm_##_name##_clk = { \
.rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
.xo_offset = (offset), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_xo_ops, \
.name = #_name "_clk", \
.parent_data = gcc_cxo, \
.num_parents = ARRAY_SIZE(gcc_cxo), \
}, \
}
#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \
static struct clk_rpm clk_rpm_##_name##_clk = { \
.rpm_clk_id = (r_id), \
.rate = (r), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_fixed_ops, \
.name = #_name "_clk", \
.parent_data = gcc_pxo, \
.num_parents = ARRAY_SIZE(gcc_pxo), \
}, \
}
#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
struct rpm_cc;
struct clk_rpm {
const int rpm_clk_id;
const int xo_offset;
const bool active_only;
unsigned long rate;
bool enabled;
bool branch;
struct clk_rpm *peer;
struct clk_hw hw;
struct qcom_rpm *rpm;
struct rpm_cc *rpm_cc;
};
struct rpm_cc {
struct qcom_rpm *rpm;
struct clk_rpm **clks;
size_t num_clks;
u32 xo_buffer_value;
struct mutex xo_lock;
};
struct rpm_clk_desc {
struct clk_rpm **clks;
size_t num_clks;
};
static DEFINE_MUTEX(rpm_clk_lock);
static int clk_rpm_handoff(struct clk_rpm *r)
{
int ret;
u32 value = INT_MAX;
/*
* The vendor tree simply reads the status for this
* RPM clock.
*/
if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
return 0;
ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
r->rpm_clk_id, &value, 1);
if (ret)
return ret;
ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
r->rpm_clk_id, &value, 1);
if (ret)
return ret;
return 0;
}
static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
{
u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
r->rpm_clk_id, &value, 1);
}
static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
{
u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
r->rpm_clk_id, &value, 1);
}
static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
unsigned long *active, unsigned long *sleep)
{
*active = rate;
/*
* Active-only clocks don't care what the rate is during sleep. So,
* they vote for zero.
*/
if (r->active_only)
*sleep = 0;
else
*sleep = *active;
}
static int clk_rpm_prepare(struct clk_hw *hw)
{
struct clk_rpm *r = to_clk_rpm(hw);
struct clk_rpm *peer = r->peer;
unsigned long this_rate = 0, this_sleep_rate = 0;
unsigned long peer_rate = 0, peer_sleep_rate = 0;
unsigned long active_rate, sleep_rate;
int ret = 0;
mutex_lock(&rpm_clk_lock);
/* Don't send requests to the RPM if the rate has not been set. */
if (!r->rate)
goto out;
to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
/* Take peer clock's rate into account only if it's enabled. */
if (peer->enabled)
to_active_sleep(peer, peer->rate,
&peer_rate, &peer_sleep_rate);
active_rate = max(this_rate, peer_rate);
if (r->branch)
active_rate = !!active_rate;
ret = clk_rpm_set_rate_active(r, active_rate);
if (ret)
goto out;
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
if (r->branch)
sleep_rate = !!sleep_rate;
ret = clk_rpm_set_rate_sleep(r, sleep_rate);
if (ret)
/* Undo the active set vote and restore it */
ret = clk_rpm_set_rate_active(r, peer_rate);
out:
if (!ret)
r->enabled = true;
mutex_unlock(&rpm_clk_lock);
return ret;
}
static void clk_rpm_unprepare(struct clk_hw *hw)
{
struct clk_rpm *r = to_clk_rpm(hw);
struct clk_rpm *peer = r->peer;
unsigned long peer_rate = 0, peer_sleep_rate = 0;
unsigned long active_rate, sleep_rate;
int ret;
mutex_lock(&rpm_clk_lock);
if (!r->rate)
goto out;
/* Take peer clock's rate into account only if it's enabled. */
if (peer->enabled)
to_active_sleep(peer, peer->rate, &peer_rate,
&peer_sleep_rate);
active_rate = r->branch ? !!peer_rate : peer_rate;
ret = clk_rpm_set_rate_active(r, active_rate);
if (ret)
goto out;
sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
ret = clk_rpm_set_rate_sleep(r, sleep_rate);
if (ret)
goto out;
r->enabled = false;
out:
mutex_unlock(&rpm_clk_lock);
}
static int clk_rpm_xo_prepare(struct clk_hw *hw)
{
struct clk_rpm *r = to_clk_rpm(hw);
struct rpm_cc *rcc = r->rpm_cc;
int ret, clk_id = r->rpm_clk_id;
u32 value;
mutex_lock(&rcc->xo_lock);
value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
if (!ret) {
r->enabled = true;
rcc->xo_buffer_value = value;
}
mutex_unlock(&rcc->xo_lock);
return ret;
}
static void clk_rpm_xo_unprepare(struct clk_hw *hw)
{
struct clk_rpm *r = to_clk_rpm(hw);
struct rpm_cc *rcc = r->rpm_cc;
int ret, clk_id = r->rpm_clk_id;
u32 value;
mutex_lock(&rcc->xo_lock);
value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
if (!ret) {
r->enabled = false;
rcc->xo_buffer_value = value;
}
mutex_unlock(&rcc->xo_lock);
}
static int clk_rpm_fixed_prepare(struct clk_hw *hw)
{
struct clk_rpm *r = to_clk_rpm(hw);
u32 value = 1;
int ret;
ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
r->rpm_clk_id, &value, 1);
if (!ret)
r->enabled = true;
return ret;
}
static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
{
struct clk_rpm *r = to_clk_rpm(hw);
u32 value = 0;
int ret;
ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
r->rpm_clk_id, &value, 1);
if (!ret)
r->enabled = false;
}
static int clk_rpm_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate)
{
struct clk_rpm *r = to_clk_rpm(hw);
struct clk_rpm *peer = r->peer;
unsigned long active_rate, sleep_rate;
unsigned long this_rate = 0, this_sleep_rate = 0;
unsigned long peer_rate = 0, peer_sleep_rate = 0;
int ret = 0;
mutex_lock(&rpm_clk_lock);
if (!r->enabled)
goto out;
to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
/* Take peer clock's rate into account only if it's enabled. */
if (peer->enabled)
to_active_sleep(peer, peer->rate,
&peer_rate, &peer_sleep_rate);
active_rate = max(this_rate, peer_rate);
ret = clk_rpm_set_rate_active(r, active_rate);
if (ret)
goto out;
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
ret = clk_rpm_set_rate_sleep(r, sleep_rate);
if (ret)
goto out;
r->rate = rate;
out:
mutex_unlock(&rpm_clk_lock);
return ret;
}
static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
/*
* RPM handles rate rounding and we don't have a way to
* know what the rate will be, so just return whatever
* rate is requested.
*/
return rate;
}
static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_rpm *r = to_clk_rpm(hw);
/*
* RPM handles rate rounding and we don't have a way to
* know what the rate will be, so just return whatever
* rate was set.
*/
return r->rate;
}
static const struct clk_ops clk_rpm_xo_ops = {
.prepare = clk_rpm_xo_prepare,
.unprepare = clk_rpm_xo_unprepare,
};
static const struct clk_ops clk_rpm_fixed_ops = {
.prepare = clk_rpm_fixed_prepare,
.unprepare = clk_rpm_fixed_unprepare,
.round_rate = clk_rpm_round_rate,
.recalc_rate = clk_rpm_recalc_rate,
};
static const struct clk_ops clk_rpm_ops = {
.prepare = clk_rpm_prepare,
.unprepare = clk_rpm_unprepare,
.set_rate = clk_rpm_set_rate,
.round_rate = clk_rpm_round_rate,
.recalc_rate = clk_rpm_recalc_rate,
};
DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);
DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);
DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);
DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);
static struct clk_rpm *msm8660_clks[] = {
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
[RPM_SMI_CLK] = &clk_rpm_smi_clk,
[RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
[RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
};
static const struct rpm_clk_desc rpm_clk_msm8660 = {
.clks = msm8660_clks,
.num_clks = ARRAY_SIZE(msm8660_clks),
};
static struct clk_rpm *apq8064_clks[] = {
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
[RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
[RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
[RPM_XO_D0] = &clk_rpm_xo_d0_clk,
[RPM_XO_D1] = &clk_rpm_xo_d1_clk,
[RPM_XO_A0] = &clk_rpm_xo_a0_clk,
[RPM_XO_A1] = &clk_rpm_xo_a1_clk,
[RPM_XO_A2] = &clk_rpm_xo_a2_clk,
};
static const struct rpm_clk_desc rpm_clk_apq8064 = {
.clks = apq8064_clks,
.num_clks = ARRAY_SIZE(apq8064_clks),
};
static struct clk_rpm *ipq806x_clks[] = {
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
[RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
[RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
[RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
[RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
};
static const struct rpm_clk_desc rpm_clk_ipq806x = {
.clks = ipq806x_clks,
.num_clks = ARRAY_SIZE(ipq806x_clks),
};
static const struct of_device_id rpm_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
{ .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct rpm_cc *rcc = data;
unsigned int idx = clkspec->args[0];
if (idx >= rcc->num_clks) {
pr_err("%s: invalid index %u\n", __func__, idx);
return ERR_PTR(-EINVAL);
}
return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
}
static int rpm_clk_probe(struct platform_device *pdev)
{
struct rpm_cc *rcc;
int ret;
size_t num_clks, i;
struct qcom_rpm *rpm;
struct clk_rpm **rpm_clks;
const struct rpm_clk_desc *desc;
rpm = dev_get_drvdata(pdev->dev.parent);
if (!rpm) {
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
return -ENODEV;
}
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
rpm_clks = desc->clks;
num_clks = desc->num_clks;
rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
if (!rcc)
return -ENOMEM;
rcc->clks = rpm_clks;
rcc->num_clks = num_clks;
mutex_init(&rcc->xo_lock);
for (i = 0; i < num_clks; i++) {
if (!rpm_clks[i])
continue;
rpm_clks[i]->rpm = rpm;
rpm_clks[i]->rpm_cc = rcc;
ret = clk_rpm_handoff(rpm_clks[i]);
if (ret)
goto err;
}
for (i = 0; i < num_clks; i++) {
if (!rpm_clks[i])
continue;
ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
if (ret)
goto err;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_rpm_clk_hw_get,
rcc);
if (ret)
goto err;
return 0;
err:
dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
return ret;
}
static struct platform_driver rpm_clk_driver = {
.driver = {
.name = "qcom-clk-rpm",
.of_match_table = rpm_clk_match_table,
},
.probe = rpm_clk_probe,
};
static int __init rpm_clk_init(void)
{
return platform_driver_register(&rpm_clk_driver);
}
core_initcall(rpm_clk_init);
static void __exit rpm_clk_exit(void)
{
platform_driver_unregister(&rpm_clk_driver);
}
module_exit(rpm_clk_exit);
MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:qcom-clk-rpm");
| linux-master | drivers/clk/qcom/clk-rpm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2020000000, 0 },
};
/* 810MHz configuration */
static struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x2a,
.alpha = 0x3000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00400805,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 1000MHz configuration */
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x34,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00400805,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x9430,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x942c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cb_clk = {
.halt_reg = 0x93a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x9130,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_demet_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_demet_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_demet_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_memnoc_gfx_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
};
static struct gdsc cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x905c,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = AON_RESET | RETAIN_FF_ENABLE,
};
static struct gdsc *gpu_cc_sa8775p_gdscs[] = {
[GPU_CC_CX_GDSC] = &cx_gdsc,
[GPU_CC_GX_GDSC] = &gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_CB_BCR] = { 0x93a0 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
};
static const struct regmap_config gpu_cc_sa8775p_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
.config = &gpu_cc_sa8775p_regmap_config,
.clks = gpu_cc_sa8775p_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks),
.resets = gpu_cc_sa8775p_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets),
.gdscs = gpu_cc_sa8775p_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs),
};
static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
{ .compatible = "qcom,sa8775p-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table);
static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap);
}
static struct platform_driver gpu_cc_sa8775p_driver = {
.probe = gpu_cc_sa8775p_probe,
.driver = {
.name = "gpu_cc-sa8775p",
.of_match_table = gpu_cc_sa8775p_match_table,
},
};
static int __init gpu_cc_sa8775p_init(void)
{
return platform_driver_register(&gpu_cc_sa8775p_driver);
}
subsys_initcall(gpu_cc_sa8775p_init);
static void __exit gpu_cc_sa8775p_exit(void)
{
platform_driver_unregister(&gpu_cc_sa8775p_driver);
}
module_exit(gpu_cc_sa8775p_exit);
MODULE_DESCRIPTION("SA8775P GPUCC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sa8775p.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_EVEN,
P_CAM_CC_PLL3_OUT_EVEN,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
.offset = 0x2000,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.offset = 0x3000,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &cam_cc_pll2_out_even.clkr.hw },
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
/*
* As per HW design, some of the CAMCC RCGs needs to
* move to XO clock during their clock disable so using
* clk_rcg2_shared_ops for such RCGs. This is required
* to power down the camera memories gracefully.
* Also, use CLK_SET_RATE_PARENT flag for the RCGs which
* have CAM_CC_PLL2_OUT_EVEN PLL as parent in frequency
* table and requires reconfiguration of the PLL frequency.
*/
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x600c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_clk_src = {
.cmd_rcgr = 0xb0d8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0x9060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0),
F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x5004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x5028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x504c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x5070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x6038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fd_core_clk_src = {
.cmd_rcgr = 0xb0b0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0xb088,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0x900c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.cmd_rcgr = 0x9038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0xa00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.cmd_rcgr = 0xa030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.cmd_rcgr = 0xb004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0xb024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.cmd_rcgr = 0x700c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
.cmd_rcgr = 0x800c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0xb04c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_lrme_clk_src = {
.cmd_rcgr = 0xb0f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_lrme_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 2),
F(33333333, P_CAM_CC_PLL0_OUT_EVEN, 2, 1, 9),
F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0x4004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0x4024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0x4044,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0x4064,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0),
F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0),
F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x6054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x606c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x606c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_areg_clk = {
.halt_reg = 0x6050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_axi_clk = {
.halt_reg = 0x6034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x6024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_atb_clk = {
.halt_reg = 0xb12c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb12c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_atb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_clk = {
.halt_reg = 0xb124,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_clk = {
.halt_reg = 0xb0f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0f0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0xb11c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb11c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0x501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0x5040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0x5064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0x5088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0x5020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0x5044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0x5068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0x508c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x508c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_fd_core_clk = {
.halt_reg = 0xb0c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fd_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_fd_core_uar_clk = {
.halt_reg = 0xb0d0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_uar_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fd_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_apb_clk = {
.halt_reg = 0xb084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_atb_clk = {
.halt_reg = 0xb078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_atb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0xb0a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_cti_clk = {
.halt_reg = 0xb07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_cti_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_ts_clk = {
.halt_reg = 0xb080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_ts_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_axi_clk = {
.halt_reg = 0x907c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x907c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0x9024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
.halt_reg = 0x9078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_csid_clk = {
.halt_reg = 0x9050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_dsp_clk = {
.halt_reg = 0x9034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_axi_clk = {
.halt_reg = 0xa054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0xa024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
.halt_reg = 0xa050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_csid_clk = {
.halt_reg = 0xa048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_dsp_clk = {
.halt_reg = 0xa02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.halt_reg = 0xb044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_csid_clk = {
.halt_reg = 0xb03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_ahb_clk = {
.halt_reg = 0x703c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x703c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_areg_clk = {
.halt_reg = 0x7038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_axi_clk = {
.halt_reg = 0x7034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_clk = {
.halt_reg = 0x7024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ipe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_1_ahb_clk = {
.halt_reg = 0x803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_1_areg_clk = {
.halt_reg = 0x8038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_1_axi_clk = {
.halt_reg = 0x8034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_1_clk = {
.halt_reg = 0x8024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ipe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0xb064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_lrme_clk = {
.halt_reg = 0xb110,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_lrme_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0x401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0x403c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0x405c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x405c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0x407c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x407c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_soc_ahb_clk = {
.halt_reg = 0xb13c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb13c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_soc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sys_tmr_clk = {
.halt_reg = 0xb0a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sys_tmr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc titan_top_gdsc;
static struct gdsc bps_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "bps_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x7004,
.pd = {
.name = "ipe_0_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ipe_1_gdsc = {
.gdscr = 0x8004,
.pd = {
.name = "ipe_1_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_0_gdsc = {
.gdscr = 0x9004,
.pd = {
.name = "ife_0_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_1_gdsc = {
.gdscr = 0xa004,
.pd = {
.name = "ife_1_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc titan_top_gdsc = {
.gdscr = 0xb134,
.pd = {
.name = "titan_top_gdsc",
},
.flags = POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *cam_cc_sdm845_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr,
[CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
[CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
[CAM_CC_ICP_APB_CLK] = &cam_cc_icp_apb_clk.clkr,
[CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr,
[CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr,
[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
[CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr,
[CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr,
[CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr,
[CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr,
[CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
[CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
};
static struct gdsc *cam_cc_sdm845_gdscs[] = {
[BPS_GDSC] = &bps_gdsc,
[IPE_0_GDSC] = &ipe_0_gdsc,
[IPE_1_GDSC] = &ipe_1_gdsc,
[IFE_0_GDSC] = &ife_0_gdsc,
[IFE_1_GDSC] = &ife_1_gdsc,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static const struct regmap_config cam_cc_sdm845_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xd004,
.fast_io = true,
};
static const struct qcom_cc_desc cam_cc_sdm845_desc = {
.config = &cam_cc_sdm845_regmap_config,
.clks = cam_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sdm845_clocks),
.gdscs = cam_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sdm845_gdscs),
};
static const struct of_device_id cam_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table);
static int cam_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config cam_cc_pll_config = { };
regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
cam_cc_pll_config.l = 0x1f;
cam_cc_pll_config.alpha = 0x4000;
clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config);
cam_cc_pll_config.l = 0x2a;
cam_cc_pll_config.alpha = 0x1556;
clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config);
cam_cc_pll_config.l = 0x32;
cam_cc_pll_config.alpha = 0x0;
clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config);
cam_cc_pll_config.l = 0x14;
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
}
static struct platform_driver cam_cc_sdm845_driver = {
.probe = cam_cc_sdm845_probe,
.driver = {
.name = "sdm845-camcc",
.of_match_table = cam_cc_sdm845_match_table,
},
};
static int __init cam_cc_sdm845_init(void)
{
return platform_driver_register(&cam_cc_sdm845_driver);
}
subsys_initcall(cam_cc_sdm845_init);
static void __exit cam_cc_sdm845_exit(void)
{
platform_driver_unregister(&cam_cc_sdm845_driver);
}
module_exit(cam_cc_sdm845_exit);
MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/camcc-sdm845.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
#include <asm/krait-l2-accessors.h>
#include "clk-krait.h"
/* Secondary and primary muxes share the same cp15 register */
static DEFINE_SPINLOCK(krait_clock_reg_lock);
#define LPL_SHIFT 8
#define SECCLKAGD BIT(4)
static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
{
unsigned long flags;
u32 regval;
spin_lock_irqsave(&krait_clock_reg_lock, flags);
regval = krait_get_l2_indirect_reg(mux->offset);
/* apq/ipq8064 Errata: disable sec_src clock gating during switch. */
if (mux->disable_sec_src_gating) {
regval |= SECCLKAGD;
krait_set_l2_indirect_reg(mux->offset, regval);
}
regval &= ~(mux->mask << mux->shift);
regval |= (sel & mux->mask) << mux->shift;
if (mux->lpl) {
regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
}
krait_set_l2_indirect_reg(mux->offset, regval);
/* apq/ipq8064 Errata: re-enabled sec_src clock gating. */
if (mux->disable_sec_src_gating) {
regval &= ~SECCLKAGD;
krait_set_l2_indirect_reg(mux->offset, regval);
}
/* Wait for switch to complete. */
mb();
udelay(1);
/*
* Unlock now to make sure the mux register is not
* modified while switching to the new parent.
*/
spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
}
static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
sel = clk_mux_index_to_val(mux->parent_map, 0, index);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
mux->reparent = true;
return 0;
}
static u8 krait_mux_get_parent(struct clk_hw *hw)
{
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
sel = krait_get_l2_indirect_reg(mux->offset);
sel >>= mux->shift;
sel &= mux->mask;
mux->en_mask = sel;
return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
const struct clk_ops krait_mux_clk_ops = {
.set_parent = krait_mux_set_parent,
.get_parent = krait_mux_get_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
static int krait_div2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2);
req->rate = DIV_ROUND_UP(req->best_parent_rate, 2);
return 0;
}
static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct krait_div2_clk *d = to_krait_div2_clk(hw);
unsigned long flags;
u32 val;
u32 mask = BIT(d->width) - 1;
if (d->lpl)
mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
else
mask <<= d->shift;
spin_lock_irqsave(&krait_clock_reg_lock, flags);
val = krait_get_l2_indirect_reg(d->offset);
val &= ~mask;
krait_set_l2_indirect_reg(d->offset, val);
spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
return 0;
}
static unsigned long
krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct krait_div2_clk *d = to_krait_div2_clk(hw);
u32 mask = BIT(d->width) - 1;
u32 div;
div = krait_get_l2_indirect_reg(d->offset);
div >>= d->shift;
div &= mask;
div = (div + 1) * 2;
return DIV_ROUND_UP(parent_rate, div);
}
const struct clk_ops krait_div2_clk_ops = {
.determine_rate = krait_div2_determine_rate,
.set_rate = krait_div2_set_rate,
.recalc_rate = krait_div2_recalc_rate,
};
EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
| linux-master | drivers/clk/qcom/clk-krait.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_XO,
P_GPLL0,
P_GPLL0_DIV2,
P_GPLL2,
P_GPLL4,
P_GPLL6,
P_SLEEP_CLK,
P_PCIE20_PHY0_PIPE,
P_PCIE20_PHY1_PIPE,
P_USB3PHY_0_PIPE,
P_USB3PHY_1_PIPE,
P_UBI32_PLL,
P_NSS_CRYPTO_PLL,
P_BIAS_PLL,
P_BIAS_PLL_NSS_NOC,
P_UNIPHY0_RX,
P_UNIPHY0_TX,
P_UNIPHY1_RX,
P_UNIPHY1_TX,
P_UNIPHY2_RX,
P_UNIPHY2_TX,
};
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll0_out_main_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main_div2",
.parent_hws = (const struct clk_hw *[]){
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]){
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll2_main = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_hws = (const struct clk_hw *[]){
&gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll4_main = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]){
&gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll6_main = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_alpha_pll_postdiv gpll6 = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_hws = (const struct clk_hw *[]){
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor gpll6_out_main_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main_div2",
.parent_hws = (const struct clk_hw *[]){
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll ubi32_pll_main = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "ubi32_pll_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
},
};
static struct clk_alpha_pll_postdiv ubi32_pll = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi32_pll",
.parent_hws = (const struct clk_hw *[]){
&ubi32_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll nss_crypto_pll_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv nss_crypto_pll = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll",
.parent_hws = (const struct clk_hw *[]){
&nss_crypto_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw},
{ .hw = &gpll0_out_main_div2.hw},
};
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
};
static struct clk_fixed_factor pcnoc_clk_src = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "pcnoc_clk_src",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_branch gcc_sleep_clk_src = {
.halt_reg = 0x30000,
.clkr = {
.enable_reg = 0x30000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_sleep_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
.name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(12500000, P_GPLL0_DIV2, 16, 1, 2),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x06000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x06014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x07000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x07014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
F(16000000, P_GPLL0_DIV2, 5, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 12.5, 1, 1),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x04034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x05034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x06034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x07034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 pcie0_axi_clk_src = {
.cmd_rcgr = 0x75054,
.freq_tbl = ftbl_pcie_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
};
static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
{ P_SLEEP_CLK, 6 },
};
static struct clk_rcg2 pcie0_aux_clk_src = {
.cmd_rcgr = 0x75024,
.freq_tbl = ftbl_pcie_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_aux_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
{ .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
{ P_PCIE20_PHY0_PIPE, 0 },
{ P_XO, 2 },
};
static struct clk_regmap_mux pcie0_pipe_clk_src = {
.reg = 0x7501c,
.shift = 8,
.width = 2,
.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie0_pipe_clk_src",
.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 pcie1_axi_clk_src = {
.cmd_rcgr = 0x76054,
.freq_tbl = ftbl_pcie_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pcie1_aux_clk_src = {
.cmd_rcgr = 0x76024,
.freq_tbl = ftbl_pcie_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_aux_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
{ .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
{ P_PCIE20_PHY1_PIPE, 0 },
{ P_XO, 2 },
};
static struct clk_regmap_mux pcie1_pipe_clk_src = {
.reg = 0x7601c,
.shift = 8,
.width = 2,
.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_pipe_clk_src",
.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(24000000, P_GPLL2, 12, 1, 4),
F(48000000, P_GPLL2, 12, 1, 2),
F(96000000, P_GPLL2, 12, 0, 0),
F(177777778, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL2, 6, 0, 0),
F(384000000, P_GPLL2, 3, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_usb_master_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0_out_main_div2.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0_DIV2, 2 },
{ P_GPLL0, 1 },
};
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x3e00c,
.freq_tbl = ftbl_usb_master_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_master_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb0_aux_clk_src = {
.cmd_rcgr = 0x3e05c,
.freq_tbl = ftbl_usb_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_aux_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(20000000, P_GPLL6, 6, 1, 9),
F(60000000, P_GPLL6, 6, 1, 3),
{ }
};
static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL6, 1 },
{ P_GPLL0, 3 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x3e020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
{ .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
{ P_USB3PHY_0_PIPE, 0 },
{ P_XO, 2 },
};
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x3e048,
.shift = 8,
.width = 2,
.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb0_pipe_clk_src",
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 usb1_master_clk_src = {
.cmd_rcgr = 0x3f00c,
.freq_tbl = ftbl_usb_master_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_master_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb1_aux_clk_src = {
.cmd_rcgr = 0x3f05c,
.freq_tbl = ftbl_usb_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_aux_clk_src",
.parent_data = gcc_xo_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb1_mock_utmi_clk_src = {
.cmd_rcgr = 0x3f020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
{ .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
{ P_USB3PHY_1_PIPE, 0 },
{ P_XO, 2 },
};
static struct clk_regmap_mux usb1_pipe_clk_src = {
.reg = 0x3f048,
.shift = 8,
.width = 2,
.parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb1_pipe_clk_src",
.parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_xo_clk_src = {
.halt_reg = 0x30018,
.clkr = {
.enable_reg = 0x30018,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_div4_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 3 },
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
};
static struct clk_fixed_factor system_noc_clk_src = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_hws = (const struct clk_hw *[]){
&system_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 nss_ce_clk_src = {
.cmd_rcgr = 0x68098,
.freq_tbl = ftbl_nss_ce_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ce_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
{ P_XO, 0 },
{ P_BIAS_PLL_NSS_NOC, 1 },
{ P_GPLL0, 2 },
{ P_GPLL2, 3 },
};
static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x68088,
.freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_noc_bfdcd_clk_src",
.parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor nss_noc_clk_src = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "nss_noc_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &nss_crypto_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
{ P_XO, 0 },
{ P_NSS_CRYPTO_PLL, 1 },
{ P_GPLL0, 2 },
};
static struct clk_rcg2 nss_crypto_clk_src = {
.cmd_rcgr = 0x68144,
.freq_tbl = ftbl_nss_crypto_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_clk_src",
.parent_data = gcc_xo_nss_crypto_pll_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(187200000, P_UBI32_PLL, 8, 0, 0),
F(748800000, P_UBI32_PLL, 2, 0, 0),
F(1497600000, P_UBI32_PLL, 1, 0, 0),
F(1689600000, P_UBI32_PLL, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll6.clkr.hw },
};
static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
{ P_XO, 0 },
{ P_UBI32_PLL, 1 },
{ P_GPLL0, 2 },
{ P_GPLL2, 3 },
{ P_GPLL4, 4 },
{ P_GPLL6, 5 },
};
static struct clk_rcg2 nss_ubi0_clk_src = {
.cmd_rcgr = 0x68104,
.freq_tbl = ftbl_nss_ubi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_clk_src",
.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
.num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap_div nss_ubi0_div_clk_src = {
.reg = 0x68118,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_ubi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_ubi1_clk_src = {
.cmd_rcgr = 0x68124,
.freq_tbl = ftbl_nss_ubi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_clk_src",
.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
.num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap_div nss_ubi1_div_clk_src = {
.reg = 0x68138,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_ubi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0_DIV2, 1 },
};
static struct clk_rcg2 ubi_mpt_clk_src = {
.cmd_rcgr = 0x68090,
.freq_tbl = ftbl_ubi_mpt_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi_mpt_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};
static struct clk_rcg2 nss_imem_clk_src = {
.cmd_rcgr = 0x68158,
.freq_tbl = ftbl_nss_imem_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_imem_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(300000000, P_BIAS_PLL, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
{ .hw = &ubi32_pll.clkr.hw },
};
static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
{ P_XO, 0 },
{ P_BIAS_PLL, 1 },
{ P_GPLL0, 2 },
{ P_GPLL4, 3 },
{ P_NSS_CRYPTO_PLL, 4 },
{ P_UBI32_PLL, 5 },
};
static struct clk_rcg2 nss_ppe_clk_src = {
.cmd_rcgr = 0x68080,
.freq_tbl = ftbl_nss_ppe_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ppe_clk_src",
.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
.num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "nss_ppe_cdiv_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_RX, 1 },
{ P_UNIPHY0_TX, 2 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port1_rx_clk_src = {
.cmd_rcgr = 0x68020,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port1_rx_div_clk_src = {
.reg = 0x68400,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_TX, 1 },
{ P_UNIPHY0_RX, 2 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port1_tx_clk_src = {
.cmd_rcgr = 0x68028,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port1_tx_div_clk_src = {
.reg = 0x68404,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_port2_rx_clk_src = {
.cmd_rcgr = 0x68030,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port2_rx_div_clk_src = {
.reg = 0x68410,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_port2_tx_clk_src = {
.cmd_rcgr = 0x68038,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port2_tx_div_clk_src = {
.reg = 0x68414,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_port3_rx_clk_src = {
.cmd_rcgr = 0x68040,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port3_rx_div_clk_src = {
.reg = 0x68420,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_port3_tx_clk_src = {
.cmd_rcgr = 0x68048,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port3_tx_div_clk_src = {
.reg = 0x68424,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_port4_rx_clk_src = {
.cmd_rcgr = 0x68050,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port4_rx_div_clk_src = {
.reg = 0x68430,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 nss_port4_tx_clk_src = {
.cmd_rcgr = 0x68058,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port4_tx_div_clk_src = {
.reg = 0x68434,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_RX, 1 },
{ P_UNIPHY0_TX, 2 },
{ P_UNIPHY1_RX, 3 },
{ P_UNIPHY1_TX, 4 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port5_rx_div_clk_src = {
.reg = 0x68440,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_TX, 1 },
{ P_UNIPHY0_RX, 2 },
{ P_UNIPHY1_TX, 3 },
{ P_UNIPHY1_RX, 4 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port5_tx_div_clk_src = {
.reg = 0x68444,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY2_RX, 5, 0, 0),
F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
F(125000000, P_UNIPHY2_RX, 1, 0, 0),
F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY2_RX, 1 },
{ P_UNIPHY2_TX, 2 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port6_rx_clk_src = {
.cmd_rcgr = 0x68070,
.freq_tbl = ftbl_nss_port6_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_clk_src",
.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port6_rx_div_clk_src = {
.reg = 0x68450,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port6_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY2_TX, 5, 0, 0),
F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
F(125000000, P_UNIPHY2_TX, 1, 0, 0),
F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY2_TX, 1 },
{ P_UNIPHY2_RX, 2 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port6_tx_clk_src = {
.cmd_rcgr = 0x68078,
.freq_tbl = ftbl_nss_port6_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_clk_src",
.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port6_tx_div_clk_src = {
.reg = 0x68454,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port6_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl ftbl_crypto_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.freq_tbl = ftbl_crypto_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_gp_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_SLEEP_CLK, 6 },
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.clkr = {
.enable_reg = 0x01008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04010,
.clkr = {
.enable_reg = 0x04010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0400c,
.clkr = {
.enable_reg = 0x0400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05010,
.clkr = {
.enable_reg = 0x05010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0500c,
.clkr = {
.enable_reg = 0x0500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x06010,
.clkr = {
.enable_reg = 0x06010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0600c,
.clkr = {
.enable_reg = 0x0600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x07010,
.clkr = {
.enable_reg = 0x07010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0700c,
.clkr = {
.enable_reg = 0x0700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x0402c,
.clkr = {
.enable_reg = 0x0402c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x0502c,
.clkr = {
.enable_reg = 0x0502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x0602c,
.clkr = {
.enable_reg = 0x0602c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x0702c,
.clkr = {
.enable_reg = 0x0702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_ahb_clk = {
.halt_reg = 0x57024,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_clk = {
.halt_reg = 0x57020,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_ahb_clk = {
.halt_reg = 0x75010,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_aux_clk = {
.halt_reg = 0x75014,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_m_clk = {
.halt_reg = 0x75008,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_m_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_clk = {
.halt_reg = 0x7500c,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_pipe_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_pipe_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
.halt_reg = 0x26048,
.clkr = {
.enable_reg = 0x26048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie0_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_ahb_clk = {
.halt_reg = 0x76010,
.clkr = {
.enable_reg = 0x76010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_aux_clk = {
.halt_reg = 0x76014,
.clkr = {
.enable_reg = 0x76014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_axi_m_clk = {
.halt_reg = 0x76008,
.clkr = {
.enable_reg = 0x76008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_m_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie1_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_axi_s_clk = {
.halt_reg = 0x7600c,
.clkr = {
.enable_reg = 0x7600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_s_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie1_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_pipe_clk = {
.halt_reg = 0x76018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x76018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_pipe_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
.halt_reg = 0x2604c,
.clkr = {
.enable_reg = 0x2604c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie1_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie1_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_aux_clk = {
.halt_reg = 0x3e044,
.clkr = {
.enable_reg = 0x3e044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
.halt_reg = 0x26040,
.clkr = {
.enable_reg = 0x26040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb0_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_master_clk = {
.halt_reg = 0x3e000,
.clkr = {
.enable_reg = 0x3e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_master_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_mock_utmi_clk = {
.halt_reg = 0x3e008,
.clkr = {
.enable_reg = 0x3e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
.halt_reg = 0x3e080,
.clkr = {
.enable_reg = 0x3e080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_pipe_clk = {
.halt_reg = 0x3e040,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x3e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_sleep_clk = {
.halt_reg = 0x3e004,
.clkr = {
.enable_reg = 0x3e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sleep_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_aux_clk = {
.halt_reg = 0x3f044,
.clkr = {
.enable_reg = 0x3f044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&usb1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
.halt_reg = 0x26044,
.clkr = {
.enable_reg = 0x26044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb1_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb1_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_master_clk = {
.halt_reg = 0x3f000,
.clkr = {
.enable_reg = 0x3f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_master_clk",
.parent_hws = (const struct clk_hw *[]){
&usb1_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_mock_utmi_clk = {
.halt_reg = 0x3f008,
.clkr = {
.enable_reg = 0x3f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb1_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
.halt_reg = 0x3f080,
.clkr = {
.enable_reg = 0x3f080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_pipe_clk = {
.halt_reg = 0x3f040,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x3f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_pipe_clk",
.parent_hws = (const struct clk_hw *[]){
&usb1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_sleep_clk = {
.halt_reg = 0x3f004,
.clkr = {
.enable_reg = 0x3f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_sleep_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sleep_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x5d014,
.clkr = {
.enable_reg = 0x5d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&sdcc1_ice_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mem_noc_nss_axi_clk = {
.halt_reg = 0x1d03c,
.clkr = {
.enable_reg = 0x1d03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mem_noc_nss_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ce_apb_clk = {
.halt_reg = 0x68174,
.clkr = {
.enable_reg = 0x68174,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_apb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ce_axi_clk = {
.halt_reg = 0x68170,
.clkr = {
.enable_reg = 0x68170,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_cfg_clk = {
.halt_reg = 0x68160,
.clkr = {
.enable_reg = 0x68160,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_crypto_clk = {
.halt_reg = 0x68164,
.clkr = {
.enable_reg = 0x68164,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_csr_clk = {
.halt_reg = 0x68318,
.clkr = {
.enable_reg = 0x68318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_csr_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_edma_cfg_clk = {
.halt_reg = 0x6819c,
.clkr = {
.enable_reg = 0x6819c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_edma_clk = {
.halt_reg = 0x68198,
.clkr = {
.enable_reg = 0x68198,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_imem_clk = {
.halt_reg = 0x68178,
.clkr = {
.enable_reg = 0x68178,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_imem_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_imem_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_noc_clk = {
.halt_reg = 0x68168,
.clkr = {
.enable_reg = 0x68168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_noc_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_btq_clk = {
.halt_reg = 0x6833c,
.clkr = {
.enable_reg = 0x6833c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_btq_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_cfg_clk = {
.halt_reg = 0x68194,
.clkr = {
.enable_reg = 0x68194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_clk = {
.halt_reg = 0x68190,
.clkr = {
.enable_reg = 0x68190,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_ipe_clk = {
.halt_reg = 0x68338,
.clkr = {
.enable_reg = 0x68338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_ipe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ptp_ref_clk = {
.halt_reg = 0x6816c,
.clkr = {
.enable_reg = 0x6816c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ptp_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_cdiv_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ppe_clk = {
.halt_reg = 0x68310,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x68310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ppe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
.halt_reg = 0x6830c,
.clkr = {
.enable_reg = 0x6830c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_apb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ce_axi_clk = {
.halt_reg = 0x68308,
.clkr = {
.enable_reg = 0x68308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_crypto_clk = {
.halt_reg = 0x68314,
.clkr = {
.enable_reg = 0x68314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
.halt_reg = 0x68304,
.clkr = {
.enable_reg = 0x68304,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ppe_clk = {
.halt_reg = 0x68300,
.clkr = {
.enable_reg = 0x68300,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
.halt_reg = 0x68180,
.clkr = {
.enable_reg = 0x68180,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_qosgen_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_snoc_clk = {
.halt_reg = 0x68188,
.clkr = {
.enable_reg = 0x68188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_snoc_clk",
.parent_hws = (const struct clk_hw *[]){
&system_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
.halt_reg = 0x68184,
.clkr = {
.enable_reg = 0x68184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_timeout_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_div4_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
.halt_reg = 0x68270,
.clkr = {
.enable_reg = 0x68270,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
.halt_reg = 0x68274,
.clkr = {
.enable_reg = 0x68274,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_ahb_clk = {
.halt_reg = 0x6820c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6820c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_axi_clk = {
.halt_reg = 0x68200,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68200,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_nc_axi_clk = {
.halt_reg = 0x68204,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_nc_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_core_clk = {
.halt_reg = 0x68210,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68210,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_core_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ubi0_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_mpt_clk = {
.halt_reg = 0x68208,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68208,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_mpt_clk",
.parent_hws = (const struct clk_hw *[]){
&ubi_mpt_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi1_ahb_clk = {
.halt_reg = 0x6822c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6822c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi1_axi_clk = {
.halt_reg = 0x68220,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68220,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi1_nc_axi_clk = {
.halt_reg = 0x68224,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_nc_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi1_core_clk = {
.halt_reg = 0x68230,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68230,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_core_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ubi1_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi1_mpt_clk = {
.halt_reg = 0x68228,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68228,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_mpt_clk",
.parent_hws = (const struct clk_hw *[]){
&ubi_mpt_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
.halt_reg = 0x56308,
.clkr = {
.enable_reg = 0x56308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_sys_clk = {
.halt_reg = 0x5630c,
.clkr = {
.enable_reg = 0x5630c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio_ahb_clk = {
.halt_reg = 0x58004,
.clkr = {
.enable_reg = 0x58004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdio_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_ahb_clk = {
.halt_reg = 0x56008,
.clkr = {
.enable_reg = 0x56008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_sys_clk = {
.halt_reg = 0x5600c,
.clkr = {
.enable_reg = 0x5600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_ahb_clk = {
.halt_reg = 0x56108,
.clkr = {
.enable_reg = 0x56108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_sys_clk = {
.halt_reg = 0x5610c,
.clkr = {
.enable_reg = 0x5610c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy2_ahb_clk = {
.halt_reg = 0x56208,
.clkr = {
.enable_reg = 0x56208,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy2_sys_clk = {
.halt_reg = 0x5620c,
.clkr = {
.enable_reg = 0x5620c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port1_rx_clk = {
.halt_reg = 0x68240,
.clkr = {
.enable_reg = 0x68240,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port1_tx_clk = {
.halt_reg = 0x68244,
.clkr = {
.enable_reg = 0x68244,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port2_rx_clk = {
.halt_reg = 0x68248,
.clkr = {
.enable_reg = 0x68248,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port2_tx_clk = {
.halt_reg = 0x6824c,
.clkr = {
.enable_reg = 0x6824c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port3_rx_clk = {
.halt_reg = 0x68250,
.clkr = {
.enable_reg = 0x68250,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port3_tx_clk = {
.halt_reg = 0x68254,
.clkr = {
.enable_reg = 0x68254,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port4_rx_clk = {
.halt_reg = 0x68258,
.clkr = {
.enable_reg = 0x68258,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port4_tx_clk = {
.halt_reg = 0x6825c,
.clkr = {
.enable_reg = 0x6825c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port5_rx_clk = {
.halt_reg = 0x68260,
.clkr = {
.enable_reg = 0x68260,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port5_tx_clk = {
.halt_reg = 0x68264,
.clkr = {
.enable_reg = 0x68264,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port6_rx_clk = {
.halt_reg = 0x68268,
.clkr = {
.enable_reg = 0x68268,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port6_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port6_tx_clk = {
.halt_reg = 0x6826c,
.clkr = {
.enable_reg = 0x6826c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port6_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port1_mac_clk = {
.halt_reg = 0x68320,
.clkr = {
.enable_reg = 0x68320,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port1_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port2_mac_clk = {
.halt_reg = 0x68324,
.clkr = {
.enable_reg = 0x68324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port2_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port3_mac_clk = {
.halt_reg = 0x68328,
.clkr = {
.enable_reg = 0x68328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port3_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port4_mac_clk = {
.halt_reg = 0x6832c,
.clkr = {
.enable_reg = 0x6832c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port4_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port5_mac_clk = {
.halt_reg = 0x68330,
.clkr = {
.enable_reg = 0x68330,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port5_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port6_mac_clk = {
.halt_reg = 0x68334,
.clkr = {
.enable_reg = 0x68334,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port6_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port1_rx_clk = {
.halt_reg = 0x56010,
.clkr = {
.enable_reg = 0x56010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port1_tx_clk = {
.halt_reg = 0x56014,
.clkr = {
.enable_reg = 0x56014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port2_rx_clk = {
.halt_reg = 0x56018,
.clkr = {
.enable_reg = 0x56018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port2_tx_clk = {
.halt_reg = 0x5601c,
.clkr = {
.enable_reg = 0x5601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port3_rx_clk = {
.halt_reg = 0x56020,
.clkr = {
.enable_reg = 0x56020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port3_tx_clk = {
.halt_reg = 0x56024,
.clkr = {
.enable_reg = 0x56024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port4_rx_clk = {
.halt_reg = 0x56028,
.clkr = {
.enable_reg = 0x56028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port4_tx_clk = {
.halt_reg = 0x5602c,
.clkr = {
.enable_reg = 0x5602c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port5_rx_clk = {
.halt_reg = 0x56030,
.clkr = {
.enable_reg = 0x56030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port5_tx_clk = {
.halt_reg = 0x56034,
.clkr = {
.enable_reg = 0x56034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_port5_rx_clk = {
.halt_reg = 0x56110,
.clkr = {
.enable_reg = 0x56110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_port5_tx_clk = {
.halt_reg = 0x56114,
.clkr = {
.enable_reg = 0x56114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy2_port6_rx_clk = {
.halt_reg = 0x56210,
.clkr = {
.enable_reg = 0x56210,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port6_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy2_port6_tx_clk = {
.halt_reg = 0x56214,
.clkr = {
.enable_reg = 0x56214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port6_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcie0_rchng_clk_src = {
.cmd_rcgr = 0x75070,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie0_rchng_clk = {
.halt_reg = 0x75070,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x75070,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_rchng_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
.halt_reg = 0x75048,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x75048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb0_gdsc = {
.gdscr = 0x3e078,
.pd = {
.name = "usb0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb1_gdsc = {
.gdscr = 0x3f078,
.pd = {
.name = "usb1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x4e,
.config_ctl_val = 0x200d4aa8,
.config_ctl_hi_val = 0x3c2,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = GENMASK(9, 8),
};
static const struct alpha_pll_config nss_crypto_pll_config = {
.l = 0x3e,
.alpha = 0x0,
.alpha_hi = 0x80,
.config_ctl_val = 0x4001055b,
.main_output_mask = BIT(0),
.pre_div_val = 0x0,
.pre_div_mask = GENMASK(14, 12),
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.vco_mask = GENMASK(21, 20),
.vco_val = 0x0,
.alpha_en_mask = BIT(24),
};
static struct clk_hw *gcc_ipq8074_hws[] = {
&gpll0_out_main_div2.hw,
&gpll6_out_main_div2.hw,
&pcnoc_clk_src.hw,
&system_noc_clk_src.hw,
&gcc_xo_div4_clk_src.hw,
&nss_noc_clk_src.hw,
&nss_ppe_cdiv_clk_src.hw,
};
static struct clk_regmap *gcc_ipq8074_clks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL2_MAIN] = &gpll2_main.clkr,
[GPLL2] = &gpll2.clkr,
[GPLL4_MAIN] = &gpll4_main.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL6_MAIN] = &gpll6_main.clkr,
[GPLL6] = &gpll6.clkr,
[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
[UBI32_PLL] = &ubi32_pll.clkr,
[NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
[NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
[USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
[USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
[USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
[NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
[NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
[NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
[NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
[NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
[NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
[UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
[NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
[NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
[NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
[NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
[NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
[NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
[NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
[NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
[NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
[NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
[NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
[NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
[NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
[NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
[NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
[NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
[NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
[NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
[NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
[NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
[NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
[NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
[NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
[NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
[NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
[NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
[GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
[GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
[GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
[GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
[GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
[GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
[GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
[GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
[GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
[GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
[GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
[GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
[GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
[GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
[GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
[GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
[GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
[GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
[GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
[GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
[GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
[GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
[GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
[GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
[GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
[GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
[GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
[GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
[GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
[GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
[GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
[GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
[GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
[GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
[GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
[GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
[GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
[GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
[GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
[GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
[GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
[GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
[GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
[GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
[GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
[GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
[GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
[GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
[GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
[GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
[GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
[GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
[GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
[GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
[GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
[GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
[GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
[GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
[GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
[GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
[GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
[GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
[GCC_BLSP1_BCR] = { 0x01000, 0 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
[GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
[GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
[GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
[GCC_IMEM_BCR] = { 0x0e000, 0 },
[GCC_SMMU_BCR] = { 0x12000, 0 },
[GCC_APSS_TCU_BCR] = { 0x12050, 0 },
[GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
[GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
[GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
[GCC_PRNG_BCR] = { 0x13000, 0 },
[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
[GCC_CRYPTO_BCR] = { 0x16000, 0 },
[GCC_WCSS_BCR] = { 0x18000, 0 },
[GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
[GCC_NSS_BCR] = { 0x19000, 0 },
[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
[GCC_ADSS_BCR] = { 0x1c000, 0 },
[GCC_DDRSS_BCR] = { 0x1e000, 0 },
[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
[GCC_PCNOC_BCR] = { 0x27018, 0 },
[GCC_TCSR_BCR] = { 0x28000, 0 },
[GCC_QDSS_BCR] = { 0x29000, 0 },
[GCC_DCD_BCR] = { 0x2a000, 0 },
[GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
[GCC_MPM_BCR] = { 0x2c000, 0 },
[GCC_SPMI_BCR] = { 0x2e000, 0 },
[GCC_SPDM_BCR] = { 0x2f000, 0 },
[GCC_RBCPR_BCR] = { 0x33000, 0 },
[GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
[GCC_TLMM_BCR] = { 0x34000, 0 },
[GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
[GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
[GCC_USB0_BCR] = { 0x3e070, 0 },
[GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
[GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
[GCC_USB1_BCR] = { 0x3f070, 0 },
[GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
[GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
[GCC_SDCC1_BCR] = { 0x42000, 0 },
[GCC_SDCC2_BCR] = { 0x43000, 0 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
[GCC_UNIPHY0_BCR] = { 0x56000, 0 },
[GCC_UNIPHY1_BCR] = { 0x56100, 0 },
[GCC_UNIPHY2_BCR] = { 0x56200, 0 },
[GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
[GCC_QPIC_BCR] = { 0x57018, 0 },
[GCC_MDIO_BCR] = { 0x58000, 0 },
[GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
[GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
[GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
[GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
[GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
[GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
[GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
[GCC_PCIE0_BCR] = { 0x75004, 0 },
[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
[GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
[GCC_PCIE1_BCR] = { 0x76004, 0 },
[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
[GCC_DCC_BCR] = { 0x77000, 0 },
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
[GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
[GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
[GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
[GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
[GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
[GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
[GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
[GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
[GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
[GCC_NSS_CFG_ARES] = { 0x68010, 16 },
[GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
[GCC_NSS_NOC_ARES] = { 0x68010, 18 },
[GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
[GCC_NSS_CSR_ARES] = { 0x68010, 20 },
[GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
[GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
[GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
[GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
[GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
[GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
[GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
[GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
[GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
[GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
[GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
};
static struct gdsc *gcc_ipq8074_gdscs[] = {
[USB0_GDSC] = &usb0_gdsc,
[USB1_GDSC] = &usb1_gdsc,
};
static const struct of_device_id gcc_ipq8074_match_table[] = {
{ .compatible = "qcom,gcc-ipq8074" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
static const struct regmap_config gcc_ipq8074_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x7fffc,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_ipq8074_desc = {
.config = &gcc_ipq8074_regmap_config,
.clks = gcc_ipq8074_clks,
.num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
.resets = gcc_ipq8074_resets,
.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
.clk_hws = gcc_ipq8074_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
.gdscs = gcc_ipq8074_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
};
static int gcc_ipq8074_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* SW Workaround for UBI32 Huayra PLL */
regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
}
static struct platform_driver gcc_ipq8074_driver = {
.probe = gcc_ipq8074_probe,
.driver = {
.name = "qcom,gcc-ipq8074",
.of_match_table = gcc_ipq8074_match_table,
},
};
static int __init gcc_ipq8074_init(void)
{
return platform_driver_register(&gcc_ipq8074_driver);
}
core_initcall(gcc_ipq8074_init);
static void __exit gcc_ipq8074_exit(void)
{
platform_driver_unregister(&gcc_ipq8074_driver);
}
module_exit(gcc_ipq8074_exit);
MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-ipq8074");
| linux-master | drivers/clk/qcom/gcc-ipq8074.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm A53 PLL driver
*
* Copyright (c) 2017, Linaro Limited
* Author: Georgi Djakov <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include "clk-pll.h"
#include "clk-regmap.h"
static const struct pll_freq_tbl a53pll_freq[] = {
{ 998400000, 52, 0x0, 0x1, 0 },
{ 1094400000, 57, 0x0, 0x1, 0 },
{ 1152000000, 62, 0x0, 0x1, 0 },
{ 1209600000, 63, 0x0, 0x1, 0 },
{ 1248000000, 65, 0x0, 0x1, 0 },
{ 1363200000, 71, 0x0, 0x1, 0 },
{ 1401600000, 73, 0x0, 0x1, 0 },
{ }
};
static const struct regmap_config a53pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x40,
.fast_io = true,
};
static struct pll_freq_tbl *qcom_a53pll_get_freq_tbl(struct device *dev)
{
struct pll_freq_tbl *freq_tbl;
unsigned long xo_freq;
unsigned long freq;
struct clk *xo_clk;
int count;
int ret;
int i;
xo_clk = devm_clk_get(dev, "xo");
if (IS_ERR(xo_clk))
return NULL;
xo_freq = clk_get_rate(xo_clk);
ret = devm_pm_opp_of_add_table(dev);
if (ret)
return NULL;
count = dev_pm_opp_get_opp_count(dev);
if (count <= 0)
return NULL;
freq_tbl = devm_kcalloc(dev, count + 1, sizeof(*freq_tbl), GFP_KERNEL);
if (!freq_tbl)
return NULL;
for (i = 0, freq = 0; i < count; i++, freq++) {
struct dev_pm_opp *opp;
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
if (IS_ERR(opp))
return NULL;
/* Skip the freq that is not divisible */
if (freq % xo_freq)
continue;
freq_tbl[i].freq = freq;
freq_tbl[i].l = freq / xo_freq;
freq_tbl[i].n = 1;
dev_pm_opp_put(opp);
}
return freq_tbl;
}
static int qcom_a53pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct regmap *regmap;
struct clk_pll *pll;
void __iomem *base;
struct clk_init_data init = { };
int ret;
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
if (!pll)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
pll->l_reg = 0x04;
pll->m_reg = 0x08;
pll->n_reg = 0x0c;
pll->config_reg = 0x14;
pll->mode_reg = 0x00;
pll->status_reg = 0x1c;
pll->status_bit = 16;
pll->freq_tbl = qcom_a53pll_get_freq_tbl(dev);
if (!pll->freq_tbl) {
/* Fall on a53pll_freq if no freq_tbl is found from OPP */
pll->freq_tbl = a53pll_freq;
}
/* Use an unique name by appending @unit-address */
init.name = devm_kasprintf(dev, GFP_KERNEL, "a53pll%s",
strchrnul(np->full_name, '@'));
if (!init.name)
return -ENOMEM;
init.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
};
init.num_parents = 1;
init.ops = &clk_pll_sr2_ops;
pll->clkr.hw.init = &init;
ret = devm_clk_register_regmap(dev, &pll->clkr);
if (ret) {
dev_err(dev, "failed to register regmap clock: %d\n", ret);
return ret;
}
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&pll->clkr.hw);
if (ret) {
dev_err(dev, "failed to add clock provider: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id qcom_a53pll_match_table[] = {
{ .compatible = "qcom,msm8916-a53pll" },
{ .compatible = "qcom,msm8939-a53pll" },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);
static struct platform_driver qcom_a53pll_driver = {
.probe = qcom_a53pll_probe,
.driver = {
.name = "qcom-a53pll",
.of_match_table = qcom_a53pll_match_table,
},
};
module_platform_driver(qcom_a53pll_driver);
MODULE_DESCRIPTION("Qualcomm A53 PLL Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/a53-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_VIDEO_PLL0_OUT_MAIN,
};
static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_venus_clk_src = {
.cmd_rcgr = 0x7f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_venus_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch video_cc_vcodec0_axi_clk = {
.halt_reg = 0x9ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9ec,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_vcodec0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_vcodec0_core_clk = {
.halt_reg = 0x890,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x890,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_vcodec0_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ahb_clk = {
.halt_reg = 0xa4c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa4c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ctl_axi_clk = {
.halt_reg = 0x9cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_venus_ctl_core_clk = {
.halt_reg = 0x850,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x850,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_venus_ctl_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x814,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec0_gdsc = {
.gdscr = 0x874,
.pd = {
.name = "vcodec0_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sc7180_clocks[] = {
[VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
[VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
[VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
[VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
[VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
[VIDEO_PLL0] = &video_pll0.clkr,
};
static struct gdsc *video_cc_sc7180_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VCODEC0_GDSC] = &vcodec0_gdsc,
};
static const struct regmap_config video_cc_sc7180_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xb94,
.fast_io = true,
};
static const struct qcom_cc_desc video_cc_sc7180_desc = {
.config = &video_cc_sc7180_regmap_config,
.clks = video_cc_sc7180_clocks,
.num_clks = ARRAY_SIZE(video_cc_sc7180_clocks),
.gdscs = video_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sc7180_gdscs),
};
static const struct of_device_id video_cc_sc7180_match_table[] = {
{ .compatible = "qcom,sc7180-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sc7180_match_table);
static int video_cc_sc7180_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config video_pll0_config = {};
regmap = qcom_cc_map(pdev, &video_cc_sc7180_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
video_pll0_config.l = 0x1f;
video_pll0_config.alpha = 0x4000;
video_pll0_config.user_ctl_val = 0x00000001;
video_pll0_config.user_ctl_hi_val = 0x00004805;
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap);
}
static struct platform_driver video_cc_sc7180_driver = {
.probe = video_cc_sc7180_probe,
.driver = {
.name = "sc7180-videocc",
.of_match_table = video_cc_sc7180_match_table,
},
};
static int __init video_cc_sc7180_init(void)
{
return platform_driver_register(&video_cc_sc7180_driver);
}
subsys_initcall(video_cc_sc7180_init);
static void __exit video_cc_sc7180_exit(void)
{
platform_driver_unregister(&video_cc_sc7180_driver);
}
module_exit(video_cc_sc7180_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SC7180 Driver");
| linux-master | drivers/clk/qcom/videocc-sc7180.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022, 2023 Linaro Ltd.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/interconnect-clk.h>
#include <linux/interconnect-provider.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
#include "clk-alpha-pll.h"
#include "clk-regmap.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_XO,
DT_APCS_AUX,
};
enum {
CBF_XO_INDEX,
CBF_PLL_INDEX,
CBF_DIV_INDEX,
CBF_APCS_AUX_INDEX,
};
#define DIV_THRESHOLD 600000000
#define CBF_MUX_OFFSET 0x18
#define CBF_MUX_PARENT_MASK GENMASK(1, 0)
#define CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)
#define CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \
FIELD_PREP(CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03)
#define CBF_MUX_AUTO_CLK_SEL_BIT BIT(6)
#define CBF_PLL_OFFSET 0xf000
static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
};
static struct alpha_pll_config cbfpll_config = {
.l = 72,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x006,
.test_ctl_val = 0x1c000000,
.test_ctl_hi_val = 0x00004000,
.pre_div_mask = BIT(12),
.post_div_mask = 0x3 << 8,
.post_div_val = 0x1 << 8,
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
};
static struct clk_alpha_pll cbf_pll = {
.offset = CBF_PLL_OFFSET,
.regs = cbf_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
.name = "cbf_pll",
.parent_data = (const struct clk_parent_data[]) {
{ .index = DT_XO, },
},
.num_parents = 1,
.ops = &clk_alpha_pll_hwfsm_ops,
},
};
static struct clk_fixed_factor cbf_pll_postdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "cbf_pll_postdiv",
.parent_hws = (const struct clk_hw*[]){
&cbf_pll.clkr.hw
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_parent_data cbf_mux_parent_data[] = {
{ .index = DT_XO },
{ .hw = &cbf_pll.clkr.hw },
{ .hw = &cbf_pll_postdiv.hw },
{ .index = DT_APCS_AUX },
};
struct clk_cbf_8996_mux {
u32 reg;
struct notifier_block nb;
struct clk_regmap clkr;
};
static struct clk_cbf_8996_mux *to_clk_cbf_8996_mux(struct clk_regmap *clkr)
{
return container_of(clkr, struct clk_cbf_8996_mux, clkr);
}
static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data);
static u8 clk_cbf_8996_mux_get_parent(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_cbf_8996_mux *mux = to_clk_cbf_8996_mux(clkr);
u32 val;
regmap_read(clkr->regmap, mux->reg, &val);
return FIELD_GET(CBF_MUX_PARENT_MASK, val);
}
static int clk_cbf_8996_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_cbf_8996_mux *mux = to_clk_cbf_8996_mux(clkr);
u32 val;
val = FIELD_PREP(CBF_MUX_PARENT_MASK, index);
return regmap_update_bits(clkr->regmap, mux->reg, CBF_MUX_PARENT_MASK, val);
}
static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw *parent;
if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div))
return -EINVAL;
if (req->rate < DIV_THRESHOLD)
parent = clk_hw_get_parent_by_index(hw, CBF_DIV_INDEX);
else
parent = clk_hw_get_parent_by_index(hw, CBF_PLL_INDEX);
if (!parent)
return -EINVAL;
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
req->best_parent_hw = parent;
return 0;
}
static const struct clk_ops clk_cbf_8996_mux_ops = {
.set_parent = clk_cbf_8996_mux_set_parent,
.get_parent = clk_cbf_8996_mux_get_parent,
.determine_rate = clk_cbf_8996_mux_determine_rate,
};
static struct clk_cbf_8996_mux cbf_mux = {
.reg = CBF_MUX_OFFSET,
.nb.notifier_call = cbf_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cbf_mux",
.parent_data = cbf_mux_parent_data,
.num_parents = ARRAY_SIZE(cbf_mux_parent_data),
.ops = &clk_cbf_8996_mux_ops,
/* CPU clock is critical and should never be gated */
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
},
};
static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
void *data)
{
struct clk_notifier_data *cnd = data;
switch (event) {
case PRE_RATE_CHANGE:
/*
* Avoid overvolting. clk_core_set_rate_nolock() walks from top
* to bottom, so it will change the rate of the PLL before
* chaging the parent of PMUX. This can result in pmux getting
* clocked twice the expected rate.
*
* Manually switch to PLL/2 here.
*/
if (cnd->old_rate > DIV_THRESHOLD &&
cnd->new_rate < DIV_THRESHOLD)
clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_DIV_INDEX);
break;
case ABORT_RATE_CHANGE:
/* Revert manual change */
if (cnd->new_rate < DIV_THRESHOLD &&
cnd->old_rate > DIV_THRESHOLD)
clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_PLL_INDEX);
break;
default:
break;
}
return notifier_from_errno(0);
};
static struct clk_hw *cbf_msm8996_hw_clks[] = {
&cbf_pll_postdiv.hw,
};
static struct clk_regmap *cbf_msm8996_clks[] = {
&cbf_pll.clkr,
&cbf_mux.clkr,
};
static const struct regmap_config cbf_msm8996_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
#ifdef CONFIG_INTERCONNECT
/* Random ID that doesn't clash with main qnoc and OSM */
#define CBF_MASTER_NODE 2000
static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
{
struct device *dev = &pdev->dev;
struct clk *clk = devm_clk_hw_get_clk(dev, cbf_hw, "cbf");
const struct icc_clk_data data[] = {
{ .clk = clk, .name = "cbf", },
};
struct icc_provider *provider;
provider = icc_clk_register(dev, CBF_MASTER_NODE, ARRAY_SIZE(data), data);
if (IS_ERR(provider))
return PTR_ERR(provider);
platform_set_drvdata(pdev, provider);
return 0;
}
static int qcom_msm8996_cbf_icc_remove(struct platform_device *pdev)
{
struct icc_provider *provider = platform_get_drvdata(pdev);
icc_clk_unregister(provider);
return 0;
}
#define qcom_msm8996_cbf_icc_sync_state icc_sync_state
#else
static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
{
dev_warn(&pdev->dev, "CONFIG_INTERCONNECT is disabled, CBF clock is fixed\n");
return 0;
}
#define qcom_msm8996_cbf_icc_remove(pdev) (0)
#define qcom_msm8996_cbf_icc_sync_state NULL
#endif
static int qcom_msm8996_cbf_probe(struct platform_device *pdev)
{
void __iomem *base;
struct regmap *regmap;
struct device *dev = &pdev->dev;
int i, ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &cbf_msm8996_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Select GPLL0 for 300MHz for the CBF clock */
regmap_write(regmap, CBF_MUX_OFFSET, 0x3);
/* Ensure write goes through before PLLs are reconfigured */
udelay(5);
/* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */
regmap_update_bits(regmap, CBF_MUX_OFFSET,
CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
clk_alpha_pll_configure(&cbf_pll, regmap, &cbfpll_config);
/* Wait for PLL(s) to lock */
udelay(50);
/* Enable auto clock selection for CBF */
regmap_update_bits(regmap, CBF_MUX_OFFSET,
CBF_MUX_AUTO_CLK_SEL_BIT,
CBF_MUX_AUTO_CLK_SEL_BIT);
/* Ensure write goes through before muxes are switched */
udelay(5);
/* Switch CBF to use the primary PLL */
regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1);
if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) {
cbfpll_config.post_div_val = 0x3 << 8;
cbf_pll_postdiv.div = 4;
}
for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) {
ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]);
if (ret)
return ret;
}
for (i = 0; i < ARRAY_SIZE(cbf_msm8996_clks); i++) {
ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[i]);
if (ret)
return ret;
}
ret = devm_clk_notifier_register(dev, cbf_mux.clkr.hw.clk, &cbf_mux.nb);
if (ret)
return ret;
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &cbf_mux.clkr.hw);
if (ret)
return ret;
return qcom_msm8996_cbf_icc_register(pdev, &cbf_mux.clkr.hw);
}
static int qcom_msm8996_cbf_remove(struct platform_device *pdev)
{
return qcom_msm8996_cbf_icc_remove(pdev);
}
static const struct of_device_id qcom_msm8996_cbf_match_table[] = {
{ .compatible = "qcom,msm8996-cbf" },
{ .compatible = "qcom,msm8996pro-cbf" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);
static struct platform_driver qcom_msm8996_cbf_driver = {
.probe = qcom_msm8996_cbf_probe,
.remove = qcom_msm8996_cbf_remove,
.driver = {
.name = "qcom-msm8996-cbf",
.of_match_table = qcom_msm8996_cbf_match_table,
.sync_state = qcom_msm8996_cbf_icc_sync_state,
},
};
/* Register early enough to fix the clock to be used for other cores */
static int __init qcom_msm8996_cbf_init(void)
{
return platform_driver_register(&qcom_msm8996_cbf_driver);
}
postcore_initcall(qcom_msm8996_cbf_init);
static void __exit qcom_msm8996_cbf_exit(void)
{
platform_driver_unregister(&qcom_msm8996_cbf_driver);
}
module_exit(qcom_msm8996_cbf_exit);
MODULE_DESCRIPTION("QCOM MSM8996 CPU Bus Fabric Clock Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/clk-cbf-8996.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,camcc-sm8250.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL0_OUT_MAIN,
P_CAM_CC_PLL0_OUT_ODD,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_EARLY,
P_CAM_CC_PLL2_OUT_MAIN,
P_CAM_CC_PLL3_OUT_EVEN,
P_CAM_CC_PLL4_OUT_EVEN,
P_SLEEP_CLK,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct pll_vco zonda_vco[] = {
{ 595200000UL, 3600000000UL, 0 },
};
static const struct alpha_pll_config cam_cc_pll0_config = {
.l = 0x3e,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699c,
.user_ctl_val = 0x00003100,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
{ 0x3, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
.offset = 0x0,
.post_div_shift = 12,
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_odd",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct alpha_pll_config cam_cc_pll1_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699c,
.user_ctl_val = 0x00000100,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct alpha_pll_config cam_cc_pll2_config = {
.l = 0x4b,
.alpha = 0x0,
.config_ctl_val = 0x08200920,
.config_ctl_hi_val = 0x05002015,
.config_ctl_hi1_val = 0x00000000,
.user_ctl_val = 0x00000100,
.user_ctl_hi_val = 0x00000000,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = zonda_vco,
.num_vco = ARRAY_SIZE(zonda_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_zonda_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
.offset = 0x2000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll2_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_main",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_zonda_ops,
},
};
static const struct alpha_pll_config cam_cc_pll3_config = {
.l = 0x24,
.alpha = 0x7555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699c,
.user_ctl_val = 0x00000100,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.offset = 0x3000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct alpha_pll_config cam_cc_pll4_config = {
.l = 0x24,
.alpha = 0x7555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699c,
.user_ctl_val = 0x00000100,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
.offset = 0x4000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll4_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll4_out_even",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll2_out_main.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_EARLY, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll2.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
};
static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_5[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .fw_name = "sleep_clk" },
};
static const struct parent_map cam_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x7010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
.cmd_rcgr = 0xc0f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0xc0bc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.cmd_rcgr = 0xc0d8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0xa068,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x6000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x6020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x6040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x6060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
.cmd_rcgr = 0x6080,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi4phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
.cmd_rcgr = 0x60a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi5phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x703c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fd_core_clk_src = {
.cmd_rcgr = 0xc098,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0xc074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0xa010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div cam_cc_sbi_div_clk_src = {
.reg = 0x9010,
.shift = 0,
.width = 3,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cam_cc_sbi_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.cmd_rcgr = 0xa040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0xb010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.cmd_rcgr = 0xb040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.cmd_rcgr = 0xc000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0xc01c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.cmd_rcgr = 0x8010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0xc048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 21),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0x5000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0x501c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0x5038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0x5054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.cmd_rcgr = 0x5070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
.cmd_rcgr = 0x508c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk5_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk6_clk_src = {
.cmd_rcgr = 0x50a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk6_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_sbi_csid_clk_src = {
.cmd_rcgr = 0x901c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
F(32768, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sleep_clk_src = {
.cmd_rcgr = 0xc170,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_sleep_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x7058,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_xo_clk_src = {
.cmd_rcgr = 0xc154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_6,
.freq_tbl = ftbl_cam_cc_xo_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_xo_clk_src",
.parent_data = cam_cc_parent_data_6,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x7070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_areg_clk = {
.halt_reg = 0x7054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_axi_clk = {
.halt_reg = 0x7038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x7028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_bps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_clk = {
.halt_reg = 0xc114,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
.halt_reg = 0xc11c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc11c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_dcd_xo_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_xo_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0xc0d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cci_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_1_clk = {
.halt_reg = 0xc0f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0f0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cci_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_core_ahb_clk = {
.halt_reg = 0xc150,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xc150,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_core_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0xc0f4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0x6018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0x6038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0x6058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0x6078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi3phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi4phytimer_clk = {
.halt_reg = 0x6098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi4phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi4phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi5phytimer_clk = {
.halt_reg = 0x60b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x60b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi5phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi5phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0x601c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0x603c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x603c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0x605c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x605c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0x607c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x607c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy4_clk = {
.halt_reg = 0x609c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x609c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy4_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy5_clk = {
.halt_reg = 0x60bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x60bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy5_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_fd_core_clk = {
.halt_reg = 0xc0b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fd_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_fd_core_uar_clk = {
.halt_reg = 0xc0b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc0b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_uar_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fd_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_gdsc_clk = {
.halt_reg = 0xc16c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc16c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_gdsc_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_xo_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_ahb_clk = {
.halt_reg = 0xc094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0xc08c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc08c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_icp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_ahb_clk = {
.halt_reg = 0xa088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_areg_clk = {
.halt_reg = 0xa030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_axi_clk = {
.halt_reg = 0xa084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0xa028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
.halt_reg = 0xa080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_csid_clk = {
.halt_reg = 0xa058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_dsp_clk = {
.halt_reg = 0xa03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_ahb_clk = {
.halt_reg = 0xb068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_areg_clk = {
.halt_reg = 0xb030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_axi_clk = {
.halt_reg = 0xb064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
.halt_reg = 0xb060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_csid_clk = {
.halt_reg = 0xb058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_dsp_clk = {
.halt_reg = 0xb03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
.halt_reg = 0xc040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_axi_clk = {
.halt_reg = 0xc044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_clk = {
.halt_reg = 0xc018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_lite_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.halt_reg = 0xc03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_csid_clk = {
.halt_reg = 0xc034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_lite_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_ahb_clk = {
.halt_reg = 0x8040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_areg_clk = {
.halt_reg = 0x803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_axi_clk = {
.halt_reg = 0x8038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_clk = {
.halt_reg = 0x8028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ipe_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0xc060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_jpeg_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0x5018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0x5034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0x5050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0x506c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x506c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk4_clk = {
.halt_reg = 0x5088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk4_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk5_clk = {
.halt_reg = 0x50a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk5_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk6_clk = {
.halt_reg = 0x50c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk6_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk6_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_ahb_clk = {
.halt_reg = 0x9040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_axi_clk = {
.halt_reg = 0x903c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x903c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_camnoc_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_clk = {
.halt_reg = 0x9014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_sbi_div_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_cphy_rx_clk = {
.halt_reg = 0x9038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_csid_clk = {
.halt_reg = 0x9034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_sbi_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_ife_0_clk = {
.halt_reg = 0x9044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_ife_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_ife_1_clk = {
.halt_reg = 0x9048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sbi_ife_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sleep_clk = {
.halt_reg = 0xc188,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_sleep_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc titan_top_gdsc;
static struct gdsc bps_gdsc = {
.gdscr = 0x7004,
.pd = {
.name = "bps_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x8004,
.pd = {
.name = "ipe_0_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sbi_gdsc = {
.gdscr = 0x9004,
.pd = {
.name = "sbi_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_0_gdsc = {
.gdscr = 0xa004,
.pd = {
.name = "ife_0_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_1_gdsc = {
.gdscr = 0xb004,
.pd = {
.name = "ife_1_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc titan_top_gdsc = {
.gdscr = 0xc144,
.pd = {
.name = "titan_top_gdsc",
},
.flags = POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *cam_cc_sm8250_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
[CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_IFE_0_AHB_CLK] = &cam_cc_ife_0_ahb_clk.clkr,
[CAM_CC_IFE_0_AREG_CLK] = &cam_cc_ife_0_areg_clk.clkr,
[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
[CAM_CC_IFE_1_AHB_CLK] = &cam_cc_ife_1_ahb_clk.clkr,
[CAM_CC_IFE_1_AREG_CLK] = &cam_cc_ife_1_areg_clk.clkr,
[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
[CAM_CC_IFE_LITE_AXI_CLK] = &cam_cc_ife_lite_axi_clk.clkr,
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
[CAM_CC_SBI_AXI_CLK] = &cam_cc_sbi_axi_clk.clkr,
[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
[CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr,
[CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr,
[CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr,
[CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr,
[CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr,
[CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr,
[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
};
static struct gdsc *cam_cc_sm8250_gdscs[] = {
[BPS_GDSC] = &bps_gdsc,
[IPE_0_GDSC] = &ipe_0_gdsc,
[SBI_GDSC] = &sbi_gdsc,
[IFE_0_GDSC] = &ife_0_gdsc,
[IFE_1_GDSC] = &ife_1_gdsc,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static const struct qcom_reset_map cam_cc_sm8250_resets[] = {
[CAM_CC_BPS_BCR] = { 0x7000 },
[CAM_CC_ICP_BCR] = { 0xc070 },
[CAM_CC_IFE_0_BCR] = { 0xa000 },
[CAM_CC_IFE_1_BCR] = { 0xb000 },
[CAM_CC_IPE_0_BCR] = { 0x8000 },
[CAM_CC_SBI_BCR] = { 0x9000 },
};
static const struct regmap_config cam_cc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xe004,
.fast_io = true,
};
static const struct qcom_cc_desc cam_cc_sm8250_desc = {
.config = &cam_cc_sm8250_regmap_config,
.clks = cam_cc_sm8250_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sm8250_clocks),
.resets = cam_cc_sm8250_resets,
.num_resets = ARRAY_SIZE(cam_cc_sm8250_resets),
.gdscs = cam_cc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sm8250_gdscs),
};
static const struct of_device_id cam_cc_sm8250_match_table[] = {
{ .compatible = "qcom,sm8250-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sm8250_match_table);
static int cam_cc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);
}
static struct platform_driver cam_cc_sm8250_driver = {
.probe = cam_cc_sm8250_probe,
.driver = {
.name = "cam_cc-sm8250",
.of_match_table = cam_cc_sm8250_match_table,
},
};
module_platform_driver(cam_cc_sm8250_driver);
MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/camcc-sm8250.c |
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (c) 2023, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "reset.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_XO,
DT_SLEEP_CLK,
DT_PCIE20_PHY0_PIPE_CLK,
DT_PCIE20_PHY1_PIPE_CLK,
DT_USB3_PHY0_CC_PIPE_CLK,
DT_GEPHY_RX_CLK,
DT_GEPHY_TX_CLK,
DT_UNIPHY_RX_CLK,
DT_UNIPHY_TX_CLK,
};
enum {
P_XO,
P_CORE_PI_SLEEP_CLK,
P_PCIE20_PHY0_PIPE,
P_PCIE20_PHY1_PIPE,
P_USB3PHY_0_PIPE,
P_GEPHY_RX,
P_GEPHY_TX,
P_UNIPHY_RX,
P_UNIPHY_TX,
P_GPLL0,
P_GPLL0_DIV2,
P_GPLL2,
P_GPLL4,
P_UBI32_PLL,
};
static const struct clk_parent_data gcc_xo_data[] = {
{ .index = DT_XO },
};
static const struct clk_parent_data gcc_sleep_clk_data[] = {
{ .index = DT_SLEEP_CLK },
};
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gpll0_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_alpha_pll gpll2_main = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "gpll2_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_alpha_pll gpll4_main = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data) {
.name = "gpll4_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_alpha_pll ubi32_pll_main = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data) {
.name = "ubi32_pll_main",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll2",
.parent_hws = (const struct clk_hw *[]) {
&gpll2_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]) {
&gpll4_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll_postdiv ubi32_pll = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "ubi32_pll",
.parent_hws = (const struct clk_hw *[]) {
&ubi32_pll_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_fixed_factor gpll0_out_main_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "gpll0_out_main_div2",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
{ .index = DT_XO },
{ .hw = &gpll0_out_main_div2.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0_DIV2, 2 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
{ .index = DT_XO },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
{ P_XO, 0 },
{ P_UBI32_PLL, 1 },
{ P_GPLL0, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL4, 3 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
{ P_CORE_PI_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
{ P_CORE_PI_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
{ P_XO, 0 },
{ P_GPLL4, 1 },
{ P_GPLL0, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
{ P_XO, 0 },
{ P_GPLL4, 1 },
{ P_GPLL0, 3 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
{ .index = DT_XO },
{ .index = DT_GEPHY_RX_CLK },
{ .index = DT_GEPHY_TX_CLK },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
{ P_XO, 0 },
{ P_GEPHY_RX, 1 },
{ P_GEPHY_TX, 2 },
{ P_UBI32_PLL, 3 },
{ P_GPLL0, 4 },
};
static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
{ .index = DT_XO },
{ .index = DT_GEPHY_TX_CLK },
{ .index = DT_GEPHY_RX_CLK },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
{ P_XO, 0 },
{ P_GEPHY_TX, 1 },
{ P_GEPHY_RX, 2 },
{ P_UBI32_PLL, 3 },
{ P_GPLL0, 4 },
};
static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
{ .index = DT_XO },
{ .index = DT_UNIPHY_RX_CLK },
{ .index = DT_UNIPHY_TX_CLK },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
{ P_XO, 0 },
{ P_UNIPHY_RX, 1 },
{ P_UNIPHY_TX, 2 },
{ P_UBI32_PLL, 3 },
{ P_GPLL0, 4 },
};
static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
{ .index = DT_XO },
{ .index = DT_UNIPHY_TX_CLK },
{ .index = DT_UNIPHY_RX_CLK },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
{ P_XO, 0 },
{ P_UNIPHY_TX, 1 },
{ P_UNIPHY_RX, 2 },
{ P_UBI32_PLL, 3 },
{ P_GPLL0, 4 },
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
{ .index = DT_PCIE20_PHY0_PIPE_CLK },
{ .index = DT_XO },
};
static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
{ P_PCIE20_PHY0_PIPE, 0 },
{ P_XO, 2 },
};
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
{ .index = DT_PCIE20_PHY1_PIPE_CLK },
{ .index = DT_XO },
};
static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
{ P_PCIE20_PHY1_PIPE, 0 },
{ P_XO, 2 },
};
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
{ .index = DT_USB3_PHY0_CC_PIPE_CLK },
{ .index = DT_XO },
};
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
{ P_USB3PHY_0_PIPE, 0 },
{ P_XO, 2 },
};
static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 adss_pwm_clk_src = {
.cmd_rcgr = 0x1f008,
.freq_tbl = ftbl_adss_pwm_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "adss_pwm_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 2, 5),
F(4800000, P_XO, 5, 0, 0),
F(9600000, P_XO, 2, 4, 5),
F(16000000, P_GPLL0, 10, 1, 5),
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 10, 4, 5),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.freq_tbl = ftbl_crypto_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
F(2500000, P_GEPHY_TX, 5, 0, 0),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GEPHY_TX, 5, 0, 0),
F(125000000, P_GEPHY_TX, 1, 0, 0),
{ }
};
static struct clk_rcg2 gmac0_rx_clk_src = {
.cmd_rcgr = 0x68020,
.parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
.hid_width = 5,
.freq_tbl = ftbl_gmac0_tx_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gmac0_rx_clk_src",
.parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gmac0_rx_div_clk_src = {
.reg = 0x68420,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gmac0_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gmac0_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 gmac0_tx_clk_src = {
.cmd_rcgr = 0x68028,
.parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
.hid_width = 5,
.freq_tbl = ftbl_gmac0_tx_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gmac0_tx_clk_src",
.parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gmac0_tx_div_clk_src = {
.reg = 0x68424,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gmac0_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gmac0_tx_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
F(125000000, P_UNIPHY_RX, 1, 0, 0),
F(312500000, P_UNIPHY_RX, 1, 0, 0),
{ }
};
static struct clk_rcg2 gmac1_rx_clk_src = {
.cmd_rcgr = 0x68030,
.parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
.hid_width = 5,
.freq_tbl = ftbl_gmac1_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gmac1_rx_clk_src",
.parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gmac1_rx_div_clk_src = {
.reg = 0x68430,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gmac1_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gmac1_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
F(125000000, P_UNIPHY_TX, 1, 0, 0),
F(312500000, P_UNIPHY_TX, 1, 0, 0),
{ }
};
static struct clk_rcg2 gmac1_tx_clk_src = {
.cmd_rcgr = 0x68038,
.parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
.hid_width = 5,
.freq_tbl = ftbl_gmac1_tx_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gmac1_tx_clk_src",
.parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gmac1_tx_div_clk_src = {
.reg = 0x68434,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gmac1_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gmac1_tx_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gmac_clk_src[] = {
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static struct clk_rcg2 gmac_clk_src = {
.cmd_rcgr = 0x68080,
.parent_map = gcc_xo_gpll0_gpll4_map,
.hid_width = 5,
.freq_tbl = ftbl_gmac_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gmac_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp_clk_src[] = {
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
F(133333334, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 lpass_axim_clk_src = {
.cmd_rcgr = 0x2e028,
.freq_tbl = ftbl_lpass_axim_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "lpass_axim_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
F(66666667, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 lpass_sway_clk_src = {
.cmd_rcgr = 0x2e040,
.freq_tbl = ftbl_lpass_sway_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "lpass_sway_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
F(2000000, P_XO, 12, 0, 0),
};
static struct clk_rcg2 pcie0_aux_clk_src = {
.cmd_rcgr = 0x75020,
.freq_tbl = ftbl_pcie0_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pcie0_aux_clk_src",
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static struct clk_rcg2 pcie0_axi_clk_src = {
.cmd_rcgr = 0x75050,
.freq_tbl = ftbl_pcie0_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pcie0_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pcie1_aux_clk_src = {
.cmd_rcgr = 0x76020,
.freq_tbl = ftbl_pcie0_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pcie1_aux_clk_src",
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pcie1_axi_clk_src = {
.cmd_rcgr = 0x76050,
.freq_tbl = ftbl_gp_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pcie1_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_mux pcie0_pipe_clk_src = {
.reg = 0x7501c,
.shift = 8,
.width = 2,
.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "pcie0_pipe_clk_src",
.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_mux pcie1_pipe_clk_src = {
.reg = 0x7601c,
.shift = 8,
.width = 2,
.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
.hw.init = &(struct clk_init_data) {
.name = "pcie1_pipe_clk_src",
.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor pcnoc_clk_src = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data) {
.name = "pcnoc_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static struct clk_rcg2 qdss_at_clk_src = {
.cmd_rcgr = 0x2900c,
.freq_tbl = ftbl_qdss_at_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
.clkr.hw.init = &(struct clk_init_data) {
.name = "qdss_at_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 qdss_stm_clk_src = {
.cmd_rcgr = 0x2902c,
.freq_tbl = ftbl_qdss_stm_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "qdss_stm_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 qdss_traceclkin_clk_src = {
.cmd_rcgr = 0x29048,
.freq_tbl = ftbl_qdss_traceclkin_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
.clkr.hw.init = &(struct clk_init_data) {
.name = "qdss_traceclkin_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
F(600000000, P_GPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 qdss_tsctr_clk_src = {
.cmd_rcgr = 0x29064,
.freq_tbl = ftbl_qdss_tsctr_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
.clkr.hw.init = &(struct clk_init_data) {
.name = "qdss_tsctr_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "qdss_tsctr_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor qdss_dap_sync_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data) {
.name = "qdss_dap_sync_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor eud_at_clk_src = {
.mult = 1,
.div = 6,
.hw.init = &(struct clk_init_data) {
.name = "eud_at_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
};
static struct clk_rcg2 qpic_io_macro_clk_src = {
.cmd_rcgr = 0x57010,
.freq_tbl = ftbl_qpic_io_macro_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "qpic_io_macro_clk_src",
.parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(143713, P_XO, 1, 1, 167),
F(400000, P_XO, 1, 1, 60),
F(24000000, P_XO, 1, 0, 0),
F(48000000, P_GPLL2, 12, 1, 2),
F(96000000, P_GPLL2, 12, 0, 0),
F(177777778, P_GPLL0, 1, 2, 9),
F(192000000, P_GPLL2, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor system_noc_clk_src = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data) {
.name = "system_noc_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 ubi0_axi_clk_src = {
.cmd_rcgr = 0x68088,
.freq_tbl = ftbl_apss_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "ubi0_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
F(850000000, P_UBI32_PLL, 1, 0, 0),
F(1000000000, P_UBI32_PLL, 1, 0, 0),
};
static struct clk_rcg2 ubi0_core_clk_src = {
.cmd_rcgr = 0x68100,
.freq_tbl = ftbl_ubi0_core_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_ubi32_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "ubi0_core_clk_src",
.parent_data = gcc_xo_ubi32_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 usb0_aux_clk_src = {
.cmd_rcgr = 0x3e05c,
.freq_tbl = ftbl_pcie0_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb0_aux_clk_src",
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
F(25000000, P_GPLL0, 16, 1, 2),
{ }
};
static struct clk_rcg2 usb0_lfps_clk_src = {
.cmd_rcgr = 0x3e090,
.freq_tbl = ftbl_usb0_lfps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb0_lfps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x3e00c,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb0_master_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
F(60000000, P_GPLL4, 10, 1, 2),
{ }
};
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x3e020,
.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x3e048,
.shift = 8,
.width = 2,
.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "usb0_pipe_clk_src",
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 q6_axi_clk_src = {
.cmd_rcgr = 0x59120,
.freq_tbl = ftbl_q6_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "q6_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
F(133333333, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 wcss_ahb_clk_src = {
.cmd_rcgr = 0x59020,
.freq_tbl = ftbl_wcss_ahb_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "wcss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_sleep_clk_src = {
.halt_reg = 0x30000,
.clkr = {
.enable_reg = 0x30000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sleep_clk_src",
.parent_data = gcc_sleep_clk_data,
.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_clk_src = {
.halt_reg = 0x30018,
.clkr = {
.enable_reg = 0x30018,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_xo_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_clk = {
.halt_reg = 0x30030,
.clkr = {
.enable_reg = 0x30030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_xo_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_adss_pwm_clk = {
.halt_reg = 0x1f020,
.clkr = {
.enable_reg = 0x1f020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_adss_pwm_clk",
.parent_hws = (const struct clk_hw *[]) {
&adss_pwm_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04010,
.clkr = {
.enable_reg = 0x04010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0400c,
.clkr = {
.enable_reg = 0x0400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_btss_lpo_clk = {
.halt_reg = 0x1c004,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_btss_lpo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_blk_ahb_clk = {
.halt_reg = 0x56308,
.clkr = {
.enable_reg = 0x56308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cmn_blk_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_blk_sys_clk = {
.halt_reg = 0x5630c,
.clkr = {
.enable_reg = 0x5630c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cmn_blk_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]) {
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_clk = {
.halt_reg = 0x77004,
.clkr = {
.enable_reg = 0x77004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_dcc_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gephy_rx_clk = {
.halt_reg = 0x56010,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x56010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gephy_rx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac0_rx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_gephy_tx_clk = {
.halt_reg = 0x56014,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x56014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gephy_tx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac0_tx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_gmac0_cfg_clk = {
.halt_reg = 0x68304,
.clkr = {
.enable_reg = 0x68304,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac0_cfg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gmac0_ptp_clk = {
.halt_reg = 0x68300,
.clkr = {
.enable_reg = 0x68300,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac0_ptp_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gmac0_rx_clk = {
.halt_reg = 0x68240,
.clkr = {
.enable_reg = 0x68240,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac0_rx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac0_rx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_gmac0_sys_clk = {
.halt_reg = 0x68190,
.halt_check = BRANCH_HALT_DELAY,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x683190,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac0_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gmac0_tx_clk = {
.halt_reg = 0x68244,
.clkr = {
.enable_reg = 0x68244,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac0_tx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac0_tx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_gmac1_cfg_clk = {
.halt_reg = 0x68324,
.clkr = {
.enable_reg = 0x68324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac1_cfg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gmac1_ptp_clk = {
.halt_reg = 0x68320,
.clkr = {
.enable_reg = 0x68320,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac1_ptp_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gmac1_rx_clk = {
.halt_reg = 0x68248,
.clkr = {
.enable_reg = 0x68248,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac1_rx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac1_rx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_gmac1_sys_clk = {
.halt_reg = 0x68310,
.clkr = {
.enable_reg = 0x68310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac1_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gmac1_tx_clk = {
.halt_reg = 0x6824c,
.clkr = {
.enable_reg = 0x6824c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gmac1_tx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac1_tx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_core_axim_clk = {
.halt_reg = 0x2e048,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x2e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_lpass_core_axim_clk",
.parent_hws = (const struct clk_hw *[]) {
&lpass_axim_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_sway_clk = {
.halt_reg = 0x2e04c,
.clkr = {
.enable_reg = 0x2e04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_lpass_sway_clk",
.parent_hws = (const struct clk_hw *[]) {
&lpass_sway_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio0_ahb_clk = {
.halt_reg = 0x58004,
.clkr = {
.enable_reg = 0x58004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdioi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio1_ahb_clk = {
.halt_reg = 0x58014,
.clkr = {
.enable_reg = 0x58014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdio1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_ahb_clk = {
.halt_reg = 0x75010,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie0_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_aux_clk = {
.halt_reg = 0x75014,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie0_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_m_clk = {
.halt_reg = 0x75008,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie0_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
.halt_reg = 0x75048,
.clkr = {
.enable_reg = 0x75048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie0_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_clk = {
.halt_reg = 0x7500c,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie0_axi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_pipe_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_DELAY,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie0_pipe_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_ahb_clk = {
.halt_reg = 0x76010,
.clkr = {
.enable_reg = 0x76010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_aux_clk = {
.halt_reg = 0x76014,
.clkr = {
.enable_reg = 0x76014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie1_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_axi_m_clk = {
.halt_reg = 0x76008,
.clkr = {
.enable_reg = 0x76008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie1_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
.halt_reg = 0x76048,
.clkr = {
.enable_reg = 0x76048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie1_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_axi_s_clk = {
.halt_reg = 0x7600c,
.clkr = {
.enable_reg = 0x7600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie1_axi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_pipe_clk = {
.halt_reg = 8,
.halt_check = BRANCH_HALT_DELAY,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x76018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie1_pipe_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data) {
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_ahb_clk = {
.halt_reg = 0x59138,
.clkr = {
.enable_reg = 0x59138,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_ahb_s_clk = {
.halt_reg = 0x5914c,
.clkr = {
.enable_reg = 0x5914c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6_ahb_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_axim_clk = {
.halt_reg = 0x5913c,
.clkr = {
.enable_reg = 0x5913c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6_axim_clk",
.parent_hws = (const struct clk_hw *[]) {
&q6_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_axim2_clk = {
.halt_reg = 0x59150,
.clkr = {
.enable_reg = 0x59150,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6_axim2_clk",
.parent_hws = (const struct clk_hw *[]) {
&q6_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_axis_clk = {
.halt_reg = 0x59154,
.clkr = {
.enable_reg = 0x59154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6_axis_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_tsctr_1to2_clk = {
.halt_reg = 0x59148,
.clkr = {
.enable_reg = 0x59148,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6_tsctr_1to2_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_atbm_clk = {
.halt_reg = 0x59144,
.clkr = {
.enable_reg = 0x59144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6ss_atbm_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_pclkdbg_clk = {
.halt_reg = 0x59140,
.clkr = {
.enable_reg = 0x59140,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6ss_pclkdbg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_trig_clk = {
.halt_reg = 0x59128,
.clkr = {
.enable_reg = 0x59128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_q6ss_trig_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_at_clk = {
.halt_reg = 0x29024,
.clkr = {
.enable_reg = 0x29024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.clkr = {
.enable_reg = 0x29084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_dap_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_cfg_ahb_clk = {
.halt_reg = 0x29008,
.clkr = {
.enable_reg = 0x29008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_ahb_clk = {
.halt_reg = 0x29004,
.clkr = {
.enable_reg = 0x29004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_dap_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_etr_usb_clk = {
.halt_reg = 0x29028,
.clkr = {
.enable_reg = 0x29028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_etr_usb_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_eud_at_clk = {
.halt_reg = 0x29020,
.clkr = {
.enable_reg = 0x29020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_eud_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&eud_at_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_stm_clk = {
.halt_reg = 0x29044,
.clkr = {
.enable_reg = 0x29044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_stm_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_stm_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_traceclkin_clk = {
.halt_reg = 0x29060,
.clkr = {
.enable_reg = 0x29060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_traceclkin_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_traceclkin_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_tsctr_div8_clk = {
.halt_reg = 0x2908c,
.clkr = {
.enable_reg = 0x2908c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_tsctr_div8_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_ahb_clk = {
.halt_reg = 0x57024,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qpic_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_clk = {
.halt_reg = 0x57020,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qpic_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_io_macro_clk = {
.halt_reg = 0x5701c,
.clkr = {
.enable_reg = 0x5701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qpic_io_macro_clk",
.parent_hws = (const struct clk_hw *[]) {
&qpic_io_macro_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
.halt_reg = 0x260a0,
.clkr = {
.enable_reg = 0x260a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_gmac0_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_gmac0_axi_clk = {
.halt_reg = 0x26084,
.clkr = {
.enable_reg = 0x26084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_gmac0_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
.halt_reg = 0x260a4,
.clkr = {
.enable_reg = 0x260a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_gmac1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_gmac1_axi_clk = {
.halt_reg = 0x26088,
.clkr = {
.enable_reg = 0x26088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_gmac1_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_lpass_axim_clk = {
.halt_reg = 0x26074,
.clkr = {
.enable_reg = 0x26074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_lpass_axim_clk",
.parent_hws = (const struct clk_hw *[]) {
&lpass_axim_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_lpass_sway_clk = {
.halt_reg = 0x26078,
.clkr = {
.enable_reg = 0x26078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_lpass_sway_clk",
.parent_hws = (const struct clk_hw *[]) {
&lpass_sway_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_ubi0_axi_clk = {
.halt_reg = 0x26094,
.clkr = {
.enable_reg = 0x26094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_snoc_ubi0_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&ubi0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
.halt_reg = 0x26048,
.clkr = {
.enable_reg = 0x26048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sys_noc_pcie0_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
.halt_reg = 0x2604c,
.clkr = {
.enable_reg = 0x2604c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sys_noc_pcie1_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcie1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
.halt_reg = 0x26024,
.clkr = {
.enable_reg = 0x26024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sys_noc_qdss_stm_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_stm_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
.halt_reg = 0x26040,
.clkr = {
.enable_reg = 0x26040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sys_noc_usb0_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
.halt_reg = 0x26034,
.clkr = {
.enable_reg = 0x26034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sys_noc_wcss_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_axi_clk = {
.halt_reg = 0x68200,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68200,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_ubi0_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&ubi0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_cfg_clk = {
.halt_reg = 0x68160,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68160,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_ubi0_cfg_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_dbg_clk = {
.halt_reg = 0x68214,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_ubi0_dbg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_core_clk = {
.halt_reg = 0x68210,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68210,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_ubi0_core_clk",
.parent_hws = (const struct clk_hw *[]) {
&ubi0_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_nc_axi_clk = {
.halt_reg = 0x68204,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_ubi0_nc_axi_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_utcm_clk = {
.halt_reg = 0x68208,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68208,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_ubi0_utcm_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy_ahb_clk = {
.halt_reg = 0x56108,
.clkr = {
.enable_reg = 0x56108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_uniphy_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy_rx_clk = {
.halt_reg = 0x56110,
.clkr = {
.enable_reg = 0x56110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_uniphy_rx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac1_rx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_uniphy_tx_clk = {
.halt_reg = 0x56114,
.clkr = {
.enable_reg = 0x56114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_uniphy_tx_clk",
.parent_hws = (const struct clk_hw *[]) {
&gmac1_tx_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_uniphy_sys_clk = {
.halt_reg = 0x5610c,
.clkr = {
.enable_reg = 0x5610c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_uniphy_sys_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_aux_clk = {
.halt_reg = 0x3e044,
.clkr = {
.enable_reg = 0x3e044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_aux_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_eud_at_clk = {
.halt_reg = 0x3e04c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3e04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_eud_at_clk",
.parent_hws = (const struct clk_hw *[]) {
&eud_at_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_lfps_clk = {
.halt_reg = 0x3e050,
.clkr = {
.enable_reg = 0x3e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_lfps_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_lfps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_master_clk = {
.halt_reg = 0x3e000,
.clkr = {
.enable_reg = 0x3e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_master_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_mock_utmi_clk = {
.halt_reg = 0x3e008,
.clkr = {
.enable_reg = 0x3e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
.halt_reg = 0x3e080,
.clkr = {
.enable_reg = 0x3e080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&pcnoc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_sleep_clk = {
.halt_reg = 0x3e004,
.clkr = {
.enable_reg = 0x3e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_sleep_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_pipe_clk = {
.halt_reg = 0x3e040,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x3e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_pipe_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_acmt_clk = {
.halt_reg = 0x59064,
.clkr = {
.enable_reg = 0x59064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_acmt_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_ahb_s_clk = {
.halt_reg = 0x59034,
.clkr = {
.enable_reg = 0x59034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_ahb_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_axi_m_clk = {
.halt_reg = 0x5903c,
.clkr = {
.enable_reg = 0x5903c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_axi_m_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_axi_s_clk = {
.halt_reg = 0x59068,
.clkr = {
.enable_reg = 0x59068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wi_s_clk",
.parent_hws = (const struct clk_hw *[]) {
&system_noc_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
.halt_reg = 0x59050,
.clkr = {
.enable_reg = 0x59050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
.halt_reg = 0x59040,
.clkr = {
.enable_reg = 0x59040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_apb_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
.halt_reg = 0x59054,
.clkr = {
.enable_reg = 0x59054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
.halt_reg = 0x59044,
.clkr = {
.enable_reg = 0x59044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_atb_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
.halt_reg = 0x59060,
.clkr = {
.enable_reg = 0x59060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
.halt_reg = 0x5905c,
.clkr = {
.enable_reg = 0x5905c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_dapbus_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_dap_sync_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
.halt_reg = 0x59058,
.clkr = {
.enable_reg = 0x59058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
.halt_reg = 0x59048,
.clkr = {
.enable_reg = 0x59048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_nts_clk",
.parent_hws = (const struct clk_hw *[]) {
&qdss_tsctr_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_ecahb_clk = {
.halt_reg = 0x59038,
.clkr = {
.enable_reg = 0x59038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_wcss_ecahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_hw *gcc_ipq5018_hws[] = {
&gpll0_out_main_div2.hw,
&pcnoc_clk_src.hw,
&system_noc_clk_src.hw,
&qdss_dap_sync_clk_src.hw,
&qdss_tsctr_div2_clk_src.hw,
&eud_at_clk_src.hw,
};
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x29,
.alpha = 0xaaaaaaaa,
.alpha_hi = 0xaa,
.config_ctl_val = 0x4001075b,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.alpha_en_mask = BIT(24),
.vco_val = 0x1,
.vco_mask = GENMASK(21, 20),
.test_ctl_val = 0x0,
.test_ctl_hi_val = 0x0,
};
static struct clk_regmap *gcc_ipq5018_clks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL2_MAIN] = &gpll2_main.clkr,
[GPLL2] = &gpll2.clkr,
[GPLL4_MAIN] = &gpll4_main.clkr,
[GPLL4] = &gpll4.clkr,
[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
[UBI32_PLL] = &ubi32_pll.clkr,
[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
[GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
[GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
[GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
[GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
[GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
[GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
[GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
[GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
[GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
[GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
[GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
[GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
[GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
[GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
[GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
[GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
[GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
[GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
[GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
[GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
[GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
[GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
[GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
[GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
[GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
[GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
[GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
[GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
[GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
[GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
[GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
[GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
[GCC_XO_CLK] = &gcc_xo_clk.clkr,
[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
[GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
[GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
[GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
[GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
[GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
[GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
[GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
[GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
[GMAC_CLK_SRC] = &gmac_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
[UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
[USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq5018_resets[] = {
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
[GCC_BLSP1_BCR] = { 0x01000, 0 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
[GCC_BTSS_BCR] = { 0x1c000, 0 },
[GCC_CMN_BLK_BCR] = { 0x56300, 0 },
[GCC_CMN_LDO_BCR] = { 0x33000, 0 },
[GCC_CE_BCR] = { 0x33014, 0 },
[GCC_CRYPTO_BCR] = { 0x16000, 0 },
[GCC_DCC_BCR] = { 0x77000, 0 },
[GCC_DCD_BCR] = { 0x2a000, 0 },
[GCC_DDRSS_BCR] = { 0x1e000, 0 },
[GCC_EDPD_BCR] = { 0x3a000, 0 },
[GCC_GEPHY_BCR] = { 0x56000, 0 },
[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
[GCC_GMAC0_BCR] = { 0x19000, 0 },
[GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
[GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
[GCC_GMAC1_BCR] = { 0x19100, 0 },
[GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
[GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
[GCC_IMEM_BCR] = { 0x0e000, 0 },
[GCC_LPASS_BCR] = { 0x2e000, 0 },
[GCC_MDIO0_BCR] = { 0x58000, 0 },
[GCC_MDIO1_BCR] = { 0x58010, 0 },
[GCC_MPM_BCR] = { 0x2c000, 0 },
[GCC_PCIE0_BCR] = { 0x75004, 0 },
[GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
[GCC_PCIE1_BCR] = { 0x76004, 0 },
[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
[GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
[GCC_PCNOC_BCR] = { 0x27018, 0 },
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
[GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
[GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
[GCC_PRNG_BCR] = { 0x13000, 0 },
[GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
[GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
[GCC_Q6_AHB_ARES] = { 0x59110, 2 },
[GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
[GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
[GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
[GCC_QDSS_BCR] = { 0x29000, 0 },
[GCC_QPIC_BCR] = { 0x57018, 0 },
[GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
[GCC_SDCC1_BCR] = { 0x42000, 0 },
[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
[GCC_SPDM_BCR] = { 0x2f000, 0 },
[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
[GCC_TCSR_BCR] = { 0x28000, 0 },
[GCC_TLMM_BCR] = { 0x34000, 0 },
[GCC_UBI0_AXI_ARES] = { 0x680},
[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
[GCC_UBI32_BCR] = { 0x19064, 0 },
[GCC_UNIPHY_BCR] = { 0x56100, 0 },
[GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
[GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
[GCC_USB0_BCR] = { 0x3e070, 0 },
[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
[GCC_WCSS_BCR] = { 0x18000, 0 },
[GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
[GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
[GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
[GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
[GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
[GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
[GCC_WCSSAON_RESET] = { 0x59010, 0},
[GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
};
static const struct of_device_id gcc_ipq5018_match_table[] = {
{ .compatible = "qcom,gcc-ipq5018" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
static const struct regmap_config gcc_ipq5018_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x7fffc,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_ipq5018_desc = {
.config = &gcc_ipq5018_regmap_config,
.clks = gcc_ipq5018_clks,
.num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
.resets = gcc_ipq5018_resets,
.num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
.clk_hws = gcc_ipq5018_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
};
static int gcc_ipq5018_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
regmap = qcom_cc_map(pdev, &ipq5018_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
}
static struct platform_driver gcc_ipq5018_driver = {
.probe = gcc_ipq5018_probe,
.driver = {
.name = "qcom,gcc-ipq5018",
.of_match_table = gcc_ipq5018_match_table,
},
};
static int __init gcc_ipq5018_init(void)
{
return platform_driver_register(&gcc_ipq5018_driver);
}
core_initcall(gcc_ipq5018_init);
static void __exit gcc_ipq5018_exit(void)
{
platform_driver_unregister(&gcc_ipq5018_driver);
}
module_exit(gcc_ipq5018_exit);
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-ipq5018.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "clk-alpha-pll.h"
/*
* Even though APSS PLL type is of existing one (like Huayra), its offsets
* are different from the one mentioned in the clk-alpha-pll.c, since the
* PLL is specific to APSS, so lets the define the same.
*/
static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
};
static struct clk_alpha_pll ipq_pll_huayra = {
.offset = 0x0,
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "a53pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
},
};
static struct clk_alpha_pll ipq_pll_stromer_plus = {
.offset = 0x0,
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "a53pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static const struct alpha_pll_config ipq5332_pll_config = {
.l = 0x3e,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x304,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.early_output_mask = BIT(3),
.alpha_en_mask = BIT(24),
.status_val = 0x3,
.status_mask = GENMASK(10, 8),
.lock_det = BIT(2),
.test_ctl_hi_val = 0x00400003,
};
static const struct alpha_pll_config ipq6018_pll_config = {
.l = 0x37,
.config_ctl_val = 0x240d4828,
.config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
.aux2_output_mask = BIT(2),
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.test_ctl_val = 0x1c0000C0,
.test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config ipq8074_pll_config = {
.l = 0x48,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
.aux2_output_mask = BIT(2),
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.test_ctl_val = 0x1c000000,
.test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config ipq9574_pll_config = {
.l = 0x3b,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x6,
.early_output_mask = BIT(3),
.aux2_output_mask = BIT(2),
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.test_ctl_val = 0x0,
.test_ctl_hi_val = 0x4000,
};
struct apss_pll_data {
int pll_type;
struct clk_alpha_pll *pll;
const struct alpha_pll_config *pll_config;
};
static struct apss_pll_data ipq5332_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
.pll_config = &ipq5332_pll_config,
};
static struct apss_pll_data ipq8074_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq8074_pll_config,
};
static struct apss_pll_data ipq6018_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq6018_pll_config,
};
static struct apss_pll_data ipq9574_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq9574_pll_config,
};
static const struct regmap_config ipq_pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x40,
.fast_io = true,
};
static int apss_ipq_pll_probe(struct platform_device *pdev)
{
const struct apss_pll_data *data;
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
data = of_device_get_match_data(&pdev->dev);
if (!data)
return -ENODEV;
if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
ret = devm_clk_register_regmap(dev, &data->pll->clkr);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&data->pll->clkr.hw);
}
static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
static struct platform_driver apss_ipq_pll_driver = {
.probe = apss_ipq_pll_probe,
.driver = {
.name = "qcom-ipq-apss-pll",
.of_match_table = apss_ipq_pll_match_table,
},
};
module_platform_driver(apss_ipq_pll_driver);
MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/apss-ipq-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016, Linaro Limited
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/soc/qcom/smd-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \
type, r_id, key, ao_rate, ao_flags) \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
.rpm_res_type = (type), \
.rpm_clk_id = (r_id), \
.rpm_key = (key), \
.peer = &clk_smd_rpm_##_prefix##_active, \
.rate = INT_MAX, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_name, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}; \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \
.rpm_res_type = (type), \
.rpm_clk_id = (r_id), \
.active_only = true, \
.rpm_key = (key), \
.peer = &clk_smd_rpm_##_prefix##_name, \
.rate = (ao_rate), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_active, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
.flags = (ao_flags), \
}, \
}
#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\
ao_rate, ao_flags) \
__DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \
type, r_id, key, ao_rate, ao_flags)
#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\
type, r_id, r, key, ao_flags) \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
.rpm_res_type = (type), \
.rpm_clk_id = (r_id), \
.rpm_key = (key), \
.branch = true, \
.peer = &clk_smd_rpm_##_prefix##_active, \
.rate = (r), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_branch_ops, \
.name = #_name, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
}, \
}; \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \
.rpm_res_type = (type), \
.rpm_clk_id = (r_id), \
.active_only = true, \
.rpm_key = (key), \
.branch = true, \
.peer = &clk_smd_rpm_##_prefix##_name, \
.rate = (r), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_branch_ops, \
.name = #_active, \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
}, \
.num_parents = 1, \
.flags = (ao_flags), \
}, \
}
#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \
_name, _active, type, r_id, r, key, 0)
#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \
__DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \
_name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \
__DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \
_name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags)
#define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \
__DEFINE_CLK_SMD_RPM( \
_name##_clk_src, _name##_a_clk_src, \
type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
_name##_clk, _name##_a_clk, \
type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0)
#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
_name, _name##_a, type, \
r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags)
#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \
__DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \
QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
QCOM_RPM_KEY_SOFTWARE_ENABLE)
#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \
_name, _name##_a, \
QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
QCOM_RPM_KEY_SOFTWARE_ENABLE, 0)
#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \
DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \
__DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \
QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \
QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
static struct qcom_smd_rpm *rpmcc_smd_rpm;
struct clk_smd_rpm {
const int rpm_res_type;
const int rpm_key;
const int rpm_clk_id;
const bool active_only;
bool enabled;
bool branch;
struct clk_smd_rpm *peer;
struct clk_hw hw;
unsigned long rate;
};
struct rpm_smd_clk_desc {
struct clk_smd_rpm **clks;
size_t num_clks;
/*
* Interconnect clocks are managed by the icc framework, this driver
* only kickstarts them so that they don't get gated between
* clk_smd_rpm_enable_scaling() and interconnect driver initialization.
*/
const struct clk_smd_rpm ** const icc_clks;
size_t num_icc_clks;
bool scaling_before_handover;
};
static DEFINE_MUTEX(rpm_smd_clk_lock);
static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r)
{
int ret;
struct clk_smd_rpm_req req = {
.key = cpu_to_le32(r->rpm_key),
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(r->branch ? 1 : INT_MAX),
};
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
r->rpm_res_type, r->rpm_clk_id, &req,
sizeof(req));
if (ret)
return ret;
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
r->rpm_res_type, r->rpm_clk_id, &req,
sizeof(req));
if (ret)
return ret;
return 0;
}
static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
unsigned long rate)
{
struct clk_smd_rpm_req req = {
.key = cpu_to_le32(r->rpm_key),
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
};
return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
r->rpm_res_type, r->rpm_clk_id, &req,
sizeof(req));
}
static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
unsigned long rate)
{
struct clk_smd_rpm_req req = {
.key = cpu_to_le32(r->rpm_key),
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
};
return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
r->rpm_res_type, r->rpm_clk_id, &req,
sizeof(req));
}
static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
unsigned long *active, unsigned long *sleep)
{
*active = rate;
/*
* Active-only clocks don't care what the rate is during sleep. So,
* they vote for zero.
*/
if (r->active_only)
*sleep = 0;
else
*sleep = *active;
}
static int clk_smd_rpm_prepare(struct clk_hw *hw)
{
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
struct clk_smd_rpm *peer = r->peer;
unsigned long this_rate = 0, this_sleep_rate = 0;
unsigned long peer_rate = 0, peer_sleep_rate = 0;
unsigned long active_rate, sleep_rate;
int ret = 0;
mutex_lock(&rpm_smd_clk_lock);
/* Don't send requests to the RPM if the rate has not been set. */
if (!r->rate)
goto out;
to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
/* Take peer clock's rate into account only if it's enabled. */
if (peer->enabled)
to_active_sleep(peer, peer->rate,
&peer_rate, &peer_sleep_rate);
active_rate = max(this_rate, peer_rate);
if (r->branch)
active_rate = !!active_rate;
ret = clk_smd_rpm_set_rate_active(r, active_rate);
if (ret)
goto out;
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
if (r->branch)
sleep_rate = !!sleep_rate;
ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
if (ret)
/* Undo the active set vote and restore it */
ret = clk_smd_rpm_set_rate_active(r, peer_rate);
out:
if (!ret)
r->enabled = true;
mutex_unlock(&rpm_smd_clk_lock);
return ret;
}
static void clk_smd_rpm_unprepare(struct clk_hw *hw)
{
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
struct clk_smd_rpm *peer = r->peer;
unsigned long peer_rate = 0, peer_sleep_rate = 0;
unsigned long active_rate, sleep_rate;
int ret;
mutex_lock(&rpm_smd_clk_lock);
if (!r->rate)
goto out;
/* Take peer clock's rate into account only if it's enabled. */
if (peer->enabled)
to_active_sleep(peer, peer->rate, &peer_rate,
&peer_sleep_rate);
active_rate = r->branch ? !!peer_rate : peer_rate;
ret = clk_smd_rpm_set_rate_active(r, active_rate);
if (ret)
goto out;
sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
if (ret)
goto out;
r->enabled = false;
out:
mutex_unlock(&rpm_smd_clk_lock);
}
static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
struct clk_smd_rpm *peer = r->peer;
unsigned long active_rate, sleep_rate;
unsigned long this_rate = 0, this_sleep_rate = 0;
unsigned long peer_rate = 0, peer_sleep_rate = 0;
int ret = 0;
mutex_lock(&rpm_smd_clk_lock);
if (!r->enabled)
goto out;
to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
/* Take peer clock's rate into account only if it's enabled. */
if (peer->enabled)
to_active_sleep(peer, peer->rate,
&peer_rate, &peer_sleep_rate);
active_rate = max(this_rate, peer_rate);
ret = clk_smd_rpm_set_rate_active(r, active_rate);
if (ret)
goto out;
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
if (ret)
goto out;
r->rate = rate;
out:
mutex_unlock(&rpm_smd_clk_lock);
return ret;
}
static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
/*
* RPM handles rate rounding and we don't have a way to
* know what the rate will be, so just return whatever
* rate is requested.
*/
return rate;
}
static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
/*
* RPM handles rate rounding and we don't have a way to
* know what the rate will be, so just return whatever
* rate was set.
*/
return r->rate;
}
static int clk_smd_rpm_enable_scaling(void)
{
int ret;
struct clk_smd_rpm_req req = {
.key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(1),
};
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,
QCOM_SMD_RPM_MISC_CLK,
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
if (ret) {
pr_err("RPM clock scaling (sleep set) not enabled!\n");
return ret;
}
ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,
QCOM_SMD_RPM_MISC_CLK,
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
if (ret) {
pr_err("RPM clock scaling (active set) not enabled!\n");
return ret;
}
pr_debug("%s: RPM clock scaling is enabled\n", __func__);
return 0;
}
static const struct clk_ops clk_smd_rpm_ops = {
.prepare = clk_smd_rpm_prepare,
.unprepare = clk_smd_rpm_unprepare,
.set_rate = clk_smd_rpm_set_rate,
.round_rate = clk_smd_rpm_round_rate,
.recalc_rate = clk_smd_rpm_recalc_rate,
};
static const struct clk_ops clk_smd_rpm_branch_ops = {
.prepare = clk_smd_rpm_prepare,
.unprepare = clk_smd_rpm_unprepare,
.recalc_rate = clk_smd_rpm_recalc_rate,
};
/* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */
DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL);
DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1);
DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0);
DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1);
DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2);
DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL);
DEFINE_CLK_SMD_RPM_BUS(snoc, 1);
DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2);
DEFINE_CLK_SMD_RPM_BUS(cnoc, 2);
DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3);
DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0);
DEFINE_CLK_SMD_RPM_BUS(cnoc, 1);
DEFINE_CLK_SMD_RPM_BUS(snoc, 2);
DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5);
DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0);
DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2);
DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0);
DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1);
DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2);
DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0);
DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0);
DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0);
DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0);
DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1);
DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0);
DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0);
DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);
static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_0_pcnoc_clk,
};
static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_0_pcnoc_clk,
&clk_smd_rpm_bus_1_snoc_clk,
};
static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_0_pcnoc_clk,
&clk_smd_rpm_bus_1_snoc_clk,
&clk_smd_rpm_bus_2_sysmmnoc_clk,
};
static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_0_pcnoc_clk,
&clk_smd_rpm_bus_1_snoc_clk,
&clk_smd_rpm_bus_2_cnoc_clk,
&clk_smd_rpm_ocmemgx_clk,
};
static const struct clk_smd_rpm *msm8996_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_branch_aggre1_noc_clk,
&clk_smd_rpm_branch_aggre2_noc_clk,
&clk_smd_rpm_bus_0_pcnoc_clk,
&clk_smd_rpm_bus_1_snoc_clk,
&clk_smd_rpm_bus_2_cnoc_clk,
&clk_smd_rpm_mmssnoc_axi_rpm_clk,
};
static const struct clk_smd_rpm *msm8998_icc_clks[] = {
&clk_smd_rpm_aggre1_noc_clk,
&clk_smd_rpm_aggre2_noc_clk,
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_1_snoc_clk,
&clk_smd_rpm_bus_2_cnoc_clk,
&clk_smd_rpm_mmssnoc_axi_rpm_clk,
};
static const struct clk_smd_rpm *sdm660_icc_clks[] = {
&clk_smd_rpm_aggre2_noc_clk,
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_1_snoc_clk,
&clk_smd_rpm_bus_2_cnoc_clk,
&clk_smd_rpm_mmssnoc_axi_rpm_clk,
};
static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
&clk_smd_rpm_bimc_clk,
&clk_smd_rpm_bus_1_cnoc_clk,
&clk_smd_rpm_mmnrt_clk,
&clk_smd_rpm_mmrt_clk,
&clk_smd_rpm_qup_clk,
&clk_smd_rpm_bus_2_snoc_clk,
};
static struct clk_smd_rpm *msm8909_clks[] = {
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
.clks = msm8909_clks,
.num_clks = ARRAY_SIZE(msm8909_clks),
.icc_clks = bimc_pcnoc_snoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
};
static struct clk_smd_rpm *msm8916_clks[] = {
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
.clks = msm8916_clks,
.num_clks = ARRAY_SIZE(msm8916_clks),
.icc_clks = bimc_pcnoc_snoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
};
static struct clk_smd_rpm *msm8917_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
.clks = msm8917_clks,
.num_clks = ARRAY_SIZE(msm8917_clks),
.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *msm8936_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
.clks = msm8936_clks,
.num_clks = ARRAY_SIZE(msm8936_clks),
.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *msm8974_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0,
[RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a,
[RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1,
[RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a,
[RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0,
[RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a,
[RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1,
[RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a,
[RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2,
[RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a,
[RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk,
[RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin,
[RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin,
[RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin,
[RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin,
[RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin,
[RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin,
[RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin,
[RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin,
[RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin,
[RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
.clks = msm8974_clks,
.num_clks = ARRAY_SIZE(msm8974_clks),
.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
.scaling_before_handover = true,
};
static struct clk_smd_rpm *msm8976_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
.clks = msm8976_clks,
.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *msm8992_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
[RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
[RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk,
[RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk,
[RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
.clks = msm8992_clks,
.num_clks = ARRAY_SIZE(msm8992_clks),
.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
};
static struct clk_smd_rpm *msm8994_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
[RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
[RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk,
[RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk,
[RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk,
[RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk,
[RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
.clks = msm8994_clks,
.num_clks = ARRAY_SIZE(msm8994_clks),
.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
};
static struct clk_smd_rpm *msm8996_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
.clks = msm8996_clks,
.num_clks = ARRAY_SIZE(msm8996_clks),
.icc_clks = msm8996_icc_clks,
.num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),
};
static struct clk_smd_rpm *qcs404_clks[] = {
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,
[RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,
[RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin,
[RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
.clks = qcs404_clks,
.num_clks = ARRAY_SIZE(qcs404_clks),
.icc_clks = bimc_pcnoc_snoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
};
static struct clk_smd_rpm *msm8998_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,
[RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1,
[RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
[RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
[RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin,
[RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin,
[RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin,
[RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
[RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
[RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3,
[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
[RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin,
[RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
.clks = msm8998_clks,
.num_clks = ARRAY_SIZE(msm8998_clks),
.icc_clks = msm8998_icc_clks,
.num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
};
static struct clk_smd_rpm *sdm660_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
[RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,
[RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1,
[RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
[RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin,
[RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin,
[RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin,
[RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
[RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
[RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
.clks = sdm660_clks,
.num_clks = ARRAY_SIZE(sdm660_clks),
.icc_clks = sdm660_icc_clks,
.num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),
};
static struct clk_smd_rpm *mdm9607_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
.clks = mdm9607_clks,
.num_clks = ARRAY_SIZE(mdm9607_clks),
.icc_clks = bimc_pcnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),
};
static struct clk_smd_rpm *msm8953_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk,
[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
.clks = msm8953_clks,
.num_clks = ARRAY_SIZE(msm8953_clks),
.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *sm6125_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1,
[RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a,
[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
[RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
[RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
.clks = sm6125_clks,
.num_clks = ARRAY_SIZE(sm6125_clks),
.icc_clks = sm_qnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
/* SM6115 */
static struct clk_smd_rpm *sm6115_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
[RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
[RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,
[RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,
[RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,
[RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
.clks = sm6115_clks,
.num_clks = ARRAY_SIZE(sm6115_clks),
.icc_clks = sm_qnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
static struct clk_smd_rpm *sm6375_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
[RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk,
[RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk,
[RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk,
[RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,
[RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log,
};
static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
.clks = sm6375_clks,
.num_clks = ARRAY_SIZE(sm6375_clks),
.icc_clks = sm_qnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
static struct clk_smd_rpm *qcm2290_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
[RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
[RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk,
[RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk,
[RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk,
[RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,
[RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
[RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk,
[RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk,
};
static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
.clks = qcm2290_clks,
.num_clks = ARRAY_SIZE(qcm2290_clks),
.icc_clks = sm_qnoc_icc_clks,
.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
{ .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
{ .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
{ .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 },
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
{ .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
{ .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
{ .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
{ .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
{ .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
{ .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },
{ .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },
{ .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
const struct rpm_smd_clk_desc *desc = data;
unsigned int idx = clkspec->args[0];
if (idx >= desc->num_clks) {
pr_err("%s: invalid index %u\n", __func__, idx);
return ERR_PTR(-EINVAL);
}
return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
}
static void rpm_smd_unregister_icc(void *data)
{
struct platform_device *icc_pdev = data;
platform_device_unregister(icc_pdev);
}
static int rpm_smd_clk_probe(struct platform_device *pdev)
{
int ret;
size_t num_clks, i;
struct clk_smd_rpm **rpm_smd_clks;
const struct rpm_smd_clk_desc *desc;
struct platform_device *icc_pdev;
rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
if (!rpmcc_smd_rpm) {
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
return -ENODEV;
}
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
rpm_smd_clks = desc->clks;
num_clks = desc->num_clks;
if (desc->scaling_before_handover) {
ret = clk_smd_rpm_enable_scaling();
if (ret)
goto err;
}
for (i = 0; i < num_clks; i++) {
if (!rpm_smd_clks[i])
continue;
ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
if (ret)
goto err;
}
for (i = 0; i < desc->num_icc_clks; i++) {
if (!desc->icc_clks[i])
continue;
ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
if (ret)
goto err;
}
if (!desc->scaling_before_handover) {
ret = clk_smd_rpm_enable_scaling();
if (ret)
goto err;
}
for (i = 0; i < num_clks; i++) {
if (!rpm_smd_clks[i])
continue;
ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
if (ret)
goto err;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
(void *)desc);
if (ret)
goto err;
icc_pdev = platform_device_register_data(pdev->dev.parent,
"icc_smd_rpm", -1, NULL, 0);
if (IS_ERR(icc_pdev)) {
dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n",
icc_pdev);
/* No need to unregister clocks because of this */
} else {
ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc,
icc_pdev);
if (ret)
goto err;
}
return 0;
err:
dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
return ret;
}
static struct platform_driver rpm_smd_clk_driver = {
.driver = {
.name = "qcom-clk-smd-rpm",
.of_match_table = rpm_smd_clk_match_table,
},
.probe = rpm_smd_clk_probe,
};
static int __init rpm_smd_clk_init(void)
{
return platform_driver_register(&rpm_smd_clk_driver);
}
core_initcall(rpm_smd_clk_init);
static void __exit rpm_smd_clk_exit(void)
{
platform_driver_unregister(&rpm_smd_clk_driver);
}
module_exit(rpm_smd_clk_exit);
MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:qcom-clk-smd-rpm");
| linux-master | drivers/clk/qcom/clk-smd-rpm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_AUX2,
P_GPLL0_OUT_EARLY,
P_GPLL10_OUT_MAIN,
P_GPLL11_OUT_AUX,
P_GPLL11_OUT_AUX2,
P_GPLL11_OUT_MAIN,
P_GPLL3_OUT_EARLY,
P_GPLL3_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL5_OUT_MAIN,
P_GPLL6_OUT_EARLY,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_GPLL8_OUT_EARLY,
P_GPLL8_OUT_MAIN,
P_GPLL9_OUT_EARLY,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct pll_vco brammo_vco[] = {
{ 500000000, 1250000000, 0 },
};
static const struct pll_vco default_vco[] = {
{ 500000000, 1000000000, 2 },
};
static const struct pll_vco spark_vco[] = {
{ 750000000, 1500000000, 1 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_aux2",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
/* 1152MHz configuration */
static const struct alpha_pll_config gpll10_config = {
.l = 0x3c,
.alpha = 0x0,
.vco_val = 0x1 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
};
static struct clk_alpha_pll gpll10 = {
.offset = 0xa000,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gpll10",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
/* 532MHz configuration */
static const struct alpha_pll_config gpll11_config = {
.l = 0x1B,
.alpha = 0x55555555,
.alpha_hi = 0xB5,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
};
static struct clk_alpha_pll gpll11 = {
.offset = 0xb000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gpll11",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll3_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll3_out_main = {
.offset = 0x3000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll3_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll5",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll6_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll6_out_main = {
.offset = 0x6000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll6_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
/* 533.2MHz configuration */
static const struct alpha_pll_config gpll8_config = {
.l = 0x1B,
.alpha = 0x55555555,
.alpha_hi = 0xC5,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
};
static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gpll8",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll8_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll8_out_main = {
.offset = 0x8000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll8_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll8_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
/* 1152MHz configuration */
static const struct alpha_pll_config gpll9_config = {
.l = 0x3C,
.alpha = 0x0,
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(9, 8),
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
.config_ctl_val = 0x00004289,
.test_ctl_val = 0x08000000,
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x9000,
.vco_table = brammo_vco,
.num_vco = ARRAY_SIZE(brammo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll9_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll9_out_main = {
.offset = 0x9000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll9_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll9_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
};
static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL6_OUT_MAIN, 4 },
};
static const struct clk_parent_data gcc_parents_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll6_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL9_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parents_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parents_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll3_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll8_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parents_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll8_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL6_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll6_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_9[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll8_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL6_OUT_EARLY, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parents_10[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll3_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parents_12[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_13[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL11_OUT_MAIN, 1 },
{ P_GPLL11_OUT_AUX, 2 },
{ P_GPLL11_OUT_AUX2, 3 },
};
static const struct clk_parent_data gcc_parents_14[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll11.clkr.hw },
{ .hw = &gpll11.clkr.hw },
{ .hw = &gpll11.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x1a034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = {
.reg = 0x1a04c,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv",
.parent_hws = (const struct clk_hw *[])
{ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_axi_clk_src = {
.cmd_rcgr = 0x5802c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_cci_clk_src = {
.cmd_rcgr = 0x56000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_camss_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk_src",
.parent_data = gcc_parents_9,
.num_parents = ARRAY_SIZE(gcc_parents_9),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.cmd_rcgr = 0x45000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.cmd_rcgr = 0x4501c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2),
{ }
};
static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.cmd_rcgr = 0x5101c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.cmd_rcgr = 0x51038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.cmd_rcgr = 0x51054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
.cmd_rcgr = 0x55024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_clk_src = {
.cmd_rcgr = 0x55004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_ope_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
.cmd_rcgr = 0x52004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
.cmd_rcgr = 0x52094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
.cmd_rcgr = 0x52024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
.cmd_rcgr = 0x520b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),
F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
.cmd_rcgr = 0x52064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_cphy_rx_clk_src",
.parent_data = gcc_parents_10,
.num_parents = ARRAY_SIZE(gcc_parents_10),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
.cmd_rcgr = 0x58010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x4d004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x4e004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x4f004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x20010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x1f148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x1f278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x1f3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x1f4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x1f608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x1f738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x38028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x38010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_12,
.num_parents = ARRAY_SIZE(gcc_parents_12),
.ops = &clk_rcg2_floor_ops,
.flags = CLK_OPS_PARENT_ENABLE,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x1a01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x1a060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_13,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parents_13,
.num_parents = ARRAY_SIZE(gcc_parents_13),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_video_venus_clk_src = {
.cmd_rcgr = 0x58060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_14,
.freq_tbl = ftbl_gcc_video_venus_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_clk_src",
.parent_data = gcc_parents_14,
.num_parents = ARRAY_SIZE(gcc_parents_14),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch gcc_ahb2phy_csi_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x1d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_csi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy_usb_clk = {
.halt_reg = 0x1d008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1d008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_usb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_nrt_clk = {
.halt_reg = 0x17070,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17070,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_nrt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_rt_clk = {
.halt_reg = 0x1706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_rt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_axi_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_camnoc_atb_clk = {
.halt_reg = 0x5804c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x5804c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5804c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_camnoc_atb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
.halt_reg = 0x58050,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x58050,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_camnoc_nts_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_0_clk = {
.halt_reg = 0x56018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_0_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_cci_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_0_clk = {
.halt_reg = 0x52088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_0_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_1_clk = {
.halt_reg = 0x5208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5208c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_1_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x45018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_csi0phytimer_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x45034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_csi1phytimer_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_mclk0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x51034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_mclk1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x51050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_mclk2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk3_clk = {
.halt_reg = 0x5106c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5106c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_mclk3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_nrt_axi_clk = {
.halt_reg = 0x58054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_ahb_clk = {
.halt_reg = 0x5503c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5503c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_ope_ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_clk = {
.halt_reg = 0x5501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_ope_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_rt_axi_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_clk = {
.halt_reg = 0x5201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
.halt_reg = 0x5207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_csid_clk = {
.halt_reg = 0x520ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_0_csid_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_clk = {
.halt_reg = 0x5203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
.halt_reg = 0x52080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_csid_clk = {
.halt_reg = 0x520cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_tfe_1_csid_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x58028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_camss_top_ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a084,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1a084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
.reg = 0x17058,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[])
{ &gcc_disp_gpll0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_core_clk = {
.halt_reg = 0x17064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x4d000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x4e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x4f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x36004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[])
{ &gpll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[])
{ &gpll0_out_aux2.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_clk = {
.halt_reg = 0x36100,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x36100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x3600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x36018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_throttle_core_clk = {
.halt_reg = 0x36048,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36048,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(31),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_throttle_core_clk",
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x20004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pwm0_xo512_clk = {
.halt_reg = 0x2002c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2002c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pwm0_xo512_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x17060,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17060,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
.halt_reg = 0x36040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x17010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x1f014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1f00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1f144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1f274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1f3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1f4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x1f604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x1f734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x38008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x3800c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3800c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_sdcc1_ice_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x2b06c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b06c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a080,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1a080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x1a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x1a018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x1a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x9f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x1a054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x1a058,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1a058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vcodec0_axi_clk = {
.halt_reg = 0x6e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vcodec0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ahb_clk = {
.halt_reg = 0x6e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ctl_axi_clk = {
.halt_reg = 0x6e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1701c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_core_clk = {
.halt_reg = 0x17068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_vcodec0_sys_clk = {
.halt_reg = 0x580a4,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x580a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x580a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_vcodec0_sys_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_video_venus_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_venus_ctl_clk = {
.halt_reg = 0x5808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_ctl_clk",
.parent_hws = (const struct clk_hw *[])
{ &gcc_video_venus_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gcc_camss_top_gdsc = {
.gdscr = 0x58004,
.pd = {
.name = "gcc_camss_top",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_usb30_prim_gdsc = {
.gdscr = 0x1a004,
.pd = {
.name = "gcc_usb30_prim",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_vcodec0_gdsc = {
.gdscr = 0x58098,
.pd = {
.name = "gcc_vcodec0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_venus_gdsc = {
.gdscr = 0x5807c,
.pd = {
.name = "gcc_venus",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
.gdscr = 0x7d060,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu1",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
.gdscr = 0x7d07c,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu0",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
.gdscr = 0x7d074,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_rt",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
.gdscr = 0x7d078,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_qcm2290_clocks[] = {
[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
[GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] =
&gcc_usb30_prim_mock_utmi_postdiv.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL10] = &gpll10.clkr,
[GPLL11] = &gpll11.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL5] = &gpll5.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL8] = &gpll8.clkr,
[GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
[GPLL9] = &gpll9.clkr,
[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
};
static const struct qcom_reset_map gcc_qcm2290_resets[] = {
[GCC_CAMSS_OPE_BCR] = { 0x55000 },
[GCC_CAMSS_TFE_BCR] = { 0x52000 },
[GCC_CAMSS_TOP_BCR] = { 0x58000 },
[GCC_GPU_BCR] = { 0x36000 },
[GCC_MMSS_BCR] = { 0x17000 },
[GCC_PDM_BCR] = { 0x20000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
[GCC_SDCC1_BCR] = { 0x38000 },
[GCC_SDCC2_BCR] = { 0x1e000 },
[GCC_USB30_PRIM_BCR] = { 0x1a000 },
[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
[GCC_VCODEC0_BCR] = { 0x58094 },
[GCC_VENUS_BCR] = { 0x58078 },
[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
};
static struct gdsc *gcc_qcm2290_gdscs[] = {
[GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,
[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
[GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
[GCC_VENUS_GDSC] = &gcc_venus_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
};
static const struct regmap_config gcc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc7000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_qcm2290_desc = {
.config = &gcc_qcm2290_regmap_config,
.clks = gcc_qcm2290_clocks,
.num_clks = ARRAY_SIZE(gcc_qcm2290_clocks),
.resets = gcc_qcm2290_resets,
.num_resets = ARRAY_SIZE(gcc_qcm2290_resets),
.gdscs = gcc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs),
};
static const struct of_device_id gcc_qcm2290_match_table[] = {
{ .compatible = "qcom,gcc-qcm2290" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table);
static int gcc_qcm2290_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap);
}
static struct platform_driver gcc_qcm2290_driver = {
.probe = gcc_qcm2290_probe,
.driver = {
.name = "gcc-qcm2290",
.of_match_table = gcc_qcm2290_match_table,
},
};
static int __init gcc_qcm2290_init(void)
{
return platform_driver_register(&gcc_qcm2290_driver);
}
subsys_initcall(gcc_qcm2290_init);
static void __exit gcc_qcm2290_exit(void)
{
platform_driver_unregister(&gcc_qcm2290_driver);
}
module_exit(gcc_qcm2290_exit);
MODULE_DESCRIPTION("QTI GCC QCM2290 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-qcm2290.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022 Kernkonzept GmbH.
*
* Based on gcc-msm8916.c:
* Copyright 2015 Linaro Limited
* adapted with data from clock-gcc-8909.c in Qualcomm's msm-3.18 release:
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8909.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_XO,
DT_SLEEP_CLK,
DT_DSI0PLL,
DT_DSI0PLL_BYTE,
};
enum {
P_XO,
P_SLEEP_CLK,
P_GPLL0,
P_GPLL1,
P_GPLL2,
P_BIMC,
P_DSI0PLL,
P_DSI0PLL_BYTE,
};
static const struct parent_map gcc_xo_map[] = {
{ P_XO, 0 },
};
static const struct clk_parent_data gcc_xo_data[] = {
{ .index = DT_XO },
};
static const struct clk_parent_data gcc_sleep_clk_data[] = {
{ .index = DT_SLEEP_CLK },
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gpll0_early",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
/* Avoid rate changes for shared clock */
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll0",
.parent_hws = (const struct clk_hw*[]) {
&gpll0_early.clkr.hw,
},
.num_parents = 1,
/* Avoid rate changes for shared clock */
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
.n_reg = 0x2000c,
.config_reg = 0x20010,
.mode_reg = 0x20000,
.status_reg = 0x2001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll1",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gpll1_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_alpha_pll gpll2_early = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data) {
.name = "gpll2_early",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
/* Avoid rate changes for shared clock */
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll2",
.parent_hws = (const struct clk_hw*[]) {
&gpll2_early.clkr.hw,
},
.num_parents = 1,
/* Avoid rate changes for shared clock */
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll bimc_pll_early = {
.offset = 0x23000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "bimc_pll_early",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
/* Avoid rate changes for shared clock */
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv bimc_pll = {
.offset = 0x23000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data) {
.name = "bimc_pll",
.parent_hws = (const struct clk_hw*[]) {
&bimc_pll_early.clkr.hw,
},
.num_parents = 1,
/* Avoid rate changes for shared clock */
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_BIMC, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_bimc_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &bimc_pll.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.freq_tbl = ftbl_apss_ahb_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 bimc_ddr_clk_src = {
.cmd_rcgr = 0x32004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_rcg2 bimc_gpu_clk_src = {
.cmd_rcgr = 0x31028,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "bimc_gpu_clk_src",
.parent_data = gcc_xo_gpll0_bimc_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x06000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x07000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x06024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x07024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 72, 15625),
F(7372800, P_GPLL0, 1, 144, 15625),
F(14745600, P_GPLL0, 1, 288, 15625),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_byte0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_byte_data[] = {
{ .index = DT_XO },
{ .index = DT_DSI0PLL_BYTE },
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.hid_width = 5,
.parent_map = gcc_byte0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "byte0_clk_src",
.parent_data = gcc_byte_data,
.num_parents = ARRAY_SIZE(gcc_byte_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_gp0_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_gp1_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
F(40000000, P_GPLL0, 10, 1, 2),
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 camss_top_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_top_ahb_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_top_ahb_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.freq_tbl = ftbl_crypto_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_csi_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_map),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_esc0_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.hid_width = 5,
.freq_tbl = ftbl_esc0_clk_src,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "esc0_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_gfx3d_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
};
static const struct clk_parent_data gcc_gfx3d_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
};
static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(307200000, P_GPLL1, 4, 0, 0),
F(409600000, P_GPLL1, 3, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.freq_tbl = ftbl_gfx3d_clk_src,
.parent_map = gcc_gfx3d_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gfx3d_clk_src",
.parent_data = gcc_gfx3d_data,
.num_parents = ARRAY_SIZE(gcc_gfx3d_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_gp_clk_src[] = {
F(150000, P_XO, 1, 1, 128),
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp1_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp2_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp3_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_mclk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 3 },
};
static const struct clk_parent_data gcc_mclk_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct freq_tbl ftbl_mclk_clk_src[] = {
F(24000000, P_GPLL2, 1, 1, 33),
F(66667000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk0_clk_src",
.parent_data = gcc_mclk_data,
.num_parents = ARRAY_SIZE(gcc_mclk_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk1_clk_src",
.parent_data = gcc_mclk_data,
.num_parents = ARRAY_SIZE(gcc_mclk_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_mdp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 3 },
};
static const struct clk_parent_data gcc_mdp_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(307200000, P_GPLL1, 4, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.freq_tbl = ftbl_mdp_clk_src,
.parent_map = gcc_mdp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mdp_clk_src",
.parent_data = gcc_mdp_data,
.num_parents = ARRAY_SIZE(gcc_mdp_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_pclk0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
};
static const struct clk_parent_data gcc_pclk_data[] = {
{ .index = DT_XO },
{ .index = DT_DSI0PLL },
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pclk0_clk_src",
.parent_data = gcc_pclk_data,
.num_parents = ARRAY_SIZE(gcc_pclk_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.freq_tbl = ftbl_pdm2_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_floor_ops,
}
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_floor_ops,
}
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(57140000, P_GPLL0, 14, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_vcodec0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 3 },
};
static const struct clk_parent_data gcc_vcodec0_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
};
static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(307200000, P_GPLL1, 4, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4c000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_vcodec0_clk_src,
.parent_map = gcc_vcodec0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vcodec0_clk_src",
.parent_data = gcc_vcodec0_data,
.num_parents = ARRAY_SIZE(gcc_vcodec0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.freq_tbl = ftbl_gcc_camss_vfe0_clk,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vfe0_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_vsync_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.freq_tbl = ftbl_vsync_clk_src,
.parent_map = gcc_xo_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vsync_clk_src",
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apss_tcu_clk",
.parent_hws = (const struct clk_hw*[]) {
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x01004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_sleep_clk",
.parent_data = gcc_sleep_clk_data,
.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_gfx_tbu_clk = {
.halt_reg = 0x12010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gfx_tbu_clk",
.parent_hws = (const struct clk_hw*[]) {
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_gfx_tcu_clk = {
.halt_reg = 0x12020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gfx_tcu_clk",
.parent_hws = (const struct clk_hw*[]) {
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gtcu_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdp_tbu_clk",
.parent_hws = (const struct clk_hw*[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data) {
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data) {
.name = "gcc_smmu_cfg_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus_tbu_clk = {
.halt_reg = 0x12014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus_tbu_clk",
.parent_hws = (const struct clk_hw*[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_vfe_tbu_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data) {
.name = "gcc_vfe_tbu_clk",
.parent_hws = (const struct clk_hw*[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x31024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gfx_clk",
.parent_hws = (const struct clk_hw*[]) {
&bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x31040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gpu_clk",
.parent_hws = (const struct clk_hw*[]) {
&bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x04020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x05020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x06020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x06020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x07020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x07020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0601c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0701c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x5a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]) {
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x54018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x55018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x52018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x53018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x53018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x56004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x58038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]) {
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe_ahb_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe_axi_clk = {
.halt_reg = 0x58048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]) {
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]) {
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4d088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]) {
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb2a_phy_sleep_clk",
.parent_data = gcc_sleep_clk_data,
.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x41008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
.halt_reg = 0x41030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_hs_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_venus0_ahb_clk = {
.halt_reg = 0x4c020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_axi_clk = {
.halt_reg = 0x4c024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.halt_reg = 0x4c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_core0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]) {
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_venus0_vcodec0_clk = {
.halt_reg = 0x4c01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]) {
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.cxcs = (unsigned int []) { 0x4d080, 0x4d088 },
.cxc_count = 2,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gdsc = {
.gdscr = 0x5901c,
.cxcs = (unsigned int []) { 0x59020 },
.cxc_count = 1,
.pd = {
.name = "oxili_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.cxcs = (unsigned int []) { 0x4c024, 0x4c01c },
.cxc_count = 2,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x4c028,
.cxcs = (unsigned int []) { 0x4c02c },
.cxc_count = 1,
.pd = {
.name = "venus_core0_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe_gdsc = {
.gdscr = 0x58034,
.cxcs = (unsigned int []) { 0x58038, 0x58048, 0x58050 },
.cxc_count = 3,
.pd = {
.name = "vfe_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8909_clocks[] = {
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[GPLL2_EARLY] = &gpll2_early.clkr,
[GPLL2] = &gpll2.clkr,
[BIMC_PLL_EARLY] = &bimc_pll_early.clkr,
[BIMC_PLL] = &bimc_pll.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
[BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
};
static struct gdsc *gcc_msm8909_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
[OXILI_GDSC] = &oxili_gdsc,
[VENUS_GDSC] = &venus_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VFE_GDSC] = &vfe_gdsc,
};
static const struct qcom_reset_map gcc_msm8909_resets[] = {
[GCC_AUDIO_CORE_BCR] = { 0x1c008 },
[GCC_BLSP1_BCR] = { 0x01000 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
[GCC_BLSP1_QUP2_BCR] = { 0x03008 },
[GCC_BLSP1_QUP3_BCR] = { 0x04018 },
[GCC_BLSP1_QUP4_BCR] = { 0x05018 },
[GCC_BLSP1_QUP5_BCR] = { 0x06018 },
[GCC_BLSP1_QUP6_BCR] = { 0x07018 },
[GCC_BLSP1_UART1_BCR] = { 0x02038 },
[GCC_BLSP1_UART2_BCR] = { 0x03028 },
[GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
[GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
[GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
[GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
[GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
[GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
[GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
[GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
[GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
[GCC_CAMSS_GP0_BCR] = { 0x54014 },
[GCC_CAMSS_GP1_BCR] = { 0x55014 },
[GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
[GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
[GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
[GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
[GCC_CAMSS_TOP_BCR] = { 0x56000 },
[GCC_CAMSS_TOP_AHB_BCR] = { 0x5a018 },
[GCC_CAMSS_VFE_BCR] = { 0x58030 },
[GCC_CRYPTO_BCR] = { 0x16000 },
[GCC_MDSS_BCR] = { 0x4d074 },
[GCC_OXILI_BCR] = { 0x59018 },
[GCC_PDM_BCR] = { 0x44000 },
[GCC_PRNG_BCR] = { 0x13000 },
[GCC_QUSB2_PHY_BCR] = { 0x4103c },
[GCC_SDCC1_BCR] = { 0x42000 },
[GCC_SDCC2_BCR] = { 0x43000 },
[GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
[GCC_USB2A_PHY_BCR] = { 0x41028 },
[GCC_USB2_HS_PHY_ONLY_BCR] = { .reg = 0x41034, .udelay = 15 },
[GCC_USB_HS_BCR] = { 0x41000 },
[GCC_VENUS0_BCR] = { 0x4c014 },
/* Subsystem Restart */
[GCC_MSS_RESTART] = { 0x3e000 },
};
static const struct regmap_config gcc_msm8909_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8909_desc = {
.config = &gcc_msm8909_regmap_config,
.clks = gcc_msm8909_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8909_clocks),
.resets = gcc_msm8909_resets,
.num_resets = ARRAY_SIZE(gcc_msm8909_resets),
.gdscs = gcc_msm8909_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8909_gdscs),
};
static const struct of_device_id gcc_msm8909_match_table[] = {
{ .compatible = "qcom,gcc-msm8909" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8909_match_table);
static int gcc_msm8909_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gcc_msm8909_desc);
}
static struct platform_driver gcc_msm8909_driver = {
.probe = gcc_msm8909_probe,
.driver = {
.name = "gcc-msm8909",
.of_match_table = gcc_msm8909_match_table,
},
};
static int __init gcc_msm8909_init(void)
{
return platform_driver_register(&gcc_msm8909_driver);
}
core_initcall(gcc_msm8909_init);
static void __exit gcc_msm8909_exit(void)
{
platform_driver_unregister(&gcc_msm8909_driver);
}
module_exit(gcc_msm8909_exit);
MODULE_DESCRIPTION("Qualcomm GCC MSM8909 Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:gcc-msm8909");
| linux-master | drivers/clk/qcom/gcc-msm8909.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <asm/div64.h>
#include "clk-rcg.h"
#include "common.h"
static u32 ns_to_src(struct src_sel *s, u32 ns)
{
ns >>= s->src_sel_shift;
ns &= SRC_SEL_MASK;
return ns;
}
static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
{
u32 mask;
mask = SRC_SEL_MASK;
mask <<= s->src_sel_shift;
ns &= ~mask;
ns |= src << s->src_sel_shift;
return ns;
}
static u8 clk_rcg_get_parent(struct clk_hw *hw)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
int num_parents = clk_hw_get_num_parents(hw);
u32 ns;
int i, ret;
ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
if (ret)
goto err;
ns = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++)
if (ns == rcg->s.parent_map[i].cfg)
return i;
err:
pr_debug("%s: Clock %s has invalid parent, using default.\n",
__func__, clk_hw_get_name(hw));
return 0;
}
static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
{
bank &= BIT(rcg->mux_sel_bit);
return !!bank;
}
static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
{
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
int num_parents = clk_hw_get_num_parents(hw);
u32 ns, reg;
int bank;
int i, ret;
struct src_sel *s;
ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
if (ret)
goto err;
bank = reg_to_bank(rcg, reg);
s = &rcg->s[bank];
ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
if (ret)
goto err;
ns = ns_to_src(s, ns);
for (i = 0; i < num_parents; i++)
if (ns == s->parent_map[i].cfg)
return i;
err:
pr_debug("%s: Clock %s has invalid parent, using default.\n",
__func__, clk_hw_get_name(hw));
return 0;
}
static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
u32 ns;
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
return 0;
}
static u32 md_to_m(struct mn *mn, u32 md)
{
md >>= mn->m_val_shift;
md &= BIT(mn->width) - 1;
return md;
}
static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
{
ns >>= p->pre_div_shift;
ns &= BIT(p->pre_div_width) - 1;
return ns;
}
static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
{
u32 mask;
mask = BIT(p->pre_div_width) - 1;
mask <<= p->pre_div_shift;
ns &= ~mask;
ns |= pre_div << p->pre_div_shift;
return ns;
}
static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
{
u32 mask, mask_w;
mask_w = BIT(mn->width) - 1;
mask = (mask_w << mn->m_val_shift) | mask_w;
md &= ~mask;
if (n) {
m <<= mn->m_val_shift;
md |= m;
md |= ~n & mask_w;
}
return md;
}
static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
{
ns = ~ns >> mn->n_val_shift;
ns &= BIT(mn->width) - 1;
return ns + m;
}
static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
{
val >>= mn->mnctr_mode_shift;
val &= MNCTR_MODE_MASK;
return val;
}
static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
{
u32 mask;
mask = BIT(mn->width) - 1;
mask <<= mn->n_val_shift;
ns &= ~mask;
if (n) {
n = n - m;
n = ~n;
n &= BIT(mn->width) - 1;
n <<= mn->n_val_shift;
ns |= n;
}
return ns;
}
static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
{
u32 mask;
mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
mask |= BIT(mn->mnctr_en_bit);
val &= ~mask;
if (n) {
val |= BIT(mn->mnctr_en_bit);
val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
}
return val;
}
static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
{
u32 ns, md, reg;
int bank, new_bank, ret, index;
struct mn *mn;
struct pre_div *p;
struct src_sel *s;
bool enabled;
u32 md_reg, ns_reg;
bool banked_mn = !!rcg->mn[1].width;
bool banked_p = !!rcg->p[1].pre_div_width;
struct clk_hw *hw = &rcg->clkr.hw;
enabled = __clk_is_enabled(hw->clk);
ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
if (ret)
return ret;
bank = reg_to_bank(rcg, reg);
new_bank = enabled ? !bank : bank;
ns_reg = rcg->ns_reg[new_bank];
ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
if (ret)
return ret;
if (banked_mn) {
mn = &rcg->mn[new_bank];
md_reg = rcg->md_reg[new_bank];
ns |= BIT(mn->mnctr_reset_bit);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
if (ret)
return ret;
md = mn_to_md(mn, f->m, f->n, md);
ret = regmap_write(rcg->clkr.regmap, md_reg, md);
if (ret)
return ret;
ns = mn_to_ns(mn, f->m, f->n, ns);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
/* Two NS registers means mode control is in NS register */
if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
ns = mn_to_reg(mn, f->m, f->n, ns);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
} else {
reg = mn_to_reg(mn, f->m, f->n, reg);
ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
reg);
if (ret)
return ret;
}
ns &= ~BIT(mn->mnctr_reset_bit);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
}
if (banked_p) {
p = &rcg->p[new_bank];
ns = pre_div_to_ns(p, f->pre_div - 1, ns);
}
s = &rcg->s[new_bank];
index = qcom_find_src_index(hw, s->parent_map, f->src);
if (index < 0)
return index;
ns = src_to_ns(s, s->parent_map[index].cfg, ns);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
if (enabled) {
ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
if (ret)
return ret;
reg ^= BIT(rcg->mux_sel_bit);
ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
if (ret)
return ret;
}
return 0;
}
static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
u32 ns, md, reg;
int bank;
struct freq_tbl f = { 0 };
bool banked_mn = !!rcg->mn[1].width;
bool banked_p = !!rcg->p[1].pre_div_width;
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
bank = reg_to_bank(rcg, reg);
regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
if (banked_mn) {
regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
f.m = md_to_m(&rcg->mn[bank], md);
f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
}
if (banked_p)
f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
return configure_bank(rcg, &f);
}
/*
* Calculate m/n:d rate
*
* parent_rate m
* rate = ----------- x ---
* pre_div n
*/
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
{
if (pre_div)
rate /= pre_div + 1;
if (mode) {
u64 tmp = rate;
tmp *= m;
do_div(tmp, n);
rate = tmp;
}
return rate;
}
static unsigned long
clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
struct mn *mn = &rcg->mn;
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
pre_div = ns_to_pre_div(&rcg->p, ns);
if (rcg->mn.width) {
regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
m = md_to_m(mn, md);
n = ns_m_to_n(mn, ns, m);
/* MN counter mode is in hw.enable_reg sometimes */
if (rcg->clkr.enable_reg != rcg->ns_reg)
regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
else
mode = ns;
mode = reg_to_mnctr_mode(mn, mode);
}
return calc_rate(parent_rate, m, n, mode, pre_div);
}
static unsigned long
clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
u32 m, n, pre_div, ns, md, mode, reg;
int bank;
struct mn *mn;
bool banked_p = !!rcg->p[1].pre_div_width;
bool banked_mn = !!rcg->mn[1].width;
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
bank = reg_to_bank(rcg, reg);
regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
m = n = pre_div = mode = 0;
if (banked_mn) {
mn = &rcg->mn[bank];
regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
m = md_to_m(mn, md);
n = ns_m_to_n(mn, ns, m);
/* Two NS registers means mode control is in NS register */
if (rcg->ns_reg[0] != rcg->ns_reg[1])
reg = ns;
mode = reg_to_mnctr_mode(mn, reg);
}
if (banked_p)
pre_div = ns_to_pre_div(&rcg->p[bank], ns);
return calc_rate(parent_rate, m, n, mode, pre_div);
}
static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
struct clk_rate_request *req,
const struct parent_map *parent_map)
{
unsigned long clk_flags, rate = req->rate;
struct clk_hw *p;
int index;
f = qcom_find_freq(f, rate);
if (!f)
return -EINVAL;
index = qcom_find_src_index(hw, parent_map, f->src);
if (index < 0)
return index;
clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index);
if (clk_flags & CLK_SET_RATE_PARENT) {
rate = rate * f->pre_div;
if (f->n) {
u64 tmp = rate;
tmp = tmp * f->n;
do_div(tmp, f->m);
rate = tmp;
}
} else {
rate = clk_hw_get_rate(p);
}
req->best_parent_hw = p;
req->best_parent_rate = rate;
req->rate = f->freq;
return 0;
}
static int clk_rcg_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,
rcg->s.parent_map);
}
static int clk_dyn_rcg_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
u32 reg;
int bank;
struct src_sel *s;
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
bank = reg_to_bank(rcg, reg);
s = &rcg->s[bank];
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);
}
static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
const struct freq_tbl *f = rcg->freq_tbl;
struct clk_hw *p;
int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
req->best_parent_rate = clk_hw_round_rate(p, req->rate);
req->rate = req->best_parent_rate;
return 0;
}
static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
{
u32 ns, md, ctl;
struct mn *mn = &rcg->mn;
u32 mask = 0;
unsigned int reset_reg;
if (rcg->mn.reset_in_cc)
reset_reg = rcg->clkr.enable_reg;
else
reset_reg = rcg->ns_reg;
if (rcg->mn.width) {
mask = BIT(mn->mnctr_reset_bit);
regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
md = mn_to_md(mn, f->m, f->n, md);
regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
/* MN counter mode is in hw.enable_reg sometimes */
if (rcg->clkr.enable_reg != rcg->ns_reg) {
regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
ctl = mn_to_reg(mn, f->m, f->n, ctl);
regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
} else {
ns = mn_to_reg(mn, f->m, f->n, ns);
}
ns = mn_to_ns(mn, f->m, f->n, ns);
} else {
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
}
ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
return 0;
}
static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
const struct freq_tbl *f;
f = qcom_find_freq(rcg->freq_tbl, rate);
if (!f)
return -EINVAL;
return __clk_rcg_set_rate(rcg, f);
}
static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
const struct freq_tbl *f;
f = qcom_find_freq_floor(rcg->freq_tbl, rate);
if (!f)
return -EINVAL;
return __clk_rcg_set_rate(rcg, f);
}
static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
}
static int clk_rcg_bypass2_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw *p;
p = req->best_parent_hw;
req->best_parent_rate = clk_hw_round_rate(p, req->rate);
req->rate = req->best_parent_rate;
return 0;
}
static int clk_rcg_bypass2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
struct freq_tbl f = { 0 };
u32 ns, src;
int i, ret, num_parents = clk_hw_get_num_parents(hw);
ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
if (ret)
return ret;
src = ns_to_src(&rcg->s, ns);
f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;
for (i = 0; i < num_parents; i++) {
if (src == rcg->s.parent_map[i].cfg) {
f.src = rcg->s.parent_map[i].src;
return __clk_rcg_set_rate(rcg, &f);
}
}
return -EINVAL;
}
static int clk_rcg_bypass2_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
/* Read the hardware to determine parent during set_rate */
return clk_rcg_bypass2_set_rate(hw, rate, parent_rate);
}
struct frac_entry {
int num;
int den;
};
static const struct frac_entry pixel_table[] = {
{ 1, 2 },
{ 1, 3 },
{ 3, 16 },
{ }
};
static int clk_rcg_pixel_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
int delta = 100000;
const struct frac_entry *frac = pixel_table;
unsigned long request, src_rate;
for (; frac->num; frac++) {
request = (req->rate * frac->den) / frac->num;
src_rate = clk_hw_round_rate(req->best_parent_hw, request);
if ((src_rate < (request - delta)) ||
(src_rate > (request + delta)))
continue;
req->best_parent_rate = src_rate;
req->rate = (src_rate * frac->num) / frac->den;
return 0;
}
return -EINVAL;
}
static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
int delta = 100000;
const struct frac_entry *frac = pixel_table;
unsigned long request;
struct freq_tbl f = { 0 };
u32 ns, src;
int i, ret, num_parents = clk_hw_get_num_parents(hw);
ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
if (ret)
return ret;
src = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++) {
if (src == rcg->s.parent_map[i].cfg) {
f.src = rcg->s.parent_map[i].src;
break;
}
}
/* bypass the pre divider */
f.pre_div = 1;
/* let us find appropriate m/n values for this */
for (; frac->num; frac++) {
request = (rate * frac->den) / frac->num;
if ((parent_rate < (request - delta)) ||
(parent_rate > (request + delta)))
continue;
f.m = frac->num;
f.n = frac->den;
return __clk_rcg_set_rate(rcg, &f);
}
return -EINVAL;
}
static int clk_rcg_pixel_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return clk_rcg_pixel_set_rate(hw, rate, parent_rate);
}
static int clk_rcg_esc_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
int pre_div_max = BIT(rcg->p.pre_div_width);
int div;
unsigned long src_rate;
if (req->rate == 0)
return -EINVAL;
src_rate = clk_hw_get_rate(req->best_parent_hw);
div = src_rate / req->rate;
if (div >= 1 && div <= pre_div_max) {
req->best_parent_rate = src_rate;
req->rate = src_rate / div;
return 0;
}
return -EINVAL;
}
static int clk_rcg_esc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
struct freq_tbl f = { 0 };
int pre_div_max = BIT(rcg->p.pre_div_width);
int div;
u32 ns;
int i, ret, num_parents = clk_hw_get_num_parents(hw);
if (rate == 0)
return -EINVAL;
ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
if (ret)
return ret;
ns = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++) {
if (ns == rcg->s.parent_map[i].cfg) {
f.src = rcg->s.parent_map[i].src;
break;
}
}
div = parent_rate / rate;
if (div >= 1 && div <= pre_div_max) {
f.pre_div = div;
return __clk_rcg_set_rate(rcg, &f);
}
return -EINVAL;
}
static int clk_rcg_esc_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return clk_rcg_esc_set_rate(hw, rate, parent_rate);
}
/*
* This type of clock has a glitch-free mux that switches between the output of
* the M/N counter and an always on clock source (XO). When clk_set_rate() is
* called we need to make sure that we don't switch to the M/N counter if it
* isn't clocking because the mux will get stuck and the clock will stop
* outputting a clock. This can happen if the framework isn't aware that this
* clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
* this we switch the mux in the enable/disable ops and reprogram the M/N
* counter in the set_rate op. We also make sure to switch away from the M/N
* counter in set_rate if software thinks the clock is off.
*/
static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
const struct freq_tbl *f;
int ret;
u32 gfm = BIT(10);
f = qcom_find_freq(rcg->freq_tbl, rate);
if (!f)
return -EINVAL;
/* Switch to XO to avoid glitches */
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
ret = __clk_rcg_set_rate(rcg, f);
/* Switch back to M/N if it's clocking */
if (__clk_is_enabled(hw->clk))
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
return ret;
}
static int clk_rcg_lcc_enable(struct clk_hw *hw)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
u32 gfm = BIT(10);
/* Use M/N */
return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
}
static void clk_rcg_lcc_disable(struct clk_hw *hw)
{
struct clk_rcg *rcg = to_clk_rcg(hw);
u32 gfm = BIT(10);
/* Use XO */
regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
}
static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
{
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
const struct freq_tbl *f;
f = qcom_find_freq(rcg->freq_tbl, rate);
if (!f)
return -EINVAL;
return configure_bank(rcg, f);
}
static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return __clk_dyn_rcg_set_rate(hw, rate);
}
static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return __clk_dyn_rcg_set_rate(hw, rate);
}
const struct clk_ops clk_rcg_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_determine_rate,
.set_rate = clk_rcg_set_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_ops);
const struct clk_ops clk_rcg_floor_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_determine_rate,
.set_rate = clk_rcg_set_floor_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_floor_ops);
const struct clk_ops clk_rcg_bypass_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_bypass_determine_rate,
.set_rate = clk_rcg_bypass_set_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
const struct clk_ops clk_rcg_bypass2_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_bypass2_determine_rate,
.set_rate = clk_rcg_bypass2_set_rate,
.set_rate_and_parent = clk_rcg_bypass2_set_rate_and_parent,
};
EXPORT_SYMBOL_GPL(clk_rcg_bypass2_ops);
const struct clk_ops clk_rcg_pixel_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_pixel_determine_rate,
.set_rate = clk_rcg_pixel_set_rate,
.set_rate_and_parent = clk_rcg_pixel_set_rate_and_parent,
};
EXPORT_SYMBOL_GPL(clk_rcg_pixel_ops);
const struct clk_ops clk_rcg_esc_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_esc_determine_rate,
.set_rate = clk_rcg_esc_set_rate,
.set_rate_and_parent = clk_rcg_esc_set_rate_and_parent,
};
EXPORT_SYMBOL_GPL(clk_rcg_esc_ops);
const struct clk_ops clk_rcg_lcc_ops = {
.enable = clk_rcg_lcc_enable,
.disable = clk_rcg_lcc_disable,
.get_parent = clk_rcg_get_parent,
.set_parent = clk_rcg_set_parent,
.recalc_rate = clk_rcg_recalc_rate,
.determine_rate = clk_rcg_determine_rate,
.set_rate = clk_rcg_lcc_set_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
const struct clk_ops clk_dyn_rcg_ops = {
.enable = clk_enable_regmap,
.is_enabled = clk_is_enabled_regmap,
.disable = clk_disable_regmap,
.get_parent = clk_dyn_rcg_get_parent,
.set_parent = clk_dyn_rcg_set_parent,
.recalc_rate = clk_dyn_rcg_recalc_rate,
.determine_rate = clk_dyn_rcg_determine_rate,
.set_rate = clk_dyn_rcg_set_rate,
.set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
};
EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);
| linux-master | drivers/clk/qcom/clk-rcg.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_UFS_PHY_RX_SYMBOL_0_CLK,
DT_UFS_PHY_RX_SYMBOL_1_CLK,
DT_UFS_PHY_TX_SYMBOL_0_CLK,
DT_UFS_CARD_RX_SYMBOL_0_CLK,
DT_UFS_CARD_RX_SYMBOL_1_CLK,
DT_UFS_CARD_TX_SYMBOL_0_CLK,
DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK,
DT_PCIE_0_PIPE_CLK,
DT_PCIE_1_PIPE_CLK,
DT_PCIE_PHY_AUX_CLK,
DT_RXC0_REF_CLK,
DT_RXC1_REF_CLK,
};
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL1_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL5_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
P_PCIE_1_PIPE_CLK,
P_PCIE_PHY_AUX_CLK,
P_RXC0_REF_CLK,
P_RXC1_REF_CLK,
P_SLEEP_CLK,
P_UFS_CARD_RX_SYMBOL_0_CLK,
P_UFS_CARD_RX_SYMBOL_1_CLK,
P_UFS_CARD_TX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK,
};
static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO };
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll0",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gcc_gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll1",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll4",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll5",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll7",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x9000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x4b028,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpll9",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL1_OUT_MAIN, 4 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll1.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_RXC0_REF_CLK, 3 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .index = DT_RXC0_REF_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_RXC1_REF_CLK, 3 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .index = DT_RXC1_REF_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_PCIE_PHY_AUX_CLK, 1 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_PCIE_PHY_AUX_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_PCIE_PHY_AUX_CLK, 1 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_PCIE_PHY_AUX_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL5_OUT_MAIN, 3 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_15[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll5.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_16[] = {
{ .index = DT_UFS_CARD_RX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_17[] = {
{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_17[] = {
{ .index = DT_UFS_CARD_RX_SYMBOL_1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_18[] = {
{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_UFS_CARD_TX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_19[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_19[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_20[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_20[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_21[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_21[] = {
{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_22[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_22[] = {
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_23[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_23[] = {
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
.reg = 0xa9074,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_9,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_phy_aux_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0xa906c,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_0_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
.reg = 0x77074,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x7706c,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_1_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
.reg = 0x81060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_16,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_16,
.num_parents = ARRAY_SIZE(gcc_parent_data_16),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
.reg = 0x810d0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_17,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_17,
.num_parents = ARRAY_SIZE(gcc_parent_data_17),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
.reg = 0x81050,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_18,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_18,
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x83060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_19,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_19,
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x830d0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_20,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_20,
.num_parents = ARRAY_SIZE(gcc_parent_data_20),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x83050,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_21,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_21,
.num_parents = ARRAY_SIZE(gcc_parent_data_21),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x1b068,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_22,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_22,
.num_parents = ARRAY_SIZE(gcc_parent_data_22),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
.reg = 0x2f068,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_23,
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_23,
.num_parents = ARRAY_SIZE(gcc_parent_data_23),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {
.cmd_rcgr = 0xb6028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
.cmd_rcgr = 0xb6060,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_ptp_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
.cmd_rcgr = 0xb6048,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_rgmii_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = {
.cmd_rcgr = 0xb4028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
.cmd_rcgr = 0xb4060,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_ptp_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
.cmd_rcgr = 0xb4048,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_rgmii_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x70004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x71004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x62004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp4_clk_src = {
.cmd_rcgr = 0x1e004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_gp4_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp5_clk_src = {
.cmd_rcgr = 0x1f004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_gp5_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0xa9078,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0xa9054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x77078,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x77054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x3f010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x23154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x23288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x233bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x234f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x23624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x23758,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x2388c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x24154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x24288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x243bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x244f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x24624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x24758,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x2488c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x2a154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x2a288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x2a3bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x2a4f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x2a624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x2a758,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.name = "gcc_qupv3_wrap2_s6_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
.cmd_rcgr = 0x2a88c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = {
.name = "gcc_qupv3_wrap3_s0_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = {
.cmd_rcgr = 0xc4154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x20014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_13,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x2002c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_14,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = {
F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4),
{ }
};
static struct clk_rcg2 gcc_tscss_cntr_clk_src = {
.cmd_rcgr = 0x21008,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_15,
.freq_tbl = ftbl_gcc_tscss_cntr_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_tscss_cntr_clk_src",
.parent_data = gcc_parent_data_15,
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x8102c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x81074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x810a8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x8108c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x8302c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x83074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x830a8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x8308c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb20_master_clk_src = {
.cmd_rcgr = 0x1c028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb20_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb20_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
.cmd_rcgr = 0x1c040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x1b028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x1b040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x2f028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x2f040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x1b06c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x2f06c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = {
.reg = 0xa9070,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = {
.reg = 0x77070,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = {
.reg = 0xc4284,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap3_s0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
.reg = 0x1c058,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x1b058,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.reg = 0x2f058,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = {
.halt_reg = 0x8e200,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8e200,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_noc_qupv3_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x810d4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x810d4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x810d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x830d4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x830d4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x830d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x830d4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x830d4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x830d4,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
.halt_reg = 0x1c05c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1c05c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1c05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_usb2_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x1b084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1b084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1b084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x2f088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2f088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2f088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy0_clk = {
.halt_reg = 0x76004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x76004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x76004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ahb2phy0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy2_clk = {
.halt_reg = 0x76008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x76008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x76008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ahb2phy2_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy3_clk = {
.halt_reg = 0x7600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7600c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ahb2phy3_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x44004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x44004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x32010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x32018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_xo_clk = {
.halt_reg = 0x32024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x32024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_camera_throttle_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
.halt_reg = 0x1c060,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1c060,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1c060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_cfg_noc_usb2_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1b088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1b088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1b088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x2f084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2f084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2f084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x7d164,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7d164,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_disp1_hf_axi_clk = {
.halt_reg = 0xc7010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xc7010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xc7010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_disp1_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x33010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_edp_ref_clkref_en = {
.halt_reg = 0x97448,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x97448,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_edp_ref_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_axi_clk = {
.halt_reg = 0xb6018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb6018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb6018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_phy_aux_clk = {
.halt_reg = 0xb6024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb6024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac0_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_ptp_clk = {
.halt_reg = 0xb6040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb6040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_ptp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac0_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_rgmii_clk = {
.halt_reg = 0xb6044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb6044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_rgmii_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac0_rgmii_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_slv_ahb_clk = {
.halt_reg = 0xb6020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb6020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb6020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac0_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_axi_clk = {
.halt_reg = 0xb4018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb4018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb4018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_phy_aux_clk = {
.halt_reg = 0xb4024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb4024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac1_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_ptp_clk = {
.halt_reg = 0xb4040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb4040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_ptp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac1_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_rgmii_clk = {
.halt_reg = 0xb4044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb4044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_rgmii_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac1_rgmii_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_slv_ahb_clk = {
.halt_reg = 0xb4020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb4020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb4020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_emac1_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x70000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x70000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x71000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x62000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp4_clk = {
.halt_reg = 0x1e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gp4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp5_clk = {
.halt_reg = 0x1f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1f000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gp5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7d010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7d010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x7d01c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {
.halt_reg = 0x7d008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7d008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpu_tcu_throttle_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_tcu_throttle_clk = {
.halt_reg = 0x7d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_gpu_tcu_throttle_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0xa9038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0xa902c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa902c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0xa9024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_aux_clk = {
.halt_reg = 0xa9030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
.halt_reg = 0xa9050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0xa9040,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipediv2_clk = {
.halt_reg = 0xa9048,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4b018,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0xa901c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0xa9018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b018,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x77038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(31),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x7702c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7702c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x77024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_aux_clk = {
.halt_reg = 0x77030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
.halt_reg = 0x77050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x77040,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipediv2_clk = {
.halt_reg = 0x77048,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4b018,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_clkref_en = {
.halt_reg = 0x9746c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x9746c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_throttle_cfg_clk = {
.halt_reg = 0xb2034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b020,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pcie_throttle_cfg_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3f00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x3f004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3f004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3f004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x3f008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x32008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x3200c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp1_ahb_clk = {
.halt_reg = 0xc7008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xc7008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xc7008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_disp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = {
.halt_reg = 0xc700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xc700c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_disp1_rot_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_disp_rot_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0x34008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x34008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x3400c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3400c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3400c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = {
.halt_reg = 0x34010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x34010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qmip_video_vcpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x23018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x2300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x2314c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x23280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x233b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x234e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x2361c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x23750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x23884,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x24018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x2400c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x2414c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x24280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x243b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x244e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x2461c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x24750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x24884,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b018,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x2a018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x2a00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x2a14c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x2a280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x2a3b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x2a4e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x2a61c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x2a750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.halt_reg = 0x2a884,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b018,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap2_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
.halt_reg = 0xc4018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap3_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap3_core_clk = {
.halt_reg = 0xc400c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap3_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap3_qspi_clk = {
.halt_reg = 0xc4280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap3_qspi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
.halt_reg = 0xc414c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap3_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x24004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x24004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x24008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x24008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x2a004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x2a008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2a008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = {
.halt_reg = 0xc4004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xc4004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_3_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = {
.halt_reg = 0xc4008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xc4008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_3_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x2000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x20044,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x20044,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sgmi_clkref_en = {
.halt_reg = 0x9c034,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x9c034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_sgmi_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tscss_ahb_clk = {
.halt_reg = 0x21024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_tscss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tscss_etu_clk = {
.halt_reg = 0x21020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_tscss_etu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tscss_global_cntr_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x21004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_tscss_global_cntr_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_tscss_cntr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x81020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x81018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x8106c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8106c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8106c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x810a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x810a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x810a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_reg = 0x81028,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x81028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_reg = 0x810c0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x810c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_reg = 0x81024,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x81024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x81064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x83020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x83020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x83020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x83018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x83018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x83018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x83018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x83018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x83018,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x8306c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8306c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8306c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x8306c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8306c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8306c,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x830a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x830a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x830a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x830a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x830a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x830a4,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x83028,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x83028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x830c0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x830c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x83024,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x83024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x83064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x83064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x83064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x83064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x83064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x83064,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x1c018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb20_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_mock_utmi_clk = {
.halt_reg = 0x1c024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_sleep_clk = {
.halt_reg = 0x1c020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb20_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x1b018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x1b024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x1b020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x2f018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x2f024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x2f020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x1b05c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x1b060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x1b064,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x1b064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1b064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x2f05c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x2f060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x2f064,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2f064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_clkref_en = {
.halt_reg = 0x97468,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x97468,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_usb_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x34014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x34014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x3401c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3401c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3401c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0xa9004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x81004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x83004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb20_prim_gdsc = {
.gdscr = 0x1c004,
.pd = {
.name = "usb20_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1b004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x2f004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc emac0_gdsc = {
.gdscr = 0xb6004,
.pd = {
.name = "emac0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc emac1_gdsc = {
.gdscr = 0xb4004,
.pd = {
.name = "emac1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,
[GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,
[GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,
[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr,
[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
[GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,
[GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,
[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
[GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr,
[GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr,
[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL1] = &gcc_gpll1.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL5] = &gcc_gpll5.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,
[GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr,
[GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr,
[GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
[GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr,
[GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
[GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
[GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
[GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr,
[GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
[GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
[GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr,
[GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr,
[GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr,
[GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr,
[GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
[GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
};
static const struct qcom_reset_map gcc_sa8775p_resets[] = {
[GCC_CAMERA_BCR] = { 0x32000 },
[GCC_DISPLAY1_BCR] = { 0xc7000 },
[GCC_DISPLAY_BCR] = { 0x33000 },
[GCC_EMAC0_BCR] = { 0xb6000 },
[GCC_EMAC1_BCR] = { 0xb4000 },
[GCC_GPU_BCR] = { 0x7d000 },
[GCC_MMSS_BCR] = { 0x17000 },
[GCC_PCIE_0_BCR] = { 0xa9000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
[GCC_PCIE_0_PHY_BCR] = { 0xad144 },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
[GCC_PCIE_1_BCR] = { 0x77000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
[GCC_PDM_BCR] = { 0x3f000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 },
[GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 },
[GCC_SDCC1_BCR] = { 0x20000 },
[GCC_TSCSS_BCR] = { 0x21000 },
[GCC_UFS_CARD_BCR] = { 0x81000 },
[GCC_UFS_PHY_BCR] = { 0x83000 },
[GCC_USB20_PRIM_BCR] = { 0x1c000 },
[GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 },
[GCC_USB2_PHY_SEC_BCR] = { 0x5c02c },
[GCC_USB30_PRIM_BCR] = { 0x1b000 },
[GCC_USB30_SEC_BCR] = { 0x2f000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5c00c },
[GCC_USB3_PHY_TERT_BCR] = { 0x5c030 },
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 },
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 },
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
[GCC_VIDEO_BCR] = { 0x34000 },
};
static struct gdsc *gcc_sa8775p_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB20_PRIM_GDSC] = &usb20_prim_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[EMAC0_GDSC] = &emac0_gdsc,
[EMAC1_GDSC] = &emac1_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src),
};
static const struct regmap_config gcc_sa8775p_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc7018,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sa8775p_desc = {
.config = &gcc_sa8775p_regmap_config,
.clks = gcc_sa8775p_clocks,
.num_clks = ARRAY_SIZE(gcc_sa8775p_clocks),
.resets = gcc_sa8775p_resets,
.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
.gdscs = gcc_sa8775p_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
};
static const struct of_device_id gcc_sa8775p_match_table[] = {
{ .compatible = "qcom,sa8775p-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table);
static int gcc_sa8775p_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK,
* GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
* GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK.
*/
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
}
static struct platform_driver gcc_sa8775p_driver = {
.probe = gcc_sa8775p_probe,
.driver = {
.name = "sa8775p-gcc",
.of_match_table = gcc_sa8775p_match_table,
},
};
static int __init gcc_sa8775p_init(void)
{
return platform_driver_register(&gcc_sa8775p_driver);
}
core_initcall(gcc_sa8775p_init);
static void __exit gcc_sa8775p_exit(void)
{
platform_driver_unregister(&gcc_sa8775p_driver);
}
module_exit(gcc_sa8775p_exit);
MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-sa8775p.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019, Jeffrey Hugo
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPUPLL0_OUT_EVEN,
};
/* Instead of going directly to the block, XO is routed through this branch */
static struct clk_branch gpucc_cxo_clk = {
.halt_reg = 0x1020,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll gpupll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "gpupll0",
.parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv gpupll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpupll0_out_even",
.parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct parent_map gpu_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
};
static const struct clk_parent_data gpu_xo_gpll0[] = {
{ .hw = &gpucc_cxo_clk.clkr.hw },
{ .fw_name = "gpll0", .name = "gcc_gpu_gpll0_clk" },
};
static const struct parent_map gpu_xo_gpupll0_map[] = {
{ P_XO, 0 },
{ P_GPUPLL0_OUT_EVEN, 1 },
};
static const struct clk_hw *gpu_xo_gpupll0[] = {
&gpucc_cxo_clk.clkr.hw,
&gpupll0_out_even.clkr.hw,
};
static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_clk_src = {
.cmd_rcgr = 0x1030,
.hid_width = 5,
.parent_map = gpu_xo_gpll0_map,
.freq_tbl = ftbl_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
.parent_data = gpu_xo_gpll0,
.num_parents = ARRAY_SIZE(gpu_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x1070,
.hid_width = 5,
.parent_map = gpu_xo_gpupll0_map,
.freq_tbl = ftbl_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_hws = gpu_xo_gpupll0,
.num_parents = ARRAY_SIZE(gpu_xo_gpupll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
},
};
static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 rbbmtimer_clk_src = {
.cmd_rcgr = 0x10b0,
.hid_width = 5,
.parent_map = gpu_xo_gpll0_map,
.freq_tbl = ftbl_rbbmtimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_data = gpu_xo_gpll0,
.num_parents = ARRAY_SIZE(gpu_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0, 15, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_isense_clk_src = {
.cmd_rcgr = 0x1100,
.hid_width = 5,
.parent_map = gpu_xo_gpll0_map,
.freq_tbl = ftbl_gfx3d_isense_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_isense_clk_src",
.parent_data = gpu_xo_gpll0,
.num_parents = ARRAY_SIZE(gpu_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch rbcpr_clk = {
.halt_reg = 0x1054,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk",
.parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gfx3d_clk = {
.halt_reg = 0x1098,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk",
.parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch rbbmtimer_clk = {
.halt_reg = 0x10d0,
.clkr = {
.enable_reg = 0x10d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk",
.parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gfx3d_isense_clk = {
.halt_reg = 0x1124,
.clkr = {
.enable_reg = 0x1124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gfx3d_isense_clk",
.parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x1004,
.gds_hw_ctrl = 0x1008,
.pd = {
.name = "gpu_cx",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x1094,
.clamp_io_ctrl = 0x130,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.cxcs = (unsigned int []){ 0x1098 },
.cxc_count = 1,
.pd = {
.name = "gpu_gx",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON | PWRSTS_RET,
.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
};
static struct clk_regmap *gpucc_msm8998_clocks[] = {
[GPUPLL0] = &gpupll0.clkr,
[GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr,
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr,
[RBCPR_CLK] = &rbcpr_clk.clkr,
[GFX3D_CLK] = &gfx3d_clk.clkr,
[RBBMTIMER_CLK] = &rbbmtimer_clk.clkr,
[GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr,
[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
};
static struct gdsc *gpucc_msm8998_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct qcom_reset_map gpucc_msm8998_resets[] = {
[GPU_CX_BCR] = { 0x1000 },
[RBCPR_BCR] = { 0x1050 },
[GPU_GX_BCR] = { 0x1090 },
[GPU_ISENSE_BCR] = { 0x1120 },
};
static const struct regmap_config gpucc_msm8998_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpucc_msm8998_desc = {
.config = &gpucc_msm8998_regmap_config,
.clks = gpucc_msm8998_clocks,
.num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
.resets = gpucc_msm8998_resets,
.num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
.gdscs = gpucc_msm8998_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
};
static const struct of_device_id gpucc_msm8998_match_table[] = {
{ .compatible = "qcom,msm8998-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table);
static int gpucc_msm8998_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* force periph logic on to avoid perf counter corruption */
regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
/* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
}
static struct platform_driver gpucc_msm8998_driver = {
.probe = gpucc_msm8998_probe,
.driver = {
.name = "gpucc-msm8998",
.of_match_table = gpucc_msm8998_match_table,
},
};
module_platform_driver(gpucc_msm8998_driver);
MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-msm8998.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_1_PHY_AUX_CLK,
P_SLEEP_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x9000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_PCIE_1_PHY_AUX_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "pcie_1_phy_aux_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x7b060,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
.reg = 0x9d080,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_5,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x9d064,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x87060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_8,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x870d0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_9,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x87050,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x49068,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x74004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x75004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x76004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x7b064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0x7b048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x9d068,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x9d04c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x43010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x27014,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x27148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x2727c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x273b0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x274e4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x27618,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x2774c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x27880,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x28014,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x28148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x2827c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x283b0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x284e4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x28618,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x2874c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x2e014,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x2e148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x2e27c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x2e3b0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x2e4e4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x2e618,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.name = "gcc_qupv3_wrap2_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
.cmd_rcgr = 0x2e74c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x24014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x26014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x8702c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x87074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x870a8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x8708c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x49028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x49040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x4906c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x49058,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
.halt_reg = 0x7b08c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x7b08c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
.halt_reg = 0x9d098,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9d098,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x870d4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x870d4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x870d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x870d4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x870d4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x870d4,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x49088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x49088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x49088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x48004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x36010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x36010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x36018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x36018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
.halt_reg = 0x20030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x20030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x49084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x49084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x49084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x81154,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x81154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
.halt_reg = 0x9d094,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9d094,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_pcie_sf_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x3700c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x3700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0x37014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x37014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x37014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eusb3_0_clkref_en = {
.halt_reg = 0x9c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eusb3_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x74000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x74000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x75000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x76000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x76000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x81010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x81018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x81018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x7b034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x7b030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7b030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x9c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x7b028,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
.halt_reg = 0x7b044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x7b03c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x7b020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7b020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x7b01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x9d030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x9d02c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d02c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_clkref_en = {
.halt_reg = 0x9c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x9d024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_aux_clk = {
.halt_reg = 0x9d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
.halt_reg = 0x9d048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x9d040,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x9d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x9d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x43004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x43004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x43004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x43008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x37008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x37008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x37008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_ahb_clk = {
.halt_reg = 0x81008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x81008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x81008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_pcie_ahb_clk = {
.halt_reg = 0x7b018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7b018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7b018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_pcie_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
.halt_reg = 0x42014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x42014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x42014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cv_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0x42008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x42008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x42008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
.halt_reg = 0x42010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x42010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x42010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_v_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x4200c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x33000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x27140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x27274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x273a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x274dc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x27610,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x27744,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x27878,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x3314c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x33140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x2800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x28140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x28274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x283a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x284dc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x28610,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x28744,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x3328c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x33280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x2e00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x2e140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x2e274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x2e3a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x2e4dc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x2e610,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.halt_reg = 0x2e744,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x27004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x28004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x2e004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2e004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x2e008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x2400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x24004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x24004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_at_clk = {
.halt_reg = 0x24010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x24010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x24010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x26004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_at_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_0_clkref_en = {
.halt_reg = 0x9c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x87020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x87020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x87020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x87018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x87018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x87018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x87018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x87018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x87018,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x8706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8706c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x8706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8706c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x870a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x870a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x870a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x870a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x870a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x870a4,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x87028,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x87028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x870c0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x870c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x87024,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x87024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x87064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x87064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x87064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x87064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x87064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x87064,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x49018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x49024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x49020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_0_clkref_en = {
.halt_reg = 0x9c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x4905c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4905c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x49060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x49064,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x49064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x49064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x42018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x42018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x42020,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x42020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x42020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x7b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x9d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x87004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x49004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_sm8450_clocks[] = {
[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr,
[GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
};
static const struct qcom_reset_map gcc_sm8450_resets[] = {
[GCC_CAMERA_BCR] = { 0x36000 },
[GCC_DISPLAY_BCR] = { 0x37000 },
[GCC_GPU_BCR] = { 0x81000 },
[GCC_PCIE_0_BCR] = { 0x7b000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
[GCC_PCIE_1_BCR] = { 0x9d000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
[GCC_PCIE_PHY_BCR] = { 0x7f000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
[GCC_PDM_BCR] = { 0x43000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
[GCC_SDCC2_BCR] = { 0x24000 },
[GCC_SDCC4_BCR] = { 0x26000 },
[GCC_UFS_PHY_BCR] = { 0x87000 },
[GCC_USB30_PRIM_BCR] = { 0x49000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
[GCC_VIDEO_BCR] = { 0x42000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
};
static struct gdsc *gcc_sm8450_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
};
static const struct regmap_config gcc_sm8450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f1030,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm8450_desc = {
.config = &gcc_sm8450_regmap_config,
.clks = gcc_sm8450_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8450_clocks),
.resets = gcc_sm8450_resets,
.num_resets = ARRAY_SIZE(gcc_sm8450_resets),
.gdscs = gcc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
};
static const struct of_device_id gcc_sm8450_match_table[] = {
{ .compatible = "qcom,gcc-sm8450" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
static int gcc_sm8450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
/*
* Keep the critical clock always-On
* gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
* gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
* gcc_video_xo_clk
*/
regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
}
static struct platform_driver gcc_sm8450_driver = {
.probe = gcc_sm8450_probe,
.driver = {
.name = "gcc-sm8450",
.of_match_table = gcc_sm8450_match_table,
},
};
static int __init gcc_sm8450_init(void)
{
return platform_driver_register(&gcc_sm8450_driver);
}
subsys_initcall(gcc_sm8450_init);
static void __exit gcc_sm8450_exit(void)
{
platform_driver_unregister(&gcc_sm8450_driver);
}
module_exit(gcc_sm8450_exit);
MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sm8450.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6125-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPU_CC_PLL0_2X_CLK,
P_GPU_CC_PLL0_OUT_AUX2,
P_GPU_CC_PLL1_OUT_AUX,
P_GPU_CC_PLL1_OUT_AUX2,
};
static struct pll_vco gpu_cc_pll_vco[] = {
{ 1000000000, 2000000000, 0 },
{ 500000000, 1000000000, 2 },
};
/* 1020MHz configuration */
static const struct alpha_pll_config gpu_pll0_config = {
.l = 0x35,
.config_ctl_val = 0x4001055b,
.alpha_hi = 0x20,
.alpha = 0x00,
.alpha_en_mask = BIT(24),
.vco_val = 0x0 << 20,
.vco_mask = 0x3 << 20,
.aux2_output_mask = BIT(2),
};
/* 930MHz configuration */
static const struct alpha_pll_config gpu_pll1_config = {
.l = 0x30,
.config_ctl_val = 0x4001055b,
.alpha_hi = 0x70,
.alpha = 0x00,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.aux2_output_mask = BIT(2),
};
static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = {
.offset = 0x0,
.vco_table = gpu_cc_pll_vco,
.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0_out_aux2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = {
.offset = 0x100,
.vco_table = gpu_cc_pll_vco,
.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1_out_aux2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
{ P_GPU_CC_PLL1_OUT_AUX2, 4 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
{ .hw = &gpu_cc_pll1_out_aux2.clkr.hw },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.pd = {
.name = "gpu_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gpu_cc_sm6125_clocks[] = {
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
[GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};
static struct gdsc *gpucc_sm6125_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm6125_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm6125_desc = {
.config = &gpu_cc_sm6125_regmap_config,
.clks = gpu_cc_sm6125_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks),
.gdscs = gpucc_sm6125_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs),
};
static const struct of_device_id gpu_cc_sm6125_match_table[] = {
{ .compatible = "qcom,sm6125-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table);
static int gpu_cc_sm6125_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config);
clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config);
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
}
static struct platform_driver gpu_cc_sm6125_driver = {
.probe = gpu_cc_sm6125_probe,
.driver = {
.name = "gpucc-sm6125",
.of_match_table = gpu_cc_sm6125_match_table,
},
};
module_platform_driver(gpu_cc_sm6125_driver);
MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sm6125.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/export.h>
#include "clk-regmap-mux.h"
static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw)
{
return container_of(to_clk_regmap(hw), struct clk_regmap_mux, clkr);
}
static u8 mux_get_parent(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
struct clk_regmap *clkr = to_clk_regmap(hw);
unsigned int mask = GENMASK(mux->width - 1, 0);
unsigned int val;
regmap_read(clkr->regmap, mux->reg, &val);
val >>= mux->shift;
val &= mask;
if (mux->parent_map)
return qcom_find_cfg_index(hw, mux->parent_map, val);
return val;
}
static int mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
struct clk_regmap *clkr = to_clk_regmap(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
if (mux->parent_map)
index = mux->parent_map[index].cfg;
val = index;
val <<= mux->shift;
return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
const struct clk_ops clk_regmap_mux_closest_ops = {
.get_parent = mux_get_parent,
.set_parent = mux_set_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
| linux-master | drivers/clk/qcom/clk-regmap-mux.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019, Linaro Ltd.
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
#include "reset.h"
static struct clk_branch turing_wrapper_aon_cbcr = {
.halt_reg = 0x5098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "turing_wrapper_aon_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch turing_q6ss_ahbm_aon_cbcr = {
.halt_reg = 0x9000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "turing_q6ss_ahbm_aon_cbcr",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch turing_q6ss_q6_axim_clk = {
.halt_reg = 0xb000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "turing_q6ss_q6_axim_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch turing_q6ss_ahbs_aon_cbcr = {
.halt_reg = 0x10000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "turing_q6ss_ahbs_aon_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch turing_wrapper_qos_ahbs_aon_cbcr = {
.halt_reg = 0x11014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "turing_wrapper_qos_ahbs_aon_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_regmap *turingcc_clocks[] = {
[TURING_WRAPPER_AON_CLK] = &turing_wrapper_aon_cbcr.clkr,
[TURING_Q6SS_AHBM_AON_CLK] = &turing_q6ss_ahbm_aon_cbcr.clkr,
[TURING_Q6SS_Q6_AXIM_CLK] = &turing_q6ss_q6_axim_clk.clkr,
[TURING_Q6SS_AHBS_AON_CLK] = &turing_q6ss_ahbs_aon_cbcr.clkr,
[TURING_WRAPPER_QOS_AHBS_AON_CLK] = &turing_wrapper_qos_ahbs_aon_cbcr.clkr,
};
static const struct regmap_config turingcc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x23004,
.fast_io = true,
};
static const struct qcom_cc_desc turingcc_desc = {
.config = &turingcc_regmap_config,
.clks = turingcc_clocks,
.num_clks = ARRAY_SIZE(turingcc_clocks),
};
static int turingcc_probe(struct platform_device *pdev)
{
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, NULL);
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
ret = qcom_cc_probe(pdev, &turingcc_desc);
if (ret < 0)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static const struct dev_pm_ops turingcc_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static const struct of_device_id turingcc_match_table[] = {
{ .compatible = "qcom,qcs404-turingcc" },
{ }
};
MODULE_DEVICE_TABLE(of, turingcc_match_table);
static struct platform_driver turingcc_driver = {
.probe = turingcc_probe,
.driver = {
.name = "qcs404-turingcc",
.of_match_table = turingcc_match_table,
.pm = &turingcc_pm_ops,
},
};
module_platform_driver(turingcc_driver);
MODULE_DESCRIPTION("Qualcomm QCS404 Turing Clock Controller");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/turingcc-qcs404.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_PCIE_0_PIPE,
DT_PCIE_1_PIPE,
DT_PCIE_1_PHY_AUX,
DT_UFS_PHY_RX_SYMBOL_0,
DT_UFS_PHY_RX_SYMBOL_1,
DT_UFS_PHY_TX_SYMBOL_0,
DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,
};
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
P_PCIE_1_PHY_AUX_CLK,
P_PCIE_1_PIPE_CLK,
P_SLEEP_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll7",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x9000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll9",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_PCIE_1_PHY_AUX_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_PCIE_1_PHY_AUX },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_0 },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_1 },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_UFS_PHY_TX_SYMBOL_0 },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },
{ .index = DT_BI_TCXO },
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b070,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_0_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
.reg = 0x8d094,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d078,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_1_PIPE,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x77064,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770e0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x77054,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x3906c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_13,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b074,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0x6b058,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d07c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x8d060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
.cmd_rcgr = 0x17008,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
.cmd_rcgr = 0x17024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
.cmd_rcgr = 0x17040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
.cmd_rcgr = 0x1705c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
.cmd_rcgr = 0x17078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
.cmd_rcgr = 0x17094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
.cmd_rcgr = 0x170b0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
.cmd_rcgr = 0x170cc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
.cmd_rcgr = 0x170e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s8_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
.cmd_rcgr = 0x17104,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s9_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18280,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183b8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18628,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18760,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x18898,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e280,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e3b8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e4f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e628,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
F(125000000, P_GCC_GPLL0_OUT_MAIN, 1, 5, 24),
{ }
};
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.name = "gcc_qupv3_wrap2_s6_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
.cmd_rcgr = 0x1e760,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
.name = "gcc_qupv3_wrap2_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
.cmd_rcgr = 0x1e898,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x14018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x16018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77030,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x77080,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77098,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x3902c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x39044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x39070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x3905c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
.halt_reg = 0x1003c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1003c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770e4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770e4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x770e4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770e4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770e4,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x3908c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3908c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3908c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x2601c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2601c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
.halt_reg = 0x10028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x10028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x39088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x39088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x39088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
.halt_reg = 0x10030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_cnoc_pcie_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
.halt_reg = 0x1004c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1004c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_pcie_sf_qtb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x71010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b03c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b038,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b02c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b02c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
.halt_reg = 0x6b054,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b048,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_aux_clk = {
.halt_reg = 0x8d044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
.halt_reg = 0x8d05c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d050,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_ahb_clk = {
.halt_reg = 0x71008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_pcie_ahb_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_pcie_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
.halt_reg = 0x32014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cv_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0x32008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
.halt_reg = 0x32010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_v_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x3200c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_core_clk = {
.halt_reg = 0x23144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s0_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s1_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s2_clk = {
.halt_reg = 0x1703c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s3_clk = {
.halt_reg = 0x17058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s4_clk = {
.halt_reg = 0x17074,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s5_clk = {
.halt_reg = 0x17090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s6_clk = {
.halt_reg = 0x170ac,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s7_clk = {
.halt_reg = 0x170c8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s8_clk = {
.halt_reg = 0x170e4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s8_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s8_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s9_clk = {
.halt_reg = 0x17100,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s9_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_i2c_s9_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = {
.halt_reg = 0x23140,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23140,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_i2c_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x23294,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x23284,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x1813c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x183ac,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184e4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x1861c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x18754,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x1888c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x233d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e13c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e3ac,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e4e4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e61c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.halt_reg = 0x1e754,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
.halt_reg = 0x1e88c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x2327c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2327c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x23280,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23280,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x233cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x233cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x233d0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x233d0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77074,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x77074,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77074,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x770b0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770b0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x770b0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770b0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770b0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x7702c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x77028,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x77068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77068,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x39018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x39028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x39024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x39060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x39064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x39068,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x39068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x39068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x32018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x32024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_0_phy_gdsc = {
.gdscr = 0x6c000,
.pd = {
.name = "pcie_0_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_1_phy_gdsc = {
.gdscr = 0x8e000,
.pd = {
.name = "pcie_1_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_mem_phy_gdsc = {
.gdscr = 0x9e000,
.pd = {
.name = "ufs_mem_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x39004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb3_phy_gdsc = {
.gdscr = 0x50018,
.pd = {
.name = "usb3_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct clk_regmap *gcc_sm8550_clocks[] = {
[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr,
[GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr,
[GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr,
[GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr,
[GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr,
[GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr,
[GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr,
[GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr,
[GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr,
[GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr,
[GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr,
[GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr,
[GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr,
[GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr,
[GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr,
[GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr,
[GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr,
[GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr,
[GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr,
[GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr,
[GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr,
[GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
};
static const struct qcom_reset_map gcc_sm8550_resets[] = {
[GCC_CAMERA_BCR] = { 0x26000 },
[GCC_DISPLAY_BCR] = { 0x27000 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0x39000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
[GCC_VIDEO_BCR] = { 0x32000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
};
static struct gdsc *gcc_sm8550_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB3_PHY_GDSC] = &usb3_phy_gdsc,
};
static const struct regmap_config gcc_sm8550_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f41f0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm8550_desc = {
.config = &gcc_sm8550_regmap_config,
.clks = gcc_sm8550_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8550_clocks),
.resets = gcc_sm8550_resets,
.num_resets = ARRAY_SIZE(gcc_sm8550_resets),
.gdscs = gcc_sm8550_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs),
};
static const struct of_device_id gcc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm8550_match_table);
static int gcc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8550_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
/*
* Keep the critical clock always-On
* gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
* gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
* gcc_video_xo_clk
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0));
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52024, 0x0);
return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap);
}
static struct platform_driver gcc_sm8550_driver = {
.probe = gcc_sm8550_probe,
.driver = {
.name = "gcc-sm8550",
.of_match_table = gcc_sm8550_match_table,
},
};
static int __init gcc_sm8550_init(void)
{
return platform_driver_register(&gcc_sm8550_driver);
}
subsys_initcall(gcc_sm8550_init);
static void __exit gcc_sm8550_exit(void)
{
platform_driver_unregister(&gcc_sm8550_driver);
}
module_exit(gcc_sm8550_exit);
MODULE_DESCRIPTION("QTI GCC SM8550 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-sm8550.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/bug.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/rational.h>
#include <linux/regmap.h>
#include <linux/math64.h>
#include <linux/minmax.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include "clk-rcg.h"
#include "common.h"
#define CMD_REG 0x0
#define CMD_UPDATE BIT(0)
#define CMD_ROOT_EN BIT(1)
#define CMD_DIRTY_CFG BIT(4)
#define CMD_DIRTY_N BIT(5)
#define CMD_DIRTY_M BIT(6)
#define CMD_DIRTY_D BIT(7)
#define CMD_ROOT_OFF BIT(31)
#define CFG_REG 0x4
#define CFG_SRC_DIV_SHIFT 0
#define CFG_SRC_SEL_SHIFT 8
#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
#define CFG_MODE_SHIFT 12
#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
#define CFG_HW_CLK_CTRL_MASK BIT(20)
#define M_REG 0x8
#define N_REG 0xc
#define D_REG 0x10
#define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
#define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
#define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
#define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
/* Dynamic Frequency Scaling */
#define MAX_PERF_LEVEL 8
#define SE_CMD_DFSR_OFFSET 0x14
#define SE_CMD_DFS_EN BIT(0)
#define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
#define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
#define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
enum freq_policy {
FLOOR,
CEIL,
};
static int clk_rcg2_is_enabled(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 cmd;
int ret;
ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
if (ret)
return ret;
return (cmd & CMD_ROOT_OFF) == 0;
}
static u8 __clk_rcg2_get_parent(struct clk_hw *hw, u32 cfg)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int num_parents = clk_hw_get_num_parents(hw);
int i;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
for (i = 0; i < num_parents; i++)
if (cfg == rcg->parent_map[i].cfg)
return i;
pr_debug("%s: Clock %s has invalid parent, using default.\n",
__func__, clk_hw_get_name(hw));
return 0;
}
static u8 clk_rcg2_get_parent(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 cfg;
int ret;
ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
if (ret) {
pr_debug("%s: Unable to read CFG register for %s\n",
__func__, clk_hw_get_name(hw));
return 0;
}
return __clk_rcg2_get_parent(hw, cfg);
}
static int update_config(struct clk_rcg2 *rcg)
{
int count, ret;
u32 cmd;
struct clk_hw *hw = &rcg->clkr.hw;
const char *name = clk_hw_get_name(hw);
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
CMD_UPDATE, CMD_UPDATE);
if (ret)
return ret;
/* Wait for update to take effect */
for (count = 500; count > 0; count--) {
ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
if (ret)
return ret;
if (!(cmd & CMD_UPDATE))
return 0;
udelay(1);
}
WARN(1, "%s: rcg didn't update its configuration.", name);
return -EBUSY;
}
static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int ret;
u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
CFG_SRC_SEL_MASK, cfg);
if (ret)
return ret;
return update_config(rcg);
}
/*
* Calculate m/n:d rate
*
* parent_rate m
* rate = ----------- x ---
* hid_div n
*/
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
{
if (hid_div) {
rate *= 2;
rate /= hid_div + 1;
}
if (mode) {
u64 tmp = rate;
tmp *= m;
do_div(tmp, n);
rate = tmp;
}
return rate;
}
static unsigned long
__clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 hid_div, m = 0, n = 0, mode = 0, mask;
if (rcg->mnd_width) {
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
m &= mask;
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
n = ~n;
n &= mask;
n += m;
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
}
mask = BIT(rcg->hid_width) - 1;
hid_div = cfg >> CFG_SRC_DIV_SHIFT;
hid_div &= mask;
return calc_rate(parent_rate, m, n, mode, hid_div);
}
static unsigned long
clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 cfg;
regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
}
static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
struct clk_rate_request *req,
enum freq_policy policy)
{
unsigned long clk_flags, rate = req->rate;
struct clk_hw *p;
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int index;
switch (policy) {
case FLOOR:
f = qcom_find_freq_floor(f, rate);
break;
case CEIL:
f = qcom_find_freq(f, rate);
break;
default:
return -EINVAL;
}
if (!f)
return -EINVAL;
index = qcom_find_src_index(hw, rcg->parent_map, f->src);
if (index < 0)
return index;
clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index);
if (!p)
return -EINVAL;
if (clk_flags & CLK_SET_RATE_PARENT) {
rate = f->freq;
if (f->pre_div) {
if (!rate)
rate = req->rate;
rate /= 2;
rate *= f->pre_div + 1;
}
if (f->n) {
u64 tmp = rate;
tmp = tmp * f->n;
do_div(tmp, f->m);
rate = tmp;
}
} else {
rate = clk_hw_get_rate(p);
}
req->best_parent_hw = p;
req->best_parent_rate = rate;
req->rate = f->freq;
return 0;
}
static int clk_rcg2_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
}
static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
}
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
u32 *_cfg)
{
u32 cfg, mask, d_val, not2d_val, n_minus_m;
struct clk_hw *hw = &rcg->clkr.hw;
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
if (index < 0)
return index;
if (rcg->mnd_width && f->n) {
mask = BIT(rcg->mnd_width) - 1;
ret = regmap_update_bits(rcg->clkr.regmap,
RCG_M_OFFSET(rcg), mask, f->m);
if (ret)
return ret;
ret = regmap_update_bits(rcg->clkr.regmap,
RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
if (ret)
return ret;
/* Calculate 2d value */
d_val = f->n;
n_minus_m = f->n - f->m;
n_minus_m *= 2;
d_val = clamp_t(u32, d_val, f->m, n_minus_m);
not2d_val = ~d_val & mask;
ret = regmap_update_bits(rcg->clkr.regmap,
RCG_D_OFFSET(rcg), mask, not2d_val);
if (ret)
return ret;
}
mask = BIT(rcg->hid_width) - 1;
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
if (rcg->mnd_width && f->n && (f->m != f->n))
cfg |= CFG_MODE_DUAL_EDGE;
if (rcg->hw_clk_ctrl)
cfg |= CFG_HW_CLK_CTRL_MASK;
*_cfg &= ~mask;
*_cfg |= cfg;
return 0;
}
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
{
u32 cfg;
int ret;
ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
if (ret)
return ret;
ret = __clk_rcg2_configure(rcg, f, &cfg);
if (ret)
return ret;
ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
if (ret)
return ret;
return update_config(rcg);
}
static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
enum freq_policy policy)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f;
switch (policy) {
case FLOOR:
f = qcom_find_freq_floor(rcg->freq_tbl, rate);
break;
case CEIL:
f = qcom_find_freq(rcg->freq_tbl, rate);
break;
default:
return -EINVAL;
}
if (!f)
return -EINVAL;
return clk_rcg2_configure(rcg, f);
}
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return __clk_rcg2_set_rate(hw, rate, CEIL);
}
static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return __clk_rcg2_set_rate(hw, rate, CEIL);
}
static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 notn_m, n, m, d, not2d, mask;
if (!rcg->mnd_width) {
/* 50 % duty-cycle for Non-MND RCGs */
duty->num = 1;
duty->den = 2;
return 0;
}
regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d);
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
if (!not2d && !m && !notn_m) {
/* 50 % duty-cycle always */
duty->num = 1;
duty->den = 2;
return 0;
}
mask = BIT(rcg->mnd_width) - 1;
d = ~(not2d) & mask;
d = DIV_ROUND_CLOSEST(d, 2);
n = (~(notn_m) + m) & mask;
duty->num = d;
duty->den = n;
return 0;
}
static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
int ret;
/* Duty-cycle cannot be modified for non-MND RCGs */
if (!rcg->mnd_width)
return -EINVAL;
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
/* Duty-cycle cannot be modified if MND divider is in bypass mode. */
if (!(cfg & CFG_MODE_MASK))
return -EINVAL;
n = (~(notn_m) + m) & mask;
duty_per = (duty->num * 100) / duty->den;
/* Calculate 2d value */
d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
/*
* Check bit widths of 2d. If D is too big reduce duty cycle.
* Also make sure it is never zero.
*/
d = clamp_val(d, 1, mask);
if ((d / 2) > (n - m))
d = (n - m) * 2;
else if ((d / 2) < (m / 2))
d = m;
not2d = ~d & mask;
ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
not2d);
if (ret)
return ret;
return update_config(rcg);
}
const struct clk_ops clk_rcg2_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.determine_rate = clk_rcg2_determine_rate,
.set_rate = clk_rcg2_set_rate,
.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
.get_duty_cycle = clk_rcg2_get_duty_cycle,
.set_duty_cycle = clk_rcg2_set_duty_cycle,
};
EXPORT_SYMBOL_GPL(clk_rcg2_ops);
const struct clk_ops clk_rcg2_floor_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.determine_rate = clk_rcg2_determine_floor_rate,
.set_rate = clk_rcg2_set_floor_rate,
.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
.get_duty_cycle = clk_rcg2_get_duty_cycle,
.set_duty_cycle = clk_rcg2_set_duty_cycle,
};
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
const struct clk_ops clk_rcg2_mux_closest_ops = {
.determine_rate = __clk_mux_determine_rate_closest,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
};
EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
struct frac_entry {
int num;
int den;
};
static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
{ 52, 295 }, /* 119 M */
{ 11, 57 }, /* 130.25 M */
{ 63, 307 }, /* 138.50 M */
{ 11, 50 }, /* 148.50 M */
{ 47, 206 }, /* 154 M */
{ 31, 100 }, /* 205.25 M */
{ 107, 269 }, /* 268.50 M */
{ },
};
static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
{ 31, 211 }, /* 119 M */
{ 32, 199 }, /* 130.25 M */
{ 63, 307 }, /* 138.50 M */
{ 11, 60 }, /* 148.50 M */
{ 50, 263 }, /* 154 M */
{ 31, 120 }, /* 205.25 M */
{ 119, 359 }, /* 268.50 M */
{ },
};
static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct freq_tbl f = *rcg->freq_tbl;
const struct frac_entry *frac;
int delta = 100000;
s64 src_rate = parent_rate;
s64 request;
u32 mask = BIT(rcg->hid_width) - 1;
u32 hid_div;
if (src_rate == 810000000)
frac = frac_table_810m;
else
frac = frac_table_675m;
for (; frac->num; frac++) {
request = rate;
request *= frac->den;
request = div_s64(request, frac->num);
if ((src_rate < (request - delta)) ||
(src_rate > (request + delta)))
continue;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
&hid_div);
f.pre_div = hid_div;
f.pre_div >>= CFG_SRC_DIV_SHIFT;
f.pre_div &= mask;
f.m = frac->num;
f.n = frac->den;
return clk_rcg2_configure(rcg, &f);
}
return -EINVAL;
}
static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
/* Parent index is set statically in frequency table */
return clk_edp_pixel_set_rate(hw, rate, parent_rate);
}
static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f = rcg->freq_tbl;
const struct frac_entry *frac;
int delta = 100000;
s64 request;
u32 mask = BIT(rcg->hid_width) - 1;
u32 hid_div;
int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
/* Force the correct parent */
req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
if (req->best_parent_rate == 810000000)
frac = frac_table_810m;
else
frac = frac_table_675m;
for (; frac->num; frac++) {
request = req->rate;
request *= frac->den;
request = div_s64(request, frac->num);
if ((req->best_parent_rate < (request - delta)) ||
(req->best_parent_rate > (request + delta)))
continue;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
&hid_div);
hid_div >>= CFG_SRC_DIV_SHIFT;
hid_div &= mask;
req->rate = calc_rate(req->best_parent_rate,
frac->num, frac->den,
!!frac->den, hid_div);
return 0;
}
return -EINVAL;
}
const struct clk_ops clk_edp_pixel_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_edp_pixel_set_rate,
.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
.determine_rate = clk_edp_pixel_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
static int clk_byte_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f = rcg->freq_tbl;
int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
unsigned long parent_rate, div;
u32 mask = BIT(rcg->hid_width) - 1;
struct clk_hw *p;
if (req->rate == 0)
return -EINVAL;
req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
div = min_t(u32, div, mask);
req->rate = calc_rate(parent_rate, 0, 0, 0, div);
return 0;
}
static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct freq_tbl f = *rcg->freq_tbl;
unsigned long div;
u32 mask = BIT(rcg->hid_width) - 1;
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
div = min_t(u32, div, mask);
f.pre_div = div;
return clk_rcg2_configure(rcg, &f);
}
static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
/* Parent index is set statically in frequency table */
return clk_byte_set_rate(hw, rate, parent_rate);
}
const struct clk_ops clk_byte_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_byte_set_rate,
.set_rate_and_parent = clk_byte_set_rate_and_parent,
.determine_rate = clk_byte_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_byte_ops);
static int clk_byte2_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
unsigned long parent_rate, div;
u32 mask = BIT(rcg->hid_width) - 1;
struct clk_hw *p;
unsigned long rate = req->rate;
if (rate == 0)
return -EINVAL;
p = req->best_parent_hw;
req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
div = min_t(u32, div, mask);
req->rate = calc_rate(parent_rate, 0, 0, 0, div);
return 0;
}
static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct freq_tbl f = { 0 };
unsigned long div;
int i, num_parents = clk_hw_get_num_parents(hw);
u32 mask = BIT(rcg->hid_width) - 1;
u32 cfg;
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
div = min_t(u32, div, mask);
f.pre_div = div;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
for (i = 0; i < num_parents; i++) {
if (cfg == rcg->parent_map[i].cfg) {
f.src = rcg->parent_map[i].src;
return clk_rcg2_configure(rcg, &f);
}
}
return -EINVAL;
}
static int clk_byte2_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
/* Read the hardware to determine parent during set_rate */
return clk_byte2_set_rate(hw, rate, parent_rate);
}
const struct clk_ops clk_byte2_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_byte2_set_rate,
.set_rate_and_parent = clk_byte2_set_rate_and_parent,
.determine_rate = clk_byte2_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_byte2_ops);
static const struct frac_entry frac_table_pixel[] = {
{ 3, 8 },
{ 2, 9 },
{ 4, 9 },
{ 1, 1 },
{ 2, 3 },
{ }
};
static int clk_pixel_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long request, src_rate;
int delta = 100000;
const struct frac_entry *frac = frac_table_pixel;
for (; frac->num; frac++) {
request = (req->rate * frac->den) / frac->num;
src_rate = clk_hw_round_rate(req->best_parent_hw, request);
if ((src_rate < (request - delta)) ||
(src_rate > (request + delta)))
continue;
req->best_parent_rate = src_rate;
req->rate = (src_rate * frac->num) / frac->den;
return 0;
}
return -EINVAL;
}
static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct freq_tbl f = { 0 };
const struct frac_entry *frac = frac_table_pixel;
unsigned long request;
int delta = 100000;
u32 mask = BIT(rcg->hid_width) - 1;
u32 hid_div, cfg;
int i, num_parents = clk_hw_get_num_parents(hw);
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
for (i = 0; i < num_parents; i++)
if (cfg == rcg->parent_map[i].cfg) {
f.src = rcg->parent_map[i].src;
break;
}
for (; frac->num; frac++) {
request = (rate * frac->den) / frac->num;
if ((parent_rate < (request - delta)) ||
(parent_rate > (request + delta)))
continue;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
&hid_div);
f.pre_div = hid_div;
f.pre_div >>= CFG_SRC_DIV_SHIFT;
f.pre_div &= mask;
f.m = frac->num;
f.n = frac->den;
return clk_rcg2_configure(rcg, &f);
}
return -EINVAL;
}
static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate, u8 index)
{
return clk_pixel_set_rate(hw, rate, parent_rate);
}
const struct clk_ops clk_pixel_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_pixel_set_rate,
.set_rate_and_parent = clk_pixel_set_rate_and_parent,
.determine_rate = clk_pixel_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_pixel_ops);
static int clk_gfx3d_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rate_request parent_req = { .min_rate = 0, .max_rate = ULONG_MAX };
struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
struct clk_hw *xo, *p0, *p1, *p2;
unsigned long p0_rate;
u8 mux_div = cgfx->div;
int ret;
p0 = cgfx->hws[0];
p1 = cgfx->hws[1];
p2 = cgfx->hws[2];
/*
* This function does ping-pong the RCG between PLLs: if we don't
* have at least one fixed PLL and two variable ones,
* then it's not going to work correctly.
*/
if (WARN_ON(!p0 || !p1 || !p2))
return -EINVAL;
xo = clk_hw_get_parent_by_index(hw, 0);
if (req->rate == clk_hw_get_rate(xo)) {
req->best_parent_hw = xo;
return 0;
}
if (mux_div == 0)
mux_div = 1;
parent_req.rate = req->rate * mux_div;
/* This has to be a fixed rate PLL */
p0_rate = clk_hw_get_rate(p0);
if (parent_req.rate == p0_rate) {
req->rate = req->best_parent_rate = p0_rate;
req->best_parent_hw = p0;
return 0;
}
if (req->best_parent_hw == p0) {
/* Are we going back to a previously used rate? */
if (clk_hw_get_rate(p2) == parent_req.rate)
req->best_parent_hw = p2;
else
req->best_parent_hw = p1;
} else if (req->best_parent_hw == p2) {
req->best_parent_hw = p1;
} else {
req->best_parent_hw = p2;
}
clk_hw_get_rate_range(req->best_parent_hw,
&parent_req.min_rate, &parent_req.max_rate);
if (req->min_rate > parent_req.min_rate)
parent_req.min_rate = req->min_rate;
if (req->max_rate < parent_req.max_rate)
parent_req.max_rate = req->max_rate;
ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
if (ret)
return ret;
req->rate = req->best_parent_rate = parent_req.rate;
req->rate /= mux_div;
return 0;
}
static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate, u8 index)
{
struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
struct clk_rcg2 *rcg = &cgfx->rcg;
u32 cfg;
int ret;
cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
/* On some targets, the GFX3D RCG may need to divide PLL frequency */
if (cgfx->div > 1)
cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT;
ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
if (ret)
return ret;
return update_config(rcg);
}
static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
/*
* We should never get here; clk_gfx3d_determine_rate() should always
* make us use a different parent than what we're currently using, so
* clk_gfx3d_set_rate_and_parent() should always be called.
*/
return 0;
}
const struct clk_ops clk_gfx3d_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_gfx3d_set_rate,
.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
.determine_rate = clk_gfx3d_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
static int clk_rcg2_set_force_enable(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const char *name = clk_hw_get_name(hw);
int ret, count;
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
CMD_ROOT_EN, CMD_ROOT_EN);
if (ret)
return ret;
/* wait for RCG to turn ON */
for (count = 500; count > 0; count--) {
if (clk_rcg2_is_enabled(hw))
return 0;
udelay(1);
}
pr_err("%s: RCG did not turn on\n", name);
return -ETIMEDOUT;
}
static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
CMD_ROOT_EN, 0);
}
static int
clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int ret;
ret = clk_rcg2_set_force_enable(hw);
if (ret)
return ret;
ret = clk_rcg2_configure(rcg, f);
if (ret)
return ret;
return clk_rcg2_clear_force_enable(hw);
}
static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f;
f = qcom_find_freq(rcg->freq_tbl, rate);
if (!f)
return -EINVAL;
/*
* In case clock is disabled, update the M, N and D registers, cache
* the CFG value in parked_cfg and don't hit the update bit of CMD
* register.
*/
if (!clk_hw_is_enabled(hw))
return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg);
return clk_rcg2_shared_force_enable_clear(hw, f);
}
static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
}
static int clk_rcg2_shared_enable(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int ret;
/*
* Set the update bit because required configuration has already
* been written in clk_rcg2_shared_set_rate()
*/
ret = clk_rcg2_set_force_enable(hw);
if (ret)
return ret;
/* Write back the stored configuration corresponding to current rate */
ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg);
if (ret)
return ret;
ret = update_config(rcg);
if (ret)
return ret;
return clk_rcg2_clear_force_enable(hw);
}
static void clk_rcg2_shared_disable(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
/*
* Store current configuration as switching to safe source would clear
* the SRC and DIV of CFG register
*/
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
/*
* Park the RCG at a safe configuration - sourced off of safe source.
* Force enable and disable the RCG while configuring it to safeguard
* against any update signal coming from the downstream clock.
* The current parent is still prepared and enabled at this point, and
* the safe source is always on while application processor subsystem
* is online. Therefore, the RCG can safely switch its parent.
*/
clk_rcg2_set_force_enable(hw);
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
update_config(rcg);
clk_rcg2_clear_force_enable(hw);
}
static u8 clk_rcg2_shared_get_parent(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
/* If the shared rcg is parked use the cached cfg instead */
if (!clk_hw_is_enabled(hw))
return __clk_rcg2_get_parent(hw, rcg->parked_cfg);
return clk_rcg2_get_parent(hw);
}
static int clk_rcg2_shared_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
/* If the shared rcg is parked only update the cached cfg */
if (!clk_hw_is_enabled(hw)) {
rcg->parked_cfg &= ~CFG_SRC_SEL_MASK;
rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
return 0;
}
return clk_rcg2_set_parent(hw, index);
}
static unsigned long
clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
/* If the shared rcg is parked use the cached cfg instead */
if (!clk_hw_is_enabled(hw))
return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg);
return clk_rcg2_recalc_rate(hw, parent_rate);
}
const struct clk_ops clk_rcg2_shared_ops = {
.enable = clk_rcg2_shared_enable,
.disable = clk_rcg2_shared_disable,
.get_parent = clk_rcg2_shared_get_parent,
.set_parent = clk_rcg2_shared_set_parent,
.recalc_rate = clk_rcg2_shared_recalc_rate,
.determine_rate = clk_rcg2_determine_rate,
.set_rate = clk_rcg2_shared_set_rate,
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
};
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
/* Common APIs to be used for DFS based RCGR */
static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
struct freq_tbl *f)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct clk_hw *p;
unsigned long prate = 0;
u32 val, mask, cfg, mode, src;
int i, num_parents;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
mask = BIT(rcg->hid_width) - 1;
f->pre_div = 1;
if (cfg & mask)
f->pre_div = cfg & mask;
src = cfg & CFG_SRC_SEL_MASK;
src >>= CFG_SRC_SEL_SHIFT;
num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++) {
if (src == rcg->parent_map[i].cfg) {
f->src = rcg->parent_map[i].src;
p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
prate = clk_hw_get_rate(p);
}
}
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
if (mode) {
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
&val);
val &= mask;
f->m = val;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
&val);
val = ~val;
val &= mask;
val += f->m;
f->n = val;
}
f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
}
static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
{
struct freq_tbl *freq_tbl;
int i;
/* Allocate space for 1 extra since table is NULL terminated */
freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
if (!freq_tbl)
return -ENOMEM;
rcg->freq_tbl = freq_tbl;
for (i = 0; i < MAX_PERF_LEVEL; i++)
clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
return 0;
}
static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int ret;
if (!rcg->freq_tbl) {
ret = clk_rcg2_dfs_populate_freq_table(rcg);
if (ret) {
pr_err("Failed to update DFS tables for %s\n",
clk_hw_get_name(hw));
return ret;
}
}
return clk_rcg2_determine_rate(hw, req);
}
static unsigned long
clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
regmap_read(rcg->clkr.regmap,
rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
level &= GENMASK(4, 1);
level >>= 1;
if (rcg->freq_tbl)
return rcg->freq_tbl[level].freq;
/*
* Assume that parent_rate is actually the parent because
* we can't do any better at figuring it out when the table
* hasn't been populated yet. We only populate the table
* in determine_rate because we can't guarantee the parents
* will be registered with the framework until then.
*/
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
&cfg);
mask = BIT(rcg->hid_width) - 1;
pre_div = 1;
if (cfg & mask)
pre_div = cfg & mask;
mode = cfg & CFG_MODE_MASK;
mode >>= CFG_MODE_SHIFT;
if (mode) {
mask = BIT(rcg->mnd_width) - 1;
regmap_read(rcg->clkr.regmap,
rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
m &= mask;
regmap_read(rcg->clkr.regmap,
rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
n = ~n;
n &= mask;
n += m;
}
return calc_rate(parent_rate, m, n, mode, pre_div);
}
static const struct clk_ops clk_rcg2_dfs_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.determine_rate = clk_rcg2_dfs_determine_rate,
.recalc_rate = clk_rcg2_dfs_recalc_rate,
};
static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
struct regmap *regmap)
{
struct clk_rcg2 *rcg = data->rcg;
struct clk_init_data *init = data->init;
u32 val;
int ret;
ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
if (ret)
return -EINVAL;
if (!(val & SE_CMD_DFS_EN))
return 0;
/*
* Rate changes with consumer writing a register in
* their own I/O region
*/
init->flags |= CLK_GET_RATE_NOCACHE;
init->ops = &clk_rcg2_dfs_ops;
rcg->freq_tbl = NULL;
return 0;
}
int qcom_cc_register_rcg_dfs(struct regmap *regmap,
const struct clk_rcg_dfs_data *rcgs, size_t len)
{
int i, ret;
for (i = 0; i < len; i++) {
ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
if (ret)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
struct freq_tbl f = { 0 };
u32 mask = BIT(rcg->hid_width) - 1;
u32 hid_div, cfg;
int i, num_parents = clk_hw_get_num_parents(hw);
unsigned long num, den;
rational_best_approximation(parent_rate, rate,
GENMASK(rcg->mnd_width - 1, 0),
GENMASK(rcg->mnd_width - 1, 0), &den, &num);
if (!num || !den)
return -EINVAL;
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
hid_div = cfg;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
for (i = 0; i < num_parents; i++) {
if (cfg == rcg->parent_map[i].cfg) {
f.src = rcg->parent_map[i].src;
break;
}
}
f.pre_div = hid_div;
f.pre_div >>= CFG_SRC_DIV_SHIFT;
f.pre_div &= mask;
if (num != den) {
f.m = num;
f.n = den;
} else {
f.m = 0;
f.n = 0;
}
return clk_rcg2_configure(rcg, &f);
}
static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
return clk_rcg2_dp_set_rate(hw, rate, parent_rate);
}
static int clk_rcg2_dp_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
unsigned long num, den;
u64 tmp;
/* Parent rate is a fixed phy link rate */
rational_best_approximation(req->best_parent_rate, req->rate,
GENMASK(rcg->mnd_width - 1, 0),
GENMASK(rcg->mnd_width - 1, 0), &den, &num);
if (!num || !den)
return -EINVAL;
tmp = req->best_parent_rate * num;
do_div(tmp, den);
req->rate = tmp;
return 0;
}
const struct clk_ops clk_dp_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_rcg2_dp_set_rate,
.set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent,
.determine_rate = clk_rcg2_dp_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_dp_ops);
| linux-master | drivers/clk/qcom/clk-rcg2.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023 Otto Pflüger
*
* Based on gcc-msm8953.c:
* Copyright 2021, The Linux Foundation. All rights reserved.
* with parts taken from gcc-qcs404.c:
* Copyright 2018, The Linux Foundation. All rights reserved.
* and gcc-msm8939.c:
* Copyright 2020 Linaro Limited
* adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release:
* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8917.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_XO,
DT_SLEEP_CLK,
DT_DSI0PLL,
DT_DSI0PLL_BYTE,
};
enum {
P_XO,
P_SLEEP_CLK,
P_GPLL0,
P_GPLL3,
P_GPLL4,
P_GPLL6,
P_DSI0PLL,
P_DSI0PLL_BYTE,
};
static struct clk_alpha_pll gpll0_sleep_clk_src = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45008,
.enable_mask = BIT(23),
.enable_is_inverted = true,
.hw.init = &(struct clk_init_data){
.name = "gpll0_sleep_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_XO,
},
.num_parents = 1,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gpll0_early",
.parent_hws = (const struct clk_hw*[]){
&gpll0_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static const struct pll_vco gpll3_p_vco[] = {
{ 700000000, 1400000000, 0 },
};
static const struct alpha_pll_config gpll3_early_config = {
.l = 63,
.config_ctl_val = 0x4001055b,
.early_output_mask = 0,
.post_div_mask = GENMASK(11, 8),
.post_div_val = BIT(8),
};
static struct clk_alpha_pll gpll3_early = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpll3_p_vco,
.num_vco = ARRAY_SIZE(gpll3_p_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpll3_early",
.parent_data = &(const struct clk_parent_data) {
.index = DT_XO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll3 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_hws = (const struct clk_hw*[]){
&gpll3_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll4_early = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_early",
.parent_data = &(const struct clk_parent_data) {
.index = DT_XO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_hws = (const struct clk_hw*[]){
&gpll4_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_pll gpll6_early = {
.l_reg = 0x37004,
.m_reg = 0x37008,
.n_reg = 0x3700c,
.config_reg = 0x37014,
.mode_reg = 0x37000,
.status_reg = 0x3701c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_early",
.parent_data = &(const struct clk_parent_data) {
.index = DT_XO,
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll6 = {
.enable_reg = 0x45000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_hws = (const struct clk_hw*[]){
&gpll6_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct parent_map gcc_xo_gpll0_out_aux_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll6_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_sleep_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL4, 3 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll4_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.freq_tbl = ftbl_apss_ahb_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0c00c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x0d000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0f000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x0c024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x0d014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x0f024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 72, 15625),
F(7372800, P_GPLL0, 1, 144, 15625),
F(14745600, P_GPLL0, 1, 288, 15625),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 1, 2, 25),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x0c044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x0d034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_byte0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_byte_data[] = {
{ .index = DT_XO },
{ .index = DT_DSI0PLL_BYTE },
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.hid_width = 5,
.parent_map = gcc_byte0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "byte0_clk_src",
.parent_data = gcc_byte_data,
.num_parents = ARRAY_SIZE(gcc_byte_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_gp0_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
F(40000000, P_GPLL0, 10, 1, 2),
F(61540000, P_GPLL0, 13, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 camss_top_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.hid_width = 5,
.freq_tbl = ftbl_camss_top_ahb_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_top_ahb_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 1, 3, 64),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x51000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_cci_clk_src,
.parent_map = gcc_xo_gpll0_out_aux_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cci_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_cpp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 3 },
};
static const struct clk_parent_data gcc_cpp_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.hw },
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(308570000, P_GPLL0, 3.5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
.freq_tbl = ftbl_cpp_clk_src,
.parent_map = gcc_cpp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cpp_clk_src",
.parent_data = gcc_cpp_data,
.num_parents = ARRAY_SIZE(gcc_cpp_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.freq_tbl = ftbl_crypto_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_csi_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3c020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi2_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x4f000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi1phytimer_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_xo_gpll0_out_aux_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "esc0_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_gfx3d_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL3, 2 },
{ P_GPLL6, 3 },
};
static const struct parent_map gcc_gfx3d_map_qm215[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_GPLL3, 2 },
{ P_GPLL6, 6 },
};
static const struct clk_parent_data gcc_gfx3d_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll3.clkr.hw },
{ .hw = &gpll6.hw },
};
static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
F(240000000, P_GPLL6, 4.5, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(270000000, P_GPLL6, 4, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL3, 1, 0, 0),
F(484800000, P_GPLL3, 1, 0, 0),
F(500000000, P_GPLL3, 1, 0, 0),
F(523200000, P_GPLL3, 1, 0, 0),
F(550000000, P_GPLL3, 1, 0, 0),
F(598000000, P_GPLL3, 1, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.freq_tbl = ftbl_gfx3d_clk_src,
.parent_map = gcc_gfx3d_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gfx3d_clk_src",
.parent_data = gcc_gfx3d_data,
.num_parents = ARRAY_SIZE(gcc_gfx3d_data),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
}
};
static const struct freq_tbl ftbl_gp_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x57000,
.hid_width = 5,
.freq_tbl = ftbl_jpeg0_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "jpeg0_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_mclk_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL6, 1, 1, 45),
F(66667000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk0_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk1_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x5c000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_sleep_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk2_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_sleep_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(145450000, P_GPLL0, 5.5, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.freq_tbl = ftbl_mdp_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mdp_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_pclk_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
};
static const struct clk_parent_data gcc_pclk_data[] = {
{ .index = DT_XO },
{ .index = DT_DSI0PLL },
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pclk0_clk_src",
.parent_data = gcc_pclk_data,
.num_parents = ARRAY_SIZE(gcc_pclk_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.freq_tbl = ftbl_pdm2_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.hid_width = 5,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_sdcc1_apps_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};
static const struct clk_parent_data gcc_sdcc1_apss_data[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL4, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(384000000, P_GPLL4, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.parent_map = gcc_sdcc1_apps_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_sdcc1_apss_data,
.num_parents = ARRAY_SIZE(gcc_sdcc1_apss_data),
.ops = &clk_rcg2_floor_ops,
}
};
static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_floor_ops,
}
};
static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb_hs_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(180000000, P_GPLL6, 6, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
F(329140000, P_GPLL4, 3.5, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4c000,
.hid_width = 5,
.freq_tbl = ftbl_vcodec0_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vcodec0_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_vfe_clk_src[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(329140000, P_GPLL4, 3.5, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.freq_tbl = ftbl_vfe_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vfe0_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x58054,
.hid_width = 5,
.freq_tbl = ftbl_vfe_clk_src,
.parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vfe1_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_vsync_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.freq_tbl = ftbl_vsync_clk_src,
.parent_map = gcc_xo_gpll0_out_aux_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vsync_clk_src",
.parent_data = gcc_xo_gpll0_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apss_tcu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x59034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x59030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gpu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x0b008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x04020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x05020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x0c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x0d010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x0f020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0f020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x0c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x0d00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x0f01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x0c03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0c03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x0d02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0d02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x56004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x5101c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x58040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x5803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2_ahb_clk = {
.halt_reg = 0x3c040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2_clk = {
.halt_reg = 0x3c03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2phy_clk = {
.halt_reg = 0x3c048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x4f01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2pix_clk = {
.halt_reg = 0x3c058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2rdi_clk = {
.halt_reg = 0x3c050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi_vfe1_clk = {
.halt_reg = 0x58074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x54018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x55018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_jpeg0_clk = {
.halt_reg = 0x57020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.halt_reg = 0x57024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_jpeg_axi_clk = {
.halt_reg = 0x57028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x52018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x53018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x53018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x5c018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5c018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_micro_ahb_clk = {
.halt_reg = 0x5600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x5a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe0_ahb_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe0_axi_clk = {
.halt_reg = 0x58048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x58038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe1_ahb_clk = {
.halt_reg = 0x58060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe1_axi_clk = {
.halt_reg = 0x58068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_vfe1_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_cpp_tbu_clk = {
.halt_reg = 0x12040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cpp_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_dcc_clk = {
.halt_reg = 0x77004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x77004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_dcc_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_gfx_tbu_clk = {
.halt_reg = 0x12010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tcu_clk = {
.halt_reg = 0x12020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data) {
.name = "gcc_jpeg_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdp_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4d088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data) {
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_dap_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x5d014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data) {
.name = "gcc_smmu_cfg_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x41008,
.clkr = {
.enable_reg = 0x41008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
.halt_reg = 0x41030,
.clkr = {
.enable_reg = 0x41030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_phy_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_ahb_clk = {
.halt_reg = 0x4c020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_axi_clk = {
.halt_reg = 0x4c024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.halt_reg = 0x4c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_core0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_venus0_vcodec0_clk = {
.halt_reg = 0x4c01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_venus_tbu_clk = {
.halt_reg = 0x12014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_vfe1_tbu_clk = {
.halt_reg = 0x12090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data) {
.name = "gcc_vfe1_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_vfe_tbu_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data) {
.name = "gcc_vfe_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
.cxc_count = 2,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x4c028,
.cxcs = (unsigned int []){ 0x4c02c },
.cxc_count = 1,
.pd = {
.name = "venus_core0",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
.cxc_count = 2,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x5701c,
.cxcs = (unsigned int []){ 0x57020, 0x57028 },
.cxc_count = 2,
.pd = {
.name = "jpeg_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe0_gdsc = {
.gdscr = 0x58034,
.cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
.cxc_count = 4,
.pd = {
.name = "vfe0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe1_gdsc = {
.gdscr = 0x5806c,
.cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
.cxc_count = 4,
.pd = {
.name = "vfe1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gx_gdsc = {
.gdscr = 0x5901c,
.clamp_io_ctrl = 0x5b00c,
.cxcs = (unsigned int []){ 0x59000, 0x59020 },
.cxc_count = 2,
.pd = {
.name = "oxili_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO,
};
static struct gdsc cpp_gdsc = {
.gdscr = 0x58078,
.cxcs = (unsigned int []){ 0x5803c, 0x58064 },
.cxc_count = 2,
.pd = {
.name = "cpp_gdsc",
},
.flags = ALWAYS_ON,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8917_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_EARLY] = &gpll3_early.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL6] = &gpll6,
[GPLL6_EARLY] = &gpll6_early.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8917_resets[] = {
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
[GCC_MSS_BCR] = { 0x71000 },
[GCC_QUSB2_PHY_BCR] = { 0x4103c },
[GCC_USB_HS_BCR] = { 0x41000 },
[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
};
static const struct regmap_config gcc_msm8917_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static struct gdsc *gcc_msm8917_gdscs[] = {
[CPP_GDSC] = &cpp_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[OXILI_GX_GDSC] = &oxili_gx_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_GDSC] = &venus_gdsc,
[VFE0_GDSC] = &vfe0_gdsc,
[VFE1_GDSC] = &vfe1_gdsc,
};
static const struct qcom_cc_desc gcc_msm8917_desc = {
.config = &gcc_msm8917_regmap_config,
.clks = gcc_msm8917_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
.resets = gcc_msm8917_resets,
.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
.gdscs = gcc_msm8917_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
};
static const struct qcom_cc_desc gcc_qm215_desc = {
.config = &gcc_msm8917_regmap_config,
.clks = gcc_msm8917_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
.resets = gcc_msm8917_resets,
.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
.gdscs = gcc_msm8917_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
};
static int gcc_msm8917_probe(struct platform_device *pdev)
{
struct regmap *regmap;
const struct qcom_cc_desc *gcc_desc;
gcc_desc = of_device_get_match_data(&pdev->dev);
if (gcc_desc == &gcc_qm215_desc)
gfx3d_clk_src.parent_map = gcc_gfx3d_map_qm215;
regmap = qcom_cc_map(pdev, gcc_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
return qcom_cc_really_probe(pdev, gcc_desc, regmap);
}
static const struct of_device_id gcc_msm8917_match_table[] = {
{ .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
{},
};
static struct platform_driver gcc_msm8917_driver = {
.probe = gcc_msm8917_probe,
.driver = {
.name = "gcc-msm8917",
.of_match_table = gcc_msm8917_match_table,
},
};
static int __init gcc_msm8917_init(void)
{
return platform_driver_register(&gcc_msm8917_driver);
}
core_initcall(gcc_msm8917_init);
static void __exit gcc_msm8917_exit(void)
{
platform_driver_unregister(&gcc_msm8917_driver);
}
module_exit(gcc_msm8917_exit);
MODULE_DESCRIPTION("Qualcomm GCC MSM8917 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-msm8917.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
#define CX_GMU_CBCR_SLEEP_MASK 0xF
#define CX_GMU_CBCR_SLEEP_SHIFT 4
#define CX_GMU_CBCR_WAKE_MASK 0xF
#define CX_GMU_CBCR_WAKE_SHIFT 8
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL0_OUT_ODD,
P_GPU_CC_PLL1_OUT_EVEN,
P_GPU_CC_PLL1_OUT_MAIN,
P_GPU_CC_PLL1_OUT_ODD,
P_CRC_DIV,
};
static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 506MHz Configuration*/
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1A,
.alpha = 0x5AAA,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000002,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static struct clk_fixed_factor crc_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "crc_div",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
/* 514MHz Configuration*/
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1A,
.alpha = 0xC555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000002,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CRC_DIV, 1 },
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
{ .hw = &crc_div.hw },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(253000000, P_CRC_DIV, 1, 0, 0),
F(355000000, P_CRC_DIV, 1, 0, 0),
F(430000000, P_CRC_DIV, 1, 0, 0),
F(565000000, P_CRC_DIV, 1, 0, 0),
F(650000000, P_CRC_DIV, 1, 0, 0),
F(800000000, P_CRC_DIV, 1, 0, 0),
F(825000000, P_CRC_DIV, 1, 0, 0),
F(850000000, P_CRC_DIV, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_acd_ahb_clk = {
.halt_reg = 0x1168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_acd_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_acd_cxo_clk = {
.halt_reg = 0x1164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1164,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_acd_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
.halt_reg = 0x10a8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_slv_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_cxo_clk = {
.halt_reg = 0x1060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x1058,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | POLL_CFG_GDSCR,
};
static struct clk_hw *gpu_cc_sm6350_hws[] = {
[GPU_CC_CRC_DIV] = &crc_div.hw,
};
static struct clk_regmap *gpu_cc_sm6350_clocks[] = {
[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
};
static struct gdsc *gpu_cc_sm6350_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm6350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8008,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm6350_desc = {
.config = &gpu_cc_sm6350_regmap_config,
.clk_hws = gpu_cc_sm6350_hws,
.num_clk_hws = ARRAY_SIZE(gpu_cc_sm6350_hws),
.clks = gpu_cc_sm6350_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm6350_clocks),
.gdscs = gpu_cc_sm6350_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6350_gdscs),
};
static const struct of_device_id gpu_cc_sm6350_match_table[] = {
{ .compatible = "qcom,sm6350-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm6350_match_table);
static int gpu_cc_sm6350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
unsigned int value, mask;
regmap = qcom_cc_map(pdev, &gpu_cc_sm6350_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Configure gpu_cc_cx_gmu_clk with recommended wakeup/sleep settings */
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap);
}
static struct platform_driver gpu_cc_sm6350_driver = {
.probe = gpu_cc_sm6350_probe,
.driver = {
.name = "sm6350-gpucc",
.of_match_table = gpu_cc_sm6350_match_table,
},
};
static int __init gpu_cc_sm6350_init(void)
{
return platform_driver_register(&gpu_cc_sm6350_driver);
}
core_initcall(gpu_cc_sm6350_init);
static void __exit gpu_cc_sm6350_exit(void)
{
platform_driver_unregister(&gpu_cc_sm6350_driver);
}
module_exit(gpu_cc_sm6350_exit);
MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sm6350.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_AUD_REF_CLK,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static const struct clk_div_table post_div_table_trion_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_trion_even,
.num_post_div = ARRAY_SIZE(post_div_table_trion_even),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_trion_ops,
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x1a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x1c000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_1[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_2[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parents_3[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_5[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_6[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_AUD_REF_CLK, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_7[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac_ptp_clk_src = {
.cmd_rcgr = 0x6038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_emac_ptp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
F(2500000, P_BI_TCXO, 1, 25, 192),
F(5000000, P_BI_TCXO, 1, 25, 96),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
.cmd_rcgr = 0x601c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_rgmii_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b02c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d02c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
.cmd_rcgr = 0x6f014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qspi_core_clk_src = {
.cmd_rcgr = 0x4b008,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qspi_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
{ }
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x173a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x174d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x17608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17998,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x183a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x184d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x18608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
F(105495, P_BI_TCXO, 2, 1, 91),
{ }
};
static struct clk_rcg2 gcc_tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x75020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x75060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x75094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x75078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x77060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x77094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x1001c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x10034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x10060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x90018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x750c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x750c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x750c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x750c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750c0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_aggre_ufs_card_axi_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x770c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x770c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x770c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770c0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_aggre_ufs_phy_axi_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0xf07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x1007c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1007c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
/*
* Clock ON depends on external parent 'config noc', so cant poll
* delay and also mark as crtitical for camss boot
*/
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0xb008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xb008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0xb030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0xb034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* XO critical input to camss, so no need to poll */
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0xb044,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0xf078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x10078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw },
.num_parents = 1,
/* required for cpuss */
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_dvm_bus_clk = {
.halt_reg = 0x48190,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48190,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_dvm_bus_clk",
/* required for cpuss */
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_gnoc_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x48004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_gnoc_clk",
/* required for cpuss */
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/*
* Clock ON depends on external parent 'config noc', so cant poll
* delay and also mark as crtitical for disp boot
*/
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0xb00c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xb00c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0xb038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0xb03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* XO critical input to disp, so no need to poll */
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0xb048,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_axi_clk = {
.halt_reg = 0x6010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_ptp_clk = {
.halt_reg = 0x6034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_emac_ptp_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_rgmii_clk = {
.halt_reg = 0x6018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_rgmii_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_emac_rgmii_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_slv_ahb_clk = {
.halt_reg = 0x6014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x6014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x71004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
/* required for gpu */
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0_out_even.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_at_clk = {
.halt_reg = 0x4d010,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_cfg_ahb_clk = {
.halt_reg = 0x4d004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_cfg_ahb_clk",
/* required for npu */
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0_out_even.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_trig_clk = {
.halt_reg = 0x4d00c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_trig_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_refgen_clk = {
.halt_reg = 0x6f02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_refgen_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_refgen_clk = {
.halt_reg = 0x6f030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_refgen_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_clk = {
.halt_reg = 0x8c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b024,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_clkref_clk = {
.halt_reg = 0x8c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d024,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0xb018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0xb010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0xb014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
.halt_reg = 0x4b000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_core_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qspi_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x17274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x173a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x174d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x17604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x17734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x17864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x17994,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x183a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x184d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x18604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x4819c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw },
.num_parents = 1,
/* required for cpuss */
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_tsif_ref_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_axi_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_card_clkref_clk = {
.halt_reg = 0x8c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_ice_core_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x75090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
.halt_reg = 0x75090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75090,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_phy_aux_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x750ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75058,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_unipro_core_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_ice_core_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_phy_aux_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x770ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77058,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_unipro_core_clk.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x10014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_clkref_clk = {
.halt_reg = 0x8c028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x10050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x10054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x10058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
/*
* Clock ON depends on external parent 'config noc', so cant poll
* delay and also mark as crtitical for video boot
*/
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0xb004,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xb004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axic_clk = {
.halt_reg = 0xb02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axic_clk",
.ops = &clk_branch2_ops,
},
},
};
/* XO critical input to video, so no need to poll */
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0xb040,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc emac_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "emac_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
&gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
&gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
[GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
[GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
[GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
[GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
&gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
&gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
&gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
[GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL9] = &gpll9.clkr,
};
static const struct qcom_reset_map gcc_sm8150_resets[] = {
[GCC_EMAC_BCR] = { 0x6000 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_NPU_BCR] = { 0x4d000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_QSPI_BCR] = { 0x24008 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
static struct gdsc *gcc_sm8150_gdscs[] = {
[EMAC_GDSC] = &emac_gdsc,
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
};
static const struct regmap_config gcc_sm8150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9c040,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm8150_desc = {
.config = &gcc_sm8150_regmap_config,
.clks = gcc_sm8150_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
.resets = gcc_sm8150_resets,
.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
.gdscs = gcc_sm8150_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
};
static const struct of_device_id gcc_sm8150_match_table[] = {
{ .compatible = "qcom,gcc-sm8150" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
static int gcc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
}
static struct platform_driver gcc_sm8150_driver = {
.probe = gcc_sm8150_probe,
.driver = {
.name = "gcc-sm8150",
.of_match_table = gcc_sm8150_match_table,
},
};
static int __init gcc_sm8150_init(void)
{
return platform_driver_register(&gcc_sm8150_driver);
}
subsys_initcall(gcc_sm8150_init);
static void __exit gcc_sm8150_exit(void)
{
platform_driver_unregister(&gcc_sm8150_driver);
}
module_exit(gcc_sm8150_exit);
MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sm8150.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_IFACE,
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK
};
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL0_OUT_MAIN,
P_CAM_CC_PLL0_OUT_ODD,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_EVEN,
P_CAM_CC_PLL2_OUT_MAIN,
P_CAM_CC_PLL3_OUT_EVEN,
P_CAM_CC_PLL4_OUT_EVEN,
P_CAM_CC_PLL5_OUT_EVEN,
P_CAM_CC_PLL6_OUT_EVEN,
P_CAM_CC_PLL7_OUT_EVEN,
P_CAM_CC_PLL8_OUT_EVEN,
P_SLEEP_CLK,
};
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct pll_vco rivian_evo_vco[] = {
{ 864000000, 1056000000, 0 },
};
static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct alpha_pll_config cam_cc_pll0_config = {
.l = 0x3e,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00008400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
{ 0x2, 3 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
.offset = 0x0,
.post_div_shift = 14,
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll0_out_odd",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll1_config = {
.l = 0x25,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll1",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll2_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x90008820,
.config_ctl_hi_val = 0x00890263,
.config_ctl_hi1_val = 0x00000217,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = rivian_evo_vco,
.num_vco = ARRAY_SIZE(rivian_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll2",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_rivian_evo_ops,
},
},
};
static const struct alpha_pll_config cam_cc_pll3_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll3",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.offset = 0x3000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll3_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll4_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll4",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
.offset = 0x4000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll4_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll4_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll5_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll5 = {
.offset = 0x5000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll5",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
.offset = 0x5000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll5_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll5_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll5.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll6_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll6 = {
.offset = 0x6000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll6",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
.offset = 0x6000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll6_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll7_config = {
.l = 0x2d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll7 = {
.offset = 0x7000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll7",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
.offset = 0x7000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll7_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll7_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll7.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct alpha_pll_config cam_cc_pll8_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000400,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll cam_cc_pll8 = {
.offset = 0x8000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll8",
.parent_data = &pll_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
.offset = 0x8000,
.post_div_shift = 10,
.post_div_table = post_div_table_cam_cc_pll8_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_pll8_out_even",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll8.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
{ P_CAM_CC_PLL8_OUT_EVEN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll0.clkr.hw },
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
{ .hw = &cam_cc_pll8_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll2.clkr.hw },
{ .hw = &cam_cc_pll2.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll5_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
};
static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_cc_pll7_out_even.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_8[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_8[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map cam_cc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
{ .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x10050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
.cmd_rcgr = 0x13194,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0x1312c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.cmd_rcgr = 0x13148,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0x1104c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x150e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x15104,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x15124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x1514c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
.cmd_rcgr = 0x1516c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi4phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
.cmd_rcgr = 0x1518c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi5phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csid_clk_src = {
.cmd_rcgr = 0x13174,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csid_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x10018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0x13108,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0x11018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0x12018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_2_clk_src = {
.cmd_rcgr = 0x12064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.cmd_rcgr = 0x13000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0x13024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
.cmd_rcgr = 0x1008c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0x130dc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0x15000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0x1501c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0x15038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0x15054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.cmd_rcgr = 0x15070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
.cmd_rcgr = 0x1508c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk5_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk6_clk_src = {
.cmd_rcgr = 0x150a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk6_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 cam_cc_mclk7_clk_src = {
.cmd_rcgr = 0x150c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk7_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
.cmd_rcgr = 0x131bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
.cmd_rcgr = 0x13064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_6,
.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_clk_src",
.parent_data = cam_cc_parent_data_6,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
.cmd_rcgr = 0x130ac,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_7,
.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_clk_src",
.parent_data = cam_cc_parent_data_7,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_sleep_clk_src = {
.cmd_rcgr = 0x13210,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_8,
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sleep_clk_src",
.parent_data = cam_cc_parent_data_8,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x10034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_xo_clk_src = {
.cmd_rcgr = 0x131f4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_9,
.freq_tbl = ftbl_cam_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_xo_clk_src",
.parent_data = cam_cc_parent_data_9_ao,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch cam_cc_gdsc_clk = {
.halt_reg = 0x1320c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1320c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_gdsc_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x1004c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1004c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x10068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_fast_ahb_clk = {
.halt_reg = 0x10030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_bps_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_clk = {
.halt_reg = 0x131ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
.halt_reg = 0x131b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_camnoc_dcd_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0x13144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_1_clk = {
.halt_reg = 0x13160,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13160,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cci_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_core_ahb_clk = {
.halt_reg = 0x131f0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x131f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_core_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0x13164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_bps_clk = {
.halt_reg = 0x10070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_bps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
.halt_reg = 0x1316c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1316c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_0_clk = {
.halt_reg = 0x11038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_1_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_2_clk = {
.halt_reg = 0x12084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ife_lite_clk = {
.halt_reg = 0x13020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
.halt_reg = 0x100ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_ipe_nps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sbi_clk = {
.halt_reg = 0x100ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100ec,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sbi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_0_clk = {
.halt_reg = 0x13084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_sfe_1_clk = {
.halt_reg = 0x130cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_cpas_sfe_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0x150f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150f8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0x1511c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1511c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0x1513c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1513c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0x15164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15164,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi4phytimer_clk = {
.halt_reg = 0x15184,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15184,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi4phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi4phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi5phytimer_clk = {
.halt_reg = 0x151a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csi5phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi5phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csid_clk = {
.halt_reg = 0x1318c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1318c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
.halt_reg = 0x15100,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15100,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csid_csiphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0x150fc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150fc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0x15120,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0x15140,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15140,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0x15168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15168,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy4_clk = {
.halt_reg = 0x15188,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15188,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy5_clk = {
.halt_reg = 0x151a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x151a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_csiphy5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_ahb_clk = {
.halt_reg = 0x13128,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13128,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0x13120,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_icp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0x11030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_dsp_clk = {
.halt_reg = 0x1103c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1103c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_dsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
.halt_reg = 0x11048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x11048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_0_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0x12030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_dsp_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1203c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_dsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
.halt_reg = 0x12048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_1_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_clk = {
.halt_reg = 0x1207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1207c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_dsp_clk = {
.halt_reg = 0x12088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_dsp_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
.halt_reg = 0x12094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_2_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
.halt_reg = 0x13048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_clk = {
.halt_reg = 0x13018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.halt_reg = 0x13044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_csid_clk = {
.halt_reg = 0x1303c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1303c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ife_lite_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
.halt_reg = 0x100c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_clk = {
.halt_reg = 0x100a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
.halt_reg = 0x100c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_nps_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_pps_clk = {
.halt_reg = 0x100b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_pps_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_nps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
.halt_reg = 0x100c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_ipe_pps_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0x130f4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130f4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0x15018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0x15034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0x15050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0x1506c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1506c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk4_clk = {
.halt_reg = 0x15088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x15088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk5_clk = {
.halt_reg = 0x150a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk6_clk = {
.halt_reg = 0x150c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk6_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk7_clk = {
.halt_reg = 0x150dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x150dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_mclk7_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_clk = {
.halt_reg = 0x131d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_qdss_debug_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
.halt_reg = 0x131d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x131d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_ahb_clk = {
.halt_reg = 0x100f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sbi_clk = {
.halt_reg = 0x100e4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x100e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sbi_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_clk = {
.halt_reg = 0x1307c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1307c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
.halt_reg = 0x13090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_0_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_clk = {
.halt_reg = 0x130c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130c4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
.halt_reg = 0x130d8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x130d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sfe_1_fast_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sleep_clk = {
.halt_reg = 0x13228,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13228,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *cam_cc_sm8450_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
};
static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
[CAM_CC_BPS_BCR] = { 0x10000 },
[CAM_CC_ICP_BCR] = { 0x13104 },
[CAM_CC_IFE_0_BCR] = { 0x11000 },
[CAM_CC_IFE_1_BCR] = { 0x12000 },
[CAM_CC_IFE_2_BCR] = { 0x1204c },
[CAM_CC_IPE_0_BCR] = { 0x10074 },
[CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 },
[CAM_CC_SBI_BCR] = { 0x100cc },
[CAM_CC_SFE_0_BCR] = { 0x1304c },
[CAM_CC_SFE_1_BCR] = { 0x13094 },
};
static const struct regmap_config cam_cc_sm8450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1601c,
.fast_io = true,
};
static struct gdsc titan_top_gdsc;
static struct gdsc bps_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "bps_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x10078,
.pd = {
.name = "ipe_0_gdsc",
},
.flags = HW_CTRL | POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sbi_gdsc = {
.gdscr = 0x100d0,
.pd = {
.name = "sbi_gdsc",
},
.flags = POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_0_gdsc = {
.gdscr = 0x11004,
.pd = {
.name = "ife_0_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_1_gdsc = {
.gdscr = 0x12004,
.pd = {
.name = "ife_1_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_2_gdsc = {
.gdscr = 0x12050,
.pd = {
.name = "ife_2_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sfe_0_gdsc = {
.gdscr = 0x13050,
.pd = {
.name = "sfe_0_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc sfe_1_gdsc = {
.gdscr = 0x13098,
.pd = {
.name = "sfe_1_gdsc",
},
.flags = POLL_CFG_GDSCR,
.parent = &titan_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc titan_top_gdsc = {
.gdscr = 0x131dc,
.pd = {
.name = "titan_top_gdsc",
},
.flags = POLL_CFG_GDSCR,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc *cam_cc_sm8450_gdscs[] = {
[BPS_GDSC] = &bps_gdsc,
[IPE_0_GDSC] = &ipe_0_gdsc,
[SBI_GDSC] = &sbi_gdsc,
[IFE_0_GDSC] = &ife_0_gdsc,
[IFE_1_GDSC] = &ife_1_gdsc,
[IFE_2_GDSC] = &ife_2_gdsc,
[SFE_0_GDSC] = &sfe_0_gdsc,
[SFE_1_GDSC] = &sfe_1_gdsc,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static const struct qcom_cc_desc cam_cc_sm8450_desc = {
.config = &cam_cc_sm8450_regmap_config,
.clks = cam_cc_sm8450_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks),
.resets = cam_cc_sm8450_resets,
.num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
.gdscs = cam_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
};
static const struct of_device_id cam_cc_sm8450_match_table[] = {
{ .compatible = "qcom,sm8450-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
static int cam_cc_sm8450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
}
static struct platform_driver cam_cc_sm8450_driver = {
.probe = cam_cc_sm8450_probe,
.driver = {
.name = "camcc-sm8450",
.of_match_table = cam_cc_sm8450_match_table,
},
};
module_platform_driver(cam_cc_sm8450_driver);
MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/camcc-sm8450.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2020-2021, Linaro Ltd.
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_AUD_REF_CLK,
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL1_OUT_MAIN,
P_GPLL2_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL5_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct pll_vco trion_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static const struct clk_div_table post_div_table_trion_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_trion_even,
.num_post_div = ARRAY_SIZE(post_div_table_trion_even),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_trion_ops,
},
};
static struct clk_alpha_pll gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x1a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_1[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_2[] = {
{ .fw_name = "bi_tcxo", },
{ .fw_name = "sleep_clk", },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_MAIN, 2 },
{ P_GPLL5_OUT_MAIN, 3 },
{ P_GPLL1_OUT_MAIN, 4 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_3[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
{ .name = "gpll2" },
{ .name = "gpll5" },
{ .hw = &gpll1.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo", },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parents_5[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_6[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_7[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
{ .name = "gppl9" },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_AUD_REF_CLK, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parents_8[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
{ .name = "aud_ref_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac_ptp_clk_src = {
.cmd_rcgr = 0x6038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_emac_ptp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
F(2500000, P_BI_TCXO, 1, 25, 192),
F(5000000, P_BI_TCXO, 1, 25, 96),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
.cmd_rcgr = 0x601c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_rgmii_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp4_clk_src = {
.cmd_rcgr = 0xbe004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp4_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp5_clk_src = {
.cmd_rcgr = 0xbf004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp5_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_npu_axi_clk_src = {
.cmd_rcgr = 0x4d014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_npu_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b02c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d02c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
.cmd_rcgr = 0x9d02c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
.cmd_rcgr = 0xa302c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
.cmd_rcgr = 0x6f014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qspi_1_core_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qspi_1_core_clk_src = {
.cmd_rcgr = 0x4a00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_1_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qspi_core_clk_src = {
.cmd_rcgr = 0x4b008,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
{ }
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x173a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x174d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x17608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17998,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x183a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x184d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x18608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
F(105495, P_BI_TCXO, 2, 1, 91),
{ }
};
static struct clk_rcg2 gcc_tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_2_axi_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = {
.cmd_rcgr = 0xa2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = {
.cmd_rcgr = 0xa2060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_2_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = {
.cmd_rcgr = 0xa2094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_phy_aux_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = {
.cmd_rcgr = 0xa2078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x75020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x75060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x75094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x75078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x77060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x77094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
.cmd_rcgr = 0xa601c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mp_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mp_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
.cmd_rcgr = 0xa6034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mp_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x1001c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x10034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
.cmd_rcgr = 0xa6068,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_mp_phy_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x10060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x90018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x750c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x750c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x750c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x750c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750c0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_aggre_ufs_card_axi_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x770c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x770c0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x770c0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770c0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_aggre_ufs_phy_axi_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
.halt_reg = 0xa6084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa6084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_mp_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_mp_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0xf07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x1007c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1007c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0xb030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0xb034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
.halt_reg = 0xa609c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa609c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_mp_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_mp_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0xf078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x10078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_master_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* For CPUSS functionality the AHB clock needs to be left enabled */
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0xb038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0xb03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_axi_clk = {
.halt_reg = 0x6010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_ptp_clk = {
.halt_reg = 0x6034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_emac_ptp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_rgmii_clk = {
.halt_reg = 0x6018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_rgmii_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_emac_rgmii_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_slv_ahb_clk = {
.halt_reg = 0x6014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x6014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_emac_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp4_clk = {
.halt_reg = 0xbe000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xbe000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp4_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp5_clk = {
.halt_reg = 0xbf000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xbf000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp5_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0_out_even.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_at_clk = {
.halt_reg = 0x4d010,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_npu_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0_out_even.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_trig_clk = {
.halt_reg = 0x4d00c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_trig_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_refgen_clk = {
.halt_reg = 0x6f02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_refgen_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_refgen_clk = {
.halt_reg = 0x6f030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_refgen_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2_phy_refgen_clk = {
.halt_reg = 0x6f034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie2_phy_refgen_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3_phy_refgen_clk = {
.halt_reg = 0x6f038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie3_phy_refgen_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_0_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_clk = {
.halt_reg = 0x8c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_1_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_clkref_clk = {
.halt_reg = 0x8c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_aux_clk = {
.halt_reg = 0x9d020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_2_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
.halt_reg = 0x9d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_clkref_clk = {
.halt_reg = 0x8c014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
.halt_reg = 0x9d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x9d024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_axi_clk = {
.halt_reg = 0x9d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
.halt_reg = 0x9d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_aux_clk = {
.halt_reg = 0xa3020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_3_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
.halt_reg = 0xa301c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa301c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_clkref_clk = {
.halt_reg = 0x8c018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
.halt_reg = 0xa3018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_pipe_clk = {
.halt_reg = 0xa3024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_slv_axi_clk = {
.halt_reg = 0xa3014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa3014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
.halt_reg = 0xa3010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_3_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcie_0_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pdm2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0xb018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0xb010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0xb014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_1_cnoc_periph_ahb_clk = {
.halt_reg = 0x4a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_1_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_1_core_clk = {
.halt_reg = 0x4a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_1_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qspi_1_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
.halt_reg = 0x4b000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_core_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qspi_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x17274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x173a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x174d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x17604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x17734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x17864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x17994,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x183a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x184d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x18604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52014,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc2_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc4_apps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x4819c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_tsif_ref_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_ahb_clk = {
.halt_reg = 0xa2014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xa2014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa2014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_axi_clk = {
.halt_reg = 0xa2010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xa2010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa2010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_2_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_ice_core_clk = {
.halt_reg = 0xa205c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xa205c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa205c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_2_ice_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_phy_aux_clk = {
.halt_reg = 0xa2090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xa2090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa2090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_2_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_rx_symbol_0_clk = {
.halt_reg = 0xa201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_rx_symbol_1_clk = {
.halt_reg = 0xa20ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa20ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_tx_symbol_0_clk = {
.halt_reg = 0xa2018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa2018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
.halt_reg = 0xa2058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xa2058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa2058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_2_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_2_unipro_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_axi_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_ice_core_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x75090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
.halt_reg = 0x75090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75090,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_phy_aux_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_reg = 0x7501c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_reg = 0x750ac,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x750ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75058,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_card_unipro_core_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_ice_core_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_phy_aux_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770ac,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x770ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77058,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_unipro_core_clk.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_master_clk = {
.halt_reg = 0xa6010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa6010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mp_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_mp_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
.halt_reg = 0xa6018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa6018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mp_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_sleep_clk = {
.halt_reg = 0xa6014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa6014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mp_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x10014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
.halt_reg = 0xa6050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa6050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_mp_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_mp_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
.halt_reg = 0xa6054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa6054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_mp_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_mp_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
.halt_reg = 0xa6058,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xa6058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_mp_phy_pipe_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
.halt_reg = 0xa605c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xa605c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_mp_phy_pipe_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0xf058,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_clkref_clk = {
.halt_reg = 0x8c028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x10050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x10054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x10058,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x10058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axic_clk = {
.halt_reg = 0xb02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axic_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc emac_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "emac_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_2_gdsc = {
.gdscr = 0x9d004,
.pd = {
.name = "pcie_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc ufs_card_2_gdsc = {
.gdscr = 0xa2004,
.pd = {
.name = "ufs_card_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc pcie_3_gdsc = {
.gdscr = 0xa3004,
.pd = {
.name = "pcie_3_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_mp_gdsc = {
.gdscr = 0xa6004,
.pd = {
.name = "usb30_mp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct clk_regmap *gcc_sc8180x_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
[GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
[GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
[GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
[GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr,
[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
[GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
[GCC_PCIE3_PHY_REFGEN_CLK] = &gcc_pcie3_phy_refgen_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
[GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr,
[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
[GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr,
[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QSPI_1_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_1_cnoc_periph_ahb_clk.clkr,
[GCC_QSPI_1_CORE_CLK] = &gcc_qspi_1_core_clk.clkr,
[GCC_QSPI_1_CORE_CLK_SRC] = &gcc_qspi_1_core_clk_src.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_CARD_2_AHB_CLK] = &gcc_ufs_card_2_ahb_clk.clkr,
[GCC_UFS_CARD_2_AXI_CLK] = &gcc_ufs_card_2_axi_clk.clkr,
[GCC_UFS_CARD_2_AXI_CLK_SRC] = &gcc_ufs_card_2_axi_clk_src.clkr,
[GCC_UFS_CARD_2_ICE_CORE_CLK] = &gcc_ufs_card_2_ice_core_clk.clkr,
[GCC_UFS_CARD_2_ICE_CORE_CLK_SRC] = &gcc_ufs_card_2_ice_core_clk_src.clkr,
[GCC_UFS_CARD_2_PHY_AUX_CLK] = &gcc_ufs_card_2_phy_aux_clk.clkr,
[GCC_UFS_CARD_2_PHY_AUX_CLK_SRC] = &gcc_ufs_card_2_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = &gcc_ufs_card_2_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = &gcc_ufs_card_2_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
[GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
[GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL7] = &gpll7.clkr,
};
static const struct qcom_reset_map gcc_sc8180x_resets[] = {
[GCC_EMAC_BCR] = { 0x6000 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_NPU_BCR] = { 0x4d000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_2_BCR] = { 0x9d000 },
[GCC_PCIE_2_PHY_BCR] = { 0xa701c },
[GCC_PCIE_3_BCR] = { 0xa3000 },
[GCC_PCIE_3_PHY_BCR] = { 0xa801c },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_QSPI_1_BCR] = { 0x4a000 },
[GCC_QSPI_BCR] = { 0x24008 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_5_BCR] = { 0x12010 },
[GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
[GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
[GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
[GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
[GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
[GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_UFS_CARD_2_BCR] = { 0xa2000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_MP_BCR] = { 0xa6000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
};
static struct gdsc *gcc_sc8180x_gdscs[] = {
[EMAC_GDSC] = &emac_gdsc,
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[PCIE_2_GDSC] = &pcie_2_gdsc,
[PCIE_3_GDSC] = &pcie_3_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_CARD_2_GDSC] = &ufs_card_2_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_MP_GDSC] = &usb30_mp_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
};
static const struct regmap_config gcc_sc8180x_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc0004,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sc8180x_desc = {
.config = &gcc_sc8180x_regmap_config,
.clks = gcc_sc8180x_clocks,
.num_clks = ARRAY_SIZE(gcc_sc8180x_clocks),
.resets = gcc_sc8180x_resets,
.num_resets = ARRAY_SIZE(gcc_sc8180x_resets),
.gdscs = gcc_sc8180x_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs),
};
static const struct of_device_id gcc_sc8180x_match_table[] = {
{ .compatible = "qcom,gcc-sc8180x" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);
static int gcc_sc8180x_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Enable the following always-on clocks:
* GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
* GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK,
* GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and
* GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap);
}
static struct platform_driver gcc_sc8180x_driver = {
.probe = gcc_sc8180x_probe,
.driver = {
.name = "gcc-sc8180x",
.of_match_table = gcc_sc8180x_match_table,
},
};
static int __init gcc_sc8180x_init(void)
{
return platform_driver_register(&gcc_sc8180x_driver);
}
core_initcall(gcc_sc8180x_init);
static void __exit gcc_sc8180x_exit(void)
{
platform_driver_unregister(&gcc_sc8180x_driver);
}
module_exit(gcc_sc8180x_exit);
MODULE_DESCRIPTION("QTI GCC SC8180x driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sc8180x.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm Global Clock Controller driver for MSM8956/76
*
* Copyright (c) 2016-2021, AngeloGioacchino Del Regno
* <[email protected]>
*
* Driver cleanup and modernization
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
* Marijn Suijten <[email protected]>
*
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-msm8976.h>
#include "clk-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_GPLL0_OUT_MAIN,
P_GPLL0_AUX,
P_GPLL0_OUT,
P_GPLL0_OUT_M,
P_GPLL0_OUT_MDP,
P_GPLL2_AUX,
P_GPLL2_OUT,
P_GPLL4_OUT_MAIN,
P_GPLL4_AUX,
P_GPLL4_OUT,
P_GPLL4_GFX3D,
P_GPLL6_OUT_MAIN,
P_GPLL6_AUX,
P_GPLL6_OUT,
P_GPLL6_GFX3D,
P_DSI0PLL,
P_DSI1PLL,
P_DSI0PLL_BYTE,
P_DSI1PLL_BYTE,
P_XO_A,
P_XO,
};
static struct clk_pll gpll0 = {
.l_reg = 0x21004,
.m_reg = 0x21008,
.n_reg = 0x2100c,
.config_reg = 0x21014,
.mode_reg = 0x21000,
.status_reg = 0x2101c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_hws = (const struct clk_hw *[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
/* This clock is required for other ones to function. */
.flags = CLK_IS_CRITICAL,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll2 = {
.l_reg = 0x4a004,
.m_reg = 0x4a008,
.n_reg = 0x4a00c,
.config_reg = 0x4a014,
.mode_reg = 0x4a000,
.status_reg = 0x4a01c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll2_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_vote",
.parent_hws = (const struct clk_hw *[]) {
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct pll_freq_tbl gpll3_freq_tbl[] = {
{ 1100000000, 57, 7, 24, 0 },
{ }
};
static struct clk_pll gpll3 = {
.l_reg = 0x22004,
.m_reg = 0x22008,
.n_reg = 0x2200c,
.config_reg = 0x22010,
.mode_reg = 0x22000,
.status_reg = 0x22024,
.status_bit = 17,
.freq_tbl = gpll3_freq_tbl,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll3_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll3_vote",
.parent_hws = (const struct clk_hw *[]) {
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
/* GPLL3 at 1100MHz, main output enabled. */
static const struct pll_config gpll3_config = {
.l = 57,
.m = 7,
.n = 24,
.vco_val = 0x0,
.vco_mask = 0x3 << 20,
.pre_div_val = 0x0,
.pre_div_mask = 0x7 << 12,
.post_div_val = 0x0,
.post_div_mask = 0x3 << 8,
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
};
static struct clk_pll gpll4 = {
.l_reg = 0x24004,
.m_reg = 0x24008,
.n_reg = 0x2400c,
.config_reg = 0x24018,
.mode_reg = 0x24000,
.status_reg = 0x24024,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll4_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_vote",
.parent_hws = (const struct clk_hw *[]) {
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll6 = {
.mode_reg = 0x37000,
.l_reg = 0x37004,
.m_reg = 0x37008,
.n_reg = 0x3700c,
.config_reg = 0x37014,
.status_reg = 0x3701c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll6_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_vote",
.parent_hws = (const struct clk_hw *[]) {
&gpll6.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT, 2 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll4_vote.hw },
};
static const struct parent_map gcc_parent_map_v1_1[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT, 4 },
};
static const struct clk_parent_data gcc_parent_data_v1_1[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_AUX, 3 },
{ P_GPLL4_OUT, 2 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
{ .hw = &gpll4_vote.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_AUX, 3 },
{ P_GPLL6_AUX, 2 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
{ .hw = &gpll6_vote.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct parent_map gcc_parent_map_4_fs[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT, 2 },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_GPLL4_OUT, 2 },
{ P_GPLL6_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "xo" },
{ .hw = &gpll4_vote.hw },
{ .hw = &gpll6_vote.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll4_vote.hw },
};
static const struct parent_map gcc_parent_map_7_mdp[] = {
{ P_XO, 0 },
{ P_GPLL6_OUT, 3 },
{ P_GPLL0_OUT_MDP, 6 },
};
static const struct clk_parent_data gcc_parent_data_7_mdp[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6_vote.hw },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT, 3 },
};
static const struct clk_hw * gcc_parent_hws_7[] = {
&gpll0_vote.hw,
&gpll6_vote.hw,
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_4_8[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_parent_map_8_a[] = {
{ P_XO_A, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_8_a[] = {
{ .fw_name = "xo_a" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_parent_map_8_gp[] = {
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_hw *gcc_parent_hws_8_gp[] = {
&gpll0_vote.hw,
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_XO, 0 },
{ P_GPLL6_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6_vote.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "xo" },
};
static const struct parent_map gcc_parent_map_sdcc_ice[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_M, 3 },
};
static const struct parent_map gcc_parent_map_cci[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
};
static const struct parent_map gcc_parent_map_cpp[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_AUX, 3 },
};
static const struct parent_map gcc_parent_map_mdss_pix0[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
};
static const struct clk_parent_data gcc_parent_data_mdss_pix0[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pll" },
};
static const struct parent_map gcc_parent_map_mdss_pix1[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 3 },
{ P_DSI1PLL, 1 },
};
static const struct clk_parent_data gcc_parent_data_mdss_pix1[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pll" },
{ .fw_name = "dsi1pll" },
};
static const struct parent_map gcc_parent_map_mdss_byte0[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_parent_data_mdss_byte0[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte" },
};
static const struct parent_map gcc_parent_map_mdss_byte1[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 3 },
{ P_DSI1PLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_parent_data_mdss_byte1[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte" },
};
static const struct parent_map gcc_parent_map_gfx3d[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_GFX3D, 5 },
{ P_GPLL6_GFX3D, 3 },
};
static const struct clk_parent_data gcc_parent_data_gfx3d[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll4_vote.hw },
{ .hw = &gpll6_vote.hw },
};
static const struct freq_tbl ftbl_aps_0_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(300000000, P_GPLL4_OUT, 4, 0, 0),
F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 aps_0_clk_src = {
.cmd_rcgr = 0x78008,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_aps_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "aps_0_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_aps_1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(300000000, P_GPLL4_OUT, 4, 0, 0),
F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 aps_1_clk_src = {
.cmd_rcgr = 0x79008,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_aps_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "aps_1_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO_A, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(88890000, P_GPLL0_OUT_MAIN, 9, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.parent_map = gcc_parent_map_8_a,
.freq_tbl = ftbl_apss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_parent_data_8_a,
.num_parents = ARRAY_SIZE(gcc_parent_data_8_a),
.ops = &clk_rcg2_ops,
/*
* This clock allows the CPUs to communicate with
* the rest of the SoC. Without it, the brain will
* operate without the rest of the body.
*/
.flags = CLK_IS_CRITICAL,
},
};
static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x200c,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x3014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x4024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x5024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x2044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x3034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0xc00c,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0xc024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0xd000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0xd014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0xf000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0xf024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x18000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x18024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0xc044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0xd034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0_AUX, 1, 3, 64),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_cci,
.freq_tbl = ftbl_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(240000000, P_GPLL4_AUX, 5, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(480000000, P_GPLL4_AUX, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
.parent_map = gcc_parent_map_cpp,
.freq_tbl = ftbl_cpp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi1_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_csi1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi2_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3c020,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_csi2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8_gp,
.freq_tbl = ftbl_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_hws = gcc_parent_hws_8_gp,
.num_parents = ARRAY_SIZE(gcc_parent_hws_8_gp),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camss_gp1_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8_gp,
.freq_tbl = ftbl_camss_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_hws = gcc_parent_hws_8_gp,
.num_parents = ARRAY_SIZE(gcc_parent_hws_8_gp),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(133330000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x57000,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_jpeg0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mclk_clk_src[] = {
F(8000000, P_GPLL0_OUT_MAIN, 1, 1, 100),
F(24000000, P_GPLL6_OUT, 1, 1, 45),
F(66670000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_hws = gcc_parent_hws_7,
.num_parents = ARRAY_SIZE(gcc_parent_hws_7),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_hws = gcc_parent_hws_7,
.num_parents = ARRAY_SIZE(gcc_parent_hws_7),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x5c000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_hws = gcc_parent_hws_7,
.num_parents = ARRAY_SIZE(gcc_parent_hws_7),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi1phytimer_clk_src[] = {
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x4f000,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_csi1phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 camss_top_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_camss_top_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe0_clk_src[] = {
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL4_OUT, 4, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(466000000, P_GPLL2_AUX, 2, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe1_clk_src[] = {
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL4_OUT, 4, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(466000000, P_GPLL2_AUX, 2, 0, 0),
{ }
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x58054,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_vfe1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_crypto_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x8004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8_gp,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_vote.hw,
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp2_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x9004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8_gp,
.freq_tbl = ftbl_gp2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_vote.hw,
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp3_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0xa004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8_gp,
.freq_tbl = ftbl_gp3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_vote.hw,
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_mdss_byte0,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = gcc_parent_data_mdss_byte0,
.num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x4d0b0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_mdss_byte1,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = gcc_parent_data_mdss_byte1,
.num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte1),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_parent_map_mdss_byte0,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = gcc_parent_data_mdss_byte0,
.num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x4d0a8,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_parent_map_mdss_byte1,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = gcc_parent_data_mdss_byte1,
.num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(50000000, P_GPLL0_OUT_MDP, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MDP, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MDP, 8, 0, 0),
F(145454545, P_GPLL0_OUT_MDP, 5.5, 0, 0),
F(160000000, P_GPLL0_OUT_MDP, 5, 0, 0),
F(177777778, P_GPLL0_OUT_MDP, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MDP, 4, 0, 0),
F(270000000, P_GPLL6_OUT, 4, 0, 0),
F(320000000, P_GPLL0_OUT_MDP, 2.5, 0, 0),
F(360000000, P_GPLL6_OUT, 3, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.parent_map = gcc_parent_map_7_mdp,
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = gcc_parent_data_7_mdp,
.num_parents = ARRAY_SIZE(gcc_parent_data_7_mdp),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_mdss_pix0,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = gcc_parent_data_mdss_pix0,
.num_parents = ARRAY_SIZE(gcc_parent_data_mdss_pix0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x4d0b8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_mdss_pix1,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = gcc_parent_data_mdss_pix1,
.num_parents = ARRAY_SIZE(gcc_parent_data_mdss_pix1),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_vsync_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_vsync_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(240000000, P_GPLL6_GFX3D, 4.5, 0, 0),
F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL4_GFX3D, 4, 0, 0),
F(360000000, P_GPLL6_GFX3D, 3, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(432000000, P_GPLL6_GFX3D, 2.5, 0, 0),
F(480000000, P_GPLL4_GFX3D, 2.5, 0, 0),
F(540000000, P_GPLL6_GFX3D, 2, 0, 0),
F(600000000, P_GPLL4_GFX3D, 2, 0, 0),
{ }
};
static const struct clk_init_data gfx3d_clk_params = {
.name = "gfx3d_clk_src",
.parent_data = gcc_parent_data_gfx3d,
.num_parents = ARRAY_SIZE(gcc_parent_data_gfx3d),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.parent_map = gcc_parent_map_gfx3d,
.freq_tbl = ftbl_gfx3d_clk_src,
.clkr.hw.init = &gfx3d_clk_params,
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_gfx_clk_src = {
.cmd_rcgr = 0x3a00c,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_rbcpr_gfx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_gfx_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(342850000, P_GPLL4_OUT, 3.5, 0, 0),
F(400000000, P_GPLL4_OUT, 3, 0, 0),
{ }
};
static const struct freq_tbl ftbl_sdcc1_8976_v1_1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(186400000, P_GPLL2_OUT, 5, 0, 0),
F(372800000, P_GPLL2_OUT, 2.5, 0, 0),
{ }
};
static const struct clk_init_data sdcc1_apps_clk_src_8976v1_1_init = {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_v1_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_v1_1),
.ops = &clk_rcg2_floor_ops,
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(100000000, P_GPLL0_OUT_M, 8, 0, 0),
F(200000000, P_GPLL0_OUT_M, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_sdcc_ice,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc3_apps_clk_src = {
.cmd_rcgr = 0x39004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_fs_ic_clk_src[] = {
F(60000000, P_GPLL6_OUT_MAIN, 6, 1, 3),
{ }
};
static struct clk_rcg2 usb_fs_ic_clk_src = {
.cmd_rcgr = 0x3f034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_usb_fs_ic_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_ic_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_fs_system_clk_src[] = {
F(64000000, P_GPLL0_OUT, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_fs_system_clk_src = {
.cmd_rcgr = 0x3f010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4_fs,
.freq_tbl = ftbl_usb_fs_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_system_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
F(57140000, P_GPLL0_OUT_MAIN, 14, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(177780000, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_usb_hs_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_parent_data_4_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
F(72727200, P_GPLL0_OUT_MAIN, 11, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(228570000, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(310667000, P_GPLL2_AUX, 3, 0, 0),
F(360000000, P_GPLL6_AUX, 3, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(466000000, P_GPLL2_AUX, 2, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4c000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_vcodec0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aps_0_clk = {
.halt_reg = 0x78004,
.clkr = {
.enable_reg = 0x78004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_aps_0_clk",
.parent_hws = (const struct clk_hw *[]) {
&aps_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aps_1_clk = {
.halt_reg = 0x79004,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_aps_1_clk",
.parent_hws = (const struct clk_hw *[]) {
&aps_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x3010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x4020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x5020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x302c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0xc008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0xc004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0xd010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xd010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0xd00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xd00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0xf020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x18020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x18020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x1801c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1801c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0xc03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0xd02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xd02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x5101c,
.clkr = {
.enable_reg = 0x5101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x51018,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cci_clk",
.parent_hws = (const struct clk_hw *[]) {
&cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x58040,
.clkr = {
.enable_reg = 0x58040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_axi_clk = {
.halt_reg = 0x58064,
.clkr = {
.enable_reg = 0x58064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x5803c,
.clkr = {
.enable_reg = 0x5803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_clk",
.parent_hws = (const struct clk_hw *[]) {
&cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.clkr = {
.enable_reg = 0x4e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.clkr = {
.enable_reg = 0x4e03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.clkr = {
.enable_reg = 0x4e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phy_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.clkr = {
.enable_reg = 0x4e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.clkr = {
.enable_reg = 0x4e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.clkr = {
.enable_reg = 0x4f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.clkr = {
.enable_reg = 0x4f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.clkr = {
.enable_reg = 0x4f048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phy_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.clkr = {
.enable_reg = 0x4f058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.clkr = {
.enable_reg = 0x4f050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2_ahb_clk = {
.halt_reg = 0x3c040,
.clkr = {
.enable_reg = 0x3c040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2_clk = {
.halt_reg = 0x3c03c,
.clkr = {
.enable_reg = 0x3c03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2phy_clk = {
.halt_reg = 0x3c048,
.clkr = {
.enable_reg = 0x3c048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2phy_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2pix_clk = {
.halt_reg = 0x3c058,
.clkr = {
.enable_reg = 0x3c058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2pix_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2rdi_clk = {
.halt_reg = 0x3c050,
.clkr = {
.enable_reg = 0x3c050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw *[]) {
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe1_clk = {
.halt_reg = 0x58074,
.clkr = {
.enable_reg = 0x58074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw *[]) {
&vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x54018,
.clkr = {
.enable_reg = 0x54018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x55018,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x50004,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg0_clk = {
.halt_reg = 0x57020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg0_clk",
.parent_hws = (const struct clk_hw *[]) {
&jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.halt_reg = 0x57024,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_axi_clk = {
.halt_reg = 0x57028,
.clkr = {
.enable_reg = 0x57028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x52018,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw *[]) {
&mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x53018,
.clkr = {
.enable_reg = 0x53018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw *[]) {
&mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x5c018,
.clkr = {
.enable_reg = 0x5c018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw *[]) {
&mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_micro_ahb_clk = {
.halt_reg = 0x5600c,
.clkr = {
.enable_reg = 0x5600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.clkr = {
.enable_reg = 0x4e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x4f01c,
.clkr = {
.enable_reg = 0x4f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw *[]) {
&csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x56004,
.clkr = {
.enable_reg = 0x56004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x5a014,
.clkr = {
.enable_reg = 0x5a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x58038,
.clkr = {
.enable_reg = 0x58038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw *[]) {
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_ahb_clk = {
.halt_reg = 0x58044,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_axi_clk = {
.halt_reg = 0x58048,
.clkr = {
.enable_reg = 0x58048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe1_ahb_clk = {
.halt_reg = 0x58060,
.clkr = {
.enable_reg = 0x58060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw *[]) {
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe1_axi_clk = {
.halt_reg = 0x58068,
.clkr = {
.enable_reg = 0x58068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe1_clk = {
.halt_reg = 0x5805c,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_clk",
.parent_hws = (const struct clk_hw *[]) {
&vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_clk = {
.halt_reg = 0x77004,
.clkr = {
.enable_reg = 0x77004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_dcc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gmem_clk = {
.halt_reg = 0x59024,
.clkr = {
.enable_reg = 0x59024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_gmem_clk",
.parent_hws = (const struct clk_hw *[]) {
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x8000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x9000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0xa000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]) {
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw *[]) {
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_byte1_clk = {
.halt_reg = 0x4d0a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw *[]) {
&byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw *[]) {
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_esc1_clk = {
.halt_reg = 0x4d09c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d09c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw *[]) {
&esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4d088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw *[]) {
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw *[]) {
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_pclk1_clk = {
.halt_reg = 0x4d0a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw *[]) {
&pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw *[]) {
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x59048,
.clkr = {
.enable_reg = 0x59048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_aon_clk = {
.halt_reg = 0x59044,
.clkr = {
.enable_reg = 0x59044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_aon_clk",
.parent_hws = (const struct clk_hw *[]) {
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw *[]) {
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_timer_clk = {
.halt_reg = 0x59040,
.clkr = {
.enable_reg = 0x59040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_timer_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]) {
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rbcpr_gfx_ahb_clk = {
.halt_reg = 0x3a008,
.clkr = {
.enable_reg = 0x3a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_rbcpr_gfx_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rbcpr_gfx_clk = {
.halt_reg = 0x3a004,
.clkr = {
.enable_reg = 0x3a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_rbcpr_gfx_clk",
.parent_hws = (const struct clk_hw *[]) {
&rbcpr_gfx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x5d014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_ahb_clk = {
.halt_reg = 0x3901c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3901c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc3_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_apps_clk = {
.halt_reg = 0x39018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc3_apps_clk",
.parent_hws = (const struct clk_hw *[]) {
&sdcc3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb2a_phy_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
.halt_reg = 0x41030,
.clkr = {
.enable_reg = 0x41030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_hs_phy_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_fs_ahb_clk = {
.halt_reg = 0x3f008,
.clkr = {
.enable_reg = 0x3f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_fs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_fs_ic_clk = {
.halt_reg = 0x3f030,
.clkr = {
.enable_reg = 0x3f030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_fs_ic_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb_fs_ic_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_fs_system_clk = {
.halt_reg = 0x3f004,
.clkr = {
.enable_reg = 0x3f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_fs_system_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb_fs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x41008,
.clkr = {
.enable_reg = 0x41008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_hs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw *[]) {
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_ahb_clk = {
.halt_reg = 0x4c020,
.clkr = {
.enable_reg = 0x4c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_axi_clk = {
.halt_reg = 0x4c024,
.clkr = {
.enable_reg = 0x4c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.halt_reg = 0x4c02c,
.clkr = {
.enable_reg = 0x4c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_core0_vcodec0_clk",
.parent_hws = (const struct clk_hw *[]) {
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
.halt_reg = 0x4c034,
.clkr = {
.enable_reg = 0x4c034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_core1_vcodec0_clk",
.parent_hws = (const struct clk_hw *[]) {
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_vcodec0_clk = {
.halt_reg = 0x4c01c,
.clkr = {
.enable_reg = 0x4c01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw *[]) {
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Vote clocks */
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x46020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0xb008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]) {
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpp_tbu_clk = {
.halt_reg = 0x12040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpp_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_1_tbu_clk = {
.halt_reg = 0x12098,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_1_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tbu_clk = {
.halt_reg = 0x12010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tcu_clk = {
.halt_reg = 0x12020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_jpeg_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdp_rt_tbu_clk = {
.halt_reg = 0x1204c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_rt_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_1_tbu_clk = {
.halt_reg = 0x1209c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_1_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_tbu_clk = {
.halt_reg = 0x12014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vfe1_tbu_clk = {
.halt_reg = 0x12090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_vfe1_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vfe_tbu_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_vfe_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
.cxc_count = 2,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x4c028,
.cxcs = (unsigned int []){ 0x4c02c },
.cxc_count = 1,
.pd = {
.name = "venus_core0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core1_gdsc = {
.gdscr = 0x4c030,
.pd = {
.name = "venus_core1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
.cxc_count = 2,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x5701c,
.cxcs = (unsigned int []){ 0x57020, 0x57028 },
.cxc_count = 2,
.pd = {
.name = "jpeg_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe0_gdsc = {
.gdscr = 0x58034,
.cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
.cxc_count = 4,
.pd = {
.name = "vfe0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe1_gdsc = {
.gdscr = 0x5806c,
.cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
.cxc_count = 4,
.pd = {
.name = "vfe1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc cpp_gdsc = {
.gdscr = 0x58078,
.cxcs = (unsigned int []){ 0x5803c, 0x58064 },
.cxc_count = 2,
.pd = {
.name = "cpp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_cx_gdsc = {
.gdscr = 0x5904c,
.cxcs = (unsigned int []){ 0x59020 },
.cxc_count = 1,
.pd = {
.name = "oxili_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc oxili_gx_gdsc = {
.gdscr = 0x5901c,
.clamp_io_ctrl = 0x5b00c,
.cxcs = (unsigned int []){ 0x59000, 0x59024 },
.cxc_count = 2,
.pd = {
.name = "oxili_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.supply = "vdd_gfx",
.flags = CLAMP_IO,
};
static struct clk_regmap *gcc_msm8976_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL2] = &gpll2.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL0_CLK_SRC] = &gpll0_vote,
[GPLL2_CLK_SRC] = &gpll2_vote,
[GPLL3_CLK_SRC] = &gpll3_vote,
[GPLL4_CLK_SRC] = &gpll4_vote,
[GPLL6_CLK_SRC] = &gpll6_vote,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_RBCPR_GFX_AHB_CLK] = &gcc_rbcpr_gfx_ahb_clk.clkr,
[GCC_RBCPR_GFX_CLK] = &gcc_rbcpr_gfx_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
[GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
[GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
[GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
[GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
[GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_VENUS_1_TBU_CLK] = &gcc_venus_1_tbu_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
[GCC_APS_0_CLK] = &gcc_aps_0_clk.clkr,
[GCC_APS_1_CLK] = &gcc_aps_1_clk.clkr,
[APS_0_CLK_SRC] = &aps_0_clk_src.clkr,
[APS_1_CLK_SRC] = &aps_1_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[RBCPR_GFX_CLK_SRC] = &rbcpr_gfx_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
[USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[GCC_MDSS_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[GCC_MDSS_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
[GCC_MDSS_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[GCC_MDSS_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
[GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GCC_GFX3D_OXILI_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_GFX3D_BIMC_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_GFX3D_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_GFX3D_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
[GCC_GFX3D_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
[GCC_GFX3D_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
[GCC_GFX3D_TBU0_CLK] = &gcc_gfx_tbu_clk.clkr,
[GCC_GFX3D_TBU1_CLK] = &gcc_gfx_1_tbu_clk.clkr,
[GCC_GFX3D_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
[GCC_GFX3D_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8976_resets[] = {
[RST_CAMSS_MICRO_BCR] = { 0x56008 },
[RST_USB_HS_BCR] = { 0x41000 },
[RST_QUSB2_PHY_BCR] = { 0x4103c },
[RST_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
[RST_USB_HS_PHY_CFG_AHB_BCR] = { 0x41038 },
[RST_USB_FS_BCR] = { 0x3f000 },
[RST_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
[RST_CAMSS_CSI_VFE1_BCR] = { 0x58070 },
[RST_CAMSS_VFE1_BCR] = { 0x5807c },
[RST_CAMSS_CPP_BCR] = { 0x58080 },
[RST_MSS_BCR] = { 0x71000 },
};
static struct gdsc *gcc_msm8976_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[VFE0_GDSC] = &vfe0_gdsc,
[VFE1_GDSC] = &vfe1_gdsc,
[CPP_GDSC] = &cpp_gdsc,
[OXILI_GX_GDSC] = &oxili_gx_gdsc,
[OXILI_CX_GDSC] = &oxili_cx_gdsc,
};
static const struct regmap_config gcc_msm8976_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x7fffc,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8976_desc = {
.config = &gcc_msm8976_regmap_config,
.clks = gcc_msm8976_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8976_clocks),
.resets = gcc_msm8976_resets,
.num_resets = ARRAY_SIZE(gcc_msm8976_resets),
.gdscs = gcc_msm8976_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8976_gdscs),
};
static const struct of_device_id gcc_msm8976_match_table[] = {
{ .compatible = "qcom,gcc-msm8976" }, /* Also valid for 8x56 */
{ .compatible = "qcom,gcc-msm8976-v1.1" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8976_match_table);
static int gcc_msm8976_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8976-v1.1")) {
sdcc1_apps_clk_src.parent_map = gcc_parent_map_v1_1;
sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_8976_v1_1_apps_clk_src;
sdcc1_apps_clk_src.clkr.hw.init = &sdcc1_apps_clk_src_8976v1_1_init;
}
regmap = qcom_cc_map(pdev, &gcc_msm8976_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Set Sleep and Wakeup cycles to 0 for GMEM clock */
ret = regmap_update_bits(regmap, gcc_oxili_gmem_clk.clkr.enable_reg, 0xff0, 0);
if (ret)
return ret;
clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
/* Enable AUX2 clock for APSS */
ret = regmap_update_bits(regmap, 0x60000, BIT(2), BIT(2));
if (ret)
return ret;
/* Set Sleep cycles to 0 for OXILI clock */
ret = regmap_update_bits(regmap, gcc_oxili_gfx3d_clk.clkr.enable_reg, 0xf0, 0);
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_msm8976_desc, regmap);
}
static struct platform_driver gcc_msm8976_driver = {
.probe = gcc_msm8976_probe,
.driver = {
.name = "qcom,gcc-msm8976",
.of_match_table = gcc_msm8976_match_table,
},
};
static int __init gcc_msm8976_init(void)
{
return platform_driver_register(&gcc_msm8976_driver);
}
core_initcall(gcc_msm8976_init);
static void __exit gcc_msm8976_exit(void)
{
platform_driver_unregister(&gcc_msm8976_driver);
}
module_exit(gcc_msm8976_exit);
MODULE_AUTHOR("AngeloGioacchino Del Regno <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-msm8976.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, 2022, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_EVEN,
P_DISP_CC_PLL0_OUT_MAIN,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
};
static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_disp_cc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_phy_pll_link_clk" },
{ .fw_name = "dp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_MAIN, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
{ .hw = &disp_cc_pll0_out_even.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x22bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x2110,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.cmd_rcgr = 0x21dc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.cmd_rcgr = 0x2194,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x2178,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.cmd_rcgr = 0x21ac,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x2148,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x20c8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x2098,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x20e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x20f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x2080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x2128,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
.reg = 0x2190,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.halt_reg = 0x2054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
.halt_reg = 0x2048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.halt_reg = 0x204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x204c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x2038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x201c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x2014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x4008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc *disp_cc_sc7180_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static struct clk_regmap *disp_cc_sc7180_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
&disp_cc_mdss_dp_link_div_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
};
static const struct regmap_config disp_cc_sc7180_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sc7180_desc = {
.config = &disp_cc_sc7180_regmap_config,
.clks = disp_cc_sc7180_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
.gdscs = disp_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
};
static const struct of_device_id disp_cc_sc7180_match_table[] = {
{ .compatible = "qcom,sc7180-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
static int disp_cc_sc7180_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config disp_cc_pll_config = {};
regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* 1380MHz configuration */
disp_cc_pll_config.l = 0x47;
disp_cc_pll_config.alpha = 0xe000;
disp_cc_pll_config.user_ctl_val = 0x00000001;
disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
}
static struct platform_driver disp_cc_sc7180_driver = {
.probe = disp_cc_sc7180_probe,
.driver = {
.name = "sc7180-dispcc",
.of_match_table = disp_cc_sc7180_match_table,
},
};
static int __init disp_cc_sc7180_init(void)
{
return platform_driver_register(&disp_cc_sc7180_driver);
}
subsys_initcall(disp_cc_sc7180_init);
static void __exit disp_cc_sc7180_exit(void)
{
platform_driver_unregister(&disp_cc_sc7180_driver);
}
module_exit(disp_cc_sc7180_exit);
MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/dispcc-sc7180.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
DT_GCC_GPU_SNOC_DVM_GFX_CLK,
};
enum {
P_BI_TCXO,
P_GCC_GPU_GPLL0_CLK_SRC,
P_GCC_GPU_GPLL0_DIV_CLK_SRC,
P_GPU_CC_PLL0_OUT_EVEN,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL0_OUT_ODD,
P_GPU_CC_PLL1_OUT_EVEN,
P_GPU_CC_PLL1_OUT_MAIN,
P_GPU_CC_PLL1_OUT_ODD,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 532MHz Configuration */
static const struct alpha_pll_config gpucc_pll0_config = {
.l = 0x1b,
.alpha = 0xb555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpucc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpucc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = P_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
/* 514MHz Configuration */
static const struct alpha_pll_config gpucc_pll1_config = {
.l = 0x1a,
.alpha = 0xc555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpucc_pll1 = {
.offset = 0x100,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpucc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = P_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map gpucc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpucc_parent_data_0[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpucc_pll0.clkr.hw },
{ .hw = &gpucc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpucc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
};
static const struct clk_parent_data gpucc_parent_data_1[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpucc_pll0.clkr.hw },
{ .hw = &gpucc_pll0.clkr.hw },
{ .hw = &gpucc_pll1.clkr.hw },
{ .hw = &gpucc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
};
static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = {
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpucc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_0,
.freq_tbl = ftbl_gpucc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpucc_gmu_clk_src",
.parent_data = gpucc_parent_data_0,
.num_parents = ARRAY_SIZE(gpucc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = {
F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_1,
.freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_gfx3d_clk_src",
.parent_data = gpucc_parent_data_1,
.num_parents = ARRAY_SIZE(gpucc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpucc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_gfx3d_slv_clk = {
.halt_reg = 0x10a8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_gfx3d_slv_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_snoc_dvm_clk",
.parent_data = &(const struct clk_parent_data){
.index = DT_GCC_GPU_SNOC_DVM_GFX_CLK,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_gx_cxo_clk = {
.halt_reg = 0x1060,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_cxo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.clk_dis_wait_val = 8,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR },
.reset_count = 3,
.pd = {
.name = "gpu_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | SW_RESET | AON_RESET,
};
static struct clk_regmap *gpucc_sm6375_clocks[] = {
[GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr,
[GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr,
[GPU_CC_PLL0] = &gpucc_pll0.clkr,
[GPU_CC_PLL1] = &gpucc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr,
};
static const struct qcom_reset_map gpucc_sm6375_resets[] = {
[GPU_GX_BCR] = { 0x1008 },
[GPU_ACD_BCR] = { 0x1160 },
[GPU_GX_ACD_MISC_BCR] = { 0x8004 },
};
static struct gdsc *gpucc_sm6375_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpucc_sm6375_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpucc_sm6375_desc = {
.config = &gpucc_sm6375_regmap_config,
.clks = gpucc_sm6375_clocks,
.num_clks = ARRAY_SIZE(gpucc_sm6375_clocks),
.resets = gpucc_sm6375_resets,
.num_resets = ARRAY_SIZE(gpucc_sm6375_resets),
.gdscs = gpucc_sm6375_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs),
};
static const struct of_device_id gpucc_sm6375_match_table[] = {
{ .compatible = "qcom,sm6375-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table);
static int gpucc_sm6375_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static struct platform_driver gpucc_sm6375_driver = {
.probe = gpucc_sm6375_probe,
.driver = {
.name = "gpucc-sm6375",
.of_match_table = gpucc_sm6375_match_table,
},
};
module_platform_driver(gpucc_sm6375_driver);
MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sm6375.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include "common.h"
#include "reset.h"
static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = {
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
[LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
};
static struct regmap_config lpass_audiocc_sc8280xp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.name = "lpass-audio-csr",
.max_register = 0x1000,
};
static const struct qcom_cc_desc lpass_audiocc_sc8280xp_reset_desc = {
.config = &lpass_audiocc_sc8280xp_regmap_config,
.resets = lpass_audiocc_sc8280xp_resets,
.num_resets = ARRAY_SIZE(lpass_audiocc_sc8280xp_resets),
};
static const struct qcom_reset_map lpasscc_sc8280xp_resets[] = {
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 },
};
static struct regmap_config lpasscc_sc8280xp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.name = "lpass-tcsr",
.max_register = 0x12000,
};
static const struct qcom_cc_desc lpasscc_sc8280xp_reset_desc = {
.config = &lpasscc_sc8280xp_regmap_config,
.resets = lpasscc_sc8280xp_resets,
.num_resets = ARRAY_SIZE(lpasscc_sc8280xp_resets),
};
static const struct of_device_id lpasscc_sc8280xp_match_table[] = {
{
.compatible = "qcom,sc8280xp-lpassaudiocc",
.data = &lpass_audiocc_sc8280xp_reset_desc,
}, {
.compatible = "qcom,sc8280xp-lpasscc",
.data = &lpasscc_sc8280xp_reset_desc,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table);
static int lpasscc_sc8280xp_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev);
return qcom_cc_probe_by_index(pdev, 0, desc);
}
static struct platform_driver lpasscc_sc8280xp_driver = {
.probe = lpasscc_sc8280xp_probe,
.driver = {
.name = "lpasscc-sc8280xp",
.of_match_table = lpasscc_sc8280xp_match_table,
},
};
module_platform_driver(lpasscc_sc8280xp_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]>");
MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/lpasscc-sc8280xp.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
#include "clk-regmap.h"
#include "clk-hfpll.h"
#define PLL_OUTCTRL BIT(0)
#define PLL_BYPASSNL BIT(1)
#define PLL_RESET_N BIT(2)
/* Initialize a HFPLL at a given rate and enable it. */
static void __clk_hfpll_init_once(struct clk_hw *hw)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
if (likely(h->init_done))
return;
/* Configure PLL parameters for integer mode. */
if (hd->config_val)
regmap_write(regmap, hd->config_reg, hd->config_val);
regmap_write(regmap, hd->m_reg, 0);
regmap_write(regmap, hd->n_reg, 1);
if (hd->user_reg) {
u32 regval = hd->user_val;
unsigned long rate;
rate = clk_hw_get_rate(hw);
/* Pick the right VCO. */
if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
regval |= hd->user_vco_mask;
regmap_write(regmap, hd->user_reg, regval);
}
if (hd->droop_reg)
regmap_write(regmap, hd->droop_reg, hd->droop_val);
h->init_done = true;
}
static void __clk_hfpll_enable(struct clk_hw *hw)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
u32 val;
__clk_hfpll_init_once(hw);
/* Disable PLL bypass mode. */
regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe.
*/
udelay(10);
/* De-assert active-low PLL reset. */
regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
/* Wait for PLL to lock. */
if (hd->status_reg)
/*
* Busy wait. Should never timeout, we add a timeout to
* prevent any sort of stall.
*/
regmap_read_poll_timeout(regmap, hd->status_reg, val,
!(val & BIT(hd->lock_bit)), 0,
100 * USEC_PER_MSEC);
else
udelay(60);
/* Enable PLL output. */
regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
}
/* Enable an already-configured HFPLL. */
static int clk_hfpll_enable(struct clk_hw *hw)
{
unsigned long flags;
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
u32 mode;
spin_lock_irqsave(&h->lock, flags);
regmap_read(regmap, hd->mode_reg, &mode);
if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
__clk_hfpll_enable(hw);
spin_unlock_irqrestore(&h->lock, flags);
return 0;
}
static void __clk_hfpll_disable(struct clk_hfpll *h)
{
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
/*
* Disable the PLL output, disable test mode, enable the bypass mode,
* and assert the reset.
*/
regmap_update_bits(regmap, hd->mode_reg,
PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
}
static void clk_hfpll_disable(struct clk_hw *hw)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
unsigned long flags;
spin_lock_irqsave(&h->lock, flags);
__clk_hfpll_disable(h);
spin_unlock_irqrestore(&h->lock, flags);
}
static int clk_hfpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
unsigned long rrate;
req->rate = clamp(req->rate, hd->min_rate, hd->max_rate);
rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate;
if (rrate > hd->max_rate)
rrate -= req->best_parent_rate;
req->rate = rrate;
return 0;
}
/*
* For optimization reasons, assumes no downstream clocks are actively using
* it.
*/
static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
unsigned long flags;
u32 l_val, val;
bool enabled;
l_val = rate / parent_rate;
spin_lock_irqsave(&h->lock, flags);
enabled = __clk_is_enabled(hw->clk);
if (enabled)
__clk_hfpll_disable(h);
/* Pick the right VCO. */
if (hd->user_reg && hd->user_vco_mask) {
regmap_read(regmap, hd->user_reg, &val);
if (rate <= hd->low_vco_max_rate)
val &= ~hd->user_vco_mask;
else
val |= hd->user_vco_mask;
regmap_write(regmap, hd->user_reg, val);
}
regmap_write(regmap, hd->l_reg, l_val);
if (enabled)
__clk_hfpll_enable(hw);
spin_unlock_irqrestore(&h->lock, flags);
return 0;
}
static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
u32 l_val;
regmap_read(regmap, hd->l_reg, &l_val);
return l_val * parent_rate;
}
static int clk_hfpll_init(struct clk_hw *hw)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
u32 mode, status;
regmap_read(regmap, hd->mode_reg, &mode);
if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) {
__clk_hfpll_init_once(hw);
return 0;
}
if (hd->status_reg) {
regmap_read(regmap, hd->status_reg, &status);
if (!(status & BIT(hd->lock_bit))) {
WARN(1, "HFPLL %s is ON, but not locked!\n",
__clk_get_name(hw->clk));
clk_hfpll_disable(hw);
__clk_hfpll_init_once(hw);
}
}
return 0;
}
static int hfpll_is_enabled(struct clk_hw *hw)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
struct regmap *regmap = h->clkr.regmap;
u32 mode;
regmap_read(regmap, hd->mode_reg, &mode);
mode &= 0x7;
return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL);
}
const struct clk_ops clk_ops_hfpll = {
.enable = clk_hfpll_enable,
.disable = clk_hfpll_disable,
.is_enabled = hfpll_is_enabled,
.determine_rate = clk_hfpll_determine_rate,
.set_rate = clk_hfpll_set_rate,
.recalc_rate = clk_hfpll_recalc_rate,
.init = clk_hfpll_init,
};
EXPORT_SYMBOL_GPL(clk_ops_hfpll);
| linux-master | drivers/clk/qcom/clk-hfpll.c |
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2021, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_XO,
P_SLEEP_CLK,
P_GPLL0,
P_GPLL0_DIV2,
P_GPLL2,
P_GPLL3,
P_GPLL4,
P_GPLL6,
P_GPLL6_DIV2,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_DSI1PLL,
P_DSI1PLL_BYTE,
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gpll0_early",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_fixed_factor gpll0_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_early_div",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll2_early = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_early",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_hws = (const struct clk_hw*[]){
&gpll2_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static const struct pll_vco gpll3_p_vco[] = {
{ 1000000000, 2000000000, 0 },
};
static const struct alpha_pll_config gpll3_early_config = {
.l = 63,
.config_ctl_val = 0x4001055b,
.early_output_mask = 0,
.post_div_mask = GENMASK(11, 8),
.post_div_val = BIT(8),
};
static struct clk_alpha_pll gpll3_early = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpll3_p_vco,
.num_vco = ARRAY_SIZE(gpll3_p_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpll3_early",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll3 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_hws = (const struct clk_hw*[]){
&gpll3_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll4_early = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_early",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_hws = (const struct clk_hw*[]){
&gpll4_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll6_early = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x45000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_early",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_ops,
},
},
};
static struct clk_fixed_factor gpll6_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll6_early_div",
.parent_hws = (const struct clk_hw*[]){
&gpll6_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll_postdiv gpll6 = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_hws = (const struct clk_hw*[]){
&gpll6_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static const struct parent_map gcc_xo_gpll0_gpll0div2_2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 2 },
};
static const struct parent_map gcc_xo_gpll0_gpll0div2_4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0div2_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct parent_map gcc_apc_droop_detector_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};
static const struct clk_parent_data gcc_apc_droop_detector_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct freq_tbl ftbl_apc_droop_detector_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(576000000, P_GPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 apc0_droop_detector_clk_src = {
.cmd_rcgr = 0x78008,
.hid_width = 5,
.freq_tbl = ftbl_apc_droop_detector_clk_src,
.parent_map = gcc_apc_droop_detector_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "apc0_droop_detector_clk_src",
.parent_data = gcc_apc_droop_detector_data,
.num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 apc1_droop_detector_clk_src = {
.cmd_rcgr = 0x79008,
.hid_width = 5,
.freq_tbl = ftbl_apc_droop_detector_clk_src,
.parent_map = gcc_apc_droop_detector_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "apc1_droop_detector_clk_src",
.parent_data = gcc_apc_droop_detector_data,
.num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.freq_tbl = ftbl_apss_ahb_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0c00c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x0d000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0f000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x18000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(12500000, P_GPLL0_DIV2, 16, 1, 2),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x0c024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x0d014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x0f024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x18024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
F(16000000, P_GPLL0_DIV2, 5, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 1, 2, 25),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x0c044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x0d034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_byte0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 3 },
};
static const struct parent_map gcc_byte1_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 3 },
{ P_DSI1PLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_byte_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.hid_width = 5,
.parent_map = gcc_byte0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "byte0_clk_src",
.parent_data = gcc_byte_data,
.num_parents = ARRAY_SIZE(gcc_byte_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x4d0b0,
.hid_width = 5,
.parent_map = gcc_byte1_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "byte1_clk_src",
.parent_data = gcc_byte_data,
.num_parents = ARRAY_SIZE(gcc_byte_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct parent_map gcc_gp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_gp_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .fw_name = "sleep", .name = "sleep" },
};
static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_gp0_clk_src",
.parent_data = gcc_gp_data,
.num_parents = ARRAY_SIZE(gcc_gp_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_gp1_clk_src",
.parent_data = gcc_gp_data,
.num_parents = ARRAY_SIZE(gcc_gp_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 camss_top_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.hid_width = 5,
.freq_tbl = ftbl_camss_top_ahb_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "camss_top_ahb_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_cci_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
{ P_GPLL0_DIV2, 3 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_cci_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .fw_name = "sleep", .name = "sleep" },
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0_DIV2, 1, 3, 32),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x51000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_cci_clk_src,
.parent_map = gcc_cci_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cci_clk_src",
.parent_data = gcc_cci_data,
.num_parents = ARRAY_SIZE(gcc_cci_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_cpp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 3 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};
static const struct clk_parent_data gcc_cpp_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
.freq_tbl = ftbl_cpp_clk_src,
.parent_map = gcc_cpp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cpp_clk_src",
.parent_data = gcc_cpp_data,
.num_parents = ARRAY_SIZE(gcc_cpp_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.freq_tbl = ftbl_crypto_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_csi0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};
static const struct parent_map gcc_csi12_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 5 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_csi_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_csi_clk_src[] = {
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_csi0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0_clk_src",
.parent_data = gcc_csi_data,
.num_parents = ARRAY_SIZE(gcc_csi_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_csi12_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi1_clk_src",
.parent_data = gcc_csi_data,
.num_parents = ARRAY_SIZE(gcc_csi_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3c020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_csi12_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi2_clk_src",
.parent_data = gcc_csi_data,
.num_parents = ARRAY_SIZE(gcc_csi_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_csip_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 3 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};
static const struct clk_parent_data gcc_csip_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_csi_p_clk_src[] = {
F(66670000, P_GPLL0_DIV2, 6, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0p_clk_src = {
.cmd_rcgr = 0x58084,
.hid_width = 5,
.freq_tbl = ftbl_csi_p_clk_src,
.parent_map = gcc_csip_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0p_clk_src",
.parent_data = gcc_csip_data,
.num_parents = ARRAY_SIZE(gcc_csip_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi1p_clk_src = {
.cmd_rcgr = 0x58094,
.hid_width = 5,
.freq_tbl = ftbl_csi_p_clk_src,
.parent_map = gcc_csip_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi1p_clk_src",
.parent_data = gcc_csip_data,
.num_parents = ARRAY_SIZE(gcc_csip_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi2p_clk_src = {
.cmd_rcgr = 0x580a4,
.hid_width = 5,
.freq_tbl = ftbl_csi_p_clk_src,
.parent_map = gcc_csip_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi2p_clk_src",
.parent_data = gcc_csip_data,
.num_parents = ARRAY_SIZE(gcc_csip_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x4f000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi1phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x4f05c,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "csi2phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_esc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 3 },
};
static const struct clk_parent_data gcc_esc_vsync_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_esc_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "esc0_clk_src",
.parent_data = gcc_esc_vsync_data,
.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x4d0a8,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_esc_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "esc1_clk_src",
.parent_data = gcc_esc_vsync_data,
.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_gfx3d_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL3, 2 },
{ P_GPLL6, 3 },
{ P_GPLL4, 4 },
{ P_GPLL0_DIV2, 5 },
{ P_GPLL6_DIV2, 6 },
};
static const struct clk_parent_data gcc_gfx3d_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll3.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll6_early_div.hw },
};
static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(133330000, P_GPLL0_DIV2, 3, 0, 0),
F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
F(200000000, P_GPLL0_DIV2, 2, 0, 0),
F(266670000, P_GPLL0, 3.0, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(460800000, P_GPLL4, 2.5, 0, 0),
F(510000000, P_GPLL3, 2, 0, 0),
F(560000000, P_GPLL3, 2, 0, 0),
F(600000000, P_GPLL3, 2, 0, 0),
F(650000000, P_GPLL3, 2, 0, 0),
F(685000000, P_GPLL3, 2, 0, 0),
F(725000000, P_GPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.freq_tbl = ftbl_gfx3d_clk_src,
.parent_map = gcc_gfx3d_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gfx3d_clk_src",
.parent_data = gcc_gfx3d_data,
.num_parents = ARRAY_SIZE(gcc_gfx3d_data),
.ops = &clk_rcg2_floor_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct freq_tbl ftbl_gp_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp1_clk_src",
.parent_data = gcc_gp_data,
.num_parents = ARRAY_SIZE(gcc_gp_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp2_clk_src",
.parent_data = gcc_gp_data,
.num_parents = ARRAY_SIZE(gcc_gp_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gp3_clk_src",
.parent_data = gcc_gp_data,
.num_parents = ARRAY_SIZE(gcc_gp_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_jpeg0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_GPLL2, 5 },
};
static const struct clk_parent_data gcc_jpeg0_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(66670000, P_GPLL0_DIV2, 6, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x57000,
.hid_width = 5,
.freq_tbl = ftbl_jpeg0_clk_src,
.parent_map = gcc_jpeg0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "jpeg0_clk_src",
.parent_data = gcc_jpeg0_data,
.num_parents = ARRAY_SIZE(gcc_jpeg0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_mclk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_GPLL6_DIV2, 5 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_mclk_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll6_early_div.hw },
{ .fw_name = "sleep", .name = "sleep" },
};
static const struct freq_tbl ftbl_mclk_clk_src[] = {
F(19200000, P_GPLL6, 5, 4, 45),
F(24000000, P_GPLL6_DIV2, 1, 2, 45),
F(26000000, P_GPLL0, 1, 4, 123),
F(33330000, P_GPLL0_DIV2, 12, 0, 0),
F(36610000, P_GPLL6, 1, 2, 59),
F(66667000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk0_clk_src",
.parent_data = gcc_mclk_data,
.num_parents = ARRAY_SIZE(gcc_mclk_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk1_clk_src",
.parent_data = gcc_mclk_data,
.num_parents = ARRAY_SIZE(gcc_mclk_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x5c000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk2_clk_src",
.parent_data = gcc_mclk_data,
.num_parents = ARRAY_SIZE(gcc_mclk_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x5e000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mclk3_clk_src",
.parent_data = gcc_mclk_data,
.num_parents = ARRAY_SIZE(gcc_mclk_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_mdp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 3 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_mdp_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.freq_tbl = ftbl_mdp_clk_src,
.parent_map = gcc_mdp_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "mdp_clk_src",
.parent_data = gcc_mdp_data,
.num_parents = ARRAY_SIZE(gcc_mdp_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_pclk0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 3 },
};
static const struct parent_map gcc_pclk1_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 3 },
{ P_DSI1PLL, 1 },
};
static const struct clk_parent_data gcc_pclk_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pclk0_clk_src",
.parent_data = gcc_pclk_data,
.num_parents = ARRAY_SIZE(gcc_pclk_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x4d0b8,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk1_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pclk1_clk_src",
.parent_data = gcc_pclk_data,
.num_parents = ARRAY_SIZE(gcc_pclk_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
}
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(32000000, P_GPLL0_DIV2, 12.5, 0, 0),
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.freq_tbl = ftbl_pdm2_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_gfx_clk_src = {
.cmd_rcgr = 0x3a00c,
.hid_width = 5,
.freq_tbl = ftbl_rbcpr_gfx_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "rbcpr_gfx_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_sdcc1_ice_core_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_sdcc1_ice_core_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(270000000, P_GPLL6, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.hid_width = 5,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.parent_map = gcc_sdcc1_ice_core_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_sdcc1_ice_core_data,
.num_parents = ARRAY_SIZE(gcc_sdcc1_ice_core_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_sdcc_apps_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_sdcc_apss_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_DIV2, 5, 1, 4),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL4, 6, 0, 0),
F(384000000, P_GPLL4, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.parent_map = gcc_sdcc_apps_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_sdcc_apss_data,
.num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
.ops = &clk_rcg2_floor_ops,
}
};
static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_DIV2, 5, 1, 4),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL4, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.parent_map = gcc_sdcc_apps_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_sdcc_apss_data,
.num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
.ops = &clk_rcg2_floor_ops,
}
};
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x3f00c,
.hid_width = 5,
.freq_tbl = ftbl_usb30_master_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb30_master_clk_src",
.parent_data = gcc_xo_gpll0_gpll0div2_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_usb30_mock_utmi_map[] = {
{ P_XO, 0 },
{ P_GPLL6, 1 },
{ P_GPLL6_DIV2, 2 },
{ P_GPLL0, 3 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_usb30_mock_utmi_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll6_early_div.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL6_DIV2, 9, 1, 1),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x3f020,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.parent_map = gcc_usb30_mock_utmi_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_usb30_mock_utmi_data,
.num_parents = ARRAY_SIZE(gcc_usb30_mock_utmi_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_usb3_aux_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_usb3_aux_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "sleep", .name = "sleep" },
};
static const struct freq_tbl ftbl_usb3_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb3_aux_clk_src = {
.cmd_rcgr = 0x3f05c,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_usb3_aux_clk_src,
.parent_map = gcc_usb3_aux_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "usb3_aux_clk_src",
.parent_data = gcc_usb3_aux_data,
.num_parents = ARRAY_SIZE(gcc_usb3_aux_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_vcodec0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL2, 3 },
{ P_GPLL0_DIV2, 4 },
};
static const struct clk_parent_data gcc_vcodec0_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
F(114290000, P_GPLL0_DIV2, 3.5, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
F(540000000, P_GPLL6, 2, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4c000,
.hid_width = 5,
.freq_tbl = ftbl_vcodec0_clk_src,
.parent_map = gcc_vcodec0_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vcodec0_clk_src",
.parent_data = gcc_vcodec0_data,
.num_parents = ARRAY_SIZE(gcc_vcodec0_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_vfe_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL4, 3 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};
static const struct clk_parent_data gcc_vfe_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct freq_tbl ftbl_vfe_clk_src[] = {
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.freq_tbl = ftbl_vfe_clk_src,
.parent_map = gcc_vfe_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vfe0_clk_src",
.parent_data = gcc_vfe_data,
.num_parents = ARRAY_SIZE(gcc_vfe_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x58054,
.hid_width = 5,
.freq_tbl = ftbl_vfe_clk_src,
.parent_map = gcc_vfe_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vfe1_clk_src",
.parent_data = gcc_vfe_data,
.num_parents = ARRAY_SIZE(gcc_vfe_data),
.ops = &clk_rcg2_ops,
}
};
static const struct parent_map gcc_vsync_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
};
static const struct freq_tbl ftbl_vsync_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.freq_tbl = ftbl_vsync_clk_src,
.parent_map = gcc_vsync_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "vsync_clk_src",
.parent_data = gcc_esc_vsync_data,
.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
.ops = &clk_rcg2_ops,
}
};
static struct clk_branch gcc_apc0_droop_detector_gpll0_clk = {
.halt_reg = 0x78004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x78004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apc0_droop_detector_gpll0_clk",
.parent_hws = (const struct clk_hw*[]){
&apc0_droop_detector_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_apc1_droop_detector_gpll0_clk = {
.halt_reg = 0x79004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apc1_droop_detector_gpll0_clk",
.parent_hws = (const struct clk_hw*[]){
&apc1_droop_detector_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&apss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x46020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apss_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_apss_tcu_async_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_apss_tcu_async_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x59034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x59030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_gpu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x0b008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x04020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x05020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x0c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x0d010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x0f020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0f020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x18020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x18020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x0c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x0d00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x0f01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x1801c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1801c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x0c03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0c03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x0d02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0d02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x56004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x5101c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x58040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_cpp_axi_clk = {
.halt_reg = 0x58064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x5803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2_ahb_clk = {
.halt_reg = 0x3c040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2_clk = {
.halt_reg = 0x3c03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0_csiphy_3p_clk = {
.halt_reg = 0x58090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0_csiphy_3p_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0p_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1_csiphy_3p_clk = {
.halt_reg = 0x580a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x580a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1_csiphy_3p_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1p_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2_csiphy_3p_clk = {
.halt_reg = 0x580b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x580b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2_csiphy_3p_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2p_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2phy_clk = {
.halt_reg = 0x3c048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x4f01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2phytimer_clk = {
.halt_reg = 0x4f068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2pix_clk = {
.halt_reg = 0x3c058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi2rdi_clk = {
.halt_reg = 0x3c050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3c050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_csi_vfe1_clk = {
.halt_reg = 0x58074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x54018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x55018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_jpeg0_clk = {
.halt_reg = 0x57020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.halt_reg = 0x57024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_jpeg_axi_clk = {
.halt_reg = 0x57028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_jpeg_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x52018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x53018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x53018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x5c018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5c018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_mclk3_clk = {
.halt_reg = 0x5e018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5e018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_micro_ahb_clk = {
.halt_reg = 0x5600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x5a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe0_ahb_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe0_axi_clk = {
.halt_reg = 0x58048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x58038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe1_ahb_clk = {
.halt_reg = 0x58060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_camss_vfe1_axi_clk = {
.halt_reg = 0x58068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_camss_vfe1_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_camss_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_cpp_tbu_clk = {
.halt_reg = 0x12040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cpp_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data) {
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_dcc_clk = {
.halt_reg = 0x77004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x77004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_dcc_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data) {
.name = "gcc_jpeg_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdp_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_byte1_clk = {
.halt_reg = 0x4d0a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_esc1_clk = {
.halt_reg = 0x4d09c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d09c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4d088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_pclk1_clk = {
.halt_reg = 0x4d0a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_aon_clk = {
.halt_reg = 0x59044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_oxili_timer_clk = {
.halt_reg = 0x59040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_oxili_timer_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_pcnoc_usb3_axi_clk = {
.halt_reg = 0x3f038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcnoc_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data) {
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_dap_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_qusb_ref_clk = {
.halt_reg = 0,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x41030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_qusb_ref_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_rbcpr_gfx_clk = {
.halt_reg = 0x3a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_rbcpr_gfx_clk",
.parent_hws = (const struct clk_hw*[]){
&rbcpr_gfx_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x5d014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data) {
.name = "gcc_smmu_cfg_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x3f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x3f008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x3f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb3_aux_clk = {
.halt_reg = 0x3f044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3f044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb3_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&usb3_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_usb3_pipe_clk = {
.halt_reg = 0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x3f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb3_pipe_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb_phy_cfg_ahb_clk = {
.halt_reg = 0x3f080,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x3f080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_phy_cfg_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_usb_ss_ref_clk = {
.halt_reg = 0,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3f07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb_ss_ref_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_ahb_clk = {
.halt_reg = 0x4c020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_ahb_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_axi_clk = {
.halt_reg = 0x4c024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_axi_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.halt_reg = 0x4c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_core0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_venus0_vcodec0_clk = {
.halt_reg = 0x4c01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4c01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
}
}
};
static struct clk_branch gcc_venus_tbu_clk = {
.halt_reg = 0x12014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data) {
.name = "gcc_venus_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_vfe1_tbu_clk = {
.halt_reg = 0x12090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data) {
.name = "gcc_vfe1_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct clk_branch gcc_vfe_tbu_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data) {
.name = "gcc_vfe_tbu_clk",
.ops = &clk_branch2_ops,
}
}
};
static struct gdsc usb30_gdsc = {
.gdscr = 0x3f078,
.pd = {
.name = "usb30_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
/*
* FIXME: dwc3 usb gadget cannot resume after GDSC power off
* dwc3 7000000.dwc3: failed to enable ep0out
*/
.flags = ALWAYS_ON,
};
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
.cxc_count = 2,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x4c028,
.cxcs = (unsigned int []){ 0x4c02c },
.cxc_count = 1,
.pd = {
.name = "venus_core0",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
.cxc_count = 2,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x5701c,
.cxcs = (unsigned int []){ 0x57020, 0x57028 },
.cxc_count = 2,
.pd = {
.name = "jpeg_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe0_gdsc = {
.gdscr = 0x58034,
.cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
.cxc_count = 4,
.pd = {
.name = "vfe0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe1_gdsc = {
.gdscr = 0x5806c,
.cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
.cxc_count = 4,
.pd = {
.name = "vfe1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gx_gdsc = {
.gdscr = 0x5901c,
.clamp_io_ctrl = 0x5b00c,
.cxcs = (unsigned int []){ 0x59000, 0x59024 },
.cxc_count = 2,
.pd = {
.name = "oxili_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO,
};
static struct gdsc oxili_cx_gdsc = {
.gdscr = 0x5904c,
.cxcs = (unsigned int []){ 0x59020 },
.cxc_count = 1,
.pd = {
.name = "oxili_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc cpp_gdsc = {
.gdscr = 0x58078,
.cxcs = (unsigned int []){ 0x5803c, 0x58064 },
.cxc_count = 2,
.pd = {
.name = "cpp_gdsc",
},
.flags = ALWAYS_ON,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_hw *gcc_msm8953_hws[] = {
&gpll0_early_div.hw,
&gpll6_early_div.hw,
};
static struct clk_regmap *gcc_msm8953_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL2] = &gpll2.clkr,
[GPLL2_EARLY] = &gpll2_early.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_EARLY] = &gpll3_early.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL6_EARLY] = &gpll6_early.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_APSS_TCU_ASYNC_CLK] = &gcc_apss_tcu_async_clk.clkr,
[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[APC0_DROOP_DETECTOR_CLK_SRC] = &apc0_droop_detector_clk_src.clkr,
[APC1_DROOP_DETECTOR_CLK_SRC] = &apc1_droop_detector_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CSI0P_CLK_SRC] = &csi0p_clk_src.clkr,
[CSI1P_CLK_SRC] = &csi1p_clk_src.clkr,
[CSI2P_CLK_SRC] = &csi2p_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[RBCPR_GFX_CLK_SRC] = &rbcpr_gfx_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_AUX_CLK_SRC] = &usb3_aux_clk_src.clkr,
[GCC_APC0_DROOP_DETECTOR_GPLL0_CLK] = &gcc_apc0_droop_detector_gpll0_clk.clkr,
[GCC_APC1_DROOP_DETECTOR_GPLL0_CLK] = &gcc_apc1_droop_detector_gpll0_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI0_CSIPHY_3P_CLK] = &gcc_camss_csi0_csiphy_3p_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI1_CSIPHY_3P_CLK] = &gcc_camss_csi1_csiphy_3p_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
[GCC_CAMSS_CSI2_CSIPHY_3P_CLK] = &gcc_camss_csi2_csiphy_3p_clk.clkr,
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_PCNOC_USB3_AXI_CLK] = &gcc_pcnoc_usb3_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_RBCPR_GFX_CLK] = &gcc_rbcpr_gfx_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB3_AUX_CLK] = &gcc_usb3_aux_clk.clkr,
[GCC_USB_PHY_CFG_AHB_CLK] = &gcc_usb_phy_cfg_ahb_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
[GCC_QUSB_REF_CLK] = &gcc_qusb_ref_clk.clkr,
[GCC_USB_SS_REF_CLK] = &gcc_usb_ss_ref_clk.clkr,
[GCC_USB3_PIPE_CLK] = &gcc_usb3_pipe_clk.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
[GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
[GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
};
static const struct qcom_reset_map gcc_msm8953_resets[] = {
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
[GCC_MSS_BCR] = { 0x71000 },
[GCC_QUSB2_PHY_BCR] = { 0x4103c },
[GCC_USB3PHY_PHY_BCR] = { 0x3f03c },
[GCC_USB3_PHY_BCR] = { 0x3f034 },
[GCC_USB_30_BCR] = { 0x3f070 },
};
static const struct regmap_config gcc_msm8953_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static struct gdsc *gcc_msm8953_gdscs[] = {
[CPP_GDSC] = &cpp_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[OXILI_CX_GDSC] = &oxili_cx_gdsc,
[OXILI_GX_GDSC] = &oxili_gx_gdsc,
[USB30_GDSC] = &usb30_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_GDSC] = &venus_gdsc,
[VFE0_GDSC] = &vfe0_gdsc,
[VFE1_GDSC] = &vfe1_gdsc,
};
static const struct qcom_cc_desc gcc_msm8953_desc = {
.config = &gcc_msm8953_regmap_config,
.clks = gcc_msm8953_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8953_clocks),
.resets = gcc_msm8953_resets,
.num_resets = ARRAY_SIZE(gcc_msm8953_resets),
.gdscs = gcc_msm8953_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8953_gdscs),
.clk_hws = gcc_msm8953_hws,
.num_clk_hws = ARRAY_SIZE(gcc_msm8953_hws),
};
static int gcc_msm8953_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_msm8953_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
return qcom_cc_really_probe(pdev, &gcc_msm8953_desc, regmap);
}
static const struct of_device_id gcc_msm8953_match_table[] = {
{ .compatible = "qcom,gcc-msm8953" },
{},
};
static struct platform_driver gcc_msm8953_driver = {
.probe = gcc_msm8953_probe,
.driver = {
.name = "gcc-msm8953",
.of_match_table = gcc_msm8953_match_table,
},
};
static int __init gcc_msm8953_init(void)
{
return platform_driver_register(&gcc_msm8953_driver);
}
core_initcall(gcc_msm8953_init);
static void __exit gcc_msm8953_exit(void)
{
platform_driver_unregister(&gcc_msm8953_driver);
}
module_exit(gcc_msm8953_exit);
MODULE_DESCRIPTION("Qualcomm GCC MSM8953 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-msm8953.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_AUD_REF_CLK,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x1c000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_0_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_AUD_REF_CLK, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "aud_ref_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b038,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d038,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
.cmd_rcgr = 0x6038,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
.cmd_rcgr = 0x6f014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk_src",
.parent_data = gcc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x17270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x173a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x174d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17730,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17860,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e3a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e4d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
F(105495, P_BI_TCXO, 2, 1, 91),
{ }
};
static struct clk_rcg2 gcc_tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x75024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x7506c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x750a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x75084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x7706c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x10020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x10038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x10064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
.reg = 0x48028,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_cpuss_ahb_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0xf050,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.reg = 0x10050,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x9000c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x750cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x750cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0xf080,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xf080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x10080,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x10080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0xb02c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0xb030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0xb040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0xf07c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xf07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x1007c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1007c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
.halt_reg = 0x8d058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8d058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_pcie_sf_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0xb034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0xb038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0xb044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_en = {
.halt_reg = 0x8c014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_axi_clk = {
.halt_reg = 0x73008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x73008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = {
.halt_reg = 0x73004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x73004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_cfg_ahb_clk = {
.halt_reg = 0x4d004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_dma_clk = {
.halt_reg = 0x4d00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_dma_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_refgen_clk = {
.halt_reg = 0x6f02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_refgen_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_refgen_clk = {
.halt_reg = 0x6f030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_refgen_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2_phy_refgen_clk = {
.halt_reg = 0x6f034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie2_phy_refgen_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b02c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d02c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_aux_clk = {
.halt_reg = 0x6028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
.halt_reg = 0x6024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
.halt_reg = 0x601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x602c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_axi_clk = {
.halt_reg = 0x6014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
.halt_reg = 0x6010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_mdm_clkref_en = {
.halt_reg = 0x8c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_mdm_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_wifi_clkref_en = {
.halt_reg = 0x8c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_wifi_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_wigig_clkref_en = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_wigig_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0xb018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0xb010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0xb014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1713c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1726c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1739c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x174cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x175fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x1772c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x1785c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x23140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x23138,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x1813c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x1826c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x1839c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x185fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x23278,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x23270,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e13c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e26c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e39c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e4cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e5fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_1x_clkref_en = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_1x_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x75064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x7509c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7509c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7509c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_reg = 0x75020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x75020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_reg = 0x750b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x750b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_reg = 0x7501c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x7709c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7709c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7709c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x77020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x1001c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1001c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0xf05c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xf05c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_clkref_en = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x10054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x10058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x1005c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1005c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0xb028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0xb03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_2_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "pcie_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d050,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0x7d058,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
.gdscr = 0x7d054,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
.gdscr = 0x7d06c,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sm8250_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
[GCC_NPU_BWMON_CFG_AHB_CLK] = &gcc_npu_bwmon_cfg_ahb_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
[GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
[GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
[GCC_PCIE_MDM_CLKREF_EN] = &gcc_pcie_mdm_clkref_en.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
[GCC_PCIE_WIFI_CLKREF_EN] = &gcc_pcie_wifi_clkref_en.clkr,
[GCC_PCIE_WIGIG_CLKREF_EN] = &gcc_pcie_wigig_clkref_en.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_1X_CLKREF_EN] = &gcc_ufs_1x_clkref_en.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL9] = &gpll9.clkr,
};
static struct gdsc *gcc_sm8250_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[PCIE_2_GDSC] = &pcie_2_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
};
static const struct qcom_reset_map gcc_sm8250_resets[] = {
[GCC_GPU_BCR] = { 0x71000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_NPU_BWMON_BCR] = { 0x73000 },
[GCC_NPU_BCR] = { 0x4d000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
[GCC_PCIE_2_BCR] = { 0x6000 },
[GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
[GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_PRNG_BCR] = { 0x34000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
};
static const struct regmap_config gcc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9c100,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm8250_desc = {
.config = &gcc_sm8250_regmap_config,
.clks = gcc_sm8250_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8250_clocks),
.resets = gcc_sm8250_resets,
.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
.gdscs = gcc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
};
static const struct of_device_id gcc_sm8250_match_table[] = {
{ .compatible = "qcom,gcc-sm8250" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table);
static int gcc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8250_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to NPU and GPU
* via MISC registers.
*/
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/*
* Keep the clocks always-ON
* GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
* GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK,
* GCC_SYS_NOC_CPUSS_AHB_CLK
*/
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap);
}
static struct platform_driver gcc_sm8250_driver = {
.probe = gcc_sm8250_probe,
.driver = {
.name = "gcc-sm8250",
.of_match_table = gcc_sm8250_match_table,
},
};
static int __init gcc_sm8250_init(void)
{
return platform_driver_register(&gcc_sm8250_driver);
}
subsys_initcall(gcc_sm8250_init);
static void __exit gcc_sm8250_exit(void)
{
platform_driver_unregister(&gcc_sm8250_driver);
}
module_exit(gcc_sm8250_exit);
MODULE_DESCRIPTION("QTI GCC SM8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sm8250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_AUX2,
P_GPLL0_OUT_EARLY,
P_GPLL10_OUT_MAIN,
P_GPLL11_OUT_MAIN,
P_GPLL3_OUT_EARLY,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_EARLY,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_GPLL8_OUT_EARLY,
P_GPLL8_OUT_MAIN,
P_GPLL9_OUT_EARLY,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct pll_vco default_vco[] = {
{ 500000000, 1000000000, 2 },
};
static struct pll_vco gpll9_vco[] = {
{ 500000000, 1250000000, 0 },
};
static struct pll_vco gpll10_vco[] = {
{ 750000000, 1500000000, 1 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_aux2",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static const struct clk_div_table post_div_table_gpll0_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_main = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
/* 1152MHz configuration */
static const struct alpha_pll_config gpll10_config = {
.l = 0x3c,
.vco_val = 0x1 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll10 = {
.offset = 0xa000,
.vco_table = gpll10_vco,
.num_vco = ARRAY_SIZE(gpll10_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gpll10",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll10_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpll10_out_main = {
.offset = 0xa000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll10_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll10_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
/* 600MHz configuration */
static const struct alpha_pll_config gpll11_config = {
.l = 0x1F,
.alpha = 0x0,
.alpha_hi = 0x40,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll11 = {
.offset = 0xb000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gpll11",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll11_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpll11_out_main = {
.offset = 0xb000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll11_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll11_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll4_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpll4_out_main = {
.offset = 0x4000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll4_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll6_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll6_out_main = {
.offset = 0x6000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll6_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll7_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpll7_out_main = {
.offset = 0x7000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll7_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll7_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
/* 800MHz configuration */
static const struct alpha_pll_config gpll8_config = {
.l = 0x29,
.alpha = 0xAAAAAAAA,
.alpha_hi = 0xAA,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gpll8",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll8_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll8_out_main = {
.offset = 0x8000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll8_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll8_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
};
/* 1152MHz configuration */
static const struct alpha_pll_config gpll9_config = {
.l = 0x3C,
.alpha = 0x0,
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(9, 8),
.main_output_mask = BIT(0),
.config_ctl_val = 0x00004289,
.test_ctl_mask = GENMASK(31, 0),
.test_ctl_val = 0x08000000,
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x9000,
.vco_table = gpll9_vco,
.num_vco = ARRAY_SIZE(gpll9_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll9_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll9_out_main = {
.offset = 0x9000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll9_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll9_out_main",
.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
};
static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL6_OUT_MAIN, 4 },
};
static const struct clk_parent_data gcc_parents_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll6_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL9_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL9_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parents_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parents_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll8_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL6_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll6_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll8_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parents_9[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll8_out_main.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 2 },
{ P_GPLL10_OUT_MAIN, 3 },
{ P_GPLL6_OUT_EARLY, 4 },
{ P_GPLL9_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parents_10[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10_out_main.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parents_11[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_aux2.clkr.hw },
{ .hw = &gpll7_out_main.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parents_12[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL11_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parents_13[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll11_out_main.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_axi_clk_src = {
.cmd_rcgr = 0x5802c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_cci_clk_src = {
.cmd_rcgr = 0x56000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_camss_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk_src",
.parent_data = gcc_parents_9,
.num_parents = ARRAY_SIZE(gcc_parents_9),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.cmd_rcgr = 0x59000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.cmd_rcgr = 0x5901c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
.cmd_rcgr = 0x59038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk_src",
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),
{ }
};
static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.cmd_rcgr = 0x5101c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.cmd_rcgr = 0x51038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.cmd_rcgr = 0x51054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk_src",
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
.cmd_rcgr = 0x55024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_clk_src = {
.cmd_rcgr = 0x55004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_ope_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk_src",
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
.cmd_rcgr = 0x52004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
.cmd_rcgr = 0x52094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
.cmd_rcgr = 0x52024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
.cmd_rcgr = 0x520b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
.cmd_rcgr = 0x52044,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_clk_src",
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
.cmd_rcgr = 0x520d4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_csid_clk_src",
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),
F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
.cmd_rcgr = 0x52064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_cphy_rx_clk_src",
.parent_data = gcc_parents_10,
.num_parents = ARRAY_SIZE(gcc_parents_10),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
.cmd_rcgr = 0x58010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk_src",
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x4d004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x4e004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x4f004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_2,
.num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x20010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x1f148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x1f278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x1f3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x1f4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x1f608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x1f738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x38028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parents_1,
.num_parents = ARRAY_SIZE(gcc_parents_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x38010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_11,
.num_parents = ARRAY_SIZE(gcc_parents_11),
.ops = &clk_rcg2_floor_ops,
.flags = CLK_OPS_PARENT_ENABLE,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x45020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x45048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x4507c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x45060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x1a01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x1a034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x1a04c,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x1a060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parents_12,
.num_parents = ARRAY_SIZE(gcc_parents_12),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_video_venus_clk_src = {
.cmd_rcgr = 0x58060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_13,
.freq_tbl = ftbl_gcc_video_venus_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_clk_src",
.parent_data = gcc_parents_13,
.num_parents = ARRAY_SIZE(gcc_parents_13),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch gcc_ahb2phy_csi_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_csi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy_usb_clk = {
.halt_reg = 0x1d008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1d008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_usb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_nrt_clk = {
.halt_reg = 0x17070,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17070,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_nrt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_rt_clk = {
.halt_reg = 0x1706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_rt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_axi_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_camnoc_atb_clk = {
.halt_reg = 0x5804c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x5804c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5804c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_camnoc_atb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
.halt_reg = 0x58050,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x58050,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_camnoc_nts_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_0_clk = {
.halt_reg = 0x56018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_0_clk = {
.halt_reg = 0x52088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_1_clk = {
.halt_reg = 0x5208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5208c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_2_clk = {
.halt_reg = 0x52090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x59018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x59034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2phytimer_clk = {
.halt_reg = 0x59050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x51034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x51050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk3_clk = {
.halt_reg = 0x5106c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5106c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_nrt_axi_clk = {
.halt_reg = 0x58054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_ahb_clk = {
.halt_reg = 0x5503c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5503c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_ope_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_clk = {
.halt_reg = 0x5501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_ope_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_rt_axi_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_clk = {
.halt_reg = 0x5201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
.halt_reg = 0x5207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_csid_clk = {
.halt_reg = 0x520ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_clk = {
.halt_reg = 0x5203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
.halt_reg = 0x52080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_csid_clk = {
.halt_reg = 0x520cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_2_clk = {
.halt_reg = 0x5205c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5205c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
.halt_reg = 0x52084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_cphy_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_2_csid_clk = {
.halt_reg = 0x520ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520ec,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_csid_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_tfe_2_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x58028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a084,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1a084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_gnoc_clk = {
.halt_reg = 0x2b004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_gnoc_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
.reg = 0x17058,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gcc_disp_gpll0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_core_clk = {
.halt_reg = 0x17064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x4d000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x4e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x4f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x36004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gpll0_out_aux2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_clk = {
.halt_reg = 0x36100,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x36100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x3600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x36018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_throttle_core_clk = {
.halt_reg = 0x36048,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36048,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(31),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x20004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x21004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x17060,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17060,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
.halt_reg = 0x36040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x17010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x1f014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1f00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1f144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1f274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1f3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1f4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x1f604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x1f734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x38008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x3800c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3800c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x2b06c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b06c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
.halt_reg = 0x45098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a080,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1a080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x45014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x45010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x45044,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45044,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x45078,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45078,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x4501c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x45018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x45018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x45040,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x1a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x1a018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x1a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x9f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x1a054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x1a058,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1a058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vcodec0_axi_clk = {
.halt_reg = 0x6e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vcodec0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ahb_clk = {
.halt_reg = 0x6e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ctl_axi_clk = {
.halt_reg = 0x6e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1701c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_core_clk = {
.halt_reg = 0x17068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_vcodec0_sys_clk = {
.halt_reg = 0x580a4,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x580a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x580a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_vcodec0_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_venus_ctl_clk = {
.halt_reg = 0x5808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_ctl_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gcc_camss_top_gdsc = {
.gdscr = 0x58004,
.pd = {
.name = "gcc_camss_top",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_ufs_phy_gdsc = {
.gdscr = 0x45004,
.pd = {
.name = "gcc_ufs_phy",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_usb30_prim_gdsc = {
.gdscr = 0x1a004,
.pd = {
.name = "gcc_usb30_prim",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_vcodec0_gdsc = {
.gdscr = 0x58098,
.pd = {
.name = "gcc_vcodec0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc gcc_venus_gdsc = {
.gdscr = 0x5807c,
.pd = {
.name = "gcc_venus",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
.gdscr = 0x7d060,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu1",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
.gdscr = 0x7d07c,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu0",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
.gdscr = 0x7d074,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_rt",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
.gdscr = 0x7d078,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sm6115_clocks[] = {
[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
[GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
[GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
[GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,
[GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,
[GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,
[GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,
[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,
[GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
[GPLL10] = &gpll10.clkr,
[GPLL10_OUT_MAIN] = &gpll10_out_main.clkr,
[GPLL11] = &gpll11.clkr,
[GPLL11_OUT_MAIN] = &gpll11_out_main.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL7_OUT_MAIN] = &gpll7_out_main.clkr,
[GPLL8] = &gpll8.clkr,
[GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
[GPLL9] = &gpll9.clkr,
[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
};
static const struct qcom_reset_map gcc_sm6115_resets[] = {
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
[GCC_SDCC1_BCR] = { 0x38000 },
[GCC_SDCC2_BCR] = { 0x1e000 },
[GCC_UFS_PHY_BCR] = { 0x45000 },
[GCC_USB30_PRIM_BCR] = { 0x1a000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
[GCC_VCODEC0_BCR] = { 0x58094 },
[GCC_VENUS_BCR] = { 0x58078 },
[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
};
static struct gdsc *gcc_sm6115_gdscs[] = {
[GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,
[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
[GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
[GCC_VENUS_GDSC] = &gcc_venus_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
};
static const struct regmap_config gcc_sm6115_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc7000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm6115_desc = {
.config = &gcc_sm6115_regmap_config,
.clks = gcc_sm6115_clocks,
.num_clks = ARRAY_SIZE(gcc_sm6115_clocks),
.resets = gcc_sm6115_resets,
.num_resets = ARRAY_SIZE(gcc_sm6115_resets),
.gdscs = gcc_sm6115_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs),
};
static const struct of_device_id gcc_sm6115_match_table[] = {
{ .compatible = "qcom,gcc-sm6115" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table);
static int gcc_sm6115_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm6115_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap);
}
static struct platform_driver gcc_sm6115_driver = {
.probe = gcc_sm6115_probe,
.driver = {
.name = "gcc-sm6115",
.of_match_table = gcc_sm6115_match_table,
},
};
static int __init gcc_sm6115_init(void)
{
return platform_driver_register(&gcc_sm6115_driver);
}
subsys_initcall(gcc_sm6115_init);
static void __exit gcc_sm6115_exit(void)
{
platform_driver_unregister(&gcc_sm6115_driver);
}
module_exit(gcc_sm6115_exit);
MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-sm6115");
| linux-master | drivers/clk/qcom/gcc-sm6115.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_EVEN,
P_DISP_CC_PLL0_OUT_MAIN,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_EDP_PHY_PLL_LINK_CLK,
P_EDP_PHY_PLL_VCO_DIV_CLK,
P_GCC_DISP_GPLL0_CLK,
};
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 1520MHz Configuration*/
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x4F,
.alpha = 0x2AAA,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_phy_pll_link_clk" },
{ .fw_name = "dp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_EDP_PHY_PLL_LINK_CLK, 1 },
{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "edp_phy_pll_link_clk" },
{ .fw_name = "edp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk" },
{ .hw = &disp_cc_pll0.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_clk" },
};
static const struct parent_map disp_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x1170,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x10d8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.cmd_rcgr = 0x1158,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.cmd_rcgr = 0x1128,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x110c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.cmd_rcgr = 0x1140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
.cmd_rcgr = 0x11d0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
.cmd_rcgr = 0x11a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
.cmd_rcgr = 0x1188,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_pixel_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x10f4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x1090,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x1078,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x10a8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x10c0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x10f0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
.reg = 0x1124,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
.reg = 0x11b8,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x1050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x1030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x1034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.halt_reg = 0x104c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
.halt_reg = 0x1044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_clk = {
.halt_reg = 0x103c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x103c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x1040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.halt_reg = 0x1048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_aux_clk = {
.halt_reg = 0x1060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_link_clk = {
.halt_reg = 0x1058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
.halt_reg = 0x105c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x105c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_div_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x1038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x1014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x1024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x1010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x101c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x102c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0x5004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc disp_cc_mdss_core_gdsc = {
.gdscr = 0x1004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp_cc_mdss_core_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sc7280_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
&disp_cc_mdss_dp_link_div_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
[DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] =
&disp_cc_mdss_edp_link_div_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
};
static struct gdsc *disp_cc_sc7280_gdscs[] = {
[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
};
static const struct regmap_config disp_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sc7280_desc = {
.config = &disp_cc_sc7280_regmap_config,
.clks = disp_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
.gdscs = disp_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
};
static const struct of_device_id disp_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sc7280_match_table);
static int disp_cc_sc7280_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &disp_cc_sc7280_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/*
* Keep the clocks always-ON
* DISP_CC_XO_CLK
*/
regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
}
static struct platform_driver disp_cc_sc7280_driver = {
.probe = disp_cc_sc7280_probe,
.driver = {
.name = "disp_cc-sc7280",
.of_match_table = disp_cc_sc7280_match_table,
},
};
static int __init disp_cc_sc7280_init(void)
{
return platform_driver_register(&disp_cc_sc7280_driver);
}
subsys_initcall(disp_cc_sc7280_init);
static void __exit disp_cc_sc7280_exit(void)
{
platform_driver_unregister(&disp_cc_sc7280_driver);
}
module_exit(disp_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/dispcc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
#include "reset.h"
static struct clk_branch lcc_ahbfabric_cbc_clk = {
.halt_reg = 0x1b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lcc_ahbfabric_cbc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lcc_q6ss_ahbs_cbc_clk = {
.halt_reg = 0x22000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x22000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lcc_q6ss_ahbs_cbc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = {
.halt_reg = 0x1c000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x1c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lcc_q6ss_tcm_slave_cbc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lcc_q6ss_ahbm_cbc_clk = {
.halt_reg = 0x22004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x22004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lcc_q6ss_ahbm_cbc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lcc_q6ss_axim_cbc_clk = {
.halt_reg = 0x1c004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lcc_q6ss_axim_cbc_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lcc_q6ss_bcr_sleep_clk = {
.halt_reg = 0x6004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x6004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lcc_q6ss_bcr_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
/* TCSR clock */
static struct clk_branch tcsr_lcc_csr_cbcr_clk = {
.halt_reg = 0x8008,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "tcsr_lcc_csr_cbcr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct regmap_config q6sstop_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static struct clk_regmap *q6sstop_qcs404_clocks[] = {
[LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr,
[LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr,
[LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr,
[LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr,
[LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr,
[LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr,
};
static const struct qcom_reset_map q6sstop_qcs404_resets[] = {
[Q6SSTOP_BCR_RESET] = { 0x6000 },
};
static const struct qcom_cc_desc q6sstop_qcs404_desc = {
.config = &q6sstop_regmap_config,
.clks = q6sstop_qcs404_clocks,
.num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks),
.resets = q6sstop_qcs404_resets,
.num_resets = ARRAY_SIZE(q6sstop_qcs404_resets),
};
static struct clk_regmap *tcsr_qcs404_clocks[] = {
[TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr,
};
static const struct qcom_cc_desc tcsr_qcs404_desc = {
.config = &q6sstop_regmap_config,
.clks = tcsr_qcs404_clocks,
.num_clks = ARRAY_SIZE(tcsr_qcs404_clocks),
};
static const struct of_device_id q6sstopcc_qcs404_match_table[] = {
{ .compatible = "qcom,qcs404-q6sstopcc" },
{ }
};
MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table);
static int q6sstopcc_qcs404_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, NULL);
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
q6sstop_regmap_config.name = "q6sstop_tcsr";
desc = &tcsr_qcs404_desc;
ret = qcom_cc_probe_by_index(pdev, 1, desc);
if (ret)
goto err_put_rpm;
q6sstop_regmap_config.name = "q6sstop_cc";
desc = &q6sstop_qcs404_desc;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static const struct dev_pm_ops q6sstopcc_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver q6sstopcc_qcs404_driver = {
.probe = q6sstopcc_qcs404_probe,
.driver = {
.name = "qcs404-q6sstopcc",
.of_match_table = q6sstopcc_qcs404_match_table,
.pm = &q6sstopcc_pm_ops,
},
};
module_platform_driver(q6sstopcc_qcs404_driver);
MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/q6sstop-qcs404.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/clk.h>
#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_MMPLL0,
P_MMPLL1,
P_MMPLL3,
P_MMPLL4,
P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
P_DSI0PLL,
P_DSI1PLL,
P_DSI0PLL_BYTE,
P_DSI1PLL_BYTE,
P_HDMIPLL,
};
static const struct parent_map mmcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 }
};
static const struct clk_parent_data mmcc_xo_gpll0[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
};
static const struct parent_map mmss_xo_hdmi_map[] = {
{ P_XO, 0 },
{ P_HDMIPLL, 3 }
};
static const struct clk_parent_data mmss_xo_hdmi[] = {
{ .fw_name = "xo" },
{ .fw_name = "hdmipll" },
};
static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pll" },
{ .fw_name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsibyte_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 }
};
static const struct clk_parent_data mmcc_xo_dsibyte[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte" },
};
static struct pll_vco mmpll_p_vco[] = {
{ 250000000, 500000000, 3 },
{ 500000000, 1000000000, 2 },
{ 1000000000, 1500000000, 1 },
{ 1500000000, 2000000000, 0 },
};
static struct pll_vco mmpll_t_vco[] = {
{ 500000000, 1500000000, 0 },
};
static const struct alpha_pll_config mmpll_p_config = {
.post_div_mask = 0xf00,
};
static struct clk_alpha_pll mmpll0_early = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
.enable_reg = 0x100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv mmpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
.parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll1_early = {
.offset = 0x30,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
.enable_reg = 0x100,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "mmpll1_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
}
},
};
static struct clk_alpha_pll_postdiv mmpll1 = {
.offset = 0x30,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
.parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll3_early = {
.offset = 0x60,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll3 = {
.offset = 0x60,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
.parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll mmpll4_early = {
.offset = 0x90,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll4 = {
.offset = 0x90,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
.parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_MMPLL1, 2 }
};
static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .hw = &mmpll1.clkr.hw },
};
static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_MMPLL0, 1 }
};
static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .hw = &mmpll0.clkr.hw },
};
static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_MMPLL0, 1 },
{ P_MMPLL3, 3 }
};
static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll3.clkr.hw },
};
static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_MMPLL0, 1 },
{ P_MMPLL4, 3 }
};
static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
};
static struct clk_alpha_pll mmpll5_early = {
.offset = 0xc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll5 = {
.offset = 0xc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5",
.parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_ahb_clk_src[] = {
/* Note: There might be more frequencies desired here. */
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0, 15, 0, 0),
F(80000000, P_MMPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 ahb_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ahb_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_axi_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(333430000, P_MMPLL1, 3.5, 0, 0),
F(466800000, P_MMPLL1, 2.5, 0, 0),
{ }
};
static const struct freq_tbl ftbl_axi_clk_src_8992[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(404000000, P_MMPLL1, 2, 0, 0),
{ }
};
static struct clk_rcg2 axi_clk_src = {
.cmd_rcgr = 0x5040,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll1_map,
.freq_tbl = ftbl_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "axi_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll1,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
{ }
};
static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x3090,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
F(66670000, P_GPLL0, 9, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(510000000, P_MMPLL3, 2, 0, 0),
{ }
};
static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = {
F(66670000, P_GPLL0, 9, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(510000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
.freq_tbl = ftbl_vcodec0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x3100,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3160,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi3_clk_src = {
.cmd_rcgr = 0x31c0,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe0_clk_src[] = {
F(80000000, P_GPLL0, 7.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(533330000, P_MMPLL0, 1.5, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = {
F(80000000, P_GPLL0, 7.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x3600,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
.freq_tbl = ftbl_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe1_clk_src[] = {
F(80000000, P_GPLL0, 7.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(533330000, P_MMPLL0, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x3620,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
.freq_tbl = ftbl_vfe1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
F(640000000, P_MMPLL4, 1.5, 0, 0),
{ }
};
static const struct freq_tbl ftbl_cpp_clk_src_8992[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
F(640000000, P_MMPLL4, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x3640,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
.freq_tbl = ftbl_cpp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(480000000, P_MMPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 jpeg1_clk_src = {
.cmd_rcgr = 0x3520,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
.freq_tbl = ftbl_jpeg0_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg1_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg2_clk_src = {
.cmd_rcgr = 0x3540,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_jpeg2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x3060,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi2phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_fd_core_clk_src[] = {
F(60000000, P_GPLL0, 10, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 fd_core_clk_src = {
.cmd_rcgr = 0x3b00,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "fd_core_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(85710000, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(120000000, P_GPLL0, 5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static const struct freq_tbl ftbl_mdp_clk_src_8992[] = {
F(85710000, P_GPLL0, 7, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x2040,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x2000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = mmcc_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = mmcc_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = {
F(19200000, P_XO, 1, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 ocmemnoc_clk_src = {
.cmd_rcgr = 0x5090,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_ocmemnoc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x3300,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_map,
.freq_tbl = ftbl_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = mmcc_xo_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
F(10000, P_XO, 16, 10, 120),
F(24000, P_GPLL0, 16, 1, 50),
F(6000000, P_GPLL0, 10, 1, 10),
F(12000000, P_GPLL0, 10, 1, 5),
F(13000000, P_GPLL0, 4, 13, 150),
F(24000000, P_GPLL0, 5, 1, 5),
{ }
};
static struct clk_rcg2 mmss_gp0_clk_src = {
.cmd_rcgr = 0x3420,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_map,
.freq_tbl = ftbl_mmss_gp0_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_gp0_clk_src",
.parent_data = mmcc_xo_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mmss_gp1_clk_src = {
.cmd_rcgr = 0x3450,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_map,
.freq_tbl = ftbl_mmss_gp0_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_gp1_clk_src",
.parent_data = mmcc_xo_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x3500,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
.freq_tbl = ftbl_jpeg0_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg_dma_clk_src = {
.cmd_rcgr = 0x3560,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
.freq_tbl = ftbl_jpeg0_1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg_dma_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(8000000, P_GPLL0, 15, 1, 5),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_MMPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_MMPLL0, 5, 1, 5),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(64000000, P_MMPLL0, 12.5, 0, 0),
{ }
};
static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_MMPLL4, 10, 1, 16),
F(8000000, P_MMPLL4, 10, 1, 12),
F(9600000, P_XO, 2, 0, 0),
F(12000000, P_MMPLL4, 10, 1, 8),
F(16000000, P_MMPLL4, 10, 1, 6),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_MMPLL4, 10, 1, 4),
F(32000000, P_MMPLL4, 10, 1, 3),
F(48000000, P_MMPLL4, 10, 1, 2),
F(64000000, P_MMPLL4, 15, 0, 0),
{ }
};
static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_MMPLL4, 10, 1, 16),
F(8000000, P_MMPLL4, 10, 1, 12),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_MMPLL4, 10, 1, 6),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_MMPLL4, 10, 1, 4),
F(32000000, P_MMPLL4, 10, 1, 3),
F(48000000, P_MMPLL4, 10, 1, 2),
F(64000000, P_MMPLL4, 15, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x3360,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x3390,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x33c0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x33f0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi0_1phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x3030,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_mmpll0_map,
.freq_tbl = ftbl_csi0_1phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = mmcc_xo_gpll0_mmpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x2120,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x2140,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x2160,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x2180,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = mmcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
static struct clk_rcg2 extpclk_clk_src = {
.cmd_rcgr = 0x2060,
.hid_width = 5,
.parent_map = mmss_xo_hdmi_map,
.freq_tbl = extpclk_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
.parent_data = mmss_xo_hdmi,
.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_hdmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hdmi_clk_src = {
.cmd_rcgr = 0x2100,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_map,
.freq_tbl = ftbl_hdmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
.parent_data = mmcc_xo_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x2080,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_map,
.freq_tbl = ftbl_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = mmcc_xo_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 rbbmtimer_clk_src = {
.cmd_rcgr = 0x4090,
.hid_width = 5,
.parent_map = mmcc_xo_gpll0_map,
.freq_tbl = ftbl_rbbmtimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_data = mmcc_xo_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch camss_ahb_clk = {
.halt_reg = 0x348c,
.clkr = {
.enable_reg = 0x348c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_cci_ahb_clk = {
.halt_reg = 0x3348,
.clkr = {
.enable_reg = 0x3348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_cci_clk = {
.halt_reg = 0x3344,
.clkr = {
.enable_reg = 0x3344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_clk",
.parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_ahb_clk = {
.halt_reg = 0x36b4,
.clkr = {
.enable_reg = 0x36b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_axi_clk = {
.halt_reg = 0x36c4,
.clkr = {
.enable_reg = 0x36c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_clk = {
.halt_reg = 0x36b0,
.clkr = {
.enable_reg = 0x36b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_clk",
.parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_ahb_clk = {
.halt_reg = 0x30bc,
.clkr = {
.enable_reg = 0x30bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_clk = {
.halt_reg = 0x30b4,
.clkr = {
.enable_reg = 0x30b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0phy_clk = {
.halt_reg = 0x30c4,
.clkr = {
.enable_reg = 0x30c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phy_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0pix_clk = {
.halt_reg = 0x30e4,
.clkr = {
.enable_reg = 0x30e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0rdi_clk = {
.halt_reg = 0x30d4,
.clkr = {
.enable_reg = 0x30d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_ahb_clk = {
.halt_reg = 0x3128,
.clkr = {
.enable_reg = 0x3128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_clk = {
.halt_reg = 0x3124,
.clkr = {
.enable_reg = 0x3124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1phy_clk = {
.halt_reg = 0x3134,
.clkr = {
.enable_reg = 0x3134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phy_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1pix_clk = {
.halt_reg = 0x3154,
.clkr = {
.enable_reg = 0x3154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1rdi_clk = {
.halt_reg = 0x3144,
.clkr = {
.enable_reg = 0x3144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_ahb_clk = {
.halt_reg = 0x3188,
.clkr = {
.enable_reg = 0x3188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_clk = {
.halt_reg = 0x3184,
.clkr = {
.enable_reg = 0x3184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2phy_clk = {
.halt_reg = 0x3194,
.clkr = {
.enable_reg = 0x3194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phy_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2pix_clk = {
.halt_reg = 0x31b4,
.clkr = {
.enable_reg = 0x31b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2rdi_clk = {
.halt_reg = 0x31a4,
.clkr = {
.enable_reg = 0x31a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_ahb_clk = {
.halt_reg = 0x31e8,
.clkr = {
.enable_reg = 0x31e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_clk = {
.halt_reg = 0x31e4,
.clkr = {
.enable_reg = 0x31e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3phy_clk = {
.halt_reg = 0x31f4,
.clkr = {
.enable_reg = 0x31f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3phy_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3pix_clk = {
.halt_reg = 0x3214,
.clkr = {
.enable_reg = 0x3214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3rdi_clk = {
.halt_reg = 0x3204,
.clkr = {
.enable_reg = 0x3204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe0_clk = {
.halt_reg = 0x3704,
.clkr = {
.enable_reg = 0x3704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe1_clk = {
.halt_reg = 0x3714,
.clkr = {
.enable_reg = 0x3714,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp0_clk = {
.halt_reg = 0x3444,
.clkr = {
.enable_reg = 0x3444,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
.parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp1_clk = {
.halt_reg = 0x3474,
.clkr = {
.enable_reg = 0x3474,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
.parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ispif_ahb_clk = {
.halt_reg = 0x3224,
.clkr = {
.enable_reg = 0x3224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_dma_clk = {
.halt_reg = 0x35c0,
.clkr = {
.enable_reg = 0x35c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_dma_clk",
.parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg0_clk = {
.halt_reg = 0x35a8,
.clkr = {
.enable_reg = 0x35a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg0_clk",
.parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg1_clk = {
.halt_reg = 0x35ac,
.clkr = {
.enable_reg = 0x35ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg1_clk",
.parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg2_clk = {
.halt_reg = 0x35b0,
.clkr = {
.enable_reg = 0x35b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg2_clk",
.parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
.clkr = {
.enable_reg = 0x35b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_axi_clk = {
.halt_reg = 0x35b8,
.clkr = {
.enable_reg = 0x35b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk0_clk = {
.halt_reg = 0x3384,
.clkr = {
.enable_reg = 0x3384,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk1_clk = {
.halt_reg = 0x33b4,
.clkr = {
.enable_reg = 0x33b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk2_clk = {
.halt_reg = 0x33e4,
.clkr = {
.enable_reg = 0x33e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk3_clk = {
.halt_reg = 0x3414,
.clkr = {
.enable_reg = 0x3414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_micro_ahb_clk = {
.halt_reg = 0x3494,
.clkr = {
.enable_reg = 0x3494,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy0_csi0phytimer_clk = {
.halt_reg = 0x3024,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy0_csi0phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy1_csi1phytimer_clk = {
.halt_reg = 0x3054,
.clkr = {
.enable_reg = 0x3054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy1_csi1phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy2_csi2phytimer_clk = {
.halt_reg = 0x3084,
.clkr = {
.enable_reg = 0x3084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy2_csi2phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_top_ahb_clk = {
.halt_reg = 0x3484,
.clkr = {
.enable_reg = 0x3484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe0_clk = {
.halt_reg = 0x36a8,
.clkr = {
.enable_reg = 0x36a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe0_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe1_clk = {
.halt_reg = 0x36ac,
.clkr = {
.enable_reg = 0x36ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe1_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_ahb_clk = {
.halt_reg = 0x36b8,
.clkr = {
.enable_reg = 0x36b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_axi_clk = {
.halt_reg = 0x36bc,
.clkr = {
.enable_reg = 0x36bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_ahb_clk = {
.halt_reg = 0x3b74,
.clkr = {
.enable_reg = 0x3b74,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_axi_clk = {
.halt_reg = 0x3b70,
.clkr = {
.enable_reg = 0x3b70,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_core_clk = {
.halt_reg = 0x3b68,
.clkr = {
.enable_reg = 0x3b68,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_core_clk",
.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch fd_core_uar_clk = {
.halt_reg = 0x3b6c,
.clkr = {
.enable_reg = 0x3b6c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_core_uar_clk",
.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_axi_clk = {
.halt_reg = 0x2310,
.clkr = {
.enable_reg = 0x2310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte0_clk = {
.halt_reg = 0x233c,
.clkr = {
.enable_reg = 0x233c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte1_clk = {
.halt_reg = 0x2340,
.clkr = {
.enable_reg = 0x2340,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc0_clk = {
.halt_reg = 0x2344,
.clkr = {
.enable_reg = 0x2344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
.parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc1_clk = {
.halt_reg = 0x2348,
.clkr = {
.enable_reg = 0x2348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
.parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_extpclk_clk = {
.halt_reg = 0x2324,
.clkr = {
.enable_reg = 0x2324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
.parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_ahb_clk = {
.halt_reg = 0x230c,
.clkr = {
.enable_reg = 0x230c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_clk = {
.halt_reg = 0x2338,
.clkr = {
.enable_reg = 0x2338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
.parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_clk = {
.halt_reg = 0x231c,
.clkr = {
.enable_reg = 0x231c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk0_clk = {
.halt_reg = 0x2314,
.clkr = {
.enable_reg = 0x2314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
.parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk1_clk = {
.halt_reg = 0x2318,
.clkr = {
.enable_reg = 0x2318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
.parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_vsync_clk = {
.halt_reg = 0x2328,
.clkr = {
.enable_reg = 0x2328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
.parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_misc_ahb_clk = {
.halt_reg = 0x502c,
.clkr = {
.enable_reg = 0x502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_mmssnoc_axi_clk = {
.halt_reg = 0x506c,
.clkr = {
.enable_reg = 0x506c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
/* Gating this clock will wreck havoc among MMSS! */
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_s0_axi_clk = {
.halt_reg = 0x5064,
.clkr = {
.enable_reg = 0x5064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_s0_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ocmemcx_ocmemnoc_clk = {
.halt_reg = 0x4058,
.clkr = {
.enable_reg = 0x4058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ocmemnoc_clk",
.parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxili_gfx3d_clk = {
.halt_reg = 0x4028,
.clkr = {
.enable_reg = 0x4028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_gfx3d_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "oxili_gfx3d_clk_src",
.name = "oxili_gfx3d_clk_src"
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxili_rbbmtimer_clk = {
.halt_reg = 0x40b0,
.clkr = {
.enable_reg = 0x40b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_rbbmtimer_clk",
.parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxilicx_ahb_clk = {
.halt_reg = 0x403c,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxilicx_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_ahb_clk = {
.halt_reg = 0x1030,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_axi_clk = {
.halt_reg = 0x1034,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_ocmemnoc_clk = {
.halt_reg = 0x1038,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ocmemnoc_clk",
.parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_vcodec0_clk = {
.halt_reg = 0x1028,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_core0_vcodec_clk = {
.halt_reg = 0x1048,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core0_vcodec_clk",
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_core1_vcodec_clk = {
.halt_reg = 0x104c,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core1_vcodec_clk",
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_core2_vcodec_clk = {
.halt_reg = 0x1054,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core2_vcodec_clk",
.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x1024,
.cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
.cxc_count = 3,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x1040,
.cxcs = (unsigned int []){ 0x1048 },
.cxc_count = 1,
.pd = {
.name = "venus_core0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc venus_core1_gdsc = {
.gdscr = 0x1044,
.cxcs = (unsigned int []){ 0x104c },
.cxc_count = 1,
.pd = {
.name = "venus_core1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc venus_core2_gdsc = {
.gdscr = 0x1050,
.cxcs = (unsigned int []){ 0x1054 },
.cxc_count = 1,
.pd = {
.name = "venus_core2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x2304,
.cxcs = (unsigned int []){ 0x2310, 0x231c },
.cxc_count = 2,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_top_gdsc = {
.gdscr = 0x34a0,
.cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
.cxc_count = 3,
.pd = {
.name = "camss_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x35a4,
.cxcs = (unsigned int []){ 0x35a8 },
.cxc_count = 1,
.pd = {
.name = "jpeg_gdsc",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe_gdsc = {
.gdscr = 0x36a4,
.cxcs = (unsigned int []){ 0x36bc },
.cxc_count = 1,
.pd = {
.name = "vfe_gdsc",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc cpp_gdsc = {
.gdscr = 0x36d4,
.cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
.cxc_count = 2,
.pd = {
.name = "cpp_gdsc",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc fd_gdsc = {
.gdscr = 0x3b64,
.cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
.pd = {
.name = "fd_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_cx_gdsc = {
.gdscr = 0x4034,
.pd = {
.name = "oxili_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc oxili_gx_gdsc = {
.gdscr = 0x4024,
.cxcs = (unsigned int []){ 0x4028 },
.cxc_count = 1,
.pd = {
.name = "oxili_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &oxili_cx_gdsc.pd,
.flags = CLAMP_IO,
.supply = "VDD_GFX",
};
static struct clk_regmap *mmcc_msm8994_clocks[] = {
[MMPLL0_EARLY] = &mmpll0_early.clkr,
[MMPLL0_PLL] = &mmpll0.clkr,
[MMPLL1_EARLY] = &mmpll1_early.clkr,
[MMPLL1_PLL] = &mmpll1.clkr,
[MMPLL3_EARLY] = &mmpll3_early.clkr,
[MMPLL3_PLL] = &mmpll3.clkr,
[MMPLL4_EARLY] = &mmpll4_early.clkr,
[MMPLL4_PLL] = &mmpll4.clkr,
[MMPLL5_EARLY] = &mmpll5_early.clkr,
[MMPLL5_PLL] = &mmpll5.clkr,
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
[AXI_CLK_SRC] = &axi_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
[MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
[JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
[CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
[CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
[CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
[CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
[CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
[FD_AHB_CLK] = &fd_ahb_clk.clkr,
[FD_AXI_CLK] = &fd_axi_clk.clkr,
[FD_CORE_CLK] = &fd_core_clk.clkr,
[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
[OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
[VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
[VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
[VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
[VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
};
static struct gdsc *mmcc_msm8994_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
[VENUS_CORE2_GDSC] = &venus_core2_gdsc,
[CAMSS_TOP_GDSC] = &camss_top_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[VFE_GDSC] = &vfe_gdsc,
[CPP_GDSC] = &cpp_gdsc,
[OXILI_GX_GDSC] = &oxili_gx_gdsc,
[OXILI_CX_GDSC] = &oxili_cx_gdsc,
[FD_GDSC] = &fd_gdsc,
};
static const struct qcom_reset_map mmcc_msm8994_resets[] = {
[CAMSS_MICRO_BCR] = { 0x3490 },
};
static const struct regmap_config mmcc_msm8994_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5200,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_msm8994_desc = {
.config = &mmcc_msm8994_regmap_config,
.clks = mmcc_msm8994_clocks,
.num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
.resets = mmcc_msm8994_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
.gdscs = mmcc_msm8994_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
};
static const struct of_device_id mmcc_msm8994_match_table[] = {
{ .compatible = "qcom,mmcc-msm8992" },
{ .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
static int mmcc_msm8994_probe(struct platform_device *pdev)
{
struct regmap *regmap;
if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) {
/* MSM8992 features less clocks and some have different freq tables */
mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL;
mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL;
mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL;
mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL;
mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL;
mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL;
mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL;
mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL;
mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL;
mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL;
mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL;
mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL;
axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992;
cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992;
csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992;
mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992;
ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992;
vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992;
vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
}
regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
}
static struct platform_driver mmcc_msm8994_driver = {
.probe = mmcc_msm8994_probe,
.driver = {
.name = "mmcc-msm8994",
.of_match_table = mmcc_msm8994_match_table,
},
};
module_platform_driver(mmcc_msm8994_driver);
MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mmcc-msm8994");
| linux-master | drivers/clk/qcom/mmcc-msm8994.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2020-2021, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
P_PCIE_1_PIPE_CLK,
P_SLEEP_CLK,
P_UFS_CARD_RX_SYMBOL_0_CLK,
P_UFS_CARD_RX_SYMBOL_1_CLK,
P_UFS_CARD_TX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x1c000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .fw_name = "ufs_card_rx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "ufs_card_rx_symbol_1_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .fw_name = "ufs_card_tx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b054,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d054,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
.reg = 0x75058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
.reg = 0x750c8,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_8,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
.reg = 0x75048,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_9,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x77058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770c8,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x77048,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0xf060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_13,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
.reg = 0x10060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_14,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b058,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0x6b03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d058,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x8d03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x17270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x173a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x174d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17730,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17860,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e3a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e4d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x75024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x7506c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x750a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x75084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x7706c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x10020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x10038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x10064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0xf050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.reg = 0x10050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
.halt_reg = 0x6b080,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
.halt_reg = 0x8d084,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x9000c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9000c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x750cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x750cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x750cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x750cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750cc,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0xf080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xf080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x10080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x10080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x26014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0xf07c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xf07c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x1007c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1007c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1007c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
.halt_reg = 0x8d080,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_pcie_sf_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0x27014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x27014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_en = {
.halt_reg = 0x8c014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7100c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_rchng_clk = {
.halt_reg = 0x6b038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_rchng_clk = {
.halt_reg = 0x8d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x8c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_clkref_en = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x2800c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2800c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1713c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1726c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1739c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x174cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x175fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x1772c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x1785c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x23140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x23138,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x1813c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x1826c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x1839c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x185fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x23278,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x23270,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e13c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e26c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e39c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e4cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e5fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_throttle_pcie_ahb_clk = {
.halt_reg = 0x9044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_throttle_pcie_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_1_clkref_en = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_1_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x75064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
.halt_reg = 0x75064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75064,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x7509c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7509c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7509c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
.halt_reg = 0x7509c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7509c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7509c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_reg = 0x75020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x75020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_reg = 0x750b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x750b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_reg = 0x7501c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x77064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77064,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x7709c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7709c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7709c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x7709c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7709c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7709c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x77020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk__force_mem_core_on",
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk__force_mem_core_on",
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x1001c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1001c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0xf05c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xf05c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf05c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_clkref_en = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x10054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x10058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Clock ON depends on external parent clock, so don't poll */
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x1005c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1005c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x28010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
/* external clocks so add BRANCH_HALT_SKIP */
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x28018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d050,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0x7d058,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
.gdscr = 0x7d054,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
.gdscr = 0x7d06c,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sm8350_clocks[] = {
[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
[GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
&gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
&gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
};
static struct gdsc *gcc_sm8350_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
};
static const struct qcom_reset_map gcc_sm8350_resets[] = {
[GCC_CAMERA_BCR] = { 0x26000 },
[GCC_DISPLAY_BCR] = { 0x27000 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
[GCC_VIDEO_BCR] = { 0x28000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
};
static const struct regmap_config gcc_sm8350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9c100,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm8350_desc = {
.config = &gcc_sm8350_regmap_config,
.clks = gcc_sm8350_clocks,
.num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
.resets = gcc_sm8350_resets,
.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
.gdscs = gcc_sm8350_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
};
static const struct of_device_id gcc_sm8350_match_table[] = {
{ .compatible = "qcom,gcc-sm8350" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
static int gcc_sm8350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to map gcc registers\n");
return PTR_ERR(regmap);
}
/*
* Keep the critical clock always-On
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
* GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
}
static struct platform_driver gcc_sm8350_driver = {
.probe = gcc_sm8350_probe,
.driver = {
.name = "sm8350-gcc",
.of_match_table = gcc_sm8350_match_table,
},
};
static int __init gcc_sm8350_init(void)
{
return platform_driver_register(&gcc_sm8350_driver);
}
subsys_initcall(gcc_sm8350_init);
static void __exit gcc_sm8350_exit(void)
{
platform_driver_unregister(&gcc_sm8350_driver);
}
module_exit(gcc_sm8350_exit);
MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sm8350.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/reset/qcom,gcc-apq8084.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL1,
P_GPLL4,
P_PCIE_0_1_PIPE_CLK,
P_SATA_ASIC0_CLK,
P_SATA_RX_CLK,
P_SLEEP_CLK,
};
static struct clk_pll gpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
.n_reg = 0x000c,
.config_reg = 0x0014,
.mode_reg = 0x0000,
.status_reg = 0x001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x0044,
.m_reg = 0x0048,
.n_reg = 0x004c,
.config_reg = 0x0054,
.mode_reg = 0x0040,
.status_reg = 0x005c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x1480,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll4 = {
.l_reg = 0x1dc4,
.m_reg = 0x1dc8,
.n_reg = 0x1dcc,
.config_reg = 0x1dd4,
.mode_reg = 0x1dc0,
.status_reg = 0x1ddc,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll4_vote = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll4_vote.hw },
};
static const struct parent_map gcc_xo_sata_asic0_map[] = {
{ P_XO, 0 },
{ P_SATA_ASIC0_CLK, 2 }
};
static const struct clk_parent_data gcc_xo_sata_asic0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "sata_asic0_clk", .name = "sata_asic0_clk" },
};
static const struct parent_map gcc_xo_sata_rx_map[] = {
{ P_XO, 0 },
{ P_SATA_RX_CLK, 2}
};
static const struct clk_parent_data gcc_xo_sata_rx[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "sata_rx_clk", .name = "sata_rx_clk" },
};
static const struct parent_map gcc_xo_pcie_map[] = {
{ P_XO, 0 },
{ P_PCIE_0_1_PIPE_CLK, 2 }
};
static const struct clk_parent_data gcc_xo_pcie[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "pcie_pipe", .name = "pcie_pipe" },
};
static const struct parent_map gcc_xo_pcie_sleep_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_pcie_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 config_noc_clk_src = {
.cmd_rcgr = 0x0150,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "config_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 periph_noc_clk_src = {
.cmd_rcgr = 0x0190,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "periph_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 system_noc_clk_src = {
.cmd_rcgr = 0x0120,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 ufs_axi_clk_src = {
.cmd_rcgr = 0x1d64,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_ufs_axi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
F(125000000, P_GPLL0, 1, 5, 24),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x03d4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb30_master_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
F(125000000, P_GPLL0, 1, 5, 24),
{ }
};
static struct clk_rcg2 usb30_sec_master_clk_src = {
.cmd_rcgr = 0x1bd4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb30_sec_master_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_sec_master_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
F(125000000, P_GPLL0, 1, 5, 24),
{ }
};
static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x1be8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x1bd0,
.clkr = {
.enable_reg = 0x1bd0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x1bcc,
.clkr = {
.enable_reg = 0x1bcc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0660,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x064c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x06e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x06cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0760,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x074c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x07e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x07cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x0860,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x084c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x08e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x08cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
F(3686400, P_GPLL0, 1, 96, 15625),
F(7372800, P_GPLL0, 1, 192, 15625),
F(14745600, P_GPLL0, 1, 384, 15625),
F(16000000, P_GPLL0, 5, 2, 15),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_GPLL0, 1, 4, 75),
F(40000000, P_GPLL0, 15, 0, 0),
F(46400000, P_GPLL0, 1, 29, 375),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(51200000, P_GPLL0, 1, 32, 375),
F(56000000, P_GPLL0, 1, 7, 75),
F(58982400, P_GPLL0, 1, 1536, 15625),
F(60000000, P_GPLL0, 10, 0, 0),
F(63160000, P_GPLL0, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x068c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x070c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x078c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x080c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x088c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x090c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x09a0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x098c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x0a20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x0a0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0aa0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x0a8c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x0b20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x0b0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x0ba0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x0b8c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x0c20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x0c0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x09cc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x0a4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.cmd_rcgr = 0x0acc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.cmd_rcgr = 0x0b4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.cmd_rcgr = 0x0bcc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.cmd_rcgr = 0x0c4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(85710000, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 ce1_clk_src = {
.cmd_rcgr = 0x1050,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_ce1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce1_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(85710000, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 ce2_clk_src = {
.cmd_rcgr = 0x1090,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_ce2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(85710000, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 ce3_clk_src = {
.cmd_rcgr = 0x1d10,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_ce3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce3_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x1904,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x1944,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x1984,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
F(1010000, P_XO, 1, 1, 19),
{ }
};
static struct clk_rcg2 pcie_0_aux_clk_src = {
.cmd_rcgr = 0x1b2c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_pcie_sleep_map,
.freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
.parent_data = gcc_xo_pcie_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pcie_1_aux_clk_src = {
.cmd_rcgr = 0x1bac,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_pcie_sleep_map,
.freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_aux_clk_src",
.parent_data = gcc_xo_pcie_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 pcie_0_pipe_clk_src = {
.cmd_rcgr = 0x1b18,
.hid_width = 5,
.parent_map = gcc_xo_pcie_map,
.freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
.parent_data = gcc_xo_pcie,
.num_parents = ARRAY_SIZE(gcc_xo_pcie),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pcie_1_pipe_clk_src = {
.cmd_rcgr = 0x1b98,
.hid_width = 5,
.parent_map = gcc_xo_pcie_map,
.freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_pipe_clk_src",
.parent_data = gcc_xo_pcie,
.num_parents = ARRAY_SIZE(gcc_xo_pcie),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x0cd0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 sata_asic0_clk_src = {
.cmd_rcgr = 0x1c94,
.hid_width = 5,
.parent_map = gcc_xo_sata_asic0_map,
.freq_tbl = ftbl_gcc_sata_asic0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_asic0_clk_src",
.parent_data = gcc_xo_sata_asic0,
.num_parents = ARRAY_SIZE(gcc_xo_sata_asic0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 sata_pmalive_clk_src = {
.cmd_rcgr = 0x1c80,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sata_pmalive_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
F(75000000, P_SATA_RX_CLK, 1, 0, 0),
F(150000000, P_SATA_RX_CLK, 1, 0, 0),
F(300000000, P_SATA_RX_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 sata_rx_clk_src = {
.cmd_rcgr = 0x1ca8,
.hid_width = 5,
.parent_map = gcc_xo_sata_rx_map,
.freq_tbl = ftbl_gcc_sata_rx_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_rx_clk_src",
.parent_data = gcc_xo_sata_rx,
.num_parents = ARRAY_SIZE(gcc_xo_sata_rx),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 sata_rx_oob_clk_src = {
.cmd_rcgr = 0x1c5c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sata_rx_oob_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sata_rx_oob_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(192000000, P_GPLL4, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(384000000, P_GPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x04d0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x0510,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc3_apps_clk_src = {
.cmd_rcgr = 0x0550,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc4_apps_clk_src = {
.cmd_rcgr = 0x0590,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
F(105000, P_XO, 2, 1, 91),
{ }
};
static struct clk_rcg2 tsif_ref_clk_src = {
.cmd_rcgr = 0x0d90,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_tsif_ref_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x03e8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x0490,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
F(480000000, P_GPLL1, 1, 0, 0),
{ }
};
static const struct parent_map usb_hsic_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 4 }
};
static struct clk_rcg2 usb_hsic_clk_src = {
.cmd_rcgr = 0x0440,
.hid_width = 5,
.parent_map = usb_hsic_clk_src_map,
.freq_tbl = ftbl_gcc_usb_hsic_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_clk_src",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll1_vote.hw },
},
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
F(60000000, P_GPLL1, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_ahb_clk_src = {
.cmd_rcgr = 0x046c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = usb_hsic_clk_src_map,
.freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_ahb_clk_src",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll1_vote.hw },
},
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
F(9600000, P_XO, 2, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
.cmd_rcgr = 0x0458,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_io_cal_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
.cmd_rcgr = 0x1f00,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
.halt_reg = 0x1f14,
.clkr = {
.enable_reg = 0x1f14,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_system_clk_src = {
.cmd_rcgr = 0x041c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hsic_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap gcc_mmss_gpll0_clk_src = {
.enable_reg = 0x1484,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "mmss_gpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll0_vote.hw,
},
.num_parents = 1,
.ops = &clk_branch_simple_ops,
},
};
static struct clk_branch gcc_bam_dma_ahb_clk = {
.halt_reg = 0x0d44,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_bam_dma_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x05c4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x0648,
.clkr = {
.enable_reg = 0x0648,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x0644,
.clkr = {
.enable_reg = 0x0644,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x06c8,
.clkr = {
.enable_reg = 0x06c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x06c4,
.clkr = {
.enable_reg = 0x06c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x0748,
.clkr = {
.enable_reg = 0x0748,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0744,
.clkr = {
.enable_reg = 0x0744,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x07c8,
.clkr = {
.enable_reg = 0x07c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x07c4,
.clkr = {
.enable_reg = 0x07c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x0848,
.clkr = {
.enable_reg = 0x0848,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0844,
.clkr = {
.enable_reg = 0x0844,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x08c8,
.clkr = {
.enable_reg = 0x08c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x08c4,
.clkr = {
.enable_reg = 0x08c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0684,
.clkr = {
.enable_reg = 0x0684,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0704,
.clkr = {
.enable_reg = 0x0704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x0784,
.clkr = {
.enable_reg = 0x0784,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x0804,
.clkr = {
.enable_reg = 0x0804,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x0884,
.clkr = {
.enable_reg = 0x0884,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x0904,
.clkr = {
.enable_reg = 0x0904,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x0944,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x0988,
.clkr = {
.enable_reg = 0x0988,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x0984,
.clkr = {
.enable_reg = 0x0984,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x0a08,
.clkr = {
.enable_reg = 0x0a08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x0a04,
.clkr = {
.enable_reg = 0x0a04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x0a88,
.clkr = {
.enable_reg = 0x0a88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x0a84,
.clkr = {
.enable_reg = 0x0a84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x0b08,
.clkr = {
.enable_reg = 0x0b08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x0b04,
.clkr = {
.enable_reg = 0x0b04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.halt_reg = 0x0b88,
.clkr = {
.enable_reg = 0x0b88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.halt_reg = 0x0b84,
.clkr = {
.enable_reg = 0x0b84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.halt_reg = 0x0c08,
.clkr = {
.enable_reg = 0x0c08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.halt_reg = 0x0c04,
.clkr = {
.enable_reg = 0x0c04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x09c4,
.clkr = {
.enable_reg = 0x09c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x0a44,
.clkr = {
.enable_reg = 0x0a44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.halt_reg = 0x0ac4,
.clkr = {
.enable_reg = 0x0ac4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart4_apps_clk = {
.halt_reg = 0x0b44,
.clkr = {
.enable_reg = 0x0b44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart5_apps_clk = {
.halt_reg = 0x0bc4,
.clkr = {
.enable_reg = 0x0bc4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart6_apps_clk = {
.halt_reg = 0x0c44,
.clkr = {
.enable_reg = 0x0c44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x0e04,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x104c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x1048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x1050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.parent_hws = (const struct clk_hw*[]){
&ce1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce2_ahb_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce2_axi_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce2_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_clk",
.parent_hws = (const struct clk_hw*[]){
&ce2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce3_ahb_clk = {
.halt_reg = 0x1d0c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1d0c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce3_axi_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1d08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce3_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce3_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1d04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce3_clk",
.parent_hws = (const struct clk_hw*[]){
&ce3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x1900,
.clkr = {
.enable_reg = 0x1900,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x1940,
.clkr = {
.enable_reg = 0x1940,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x1980,
.clkr = {
.enable_reg = 0x1980,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
.halt_reg = 0x0248,
.clkr = {
.enable_reg = 0x0248,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ocmem_noc_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x1b10,
.clkr = {
.enable_reg = 0x1b10,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x1b0c,
.clkr = {
.enable_reg = 0x1b0c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x1b08,
.clkr = {
.enable_reg = 0x1b08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x1b14,
.clkr = {
.enable_reg = 0x1b14,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x1b04,
.clkr = {
.enable_reg = 0x1b04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x1b90,
.clkr = {
.enable_reg = 0x1b90,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x1b8c,
.clkr = {
.enable_reg = 0x1b8c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x1b88,
.clkr = {
.enable_reg = 0x1b88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x1b94,
.clkr = {
.enable_reg = 0x1b94,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x1b84,
.clkr = {
.enable_reg = 0x1b84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x0ccc,
.clkr = {
.enable_reg = 0x0ccc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x0cc4,
.clkr = {
.enable_reg = 0x0cc4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
.halt_reg = 0x01a4,
.clkr = {
.enable_reg = 0x01a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_periph_noc_usb_hsic_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x0d04,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sata_asic0_clk = {
.halt_reg = 0x1c54,
.clkr = {
.enable_reg = 0x1c54,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_asic0_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_asic0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sata_axi_clk = {
.halt_reg = 0x1c44,
.clkr = {
.enable_reg = 0x1c44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sata_cfg_ahb_clk = {
.halt_reg = 0x1c48,
.clkr = {
.enable_reg = 0x1c48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sata_pmalive_clk = {
.halt_reg = 0x1c50,
.clkr = {
.enable_reg = 0x1c50,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_pmalive_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_pmalive_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sata_rx_clk = {
.halt_reg = 0x1c58,
.clkr = {
.enable_reg = 0x1c58,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sata_rx_oob_clk = {
.halt_reg = 0x1c4c,
.clkr = {
.enable_reg = 0x1c4c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sata_rx_oob_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_rx_oob_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x04c8,
.clkr = {
.enable_reg = 0x04c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x04c4,
.clkr = {
.enable_reg = 0x04c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
.halt_reg = 0x04e8,
.clkr = {
.enable_reg = 0x04e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_cdccal_ff_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" }
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
.halt_reg = 0x04e4,
.clkr = {
.enable_reg = 0x04e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_cdccal_sleep_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "sleep_clk", .name = "sleep_clk" }
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x0508,
.clkr = {
.enable_reg = 0x0508,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x0504,
.clkr = {
.enable_reg = 0x0504,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_ahb_clk = {
.halt_reg = 0x0548,
.clkr = {
.enable_reg = 0x0548,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_apps_clk = {
.halt_reg = 0x0544,
.clkr = {
.enable_reg = 0x0544,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x0588,
.clkr = {
.enable_reg = 0x0588,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x0584,
.clkr = {
.enable_reg = 0x0584,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
.halt_reg = 0x013c,
.clkr = {
.enable_reg = 0x013c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
.halt_reg = 0x0108,
.clkr = {
.enable_reg = 0x0108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
.halt_reg = 0x0138,
.clkr = {
.enable_reg = 0x0138,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x0d84,
.clkr = {
.enable_reg = 0x0d84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x0d8c,
.clkr = {
.enable_reg = 0x0d8c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x0d88,
.clkr = {
.enable_reg = 0x0d88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ahb_clk = {
.halt_reg = 0x1d48,
.clkr = {
.enable_reg = 0x1d48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_axi_clk = {
.halt_reg = 0x1d44,
.clkr = {
.enable_reg = 0x1d44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_cfg_clk = {
.halt_reg = 0x1d50,
.clkr = {
.enable_reg = 0x1d50,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_cfg_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.halt_reg = 0x1d5c,
.clkr = {
.enable_reg = 0x1d5c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.halt_reg = 0x1d60,
.clkr = {
.enable_reg = 0x1d60,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_cfg_clk = {
.halt_reg = 0x1d4c,
.clkr = {
.enable_reg = 0x1d4c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_cfg_clk",
.parent_hws = (const struct clk_hw*[]){
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.halt_reg = 0x1d54,
.clkr = {
.enable_reg = 0x1d54,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
.halt_reg = 0x1d58,
.clkr = {
.enable_reg = 0x1d58,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_1_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "ufs_tx_symbol_1_clk_src", .name = "ufs_tx_symbol_1_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x04ac,
.clkr = {
.enable_reg = 0x04ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2b_phy_sleep_clk = {
.halt_reg = 0x04b4,
.clkr = {
.enable_reg = 0x04b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2b_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x03c8,
.clkr = {
.enable_reg = 0x03c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x1bc8,
.clkr = {
.enable_reg = 0x1bc8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x03d0,
.clkr = {
.enable_reg = 0x03d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x03cc,
.clkr = {
.enable_reg = 0x03cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x0488,
.clkr = {
.enable_reg = 0x0488,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
.halt_reg = 0x048c,
.clkr = {
.enable_reg = 0x048c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_inactivity_timers_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x0484,
.clkr = {
.enable_reg = 0x0484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_ahb_clk = {
.halt_reg = 0x0408,
.clkr = {
.enable_reg = 0x0408,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_clk = {
.halt_reg = 0x0410,
.clkr = {
.enable_reg = 0x0410,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_io_cal_clk = {
.halt_reg = 0x0414,
.clkr = {
.enable_reg = 0x0414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_io_cal_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_io_cal_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
.halt_reg = 0x0418,
.clkr = {
.enable_reg = 0x0418,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_io_cal_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_system_clk = {
.halt_reg = 0x040c,
.clkr = {
.enable_reg = 0x040c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb_hs_hsic_gdsc = {
.gdscr = 0x404,
.pd = {
.name = "usb_hs_hsic",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie0_gdsc = {
.gdscr = 0x1ac4,
.pd = {
.name = "pcie0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie1_gdsc = {
.gdscr = 0x1b44,
.pd = {
.name = "pcie1",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_gdsc = {
.gdscr = 0x1e84,
.pd = {
.name = "usb30",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_apq8084_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[GPLL4] = &gpll4.clkr,
[GPLL4_VOTE] = &gpll4_vote,
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
[USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
[CE1_CLK_SRC] = &ce1_clk_src.clkr,
[CE2_CLK_SRC] = &ce2_clk_src.clkr,
[CE3_CLK_SRC] = &ce3_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
[PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
[PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
[PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
[SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
[SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
[SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
[USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
[GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
[GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
[GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
[GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
[GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
[GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
[GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
[GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
[GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
[GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
[GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
[GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
[GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
[GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
[GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
[GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
};
static struct gdsc *gcc_apq8084_gdscs[] = {
[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
[PCIE0_GDSC] = &pcie0_gdsc,
[PCIE1_GDSC] = &pcie1_gdsc,
[USB30_GDSC] = &usb30_gdsc,
};
static const struct qcom_reset_map gcc_apq8084_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
[GCC_CONFIG_NOC_BCR] = { 0x0140 },
[GCC_PERIPH_NOC_BCR] = { 0x0180 },
[GCC_IMEM_BCR] = { 0x0200 },
[GCC_MMSS_BCR] = { 0x0240 },
[GCC_QDSS_BCR] = { 0x0300 },
[GCC_USB_30_BCR] = { 0x03c0 },
[GCC_USB3_PHY_BCR] = { 0x03fc },
[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
[GCC_USB_HS_BCR] = { 0x0480 },
[GCC_USB2A_PHY_BCR] = { 0x04a8 },
[GCC_USB2B_PHY_BCR] = { 0x04b0 },
[GCC_SDCC1_BCR] = { 0x04c0 },
[GCC_SDCC2_BCR] = { 0x0500 },
[GCC_SDCC3_BCR] = { 0x0540 },
[GCC_SDCC4_BCR] = { 0x0580 },
[GCC_BLSP1_BCR] = { 0x05c0 },
[GCC_BLSP1_QUP1_BCR] = { 0x0640 },
[GCC_BLSP1_UART1_BCR] = { 0x0680 },
[GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
[GCC_BLSP1_UART2_BCR] = { 0x0700 },
[GCC_BLSP1_QUP3_BCR] = { 0x0740 },
[GCC_BLSP1_UART3_BCR] = { 0x0780 },
[GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
[GCC_BLSP1_UART4_BCR] = { 0x0800 },
[GCC_BLSP1_QUP5_BCR] = { 0x0840 },
[GCC_BLSP1_UART5_BCR] = { 0x0880 },
[GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
[GCC_BLSP1_UART6_BCR] = { 0x0900 },
[GCC_BLSP2_BCR] = { 0x0940 },
[GCC_BLSP2_QUP1_BCR] = { 0x0980 },
[GCC_BLSP2_UART1_BCR] = { 0x09c0 },
[GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
[GCC_BLSP2_UART2_BCR] = { 0x0a40 },
[GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
[GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
[GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
[GCC_BLSP2_UART4_BCR] = { 0x0b40 },
[GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
[GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
[GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
[GCC_BLSP2_UART6_BCR] = { 0x0c40 },
[GCC_PDM_BCR] = { 0x0cc0 },
[GCC_PRNG_BCR] = { 0x0d00 },
[GCC_BAM_DMA_BCR] = { 0x0d40 },
[GCC_TSIF_BCR] = { 0x0d80 },
[GCC_TCSR_BCR] = { 0x0dc0 },
[GCC_BOOT_ROM_BCR] = { 0x0e00 },
[GCC_MSG_RAM_BCR] = { 0x0e40 },
[GCC_TLMM_BCR] = { 0x0e80 },
[GCC_MPM_BCR] = { 0x0ec0 },
[GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
[GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
[GCC_SEC_CTRL_BCR] = { 0x0f40 },
[GCC_SPMI_BCR] = { 0x0fc0 },
[GCC_SPDM_BCR] = { 0x1000 },
[GCC_CE1_BCR] = { 0x1040 },
[GCC_CE2_BCR] = { 0x1080 },
[GCC_BIMC_BCR] = { 0x1100 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
[GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
[GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
[GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
[GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
[GCC_DEHR_BCR] = { 0x1300 },
[GCC_RBCPR_BCR] = { 0x1380 },
[GCC_MSS_RESTART] = { 0x1680 },
[GCC_LPASS_RESTART] = { 0x16c0 },
[GCC_WCSS_RESTART] = { 0x1700 },
[GCC_VENUS_RESTART] = { 0x1740 },
[GCC_COPSS_SMMU_BCR] = { 0x1a40 },
[GCC_SPSS_BCR] = { 0x1a80 },
[GCC_PCIE_0_BCR] = { 0x1ac0 },
[GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
[GCC_PCIE_1_BCR] = { 0x1b40 },
[GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
[GCC_USB_30_SEC_BCR] = { 0x1bc0 },
[GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
[GCC_SATA_BCR] = { 0x1c40 },
[GCC_CE3_BCR] = { 0x1d00 },
[GCC_UFS_BCR] = { 0x1d40 },
[GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
};
static const struct regmap_config gcc_apq8084_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1fc0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_apq8084_desc = {
.config = &gcc_apq8084_regmap_config,
.clks = gcc_apq8084_clocks,
.num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
.resets = gcc_apq8084_resets,
.num_resets = ARRAY_SIZE(gcc_apq8084_resets),
.gdscs = gcc_apq8084_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
};
static const struct of_device_id gcc_apq8084_match_table[] = {
{ .compatible = "qcom,gcc-apq8084" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
static int gcc_apq8084_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
if (ret)
return ret;
ret = qcom_cc_register_sleep_clk(dev);
if (ret)
return ret;
return qcom_cc_probe(pdev, &gcc_apq8084_desc);
}
static struct platform_driver gcc_apq8084_driver = {
.probe = gcc_apq8084_probe,
.driver = {
.name = "gcc-apq8084",
.of_match_table = gcc_apq8084_match_table,
},
};
static int __init gcc_apq8084_init(void)
{
return platform_driver_register(&gcc_apq8084_driver);
}
core_initcall(gcc_apq8084_init);
static void __exit gcc_apq8084_exit(void)
{
platform_driver_unregister(&gcc_apq8084_driver);
}
module_exit(gcc_apq8084_exit);
MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-apq8084");
| linux-master | drivers/clk/qcom/gcc-apq8084.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
* Author: Finley Xiao <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rockchip,rv1126-cru.h>
#include "clk.h"
#define RV1126_GMAC_CON 0x460
#define RV1126_GRF_IOFUNC_CON1 0x10264
#define RV1126_GRF_SOC_STATUS0 0x10
#define RV1126_FRAC_MAX_PRATE 1200000000
#define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
enum rv1126_pmu_plls {
gpll,
};
enum rv1126_plls {
apll, dpll, cpll, hpll,
};
static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
{ /* sentinel */ },
};
#define RV1126_DIV_ACLK_CORE_MASK 0xf
#define RV1126_DIV_ACLK_CORE_SHIFT 4
#define RV1126_DIV_PCLK_DBG_MASK 0x7
#define RV1126_DIV_PCLK_DBG_SHIFT 0
#define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
{ \
.reg = RV1126_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
RV1126_DIV_ACLK_CORE_SHIFT) | \
HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
RV1126_DIV_PCLK_DBG_SHIFT), \
}
#define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
{ \
.prate = _prate, \
.divs = { \
RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
RV1126_CPUCLK_RATE(1608000000, 1, 7),
RV1126_CPUCLK_RATE(1584000000, 1, 7),
RV1126_CPUCLK_RATE(1560000000, 1, 7),
RV1126_CPUCLK_RATE(1536000000, 1, 7),
RV1126_CPUCLK_RATE(1512000000, 1, 7),
RV1126_CPUCLK_RATE(1488000000, 1, 5),
RV1126_CPUCLK_RATE(1464000000, 1, 5),
RV1126_CPUCLK_RATE(1440000000, 1, 5),
RV1126_CPUCLK_RATE(1416000000, 1, 5),
RV1126_CPUCLK_RATE(1392000000, 1, 5),
RV1126_CPUCLK_RATE(1368000000, 1, 5),
RV1126_CPUCLK_RATE(1344000000, 1, 5),
RV1126_CPUCLK_RATE(1320000000, 1, 5),
RV1126_CPUCLK_RATE(1296000000, 1, 5),
RV1126_CPUCLK_RATE(1272000000, 1, 5),
RV1126_CPUCLK_RATE(1248000000, 1, 5),
RV1126_CPUCLK_RATE(1224000000, 1, 5),
RV1126_CPUCLK_RATE(1200000000, 1, 5),
RV1126_CPUCLK_RATE(1104000000, 1, 5),
RV1126_CPUCLK_RATE(1008000000, 1, 5),
RV1126_CPUCLK_RATE(912000000, 1, 5),
RV1126_CPUCLK_RATE(816000000, 1, 3),
RV1126_CPUCLK_RATE(696000000, 1, 3),
RV1126_CPUCLK_RATE(600000000, 1, 3),
RV1126_CPUCLK_RATE(408000000, 1, 1),
RV1126_CPUCLK_RATE(312000000, 1, 1),
RV1126_CPUCLK_RATE(216000000, 1, 1),
RV1126_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
.core_reg[0] = RV1126_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 0,
.mux_core_main = 2,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
0, RV1126_PMU_PLL_CON(0),
RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
};
static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0, RV1126_PLL_CON(0),
RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, RV1126_PLL_CON(8),
RV1126_MODE_CON, 2, 1, 0, NULL),
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0, RV1126_PLL_CON(16),
RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
[hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
0, RV1126_PLL_CON(24),
RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
*/
/* PD_PMU */
COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKSEL_CON(13), 0,
RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
&rv1126_rtc32k_fracmux),
COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div",
CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(5), 0,
RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
&rv1126_uart1_fracmux),
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
};
static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RV1126_MODE_CON, 10, 2, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/*
* Clock-Architecture Diagram 3
*/
/* PD_CORE */
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RV1126_CLKGATE_CON(0), 6, GFLAGS),
GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
RV1126_CLKGATE_CON(0), 12, GFLAGS),
GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
RV1126_CLKGATE_CON(0), 10, GFLAGS),
GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
RV1126_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
RV1126_CLKGATE_CON(0), 8, GFLAGS),
/*
* Clock-Architecture Diagram 4
*/
/* PD_BUS */
COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(2), 0, GFLAGS),
GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKGATE_CON(2), 1, GFLAGS),
GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(2), 2, GFLAGS),
GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 13, GFLAGS),
/* aclk_dmac is controlled by sgrf_clkgat_con. */
SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(3), 6, GFLAGS),
GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(3), 7, GFLAGS),
GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(6), 14, GFLAGS),
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 10, GFLAGS),
COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKGATE_CON(4), 7, GFLAGS),
GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 14, GFLAGS),
GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
RV1126_CLKGATE_CON(4), 8, GFLAGS),
GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
RV1126_CLKGATE_CON(4), 9, GFLAGS),
GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
RV1126_CLKGATE_CON(4), 10, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(11), 0,
RV1126_CLKGATE_CON(5), 2, GFLAGS,
&rv1126_uart0_fracmux),
GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
RV1126_CLKGATE_CON(5), 3, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(5), 4, GFLAGS),
COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(5), 5, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(13), 0,
RV1126_CLKGATE_CON(5), 6, GFLAGS,
&rv1126_uart2_fracmux),
GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
RV1126_CLKGATE_CON(5), 7, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(5), 8, GFLAGS),
COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(5), 9, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(15), 0,
RV1126_CLKGATE_CON(5), 10, GFLAGS,
&rv1126_uart3_fracmux),
GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
RV1126_CLKGATE_CON(5), 11, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(5), 12, GFLAGS),
COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(17), 0,
RV1126_CLKGATE_CON(5), 14, GFLAGS,
&rv1126_uart4_fracmux),
GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
RV1126_CLKGATE_CON(5), 15, GFLAGS),
GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(19), 0,
RV1126_CLKGATE_CON(6), 2, GFLAGS,
&rv1126_uart5_fracmux),
GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
RV1126_CLKGATE_CON(6), 3, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(3), 10, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
RV1126_CLKGATE_CON(3), 11, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(3), 12, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
RV1126_CLKGATE_CON(3), 13, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(3), 14, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
RV1126_CLKGATE_CON(3), 15, GFLAGS),
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(4), 0, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
RV1126_CLKGATE_CON(4), 1, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(4), 3, GFLAGS),
GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
RV1126_CLKGATE_CON(4), 6, GFLAGS),
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKGATE_CON(4), 5, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
RV1126_CLKGATE_CON(7), 1, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 2, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
RV1126_CLKGATE_CON(7), 3, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 4, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
RV1126_CLKGATE_CON(7), 5, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 6, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
RV1126_CLKGATE_CON(7), 7, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
RV1126_CLKGATE_CON(6), 5, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(6), 7, GFLAGS),
GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
RV1126_CLKGATE_CON(6), 8, GFLAGS),
GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
RV1126_CLKGATE_CON(6), 9, GFLAGS),
GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
RV1126_CLKGATE_CON(6), 10, GFLAGS),
GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
RV1126_CLKGATE_CON(6), 11, GFLAGS),
GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
RV1126_CLKGATE_CON(6), 12, GFLAGS),
GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
RV1126_CLKGATE_CON(6), 13, GFLAGS),
GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
RV1126_CLKGATE_CON(6), 6, GFLAGS),
GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 11, GFLAGS),
GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 12, GFLAGS),
COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKGATE_CON(7), 13, GFLAGS),
GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(7), 8, GFLAGS),
COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(7), 9, GFLAGS),
/* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(24), 3, GFLAGS),
COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
RV1126_CLKGATE_CON(24), 4, GFLAGS),
GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
RV1126_CLKGATE_CON(24), 5, GFLAGS),
GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(24), 0, GFLAGS),
COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
RV1126_CLKGATE_CON(24), 1, GFLAGS),
GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
RV1126_CLKGATE_CON(24), 2, GFLAGS),
/*
* Clock-Architecture Diagram 6
*/
/* PD_AUDIO */
COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
RV1126_CLKGATE_CON(9), 0, GFLAGS),
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
RV1126_CLKGATE_CON(9), 4, GFLAGS),
COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(9), 5, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div",
CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(28), 0,
RV1126_CLKGATE_CON(9), 6, GFLAGS,
&rv1126_i2s0_tx_fracmux),
GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
RV1126_CLKGATE_CON(9), 9, GFLAGS),
COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKGATE_CON(9), 7, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div",
CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(29), 0,
RV1126_CLKGATE_CON(9), 8, GFLAGS,
&rv1126_i2s0_rx_fracmux),
GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
RV1126_CLKGATE_CON(9), 10, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
RV1126_CLKGATE_CON(9), 13, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
RV1126_CLKGATE_CON(9), 14, GFLAGS),
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
RV1126_CLKGATE_CON(10), 0, GFLAGS),
COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(10), 1, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div",
CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(32), 0,
RV1126_CLKGATE_CON(10), 2, GFLAGS,
&rv1126_i2s1_fracmux),
GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
RV1126_CLKGATE_CON(10), 3, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
RV1126_CLKGATE_CON(10), 4, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
RV1126_CLKGATE_CON(10), 5, GFLAGS),
COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div",
CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(34), 0,
RV1126_CLKGATE_CON(10), 7, GFLAGS,
&rv1126_i2s2_fracmux),
GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
RV1126_CLKGATE_CON(10), 8, GFLAGS),
COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
RV1126_CLKGATE_CON(10), 9, GFLAGS),
GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
RV1126_CLKGATE_CON(10), 10, GFLAGS),
COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(10), 11, GFLAGS),
GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
RV1126_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(10), 13, GFLAGS),
COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div",
CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(37), 0,
RV1126_CLKGATE_CON(10), 14, GFLAGS,
&rv1126_audpwm_fracmux),
GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
RV1126_CLKGATE_CON(10), 15, GFLAGS),
GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
RV1126_CLKGATE_CON(11), 0, GFLAGS),
GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
RV1126_CLKGATE_CON(11), 2, GFLAGS),
GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
RV1126_CLKGATE_CON(11), 3, GFLAGS),
COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(11), 1, GFLAGS),
/*
* Clock-Architecture Diagram 9
*/
/* PD_VO */
COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(14), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
RV1126_CLKGATE_CON(14), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
RV1126_CLKGATE_CON(14), 2, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
RV1126_CLKGATE_CON(14), 6, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
RV1126_CLKGATE_CON(14), 7, GFLAGS),
COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(14), 8, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
RV1126_CLKGATE_CON(14), 9, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
RV1126_CLKGATE_CON(14), 10, GFLAGS),
COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKGATE_CON(14), 11, GFLAGS),
COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
RV1126_CLKGATE_CON(14), 12, GFLAGS,
&rv1126_dclk_vop_fracmux),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RV1126_CLKGATE_CON(14), 13, GFLAGS),
GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
RV1126_CLKGATE_CON(14), 14, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
RV1126_CLKGATE_CON(12), 7, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
RV1126_CLKGATE_CON(12), 8, GFLAGS),
COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(12), 9, GFLAGS),
/*
* Clock-Architecture Diagram 12
*/
/* PD_PHP */
COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(17), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
RV1126_CLKGATE_CON(17), 1, GFLAGS),
/* PD_SDCARD */
GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
RV1126_CLKGATE_CON(17), 6, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
RV1126_CLKGATE_CON(18), 4, GFLAGS),
COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
/* PD_SDIO */
GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
RV1126_CLKGATE_CON(17), 8, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
RV1126_CLKGATE_CON(18), 6, GFLAGS),
COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKGATE_CON(18), 7, GFLAGS),
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
/* PD_NVM */
GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
RV1126_CLKGATE_CON(18), 1, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
RV1126_CLKGATE_CON(18), 8, GFLAGS),
COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKGATE_CON(18), 9, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
RV1126_CLKGATE_CON(18), 13, GFLAGS),
COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKGATE_CON(18), 14, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
RV1126_CLKGATE_CON(18), 10, GFLAGS),
GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
RV1126_CLKGATE_CON(18), 11, GFLAGS),
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKGATE_CON(18), 12, GFLAGS),
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
/* PD_USB */
GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
RV1126_CLKGATE_CON(19), 0, GFLAGS),
GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
RV1126_CLKGATE_CON(19), 1, GFLAGS),
GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
RV1126_CLKGATE_CON(19), 4, GFLAGS),
GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
RV1126_CLKGATE_CON(19), 5, GFLAGS),
COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(19), 6, GFLAGS),
GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
RV1126_CLKGATE_CON(19), 7, GFLAGS),
GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
RV1126_CLKGATE_CON(19), 8, GFLAGS),
/* PD_GMAC */
GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
RV1126_CLKGATE_CON(20), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
RV1126_CLKGATE_CON(20), 1, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
RV1126_CLKGATE_CON(20), 4, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
RV1126_CLKGATE_CON(20), 5, GFLAGS),
COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKGATE_CON(20), 6, GFLAGS),
GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
RV1126_CLKGATE_CON(20), 12, GFLAGS),
MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
RV1126_GMAC_CON, 0, 1, MFLAGS),
GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
RV1126_CLKGATE_CON(20), 13, GFLAGS),
MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
RV1126_GMAC_CON, 5, 1, MFLAGS),
MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT,
RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
RV1126_CLKGATE_CON(20), 7, GFLAGS),
GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
RV1126_CLKGATE_CON(20), 9, GFLAGS),
FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
RV1126_CLKGATE_CON(20), 8, GFLAGS),
FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
RV1126_GMAC_CON, 1, 1, MFLAGS),
MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT,
RV1126_GMAC_CON, 4, 1, MFLAGS),
GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
RV1126_CLKGATE_CON(20), 10, GFLAGS),
COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKGATE_CON(20), 11, GFLAGS),
/*
* Clock-Architecture Diagram 15
*/
GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 8, GFLAGS),
GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
RV1126_CLKGATE_CON(23), 4, GFLAGS),
GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
RV1126_CLKGATE_CON(23), 2, GFLAGS),
GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
RV1126_CLKGATE_CON(23), 3, GFLAGS),
GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
RV1126_CLKGATE_CON(19), 13, GFLAGS),
GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
RV1126_CLKGATE_CON(19), 12, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
/* PD_CORE */
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RV1126_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(0), 5, GFLAGS),
GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(0), 9, GFLAGS),
GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(0), 3, GFLAGS),
GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(0), 4, GFLAGS),
/*
* Clock-Architecture Diagram 4
*/
/* PD_BUS */
GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 10, GFLAGS),
GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 3, GFLAGS),
GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 4, GFLAGS),
GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 5, GFLAGS),
GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 6, GFLAGS),
GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 7, GFLAGS),
GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 8, GFLAGS),
GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(2), 9, GFLAGS),
GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(6), 15, GFLAGS),
GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(8), 4, GFLAGS),
GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(3), 9, GFLAGS),
GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(7), 14, GFLAGS),
/*
* Clock-Architecture Diagram 6
*/
/* PD_AUDIO */
GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(9), 2, GFLAGS),
GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(9), 3, GFLAGS),
/*
* Clock-Architecture Diagram 9
*/
/* PD_VO */
GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(14), 3, GFLAGS),
GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(14), 4, GFLAGS),
GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(14), 5, GFLAGS),
/*
* Clock-Architecture Diagram 12
*/
/* PD_PHP */
GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(17), 2, GFLAGS),
GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(17), 3, GFLAGS),
GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(17), 4, GFLAGS),
GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(17), 5, GFLAGS),
/* PD_SDCARD */
GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(17), 7, GFLAGS),
/* PD_SDIO */
GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(17), 9, GFLAGS),
/* PD_NVM */
GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(18), 3, GFLAGS),
/* PD_USB */
GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(19), 2, GFLAGS),
GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(19), 3, GFLAGS),
/* PD_GMAC */
GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(20), 2, GFLAGS),
GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(20), 3, GFLAGS),
/*
* Clock-Architecture Diagram 13
*/
/* PD_DDR */
COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
RV1126_CLKGATE_CON(21), 0, GFLAGS),
GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 15, GFLAGS),
GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 6, GFLAGS),
COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
CLK_DIVIDER_POWER_OF_TWO),
COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKGATE_CON(21), 8, GFLAGS),
GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 1, GFLAGS),
GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 10, GFLAGS),
GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 2, GFLAGS),
GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 13, GFLAGS),
GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 4, GFLAGS),
GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 14, GFLAGS),
GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 9, GFLAGS),
GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 5, GFLAGS),
GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 3, GFLAGS),
GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(20), 15, GFLAGS),
GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(21), 7, GFLAGS),
/*
* Clock-Architecture Diagram 15
*/
GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 9, GFLAGS),
GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 10, GFLAGS),
GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 11, GFLAGS),
GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 12, GFLAGS),
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(23), 0, GFLAGS),
};
static const char *const rv1126_cru_critical_clocks[] __initconst = {
"gpll",
"cpll",
"hpll",
"armclk",
"pclk_dbg",
"pclk_pdpmu",
"aclk_pdbus",
"hclk_pdbus",
"pclk_pdbus",
"aclk_pdphp",
"hclk_pdphp",
"clk_ddrphy",
"pclk_pdddr",
"pclk_pdtop",
"clk_usbhost_utmi_ohci",
"aclk_pdjpeg_niu",
"hclk_pdjpeg_niu",
"aclk_pdvdec_niu",
"hclk_pdvdec_niu",
};
static void __init rv1126_pmu_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru pmu region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip pmu clk init failed\n", __func__);
return;
}
rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
ARRAY_SIZE(rv1126_pmu_pll_clks),
RV1126_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
ARRAY_SIZE(rv1126_clk_pmu_branches));
rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_clk_of_add_provider(np, ctx);
}
static void __init rv1126_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rv1126_pll_clks,
ARRAY_SIZE(rv1126_pll_clks),
RV1126_GRF_SOC_STATUS0);
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rv1126_cpuclk_data, rv1126_cpuclk_rates,
ARRAY_SIZE(rv1126_cpuclk_rates));
rockchip_clk_register_branches(ctx, rv1126_clk_branches,
ARRAY_SIZE(rv1126_clk_branches));
rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
ARRAY_SIZE(rv1126_cru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
struct clk_rv1126_inits {
void (*inits)(struct device_node *np);
};
static const struct clk_rv1126_inits clk_rv1126_pmucru_init = {
.inits = rv1126_pmu_clk_init,
};
static const struct clk_rv1126_inits clk_rv1126_cru_init = {
.inits = rv1126_clk_init,
};
static const struct of_device_id clk_rv1126_match_table[] = {
{
.compatible = "rockchip,rv1126-cru",
.data = &clk_rv1126_cru_init,
}, {
.compatible = "rockchip,rv1126-pmucru",
.data = &clk_rv1126_pmucru_init,
},
{ }
};
static int __init clk_rv1126_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct clk_rv1126_inits *init_data;
init_data = (struct clk_rv1126_inits *)of_device_get_match_data(&pdev->dev);
if (!init_data)
return -EINVAL;
if (init_data->inits)
init_data->inits(np);
return 0;
}
static struct platform_driver clk_rv1126_driver = {
.driver = {
.name = "clk-rv1126",
.of_match_table = clk_rv1126_match_table,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_rv1126_driver, clk_rv1126_probe);
| linux-master | drivers/clk/rockchip/clk-rv1126.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
* Author: Finley Xiao <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3308-cru.h>
#include "clk.h"
#define RK3308_GRF_SOC_STATUS0 0x380
enum rk3308_plls {
apll, dpll, vpll0, vpll1,
};
static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define RK3308_DIV_ACLKM_MASK 0x7
#define RK3308_DIV_ACLKM_SHIFT 12
#define RK3308_DIV_PCLK_DBG_MASK 0xf
#define RK3308_DIV_PCLK_DBG_SHIFT 8
#define RK3308_CLKSEL0(_aclk_core, _pclk_dbg) \
{ \
.reg = RK3308_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \
RK3308_DIV_ACLKM_SHIFT) | \
HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \
RK3308_DIV_PCLK_DBG_SHIFT), \
}
#define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
{ \
.prate = _prate, \
.divs = { \
RK3308_CLKSEL0(_aclk_core, _pclk_dbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
RK3308_CPUCLK_RATE(1608000000, 1, 7),
RK3308_CPUCLK_RATE(1512000000, 1, 7),
RK3308_CPUCLK_RATE(1488000000, 1, 5),
RK3308_CPUCLK_RATE(1416000000, 1, 5),
RK3308_CPUCLK_RATE(1392000000, 1, 5),
RK3308_CPUCLK_RATE(1296000000, 1, 5),
RK3308_CPUCLK_RATE(1200000000, 1, 5),
RK3308_CPUCLK_RATE(1104000000, 1, 5),
RK3308_CPUCLK_RATE(1008000000, 1, 5),
RK3308_CPUCLK_RATE(912000000, 1, 5),
RK3308_CPUCLK_RATE(816000000, 1, 3),
RK3308_CPUCLK_RATE(696000000, 1, 3),
RK3308_CPUCLK_RATE(600000000, 1, 3),
RK3308_CPUCLK_RATE(408000000, 1, 1),
RK3308_CPUCLK_RATE(312000000, 1, 1),
RK3308_CPUCLK_RATE(216000000, 1, 1),
RK3308_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
.core_reg[0] = RK3308_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0xf,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" };
PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
PNAME(mux_mac_p) = { "clk_mac_src", "mac_clkin" };
PNAME(mux_mac_rmii_sel_p) = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" };
PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" };
PNAME(mux_rtc32k_p) = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" };
PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
PNAME(mux_wifi_src_p) = { "clk_wifi_dpll", "clk_wifi_vpll0" };
PNAME(mux_wifi_p) = { "clk_wifi_osc", "clk_wifi_src" };
PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" };
PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m" };
PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" };
PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
PNAME(mux_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" };
PNAME(mux_i2s1_8ch_tx_rx_p) = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"};
PNAME(mux_i2s1_8ch_tx_out_p) = { "clk_i2s1_8ch_tx", "xin12m" };
PNAME(mux_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" };
PNAME(mux_i2s1_8ch_rx_tx_p) = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"};
PNAME(mux_i2s2_8ch_tx_p) = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" };
PNAME(mux_i2s2_8ch_tx_rx_p) = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"};
PNAME(mux_i2s2_8ch_tx_out_p) = { "clk_i2s2_8ch_tx", "xin12m" };
PNAME(mux_i2s2_8ch_rx_p) = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" };
PNAME(mux_i2s2_8ch_rx_tx_p) = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"};
PNAME(mux_i2s3_8ch_tx_p) = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" };
PNAME(mux_i2s3_8ch_tx_rx_p) = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"};
PNAME(mux_i2s3_8ch_tx_out_p) = { "clk_i2s3_8ch_tx", "xin12m" };
PNAME(mux_i2s3_8ch_rx_p) = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" };
PNAME(mux_i2s3_8ch_rx_tx_p) = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"};
PNAME(mux_i2s0_2ch_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" };
PNAME(mux_i2s0_2ch_out_p) = { "clk_i2s0_2ch", "xin12m" };
PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"};
PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0, RK3308_PLL_CON(0),
RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, RK3308_PLL_CON(8),
RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
[vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p,
0, RK3308_PLL_CON(16),
RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),
[vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p,
0, RK3308_PLL_CON(24),
RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3308_uart0_fracmux __initdata =
MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_uart1_fracmux __initdata =
MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_uart2_fracmux __initdata =
MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_uart3_fracmux __initdata =
MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_uart4_fracmux __initdata =
MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_dclk_vop_fracmux __initdata =
MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_rtc32k_fracmux __initdata =
MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_pdm_fracmux __initdata =
MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s0_8ch_tx_fracmux __initdata =
MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(52), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s0_8ch_rx_fracmux __initdata =
MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(54), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s1_8ch_tx_fracmux __initdata =
MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(56), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s1_8ch_rx_fracmux __initdata =
MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(58), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s2_8ch_tx_fracmux __initdata =
MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(60), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s2_8ch_rx_fracmux __initdata =
MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(62), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s3_8ch_tx_fracmux __initdata =
MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(64), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s3_8ch_rx_fracmux __initdata =
MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(66), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s0_2ch_fracmux __initdata =
MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(68), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_i2s1_2ch_fracmux __initdata =
MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(70), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_spdif_tx_fracmux __initdata =
MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(48), 14, 2, MFLAGS);
static struct rockchip_clk_branch rk3308_spdif_rx_fracmux __initdata =
MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(50), 15, 1, MFLAGS);
static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK3308_MODE_CON, 8, 2, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/*
* Clock-Architecture Diagram 2
*/
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3308_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3308_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(0), 3, GFLAGS),
GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
RK3308_CLKGATE_CON(0), 4, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
RK3308_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 3, GFLAGS),
GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 15, GFLAGS),
COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(12), 0,
RK3308_CLKGATE_CON(1), 11, GFLAGS,
&rk3308_uart0_fracmux),
GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
RK3308_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(15), 0,
RK3308_CLKGATE_CON(1), 15, GFLAGS,
&rk3308_uart1_fracmux),
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
RK3308_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(18), 0,
RK3308_CLKGATE_CON(2), 3, GFLAGS,
&rk3308_uart2_fracmux),
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
RK3308_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(21), 0,
RK3308_CLKGATE_CON(2), 7, GFLAGS,
&rk3308_uart3_fracmux),
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
RK3308_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(24), 0,
RK3308_CLKGATE_CON(2), 11, GFLAGS,
&rk3308_uart4_fracmux),
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
RK3308_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(25), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(2), 13, GFLAGS),
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(26), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(2), 14, GFLAGS),
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(27), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(15), 0, GFLAGS),
COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(15), 1, GFLAGS),
COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 4, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
RK3308_CLKGATE_CON(3), 10, GFLAGS),
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
RK3308_CLKGATE_CON(3), 11, GFLAGS),
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
RK3308_CLKGATE_CON(3), 12, GFLAGS),
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
RK3308_CLKGATE_CON(3), 13, GFLAGS),
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
RK3308_CLKGATE_CON(3), 14, GFLAGS),
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
RK3308_CLKGATE_CON(3), 15, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
RK3308_CLKSEL_CON(33), 0, 11, DFLAGS,
RK3308_CLKGATE_CON(3), 5, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
RK3308_CLKSEL_CON(34), 0, 11, DFLAGS,
RK3308_CLKGATE_CON(3), 6, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
RK3308_CLKSEL_CON(35), 0, 4, DFLAGS,
RK3308_CLKGATE_CON(3), 7, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
RK3308_CLKSEL_CON(35), 4, 2, DFLAGS,
RK3308_CLKGATE_CON(3), 8, GFLAGS),
GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(3), 9, GFLAGS),
COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(7), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 5, GFLAGS),
COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RK3308_CLKGATE_CON(1), 8, GFLAGS),
/*
* Clock-Architecture Diagram 4
*/
COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
RK3308_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 1, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 2, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 3, GFLAGS),
COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 4, GFLAGS),
COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 4, GFLAGS),
COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3308_CLKSEL_CON(38), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(8), 5, GFLAGS),
COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(8), 6, GFLAGS),
COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(8), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3308_CLKSEL_CON(39), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(8), 7, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3308_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1),
COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(8), 8, GFLAGS),
COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(8), 8, GFLAGS),
COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3308_CLKSEL_CON(40), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(8), 9, GFLAGS),
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3308_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3308_SDIO_CON1, 1),
COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(8), 10, GFLAGS),
COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(8), 10, GFLAGS),
COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3308_CLKSEL_CON(41), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(8), 11, GFLAGS),
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3308_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK3308_EMMC_CON1, 1),
COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(42), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(8), 12, GFLAGS),
GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 0,
RK3308_CLKGATE_CON(8), 13, GFLAGS),
COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(8), 14, GFLAGS),
MUX(SCLK_MAC, "clk_mac", mux_mac_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(43), 14, 1, MFLAGS),
GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 0,
RK3308_CLKGATE_CON(9), 1, GFLAGS),
GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 0,
RK3308_CLKGATE_CON(9), 0, GFLAGS),
FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 0, 1, 2),
FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 0, 1, 20),
MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3308_CLKGATE_CON(8), 15, GFLAGS),
/*
* Clock-Architecture Diagram 5
*/
GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(0), 12, GFLAGS),
GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 10, GFLAGS),
GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 11, GFLAGS),
GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 12, GFLAGS),
GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 13, GFLAGS),
COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
RK3308_CLKGATE_CON(0), 10, GFLAGS),
GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(0), 11, GFLAGS),
FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
RK3308_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(1), 8, 1, MFLAGS,
RK3308_CLKGATE_CON(4), 14, GFLAGS),
/*
* Clock-Architecture Diagram 6
*/
GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 5, GFLAGS),
GATE(SCLK_PMU, "clk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
RK3308_CLKGATE_CON(4), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(3), 0,
RK3308_CLKGATE_CON(4), 3, GFLAGS,
&rk3308_rtc32k_fracmux),
MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(4), 0, 16, DFLAGS,
RK3308_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0,
RK3308_CLKSEL_CON(72), 6, 1, MFLAGS, 0, 6, DFLAGS,
RK3308_CLKGATE_CON(4), 7, GFLAGS),
COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(72), 7, 1, MFLAGS,
RK3308_CLKGATE_CON(4), 8, GFLAGS),
GATE(0, "clk_wifi_dpll", "dpll", 0,
RK3308_CLKGATE_CON(15), 2, GFLAGS),
GATE(0, "clk_wifi_vpll0", "vpll0", 0,
RK3308_CLKGATE_CON(15), 3, GFLAGS),
GATE(0, "clk_wifi_osc", "xin24m", 0,
RK3308_CLKGATE_CON(15), 4, GFLAGS),
COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0,
RK3308_CLKSEL_CON(44), 6, 1, MFLAGS, 0, 6, DFLAGS,
RK3308_CLKGATE_CON(4), 0, GFLAGS),
COMPOSITE_NODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(44), 7, 1, MFLAGS,
RK3308_CLKGATE_CON(4), 1, GFLAGS),
GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
RK3308_CLKGATE_CON(4), 4, GFLAGS),
/*
* Clock-Architecture Diagram 7
*/
COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
RK3308_CLKGATE_CON(10), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(10), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
RK3308_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(10), 3, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(47), 0,
RK3308_CLKGATE_CON(10), 4, GFLAGS,
&rk3308_pdm_fracmux),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
RK3308_CLKGATE_CON(10), 5, GFLAGS),
COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(53), 0,
RK3308_CLKGATE_CON(10), 13, GFLAGS,
&rk3308_i2s0_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(10), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(52), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(10), 15, GFLAGS),
COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(11), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(55), 0,
RK3308_CLKGATE_CON(11), 1, GFLAGS,
&rk3308_i2s0_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 2, GFLAGS),
GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 0,
RK3308_CLKGATE_CON(11), 3, GFLAGS),
COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(11), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(57), 0,
RK3308_CLKGATE_CON(11), 5, GFLAGS,
&rk3308_i2s1_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(56), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 7, GFLAGS),
COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(11), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(59), 0,
RK3308_CLKGATE_CON(11), 9, GFLAGS,
&rk3308_i2s1_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 10, GFLAGS),
GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 0,
RK3308_CLKGATE_CON(11), 11, GFLAGS),
COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(11), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(61), 0,
RK3308_CLKGATE_CON(11), 13, GFLAGS,
&rk3308_i2s2_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(60), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(11), 15, GFLAGS),
COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(12), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(63), 0,
RK3308_CLKGATE_CON(12), 1, GFLAGS,
&rk3308_i2s2_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 2, GFLAGS),
GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 0,
RK3308_CLKGATE_CON(12), 3, GFLAGS),
COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(12), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(65), 0,
RK3308_CLKGATE_CON(12), 5, GFLAGS,
&rk3308_i2s3_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(64), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 7, GFLAGS),
COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(12), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(67), 0,
RK3308_CLKGATE_CON(12), 9, GFLAGS,
&rk3308_i2s3_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 10, GFLAGS),
GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 0,
RK3308_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(12), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(69), 0,
RK3308_CLKGATE_CON(12), 13, GFLAGS,
&rk3308_i2s0_2ch_fracmux),
GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
RK3308_CLKGATE_CON(12), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(68), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(12), 15, GFLAGS),
COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
RK3308_CLKSEL_CON(70), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(13), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(71), 0,
RK3308_CLKGATE_CON(13), 1, GFLAGS,
&rk3308_i2s1_2ch_fracmux),
GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
RK3308_CLKGATE_CON(13), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(70), 15, 1, MFLAGS,
RK3308_CLKGATE_CON(13), 3, GFLAGS),
COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(10), 6, GFLAGS),
MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3308_CLKSEL_CON(48), 12, 1, MFLAGS),
COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(49), 0,
RK3308_CLKGATE_CON(10), 7, GFLAGS,
&rk3308_spdif_tx_fracmux),
GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
RK3308_CLKGATE_CON(10), 8, GFLAGS),
COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(10), 9, GFLAGS),
COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(10), 9, GFLAGS),
MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3308_CLKSEL_CON(50), 14, 1, MFLAGS),
COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(51), 0,
RK3308_CLKGATE_CON(10), 10, GFLAGS,
&rk3308_spdif_rx_fracmux),
GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
RK3308_CLKGATE_CON(10), 11, GFLAGS),
/*
* Clock-Architecture Diagram 8
*/
GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 5, GFLAGS),
GATE(0, "pclk_core_dbg_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 7, GFLAGS),
GATE(0, "aclk_core_perf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 8, GFLAGS),
GATE(0, "pclk_core_grf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 9, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 2, GFLAGS),
GATE(0, "aclk_peribus_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 3, GFLAGS),
GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 0, RK3308_CLKGATE_CON(9), 4, GFLAGS),
GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 5, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 7, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 8, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 9, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 10, GFLAGS),
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 11, GFLAGS),
GATE(HCLK_HOST, "hclk_host", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 12, GFLAGS),
GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 13, GFLAGS),
GATE(0, "pclk_peri_niu", "pclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 14, GFLAGS),
GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 0, RK3308_CLKGATE_CON(9), 15, GFLAGS),
GATE(0, "hclk_audio_niu", "hclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 0, GFLAGS),
GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 1, GFLAGS),
GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 2, GFLAGS),
GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 3, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS),
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 5, GFLAGS),
GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 6, GFLAGS),
GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 7, GFLAGS),
GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 8, GFLAGS),
GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 9, GFLAGS),
GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 10, GFLAGS),
GATE(0, "pclk_audio_niu", "pclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 11, GFLAGS),
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 0, RK3308_CLKGATE_CON(14), 12, GFLAGS),
GATE(0, "aclk_bus_niu", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 0, GFLAGS),
GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 1, GFLAGS),
GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
/* aclk_dmaci0 is controlled by sgrf_clkgat_con. */
SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
/* aclk_dmac1 is controlled by sgrf_clkgat_con. */
SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
/* watchdog pclk is controlled by sgrf_clkgat_con. */
SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 7, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 8, GFLAGS),
GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 9, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 14, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 7, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 8, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 9, GFLAGS),
GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 10, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 14, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 15, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 0, GFLAGS),
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 1, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 2, GFLAGS),
GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 3, GFLAGS),
GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 4, GFLAGS),
GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 5, GFLAGS),
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 6, GFLAGS),
GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 7, GFLAGS),
GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 8, GFLAGS),
GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
};
static const char *const rk3308_critical_clocks[] __initconst = {
"aclk_bus",
"hclk_bus",
"pclk_bus",
"aclk_peri",
"hclk_peri",
"pclk_peri",
"hclk_audio",
"pclk_audio",
"sclk_ddrc",
"clk_ddrphy4x",
};
static void __init rk3308_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3308_pll_clks,
ARRAY_SIZE(rk3308_pll_clks),
RK3308_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3308_clk_branches,
ARRAY_SIZE(rk3308_clk_branches));
rockchip_clk_protect_critical(rk3308_critical_clocks,
ARRAY_SIZE(rk3308_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3308_cpuclk_data, rk3308_cpuclk_rates,
ARRAY_SIZE(rk3308_cpuclk_rates));
rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3308_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3308.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2015 Heiko Stuebner <[email protected]>
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/kernel.h>
#include "clk.h"
struct rockchip_inv_clock {
struct clk_hw hw;
void __iomem *reg;
int shift;
int flags;
spinlock_t *lock;
};
#define to_inv_clock(_hw) container_of(_hw, struct rockchip_inv_clock, hw)
#define INVERTER_MASK 0x1
static int rockchip_inv_get_phase(struct clk_hw *hw)
{
struct rockchip_inv_clock *inv_clock = to_inv_clock(hw);
u32 val;
val = readl(inv_clock->reg) >> inv_clock->shift;
val &= INVERTER_MASK;
return val ? 180 : 0;
}
static int rockchip_inv_set_phase(struct clk_hw *hw, int degrees)
{
struct rockchip_inv_clock *inv_clock = to_inv_clock(hw);
u32 val;
if (degrees % 180 == 0) {
val = !!degrees;
} else {
pr_err("%s: unsupported phase %d for %s\n",
__func__, degrees, clk_hw_get_name(hw));
return -EINVAL;
}
if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) {
writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift),
inv_clock->reg);
} else {
unsigned long flags;
u32 reg;
spin_lock_irqsave(inv_clock->lock, flags);
reg = readl(inv_clock->reg);
reg &= ~BIT(inv_clock->shift);
reg |= val;
writel(reg, inv_clock->reg);
spin_unlock_irqrestore(inv_clock->lock, flags);
}
return 0;
}
static const struct clk_ops rockchip_inv_clk_ops = {
.get_phase = rockchip_inv_get_phase,
.set_phase = rockchip_inv_set_phase,
};
struct clk *rockchip_clk_register_inverter(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *reg, int shift, int flags,
spinlock_t *lock)
{
struct clk_init_data init;
struct rockchip_inv_clock *inv_clock;
struct clk *clk;
inv_clock = kmalloc(sizeof(*inv_clock), GFP_KERNEL);
if (!inv_clock)
return ERR_PTR(-ENOMEM);
init.name = name;
init.num_parents = num_parents;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent_names;
init.ops = &rockchip_inv_clk_ops;
inv_clock->hw.init = &init;
inv_clock->reg = reg;
inv_clock->shift = shift;
inv_clock->flags = flags;
inv_clock->lock = lock;
clk = clk_register(NULL, &inv_clock->hw);
if (IS_ERR(clk))
kfree(inv_clock);
return clk;
}
| linux-master | drivers/clk/rockchip/clk-inverter.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/slab.h>
#include "clk.h"
#define div_mask(width) ((1 << (width)) - 1)
static bool _is_best_half_div(unsigned long rate, unsigned long now,
unsigned long best, unsigned long flags)
{
if (flags & CLK_DIVIDER_ROUND_CLOSEST)
return abs(rate - now) < abs(rate - best);
return now <= rate && now > best;
}
static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
val = readl(divider->reg) >> divider->shift;
val &= div_mask(divider->width);
val = val * 2 + 3;
return DIV_ROUND_UP_ULL(((u64)parent_rate * 2), val);
}
static int clk_half_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate, u8 width,
unsigned long flags)
{
unsigned int i, bestdiv = 0;
unsigned long parent_rate, best = 0, now, maxdiv;
unsigned long parent_rate_saved = *best_parent_rate;
if (!rate)
rate = 1;
maxdiv = div_mask(width);
if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
bestdiv = DIV_ROUND_UP_ULL(((u64)parent_rate * 2), rate);
if (bestdiv < 3)
bestdiv = 0;
else
bestdiv = (bestdiv - 3) / 2;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
}
/*
* The maximum divider we can use without overflowing
* unsigned long in rate * i below
*/
maxdiv = min(ULONG_MAX / rate, maxdiv);
for (i = 0; i <= maxdiv; i++) {
if (((u64)rate * (i * 2 + 3)) == ((u64)parent_rate_saved * 2)) {
/*
* It's the most ideal case if the requested rate can be
* divided from parent clock without needing to change
* parent rate, so return the divider immediately.
*/
*best_parent_rate = parent_rate_saved;
return i;
}
parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
((u64)rate * (i * 2 + 3)) / 2);
now = DIV_ROUND_UP_ULL(((u64)parent_rate * 2),
(i * 2 + 3));
if (_is_best_half_div(rate, now, best, flags)) {
bestdiv = i;
best = now;
*best_parent_rate = parent_rate;
}
}
if (!bestdiv) {
bestdiv = div_mask(width);
*best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
}
return bestdiv;
}
static long clk_half_divider_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_divider *divider = to_clk_divider(hw);
int div;
div = clk_half_divider_bestdiv(hw, rate, prate,
divider->width,
divider->flags);
return DIV_ROUND_UP_ULL(((u64)*prate * 2), div * 2 + 3);
}
static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_divider *divider = to_clk_divider(hw);
unsigned int value;
unsigned long flags = 0;
u32 val;
value = DIV_ROUND_UP_ULL(((u64)parent_rate * 2), rate);
value = (value - 3) / 2;
value = min_t(unsigned int, value, div_mask(divider->width));
if (divider->lock)
spin_lock_irqsave(divider->lock, flags);
else
__acquire(divider->lock);
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider->width) << (divider->shift + 16);
} else {
val = readl(divider->reg);
val &= ~(div_mask(divider->width) << divider->shift);
}
val |= value << divider->shift;
writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
else
__release(divider->lock);
return 0;
}
static const struct clk_ops clk_half_divider_ops = {
.recalc_rate = clk_half_divider_recalc_rate,
.round_rate = clk_half_divider_round_rate,
.set_rate = clk_half_divider_set_rate,
};
/*
* Register a clock branch.
* Most clock branches have a form like
*
* src1 --|--\
* |M |--[GATE]-[DIV]-
* src2 --|--/
*
* sometimes without one of those components.
*/
struct clk *rockchip_clk_register_halfdiv(const char *name,
const char *const *parent_names,
u8 num_parents, void __iomem *base,
int muxdiv_offset, u8 mux_shift,
u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width,
u8 div_flags, int gate_offset,
u8 gate_shift, u8 gate_flags,
unsigned long flags,
spinlock_t *lock)
{
struct clk_hw *hw = ERR_PTR(-ENOMEM);
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
*gate_ops = NULL;
if (num_parents > 1) {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->reg = base + muxdiv_offset;
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
}
if (gate_offset >= 0) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
goto err_gate;
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
gate_ops = &clk_gate_ops;
}
if (div_width > 0) {
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
goto err_div;
div->flags = div_flags;
div->reg = base + muxdiv_offset;
div->shift = div_shift;
div->width = div_width;
div->lock = lock;
div_ops = &clk_half_divider_ops;
}
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
mux ? &mux->hw : NULL, mux_ops,
div ? &div->hw : NULL, div_ops,
gate ? &gate->hw : NULL, gate_ops,
flags);
if (IS_ERR(hw))
goto err_div;
return hw->clk;
err_div:
kfree(gate);
err_gate:
kfree(mux);
return ERR_CAST(hw);
}
| linux-master | drivers/clk/rockchip/clk-half-divider.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Lin Huang <[email protected]>
*/
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <soc/rockchip/rockchip_sip.h>
#include "clk.h"
struct rockchip_ddrclk {
struct clk_hw hw;
void __iomem *reg_base;
int mux_offset;
int mux_shift;
int mux_width;
int div_shift;
int div_width;
int ddr_flag;
spinlock_t *lock;
};
#define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
unsigned long flags;
struct arm_smccc_res res;
spin_lock_irqsave(ddrclk->lock, flags);
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
0, 0, 0, 0, &res);
spin_unlock_irqrestore(ddrclk->lock, flags);
return res.a0;
}
static unsigned long
rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct arm_smccc_res res;
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
0, 0, 0, 0, &res);
return res.a0;
}
static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *prate)
{
struct arm_smccc_res res;
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0,
ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
0, 0, 0, 0, &res);
return res.a0;
}
static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
{
struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
u32 val;
val = readl(ddrclk->reg_base +
ddrclk->mux_offset) >> ddrclk->mux_shift;
val &= GENMASK(ddrclk->mux_width - 1, 0);
return val;
}
static const struct clk_ops rockchip_ddrclk_sip_ops = {
.recalc_rate = rockchip_ddrclk_sip_recalc_rate,
.set_rate = rockchip_ddrclk_sip_set_rate,
.round_rate = rockchip_ddrclk_sip_round_rate,
.get_parent = rockchip_ddrclk_get_parent,
};
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
const char *const *parent_names,
u8 num_parents, int mux_offset,
int mux_shift, int mux_width,
int div_shift, int div_width,
int ddr_flag, void __iomem *reg_base,
spinlock_t *lock)
{
struct rockchip_ddrclk *ddrclk;
struct clk_init_data init;
struct clk *clk;
ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
if (!ddrclk)
return ERR_PTR(-ENOMEM);
init.name = name;
init.parent_names = parent_names;
init.num_parents = num_parents;
init.flags = flags;
init.flags |= CLK_SET_RATE_NO_REPARENT;
switch (ddr_flag) {
case ROCKCHIP_DDRCLK_SIP:
init.ops = &rockchip_ddrclk_sip_ops;
break;
default:
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
kfree(ddrclk);
return ERR_PTR(-EINVAL);
}
ddrclk->reg_base = reg_base;
ddrclk->lock = lock;
ddrclk->hw.init = &init;
ddrclk->mux_offset = mux_offset;
ddrclk->mux_shift = mux_shift;
ddrclk->mux_width = mux_width;
ddrclk->div_shift = div_shift;
ddrclk->div_width = div_width;
ddrclk->ddr_flag = ddr_flag;
clk = clk_register(NULL, &ddrclk->hw);
if (IS_ERR(clk))
kfree(ddrclk);
return clk;
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
| linux-master | drivers/clk/rockchip/clk-ddr.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/rk3399-cru.h>
#include "clk.h"
enum rk3399_plls {
lpll, bpll, dpll, cpll, gpll, npll, vpll,
};
enum rk3399_pmu_plls {
ppll,
};
static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
};
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
"clk_core_l_bpll_src",
"clk_core_l_dpll_src",
"clk_core_l_gpll_src" };
PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
"clk_core_b_bpll_src",
"clk_core_b_dpll_src",
"clk_core_b_gpll_src" };
PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
"clk_ddrc_bpll_src",
"clk_ddrc_dpll_src",
"clk_ddrc_gpll_src" };
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
"vpll_aclk_cci_src" };
PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
"npll_cs"};
PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
"gpll_aclk_perihp_src" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
"ppll" };
PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
"xin24m" };
PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
"clk_usbphy_480m" };
PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
"npll", "upll" };
PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
"upll", "xin24m" };
PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
"ppll", "upll", "xin24m" };
PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
"npll" };
PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
"dclk_vop0_frac" };
PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
"dclk_vop1_frac" };
PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
"cpll", "gpll" };
PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
"clk_pcie_core_phy" };
PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
"gpll_aclk_emmc_src" };
PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
"gpll_aclk_perilp0_src" };
PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
"gpll_fclk_cm0s_src" };
PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
"gpll_hclk_perilp1_src" };
PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
"clk_usbphy1_480m_src" };
PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
"gpll_aclk_gmac_src" };
PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
"clkin_i2s", "xin12m" };
PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
"clkin_i2s", "xin12m" };
PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
"clkin_i2s", "xin12m" };
PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
"clkin_i2s", "xin12m" };
PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
"clk_i2s2" };
PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
/* PMU CRU parents */
PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
"xin24m" };
PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
[lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
[bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
RK3399_PLL_CON(19), 8, 31, 0, NULL),
[cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
.core_reg[0] = RK3399_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 3,
.mux_core_main = 0,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
.core_reg[0] = RK3399_CLKSEL_CON(2),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 3,
.mux_core_main = 1,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
#define RK3399_DIV_ACLKM_MASK 0x1f
#define RK3399_DIV_ACLKM_SHIFT 8
#define RK3399_DIV_ATCLK_MASK 0x1f
#define RK3399_DIV_ATCLK_SHIFT 0
#define RK3399_DIV_PCLK_DBG_MASK 0x1f
#define RK3399_DIV_PCLK_DBG_SHIFT 8
#define RK3399_CLKSEL0(_offs, _aclkm) \
{ \
.reg = RK3399_CLKSEL_CON(0 + _offs), \
.val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
RK3399_DIV_ACLKM_SHIFT), \
}
#define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
{ \
.reg = RK3399_CLKSEL_CON(1 + _offs), \
.val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
RK3399_DIV_ATCLK_SHIFT) | \
HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
RK3399_DIV_PCLK_DBG_SHIFT), \
}
/* cluster_l: aclkm in clksel0, rest in clksel1 */
#define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
{ \
.prate = _prate##U, \
.divs = { \
RK3399_CLKSEL0(0, _aclkm), \
RK3399_CLKSEL1(0, _atclk, _pdbg), \
}, \
}
/* cluster_b: aclkm in clksel2, rest in clksel3 */
#define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
{ \
.prate = _prate##U, \
.divs = { \
RK3399_CLKSEL0(2, _aclkm), \
RK3399_CLKSEL1(2, _atclk, _pdbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
};
static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
};
static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
/*
* CRU Clock-Architecture
*/
/* usbphy */
GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 5, GFLAGS),
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
RK3399_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 0, GFLAGS),
GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(30), 0, GFLAGS),
GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
RK3399_CLKGATE_CON(30), 1, GFLAGS),
GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
RK3399_CLKGATE_CON(30), 2, GFLAGS),
GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
RK3399_CLKGATE_CON(30), 3, GFLAGS),
GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
RK3399_CLKGATE_CON(30), 4, GFLAGS),
GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
RK3399_CLKGATE_CON(12), 1, GFLAGS),
GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
RK3399_CLKGATE_CON(12), 2, GFLAGS),
COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
RK3399_CLKGATE_CON(12), 3, GFLAGS),
COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
RK3399_CLKGATE_CON(12), 4, GFLAGS),
COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 4, GFLAGS),
COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 5, GFLAGS),
COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 6, GFLAGS),
COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 7, GFLAGS),
/* little core */
GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3399_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3399_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NOMUX(PCLK_COREDBG_L, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3399_CLKGATE_CON(0), 6, GFLAGS),
GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 12, GFLAGS),
GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 13, GFLAGS),
GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 9, GFLAGS),
GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 10, GFLAGS),
GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 11, GFLAGS),
GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
RK3399_CLKGATE_CON(0), 7, GFLAGS),
/* big core */
GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(1), 0, GFLAGS),
GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(1), 1, GFLAGS),
GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(1), 2, GFLAGS),
GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3399_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3399_CLKGATE_CON(1), 5, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3399_CLKGATE_CON(1), 6, GFLAGS),
GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 5, GFLAGS),
GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 6, GFLAGS),
GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 1, GFLAGS),
GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 3, GFLAGS),
GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 4, GFLAGS),
DIV(PCLK_COREDBG_B, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(14), 2, GFLAGS),
GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
RK3399_CLKGATE_CON(1), 7, GFLAGS),
/* gmac */
GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 9, GFLAGS),
GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 8, GFLAGS),
COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(6), 10, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
RK3399_CLKGATE_CON(32), 0, GFLAGS),
GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 1, GFLAGS),
GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
RK3399_CLKGATE_CON(32), 4, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
RK3399_CLKGATE_CON(6), 11, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
RK3399_CLKGATE_CON(32), 2, GFLAGS),
GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 3, GFLAGS),
COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(5), 5, GFLAGS),
MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 6, GFLAGS),
GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 7, GFLAGS),
GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 8, GFLAGS),
GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 9, GFLAGS),
/* spdif */
COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
RK3399_CLKSEL_CON(99), 0,
RK3399_CLKGATE_CON(8), 14, GFLAGS,
&rk3399_spdif_fracmux),
GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 15, GFLAGS),
COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 6, GFLAGS),
/* i2s */
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 3, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
RK3399_CLKSEL_CON(96), 0,
RK3399_CLKGATE_CON(8), 4, GFLAGS,
&rk3399_i2s0_fracmux),
GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 5, GFLAGS),
COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
RK3399_CLKSEL_CON(97), 0,
RK3399_CLKGATE_CON(8), 7, GFLAGS,
&rk3399_i2s1_fracmux),
GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 8, GFLAGS),
COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
RK3399_CLKSEL_CON(98), 0,
RK3399_CLKGATE_CON(8), 10, GFLAGS,
&rk3399_i2s2_fracmux),
GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 11, GFLAGS),
MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
RK3399_CLKGATE_CON(8), 12, GFLAGS),
/* uart */
MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
RK3399_CLKSEL_CON(100), 0,
RK3399_CLKGATE_CON(9), 1, GFLAGS,
&rk3399_uart0_fracmux),
MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 2, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
RK3399_CLKSEL_CON(101), 0,
RK3399_CLKGATE_CON(9), 3, GFLAGS,
&rk3399_uart1_fracmux),
COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
RK3399_CLKSEL_CON(102), 0,
RK3399_CLKGATE_CON(9), 5, GFLAGS,
&rk3399_uart2_fracmux),
COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
RK3399_CLKSEL_CON(103), 0,
RK3399_CLKGATE_CON(9), 7, GFLAGS,
&rk3399_uart3_fracmux),
COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(3), 4, GFLAGS),
GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(18), 10, GFLAGS),
GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
RK3399_CLKGATE_CON(18), 12, GFLAGS),
GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(18), 15, GFLAGS),
GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(19), 2, GFLAGS),
GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
RK3399_CLKGATE_CON(4), 11, GFLAGS),
GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
RK3399_CLKGATE_CON(3), 5, GFLAGS),
GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
RK3399_CLKGATE_CON(3), 6, GFLAGS),
/* cci */
GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 0, GFLAGS),
GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 1, GFLAGS),
GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 2, GFLAGS),
GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 3, GFLAGS),
COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(2), 4, GFLAGS),
GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 0, GFLAGS),
GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 1, GFLAGS),
GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 2, GFLAGS),
GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 3, GFLAGS),
GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 4, GFLAGS),
GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 7, GFLAGS),
GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 5, GFLAGS),
GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(2), 7, GFLAGS),
GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 8, GFLAGS),
GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 9, GFLAGS),
GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 5, GFLAGS),
GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 6, GFLAGS),
/* vcodec */
COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 0, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 1, GFLAGS),
GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
RK3399_CLKGATE_CON(17), 2, GFLAGS),
GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(17), 3, GFLAGS),
GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
RK3399_CLKGATE_CON(17), 0, GFLAGS),
GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(17), 1, GFLAGS),
/* vdu */
COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 5, GFLAGS),
COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 3, GFLAGS),
GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
RK3399_CLKGATE_CON(17), 10, GFLAGS),
GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(17), 11, GFLAGS),
GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
RK3399_CLKGATE_CON(17), 8, GFLAGS),
GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(17), 9, GFLAGS),
/* iep */
COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 6, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 7, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
RK3399_CLKGATE_CON(16), 2, GFLAGS),
GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(16), 3, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
RK3399_CLKGATE_CON(16), 0, GFLAGS),
GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(16), 1, GFLAGS),
/* rga */
COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 10, GFLAGS),
COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 8, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(4), 9, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
RK3399_CLKGATE_CON(16), 10, GFLAGS),
GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(16), 11, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
RK3399_CLKGATE_CON(16), 8, GFLAGS),
GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(16), 9, GFLAGS),
/* center */
COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(3), 7, GFLAGS),
GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(19), 0, GFLAGS),
GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(19), 1, GFLAGS),
/* gpu */
COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 0, GFLAGS),
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
RK3399_CLKGATE_CON(30), 8, GFLAGS),
GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
RK3399_CLKGATE_CON(30), 10, GFLAGS),
GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
RK3399_CLKGATE_CON(30), 11, GFLAGS),
GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
RK3399_CLKGATE_CON(13), 1, GFLAGS),
/* perihp */
GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(5), 2, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 3, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
RK3399_CLKGATE_CON(20), 5, GFLAGS),
GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
RK3399_CLKGATE_CON(20), 6, GFLAGS),
GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
RK3399_CLKGATE_CON(20), 7, GFLAGS),
GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
RK3399_CLKGATE_CON(20), 8, GFLAGS),
GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
RK3399_CLKGATE_CON(20), 9, GFLAGS),
GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 13, GFLAGS),
GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 15, GFLAGS),
GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 4, GFLAGS),
GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
RK3399_CLKGATE_CON(20), 11, GFLAGS),
GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 14, GFLAGS),
GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
RK3399_CLKGATE_CON(31), 8, GFLAGS),
/* sdio & sdmmc */
COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 13, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
RK3399_CLKGATE_CON(33), 8, GFLAGS),
GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(33), 9, GFLAGS),
COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(6), 1, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
/* pcie */
COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(6), 2, GFLAGS),
COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 6, GFLAGS),
MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(6), 3, GFLAGS),
MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
/* emmc */
COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(6), 14, GFLAGS),
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 8, GFLAGS),
GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 9, GFLAGS),
GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 10, GFLAGS),
/* perilp0 */
GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(7), 1, GFLAGS),
GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(7), 2, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
RK3399_CLKGATE_CON(7), 3, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
RK3399_CLKGATE_CON(7), 4, GFLAGS),
/* aclk_perilp0 gates */
GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
/* hclk_perilp0 gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
/* pclk_perilp0 gates */
GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
/* crypto */
COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(7), 7, GFLAGS),
COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(7), 8, GFLAGS),
/* cm0s_perilp */
GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
RK3399_CLKGATE_CON(7), 6, GFLAGS),
GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
RK3399_CLKGATE_CON(7), 5, GFLAGS),
COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(7), 9, GFLAGS),
/* fclk_cm0s gates */
GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
/* perilp1 */
GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(8), 1, GFLAGS),
GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
RK3399_CLKGATE_CON(8), 2, GFLAGS),
/* hclk_perilp1 gates */
GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
/* pclk_perilp1 gates */
GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
/* saradc */
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
RK3399_CLKGATE_CON(9), 11, GFLAGS),
/* tsadc */
COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
RK3399_CLKGATE_CON(9), 10, GFLAGS),
/* cif_testout */
MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 14, GFLAGS),
MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 15, GFLAGS),
/* vio */
COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 1, GFLAGS),
GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(29), 0, GFLAGS),
GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
RK3399_CLKGATE_CON(29), 1, GFLAGS),
GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
RK3399_CLKGATE_CON(29), 2, GFLAGS),
GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(29), 12, GFLAGS),
/* hdcp */
COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 12, GFLAGS),
COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 3, GFLAGS),
COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 10, GFLAGS),
GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(29), 4, GFLAGS),
GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
RK3399_CLKGATE_CON(29), 10, GFLAGS),
GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(29), 5, GFLAGS),
GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
RK3399_CLKGATE_CON(29), 9, GFLAGS),
GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(29), 3, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
RK3399_CLKGATE_CON(29), 6, GFLAGS),
GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
RK3399_CLKGATE_CON(29), 7, GFLAGS),
GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
RK3399_CLKGATE_CON(29), 8, GFLAGS),
GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
RK3399_CLKGATE_CON(29), 11, GFLAGS),
/* edp */
COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 8, GFLAGS),
COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
RK3399_CLKGATE_CON(11), 11, GFLAGS),
GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 12, GFLAGS),
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
RK3399_CLKGATE_CON(32), 13, GFLAGS),
/* hdmi */
GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
RK3399_CLKGATE_CON(11), 6, GFLAGS),
COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
RK3399_CLKGATE_CON(11), 7, GFLAGS),
/* vop0 */
COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 8, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 9, GFLAGS),
GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
RK3399_CLKGATE_CON(28), 3, GFLAGS),
GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 1, GFLAGS),
GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
RK3399_CLKGATE_CON(28), 2, GFLAGS),
GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 0, GFLAGS),
COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
RK3399_CLKSEL_CON(106), 0,
&rk3399_dclk_vop0_fracmux),
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 14, GFLAGS),
/* vop1 */
COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 10, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 11, GFLAGS),
GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
RK3399_CLKGATE_CON(28), 7, GFLAGS),
GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 5, GFLAGS),
GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
RK3399_CLKGATE_CON(28), 6, GFLAGS),
GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 4, GFLAGS),
COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 13, GFLAGS),
COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
RK3399_CLKSEL_CON(107), 0,
&rk3399_dclk_vop1_fracmux),
COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 15, GFLAGS),
/* isp */
COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 8, GFLAGS),
COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 9, GFLAGS),
GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(27), 1, GFLAGS),
GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
RK3399_CLKGATE_CON(27), 5, GFLAGS),
GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
RK3399_CLKGATE_CON(27), 7, GFLAGS),
GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(27), 0, GFLAGS),
GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
RK3399_CLKGATE_CON(27), 4, GFLAGS),
COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 4, GFLAGS),
COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 10, GFLAGS),
COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 11, GFLAGS),
GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(27), 3, GFLAGS),
GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(27), 2, GFLAGS),
GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
RK3399_CLKGATE_CON(27), 8, GFLAGS),
COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 5, GFLAGS),
/*
* We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
* so we ignore the mux and make clocks nodes as following,
*
* pclkin_cifinv --|-------\
* |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
* pclkin_cif --|-------/
*/
GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
RK3399_CLKGATE_CON(27), 6, GFLAGS),
/* cif */
COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
RK3399_CLKGATE_CON(10), 7, GFLAGS),
COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
/* gic */
COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 12, GFLAGS),
GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
/* alive */
/* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
/* testout */
MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
RK3399_CLKSEL_CON(105), 0,
RK3399_CLKGATE_CON(13), 9, GFLAGS),
DIV(0, "clk_test_24m", "xin24m", 0,
RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
/* spi */
COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 12, GFLAGS),
COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 13, GFLAGS),
COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 14, GFLAGS),
COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3399_CLKGATE_CON(9), 15, GFLAGS),
COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3399_CLKGATE_CON(13), 13, GFLAGS),
/* i2c */
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(10), 0, GFLAGS),
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(10), 4, GFLAGS),
COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3399_CLKGATE_CON(10), 1, GFLAGS),
COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3399_CLKGATE_CON(10), 3, GFLAGS),
COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3399_CLKGATE_CON(10), 5, GFLAGS),
/* timer */
GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
/* clk_test */
/* clk_test_pre is controlled by CRU_MISC_CON[3] */
COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
RK3399_CLKGATE_CON(13), 11, GFLAGS),
/* ddrc */
GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
0, GFLAGS),
GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1, GFLAGS),
GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
2, GFLAGS),
GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
3, GFLAGS),
COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
};
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
/*
* PMU CRU Clock-Architecture
*/
GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
RK3399_PMU_CLKSEL_CON(7), 0,
&rk3399_pmuclk_wifi_fracmux),
MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
RK3399_PMU_CLKSEL_CON(6), 0,
RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
&rk3399_uart4_pmu_fracmux),
DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
/* pmu clock gates */
GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
};
static const char *const rk3399_cru_critical_clocks[] __initconst = {
"aclk_cci_pre",
"aclk_gic",
"aclk_gic_noc",
"aclk_hdcp_noc",
"hclk_hdcp_noc",
"pclk_hdcp_noc",
"pclk_perilp0",
"pclk_perilp0",
"hclk_perilp0",
"hclk_perilp0_noc",
"pclk_perilp1",
"pclk_perilp1_noc",
"pclk_perihp",
"pclk_perihp_noc",
"hclk_perihp",
"aclk_perihp",
"aclk_perihp_noc",
"aclk_perilp0",
"aclk_perilp0_noc",
"hclk_perilp1",
"hclk_perilp1_noc",
"aclk_dmac0_perilp",
"aclk_emmc_noc",
"gpll_hclk_perilp1_src",
"gpll_aclk_perilp0_src",
"gpll_aclk_perihp_src",
"aclk_vio_noc",
/* ddrc */
"sclk_ddrc",
"armclkl",
"armclkb",
};
static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
"ppll",
"pclk_pmu_src",
"fclk_cm0s_src_pmu",
"clk_timer_src_pmu",
"pclk_rkpwm_pmu",
};
static void __init rk3399_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3399_pll_clks,
ARRAY_SIZE(rk3399_pll_clks), -1);
rockchip_clk_register_branches(ctx, rk3399_clk_branches,
ARRAY_SIZE(rk3399_clk_branches));
rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
&rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
ARRAY_SIZE(rk3399_cpuclkl_rates));
rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
&rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
ARRAY_SIZE(rk3399_cpuclkb_rates));
rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
ARRAY_SIZE(rk3399_cru_critical_clocks));
rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
static void __init rk3399_pmu_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru pmu region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip pmu clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
ARRAY_SIZE(rk3399_clk_pmu_branches));
rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
ARRAY_SIZE(rk3399_pmucru_critical_clocks));
rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
struct clk_rk3399_inits {
void (*inits)(struct device_node *np);
};
static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
.inits = rk3399_pmu_clk_init,
};
static const struct clk_rk3399_inits clk_rk3399_cru_init = {
.inits = rk3399_clk_init,
};
static const struct of_device_id clk_rk3399_match_table[] = {
{
.compatible = "rockchip,rk3399-cru",
.data = &clk_rk3399_cru_init,
}, {
.compatible = "rockchip,rk3399-pmucru",
.data = &clk_rk3399_pmucru_init,
},
{ }
};
static int __init clk_rk3399_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
const struct clk_rk3399_inits *init_data;
match = of_match_device(clk_rk3399_match_table, &pdev->dev);
if (!match || !match->data)
return -EINVAL;
init_data = match->data;
if (init_data->inits)
init_data->inits(np);
return 0;
}
static struct platform_driver clk_rk3399_driver = {
.driver = {
.name = "clk-rk3399",
.of_match_table = clk_rk3399_match_table,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
| linux-master | drivers/clk/rockchip/clk-rk3399.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <[email protected]>
*/
#include <asm/div64.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/iopoll.h>
#include <linux/regmap.h>
#include <linux/clk.h>
#include "clk.h"
#define PLL_MODE_MASK 0x3
#define PLL_MODE_SLOW 0x0
#define PLL_MODE_NORM 0x1
#define PLL_MODE_DEEP 0x2
#define PLL_RK3328_MODE_MASK 0x1
struct rockchip_clk_pll {
struct clk_hw hw;
struct clk_mux pll_mux;
const struct clk_ops *pll_mux_ops;
struct notifier_block clk_nb;
void __iomem *reg_base;
int lock_offset;
unsigned int lock_shift;
enum rockchip_pll_type type;
u8 flags;
const struct rockchip_pll_rate_table *rate_table;
unsigned int rate_count;
spinlock_t *lock;
struct rockchip_clk_provider *ctx;
};
#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
#define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
struct rockchip_clk_pll *pll, unsigned long rate)
{
const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
int i;
for (i = 0; i < pll->rate_count; i++) {
if (rate == rate_table[i].rate)
return &rate_table[i];
}
return NULL;
}
static long rockchip_pll_round_rate(struct clk_hw *hw,
unsigned long drate, unsigned long *prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
int i;
/* Assumming rate_table is in descending order */
for (i = 0; i < pll->rate_count; i++) {
if (drate >= rate_table[i].rate)
return rate_table[i].rate;
}
/* return minimum supported value */
return rate_table[i - 1].rate;
}
/*
* Wait for the pll to reach the locked state.
* The calling set_rate function is responsible for making sure the
* grf regmap is available.
*/
static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
{
struct regmap *grf = pll->ctx->grf;
unsigned int val;
int ret;
ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
val & BIT(pll->lock_shift), 0, 1000);
if (ret)
pr_err("%s: timeout waiting for pll to lock\n", __func__);
return ret;
}
/*
* PLL used in RK3036
*/
#define RK3036_PLLCON(i) (i * 0x4)
#define RK3036_PLLCON0_FBDIV_MASK 0xfff
#define RK3036_PLLCON0_FBDIV_SHIFT 0
#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
#define RK3036_PLLCON1_REFDIV_MASK 0x3f
#define RK3036_PLLCON1_REFDIV_SHIFT 0
#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
#define RK3036_PLLCON1_LOCK_STATUS BIT(10)
#define RK3036_PLLCON1_DSMPD_MASK 0x1
#define RK3036_PLLCON1_DSMPD_SHIFT 12
#define RK3036_PLLCON1_PWRDOWN BIT(13)
#define RK3036_PLLCON2_FRAC_MASK 0xffffff
#define RK3036_PLLCON2_FRAC_SHIFT 0
static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
{
u32 pllcon;
int ret;
/*
* Lock time typical 250, max 500 input clock cycles @24MHz
* So define a very safe maximum of 1000us, meaning 24000 cycles.
*/
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
pllcon,
pllcon & RK3036_PLLCON1_LOCK_STATUS,
0, 1000);
if (ret)
pr_err("%s: timeout waiting for pll to lock\n", __func__);
return ret;
}
static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
struct rockchip_pll_rate_table *rate)
{
u32 pllcon;
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
& RK3036_PLLCON0_FBDIV_MASK);
rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
& RK3036_PLLCON0_POSTDIV1_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
& RK3036_PLLCON1_REFDIV_MASK);
rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
& RK3036_PLLCON1_POSTDIV2_MASK);
rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
& RK3036_PLLCON1_DSMPD_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
& RK3036_PLLCON2_FRAC_MASK);
}
static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
struct rockchip_pll_rate_table cur;
u64 rate64 = prate;
rockchip_rk3036_pll_get_params(pll, &cur);
rate64 *= cur.fbdiv;
do_div(rate64, cur.refdiv);
if (cur.dsmpd == 0) {
/* fractional mode */
u64 frac_rate64 = prate * cur.frac;
do_div(frac_rate64, cur.refdiv);
rate64 += frac_rate64 >> 24;
}
do_div(rate64, cur.postdiv1);
do_div(rate64, cur.postdiv2);
return (unsigned long)rate64;
}
static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
const struct rockchip_pll_rate_table *rate)
{
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
struct clk_mux *pll_mux = &pll->pll_mux;
struct rockchip_pll_rate_table cur;
u32 pllcon;
int rate_change_remuxed = 0;
int cur_parent;
int ret;
pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
__func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
rate->postdiv2, rate->dsmpd, rate->frac);
rockchip_rk3036_pll_get_params(pll, &cur);
cur.rate = 0;
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
if (cur_parent == PLL_MODE_NORM) {
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
rate_change_remuxed = 1;
}
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
RK3036_PLLCON0_FBDIV_SHIFT) |
HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
RK3036_PLLCON0_POSTDIV1_SHIFT),
pll->reg_base + RK3036_PLLCON(0));
writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
RK3036_PLLCON1_REFDIV_SHIFT) |
HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
RK3036_PLLCON1_POSTDIV2_SHIFT) |
HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
RK3036_PLLCON1_DSMPD_SHIFT),
pll->reg_base + RK3036_PLLCON(1));
/* GPLL CON2 is not HIWORD_MASK */
pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
/* wait for the pll to lock */
ret = rockchip_rk3036_pll_wait_lock(pll);
if (ret) {
pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
__func__);
rockchip_rk3036_pll_set_params(pll, &cur);
}
if (rate_change_remuxed)
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
return ret;
}
static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
__func__, __clk_get_name(hw->clk), drate, prate);
/* Get required rate settings from table */
rate = rockchip_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, __clk_get_name(hw->clk));
return -EINVAL;
}
return rockchip_rk3036_pll_set_params(pll, rate);
}
static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3036_PLLCON(1));
rockchip_rk3036_pll_wait_lock(pll);
return 0;
}
static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
RK3036_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3036_PLLCON(1));
}
static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
return !(pllcon & RK3036_PLLCON1_PWRDOWN);
}
static int rockchip_rk3036_pll_init(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
struct rockchip_pll_rate_table cur;
unsigned long drate;
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
return 0;
drate = clk_hw_get_rate(hw);
rate = rockchip_get_pll_settings(pll, drate);
/* when no rate setting for the current rate, rely on clk_set_rate */
if (!rate)
return 0;
rockchip_rk3036_pll_get_params(pll, &cur);
pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
drate);
pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
cur.dsmpd, cur.frac);
pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
rate->dsmpd, rate->frac);
if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
rate->dsmpd != cur.dsmpd ||
(!cur.dsmpd && (rate->frac != cur.frac))) {
struct clk *parent = clk_get_parent(hw->clk);
if (!parent) {
pr_warn("%s: parent of %s not available\n",
__func__, __clk_get_name(hw->clk));
return 0;
}
pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
__func__, __clk_get_name(hw->clk));
rockchip_rk3036_pll_set_params(pll, rate);
}
return 0;
}
static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
.recalc_rate = rockchip_rk3036_pll_recalc_rate,
.enable = rockchip_rk3036_pll_enable,
.disable = rockchip_rk3036_pll_disable,
.is_enabled = rockchip_rk3036_pll_is_enabled,
};
static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
.recalc_rate = rockchip_rk3036_pll_recalc_rate,
.round_rate = rockchip_pll_round_rate,
.set_rate = rockchip_rk3036_pll_set_rate,
.enable = rockchip_rk3036_pll_enable,
.disable = rockchip_rk3036_pll_disable,
.is_enabled = rockchip_rk3036_pll_is_enabled,
.init = rockchip_rk3036_pll_init,
};
/*
* PLL used in RK3066, RK3188 and RK3288
*/
#define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
#define RK3066_PLLCON(i) (i * 0x4)
#define RK3066_PLLCON0_OD_MASK 0xf
#define RK3066_PLLCON0_OD_SHIFT 0
#define RK3066_PLLCON0_NR_MASK 0x3f
#define RK3066_PLLCON0_NR_SHIFT 8
#define RK3066_PLLCON1_NF_MASK 0x1fff
#define RK3066_PLLCON1_NF_SHIFT 0
#define RK3066_PLLCON2_NB_MASK 0xfff
#define RK3066_PLLCON2_NB_SHIFT 0
#define RK3066_PLLCON3_RESET (1 << 5)
#define RK3066_PLLCON3_PWRDOWN (1 << 1)
#define RK3066_PLLCON3_BYPASS (1 << 0)
static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
struct rockchip_pll_rate_table *rate)
{
u32 pllcon;
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
& RK3066_PLLCON0_NR_MASK) + 1;
rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
& RK3066_PLLCON0_OD_MASK) + 1;
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
& RK3066_PLLCON1_NF_MASK) + 1;
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
& RK3066_PLLCON2_NB_MASK) + 1;
}
static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
struct rockchip_pll_rate_table cur;
u64 rate64 = prate;
u32 pllcon;
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
if (pllcon & RK3066_PLLCON3_BYPASS) {
pr_debug("%s: pll %s is bypassed\n", __func__,
clk_hw_get_name(hw));
return prate;
}
rockchip_rk3066_pll_get_params(pll, &cur);
rate64 *= cur.nf;
do_div(rate64, cur.nr);
do_div(rate64, cur.no);
return (unsigned long)rate64;
}
static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
const struct rockchip_pll_rate_table *rate)
{
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
struct clk_mux *pll_mux = &pll->pll_mux;
struct rockchip_pll_rate_table cur;
int rate_change_remuxed = 0;
int cur_parent;
int ret;
pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
__func__, rate->rate, rate->nr, rate->no, rate->nf);
rockchip_rk3066_pll_get_params(pll, &cur);
cur.rate = 0;
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
if (cur_parent == PLL_MODE_NORM) {
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
rate_change_remuxed = 1;
}
/* enter reset mode */
writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
pll->reg_base + RK3066_PLLCON(3));
/* update pll values */
writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
RK3066_PLLCON0_NR_SHIFT) |
HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
RK3066_PLLCON0_OD_SHIFT),
pll->reg_base + RK3066_PLLCON(0));
writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
RK3066_PLLCON1_NF_SHIFT),
pll->reg_base + RK3066_PLLCON(1));
writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
RK3066_PLLCON2_NB_SHIFT),
pll->reg_base + RK3066_PLLCON(2));
/* leave reset and wait the reset_delay */
writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
pll->reg_base + RK3066_PLLCON(3));
udelay(RK3066_PLL_RESET_DELAY(rate->nr));
/* wait for the pll to lock */
ret = rockchip_pll_wait_lock(pll);
if (ret) {
pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
__func__);
rockchip_rk3066_pll_set_params(pll, &cur);
}
if (rate_change_remuxed)
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
return ret;
}
static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
__func__, clk_hw_get_name(hw), drate, prate);
/* Get required rate settings from table */
rate = rockchip_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
return rockchip_rk3066_pll_set_params(pll, rate);
}
static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
pll->reg_base + RK3066_PLLCON(3));
rockchip_pll_wait_lock(pll);
return 0;
}
static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
RK3066_PLLCON3_PWRDOWN, 0),
pll->reg_base + RK3066_PLLCON(3));
}
static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
return !(pllcon & RK3066_PLLCON3_PWRDOWN);
}
static int rockchip_rk3066_pll_init(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
struct rockchip_pll_rate_table cur;
unsigned long drate;
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
return 0;
drate = clk_hw_get_rate(hw);
rate = rockchip_get_pll_settings(pll, drate);
/* when no rate setting for the current rate, rely on clk_set_rate */
if (!rate)
return 0;
rockchip_rk3066_pll_get_params(pll, &cur);
pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
__func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
|| rate->nb != cur.nb) {
pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
__func__, clk_hw_get_name(hw));
rockchip_rk3066_pll_set_params(pll, rate);
}
return 0;
}
static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
.recalc_rate = rockchip_rk3066_pll_recalc_rate,
.enable = rockchip_rk3066_pll_enable,
.disable = rockchip_rk3066_pll_disable,
.is_enabled = rockchip_rk3066_pll_is_enabled,
};
static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
.recalc_rate = rockchip_rk3066_pll_recalc_rate,
.round_rate = rockchip_pll_round_rate,
.set_rate = rockchip_rk3066_pll_set_rate,
.enable = rockchip_rk3066_pll_enable,
.disable = rockchip_rk3066_pll_disable,
.is_enabled = rockchip_rk3066_pll_is_enabled,
.init = rockchip_rk3066_pll_init,
};
/*
* PLL used in RK3399
*/
#define RK3399_PLLCON(i) (i * 0x4)
#define RK3399_PLLCON0_FBDIV_MASK 0xfff
#define RK3399_PLLCON0_FBDIV_SHIFT 0
#define RK3399_PLLCON1_REFDIV_MASK 0x3f
#define RK3399_PLLCON1_REFDIV_SHIFT 0
#define RK3399_PLLCON1_POSTDIV1_MASK 0x7
#define RK3399_PLLCON1_POSTDIV1_SHIFT 8
#define RK3399_PLLCON1_POSTDIV2_MASK 0x7
#define RK3399_PLLCON1_POSTDIV2_SHIFT 12
#define RK3399_PLLCON2_FRAC_MASK 0xffffff
#define RK3399_PLLCON2_FRAC_SHIFT 0
#define RK3399_PLLCON2_LOCK_STATUS BIT(31)
#define RK3399_PLLCON3_PWRDOWN BIT(0)
#define RK3399_PLLCON3_DSMPD_MASK 0x1
#define RK3399_PLLCON3_DSMPD_SHIFT 3
static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
{
u32 pllcon;
int ret;
/*
* Lock time typical 250, max 500 input clock cycles @24MHz
* So define a very safe maximum of 1000us, meaning 24000 cycles.
*/
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
pllcon,
pllcon & RK3399_PLLCON2_LOCK_STATUS,
0, 1000);
if (ret)
pr_err("%s: timeout waiting for pll to lock\n", __func__);
return ret;
}
static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
struct rockchip_pll_rate_table *rate)
{
u32 pllcon;
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
& RK3399_PLLCON0_FBDIV_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
& RK3399_PLLCON1_REFDIV_MASK);
rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
& RK3399_PLLCON1_POSTDIV1_MASK);
rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
& RK3399_PLLCON1_POSTDIV2_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
& RK3399_PLLCON2_FRAC_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
& RK3399_PLLCON3_DSMPD_MASK);
}
static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
struct rockchip_pll_rate_table cur;
u64 rate64 = prate;
rockchip_rk3399_pll_get_params(pll, &cur);
rate64 *= cur.fbdiv;
do_div(rate64, cur.refdiv);
if (cur.dsmpd == 0) {
/* fractional mode */
u64 frac_rate64 = prate * cur.frac;
do_div(frac_rate64, cur.refdiv);
rate64 += frac_rate64 >> 24;
}
do_div(rate64, cur.postdiv1);
do_div(rate64, cur.postdiv2);
return (unsigned long)rate64;
}
static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
const struct rockchip_pll_rate_table *rate)
{
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
struct clk_mux *pll_mux = &pll->pll_mux;
struct rockchip_pll_rate_table cur;
u32 pllcon;
int rate_change_remuxed = 0;
int cur_parent;
int ret;
pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
__func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
rate->postdiv2, rate->dsmpd, rate->frac);
rockchip_rk3399_pll_get_params(pll, &cur);
cur.rate = 0;
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
if (cur_parent == PLL_MODE_NORM) {
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
rate_change_remuxed = 1;
}
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
RK3399_PLLCON0_FBDIV_SHIFT),
pll->reg_base + RK3399_PLLCON(0));
writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
RK3399_PLLCON1_REFDIV_SHIFT) |
HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
RK3399_PLLCON1_POSTDIV1_SHIFT) |
HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
RK3399_PLLCON1_POSTDIV2_SHIFT),
pll->reg_base + RK3399_PLLCON(1));
/* xPLL CON2 is not HIWORD_MASK */
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
RK3399_PLLCON3_DSMPD_SHIFT),
pll->reg_base + RK3399_PLLCON(3));
/* wait for the pll to lock */
ret = rockchip_rk3399_pll_wait_lock(pll);
if (ret) {
pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
__func__);
rockchip_rk3399_pll_set_params(pll, &cur);
}
if (rate_change_remuxed)
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
return ret;
}
static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
__func__, __clk_get_name(hw->clk), drate, prate);
/* Get required rate settings from table */
rate = rockchip_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, __clk_get_name(hw->clk));
return -EINVAL;
}
return rockchip_rk3399_pll_set_params(pll, rate);
}
static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
pll->reg_base + RK3399_PLLCON(3));
rockchip_rk3399_pll_wait_lock(pll);
return 0;
}
static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
RK3399_PLLCON3_PWRDOWN, 0),
pll->reg_base + RK3399_PLLCON(3));
}
static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
return !(pllcon & RK3399_PLLCON3_PWRDOWN);
}
static int rockchip_rk3399_pll_init(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
struct rockchip_pll_rate_table cur;
unsigned long drate;
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
return 0;
drate = clk_hw_get_rate(hw);
rate = rockchip_get_pll_settings(pll, drate);
/* when no rate setting for the current rate, rely on clk_set_rate */
if (!rate)
return 0;
rockchip_rk3399_pll_get_params(pll, &cur);
pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
drate);
pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
cur.dsmpd, cur.frac);
pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
rate->dsmpd, rate->frac);
if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
rate->dsmpd != cur.dsmpd ||
(!cur.dsmpd && (rate->frac != cur.frac))) {
struct clk *parent = clk_get_parent(hw->clk);
if (!parent) {
pr_warn("%s: parent of %s not available\n",
__func__, __clk_get_name(hw->clk));
return 0;
}
pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
__func__, __clk_get_name(hw->clk));
rockchip_rk3399_pll_set_params(pll, rate);
}
return 0;
}
static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
.recalc_rate = rockchip_rk3399_pll_recalc_rate,
.enable = rockchip_rk3399_pll_enable,
.disable = rockchip_rk3399_pll_disable,
.is_enabled = rockchip_rk3399_pll_is_enabled,
};
static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
.recalc_rate = rockchip_rk3399_pll_recalc_rate,
.round_rate = rockchip_pll_round_rate,
.set_rate = rockchip_rk3399_pll_set_rate,
.enable = rockchip_rk3399_pll_enable,
.disable = rockchip_rk3399_pll_disable,
.is_enabled = rockchip_rk3399_pll_is_enabled,
.init = rockchip_rk3399_pll_init,
};
/*
* PLL used in RK3588
*/
#define RK3588_PLLCON(i) (i * 0x4)
#define RK3588_PLLCON0_M_MASK 0x3ff
#define RK3588_PLLCON0_M_SHIFT 0
#define RK3588_PLLCON1_P_MASK 0x3f
#define RK3588_PLLCON1_P_SHIFT 0
#define RK3588_PLLCON1_S_MASK 0x7
#define RK3588_PLLCON1_S_SHIFT 6
#define RK3588_PLLCON2_K_MASK 0xffff
#define RK3588_PLLCON2_K_SHIFT 0
#define RK3588_PLLCON1_PWRDOWN BIT(13)
#define RK3588_PLLCON6_LOCK_STATUS BIT(15)
static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
{
u32 pllcon;
int ret;
/*
* Lock time typical 250, max 500 input clock cycles @24MHz
* So define a very safe maximum of 1000us, meaning 24000 cycles.
*/
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
pllcon,
pllcon & RK3588_PLLCON6_LOCK_STATUS,
0, 1000);
if (ret)
pr_err("%s: timeout waiting for pll to lock\n", __func__);
return ret;
}
static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
struct rockchip_pll_rate_table *rate)
{
u32 pllcon;
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));
rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK);
rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK);
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
}
static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
struct rockchip_pll_rate_table cur;
u64 rate64 = prate, postdiv;
rockchip_rk3588_pll_get_params(pll, &cur);
rate64 *= cur.m;
do_div(rate64, cur.p);
if (cur.k) {
/* fractional mode */
u64 frac_rate64 = prate * cur.k;
postdiv = cur.p * 65535;
do_div(frac_rate64, postdiv);
rate64 += frac_rate64;
}
rate64 = rate64 >> cur.s;
return (unsigned long)rate64;
}
static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
const struct rockchip_pll_rate_table *rate)
{
const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
struct clk_mux *pll_mux = &pll->pll_mux;
struct rockchip_pll_rate_table cur;
int rate_change_remuxed = 0;
int cur_parent;
int ret;
pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
__func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
rockchip_rk3588_pll_get_params(pll, &cur);
cur.rate = 0;
if (pll->type == pll_rk3588) {
cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
if (cur_parent == PLL_MODE_NORM) {
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
rate_change_remuxed = 1;
}
}
/* set pll power down */
writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
RK3588_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3399_PLLCON(1));
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),
pll->reg_base + RK3399_PLLCON(0));
writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |
HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),
pll->reg_base + RK3399_PLLCON(1));
writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
pll->reg_base + RK3399_PLLCON(2));
/* set pll power up */
writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3588_PLLCON(1));
/* wait for the pll to lock */
ret = rockchip_rk3588_pll_wait_lock(pll);
if (ret) {
pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
__func__);
rockchip_rk3588_pll_set_params(pll, &cur);
}
if ((pll->type == pll_rk3588) && rate_change_remuxed)
pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
return ret;
}
static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate;
pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
__func__, __clk_get_name(hw->clk), drate, prate);
/* Get required rate settings from table */
rate = rockchip_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, __clk_get_name(hw->clk));
return -EINVAL;
}
return rockchip_rk3588_pll_set_params(pll, rate);
}
static int rockchip_rk3588_pll_enable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3588_PLLCON(1));
rockchip_rk3588_pll_wait_lock(pll);
return 0;
}
static void rockchip_rk3588_pll_disable(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0),
pll->reg_base + RK3588_PLLCON(1));
}
static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));
return !(pllcon & RK3588_PLLCON1_PWRDOWN);
}
static int rockchip_rk3588_pll_init(struct clk_hw *hw)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
return 0;
return 0;
}
static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = {
.recalc_rate = rockchip_rk3588_pll_recalc_rate,
.enable = rockchip_rk3588_pll_enable,
.disable = rockchip_rk3588_pll_disable,
.is_enabled = rockchip_rk3588_pll_is_enabled,
};
static const struct clk_ops rockchip_rk3588_pll_clk_ops = {
.recalc_rate = rockchip_rk3588_pll_recalc_rate,
.round_rate = rockchip_pll_round_rate,
.set_rate = rockchip_rk3588_pll_set_rate,
.enable = rockchip_rk3588_pll_enable,
.disable = rockchip_rk3588_pll_disable,
.is_enabled = rockchip_rk3588_pll_is_enabled,
.init = rockchip_rk3588_pll_init,
};
/*
* Common registering of pll clocks
*/
struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
enum rockchip_pll_type pll_type,
const char *name, const char *const *parent_names,
u8 num_parents, int con_offset, int grf_lock_offset,
int lock_shift, int mode_offset, int mode_shift,
struct rockchip_pll_rate_table *rate_table,
unsigned long flags, u8 clk_pll_flags)
{
const char *pll_parents[3];
struct clk_init_data init;
struct rockchip_clk_pll *pll;
struct clk_mux *pll_mux;
struct clk *pll_clk, *mux_clk;
char pll_name[20];
if ((pll_type != pll_rk3328 && num_parents != 2) ||
(pll_type == pll_rk3328 && num_parents != 1)) {
pr_err("%s: needs two parent clocks\n", __func__);
return ERR_PTR(-EINVAL);
}
/* name the actual pll */
snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
/* create the mux on top of the real pll */
pll->pll_mux_ops = &clk_mux_ops;
pll_mux = &pll->pll_mux;
pll_mux->reg = ctx->reg_base + mode_offset;
pll_mux->shift = mode_shift;
if (pll_type == pll_rk3328)
pll_mux->mask = PLL_RK3328_MODE_MASK;
else
pll_mux->mask = PLL_MODE_MASK;
pll_mux->flags = 0;
pll_mux->lock = &ctx->lock;
pll_mux->hw.init = &init;
if (pll_type == pll_rk3036 ||
pll_type == pll_rk3066 ||
pll_type == pll_rk3328 ||
pll_type == pll_rk3399 ||
pll_type == pll_rk3588)
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
/* the actual muxing is xin24m, pll-output, xin32k */
pll_parents[0] = parent_names[0];
pll_parents[1] = pll_name;
pll_parents[2] = parent_names[1];
init.name = name;
init.flags = CLK_SET_RATE_PARENT;
init.ops = pll->pll_mux_ops;
init.parent_names = pll_parents;
if (pll_type == pll_rk3328)
init.num_parents = 2;
else
init.num_parents = ARRAY_SIZE(pll_parents);
mux_clk = clk_register(NULL, &pll_mux->hw);
if (IS_ERR(mux_clk))
goto err_mux;
/* now create the actual pll */
init.name = pll_name;
/* keep all plls untouched for now */
init.flags = flags | CLK_IGNORE_UNUSED;
init.parent_names = &parent_names[0];
init.num_parents = 1;
if (rate_table) {
int len;
/* find count of rates in rate_table */
for (len = 0; rate_table[len].rate != 0; )
len++;
pll->rate_count = len;
pll->rate_table = kmemdup(rate_table,
pll->rate_count *
sizeof(struct rockchip_pll_rate_table),
GFP_KERNEL);
WARN(!pll->rate_table,
"%s: could not allocate rate table for %s\n",
__func__, name);
}
switch (pll_type) {
case pll_rk3036:
case pll_rk3328:
if (!pll->rate_table)
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3036_pll_clk_ops;
break;
case pll_rk3066:
if (!pll->rate_table || IS_ERR(ctx->grf))
init.ops = &rockchip_rk3066_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3066_pll_clk_ops;
break;
case pll_rk3399:
if (!pll->rate_table)
init.ops = &rockchip_rk3399_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3399_pll_clk_ops;
break;
case pll_rk3588:
case pll_rk3588_core:
if (!pll->rate_table)
init.ops = &rockchip_rk3588_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3588_pll_clk_ops;
init.flags = flags;
break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, name);
}
pll->hw.init = &init;
pll->type = pll_type;
pll->reg_base = ctx->reg_base + con_offset;
pll->lock_offset = grf_lock_offset;
pll->lock_shift = lock_shift;
pll->flags = clk_pll_flags;
pll->lock = &ctx->lock;
pll->ctx = ctx;
pll_clk = clk_register(NULL, &pll->hw);
if (IS_ERR(pll_clk)) {
pr_err("%s: failed to register pll clock %s : %ld\n",
__func__, name, PTR_ERR(pll_clk));
goto err_pll;
}
return mux_clk;
err_pll:
kfree(pll->rate_table);
clk_unregister(mux_clk);
mux_clk = pll_clk;
err_mux:
kfree(pll);
return mux_clk;
}
| linux-master | drivers/clk/rockchip/clk-pll.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang<[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/px30-cru.h>
#include "clk.h"
#define PX30_GRF_SOC_STATUS0 0x480
enum px30_plls {
apll, dpll, cpll, npll, apll_b_h, apll_b_l,
};
enum px30_pmu_plls {
gpll,
};
static struct rockchip_pll_rate_table px30_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define PX30_DIV_ACLKM_MASK 0x7
#define PX30_DIV_ACLKM_SHIFT 12
#define PX30_DIV_PCLK_DBG_MASK 0xf
#define PX30_DIV_PCLK_DBG_SHIFT 8
#define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \
{ \
.reg = PX30_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
PX30_DIV_ACLKM_SHIFT) | \
HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
PX30_DIV_PCLK_DBG_SHIFT), \
}
#define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
{ \
.prate = _prate, \
.divs = { \
PX30_CLKSEL0(_aclk_core, _pclk_dbg), \
}, \
}
static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
PX30_CPUCLK_RATE(1608000000, 1, 7),
PX30_CPUCLK_RATE(1584000000, 1, 7),
PX30_CPUCLK_RATE(1560000000, 1, 7),
PX30_CPUCLK_RATE(1536000000, 1, 7),
PX30_CPUCLK_RATE(1512000000, 1, 7),
PX30_CPUCLK_RATE(1488000000, 1, 5),
PX30_CPUCLK_RATE(1464000000, 1, 5),
PX30_CPUCLK_RATE(1440000000, 1, 5),
PX30_CPUCLK_RATE(1416000000, 1, 5),
PX30_CPUCLK_RATE(1392000000, 1, 5),
PX30_CPUCLK_RATE(1368000000, 1, 5),
PX30_CPUCLK_RATE(1344000000, 1, 5),
PX30_CPUCLK_RATE(1320000000, 1, 5),
PX30_CPUCLK_RATE(1296000000, 1, 5),
PX30_CPUCLK_RATE(1272000000, 1, 5),
PX30_CPUCLK_RATE(1248000000, 1, 5),
PX30_CPUCLK_RATE(1224000000, 1, 5),
PX30_CPUCLK_RATE(1200000000, 1, 5),
PX30_CPUCLK_RATE(1104000000, 1, 5),
PX30_CPUCLK_RATE(1008000000, 1, 5),
PX30_CPUCLK_RATE(912000000, 1, 5),
PX30_CPUCLK_RATE(816000000, 1, 3),
PX30_CPUCLK_RATE(696000000, 1, 3),
PX30_CPUCLK_RATE(600000000, 1, 3),
PX30_CPUCLK_RATE(408000000, 1, 1),
PX30_CPUCLK_RATE(312000000, 1, 1),
PX30_CPUCLK_RATE(216000000, 1, 1),
PX30_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
.core_reg[0] = PX30_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0xf,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 7,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "xin24m"};
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"};
PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"};
PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" };
static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0, PX30_PLL_CON(0),
PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, PX30_PLL_CON(8),
PX30_MODE_CON, 4, 1, 0, NULL),
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0, PX30_PLL_CON(16),
PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
0, PX30_PLL_CON(24),
PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
};
static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
PX30_MODE_CON, 8, 2, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/*
* Clock-Architecture Diagram 3
*/
/* PD_CORE */
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
PX30_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
PX30_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(17), 5, GFLAGS),
GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 5, GFLAGS),
GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(17), 6, GFLAGS),
GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 3, GFLAGS),
GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
PX30_CLKGATE_CON(17), 4, GFLAGS),
/* PD_GPU */
COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0,
PX30_CLKSEL_CON(1), 6, 2, MFLAGS,
PX30_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0,
PX30_CLKSEL_CON(1), 0, 4, DFLAGS,
PX30_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0,
PX30_CLKSEL_CON(1), 8, 4, DFLAGS,
PX30_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(1), 15, 1, MFLAGS,
PX30_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
PX30_CLKGATE_CON(17), 10, GFLAGS),
GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 11, GFLAGS),
GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(17), 8, GFLAGS),
GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(17), 9, GFLAGS),
/*
* Clock-Architecture Diagram 4
*/
/* PD_DDR */
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 7, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
PX30_CLKGATE_CON(1), 13, GFLAGS),
GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 15, GFLAGS),
GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 8, GFLAGS),
GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 5, GFLAGS),
GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 6, GFLAGS),
GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 6, GFLAGS),
GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 11, GFLAGS),
GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
PX30_CLKGATE_CON(1), 1, GFLAGS),
GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 10, GFLAGS),
GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 7, GFLAGS),
GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 9, GFLAGS),
GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 12, GFLAGS),
GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 14, GFLAGS),
GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(1), 3, GFLAGS),
/*
* Clock-Architecture Diagram 5
*/
/* PD_VI */
COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(4), 8, GFLAGS),
COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0,
PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
PX30_CLKGATE_CON(4), 12, GFLAGS),
COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(4), 9, GFLAGS),
COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
PX30_CLKGATE_CON(4), 11, GFLAGS),
GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
PX30_CLKGATE_CON(4), 13, GFLAGS),
GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
PX30_CLKGATE_CON(4), 14, GFLAGS),
/*
* Clock-Architecture Diagram 6
*/
/* PD_VO */
COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0,
PX30_CLKSEL_CON(3), 8, 4, DFLAGS,
PX30_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0,
PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
PX30_CLKGATE_CON(2), 13, GFLAGS),
COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(2), 5, GFLAGS),
COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(6), 0,
PX30_CLKGATE_CON(2), 3, GFLAGS,
&px30_dclk_vopb_fracmux),
GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(9), 0,
PX30_CLKGATE_CON(2), 7, GFLAGS,
&px30_dclk_vopl_fracmux),
GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 8, GFLAGS),
/* PD_VPU */
COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(4), 0, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
PX30_CLKSEL_CON(10), 8, 4, DFLAGS,
PX30_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
PX30_CLKGATE_CON(4), 1, GFLAGS),
/*
* Clock-Architecture Diagram 7
*/
COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0,
PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
PX30_CLKGATE_CON(5), 7, GFLAGS),
COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
PX30_CLKGATE_CON(5), 8, GFLAGS),
DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
/* PD_MMC_NAND */
GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
PX30_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(5), 11, GFLAGS),
COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
PX30_CLKGATE_CON(5), 12, GFLAGS),
COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
PX30_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
mux_gpll_cpll_npll_xin24m_p, 0,
PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
PX30_CLKGATE_CON(6), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
PX30_CLKGATE_CON(6), 3, GFLAGS),
COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
PX30_CLKGATE_CON(6), 5, GFLAGS),
COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
PX30_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(6), 7, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
PX30_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
PX30_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
PX30_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
PX30_SDIO_CON1, 1),
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
PX30_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
PX30_EMMC_CON1, 1),
/* PD_SDCARD */
GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
PX30_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(6), 13, GFLAGS),
COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
PX30_CLKGATE_CON(6), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
PX30_CLKGATE_CON(6), 15, GFLAGS),
/* PD_USB */
GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0,
PX30_CLKGATE_CON(7), 2, GFLAGS),
GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
PX30_CLKGATE_CON(7), 3, GFLAGS),
/* PD_GMAC */
COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
PX30_CLKGATE_CON(7), 11, GFLAGS),
MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0,
PX30_CLKGATE_CON(7), 15, GFLAGS),
GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0,
PX30_CLKGATE_CON(7), 13, GFLAGS),
FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
PX30_CLKGATE_CON(7), 10, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
PX30_CLKSEL_CON(23), 0, 4, DFLAGS,
PX30_CLKGATE_CON(7), 12, GFLAGS),
COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
PX30_CLKGATE_CON(8), 5, GFLAGS),
/*
* Clock-Architecture Diagram 8
*/
/* PD_BUS */
COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
PX30_CLKGATE_CON(8), 6, GFLAGS),
COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
PX30_CLKGATE_CON(8), 8, GFLAGS),
COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
PX30_CLKGATE_CON(8), 7, GFLAGS),
COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
PX30_CLKGATE_CON(8), 9, GFLAGS),
GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(8), 10, GFLAGS),
COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(9), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(27), 0,
PX30_CLKGATE_CON(9), 10, GFLAGS,
&px30_pdm_fracmux),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(9), 11, GFLAGS),
COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(9), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(29), 0,
PX30_CLKGATE_CON(9), 13, GFLAGS,
&px30_i2s0_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
PX30_CLKGATE_CON(9), 14, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0,
PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
PX30_CLKGATE_CON(9), 15, GFLAGS),
GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(17), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(59), 0,
PX30_CLKGATE_CON(17), 1, GFLAGS,
&px30_i2s0_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
PX30_CLKGATE_CON(17), 2, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
PX30_CLKGATE_CON(17), 3, GFLAGS),
GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(10), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(31), 0,
PX30_CLKGATE_CON(10), 1, GFLAGS,
&px30_i2s1_fracmux),
GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
PX30_CLKGATE_CON(10), 3, GFLAGS),
GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(10), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(33), 0,
PX30_CLKGATE_CON(10), 5, GFLAGS,
&px30_i2s2_fracmux),
GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
PX30_CLKGATE_CON(10), 7, GFLAGS),
GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
PX30_CLKGATE_CON(10), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(36), 0,
PX30_CLKGATE_CON(10), 14, GFLAGS,
&px30_uart1_fracmux),
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 15, GFLAGS),
COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 0, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(39), 0,
PX30_CLKGATE_CON(11), 2, GFLAGS,
&px30_uart2_fracmux),
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 3, GFLAGS),
COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 4, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(42), 0,
PX30_CLKGATE_CON(11), 6, GFLAGS,
&px30_uart3_fracmux),
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 7, GFLAGS),
COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 8, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(45), 0,
PX30_CLKGATE_CON(11), 10, GFLAGS,
&px30_uart4_fracmux),
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 11, GFLAGS),
COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 12, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
PX30_CLKGATE_CON(11), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(48), 0,
PX30_CLKGATE_CON(11), 14, GFLAGS,
&px30_uart5_fracmux),
GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 15, GFLAGS),
COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(12), 0, GFLAGS),
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
PX30_CLKGATE_CON(12), 1, GFLAGS),
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(12), 2, GFLAGS),
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
PX30_CLKGATE_CON(12), 3, GFLAGS),
COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(12), 5, GFLAGS),
COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
PX30_CLKGATE_CON(12), 6, GFLAGS),
COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
PX30_CLKGATE_CON(12), 7, GFLAGS),
COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
PX30_CLKGATE_CON(12), 8, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
PX30_CLKGATE_CON(13), 0, GFLAGS),
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
PX30_CLKGATE_CON(13), 1, GFLAGS),
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
PX30_CLKGATE_CON(13), 2, GFLAGS),
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
PX30_CLKGATE_CON(13), 3, GFLAGS),
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
PX30_CLKGATE_CON(13), 4, GFLAGS),
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
PX30_CLKGATE_CON(13), 5, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
PX30_CLKSEL_CON(54), 0, 11, DFLAGS,
PX30_CLKGATE_CON(12), 9, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
PX30_CLKGATE_CON(12), 10, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
PX30_CLKGATE_CON(13), 6, GFLAGS),
GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(12), 12, GFLAGS),
/* PD_CRYPTO */
GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0,
PX30_CLKGATE_CON(8), 12, GFLAGS),
GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0,
PX30_CLKGATE_CON(8), 13, GFLAGS),
COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
PX30_CLKGATE_CON(8), 14, GFLAGS),
COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS,
PX30_CLKGATE_CON(8), 15, GFLAGS),
/*
* Clock-Architecture Diagram 9
*/
/* PD_BUS_TOP */
GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 6, GFLAGS),
GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
/* PD_VI */
GATE(0, "aclk_vi_niu", "aclk_vi_pre", 0, PX30_CLKGATE_CON(4), 15, GFLAGS),
GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
GATE(0, "hclk_vi_niu", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 0, GFLAGS),
GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
/* PD_VO */
GATE(0, "aclk_vo_niu", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 0, GFLAGS),
GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
GATE(0, "hclk_vo_niu", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 1, GFLAGS),
GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
GATE(0, "pclk_vo_niu", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 2, GFLAGS),
GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
/* PD_BUS */
GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
/* PD_VPU */
GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
/* PD_CRYPTO */
GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
/* PD_SDCARD */
GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
/* PD_PERI */
GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS),
/* PD_MMC_NAND */
GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
/* PD_USB */
GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS),
GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
/* PD_GMAC */
GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(8), 0, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
PX30_CLKGATE_CON(8), 2, GFLAGS),
GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
PX30_CLKGATE_CON(8), 3, GFLAGS),
};
static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
*/
COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
PX30_PMU_CLKSEL_CON(1), 0,
PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
&px30_rtc32k_pmu_fracmux),
COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
PX30_PMU_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,
PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(5), 0,
PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
&px30_uart0_pmu_fracmux),
GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0,
PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,
PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
/*
* Clock-Architecture Diagram 9
*/
/* PD_PMU */
GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
};
static const char *const px30_cru_critical_clocks[] __initconst = {
"aclk_bus_pre",
"pclk_bus_pre",
"hclk_bus_pre",
"aclk_peri_pre",
"hclk_peri_pre",
"aclk_gpu_niu",
"pclk_top_pre",
"pclk_pmu_pre",
"hclk_usb_niu",
"pclk_vo_niu",
"aclk_vo_niu",
"hclk_vo_niu",
"aclk_vi_niu",
"hclk_vi_niu",
"pll_npll",
"usb480m",
"clk_uart2",
"pclk_uart2",
"pclk_usb_grf",
};
static void __init px30_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, px30_pll_clks,
ARRAY_SIZE(px30_pll_clks),
PX30_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, px30_clk_branches,
ARRAY_SIZE(px30_clk_branches));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&px30_cpuclk_data, px30_cpuclk_rates,
ARRAY_SIZE(px30_cpuclk_rates));
rockchip_clk_protect_critical(px30_cru_critical_clocks,
ARRAY_SIZE(px30_cru_critical_clocks));
rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
static void __init px30_pmu_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru pmu region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip pmu clk init failed\n", __func__);
return;
}
rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
ARRAY_SIZE(px30_clk_pmu_branches));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
| linux-master | drivers/clk/rockchip/clk-px30.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*/
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include "clk.h"
struct rockchip_softrst {
struct reset_controller_dev rcdev;
const int *lut;
void __iomem *reg_base;
int num_regs;
int num_per_reg;
u8 flags;
spinlock_t lock;
};
static int rockchip_softrst_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rockchip_softrst *softrst = container_of(rcdev,
struct rockchip_softrst,
rcdev);
int bank, offset;
if (softrst->lut)
id = softrst->lut[id];
bank = id / softrst->num_per_reg;
offset = id % softrst->num_per_reg;
if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
writel(BIT(offset) | (BIT(offset) << 16),
softrst->reg_base + (bank * 4));
} else {
unsigned long flags;
u32 reg;
spin_lock_irqsave(&softrst->lock, flags);
reg = readl(softrst->reg_base + (bank * 4));
writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
spin_unlock_irqrestore(&softrst->lock, flags);
}
return 0;
}
static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rockchip_softrst *softrst = container_of(rcdev,
struct rockchip_softrst,
rcdev);
int bank, offset;
if (softrst->lut)
id = softrst->lut[id];
bank = id / softrst->num_per_reg;
offset = id % softrst->num_per_reg;
if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
} else {
unsigned long flags;
u32 reg;
spin_lock_irqsave(&softrst->lock, flags);
reg = readl(softrst->reg_base + (bank * 4));
writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
spin_unlock_irqrestore(&softrst->lock, flags);
}
return 0;
}
static const struct reset_control_ops rockchip_softrst_ops = {
.assert = rockchip_softrst_assert,
.deassert = rockchip_softrst_deassert,
};
void rockchip_register_softrst_lut(struct device_node *np,
const int *lookup_table,
unsigned int num_regs,
void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
softrst = kzalloc(sizeof(*softrst), GFP_KERNEL);
if (!softrst)
return;
spin_lock_init(&softrst->lock);
softrst->reg_base = base;
softrst->lut = lookup_table;
softrst->flags = flags;
softrst->num_regs = num_regs;
softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
: 32;
softrst->rcdev.owner = THIS_MODULE;
if (lookup_table)
softrst->rcdev.nr_resets = num_regs;
else
softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
softrst->rcdev.ops = &rockchip_softrst_ops;
softrst->rcdev.of_node = np;
ret = reset_controller_register(&softrst->rcdev);
if (ret) {
pr_err("%s: could not register reset controller, %d\n",
__func__, ret);
kfree(softrst);
}
};
EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut);
| linux-master | drivers/clk/rockchip/softrst.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include "clk.h"
/*
* Recent Rockchip SoCs have a new hardware block called Native Interface
* Unit (NIU), which gates clocks to devices behind them. These effectively
* need two parent clocks.
*
* Downstream enables the linked clock via runtime PM whenever the gate is
* enabled. This implementation uses separate clock nodes for each of the
* linked gate clocks, which leaks parts of the clock tree into DT.
*
* The GATE_LINK macro instead takes the second parent via 'linkname', but
* ignores the information. Once the clock framework is ready to handle it, the
* information should be passed on here. But since these clocks are required to
* access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
* clocks critical until a better solution is available. This will waste some
* power, but avoids leaking implementation details into DT or hanging the
* system.
*/
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
GATE(_id, cname, pname, f, o, b, gf)
#define RK3588_LINKED_CLK CLK_IS_CRITICAL
#define RK3588_GRF_SOC_STATUS0 0x600
#define RK3588_PHYREF_ALT_GATE 0xc38
enum rk3588_plls {
b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll,
};
static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
/* _mhz, _p, _m, _s, _k */
RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),
RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),
RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),
RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),
RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),
RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),
RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),
RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),
RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),
RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),
RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),
RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),
RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),
RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),
RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),
RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),
RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),
RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),
RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),
RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),
RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),
RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),
RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),
RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),
RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),
RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),
RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),
RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),
RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),
RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),
RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),
RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),
RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),
RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),
RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),
RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),
RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),
RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),
RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),
RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
{ /* sentinel */ },
};
#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3
#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13
#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3
#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5
#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f
#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1
#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3
#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12
#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5
#define RK3588_CLK_DSU_SEL_DF_MASK 0x1
#define RK3588_CLK_DSU_SEL_DF_SHIFT 15
#define RK3588_CLK_DSU_DF_SRC_MASK 0x3
#define RK3588_CLK_DSU_DF_SRC_SHIFT 12
#define RK3588_CLK_DSU_DF_DIV_MASK 0x1f
#define RK3588_CLK_DSU_DF_DIV_SHIFT 7
#define RK3588_ACLKM_DSU_DIV_MASK 0x1f
#define RK3588_ACLKM_DSU_DIV_SHIFT 1
#define RK3588_ACLKS_DSU_DIV_MASK 0x1f
#define RK3588_ACLKS_DSU_DIV_SHIFT 6
#define RK3588_ACLKMP_DSU_DIV_MASK 0x1f
#define RK3588_ACLKMP_DSU_DIV_SHIFT 11
#define RK3588_PERIPH_DSU_DIV_MASK 0x1f
#define RK3588_PERIPH_DSU_DIV_SHIFT 0
#define RK3588_ATCLK_DSU_DIV_MASK 0x1f
#define RK3588_ATCLK_DSU_DIV_SHIFT 0
#define RK3588_GICCLK_DSU_DIV_MASK 0x1f
#define RK3588_GICCLK_DSU_DIV_SHIFT 5
#define RK3588_CORE_B0_SEL(_apllcore) \
{ \
.reg = RK3588_BIGCORE0_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \
HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \
}
#define RK3588_CORE_B1_SEL(_apllcore) \
{ \
.reg = RK3588_BIGCORE0_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \
}
#define RK3588_CORE_B2_SEL(_apllcore) \
{ \
.reg = RK3588_BIGCORE1_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \
HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \
}
#define RK3588_CORE_B3_SEL(_apllcore) \
{ \
.reg = RK3588_BIGCORE1_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \
}
#define RK3588_CORE_L_SEL0(_offs, _apllcore) \
{ \
.reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \
.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \
HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \
}
#define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \
{ \
.reg = RK3588_DSU_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
RK3588_CLK_DSU_DF_SRC_SHIFT) | \
HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \
RK3588_CLK_DSU_DF_DIV_SHIFT), \
}
#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \
{ \
.reg = RK3588_DSU_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \
RK3588_ACLKM_DSU_DIV_SHIFT) | \
HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \
RK3588_ACLKMP_DSU_DIV_SHIFT) | \
HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \
RK3588_ACLKS_DSU_DIV_SHIFT), \
}
#define RK3588_CORE_L_SEL3(_periph) \
{ \
.reg = RK3588_DSU_CLKSEL_CON(2), \
.val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \
RK3588_PERIPH_DSU_DIV_SHIFT), \
}
#define RK3588_CORE_L_SEL4(_gicclk, _atclk) \
{ \
.reg = RK3588_DSU_CLKSEL_CON(3), \
.val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \
RK3588_GICCLK_DSU_DIV_SHIFT) | \
HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \
RK3588_ATCLK_DSU_DIV_SHIFT), \
}
#define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \
{ \
.prate = _prate##U, \
.pre_muxs = { \
RK3588_CORE_B0_SEL(0), \
RK3588_CORE_B1_SEL(0), \
}, \
.post_muxs = { \
RK3588_CORE_B0_SEL(_apllcore), \
RK3588_CORE_B1_SEL(_apllcore), \
}, \
}
#define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \
{ \
.prate = _prate##U, \
.pre_muxs = { \
RK3588_CORE_B2_SEL(0), \
RK3588_CORE_B3_SEL(0), \
}, \
.post_muxs = { \
RK3588_CORE_B2_SEL(_apllcore), \
RK3588_CORE_B3_SEL(_apllcore), \
}, \
}
#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \
{ \
.prate = _prate##U, \
.pre_muxs = { \
RK3588_CORE_L_SEL0(0, 0), \
RK3588_CORE_L_SEL0(1, 0), \
RK3588_CORE_L_SEL1(3, 2), \
RK3588_CORE_L_SEL2(2, 3, 3), \
RK3588_CORE_L_SEL3(4), \
RK3588_CORE_L_SEL4(4, 4), \
}, \
.post_muxs = { \
RK3588_CORE_L_SEL0(0, _apllcore), \
RK3588_CORE_L_SEL0(1, _apllcore), \
RK3588_CORE_L_SEL1(_seldsu, _divdsu), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = {
RK3588_CPUB01CLK_RATE(2496000000, 1),
RK3588_CPUB01CLK_RATE(2400000000, 1),
RK3588_CPUB01CLK_RATE(2304000000, 1),
RK3588_CPUB01CLK_RATE(2208000000, 1),
RK3588_CPUB01CLK_RATE(2184000000, 1),
RK3588_CPUB01CLK_RATE(2088000000, 1),
RK3588_CPUB01CLK_RATE(2040000000, 1),
RK3588_CPUB01CLK_RATE(2016000000, 1),
RK3588_CPUB01CLK_RATE(1992000000, 1),
RK3588_CPUB01CLK_RATE(1896000000, 1),
RK3588_CPUB01CLK_RATE(1800000000, 1),
RK3588_CPUB01CLK_RATE(1704000000, 0),
RK3588_CPUB01CLK_RATE(1608000000, 0),
RK3588_CPUB01CLK_RATE(1584000000, 0),
RK3588_CPUB01CLK_RATE(1560000000, 0),
RK3588_CPUB01CLK_RATE(1536000000, 0),
RK3588_CPUB01CLK_RATE(1512000000, 0),
RK3588_CPUB01CLK_RATE(1488000000, 0),
RK3588_CPUB01CLK_RATE(1464000000, 0),
RK3588_CPUB01CLK_RATE(1440000000, 0),
RK3588_CPUB01CLK_RATE(1416000000, 0),
RK3588_CPUB01CLK_RATE(1392000000, 0),
RK3588_CPUB01CLK_RATE(1368000000, 0),
RK3588_CPUB01CLK_RATE(1344000000, 0),
RK3588_CPUB01CLK_RATE(1320000000, 0),
RK3588_CPUB01CLK_RATE(1296000000, 0),
RK3588_CPUB01CLK_RATE(1272000000, 0),
RK3588_CPUB01CLK_RATE(1248000000, 0),
RK3588_CPUB01CLK_RATE(1224000000, 0),
RK3588_CPUB01CLK_RATE(1200000000, 0),
RK3588_CPUB01CLK_RATE(1104000000, 0),
RK3588_CPUB01CLK_RATE(1008000000, 0),
RK3588_CPUB01CLK_RATE(912000000, 0),
RK3588_CPUB01CLK_RATE(816000000, 0),
RK3588_CPUB01CLK_RATE(696000000, 0),
RK3588_CPUB01CLK_RATE(600000000, 0),
RK3588_CPUB01CLK_RATE(408000000, 0),
RK3588_CPUB01CLK_RATE(312000000, 0),
RK3588_CPUB01CLK_RATE(216000000, 0),
RK3588_CPUB01CLK_RATE(96000000, 0),
};
static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = {
.core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0),
.div_core_shift[0] = 8,
.div_core_mask[0] = 0x1f,
.core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1),
.div_core_shift[1] = 0,
.div_core_mask[1] = 0x1f,
.num_cores = 2,
.mux_core_alt = 1,
.mux_core_main = 2,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = {
RK3588_CPUB23CLK_RATE(2496000000, 1),
RK3588_CPUB23CLK_RATE(2400000000, 1),
RK3588_CPUB23CLK_RATE(2304000000, 1),
RK3588_CPUB23CLK_RATE(2208000000, 1),
RK3588_CPUB23CLK_RATE(2184000000, 1),
RK3588_CPUB23CLK_RATE(2088000000, 1),
RK3588_CPUB23CLK_RATE(2040000000, 1),
RK3588_CPUB23CLK_RATE(2016000000, 1),
RK3588_CPUB23CLK_RATE(1992000000, 1),
RK3588_CPUB23CLK_RATE(1896000000, 1),
RK3588_CPUB23CLK_RATE(1800000000, 1),
RK3588_CPUB23CLK_RATE(1704000000, 0),
RK3588_CPUB23CLK_RATE(1608000000, 0),
RK3588_CPUB23CLK_RATE(1584000000, 0),
RK3588_CPUB23CLK_RATE(1560000000, 0),
RK3588_CPUB23CLK_RATE(1536000000, 0),
RK3588_CPUB23CLK_RATE(1512000000, 0),
RK3588_CPUB23CLK_RATE(1488000000, 0),
RK3588_CPUB23CLK_RATE(1464000000, 0),
RK3588_CPUB23CLK_RATE(1440000000, 0),
RK3588_CPUB23CLK_RATE(1416000000, 0),
RK3588_CPUB23CLK_RATE(1392000000, 0),
RK3588_CPUB23CLK_RATE(1368000000, 0),
RK3588_CPUB23CLK_RATE(1344000000, 0),
RK3588_CPUB23CLK_RATE(1320000000, 0),
RK3588_CPUB23CLK_RATE(1296000000, 0),
RK3588_CPUB23CLK_RATE(1272000000, 0),
RK3588_CPUB23CLK_RATE(1248000000, 0),
RK3588_CPUB23CLK_RATE(1224000000, 0),
RK3588_CPUB23CLK_RATE(1200000000, 0),
RK3588_CPUB23CLK_RATE(1104000000, 0),
RK3588_CPUB23CLK_RATE(1008000000, 0),
RK3588_CPUB23CLK_RATE(912000000, 0),
RK3588_CPUB23CLK_RATE(816000000, 0),
RK3588_CPUB23CLK_RATE(696000000, 0),
RK3588_CPUB23CLK_RATE(600000000, 0),
RK3588_CPUB23CLK_RATE(408000000, 0),
RK3588_CPUB23CLK_RATE(312000000, 0),
RK3588_CPUB23CLK_RATE(216000000, 0),
RK3588_CPUB23CLK_RATE(96000000, 0),
};
static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = {
.core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0),
.div_core_shift[0] = 8,
.div_core_mask[0] = 0x1f,
.core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1),
.div_core_shift[1] = 0,
.div_core_mask[1] = 0x1f,
.num_cores = 2,
.mux_core_alt = 1,
.mux_core_main = 2,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = {
RK3588_CPULCLK_RATE(2208000000, 1, 3, 1),
RK3588_CPULCLK_RATE(2184000000, 1, 3, 1),
RK3588_CPULCLK_RATE(2088000000, 1, 3, 1),
RK3588_CPULCLK_RATE(2040000000, 1, 3, 1),
RK3588_CPULCLK_RATE(2016000000, 1, 3, 1),
RK3588_CPULCLK_RATE(1992000000, 1, 3, 1),
RK3588_CPULCLK_RATE(1896000000, 1, 3, 1),
RK3588_CPULCLK_RATE(1800000000, 1, 3, 1),
RK3588_CPULCLK_RATE(1704000000, 0, 3, 1),
RK3588_CPULCLK_RATE(1608000000, 0, 3, 1),
RK3588_CPULCLK_RATE(1584000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1560000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1536000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1512000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1488000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1464000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1440000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1416000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1392000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1368000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1344000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1320000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1296000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1272000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1248000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1224000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1200000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1104000000, 0, 2, 1),
RK3588_CPULCLK_RATE(1008000000, 0, 2, 1),
RK3588_CPULCLK_RATE(912000000, 0, 2, 1),
RK3588_CPULCLK_RATE(816000000, 0, 2, 1),
RK3588_CPULCLK_RATE(696000000, 0, 2, 1),
RK3588_CPULCLK_RATE(600000000, 0, 2, 1),
RK3588_CPULCLK_RATE(408000000, 0, 2, 1),
RK3588_CPULCLK_RATE(312000000, 0, 2, 1),
RK3588_CPULCLK_RATE(216000000, 0, 2, 1),
RK3588_CPULCLK_RATE(96000000, 0, 2, 1),
};
static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = {
.core_reg[0] = RK3588_DSU_CLKSEL_CON(6),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.core_reg[1] = RK3588_DSU_CLKSEL_CON(6),
.div_core_shift[1] = 7,
.div_core_mask[1] = 0x1f,
.core_reg[2] = RK3588_DSU_CLKSEL_CON(7),
.div_core_shift[2] = 0,
.div_core_mask[2] = 0x1f,
.core_reg[3] = RK3588_DSU_CLKSEL_CON(7),
.div_core_shift[3] = 7,
.div_core_mask[3] = 0x1f,
.num_cores = 4,
.mux_core_reg = RK3588_DSU_CLKSEL_CON(5),
.mux_core_alt = 1,
.mux_core_main = 2,
.mux_core_shift = 14,
.mux_core_mask = 0x3,
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" };
PNAME(gpll_24m_p) = { "gpll", "xin24m" };
PNAME(gpll_aupll_p) = { "gpll", "aupll" };
PNAME(gpll_lpll_p) = { "gpll", "lpll" };
PNAME(gpll_cpll_p) = { "gpll", "cpll" };
PNAME(gpll_spll_p) = { "gpll", "spll" };
PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"};
PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"};
PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"};
PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" };
PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" };
PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" };
PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" };
PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" };
PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" };
PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" };
PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" };
PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" };
PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" };
PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" };
PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" };
PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" };
PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" };
PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" };
PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" };
PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" };
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" };
PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" };
PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" };
PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" };
PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" };
PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" };
PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" };
PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" };
PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" };
PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" };
PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" };
PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" };
PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" };
PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" };
PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" };
PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" };
PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" };
PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" };
PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" };
PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" };
PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" };
PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" };
PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" };
PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" };
PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" };
PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" };
PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" };
PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" };
PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" };
PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" };
PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" };
PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" };
PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" };
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata =
MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(26), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata =
MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(28), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata =
MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata =
MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata =
MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(30), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata =
MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(32), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata =
MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(120), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata =
MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(142), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata =
MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(146), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata =
MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(148), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata =
MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(131), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata =
MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(122), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata =
MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(155), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata =
MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(157), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata =
MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(34), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata =
MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(36), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata =
MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(124), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata =
MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(150), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata =
MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(152), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata =
MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(126), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata =
MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata =
MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(43), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata =
MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(45), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata =
MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(47), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata =
MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(49), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata =
MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(51), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata =
MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(53), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata =
MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(55), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata =
MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(57), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata =
MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(59), 0, 2, MFLAGS);
static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata =
MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(140), 0, 1, MFLAGS);
static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
[b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0),
RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8),
RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16),
RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
0, RK3588_PLL_CON(88),
RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
[aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,
0, RK3588_PLL_CON(96),
RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
[cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
CLK_IGNORE_UNUSED, RK3588_PLL_CON(104),
RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
[gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
CLK_IGNORE_UNUSED, RK3588_PLL_CON(112),
RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
[npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
0, RK3588_PLL_CON(120),
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
};
static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
/*
* CRU Clock-Architecture
*/
/* fixed */
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/* top */
COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0,
RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(9), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(9), 2, 2, MFLAGS,
RK3588_CLKGATE_CON(1), 11, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(9), 4, 2, MFLAGS,
RK3588_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(9), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(9), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(8), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0,
RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(5), 9, GFLAGS),
COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0,
RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(5), 10, GFLAGS),
COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0,
RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(5), 11, GFLAGS),
COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0,
RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(5), 12, GFLAGS),
COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0,
RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(5), 3, GFLAGS),
COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3588_CLKGATE_CON(5), 4, GFLAGS),
COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(5), 5, GFLAGS),
COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(5), 6, GFLAGS),
GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(3), 14, GFLAGS),
GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(4), 3, GFLAGS),
GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(1), 6, GFLAGS),
GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(1), 8, GFLAGS),
GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(5), 0, GFLAGS),
/* bigcore0 */
COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p,
CLK_IS_CRITICAL,
RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS,
RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS),
GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS),
GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS),
GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS),
/* bigcore1 */
COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p,
CLK_IS_CRITICAL,
RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS,
RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS),
GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS),
GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS),
GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0,
RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS),
/* dsu */
COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS,
RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS,
RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS),
GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0,
RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS),
GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL,
RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS),
GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL,
RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS),
GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED,
RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS),
GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED,
RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS),
GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS),
GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0,
RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS),
/* audio */
COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(24), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(24), 2, 2, MFLAGS,
RK3588_CLKGATE_CON(7), 1, GFLAGS),
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(7), 12, GFLAGS),
GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(7), 13, GFLAGS),
COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS,
RK3588_CLKGATE_CON(7), 14, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(29), 0,
RK3588_CLKGATE_CON(7), 15, GFLAGS,
&rk3588_i2s2_2ch_fracmux),
GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
RK3588_CLKGATE_CON(8), 0, GFLAGS),
MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(30), 2, 1, MFLAGS),
COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(8), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(31), 0,
RK3588_CLKGATE_CON(8), 2, GFLAGS,
&rk3588_i2s3_2ch_fracmux),
GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0,
RK3588_CLKGATE_CON(8), 3, GFLAGS),
GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0,
RK3588_CLKGATE_CON(8), 4, GFLAGS),
MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(32), 2, 1, MFLAGS),
GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
RK3588_CLKGATE_CON(7), 11, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(7), 4, GFLAGS),
COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS,
RK3588_CLKGATE_CON(7), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(25), 0,
RK3588_CLKGATE_CON(7), 6, GFLAGS,
&rk3588_i2s0_8ch_tx_fracmux),
GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
RK3588_CLKGATE_CON(7), 7, GFLAGS),
COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(7), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(27), 0,
RK3588_CLKGATE_CON(7), 9, GFLAGS,
&rk3588_i2s0_8ch_rx_fracmux),
GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
RK3588_CLKGATE_CON(7), 10, GFLAGS),
MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(28), 2, 2, MFLAGS),
GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(9), 6, GFLAGS),
COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(9), 7, GFLAGS),
GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(8), 14, GFLAGS),
COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(8), 15, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(33), 0,
RK3588_CLKGATE_CON(9), 0, GFLAGS,
&rk3588_spdif0_fracmux),
GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0,
RK3588_CLKGATE_CON(9), 1, GFLAGS),
GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0,
RK3588_CLKGATE_CON(9), 2, GFLAGS),
COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(9), 3, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(35), 0,
RK3588_CLKGATE_CON(9), 4, GFLAGS,
&rk3588_spdif1_fracmux),
GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0,
RK3588_CLKGATE_CON(9), 5, GFLAGS),
COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(68), 0, GFLAGS),
COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(163), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(68), 3, GFLAGS),
/* bus */
COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(10), 0, GFLAGS),
GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(16), 11, GFLAGS),
GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(16), 12, GFLAGS),
GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(16), 13, GFLAGS),
GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(19), 3, GFLAGS),
GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(19), 4, GFLAGS),
GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(19), 5, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(15), 3, GFLAGS),
COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(59), 12, 2, MFLAGS,
RK3588_CLKGATE_CON(15), 4, GFLAGS),
GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
RK3588_CLKGATE_CON(15), 5, GFLAGS),
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(15), 6, GFLAGS),
COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(59), 14, 2, MFLAGS,
RK3588_CLKGATE_CON(15), 7, GFLAGS),
GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
RK3588_CLKGATE_CON(15), 8, GFLAGS),
GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0,
RK3588_CLKGATE_CON(15), 9, GFLAGS),
COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(60), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(15), 10, GFLAGS),
GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
RK3588_CLKGATE_CON(15), 11, GFLAGS),
GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(15), 12, GFLAGS),
GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(15), 13, GFLAGS),
COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0,
RK3588_CLKSEL_CON(60), 2, 1, MFLAGS,
RK3588_CLKGATE_CON(15), 14, GFLAGS),
GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(15), 15, GFLAGS),
GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 0, GFLAGS),
GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 1, GFLAGS),
GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 2, GFLAGS),
GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 3, GFLAGS),
GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 4, GFLAGS),
GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 5, GFLAGS),
GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 6, GFLAGS),
GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 7, GFLAGS),
GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 8, GFLAGS),
GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 9, GFLAGS),
GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0,
RK3588_CLKGATE_CON(16), 10, GFLAGS),
GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(15), 0, GFLAGS),
GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
RK3588_CLKGATE_CON(15), 1, GFLAGS),
GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(11), 8, GFLAGS),
COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(11), 9, GFLAGS),
GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(11), 10, GFLAGS),
COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(11), 11, GFLAGS),
GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(11), 12, GFLAGS),
COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(11), 13, GFLAGS),
GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,
RK3588_CLKGATE_CON(17), 6, GFLAGS),
GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0,
RK3588_CLKGATE_CON(17), 7, GFLAGS),
COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0,
RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(17), 8, GFLAGS),
GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
RK3588_CLKGATE_CON(10), 5, GFLAGS),
GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
RK3588_CLKGATE_CON(10), 6, GFLAGS),
GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,
RK3588_CLKGATE_CON(10), 7, GFLAGS),
GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(10), 3, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(16), 14, GFLAGS),
COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0,
RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(16), 15, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(17), 0, GFLAGS),
COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0,
RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(17), 1, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0,
RK3588_CLKGATE_CON(17), 2, GFLAGS),
COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0,
RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(17), 3, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0,
RK3588_CLKGATE_CON(17), 4, GFLAGS),
COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0,
RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(17), 5, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 8, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 9, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 10, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 11, GFLAGS),
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 12, GFLAGS),
GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 13, GFLAGS),
GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 14, GFLAGS),
GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0,
RK3588_CLKGATE_CON(10), 15, GFLAGS),
COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 6, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 0, GFLAGS),
COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 7, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 1, GFLAGS),
COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 8, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 2, GFLAGS),
COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 9, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 3, GFLAGS),
COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 10, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 4, GFLAGS),
COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 11, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 5, GFLAGS),
COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 12, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 6, GFLAGS),
COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0,
RK3588_CLKSEL_CON(38), 13, 1, MFLAGS,
RK3588_CLKGATE_CON(11), 7, GFLAGS),
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0,
RK3588_CLKGATE_CON(18), 9, GFLAGS),
GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
RK3588_CLKGATE_CON(18), 10, GFLAGS),
GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
RK3588_CLKGATE_CON(18), 11, GFLAGS),
GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
RK3588_CLKGATE_CON(18), 13, GFLAGS),
GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
RK3588_CLKGATE_CON(18), 12, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0,
RK3588_CLKGATE_CON(11), 14, GFLAGS),
COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,
RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS,
RK3588_CLKGATE_CON(11), 15, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(14), 6, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(14), 7, GFLAGS),
GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(14), 8, GFLAGS),
GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0,
RK3588_CLKGATE_CON(14), 9, GFLAGS),
GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0,
RK3588_CLKGATE_CON(14), 10, GFLAGS),
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0,
RK3588_CLKSEL_CON(59), 2, 2, MFLAGS,
RK3588_CLKGATE_CON(14), 11, GFLAGS),
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0,
RK3588_CLKSEL_CON(59), 4, 2, MFLAGS,
RK3588_CLKGATE_CON(14), 12, GFLAGS),
COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0,
RK3588_CLKSEL_CON(59), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(14), 13, GFLAGS),
COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0,
RK3588_CLKSEL_CON(59), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(14), 14, GFLAGS),
COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0,
RK3588_CLKSEL_CON(59), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(14), 15, GFLAGS),
GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(18), 6, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 0, GFLAGS),
COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0,
RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(12), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 2, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 3, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 4, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 5, GFLAGS),
GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 6, GFLAGS),
GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 7, GFLAGS),
GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 8, GFLAGS),
GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 9, GFLAGS),
GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0,
RK3588_CLKGATE_CON(12), 10, GFLAGS),
COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(42), 0,
RK3588_CLKGATE_CON(12), 12, GFLAGS,
&rk3588_uart1_fracmux),
GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
RK3588_CLKGATE_CON(12), 13, GFLAGS),
COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(12), 14, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(44), 0,
RK3588_CLKGATE_CON(12), 15, GFLAGS,
&rk3588_uart2_fracmux),
GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
RK3588_CLKGATE_CON(13), 0, GFLAGS),
COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(13), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(46), 0,
RK3588_CLKGATE_CON(13), 2, GFLAGS,
&rk3588_uart3_fracmux),
GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
RK3588_CLKGATE_CON(13), 3, GFLAGS),
COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(13), 4, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(48), 0,
RK3588_CLKGATE_CON(13), 5, GFLAGS,
&rk3588_uart4_fracmux),
GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
RK3588_CLKGATE_CON(13), 6, GFLAGS),
COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(13), 7, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(50), 0,
RK3588_CLKGATE_CON(13), 8, GFLAGS,
&rk3588_uart5_fracmux),
GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
RK3588_CLKGATE_CON(13), 9, GFLAGS),
COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(13), 10, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(52), 0,
RK3588_CLKGATE_CON(13), 11, GFLAGS,
&rk3588_uart6_fracmux),
GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
RK3588_CLKGATE_CON(13), 12, GFLAGS),
COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(13), 13, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(54), 0,
RK3588_CLKGATE_CON(13), 14, GFLAGS,
&rk3588_uart7_fracmux),
GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
RK3588_CLKGATE_CON(13), 15, GFLAGS),
COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(14), 0, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(56), 0,
RK3588_CLKGATE_CON(14), 1, GFLAGS,
&rk3588_uart8_fracmux),
GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
RK3588_CLKGATE_CON(14), 2, GFLAGS),
COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(14), 3, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(58), 0,
RK3588_CLKGATE_CON(14), 4, GFLAGS,
&rk3588_uart9_fracmux),
GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
RK3588_CLKGATE_CON(14), 5, GFLAGS),
/* center */
COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p,
CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(165), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(69), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p,
CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(165), 2, 2, MFLAGS,
RK3588_CLKGATE_CON(69), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p,
CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(165), 4, 2, MFLAGS,
RK3588_CLKGATE_CON(69), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p,
CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
RK3588_CLKGATE_CON(69), 3, GFLAGS),
GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(69), 5, GFLAGS),
GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(69), 6, GFLAGS),
COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p,
CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(165), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(69), 8, GFLAGS),
COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p,
CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(165), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(69), 9, GFLAGS),
GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(69), 14, GFLAGS),
COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED,
RK3588_CLKSEL_CON(165), 12, 1, MFLAGS,
RK3588_CLKGATE_CON(69), 15, GFLAGS),
GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,
RK3588_CLKGATE_CON(70), 0, GFLAGS),
GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,
RK3588_CLKGATE_CON(70), 1, GFLAGS),
GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
RK3588_CLKGATE_CON(70), 2, GFLAGS),
COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(70), 4, GFLAGS),
GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0,
RK3588_CLKGATE_CON(70), 7, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0,
RK3588_CLKGATE_CON(70), 8, GFLAGS),
GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(70), 9, GFLAGS),
GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(70), 10, GFLAGS),
/* gpu */
COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(66), 1, GFLAGS),
GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
RK3588_CLKGATE_CON(66), 4, GFLAGS),
GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0,
RK3588_CLKGATE_CON(66), 6, GFLAGS),
COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0,
RK3588_CLKSEL_CON(159), 0, 5, DFLAGS,
RK3588_CLKGATE_CON(66), 7, GFLAGS),
GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
RK3588_CLKGATE_CON(67), 0, GFLAGS),
GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0,
RK3588_CLKGATE_CON(67), 1, GFLAGS),
/* isp1 */
COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(26), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(67), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(26), 1, GFLAGS),
COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(26), 2, GFLAGS),
GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0,
RK3588_CLKGATE_CON(26), 3, GFLAGS),
GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0,
RK3588_CLKGATE_CON(26), 4, GFLAGS),
/* npu */
COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(73), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(29), 0, GFLAGS),
COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(29), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(74), 1, 2, MFLAGS,
RK3588_CLKGATE_CON(29), 4, GFLAGS),
GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0,
RK3588_CLKGATE_CON(27), 0, GFLAGS),
GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0,
RK3588_CLKGATE_CON(27), 2, GFLAGS),
GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0,
RK3588_CLKGATE_CON(28), 0, GFLAGS),
GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0,
RK3588_CLKGATE_CON(28), 2, GFLAGS),
COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(74), 5, 2, MFLAGS,
RK3588_CLKGATE_CON(30), 1, GFLAGS),
GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,
RK3588_CLKGATE_CON(30), 3, GFLAGS),
COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0,
RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(30), 5, GFLAGS),
GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0,
RK3588_CLKGATE_CON(29), 12, GFLAGS),
GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(29), 13, GFLAGS),
GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
RK3588_CLKGATE_CON(29), 14, GFLAGS),
GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0,
RK3588_CLKGATE_CON(29), 15, GFLAGS),
GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0,
RK3588_CLKGATE_CON(30), 6, GFLAGS),
GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0,
RK3588_CLKGATE_CON(30), 8, GFLAGS),
GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0,
RK3588_CLKGATE_CON(29), 6, GFLAGS),
COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0,
RK3588_CLKSEL_CON(74), 3, 1, MFLAGS,
RK3588_CLKGATE_CON(29), 7, GFLAGS),
GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
RK3588_CLKGATE_CON(29), 8, GFLAGS),
GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
RK3588_CLKGATE_CON(29), 9, GFLAGS),
GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0,
RK3588_CLKGATE_CON(29), 10, GFLAGS),
GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
RK3588_CLKGATE_CON(29), 11, GFLAGS),
/* nvm */
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(31), 0, GFLAGS),
COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 1, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
RK3588_CLKGATE_CON(31), 5, GFLAGS),
COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0,
RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3588_CLKGATE_CON(31), 6, GFLAGS),
COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 7, GFLAGS),
GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
RK3588_CLKGATE_CON(31), 8, GFLAGS),
COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS,
RK3588_CLKGATE_CON(31), 9, GFLAGS),
/* php */
COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0,
RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
RK3588_CLKGATE_CON(34), 10, GFLAGS),
COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0,
RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
RK3588_CLKGATE_CON(34), 11, GFLAGS),
COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3588_CLKGATE_CON(35), 5, GFLAGS),
COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(35), 6, GFLAGS),
COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(32), 6, GFLAGS),
COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS,
RK3588_CLKGATE_CON(32), 7, GFLAGS),
COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0,
RK3588_CLKSEL_CON(80), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(32), 0, GFLAGS),
GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL,
RK3588_CLKGATE_CON(34), 6, GFLAGS),
GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0,
RK3588_CLKGATE_CON(32), 8, GFLAGS),
GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0,
RK3588_CLKGATE_CON(34), 7, GFLAGS),
GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0,
RK3588_CLKGATE_CON(34), 8, GFLAGS),
GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0,
RK3588_CLKGATE_CON(32), 13, GFLAGS),
GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0,
RK3588_CLKGATE_CON(32), 14, GFLAGS),
GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0,
RK3588_CLKGATE_CON(32), 15, GFLAGS),
GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 0, GFLAGS),
GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 1, GFLAGS),
GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0,
RK3588_CLKGATE_CON(33), 2, GFLAGS),
GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0,
RK3588_CLKGATE_CON(33), 3, GFLAGS),
GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0,
RK3588_CLKGATE_CON(33), 4, GFLAGS),
GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0,
RK3588_CLKGATE_CON(33), 5, GFLAGS),
GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0,
RK3588_CLKGATE_CON(33), 6, GFLAGS),
GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 7, GFLAGS),
GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 8, GFLAGS),
GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 9, GFLAGS),
GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 10, GFLAGS),
GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0,
RK3588_CLKGATE_CON(33), 11, GFLAGS),
GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0,
RK3588_CLKGATE_CON(33), 12, GFLAGS),
GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0,
RK3588_CLKGATE_CON(33), 13, GFLAGS),
GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0,
RK3588_CLKGATE_CON(33), 14, GFLAGS),
GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0,
RK3588_CLKGATE_CON(33), 15, GFLAGS),
GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0,
RK3588_CLKGATE_CON(34), 0, GFLAGS),
GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
RK3588_CLKGATE_CON(34), 1, GFLAGS),
GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
RK3588_CLKGATE_CON(34), 2, GFLAGS),
GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
RK3588_CLKGATE_CON(34), 3, GFLAGS),
GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
RK3588_CLKGATE_CON(34), 4, GFLAGS),
GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
RK3588_CLKGATE_CON(34), 5, GFLAGS),
GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
RK3588_CLKGATE_CON(37), 0, GFLAGS),
GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
RK3588_CLKGATE_CON(37), 1, GFLAGS),
GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
RK3588_CLKGATE_CON(37), 2, GFLAGS),
GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0,
RK3588_CLKGATE_CON(32), 3, GFLAGS),
GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0,
RK3588_CLKGATE_CON(32), 4, GFLAGS),
GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0,
RK3588_CLKGATE_CON(32), 10, GFLAGS),
GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0,
RK3588_CLKGATE_CON(32), 11, GFLAGS),
GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
RK3588_CLKGATE_CON(37), 4, GFLAGS),
GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
RK3588_CLKGATE_CON(37), 5, GFLAGS),
GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
RK3588_CLKGATE_CON(37), 6, GFLAGS),
GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0,
RK3588_CLKGATE_CON(37), 7, GFLAGS),
GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0,
RK3588_CLKGATE_CON(37), 8, GFLAGS),
GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0,
RK3588_CLKGATE_CON(37), 9, GFLAGS),
COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(37), 10, GFLAGS),
COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3588_CLKGATE_CON(37), 11, GFLAGS),
COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(37), 12, GFLAGS),
GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0,
RK3588_CLKGATE_CON(35), 7, GFLAGS),
GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
RK3588_CLKGATE_CON(35), 8, GFLAGS),
GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
RK3588_CLKGATE_CON(35), 9, GFLAGS),
COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0,
RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS,
RK3588_CLKGATE_CON(35), 10, GFLAGS),
GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0,
RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS),
GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0,
RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS),
GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0,
RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS),
GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0,
RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS),
/* rga */
COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(76), 6, GFLAGS),
COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(76), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(174), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(76), 1, GFLAGS),
GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0,
RK3588_CLKGATE_CON(76), 4, GFLAGS),
GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0,
RK3588_CLKGATE_CON(76), 5, GFLAGS),
/* vdec */
COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(89), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(40), 0, GFLAGS),
COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(40), 1, GFLAGS),
COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(40), 2, GFLAGS),
COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(40), 7, GFLAGS),
COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0,
RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(40), 8, GFLAGS),
COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(40), 9, GFLAGS),
COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(93), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(41), 0, GFLAGS),
COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(41), 1, GFLAGS),
COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(41), 6, GFLAGS),
COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0,
RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(41), 7, GFLAGS),
COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(41), 8, GFLAGS),
/* sdio */
COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(172), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(75), 0, GFLAGS),
COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0,
RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS,
RK3588_CLKGATE_CON(75), 3, GFLAGS),
MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1),
/* usb */
COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(42), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(96), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(42), 1, GFLAGS),
GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
RK3588_CLKGATE_CON(42), 5, GFLAGS),
GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
RK3588_CLKGATE_CON(42), 6, GFLAGS),
GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
RK3588_CLKGATE_CON(42), 8, GFLAGS),
GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
RK3588_CLKGATE_CON(42), 9, GFLAGS),
/* vdpu */
COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 2, GFLAGS),
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 3, GFLAGS),
GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 4, GFLAGS),
COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(45), 6, GFLAGS),
GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 11, GFLAGS),
GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 13, GFLAGS),
GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 15, GFLAGS),
GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 1, GFLAGS),
GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 3, GFLAGS),
GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 7, GFLAGS),
GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 8, GFLAGS),
COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(45), 9, GFLAGS),
GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 10, GFLAGS),
GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 11, GFLAGS),
COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS,
RK3588_CLKGATE_CON(45), 12, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 9, GFLAGS),
/* venc */
COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(104), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(48), 0, GFLAGS),
COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(48), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(102), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(47), 0, GFLAGS),
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 1, GFLAGS),
GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 4, GFLAGS),
GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 5, GFLAGS),
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 6, GFLAGS),
COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(48), 6, GFLAGS),
/* vi */
COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(106), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 2, GFLAGS),
COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(108), 14, 2, MFLAGS,
RK3588_CLKGATE_CON(51), 10, GFLAGS),
GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,
RK3588_CLKGATE_CON(51), 11, GFLAGS),
GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0,
RK3588_CLKGATE_CON(51), 12, GFLAGS),
GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 4, GFLAGS),
GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 5, GFLAGS),
GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 6, GFLAGS),
GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 7, GFLAGS),
GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 8, GFLAGS),
GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 9, GFLAGS),
GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0,
RK3588_CLKGATE_CON(49), 14, GFLAGS),
GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0,
RK3588_CLKGATE_CON(49), 15, GFLAGS),
COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(50), 0, GFLAGS),
GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 1, GFLAGS),
GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0,
RK3588_CLKGATE_CON(50), 2, GFLAGS),
COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(50), 3, GFLAGS),
COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 9, GFLAGS),
GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0,
RK3588_CLKGATE_CON(49), 10, GFLAGS),
GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0,
RK3588_CLKGATE_CON(49), 11, GFLAGS),
GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0,
RK3588_CLKGATE_CON(49), 12, GFLAGS),
GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0,
RK3588_CLKGATE_CON(49), 13, GFLAGS),
COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 6, GFLAGS),
GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
RK3588_CLKGATE_CON(49), 7, GFLAGS),
GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
RK3588_CLKGATE_CON(49), 8, GFLAGS),
/* vo0 */
COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(55), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(116), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(55), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(116), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(55), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(116), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(55), 3, GFLAGS),
COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(116), 12, 2, MFLAGS,
RK3588_CLKGATE_CON(55), 4, GFLAGS),
GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 4, GFLAGS),
GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 5, GFLAGS),
GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0,
RK3588_CLKGATE_CON(56), 6, GFLAGS),
GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0,
RK3588_CLKGATE_CON(56), 7, GFLAGS),
GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 8, GFLAGS),
GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 9, GFLAGS),
GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0,
RK3588_CLKGATE_CON(55), 11, GFLAGS),
GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
RK3588_CLKGATE_CON(55), 14, GFLAGS),
GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 0, GFLAGS),
GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 1, GFLAGS),
GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(55), 10, GFLAGS),
COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(56), 11, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(119), 0,
RK3588_CLKGATE_CON(56), 12, GFLAGS,
&rk3588_i2s4_8ch_tx_fracmux),
GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0,
RK3588_CLKGATE_CON(56), 13, GFLAGS),
COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(56), 15, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(121), 0,
RK3588_CLKGATE_CON(57), 0, GFLAGS,
&rk3588_i2s8_8ch_tx_fracmux),
GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0,
RK3588_CLKGATE_CON(57), 1, GFLAGS),
COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(57), 3, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(123), 0,
RK3588_CLKGATE_CON(57), 4, GFLAGS,
&rk3588_spdif2_dp0_fracmux),
GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0,
RK3588_CLKGATE_CON(57), 5, GFLAGS),
GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0,
RK3588_CLKGATE_CON(57), 6, GFLAGS),
COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(57), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(125), 0,
RK3588_CLKGATE_CON(57), 9, GFLAGS,
&rk3588_spdif5_dp1_fracmux),
GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0,
RK3588_CLKGATE_CON(57), 10, GFLAGS),
GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0,
RK3588_CLKGATE_CON(57), 11, GFLAGS),
COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0,
RK3588_CLKSEL_CON(117), 0, 8, DFLAGS,
RK3588_CLKGATE_CON(56), 2, GFLAGS),
COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0,
RK3588_CLKSEL_CON(117), 8, 8, DFLAGS,
RK3588_CLKGATE_CON(56), 3, GFLAGS),
/* vo1 */
COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(65), 9, GFLAGS),
COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0,
RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(59), 0, GFLAGS),
COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(59), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(128), 13, 2, MFLAGS,
RK3588_CLKGATE_CON(59), 2, GFLAGS),
COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(129), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(59), 3, GFLAGS),
COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0,
RK3588_CLKSEL_CON(129), 2, 2, MFLAGS,
RK3588_CLKGATE_CON(59), 4, GFLAGS),
COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(129), 4, 2, MFLAGS,
RK3588_CLKGATE_CON(59), 5, GFLAGS),
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(110), 12, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 3, GFLAGS),
COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(74), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(170), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(74), 2, GFLAGS),
MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(115), 9, 1, MFLAGS),
GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(62), 0, GFLAGS),
GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
RK3588_CLKGATE_CON(62), 1, GFLAGS),
COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(140), 1, 2, MFLAGS,
RK3588_CLKGATE_CON(62), 2, GFLAGS),
GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(62), 3, GFLAGS),
GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
RK3588_CLKGATE_CON(62), 4, GFLAGS),
COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(140), 3, 2, MFLAGS,
RK3588_CLKGATE_CON(62), 5, GFLAGS),
GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(60), 4, GFLAGS),
GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(60), 7, GFLAGS),
GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0,
RK3588_CLKGATE_CON(61), 9, GFLAGS),
GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(61), 10, GFLAGS),
GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0,
RK3588_CLKGATE_CON(61), 11, GFLAGS),
COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS,
RK3588_CLKGATE_CON(61), 12, GFLAGS),
COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(139), 0,
RK3588_CLKGATE_CON(61), 13, GFLAGS,
&rk3588_hdmirx_aud_fracmux),
GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0,
RK3588_CLKGATE_CON(61), 14, GFLAGS),
GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(60), 11, GFLAGS),
COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS,
RK3588_CLKGATE_CON(60), 15, GFLAGS),
GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0,
RK3588_CLKGATE_CON(61), 0, GFLAGS),
GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(61), 2, GFLAGS),
COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS,
RK3588_CLKGATE_CON(61), 6, GFLAGS),
GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0,
RK3588_CLKGATE_CON(61), 7, GFLAGS),
GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0,
RK3588_CLKGATE_CON(60), 9, GFLAGS),
GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(60), 10, GFLAGS),
GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(59), 12, GFLAGS),
GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(59), 14, GFLAGS),
GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(59), 15, GFLAGS),
GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(65), 8, GFLAGS),
COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(65), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(156), 0,
RK3588_CLKGATE_CON(65), 6, GFLAGS,
&rk3588_i2s10_8ch_rx_fracmux),
GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0,
RK3588_CLKGATE_CON(65), 7, GFLAGS),
COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(60), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(130), 0,
RK3588_CLKGATE_CON(60), 2, GFLAGS,
&rk3588_i2s7_8ch_rx_fracmux),
GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0,
RK3588_CLKGATE_CON(60), 3, GFLAGS),
COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(65), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(154), 0,
RK3588_CLKGATE_CON(65), 2, GFLAGS,
&rk3588_i2s9_8ch_rx_fracmux),
GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0,
RK3588_CLKGATE_CON(65), 3, GFLAGS),
COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS,
RK3588_CLKGATE_CON(62), 6, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0,
RK3588_CLKSEL_CON(141), 0,
RK3588_CLKGATE_CON(62), 7, GFLAGS,
&rk3588_i2s5_8ch_tx_fracmux),
GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0,
RK3588_CLKGATE_CON(62), 8, GFLAGS),
COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS,
RK3588_CLKGATE_CON(62), 13, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(145), 0,
RK3588_CLKGATE_CON(62), 14, GFLAGS,
&rk3588_i2s6_8ch_tx_fracmux),
GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0,
RK3588_CLKGATE_CON(62), 15, GFLAGS),
COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 0, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0,
RK3588_CLKSEL_CON(147), 0,
RK3588_CLKGATE_CON(63), 1, GFLAGS,
&rk3588_i2s6_8ch_rx_fracmux),
GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0,
RK3588_CLKGATE_CON(63), 2, GFLAGS),
MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(148), 2, 2, MFLAGS),
COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(149), 0,
RK3588_CLKGATE_CON(63), 6, GFLAGS,
&rk3588_spdif3_fracmux),
GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0,
RK3588_CLKGATE_CON(63), 7, GFLAGS),
COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 9, GFLAGS),
COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src",
CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(151), 0,
RK3588_CLKGATE_CON(63), 10, GFLAGS,
&rk3588_spdif4_fracmux),
GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0,
RK3588_CLKGATE_CON(63), 11, GFLAGS),
COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 13, GFLAGS),
COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 15, GFLAGS),
COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(64), 1, GFLAGS),
GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
RK3588_CLKGATE_CON(73), 12, GFLAGS),
GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
RK3588_CLKGATE_CON(73), 13, GFLAGS),
GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(72), 5, GFLAGS),
GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(72), 6, GFLAGS),
GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0,
RK3588_CLKGATE_CON(72), 2, GFLAGS),
GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0,
RK3588_CLKGATE_CON(72), 4, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
RK3588_CLKGATE_CON(52), 8, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0,
RK3588_CLKGATE_CON(52), 9, GFLAGS),
COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0,
RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(52), 10, GFLAGS),
COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 11, GFLAGS),
COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 12, GFLAGS),
COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 13, GFLAGS),
COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(53), 0, GFLAGS),
COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p,
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 11, 2, MFLAGS,
RK3588_CLKGATE_CON(53), 1, GFLAGS),
COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0,
RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(53), 2, GFLAGS),
GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0,
RK3588_CLKGATE_CON(53), 4, GFLAGS),
GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0,
RK3588_CLKGATE_CON(53), 5, GFLAGS),
COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0,
RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(53), 6, GFLAGS),
COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0,
RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS,
RK3588_CLKGATE_CON(53), 7, GFLAGS),
GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(53), 8, GFLAGS),
GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0,
RK3588_CLKGATE_CON(53), 10, GFLAGS),
GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(2), 8, GFLAGS),
GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
RK3588_CLKGATE_CON(2), 15, GFLAGS),
GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
RK3588_CLKGATE_CON(77), 0, GFLAGS),
GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
RK3588_CLKGATE_CON(77), 1, GFLAGS),
GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
RK3588_CLKGATE_CON(77), 2, GFLAGS),
COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
RK3588_CLKSEL_CON(176), 0, 6, DFLAGS,
RK3588_CLKGATE_CON(77), 3, GFLAGS),
COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
RK3588_CLKSEL_CON(176), 6, 6, DFLAGS,
RK3588_CLKGATE_CON(77), 4, GFLAGS),
COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
RK3588_CLKSEL_CON(177), 0, 6, DFLAGS,
RK3588_CLKGATE_CON(77), 5, GFLAGS),
MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(177), 6, 1, MFLAGS),
MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(177), 7, 1, MFLAGS),
MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(177), 8, 1, MFLAGS),
/* pmu */
COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0,
RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0,
RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0,
RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS,
RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0,
RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS,
RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0,
RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS,
RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL,
RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS,
RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL,
RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS,
RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS),
GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL,
RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS,
RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS),
GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS),
GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS),
GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS,
RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0,
RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0,
RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS,
RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS),
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0,
RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS),
COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0,
RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src",
CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(6), 0,
RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS,
&rk3588_i2s1_8ch_tx_fracmux),
GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0,
RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src",
CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(8), 0,
RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS,
&rk3588_i2s1_8ch_rx_fracmux),
GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS),
MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS),
GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS),
GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS),
GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS),
GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS),
COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0,
RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS,
RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS),
GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS),
GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL,
RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS),
GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED,
RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS),
GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0,
RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0,
RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS,
RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS),
GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,
RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS),
GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0,
RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0,
RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS,
RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS),
GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0,
RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS),
GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0,
RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS),
COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0,
RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
RK3588_PMU_CLKSEL_CON(4), 0,
RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS,
&rk3588_uart0_fracmux),
GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0,
RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS),
GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0,
RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0,
RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS),
COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0,
RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS),
COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p,
CLK_IS_CRITICAL,
RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS,
RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS),
COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p,
CLK_IS_CRITICAL,
RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 0, GFLAGS),
GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 1, GFLAGS),
GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 2, GFLAGS),
GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 3, GFLAGS),
GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 12, GFLAGS),
GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 14, GFLAGS),
GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0,
RK3588_CLKGATE_CON(64), 0, GFLAGS),
GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 8, GFLAGS),
GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 4, GFLAGS),
GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 3, GFLAGS),
GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(62), 12, GFLAGS),
GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(65), 0, GFLAGS),
GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(60), 0, GFLAGS),
GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(65), 4, GFLAGS),
GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0,
RK3588_CLKGATE_CON(60), 5, GFLAGS),
GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
RK3588_CLKGATE_CON(60), 6, GFLAGS),
GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0,
RK3588_CLKGATE_CON(57), 7, GFLAGS),
GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0,
RK3588_CLKGATE_CON(57), 2, GFLAGS),
GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0,
RK3588_CLKGATE_CON(56), 14, GFLAGS),
GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0,
RK3588_CLKGATE_CON(56), 10, GFLAGS),
GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0,
RK3588_CLKGATE_CON(55), 12, GFLAGS),
GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
RK3588_CLKGATE_CON(55), 13, GFLAGS),
GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0,
RK3588_CLKGATE_CON(48), 4, GFLAGS),
GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0,
RK3588_CLKGATE_CON(48), 5, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 8, GFLAGS),
GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(45), 5, GFLAGS),
GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 10, GFLAGS),
GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 12, GFLAGS),
GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 14, GFLAGS),
GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(45), 0, GFLAGS),
GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0,
RK3588_CLKGATE_CON(45), 2, GFLAGS),
GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0,
RK3588_CLKGATE_CON(42), 7, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 10, GFLAGS),
GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 11, GFLAGS),
GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 12, GFLAGS),
GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 13, GFLAGS),
GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0,
RK3588_CLKGATE_CON(42), 4, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0,
RK3588_CLKGATE_CON(75), 2, GFLAGS),
GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0,
RK3588_CLKGATE_CON(41), 2, GFLAGS),
GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0,
RK3588_CLKGATE_CON(41), 3, GFLAGS),
GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0,
RK3588_CLKGATE_CON(40), 3, GFLAGS),
GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0,
RK3588_CLKGATE_CON(40), 4, GFLAGS),
GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0,
RK3588_CLKGATE_CON(39), 0, GFLAGS),
GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0,
RK3588_CLKGATE_CON(39), 1, GFLAGS),
GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0,
RK3588_CLKGATE_CON(38), 3, GFLAGS),
GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0,
RK3588_CLKGATE_CON(38), 4, GFLAGS),
GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0,
RK3588_CLKGATE_CON(38), 5, GFLAGS),
GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0,
RK3588_CLKGATE_CON(38), 6, GFLAGS),
GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0,
RK3588_CLKGATE_CON(38), 7, GFLAGS),
GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0,
RK3588_CLKGATE_CON(38), 8, GFLAGS),
GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0,
RK3588_CLKGATE_CON(38), 9, GFLAGS),
GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0,
RK3588_CLKGATE_CON(38), 13, GFLAGS),
GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0,
RK3588_CLKGATE_CON(38), 14, GFLAGS),
GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0,
RK3588_CLKGATE_CON(38), 15, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
RK3588_CLKGATE_CON(31), 10, GFLAGS),
GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0,
RK3588_CLKGATE_CON(31), 11, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0,
RK3588_CLKGATE_CON(31), 4, GFLAGS),
GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0,
RK3588_CLKGATE_CON(26), 5, GFLAGS),
GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0,
RK3588_CLKGATE_CON(26), 7, GFLAGS),
GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0,
RK3588_CLKGATE_CON(68), 5, GFLAGS),
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
RK3588_CLKGATE_CON(68), 2, GFLAGS),
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
};
static void __init rk3588_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3588_pll_clks,
ARRAY_SIZE(rk3588_pll_clks),
RK3588_GRF_SOC_STATUS0);
rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",
mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
&rk3588_cpulclk_data, rk3588_cpulclk_rates,
ARRAY_SIZE(rk3588_cpulclk_rates));
rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01",
mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p),
&rk3588_cpub0clk_data, rk3588_cpub0clk_rates,
ARRAY_SIZE(rk3588_cpub0clk_rates));
rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23",
mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p),
&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
ARRAY_SIZE(rk3588_cpub1clk_rates));
rockchip_clk_register_branches(ctx, rk3588_clk_branches,
ARRAY_SIZE(rk3588_clk_branches));
rk3588_rst_init(np, reg_base);
rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
struct clk_rk3588_inits {
void (*inits)(struct device_node *np);
};
static const struct clk_rk3588_inits clk_3588_cru_init = {
.inits = rk3588_clk_init,
};
static const struct of_device_id clk_rk3588_match_table[] = {
{
.compatible = "rockchip,rk3588-cru",
.data = &clk_3588_cru_init,
},
{ }
};
static int __init clk_rk3588_probe(struct platform_device *pdev)
{
const struct clk_rk3588_inits *init_data;
struct device *dev = &pdev->dev;
init_data = device_get_match_data(dev);
if (!init_data)
return -EINVAL;
if (init_data->inits)
init_data->inits(dev->of_node);
return 0;
}
static struct platform_driver clk_rk3588_driver = {
.driver = {
.name = "clk-rk3588",
.of_match_table = clk_rk3588_match_table,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
| linux-master | drivers/clk/rockchip/clk-rk3588.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <[email protected]>
*
* based on
*
* samsung/clk.c
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <[email protected]>
*/
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/reboot.h>
#include "../clk-fractional-divider.h"
#include "clk.h"
/*
* Register a clock branch.
* Most clock branches have a form like
*
* src1 --|--\
* |M |--[GATE]-[DIV]-
* src2 --|--/
*
* sometimes without one of those components.
*/
static struct clk *rockchip_clk_register_branch(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
u32 *mux_table,
int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
*gate_ops = NULL;
int ret;
if (num_parents > 1) {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->reg = base + muxdiv_offset;
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
mux->table = mux_table;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
}
if (gate_offset >= 0) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate) {
ret = -ENOMEM;
goto err_gate;
}
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
gate_ops = &clk_gate_ops;
}
if (div_width > 0) {
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div) {
ret = -ENOMEM;
goto err_div;
}
div->flags = div_flags;
if (div_offset)
div->reg = base + div_offset;
else
div->reg = base + muxdiv_offset;
div->shift = div_shift;
div->width = div_width;
div->lock = lock;
div->table = div_table;
div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
? &clk_divider_ro_ops
: &clk_divider_ops;
}
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
mux ? &mux->hw : NULL, mux_ops,
div ? &div->hw : NULL, div_ops,
gate ? &gate->hw : NULL, gate_ops,
flags);
if (IS_ERR(hw)) {
kfree(div);
kfree(gate);
return ERR_CAST(hw);
}
return hw->clk;
err_div:
kfree(gate);
err_gate:
kfree(mux);
return ERR_PTR(ret);
}
struct rockchip_clk_frac {
struct notifier_block clk_nb;
struct clk_fractional_divider div;
struct clk_gate gate;
struct clk_mux mux;
const struct clk_ops *mux_ops;
int mux_frac_idx;
bool rate_change_remuxed;
int rate_change_idx;
};
#define to_rockchip_clk_frac_nb(nb) \
container_of(nb, struct rockchip_clk_frac, clk_nb)
static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
struct clk_mux *frac_mux = &frac->mux;
int ret = 0;
pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
__func__, event, ndata->old_rate, ndata->new_rate);
if (event == PRE_RATE_CHANGE) {
frac->rate_change_idx =
frac->mux_ops->get_parent(&frac_mux->hw);
if (frac->rate_change_idx != frac->mux_frac_idx) {
frac->mux_ops->set_parent(&frac_mux->hw,
frac->mux_frac_idx);
frac->rate_change_remuxed = 1;
}
} else if (event == POST_RATE_CHANGE) {
/*
* The POST_RATE_CHANGE notifier runs directly after the
* divider clock is set in clk_change_rate, so we'll have
* remuxed back to the original parent before clk_change_rate
* reaches the mux itself.
*/
if (frac->rate_change_remuxed) {
frac->mux_ops->set_parent(&frac_mux->hw,
frac->rate_change_idx);
frac->rate_change_remuxed = 0;
}
}
return notifier_from_errno(ret);
}
/*
* fractional divider must set that denominator is 20 times larger than
* numerator to generate precise clock frequency.
*/
static void rockchip_fractional_approximation(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate,
unsigned long *m, unsigned long *n)
{
struct clk_fractional_divider *fd = to_clk_fd(hw);
unsigned long p_rate, p_parent_rate;
struct clk_hw *p_parent;
p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
p_parent_rate = clk_hw_get_rate(p_parent);
*parent_rate = p_parent_rate;
}
fd->flags |= CLK_FRAC_DIVIDER_POWER_OF_TWO_PS;
clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
}
static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
struct clk *clk, unsigned int id)
{
ctx->clk_data.clks[id] = clk;
}
static struct clk *rockchip_clk_register_frac_branch(
struct rockchip_clk_provider *ctx, const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base, int muxdiv_offset, u8 div_flags,
int gate_offset, u8 gate_shift, u8 gate_flags,
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
struct clk_hw *hw;
struct rockchip_clk_frac *frac;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
if (muxdiv_offset < 0)
return ERR_PTR(-EINVAL);
if (child && child->branch_type != branch_mux) {
pr_err("%s: fractional child clock for %s can only be a mux\n",
__func__, name);
return ERR_PTR(-EINVAL);
}
frac = kzalloc(sizeof(*frac), GFP_KERNEL);
if (!frac)
return ERR_PTR(-ENOMEM);
if (gate_offset >= 0) {
gate = &frac->gate;
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
gate_ops = &clk_gate_ops;
}
div = &frac->div;
div->flags = div_flags;
div->reg = base + muxdiv_offset;
div->mshift = 16;
div->mwidth = 16;
div->nshift = 0;
div->nwidth = 16;
div->lock = lock;
div->approximation = rockchip_fractional_approximation;
div_ops = &clk_fractional_divider_ops;
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
NULL, NULL,
&div->hw, div_ops,
gate ? &gate->hw : NULL, gate_ops,
flags | CLK_SET_RATE_UNGATE);
if (IS_ERR(hw)) {
kfree(frac);
return ERR_CAST(hw);
}
if (child) {
struct clk_mux *frac_mux = &frac->mux;
struct clk_init_data init;
struct clk *mux_clk;
int ret;
frac->mux_frac_idx = match_string(child->parent_names,
child->num_parents, name);
frac->mux_ops = &clk_mux_ops;
frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
frac_mux->reg = base + child->muxdiv_offset;
frac_mux->shift = child->mux_shift;
frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
if (child->mux_table)
frac_mux->table = child->mux_table;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
init.name = child->name;
init.flags = child->flags | CLK_SET_RATE_PARENT;
init.ops = frac->mux_ops;
init.parent_names = child->parent_names;
init.num_parents = child->num_parents;
mux_clk = clk_register(NULL, &frac_mux->hw);
if (IS_ERR(mux_clk)) {
kfree(frac);
return mux_clk;
}
rockchip_clk_add_lookup(ctx, mux_clk, child->id);
/* notifier on the fraction divider to catch rate changes */
if (frac->mux_frac_idx >= 0) {
pr_debug("%s: found fractional parent in mux at pos %d\n",
__func__, frac->mux_frac_idx);
ret = clk_notifier_register(hw->clk, &frac->clk_nb);
if (ret)
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
} else {
pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
__func__, name, child->name);
}
}
return hw->clk;
}
static struct clk *rockchip_clk_register_factor_branch(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base, unsigned int mult, unsigned int div,
int gate_offset, u8 gate_shift, u8 gate_flags,
unsigned long flags, spinlock_t *lock)
{
struct clk_hw *hw;
struct clk_gate *gate = NULL;
struct clk_fixed_factor *fix = NULL;
/* without gate, register a simple factor clock */
if (gate_offset == 0) {
return clk_register_fixed_factor(NULL, name,
parent_names[0], flags, mult,
div);
}
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
fix = kzalloc(sizeof(*fix), GFP_KERNEL);
if (!fix) {
kfree(gate);
return ERR_PTR(-ENOMEM);
}
fix->mult = mult;
fix->div = div;
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
NULL, NULL,
&fix->hw, &clk_fixed_factor_ops,
&gate->hw, &clk_gate_ops, flags);
if (IS_ERR(hw)) {
kfree(fix);
kfree(gate);
return ERR_CAST(hw);
}
return hw->clk;
}
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
void __iomem *base,
unsigned long nr_clks)
{
struct rockchip_clk_provider *ctx;
struct clk **clk_table;
int i;
ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
if (!ctx)
return ERR_PTR(-ENOMEM);
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
if (!clk_table)
goto err_free;
for (i = 0; i < nr_clks; ++i)
clk_table[i] = ERR_PTR(-ENOENT);
ctx->reg_base = base;
ctx->clk_data.clks = clk_table;
ctx->clk_data.clk_num = nr_clks;
ctx->cru_node = np;
spin_lock_init(&ctx->lock);
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
return ctx;
err_free:
kfree(ctx);
return ERR_PTR(-ENOMEM);
}
EXPORT_SYMBOL_GPL(rockchip_clk_init);
void rockchip_clk_of_add_provider(struct device_node *np,
struct rockchip_clk_provider *ctx)
{
if (of_clk_add_provider(np, of_clk_src_onecell_get,
&ctx->clk_data))
pr_err("%s: could not register clk provider\n", __func__);
}
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
struct clk *clk;
int idx;
for (idx = 0; idx < nr_pll; idx++, list++) {
clk = rockchip_clk_register_pll(ctx, list->type, list->name,
list->parent_names, list->num_parents,
list->con_offset, grf_lock_offset,
list->lock_shift, list->mode_offset,
list->mode_shift, list->rate_table,
list->flags, list->pll_flags);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
struct rockchip_clk_branch *list,
unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
unsigned long flags;
for (idx = 0; idx < nr_clk; idx++, list++) {
flags = list->flags;
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
if (list->mux_table)
clk = clk_register_mux_table(NULL, list->name,
list->parent_names, list->num_parents,
flags,
ctx->reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, list->mux_table,
&ctx->lock);
else
clk = clk_register_mux(NULL, list->name,
list->parent_names, list->num_parents,
flags,
ctx->reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, &ctx->lock);
break;
case branch_muxgrf:
clk = rockchip_clk_register_muxgrf(list->name,
list->parent_names, list->num_parents,
flags, ctx->grf, list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags);
break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,
list->name, list->parent_names[0],
flags,
ctx->reg_base + list->muxdiv_offset,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
&ctx->lock);
else
clk = clk_register_divider(NULL, list->name,
list->parent_names[0], flags,
ctx->reg_base + list->muxdiv_offset,
list->div_shift, list->div_width,
list->div_flags, &ctx->lock);
break;
case branch_fraction_divider:
clk = rockchip_clk_register_frac_branch(ctx, list->name,
list->parent_names, list->num_parents,
ctx->reg_base, list->muxdiv_offset,
list->div_flags,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, list->child,
&ctx->lock);
break;
case branch_half_divider:
clk = rockchip_clk_register_halfdiv(list->name,
list->parent_names, list->num_parents,
ctx->reg_base, list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, list->div_shift,
list->div_width, list->div_flags,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
break;
case branch_gate:
flags |= CLK_SET_RATE_PARENT;
clk = clk_register_gate(NULL, list->name,
list->parent_names[0], flags,
ctx->reg_base + list->gate_offset,
list->gate_shift, list->gate_flags, &ctx->lock);
break;
case branch_composite:
clk = rockchip_clk_register_branch(list->name,
list->parent_names, list->num_parents,
ctx->reg_base, list->muxdiv_offset,
list->mux_shift,
list->mux_width, list->mux_flags,
list->mux_table, list->div_offset,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
break;
case branch_mmc:
clk = rockchip_clk_register_mmc(
list->name,
list->parent_names, list->num_parents,
ctx->reg_base + list->muxdiv_offset,
list->div_shift
);
break;
case branch_inverter:
clk = rockchip_clk_register_inverter(
list->name, list->parent_names,
list->num_parents,
ctx->reg_base + list->muxdiv_offset,
list->div_shift, list->div_flags, &ctx->lock);
break;
case branch_factor:
clk = rockchip_clk_register_factor_branch(
list->name, list->parent_names,
list->num_parents, ctx->reg_base,
list->div_shift, list->div_width,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
break;
case branch_ddrclk:
clk = rockchip_clk_register_ddrclk(
list->name, list->flags,
list->parent_names, list->num_parents,
list->muxdiv_offset, list->mux_shift,
list->mux_width, list->div_shift,
list->div_width, list->div_flags,
ctx->reg_base, &ctx->lock);
break;
}
/* none of the cases above matched */
if (!clk) {
pr_err("%s: unknown clock type %d\n",
__func__, list->branch_type);
continue;
}
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s: %ld\n",
__func__, list->name, PTR_ERR(clk));
continue;
}
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
unsigned int lookup_id,
const char *name, const char *const *parent_names,
u8 num_parents,
const struct rockchip_cpuclk_reg_data *reg_data,
const struct rockchip_cpuclk_rate_table *rates,
int nrates)
{
struct clk *clk;
clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
reg_data, rates, nrates,
ctx->reg_base, &ctx->lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s: %ld\n",
__func__, name, PTR_ERR(clk));
return;
}
rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
void rockchip_clk_protect_critical(const char *const clocks[],
int nclocks)
{
int i;
/* Protect the clocks that needs to stay on */
for (i = 0; i < nclocks; i++) {
struct clk *clk = __clk_lookup(clocks[i]);
clk_prepare_enable(clk);
}
}
EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
static void __iomem *rst_base;
static unsigned int reg_restart;
static void (*cb_restart)(void);
static int rockchip_restart_notify(struct notifier_block *this,
unsigned long mode, void *cmd)
{
if (cb_restart)
cb_restart();
writel(0xfdb9, rst_base + reg_restart);
return NOTIFY_DONE;
}
static struct notifier_block rockchip_restart_handler = {
.notifier_call = rockchip_restart_notify,
.priority = 128,
};
void
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
unsigned int reg,
void (*cb)(void))
{
int ret;
rst_base = ctx->reg_base;
reg_restart = reg;
cb_restart = cb;
ret = register_restart_handler(&rockchip_restart_handler);
if (ret)
pr_err("%s: cannot register restart handler, %d\n",
__func__, ret);
}
EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
| linux-master | drivers/clk/rockchip/clk.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Collabora Ltd.
* Author: Sebastian Reichel <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include "clk.h"
/* 0xFD7C0000 + 0x0A00 */
#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
/* 0xFD7C8000 + 0x0A00 */
#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
/* 0xFD7D0000 + 0x0A00 */
#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
/* 0xFD7F0000 + 0x0A00 */
#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
/* mapping table for reset ID to register offset */
static const int rk3588_register_offset[] = {
/* SOFTRST_CON01 */
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6),
RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8),
RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15),
/* SOFTRST_CON02 */
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1),
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15),
/* SOFTRST_CON03 */
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1),
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2),
RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15),
/* SOFTRST_CON04 */
RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
/* SOFTRST_CON05 */
RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14),
RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15),
/* SOFTRST_CON06 */
RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1),
/* SOFTRST_CON07 */
RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),
/* SOFTRST_CON08 */
RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3),
RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14),
/* SOFTRST_CON09 */
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5),
RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6),
RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
/* SOFTRST_CON10 */
RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3),
RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15),
/* SOFTRST_CON11 */
RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1),
RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2),
RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3),
RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4),
RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5),
RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6),
RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8),
RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12),
RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
/* SOFTRST_CON12 */
RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0),
RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10),
RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13),
/* SOFTRST_CON13 */
RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0),
RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3),
RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6),
RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9),
RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12),
RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15),
/* SOFTRST_CON14 */
RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2),
RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10),
RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12),
RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13),
RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14),
RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15),
/* SOFTRST_CON15 */
RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0),
RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3),
RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6),
RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9),
RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15),
/* SOFTRST_CON16 */
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9),
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14),
RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15),
/* SOFTRST_CON17 */
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0),
RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2),
RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4),
RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7),
RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9),
RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15),
/* SOFTRST_CON18 */
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9),
RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10),
RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11),
/* SOFTRST_CON19 */
RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5),
/* SOFTRST_CON20 */
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3),
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5),
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6),
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7),
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8),
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9),
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10),
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15),
/* SOFTRST_CON21 */
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0),
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1),
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2),
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3),
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4),
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5),
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6),
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15),
/* SOFTRST_CON22 */
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8),
/* SOFTRST_CON23 */
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3),
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5),
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6),
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7),
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8),
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9),
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10),
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15),
/* SOFTRST_CON24 */
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0),
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1),
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2),
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3),
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4),
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5),
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6),
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15),
/* SOFTRST_CON25 */
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8),
/* SOFTRST_CON26 */
RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3),
RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6),
RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8),
/* SOFTRST_CON27 */
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1),
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2),
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3),
/* SOFTRST_CON28 */
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1),
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2),
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3),
/* SOFTRST_CON29 */
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6),
RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8),
RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10),
RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13),
RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14),
/* SOFTRST_CON30 */
RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0),
RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2),
RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3),
RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7),
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9),
/* SOFTRST_CON31 */
RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5),
RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6),
RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7),
RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8),
RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9),
RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10),
RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11),
/* SOFTRST_CON32 */
RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9),
RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10),
RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11),
RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12),
RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13),
RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14),
RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15),
/* SOFTRST_CON33 */
RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0),
RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13),
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15),
/* SOFTRST_CON34 */
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0),
RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9),
/* SOFTRST_CON35 */
RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7),
/* SOFTRST_CON37 */
RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4),
RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5),
RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9),
RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10),
RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11),
RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12),
RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13),
RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14),
RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15),
/* SOFTRST_CON40 */
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2),
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4),
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6),
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7),
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8),
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9),
/* SOFTRST_CON41 */
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5),
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6),
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7),
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8),
/* SOFTRST_CON42 */
RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2),
RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3),
RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7),
RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10),
RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11),
RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12),
RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13),
RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14),
RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15),
/* SOFTRST_CON43 */
RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0),
RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1),
RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2),
/* SOFTRST_CON44 */
RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5),
RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9),
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10),
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11),
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12),
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13),
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14),
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15),
/* SOFTRST_CON45 */
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0),
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1),
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2),
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5),
RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6),
RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8),
RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9),
RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10),
RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11),
RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12),
/* SOFTRST_CON47 */
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5),
RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6),
/* SOFTRST_CON48 */
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5),
RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6),
/* SOFTRST_CON49 */
RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5),
RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7),
RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8),
RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10),
RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11),
/* SOFTRST_CON50 */
RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0),
RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9),
/* SOFTRST_CON51 */
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4),
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5),
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6),
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7),
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8),
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9),
RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13),
/* SOFTRST_CON52 */
RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9),
RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13),
RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14),
RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15),
/* SOFTRST_CON53 */
RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0),
RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1),
RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5),
RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6),
RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7),
RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9),
/* SOFTRST_CON55 */
RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5),
RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10),
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11),
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12),
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13),
RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15),
/* SOFTRST_CON56 */
RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1),
RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8),
RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14),
/* SOFTRST_CON57 */
RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11),
/* SOFTRST_CON59 */
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13),
/* SOFTRST_CON60 */
RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5),
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6),
RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11),
/* SOFTRST_CON61 */
RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2),
RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10),
RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11),
/* SOFTRST_CON62 */
RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0),
RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3),
RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15),
/* SOFTRST_CON63 */
RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13),
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15),
/* SOFTRST_CON64 */
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0),
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1),
RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12),
RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13),
RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14),
RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15),
/* SOFTRST_CON65 */
RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4),
RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8),
/* SOFTRST_CON66 */
RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4),
RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8),
RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9),
RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10),
RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11),
RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12),
RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14),
RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15),
/* SOFTRST_CON67 */
RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0),
RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2),
RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3),
RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4),
/* SOFTRST_CON68 */
RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1),
RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5),
/* SOFTRST_CON69 */
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6),
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10),
RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12),
RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13),
RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14),
/* SOFTRST_CON70 */
RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0),
RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1),
RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2),
RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11),
RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12),
/* SOFTRST_CON72 */
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1),
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2),
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3),
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4),
RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5),
RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6),
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7),
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8),
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9),
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10),
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11),
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM
/* SOFTRST_CON73 */
RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM
RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12),
RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13),
/* SOFTRST_CON74 */
RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1),
RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3),
/* SOFTRST_CON75 */
RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1),
RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2),
RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3),
/* SOFTRST_CON76 */
RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2),
RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3),
RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4),
RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5),
RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6),
/* SOFTRST_CON77 */
RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6),
RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7),
RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8),
/* PHPTOPCRU_SOFTRST_CON00 */
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9),
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10),
/* PMU1CRU_SOFTRST_CON00 */
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12),
RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13),
RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
/* PMU1CRU_SOFTRST_CON01 */
RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6),
RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8),
RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10),
RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12),
RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13),
/* PMU1CRU_SOFTRST_CON02 */
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1),
RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2),
RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6),
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10),
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13),
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14),
RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15),
/* PMU1CRU_SOFTRST_CON03 */
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0),
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12),
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13),
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15),
/* PMU1CRU_SOFTRST_CON04 */
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0),
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1),
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3),
RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4),
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5),
RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6),
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8),
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9),
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10),
/* PMU1CRU_SOFTRST_CON05 */
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),
/* SECURECRU_SOFTRST_CON00 */
RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13),
RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
/* SECURECRU_SOFTRST_CON01 */
RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0),
RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1),
RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3),
RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),
RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12),
RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13),
RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15),
/* SECURECRU_SOFTRST_CON02 */
RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1),
RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2),
RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5),
RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15),
/* SECURECRU_SOFTRST_CON03 */
RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0),
RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2),
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3),
RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4),
RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5),
RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6),
};
void rk3588_rst_init(struct device_node *np, void __iomem *reg_base)
{
rockchip_register_softrst_lut(np,
rk3588_register_offset,
ARRAY_SIZE(rk3588_register_offset),
reg_base + RK3588_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
}
| linux-master | drivers/clk/rockchip/rst-rk3588.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "clk.h"
#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
#define RK3288_GRF_SOC_STATUS1 0x284
enum rk3288_variant {
RK3288_CRU,
RK3288W_CRU,
};
enum rk3288_plls {
apll, dpll, cpll, gpll, npll,
};
static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE(2208000000, 1, 92, 1),
RK3066_PLL_RATE(2184000000, 1, 91, 1),
RK3066_PLL_RATE(2160000000, 1, 90, 1),
RK3066_PLL_RATE(2136000000, 1, 89, 1),
RK3066_PLL_RATE(2112000000, 1, 88, 1),
RK3066_PLL_RATE(2088000000, 1, 87, 1),
RK3066_PLL_RATE(2064000000, 1, 86, 1),
RK3066_PLL_RATE(2040000000, 1, 85, 1),
RK3066_PLL_RATE(2016000000, 1, 84, 1),
RK3066_PLL_RATE(1992000000, 1, 83, 1),
RK3066_PLL_RATE(1968000000, 1, 82, 1),
RK3066_PLL_RATE(1944000000, 1, 81, 1),
RK3066_PLL_RATE(1920000000, 1, 80, 1),
RK3066_PLL_RATE(1896000000, 1, 79, 1),
RK3066_PLL_RATE(1872000000, 1, 78, 1),
RK3066_PLL_RATE(1848000000, 1, 77, 1),
RK3066_PLL_RATE(1824000000, 1, 76, 1),
RK3066_PLL_RATE(1800000000, 1, 75, 1),
RK3066_PLL_RATE(1776000000, 1, 74, 1),
RK3066_PLL_RATE(1752000000, 1, 73, 1),
RK3066_PLL_RATE(1728000000, 1, 72, 1),
RK3066_PLL_RATE(1704000000, 1, 71, 1),
RK3066_PLL_RATE(1680000000, 1, 70, 1),
RK3066_PLL_RATE(1656000000, 1, 69, 1),
RK3066_PLL_RATE(1632000000, 1, 68, 1),
RK3066_PLL_RATE(1608000000, 1, 67, 1),
RK3066_PLL_RATE(1560000000, 1, 65, 1),
RK3066_PLL_RATE(1512000000, 1, 63, 1),
RK3066_PLL_RATE(1488000000, 1, 62, 1),
RK3066_PLL_RATE(1464000000, 1, 61, 1),
RK3066_PLL_RATE(1440000000, 1, 60, 1),
RK3066_PLL_RATE(1416000000, 1, 59, 1),
RK3066_PLL_RATE(1392000000, 1, 58, 1),
RK3066_PLL_RATE(1368000000, 1, 57, 1),
RK3066_PLL_RATE(1344000000, 1, 56, 1),
RK3066_PLL_RATE(1320000000, 1, 55, 1),
RK3066_PLL_RATE(1296000000, 1, 54, 1),
RK3066_PLL_RATE(1272000000, 1, 53, 1),
RK3066_PLL_RATE(1248000000, 1, 52, 1),
RK3066_PLL_RATE(1224000000, 1, 51, 1),
RK3066_PLL_RATE(1200000000, 1, 50, 1),
RK3066_PLL_RATE(1188000000, 2, 99, 1),
RK3066_PLL_RATE(1176000000, 1, 49, 1),
RK3066_PLL_RATE(1128000000, 1, 47, 1),
RK3066_PLL_RATE(1104000000, 1, 46, 1),
RK3066_PLL_RATE(1008000000, 1, 84, 2),
RK3066_PLL_RATE( 912000000, 1, 76, 2),
RK3066_PLL_RATE( 891000000, 8, 594, 2),
RK3066_PLL_RATE( 888000000, 1, 74, 2),
RK3066_PLL_RATE( 816000000, 1, 68, 2),
RK3066_PLL_RATE( 798000000, 2, 133, 2),
RK3066_PLL_RATE( 792000000, 1, 66, 2),
RK3066_PLL_RATE( 768000000, 1, 64, 2),
RK3066_PLL_RATE( 742500000, 8, 495, 2),
RK3066_PLL_RATE( 696000000, 1, 58, 2),
RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
RK3066_PLL_RATE( 600000000, 1, 50, 2),
RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
RK3066_PLL_RATE( 552000000, 1, 46, 2),
RK3066_PLL_RATE( 504000000, 1, 84, 4),
RK3066_PLL_RATE( 500000000, 3, 125, 2),
RK3066_PLL_RATE( 456000000, 1, 76, 4),
RK3066_PLL_RATE( 428000000, 1, 107, 6),
RK3066_PLL_RATE( 408000000, 1, 68, 4),
RK3066_PLL_RATE( 400000000, 3, 100, 2),
RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
RK3066_PLL_RATE( 384000000, 2, 128, 4),
RK3066_PLL_RATE( 360000000, 1, 60, 4),
RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
RK3066_PLL_RATE( 312000000, 1, 52, 4),
RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),
RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
RK3066_PLL_RATE( 300000000, 1, 75, 6),
RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
RK3066_PLL_RATE( 273600000, 1, 114, 10),
RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),
RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),
RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),
RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),
RK3066_PLL_RATE( 252000000, 1, 84, 8),
RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),
RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),
RK3066_PLL_RATE( 238000000, 1, 119, 12),
RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),
RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),
RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),
RK3066_PLL_RATE( 195428571, 1, 114, 14),
RK3066_PLL_RATE( 160000000, 1, 80, 12),
RK3066_PLL_RATE( 157500000, 1, 105, 16),
RK3066_PLL_RATE( 126000000, 1, 84, 16),
{ /* sentinel */ },
};
#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
#define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
#define RK3288_DIV_L2RAM_MASK 0x7
#define RK3288_DIV_L2RAM_SHIFT 0
#define RK3288_DIV_ATCLK_MASK 0x1f
#define RK3288_DIV_ATCLK_SHIFT 4
#define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
#define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
#define RK3288_CLKSEL0(_core_m0, _core_mp) \
{ \
.reg = RK3288_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
RK3288_DIV_ACLK_CORE_MP_SHIFT), \
}
#define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
{ \
.reg = RK3288_CLKSEL_CON(37), \
.val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
RK3288_DIV_L2RAM_SHIFT) | \
HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
RK3288_DIV_ATCLK_SHIFT) | \
HIWORD_UPDATE(_pclk_dbg_pre, \
RK3288_DIV_PCLK_DBGPRE_MASK, \
RK3288_DIV_PCLK_DBGPRE_SHIFT), \
}
#define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
{ \
.prate = _prate, \
.divs = { \
RK3288_CLKSEL0(_core_m0, _core_mp), \
RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
};
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
.core_reg[0] = RK3288_CLKSEL_CON(0),
.div_core_shift[0] = 8,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 15,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
"sclk_otgphy0_480m" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
RK3288_MODE_CON, 4, 5, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 3, .div = 4 },
{ /* sentinel */},
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 0, GFLAGS),
COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 1, GFLAGS),
COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 2, GFLAGS),
COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 3, GFLAGS),
COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 4, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 5, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 6, GFLAGS),
COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 7, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 8, GFLAGS),
GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
RK3288_CLKGATE_CON(12), 9, GFLAGS),
GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 10, GFLAGS),
GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
RK3288_CLKGATE_CON(12), 11, GFLAGS),
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 8, GFLAGS),
GATE(0, "gpll_ddr", "gpll", 0,
RK3288_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 10, GFLAGS),
GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
RK3288_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
RK3288_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "c2c_host", "aclk_cpu_src", 0,
RK3288_CLKGATE_CON(13), 8, GFLAGS),
COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
RK3288_CLKGATE_CON(5), 4, GFLAGS),
GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(0), 7, GFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(8), 0,
RK3288_CLKGATE_CON(4), 2, GFLAGS,
&rk3288_i2s_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
RK3288_CLKGATE_CON(4), 0, GFLAGS),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 3, GFLAGS),
MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(9), 0,
RK3288_CLKGATE_CON(4), 5, GFLAGS,
&rk3288_spdif_fracmux),
GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 6, GFLAGS),
COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 7, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(41), 0,
RK3288_CLKGATE_CON(4), 8, GFLAGS,
&rk3288_spdif_8ch_fracmux),
GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 9, GFLAGS),
GATE(0, "sclk_acc_efuse", "xin24m", 0,
RK3288_CLKGATE_CON(0), 12, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
RK3288_CLKGATE_CON(1), 0, GFLAGS),
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
RK3288_CLKGATE_CON(1), 1, GFLAGS),
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
RK3288_CLKGATE_CON(1), 2, GFLAGS),
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
RK3288_CLKGATE_CON(1), 3, GFLAGS),
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
RK3288_CLKGATE_CON(1), 4, GFLAGS),
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
RK3288_CLKGATE_CON(1), 5, GFLAGS),
/*
* Clock-Architecture Diagram 2
*/
COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 9, GFLAGS),
COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 11, GFLAGS),
MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
RK3288_CLKGATE_CON(9), 0, GFLAGS),
FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,
RK3288_CLKGATE_CON(3), 10, GFLAGS),
GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
RK3288_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 5, GFLAGS),
COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 12, GFLAGS),
COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 13, GFLAGS),
COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 14, GFLAGS),
COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 15, GFLAGS),
GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK3288_CLKGATE_CON(5), 12, GFLAGS),
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3288_CLKGATE_CON(5), 11, GFLAGS),
COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 13, GFLAGS),
DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 14, GFLAGS),
COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 15, GFLAGS),
COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 7, GFLAGS),
COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
DIV(0, "pclk_pd_alive", "gpll", 0,
RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 8, GFLAGS),
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 7, GFLAGS),
COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKGATE_CON(2), 3, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKGATE_CON(2), 2, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(2), 1, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3288_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(13), 0, GFLAGS),
COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(13), 1, GFLAGS),
COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(13), 2, GFLAGS),
COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(13), 3, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 11, GFLAGS),
COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 10, GFLAGS),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 4, GFLAGS),
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 5, GFLAGS),
GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 6, GFLAGS),
GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 7, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
RK3288_CLKGATE_CON(2), 7, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
RK3288_CLKGATE_CON(2), 8, GFLAGS),
GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
RK3288_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 5, GFLAGS),
COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 6, GFLAGS),
COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(17), 0,
RK3288_CLKGATE_CON(1), 9, GFLAGS,
&rk3288_uart0_fracmux),
MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(18), 0,
RK3288_CLKGATE_CON(1), 11, GFLAGS,
&rk3288_uart1_fracmux),
COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(19), 0,
RK3288_CLKGATE_CON(1), 13, GFLAGS,
&rk3288_uart2_fracmux),
COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(20), 0,
RK3288_CLKGATE_CON(1), 15, GFLAGS,
&rk3288_uart3_fracmux),
COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(7), 0,
RK3288_CLKGATE_CON(2), 13, GFLAGS,
&rk3288_uart4_fracmux),
COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(2), 5, GFLAGS),
MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 3, GFLAGS),
GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 2, GFLAGS),
GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 0, GFLAGS),
GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(2), 6, GFLAGS),
MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
RK3288_CLKSEL_CON(22), 7, IFLAGS),
GATE(0, "jtag", "ext_jtag", 0,
RK3288_CLKGATE_CON(4), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
RK3288_CLKGATE_CON(5), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
RK3288_CLKGATE_CON(13), 9, GFLAGS),
DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
/*
* Clock-Architecture Diagram 4
*/
/* aclk_cpu gates */
GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
/* hclk_cpu gates */
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
/* pclk_cpu gates */
GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
/* ddrctrl [DDR Controller PHY clock] gates */
GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
/* ddrphy gates */
GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
/* aclk_peri gates */
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
/* hclk_peri gates */
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
/* sclk_gpu gates */
GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
/* pclk_pd_alive gates */
GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
/* pclk_pd_pmu gates */
GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
/* hclk_vio gates */
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
/* aclk_vio0 gates */
GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
/* aclk_vio1 gates */
GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
/* aclk_rga_pre gates */
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
/*
* Other ungrouped clocks.
*/
GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
};
static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
DIV(0, "hclk_vio", "aclk_vio1", 0,
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
};
static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
DIV(0, "hclk_vio", "aclk_vio0", 0,
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
};
static const char *const rk3288_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
"aclk_peri_niu",
"aclk_vio0_niu",
"aclk_vio1_niu",
"aclk_rga_niu",
"hclk_peri",
"hclk_vio_niu",
"pclk_alive_niu",
"pclk_pd_pmu",
"pclk_pmu_niu",
"pmu_hclk_otg0",
/* pwm-regulators on some boards, so handoff-critical later */
"pclk_rkpwm",
};
static void __iomem *rk3288_cru_base;
/*
* Some CRU registers will be reset in maskrom when the system
* wakes up from fastboot.
* So save them before suspend, restore them after resume.
*/
static const int rk3288_saved_cru_reg_ids[] = {
RK3288_MODE_CON,
RK3288_CLKSEL_CON(0),
RK3288_CLKSEL_CON(1),
RK3288_CLKSEL_CON(10),
RK3288_CLKSEL_CON(33),
RK3288_CLKSEL_CON(37),
/* We turn aclk_dmac1 on for suspend; this will restore it */
RK3288_CLKGATE_CON(10),
};
static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
static int rk3288_clk_suspend(void)
{
int i, reg_id;
for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
reg_id = rk3288_saved_cru_reg_ids[i];
rk3288_saved_cru_regs[i] =
readl_relaxed(rk3288_cru_base + reg_id);
}
/*
* Going into deep sleep (specifically setting PMU_CLR_DMA in
* RK3288_PMU_PWRMODE_CON1) appears to fail unless
* "aclk_dmac1" is on.
*/
writel_relaxed(1 << (12 + 16),
rk3288_cru_base + RK3288_CLKGATE_CON(10));
/*
* Switch PLLs other than DPLL (for SDRAM) to slow mode to
* avoid crashes on resume. The Mask ROM on the system will
* put APLL, CPLL, and GPLL into slow mode at resume time
* anyway (which is why we restore them), but we might not
* even make it to the Mask ROM if this isn't done at suspend
* time.
*
* NOTE: only APLL truly matters here, but we'll do them all.
*/
writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
return 0;
}
static void rk3288_clk_resume(void)
{
int i, reg_id;
for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
reg_id = rk3288_saved_cru_reg_ids[i];
writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
rk3288_cru_base + reg_id);
}
}
static void rk3288_clk_shutdown(void)
{
writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
}
static struct syscore_ops rk3288_clk_syscore_ops = {
.suspend = rk3288_clk_suspend,
.resume = rk3288_clk_resume,
};
static void __init rk3288_common_init(struct device_node *np,
enum rk3288_variant soc)
{
struct rockchip_clk_provider *ctx;
rk3288_cru_base = of_iomap(np, 0);
if (!rk3288_cru_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(rk3288_cru_base);
return;
}
rockchip_clk_register_plls(ctx, rk3288_pll_clks,
ARRAY_SIZE(rk3288_pll_clks),
RK3288_GRF_SOC_STATUS1);
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
ARRAY_SIZE(rk3288_clk_branches));
if (soc == RK3288W_CRU)
rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
ARRAY_SIZE(rk3288w_hclkvio_branch));
else
rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
ARRAY_SIZE(rk3288_hclkvio_branch));
rockchip_clk_protect_critical(rk3288_critical_clocks,
ARRAY_SIZE(rk3288_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3288_cpuclk_data, rk3288_cpuclk_rates,
ARRAY_SIZE(rk3288_cpuclk_rates));
rockchip_register_softrst(np, 12,
rk3288_cru_base + RK3288_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
rk3288_clk_shutdown);
register_syscore_ops(&rk3288_clk_syscore_ops);
rockchip_clk_of_add_provider(np, ctx);
}
static void __init rk3288_clk_init(struct device_node *np)
{
rk3288_common_init(np, RK3288_CRU);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
static void __init rk3288w_clk_init(struct device_node *np)
{
rk3288_common_init(np, RK3288W_CRU);
}
CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3288.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/rk3188-cru-common.h>
#include "clk.h"
#define RK3066_GRF_SOC_STATUS 0x15c
#define RK3188_GRF_SOC_STATUS 0xac
enum rk3188_plls {
apll, cpll, dpll, gpll,
};
static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
RK3066_PLL_RATE(2208000000, 1, 92, 1),
RK3066_PLL_RATE(2184000000, 1, 91, 1),
RK3066_PLL_RATE(2160000000, 1, 90, 1),
RK3066_PLL_RATE(2136000000, 1, 89, 1),
RK3066_PLL_RATE(2112000000, 1, 88, 1),
RK3066_PLL_RATE(2088000000, 1, 87, 1),
RK3066_PLL_RATE(2064000000, 1, 86, 1),
RK3066_PLL_RATE(2040000000, 1, 85, 1),
RK3066_PLL_RATE(2016000000, 1, 84, 1),
RK3066_PLL_RATE(1992000000, 1, 83, 1),
RK3066_PLL_RATE(1968000000, 1, 82, 1),
RK3066_PLL_RATE(1944000000, 1, 81, 1),
RK3066_PLL_RATE(1920000000, 1, 80, 1),
RK3066_PLL_RATE(1896000000, 1, 79, 1),
RK3066_PLL_RATE(1872000000, 1, 78, 1),
RK3066_PLL_RATE(1848000000, 1, 77, 1),
RK3066_PLL_RATE(1824000000, 1, 76, 1),
RK3066_PLL_RATE(1800000000, 1, 75, 1),
RK3066_PLL_RATE(1776000000, 1, 74, 1),
RK3066_PLL_RATE(1752000000, 1, 73, 1),
RK3066_PLL_RATE(1728000000, 1, 72, 1),
RK3066_PLL_RATE(1704000000, 1, 71, 1),
RK3066_PLL_RATE(1680000000, 1, 70, 1),
RK3066_PLL_RATE(1656000000, 1, 69, 1),
RK3066_PLL_RATE(1632000000, 1, 68, 1),
RK3066_PLL_RATE(1608000000, 1, 67, 1),
RK3066_PLL_RATE(1560000000, 1, 65, 1),
RK3066_PLL_RATE(1512000000, 1, 63, 1),
RK3066_PLL_RATE(1488000000, 1, 62, 1),
RK3066_PLL_RATE(1464000000, 1, 61, 1),
RK3066_PLL_RATE(1440000000, 1, 60, 1),
RK3066_PLL_RATE(1416000000, 1, 59, 1),
RK3066_PLL_RATE(1392000000, 1, 58, 1),
RK3066_PLL_RATE(1368000000, 1, 57, 1),
RK3066_PLL_RATE(1344000000, 1, 56, 1),
RK3066_PLL_RATE(1320000000, 1, 55, 1),
RK3066_PLL_RATE(1296000000, 1, 54, 1),
RK3066_PLL_RATE(1272000000, 1, 53, 1),
RK3066_PLL_RATE(1248000000, 1, 52, 1),
RK3066_PLL_RATE(1224000000, 1, 51, 1),
RK3066_PLL_RATE(1200000000, 1, 50, 1),
RK3066_PLL_RATE(1188000000, 2, 99, 1),
RK3066_PLL_RATE(1176000000, 1, 49, 1),
RK3066_PLL_RATE(1128000000, 1, 47, 1),
RK3066_PLL_RATE(1104000000, 1, 46, 1),
RK3066_PLL_RATE(1008000000, 1, 84, 2),
RK3066_PLL_RATE( 912000000, 1, 76, 2),
RK3066_PLL_RATE( 891000000, 8, 594, 2),
RK3066_PLL_RATE( 888000000, 1, 74, 2),
RK3066_PLL_RATE( 816000000, 1, 68, 2),
RK3066_PLL_RATE( 798000000, 2, 133, 2),
RK3066_PLL_RATE( 792000000, 1, 66, 2),
RK3066_PLL_RATE( 768000000, 1, 64, 2),
RK3066_PLL_RATE( 742500000, 8, 495, 2),
RK3066_PLL_RATE( 696000000, 1, 58, 2),
RK3066_PLL_RATE( 600000000, 1, 50, 2),
RK3066_PLL_RATE( 594000000, 2, 198, 4),
RK3066_PLL_RATE( 552000000, 1, 46, 2),
RK3066_PLL_RATE( 504000000, 1, 84, 4),
RK3066_PLL_RATE( 456000000, 1, 76, 4),
RK3066_PLL_RATE( 408000000, 1, 68, 4),
RK3066_PLL_RATE( 400000000, 3, 100, 2),
RK3066_PLL_RATE( 384000000, 2, 128, 4),
RK3066_PLL_RATE( 360000000, 1, 60, 4),
RK3066_PLL_RATE( 312000000, 1, 52, 4),
RK3066_PLL_RATE( 300000000, 1, 50, 4),
RK3066_PLL_RATE( 297000000, 2, 198, 8),
RK3066_PLL_RATE( 252000000, 1, 84, 8),
RK3066_PLL_RATE( 216000000, 1, 72, 8),
RK3066_PLL_RATE( 148500000, 2, 99, 8),
RK3066_PLL_RATE( 126000000, 1, 84, 16),
RK3066_PLL_RATE( 48000000, 1, 64, 32),
{ /* sentinel */ },
};
#define RK3066_DIV_CORE_PERIPH_MASK 0x3
#define RK3066_DIV_CORE_PERIPH_SHIFT 6
#define RK3066_DIV_ACLK_CORE_MASK 0x7
#define RK3066_DIV_ACLK_CORE_SHIFT 0
#define RK3066_DIV_ACLK_HCLK_MASK 0x3
#define RK3066_DIV_ACLK_HCLK_SHIFT 8
#define RK3066_DIV_ACLK_PCLK_MASK 0x3
#define RK3066_DIV_ACLK_PCLK_SHIFT 12
#define RK3066_DIV_AHB2APB_MASK 0x3
#define RK3066_DIV_AHB2APB_SHIFT 14
#define RK3066_CLKSEL0(_core_peri) \
{ \
.reg = RK2928_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
RK3066_DIV_CORE_PERIPH_SHIFT) \
}
#define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \
{ \
.reg = RK2928_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
RK3066_DIV_ACLK_CORE_SHIFT) | \
HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
RK3066_DIV_ACLK_HCLK_SHIFT) | \
HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
RK3066_DIV_ACLK_PCLK_SHIFT) | \
HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
RK3066_DIV_AHB2APB_SHIFT), \
}
#define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
{ \
.prate = _prate, \
.divs = { \
RK3066_CLKSEL0(_core_peri), \
RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
};
static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
.core_reg[0] = RK2928_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 8,
.mux_core_mask = 0x1,
};
#define RK3188_DIV_ACLK_CORE_MASK 0x7
#define RK3188_DIV_ACLK_CORE_SHIFT 3
#define RK3188_CLKSEL1(_aclk_core) \
{ \
.reg = RK2928_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
RK3188_DIV_ACLK_CORE_SHIFT) \
}
#define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \
{ \
.prate = _prate, \
.divs = { \
RK3066_CLKSEL0(_core_peri), \
RK3188_CLKSEL1(_aclk_core), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
RK3188_CPUCLK_RATE(1608000000, 2, 3),
RK3188_CPUCLK_RATE(1416000000, 2, 3),
RK3188_CPUCLK_RATE(1200000000, 2, 3),
RK3188_CPUCLK_RATE(1008000000, 2, 3),
RK3188_CPUCLK_RATE( 816000000, 2, 3),
RK3188_CPUCLK_RATE( 600000000, 1, 3),
RK3188_CPUCLK_RATE( 504000000, 1, 3),
RK3188_CPUCLK_RATE( 312000000, 0, 1),
};
static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
.core_reg[0] = RK2928_CLKSEL_CON(0),
.div_core_shift[0] = 9,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 8,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
PNAME(mux_mac_p) = { "gpll", "dpll" };
PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
RK2928_MODE_CON, 4, 4, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
};
static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
RK2928_MODE_CON, 4, 5, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
/* 2 ^ (val + 1) */
static struct clk_div_table div_core_peri_t[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 4 },
{ .val = 2, .div = 8 },
{ .val = 3, .div = 16 },
{ /* sentinel */ },
};
static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
static struct rockchip_clk_branch common_spdif_fracmux __initdata =
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch common_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
static struct rockchip_clk_branch common_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch common_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
static struct rockchip_clk_branch common_uart3_fracmux __initdata =
MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
static struct rockchip_clk_branch common_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
*/
GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
/* these two are set by the cpuclk and should not be changed */
COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 9, GFLAGS),
GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
RK2928_CLKGATE_CON(3), 10, GFLAGS),
COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
RK2928_CLKGATE_CON(0), 3, GFLAGS),
GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0,
RK2928_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0,
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0,
RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(2), 3, GFLAGS),
MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 7, GFLAGS),
MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
GATE(0, "pclkin_cif0", "ext_cif0", 0,
RK2928_CLKGATE_CON(3), 3, GFLAGS),
INVERTER(0, "pclk_cif0", "pclkin_cif0",
RK2928_CLKSEL_CON(30), 8, IFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/*
* the 480m are generated inside the usb block from these clocks,
* but they are also a source for the hsicphy clock.
*/
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE(0, "mac_src", mux_mac_p, 0,
RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
RK2928_CLKSEL_CON(23), 0,
RK2928_CLKGATE_CON(2), 7, GFLAGS,
&common_hsadc_out_fracmux),
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
RK2928_CLKSEL_CON(22), 7, IFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(0), 14, GFLAGS,
&common_spdif_fracmux),
/*
* Clock-Architecture Diagram 4
*/
GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 13, GFLAGS),
COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 14, GFLAGS),
MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&common_uart0_fracmux),
COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&common_uart1_fracmux),
COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&common_uart2_fracmux),
COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(1), 15, GFLAGS,
&common_uart3_fracmux),
GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
/* clk_core_pre gates */
GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
/* aclk_cpu gates */
GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
/* hclk_ahb2apb is part of a clk branch */
GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
/* hclk_peri gates */
GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
/* aclk_lcdc0_pre gates */
GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
/* aclk_lcdc1_pre gates */
GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
/* atclk_cpu gates */
GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
/* pclk_cpu gates */
GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
/* aclk_peri */
GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
/* pclk_peri gates */
GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
};
PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
static struct clk_div_table div_aclk_cpu_t[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 3 },
{ .val = 3, .div = 4 },
{ .val = 4, .div = 8 },
{ /* sentinel */ },
};
static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
| CLK_DIVIDER_READ_ONLY),
DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
| CLK_DIVIDER_READ_ONLY),
COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
| CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(4), 9, GFLAGS),
GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(9), 4, GFLAGS),
COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 8, GFLAGS),
MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
GATE(0, "pclkin_cif1", "ext_cif1", 0,
RK2928_CLKGATE_CON(3), 4, GFLAGS),
INVERTER(0, "pclk_cif1", "pclkin_cif1",
RK2928_CLKSEL_CON(30), 12, IFLAGS),
COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 13, GFLAGS),
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
RK2928_CLKGATE_CON(5), 15, GFLAGS),
GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(6), 0,
RK2928_CLKGATE_CON(0), 8, GFLAGS,
&rk3066a_i2s0_fracmux),
COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3066a_i2s1_fracmux),
COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(8), 0,
RK2928_CLKGATE_CON(0), 12, GFLAGS,
&rk3066a_i2s2_fracmux),
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(5), 14, GFLAGS),
GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
};
static struct clk_div_table div_rk3188_aclk_core_t[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 3 },
{ .val = 3, .div = 4 },
{ .val = 4, .div = 8 },
{ /* sentinel */ },
};
PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
"gpll", "cpll" };
static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
/* do not source aclk_cpu_pre from the apll, to keep complexity down */
COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(4), 9, GFLAGS),
GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(9), 4, GFLAGS),
COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 15, GFLAGS),
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
RK2928_CLKGATE_CON(9), 7, GFLAGS),
GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
RK2928_CLKGATE_CON(3), 6, GFLAGS),
DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3188_i2s0_fracmux),
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
};
static const char *const rk3188_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
"hclk_peri",
"pclk_cpu",
"pclk_peri",
"hclk_cpubus",
"hclk_vio_bus",
"sclk_mac_lbtest",
};
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return ERR_PTR(-ENOMEM);
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return ERR_PTR(-ENOMEM);
}
rockchip_clk_register_branches(ctx, common_clk_branches,
ARRAY_SIZE(common_clk_branches));
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
return ctx;
}
static void __init rk3066a_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
ctx = rk3188_common_clk_init(np);
if (IS_ERR(ctx))
return;
rockchip_clk_register_plls(ctx, rk3066_pll_clks,
ARRAY_SIZE(rk3066_pll_clks),
RK3066_GRF_SOC_STATUS);
rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
ARRAY_SIZE(rk3066a_clk_branches));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3066_cpuclk_data, rk3066_cpuclk_rates,
ARRAY_SIZE(rk3066_cpuclk_rates));
rockchip_clk_protect_critical(rk3188_critical_clocks,
ARRAY_SIZE(rk3188_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
static void __init rk3188a_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
struct clk *clk1, *clk2;
unsigned long rate;
int ret;
ctx = rk3188_common_clk_init(np);
if (IS_ERR(ctx))
return;
rockchip_clk_register_plls(ctx, rk3188_pll_clks,
ARRAY_SIZE(rk3188_pll_clks),
RK3188_GRF_SOC_STATUS);
rockchip_clk_register_branches(ctx, rk3188_clk_branches,
ARRAY_SIZE(rk3188_clk_branches));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3188_cpuclk_data, rk3188_cpuclk_rates,
ARRAY_SIZE(rk3188_cpuclk_rates));
/* reparent aclk_cpu_pre from apll */
clk1 = __clk_lookup("aclk_cpu_pre");
clk2 = __clk_lookup("gpll");
if (clk1 && clk2) {
rate = clk_get_rate(clk1);
ret = clk_set_parent(clk1, clk2);
if (ret < 0)
pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
__func__);
clk_set_rate(clk1, rate);
} else {
pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
__func__);
}
rockchip_clk_protect_critical(rk3188_critical_clocks,
ARRAY_SIZE(rk3188_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
static void __init rk3188_clk_init(struct device_node *np)
{
int i;
for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
struct rockchip_pll_rate_table *rate;
if (!pll->rate_table)
continue;
rate = pll->rate_table;
while (rate->rate > 0) {
rate->nb = 1;
rate++;
}
}
rk3188a_clk_init(np);
}
CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3188.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include "clk.h"
struct rockchip_muxgrf_clock {
struct clk_hw hw;
struct regmap *regmap;
u32 reg;
u32 shift;
u32 width;
int flags;
};
#define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
{
struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
unsigned int mask = GENMASK(mux->width - 1, 0);
unsigned int val;
regmap_read(mux->regmap, mux->reg, &val);
val >>= mux->shift;
val &= mask;
return val;
}
static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
{
struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
val = index;
val <<= mux->shift;
if (mux->flags & CLK_MUX_HIWORD_MASK)
return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
else
return regmap_update_bits(mux->regmap, mux->reg, mask, val);
}
static const struct clk_ops rockchip_muxgrf_clk_ops = {
.get_parent = rockchip_muxgrf_get_parent,
.set_parent = rockchip_muxgrf_set_parent,
.determine_rate = __clk_mux_determine_rate,
};
struct clk *rockchip_clk_register_muxgrf(const char *name,
const char *const *parent_names, u8 num_parents,
int flags, struct regmap *regmap, int reg,
int shift, int width, int mux_flags)
{
struct rockchip_muxgrf_clock *muxgrf_clock;
struct clk_init_data init;
struct clk *clk;
if (IS_ERR(regmap)) {
pr_err("%s: regmap not available\n", __func__);
return ERR_PTR(-ENOTSUPP);
}
muxgrf_clock = kmalloc(sizeof(*muxgrf_clock), GFP_KERNEL);
if (!muxgrf_clock)
return ERR_PTR(-ENOMEM);
init.name = name;
init.flags = flags;
init.num_parents = num_parents;
init.parent_names = parent_names;
init.ops = &rockchip_muxgrf_clk_ops;
muxgrf_clock->hw.init = &init;
muxgrf_clock->regmap = regmap;
muxgrf_clock->reg = reg;
muxgrf_clock->shift = shift;
muxgrf_clock->width = width;
muxgrf_clock->flags = mux_flags;
clk = clk_register(NULL, &muxgrf_clock->hw);
if (IS_ERR(clk))
kfree(muxgrf_clock);
return clk;
}
| linux-master | drivers/clk/rockchip/clk-muxgrf.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*
* based on clk/samsung/clk-cpu.c
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Thomas Abraham <[email protected]>
*
* A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.
* The CPU clock is typically derived from a hierarchy of clock
* blocks which includes mux and divider blocks. There are a number of other
* auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
* clock for CPU domain. The rates of these auxiliary clocks are related to the
* CPU clock rate and this relation is usually specified in the hardware manual
* of the SoC or supplied after the SoC characterization.
*
* The below implementation of the CPU clock allows the rate changes of the CPU
* clock and the corresponding rate changes of the auxillary clocks of the CPU
* domain. The platform clock driver provides a clock register configuration
* for each configurable rate which is then used to program the clock hardware
* registers to acheive a fast co-oridinated rate change for all the CPU domain
* clocks.
*
* On a rate change request for the CPU clock, the rate change is propagated
* upto the PLL supplying the clock to the CPU domain clock blocks. While the
* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
* alternate clock source. If required, the alternate clock source is divided
* down in order to keep the output clock rate within the previous OPP limits.
*/
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include "clk.h"
/**
* struct rockchip_cpuclk: information about clock supplied to a CPU core.
* @hw: handle between ccf and cpu clock.
* @alt_parent: alternate parent clock to use when switching the speed
* of the primary parent clock.
* @reg_base: base register for cpu-clock values.
* @clk_nb: clock notifier registered for changes in clock speed of the
* primary parent clock.
* @rate_count: number of rates in the rate_table
* @rate_table: pll-rates and their associated dividers
* @reg_data: cpu-specific register settings
* @lock: clock lock
*/
struct rockchip_cpuclk {
struct clk_hw hw;
struct clk *alt_parent;
void __iomem *reg_base;
struct notifier_block clk_nb;
unsigned int rate_count;
struct rockchip_cpuclk_rate_table *rate_table;
const struct rockchip_cpuclk_reg_data *reg_data;
spinlock_t *lock;
};
#define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw)
#define to_rockchip_cpuclk_nb(nb) \
container_of(nb, struct rockchip_cpuclk, clk_nb)
static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings(
struct rockchip_cpuclk *cpuclk, unsigned long rate)
{
const struct rockchip_cpuclk_rate_table *rate_table =
cpuclk->rate_table;
int i;
for (i = 0; i < cpuclk->rate_count; i++) {
if (rate == rate_table[i].prate)
return &rate_table[i];
}
return NULL;
}
static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
clksel0 >>= reg_data->div_core_shift[0];
clksel0 &= reg_data->div_core_mask[0];
return parent_rate / (clksel0 + 1);
}
static const struct clk_ops rockchip_cpuclk_ops = {
.recalc_rate = rockchip_cpuclk_recalc_rate,
};
static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate)
{
int i;
/* alternate parent is active now. set the dividers */
for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {
const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];
if (!clksel->reg)
continue;
pr_debug("%s: setting reg 0x%x to 0x%x\n",
__func__, clksel->reg, clksel->val);
writel(clksel->val, cpuclk->reg_base + clksel->reg);
}
}
static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate)
{
int i;
/* alternate parent is active now. set the pre_muxs */
for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
if (!clksel->reg)
break;
pr_debug("%s: setting reg 0x%x to 0x%x\n",
__func__, clksel->reg, clksel->val);
writel(clksel->val, cpuclk->reg_base + clksel->reg);
}
}
static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate)
{
int i;
/* alternate parent is active now. set the muxs */
for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
if (!clksel->reg)
break;
pr_debug("%s: setting reg 0x%x to 0x%x\n",
__func__, clksel->reg, clksel->val);
writel(clksel->val, cpuclk->reg_base + clksel->reg);
}
}
static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
struct clk_notifier_data *ndata)
{
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
const struct rockchip_cpuclk_rate_table *rate;
unsigned long alt_prate, alt_div;
unsigned long flags;
int i = 0;
/* check validity of the new rate */
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for cpuclk\n",
__func__, ndata->new_rate);
return -EINVAL;
}
alt_prate = clk_get_rate(cpuclk->alt_parent);
spin_lock_irqsave(cpuclk->lock, flags);
/*
* If the old parent clock speed is less than the clock speed
* of the alternate parent, then it should be ensured that at no point
* the armclk speed is more than the old_rate until the dividers are
* set.
*/
if (alt_prate > ndata->old_rate) {
/* calculate dividers */
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
if (alt_div > reg_data->div_core_mask[0]) {
pr_warn("%s: limiting alt-divider %lu to %d\n",
__func__, alt_div, reg_data->div_core_mask[0]);
alt_div = reg_data->div_core_mask[0];
}
/*
* Change parents and add dividers in a single transaction.
*
* NOTE: we do this in a single transaction so we're never
* dividing the primary parent by the extra dividers that were
* needed for the alt.
*/
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
__func__, alt_div, alt_prate, ndata->old_rate);
for (i = 0; i < reg_data->num_cores; i++) {
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
reg_data->div_core_shift[i]),
cpuclk->reg_base + reg_data->core_reg[i]);
}
}
rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
/* select alternate parent */
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->mux_core_reg);
else
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
struct clk_notifier_data *ndata)
{
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
const struct rockchip_cpuclk_rate_table *rate;
unsigned long flags;
int i = 0;
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for cpuclk\n",
__func__, ndata->new_rate);
return -EINVAL;
}
spin_lock_irqsave(cpuclk->lock, flags);
if (ndata->old_rate < ndata->new_rate)
rockchip_cpuclk_set_dividers(cpuclk, rate);
/*
* post-rate change event, re-mux to primary parent and remove dividers.
*
* NOTE: we do this in a single transaction so we're never dividing the
* primary parent by the extra dividers that were needed for the alt.
*/
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_main,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->mux_core_reg);
else
writel(HIWORD_UPDATE(reg_data->mux_core_main,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
rockchip_cpuclk_set_post_muxs(cpuclk, rate);
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
reg_data->div_core_shift[i]),
cpuclk->reg_base + reg_data->core_reg[i]);
}
if (ndata->old_rate > ndata->new_rate)
rockchip_cpuclk_set_dividers(cpuclk, rate);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
/*
* This clock notifier is called when the frequency of the parent clock
* of cpuclk is to be changed. This notifier handles the setting up all
* the divider clocks, remux to temporary parent and handling the safe
* frequency levels when using temporary parent.
*/
static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
int ret = 0;
pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
__func__, event, ndata->old_rate, ndata->new_rate);
if (event == PRE_RATE_CHANGE)
ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
else if (event == POST_RATE_CHANGE)
ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
return notifier_from_errno(ret);
}
struct clk *rockchip_clk_register_cpuclk(const char *name,
const char *const *parent_names, u8 num_parents,
const struct rockchip_cpuclk_reg_data *reg_data,
const struct rockchip_cpuclk_rate_table *rates,
int nrates, void __iomem *reg_base, spinlock_t *lock)
{
struct rockchip_cpuclk *cpuclk;
struct clk_init_data init;
struct clk *clk, *cclk;
int ret;
if (num_parents < 2) {
pr_err("%s: needs at least two parent clocks\n", __func__);
return ERR_PTR(-EINVAL);
}
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
if (!cpuclk)
return ERR_PTR(-ENOMEM);
init.name = name;
init.parent_names = &parent_names[reg_data->mux_core_main];
init.num_parents = 1;
init.ops = &rockchip_cpuclk_ops;
/* only allow rate changes when we have a rate table */
init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0;
/* disallow automatic parent changes by ccf */
init.flags |= CLK_SET_RATE_NO_REPARENT;
init.flags |= CLK_GET_RATE_NOCACHE;
cpuclk->reg_base = reg_base;
cpuclk->lock = lock;
cpuclk->reg_data = reg_data;
cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
cpuclk->hw.init = &init;
cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
if (!cpuclk->alt_parent) {
pr_err("%s: could not lookup alternate parent: (%d)\n",
__func__, reg_data->mux_core_alt);
ret = -EINVAL;
goto free_cpuclk;
}
ret = clk_prepare_enable(cpuclk->alt_parent);
if (ret) {
pr_err("%s: could not enable alternate parent\n",
__func__);
goto free_cpuclk;
}
clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
if (!clk) {
pr_err("%s: could not lookup parent clock: (%d) %s\n",
__func__, reg_data->mux_core_main,
parent_names[reg_data->mux_core_main]);
ret = -EINVAL;
goto free_alt_parent;
}
ret = clk_notifier_register(clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
goto free_alt_parent;
}
if (nrates > 0) {
cpuclk->rate_count = nrates;
cpuclk->rate_table = kmemdup(rates,
sizeof(*rates) * nrates,
GFP_KERNEL);
if (!cpuclk->rate_table) {
ret = -ENOMEM;
goto unregister_notifier;
}
}
cclk = clk_register(NULL, &cpuclk->hw);
if (IS_ERR(cclk)) {
pr_err("%s: could not register cpuclk %s\n", __func__, name);
ret = PTR_ERR(cclk);
goto free_rate_table;
}
return cclk;
free_rate_table:
kfree(cpuclk->rate_table);
unregister_notifier:
clk_notifier_unregister(clk, &cpuclk->clk_nb);
free_alt_parent:
clk_disable_unprepare(cpuclk->alt_parent);
free_cpuclk:
kfree(cpuclk);
return ERR_PTR(ret);
}
| linux-master | drivers/clk/rockchip/clk-cpu.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Shawn Lin <[email protected]>
* Andy Yan <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rv1108-cru.h>
#include "clk.h"
#define RV1108_GRF_SOC_STATUS0 0x480
enum rv1108_plls {
apll, dpll, gpll,
};
static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define RV1108_DIV_CORE_MASK 0xf
#define RV1108_DIV_CORE_SHIFT 4
#define RV1108_CLKSEL0(_core_peri_div) \
{ \
.reg = RV1108_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
RV1108_DIV_CORE_SHIFT) \
}
#define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \
{ \
.prate = _prate, \
.divs = { \
RV1108_CLKSEL0(_core_peri_div), \
}, \
}
static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
RV1108_CPUCLK_RATE(1608000000, 7),
RV1108_CPUCLK_RATE(1512000000, 7),
RV1108_CPUCLK_RATE(1488000000, 5),
RV1108_CPUCLK_RATE(1416000000, 5),
RV1108_CPUCLK_RATE(1392000000, 5),
RV1108_CPUCLK_RATE(1296000000, 5),
RV1108_CPUCLK_RATE(1200000000, 5),
RV1108_CPUCLK_RATE(1104000000, 5),
RV1108_CPUCLK_RATE(1008000000, 5),
RV1108_CPUCLK_RATE(912000000, 5),
RV1108_CPUCLK_RATE(816000000, 3),
RV1108_CPUCLK_RATE(696000000, 3),
RV1108_CPUCLK_RATE(600000000, 3),
RV1108_CPUCLK_RATE(500000000, 3),
RV1108_CPUCLK_RATE(408000000, 1),
RV1108_CPUCLK_RATE(312000000, 1),
RV1108_CPUCLK_RATE(216000000, 1),
RV1108_CPUCLK_RATE(96000000, 1),
};
static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
.core_reg[0] = RV1108_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 8,
.mux_core_mask = 0x3,
};
PNAME(mux_pll_p) = { "xin24m", "xin24m"};
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" };
PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" };
PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" };
PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" };
PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" };
PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" };
PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" };
PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" };
PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" };
PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" };
PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" };
PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
RV1108_PLL_CON(11), 8, 1, 0, NULL),
[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata =
MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata =
MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
RV1108_MISC_CON, 13, 1, MFLAGS),
MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
RV1108_MISC_CON, 15, 1, MFLAGS),
/*
* Clock-Architecture Diagram 2
*/
/* PD_CORE */
GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RV1108_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RV1108_CLKGATE_CON(0), 4, GFLAGS),
GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(11), 0, GFLAGS),
GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(11), 1, GFLAGS),
/* PD_RKVENC */
COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 8, GFLAGS),
FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4,
RV1108_CLKGATE_CON(8), 10, GFLAGS),
COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 9, GFLAGS),
GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
RV1108_CLKGATE_CON(19), 8, GFLAGS),
GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
RV1108_CLKGATE_CON(19), 9, GFLAGS),
GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(19), 11, GFLAGS),
GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(19), 10, GFLAGS),
/* PD_RKVDEC */
COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 2, GFLAGS),
FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4,
RV1108_CLKGATE_CON(8), 10, GFLAGS),
COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 1, GFLAGS),
COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 3, GFLAGS),
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
RV1108_CLKGATE_CON(19), 0, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
RV1108_CLKGATE_CON(19), 1, GFLAGS),
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
RV1108_CLKGATE_CON(19), 2, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
RV1108_CLKGATE_CON(19), 3, GFLAGS),
GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(19), 4, GFLAGS),
GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(19), 5, GFLAGS),
GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(19), 6, GFLAGS),
/* PD_PMU_wrapper */
COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(8), 12, GFLAGS),
GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(10), 0, GFLAGS),
GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(10), 1, GFLAGS),
GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
RV1108_CLKGATE_CON(10), 2, GFLAGS),
GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(10), 3, GFLAGS),
GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(10), 4, GFLAGS),
GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
RV1108_CLKGATE_CON(10), 5, GFLAGS),
GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
RV1108_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(8), 15, GFLAGS),
COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(8), 14, GFLAGS),
GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(8), 13, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
RV1108_CLKGATE_CON(9), 8, GFLAGS),
COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
RV1108_CLKGATE_CON(9), 11, GFLAGS),
COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 12, GFLAGS),
GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 6, GFLAGS),
GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 14, GFLAGS),
GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(18), 10, GFLAGS),
GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 10, GFLAGS),
COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,
RV1108_CLKGATE_CON(7), 9, GFLAGS),
GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(17), 6, GFLAGS),
GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(17), 7, GFLAGS),
COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0,
RV1108_CLKSEL_CON(31), 2, 2, MFLAGS,
RV1108_CLKGATE_CON(7), 10, GFLAGS),
GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(17), 8, GFLAGS),
GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(17), 9, GFLAGS),
COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0,
RV1108_CLKSEL_CON(31), 4, 2, MFLAGS,
RV1108_CLKGATE_CON(7), 11, GFLAGS),
GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(17), 10, GFLAGS),
GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(17), 11, GFLAGS),
COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0,
RV1108_CLKSEL_CON(31), 6, 2, MFLAGS,
RV1108_CLKGATE_CON(7), 12, GFLAGS),
GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(7), 8, GFLAGS),
/* PD_DSP_wrapper */
COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 0, GFLAGS),
GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 0, GFLAGS),
GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 1, GFLAGS),
GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 2, GFLAGS),
GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 3, GFLAGS),
GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 13, GFLAGS),
COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0,
RV1108_CLKSEL_CON(44), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0,
RV1108_CLKSEL_CON(44), 8, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 2, GFLAGS),
COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0,
RV1108_CLKSEL_CON(45), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 3, GFLAGS),
COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0,
RV1108_CLKSEL_CON(45), 8, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 4, GFLAGS),
GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 4, GFLAGS),
GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 5, GFLAGS),
GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 6, GFLAGS),
GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 7, GFLAGS),
GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 14, GFLAGS),
COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0,
RV1108_CLKSEL_CON(43), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 5, GFLAGS),
COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0,
RV1108_CLKSEL_CON(43), 8, 5, DFLAGS,
RV1108_CLKGATE_CON(9), 6, GFLAGS),
GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 8, GFLAGS),
GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 9, GFLAGS),
GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 10, GFLAGS),
GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 11, GFLAGS),
GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 12, GFLAGS),
GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(16), 15, GFLAGS),
GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(11), 8, GFLAGS),
/*
* Clock-Architecture Diagram 4
*/
COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(6), 0, GFLAGS),
GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
RV1108_CLKGATE_CON(17), 0, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(7), 2, GFLAGS),
GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(17), 2, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
RV1108_CLKGATE_CON(7), 3, GFLAGS),
GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
RV1108_CLKGATE_CON(17), 3, GFLAGS),
COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(6), 1, GFLAGS),
GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(17), 1, GFLAGS),
INVERTER(0, "pclk_vip", "ext_vip",
RV1108_CLKSEL_CON(31), 8, IFLAGS),
GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(7), 6, GFLAGS),
GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(18), 10, GFLAGS),
GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(6), 5, GFLAGS),
GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0,
RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS),
COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0,
RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS),
MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(32), 7, 1, MFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
RV1108_CLKGATE_CON(18), 0, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 1, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
RV1108_CLKGATE_CON(18), 2, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 3, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(18), 4, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 5, GFLAGS),
COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0,
RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(6), 7, GFLAGS),
FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2),
GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
RV1108_CLKGATE_CON(6), 8, GFLAGS),
COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0,
RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS,
RV1108_CLKGATE_CON(6), 9, GFLAGS),
GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 8, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 9, GFLAGS),
GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
RV1108_CLKGATE_CON(18), 12, GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
RV1108_CLKGATE_CON(18), 11, GFLAGS),
COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(6), 3, GFLAGS),
GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(9), 10, GFLAGS),
GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 9, GFLAGS),
GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 11, GFLAGS),
GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 12, GFLAGS),
/*
* Clock-Architecture Diagram 5
*/
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(8), 0,
RV1108_CLKGATE_CON(2), 1, GFLAGS,
&rv1108_i2s0_fracmux),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
RV1108_CLKGATE_CON(2), 3, GFLAGS),
COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(2), 5, GFLAGS,
&rv1108_i2s1_fracmux),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(10), 0,
RV1108_CLKGATE_CON(2), 9, GFLAGS,
&rv1108_i2s2_fracmux),
GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 10, GFLAGS),
/* PD_BUS */
GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 0, GFLAGS),
GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 1, GFLAGS),
GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
RV1108_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
RV1108_CLKGATE_CON(1), 5, GFLAGS),
GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(1), 6, GFLAGS),
GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 7, GFLAGS),
GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 8, GFLAGS),
GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
RV1108_CLKGATE_CON(1), 9, GFLAGS),
GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(1), 10, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(13), 4, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 7, GFLAGS),
GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 8, GFLAGS),
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 9, GFLAGS),
GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 10, GFLAGS),
GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(3), 0, GFLAGS),
GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 5, GFLAGS),
COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(16), 0,
RV1108_CLKGATE_CON(3), 2, GFLAGS,
&rv1108_uart0_fracmux),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(17), 0,
RV1108_CLKGATE_CON(3), 4, GFLAGS,
&rv1108_uart1_fracmux),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(18), 0,
RV1108_CLKGATE_CON(3), 6, GFLAGS,
&rv1108_uart2_fracmux),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 10, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 11, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 12, GFLAGS),
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 7, GFLAGS),
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 8, GFLAGS),
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 9, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 0, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 1, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 2, GFLAGS),
COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
RV1108_CLKGATE_CON(3), 10, GFLAGS),
GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 3, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 7, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 8, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 9, GFLAGS),
GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 0, GFLAGS),
GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 12, GFLAGS),
GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 13, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 13, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
RV1108_CLKSEL_CON(21), 0, 10, DFLAGS,
RV1108_CLKGATE_CON(3), 11, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 14, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RV1108_CLKSEL_CON(22), 0, 10, DFLAGS,
RV1108_CLKGATE_CON(3), 12, GFLAGS),
GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
RV1108_CLKGATE_CON(12), 2, GFLAGS),
GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(12), 3, GFLAGS),
GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(12), 1, GFLAGS),
/* PD_DDR */
GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 8, GFLAGS),
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 9, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(10), 9, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(12), 4, GFLAGS),
GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(12), 5, GFLAGS),
GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(12), 6, GFLAGS),
GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(0), 11, GFLAGS),
GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 2, GFLAGS),
GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(14), 4, GFLAGS),
/*
* Clock-Architecture Diagram 6
*/
/* PD_PERI */
COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
RV1108_CLKGATE_CON(4), 5, GFLAGS),
GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(15), 13, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
RV1108_CLKGATE_CON(4), 4, GFLAGS),
GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(15), 12, GFLAGS),
GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(4), 1, GFLAGS),
GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
RV1108_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(15), 11, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
RV1108_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
RV1108_CLKSEL_CON(25), 10, 2, MFLAGS,
RV1108_CLKGATE_CON(5), 2, GFLAGS),
DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
RV1108_CLKSEL_CON(26), 0, 8, DFLAGS),
COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
RV1108_CLKSEL_CON(25), 12, 2, MFLAGS,
RV1108_CLKGATE_CON(5), 1, GFLAGS),
DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS,
RV1108_CLKGATE_CON(5), 3, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1108_CLKGATE_CON(5), 4, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
RV1108_CLKGATE_CON(4), 10, GFLAGS),
MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1),
};
static const char *const rv1108_critical_clocks[] __initconst = {
"aclk_core",
"aclk_bus",
"hclk_bus",
"pclk_bus",
"aclk_periph",
"hclk_periph",
"pclk_periph",
"nclk_ddrupctl",
"pclk_ddrmon",
"pclk_acodecphy",
"pclk_pmu",
};
static void __init rv1108_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rv1108_pll_clks,
ARRAY_SIZE(rv1108_pll_clks),
RV1108_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rv1108_clk_branches,
ARRAY_SIZE(rv1108_clk_branches));
rockchip_clk_protect_critical(rv1108_critical_clocks,
ARRAY_SIZE(rv1108_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rv1108_cpuclk_data, rv1108_cpuclk_rates,
ARRAY_SIZE(rv1108_cpuclk_rates));
rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
| linux-master | drivers/clk/rockchip/clk-rv1108.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include "clk.h"
#define RK3036_GRF_SOC_STATUS0 0x14c
enum rk3036_plls {
apll, dpll, gpll,
};
static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define RK3036_DIV_CPU_MASK 0x1f
#define RK3036_DIV_CPU_SHIFT 8
#define RK3036_DIV_PERI_MASK 0xf
#define RK3036_DIV_PERI_SHIFT 0
#define RK3036_DIV_ACLK_MASK 0x7
#define RK3036_DIV_ACLK_SHIFT 4
#define RK3036_DIV_HCLK_MASK 0x3
#define RK3036_DIV_HCLK_SHIFT 8
#define RK3036_DIV_PCLK_MASK 0x7
#define RK3036_DIV_PCLK_SHIFT 12
#define RK3036_CLKSEL1(_core_periph_div) \
{ \
.reg = RK2928_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
RK3036_DIV_PERI_SHIFT) \
}
#define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \
{ \
.prate = _prate, \
.divs = { \
RK3036_CLKSEL1(_core_periph_div), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
RK3036_CPUCLK_RATE(816000000, 4),
RK3036_CPUCLK_RATE(600000000, 4),
RK3036_CPUCLK_RATE(312000000, 4),
};
static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
.core_reg[0] = RK2928_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 7,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "xin24m", "xin24m" };
PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" };
PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
RK2928_MODE_CON, 4, 4, 0, NULL),
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata =
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata =
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/*
* Clock-Architecture Diagram 2
*/
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
RK2928_CLKGATE_CON(2), 1, GFLAGS),
DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
RK2928_CLKGATE_CON(2), 3, GFLAGS),
DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
RK2928_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
RK2928_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
RK2928_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&rk3036_uart0_fracmux),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&rk3036_uart1_fracmux),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3036_uart2_fracmux),
COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
RK2928_CLKGATE_CON(2), 13, GFLAGS),
DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 14, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0),
COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3036_i2s_fracmux),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
RK2928_CLKGATE_CON(0), 13, GFLAGS),
GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3036_spdif_fracmux),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 13, GFLAGS),
COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 4, GFLAGS),
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2),
MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
/*
* Clock-Architecture Diagram 3
*/
/* aclk_cpu gates */
GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
/* pclk_cpu gates */
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
/* aclk_vio gates */
GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
/* xin24m gates */
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
/* aclk_peri gates */
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
/* hclk_peri gates */
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
};
static const char *const rk3036_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
"hclk_peri",
"pclk_peri",
"pclk_ddrupctl",
};
static void __init rk3036_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
struct clk *clk;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
/*
* Make uart_pll_clk a child of the gpll, as all other sources are
* not that usable / stable.
*/
writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
reg_base + RK2928_CLKSEL_CON(13));
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
if (IS_ERR(clk))
pr_warn("%s: could not register clock usb480m: %ld\n",
__func__, PTR_ERR(clk));
rockchip_clk_register_plls(ctx, rk3036_pll_clks,
ARRAY_SIZE(rk3036_pll_clks),
RK3036_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3036_clk_branches,
ARRAY_SIZE(rk3036_clk_branches));
rockchip_clk_protect_critical(rk3036_critical_clocks,
ARRAY_SIZE(rk3036_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3036_cpuclk_data, rk3036_cpuclk_rates,
ARRAY_SIZE(rk3036_cpuclk_rates));
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3036.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2014 Google, Inc
* Author: Alexandru M Stan <[email protected]>
*/
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "clk.h"
struct rockchip_mmc_clock {
struct clk_hw hw;
void __iomem *reg;
int id;
int shift;
int cached_phase;
struct notifier_block clk_rate_change_nb;
};
#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
#define RK3288_MMC_CLKGEN_DIV 2
static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
return parent_rate / RK3288_MMC_CLKGEN_DIV;
}
#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
#define ROCKCHIP_MMC_DEGREE_MASK 0x3
#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
#define PSECS_PER_SEC 1000000000000LL
/*
* Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
* simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
*/
#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
static int rockchip_mmc_get_phase(struct clk_hw *hw)
{
struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
unsigned long rate = clk_hw_get_rate(hw);
u32 raw_value;
u16 degrees;
u32 delay_num = 0;
/* Constant signal, no measurable phase shift */
if (!rate)
return 0;
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
/* degrees/delaynum * 1000000 */
unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
36 * (rate / 10000);
delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);
}
return degrees % 360;
}
static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
{
struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
unsigned long rate = clk_hw_get_rate(hw);
u8 nineties, remainder;
u8 delay_num;
u32 raw_value;
u32 delay;
/*
* The below calculation is based on the output clock from
* MMC host to the card, which expects the phase clock inherits
* the clock rate from its parent, namely the output clock
* provider of MMC host. However, things may go wrong if
* (1) It is orphan.
* (2) It is assigned to the wrong parent.
*
* This check help debug the case (1), which seems to be the
* most likely problem we often face and which makes it difficult
* for people to debug unstable mmc tuning results.
*/
if (!rate) {
pr_err("%s: invalid clk rate\n", __func__);
return -EINVAL;
}
nineties = degrees / 90;
remainder = (degrees % 90);
/*
* Due to the inexact nature of the "fine" delay, we might
* actually go non-monotonic. We don't go _too_ monotonic
* though, so we should be OK. Here are options of how we may
* work:
*
* Ideally we end up with:
* 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
*
* On one extreme (if delay is actually 44ps):
* .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
* The other (if delay is actually 77ps):
* 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
*
* It's possible we might make a delay that is up to 25
* degrees off from what we think we're making. That's OK
* though because we should be REALLY far from any bad range.
*/
/*
* Convert to delay; do a little extra work to make sure we
* don't overflow 32-bit / 64-bit numbers.
*/
delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
delay *= remainder;
delay = DIV_ROUND_CLOSEST(delay,
(rate / 1000) * 36 *
(ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
delay_num = (u8) min_t(u32, delay, 255);
raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
raw_value |= nineties;
writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
mmc_clock->reg);
pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
clk_hw_get_name(hw), degrees, delay_num,
mmc_clock->reg, raw_value>>(mmc_clock->shift),
rockchip_mmc_get_phase(hw)
);
return 0;
}
static const struct clk_ops rockchip_mmc_clk_ops = {
.recalc_rate = rockchip_mmc_recalc,
.get_phase = rockchip_mmc_get_phase,
.set_phase = rockchip_mmc_set_phase,
};
#define to_rockchip_mmc_clock(x) \
container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb)
static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,
unsigned long event, void *data)
{
struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb);
struct clk_notifier_data *ndata = data;
/*
* rockchip_mmc_clk is mostly used by mmc controllers to sample
* the intput data, which expects the fixed phase after the tuning
* process. However if the clock rate is changed, the phase is stale
* and may break the data sampling. So here we try to restore the phase
* for that case, except that
* (1) cached_phase is invaild since we inevitably cached it when the
* clock provider be reparented from orphan to its real parent in the
* first place. Otherwise we may mess up the initialization of MMC cards
* since we only set the default sample phase and drive phase later on.
* (2) the new coming rate is higher than the older one since mmc driver
* set the max-frequency to match the boards' ability but we can't go
* over the heads of that, otherwise the tests smoke out the issue.
*/
if (ndata->old_rate <= ndata->new_rate)
return NOTIFY_DONE;
if (event == PRE_RATE_CHANGE)
mmc_clock->cached_phase =
rockchip_mmc_get_phase(&mmc_clock->hw);
else if (mmc_clock->cached_phase != -EINVAL &&
event == POST_RATE_CHANGE)
rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);
return NOTIFY_DONE;
}
struct clk *rockchip_clk_register_mmc(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *reg, int shift)
{
struct clk_init_data init;
struct rockchip_mmc_clock *mmc_clock;
struct clk *clk;
int ret;
mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
if (!mmc_clock)
return ERR_PTR(-ENOMEM);
init.name = name;
init.flags = 0;
init.num_parents = num_parents;
init.parent_names = parent_names;
init.ops = &rockchip_mmc_clk_ops;
mmc_clock->hw.init = &init;
mmc_clock->reg = reg;
mmc_clock->shift = shift;
clk = clk_register(NULL, &mmc_clock->hw);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto err_register;
}
mmc_clock->clk_rate_change_nb.notifier_call =
&rockchip_mmc_clk_rate_notify;
ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);
if (ret)
goto err_notifier;
return clk;
err_notifier:
clk_unregister(clk);
err_register:
kfree(mmc_clock);
return ERR_PTR(ret);
}
| linux-master | drivers/clk/rockchip/clk-mmc-phase.c |
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